ath.c revision 1.126
1 /* $NetBSD: ath.c,v 1.126 2019/05/23 13:10:51 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.126 2019/05/23 13:10:51 msaitoh Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #ifdef _KERNEL_OPT 55 #include "opt_inet.h" 56 #endif 57 58 #include <sys/param.h> 59 #include <sys/reboot.h> 60 #include <sys/systm.h> 61 #include <sys/types.h> 62 #include <sys/sysctl.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/errno.h> 69 #include <sys/callout.h> 70 #include <sys/bus.h> 71 #include <sys/endian.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_arp.h> 78 #include <net/if_ether.h> 79 #include <net/if_llc.h> 80 81 #include <net80211/ieee80211_netbsd.h> 82 #include <net80211/ieee80211_var.h> 83 84 #include <net/bpf.h> 85 86 #ifdef INET 87 #include <netinet/in.h> 88 #endif 89 90 #include <sys/device.h> 91 #include <dev/ic/ath_netbsd.h> 92 93 #define AR_DEBUG 94 #include <dev/ic/athvar.h> 95 #include "ah_desc.h" 96 #include "ah_devid.h" /* XXX for softled */ 97 #include "opt_ah.h" 98 99 #ifdef ATH_TX99_DIAG 100 #include <dev/ath/ath_tx99/ath_tx99.h> 101 #endif 102 103 /* unaligned little endian access */ 104 #define LE_READ_2(p) \ 105 ((u_int16_t) \ 106 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 107 #define LE_READ_4(p) \ 108 ((u_int32_t) \ 109 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 110 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 111 112 enum { 113 ATH_LED_TX, 114 ATH_LED_RX, 115 ATH_LED_POLL, 116 }; 117 118 #ifdef AH_NEED_DESC_SWAP 119 #define HTOAH32(x) htole32(x) 120 #else 121 #define HTOAH32(x) (x) 122 #endif 123 124 static int ath_ifinit(struct ifnet *); 125 static int ath_init(struct ath_softc *); 126 static void ath_stop_locked(struct ifnet *, int); 127 static void ath_stop(struct ifnet *, int); 128 static void ath_start(struct ifnet *); 129 static int ath_media_change(struct ifnet *); 130 static void ath_watchdog(struct ifnet *); 131 static int ath_ioctl(struct ifnet *, u_long, void *); 132 static void ath_fatal_proc(void *, int); 133 static void ath_rxorn_proc(void *, int); 134 static void ath_bmiss_proc(void *, int); 135 static void ath_radar_proc(void *, int); 136 static int ath_key_alloc(struct ieee80211com *, 137 const struct ieee80211_key *, 138 ieee80211_keyix *, ieee80211_keyix *); 139 static int ath_key_delete(struct ieee80211com *, 140 const struct ieee80211_key *); 141 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 142 const u_int8_t mac[IEEE80211_ADDR_LEN]); 143 static void ath_key_update_begin(struct ieee80211com *); 144 static void ath_key_update_end(struct ieee80211com *); 145 static void ath_mode_init(struct ath_softc *); 146 static void ath_setslottime(struct ath_softc *); 147 static void ath_updateslot(struct ifnet *); 148 static int ath_beaconq_setup(struct ath_hal *); 149 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 150 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 151 static void ath_beacon_proc(void *, int); 152 static void ath_bstuck_proc(void *, int); 153 static void ath_beacon_free(struct ath_softc *); 154 static void ath_beacon_config(struct ath_softc *); 155 static void ath_descdma_cleanup(struct ath_softc *sc, 156 struct ath_descdma *, ath_bufhead *); 157 static int ath_desc_alloc(struct ath_softc *); 158 static void ath_desc_free(struct ath_softc *); 159 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 160 static void ath_node_free(struct ieee80211_node *); 161 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 162 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 163 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 164 struct ieee80211_node *ni, 165 int subtype, int rssi, u_int32_t rstamp); 166 static void ath_setdefantenna(struct ath_softc *, u_int); 167 static void ath_rx_proc(void *, int); 168 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 169 static int ath_tx_setup(struct ath_softc *, int, int); 170 static int ath_wme_update(struct ieee80211com *); 171 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 172 static void ath_tx_cleanup(struct ath_softc *); 173 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 174 struct ath_buf *, struct mbuf *); 175 static void ath_tx_proc_q0(void *, int); 176 static void ath_tx_proc_q0123(void *, int); 177 static void ath_tx_proc(void *, int); 178 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 179 static void ath_draintxq(struct ath_softc *); 180 static void ath_stoprecv(struct ath_softc *); 181 static int ath_startrecv(struct ath_softc *); 182 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_next_scan(void *); 184 static void ath_calibrate(void *); 185 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 186 static void ath_setup_stationkey(struct ieee80211_node *); 187 static void ath_newassoc(struct ieee80211_node *, int); 188 static int ath_getchannels(struct ath_softc *, u_int cc, 189 HAL_BOOL outdoor, HAL_BOOL xchanmode); 190 static void ath_led_event(struct ath_softc *, int); 191 static void ath_update_txpow(struct ath_softc *); 192 static void ath_freetx(struct mbuf *); 193 static void ath_restore_diversity(struct ath_softc *); 194 195 static int ath_rate_setup(struct ath_softc *, u_int mode); 196 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 197 198 static void ath_bpfattach(struct ath_softc *); 199 static void ath_announce(struct ath_softc *); 200 201 #ifdef __NetBSD__ 202 #define ATH_TASK_FUNC(__func) \ 203 static void __CONCAT(__func, _si)(void *arg) \ 204 { \ 205 __func(arg, 1); \ 206 } 207 ATH_TASK_FUNC(ath_rx_proc); 208 ATH_TASK_FUNC(ath_rxorn_proc); 209 ATH_TASK_FUNC(ath_fatal_proc); 210 ATH_TASK_FUNC(ath_bmiss_proc); 211 ATH_TASK_FUNC(ath_bstuck_proc); 212 ATH_TASK_FUNC(ath_radar_proc); 213 ATH_TASK_FUNC(ath_tx_proc_q0); 214 ATH_TASK_FUNC(ath_tx_proc_q0123); 215 ATH_TASK_FUNC(ath_tx_proc); 216 #endif 217 218 int ath_dwelltime = 200; /* 5 channels/second */ 219 int ath_calinterval = 30; /* calibrate every 30 secs */ 220 int ath_outdoor = AH_TRUE; /* outdoor operation */ 221 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 222 int ath_countrycode = CTRY_DEFAULT; /* country code */ 223 int ath_regdomain = 0; /* regulatory domain */ 224 int ath_debug = 0; 225 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 226 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 227 228 #ifdef AR_DEBUG 229 enum { 230 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 231 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 232 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 233 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 234 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 235 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 236 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 237 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 238 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 239 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 240 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 241 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 242 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 243 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 244 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 245 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 246 ATH_DEBUG_NODE = 0x00080000, /* node management */ 247 ATH_DEBUG_LED = 0x00100000, /* led management */ 248 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 249 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 250 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 251 ATH_DEBUG_ANY = 0xffffffff 252 }; 253 #define IFF_DUMPPKTS(sc, m) \ 254 ((sc->sc_debug & (m)) || \ 255 (sc->sc_if.if_flags & (IFF_DEBUG | IFF_LINK2)) \ 256 == (IFF_DEBUG | IFF_LINK2)) 257 #define DPRINTF(sc, m, fmt, ...) do { \ 258 if (sc->sc_debug & (m)) \ 259 printf(fmt, __VA_ARGS__); \ 260 } while (0) 261 #define KEYPRINTF(sc, ix, hk, mac) do { \ 262 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 263 ath_keyprint(__func__, ix, hk, mac); \ 264 } while (0) 265 static void ath_printrxbuf(struct ath_buf *bf, int); 266 static void ath_printtxbuf(struct ath_buf *bf, int); 267 #else 268 #define IFF_DUMPPKTS(sc, m) \ 269 ((sc->sc_if.if_flags & (IFF_DEBUG | IFF_LINK2)) \ 270 == (IFF_DEBUG | IFF_LINK2)) 271 #define DPRINTF(m, fmt, ...) 272 #define KEYPRINTF(sc, k, ix, mac) 273 #endif 274 275 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 276 277 int 278 ath_attach(u_int16_t devid, struct ath_softc *sc) 279 { 280 struct ifnet *ifp = &sc->sc_if; 281 struct ieee80211com *ic = &sc->sc_ic; 282 struct ath_hal *ah = NULL; 283 HAL_STATUS status; 284 int error = 0, i; 285 286 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 287 288 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 289 290 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 291 292 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 293 if (ah == NULL) { 294 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 295 status); 296 error = ENXIO; 297 goto bad; 298 } 299 if (ah->ah_abi != HAL_ABI_VERSION) { 300 if_printf(ifp, "HAL ABI mismatch detected " 301 "(HAL:0x%x != driver:0x%x)\n", 302 ah->ah_abi, HAL_ABI_VERSION); 303 error = ENXIO; 304 goto bad; 305 } 306 sc->sc_ah = ah; 307 308 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 309 "pmf-powerdown", false)) 310 goto bad; 311 312 /* 313 * Check if the MAC has multi-rate retry support. 314 * We do this by trying to setup a fake extended 315 * descriptor. MAC's that don't have support will 316 * return false w/o doing anything. MAC's that do 317 * support it will return true w/o doing anything. 318 */ 319 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 320 321 /* 322 * Check if the device has hardware counters for PHY 323 * errors. If so we need to enable the MIB interrupt 324 * so we can act on stat triggers. 325 */ 326 if (ath_hal_hwphycounters(ah)) 327 sc->sc_needmib = 1; 328 329 /* 330 * Get the hardware key cache size. 331 */ 332 sc->sc_keymax = ath_hal_keycachesize(ah); 333 if (sc->sc_keymax > ATH_KEYMAX) { 334 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 335 ATH_KEYMAX, sc->sc_keymax); 336 sc->sc_keymax = ATH_KEYMAX; 337 } 338 /* 339 * Reset the key cache since some parts do not 340 * reset the contents on initial power up. 341 */ 342 for (i = 0; i < sc->sc_keymax; i++) 343 ath_hal_keyreset(ah, i); 344 /* 345 * Mark key cache slots associated with global keys 346 * as in use. If we knew TKIP was not to be used we 347 * could leave the +32, +64, and +32+64 slots free. 348 * XXX only for splitmic. 349 */ 350 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 351 setbit(sc->sc_keymap, i); 352 setbit(sc->sc_keymap, i+32); 353 setbit(sc->sc_keymap, i+64); 354 setbit(sc->sc_keymap, i+32+64); 355 } 356 357 /* 358 * Collect the channel list using the default country 359 * code and including outdoor channels. The 802.11 layer 360 * is resposible for filtering this list based on settings 361 * like the phy mode. 362 */ 363 error = ath_getchannels(sc, ath_countrycode, 364 ath_outdoor, ath_xchanmode); 365 if (error != 0) 366 goto bad; 367 368 /* 369 * Setup rate tables for all potential media types. 370 */ 371 ath_rate_setup(sc, IEEE80211_MODE_11A); 372 ath_rate_setup(sc, IEEE80211_MODE_11B); 373 ath_rate_setup(sc, IEEE80211_MODE_11G); 374 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 375 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 376 /* NB: setup here so ath_rate_update is happy */ 377 ath_setcurmode(sc, IEEE80211_MODE_11A); 378 379 /* 380 * Allocate tx+rx descriptors and populate the lists. 381 */ 382 error = ath_desc_alloc(sc); 383 if (error != 0) { 384 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 385 goto bad; 386 } 387 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 388 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 389 #if 0 390 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 391 #endif 392 393 ATH_TXBUF_LOCK_INIT(sc); 394 395 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 396 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 397 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 398 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 399 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 400 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 401 402 /* 403 * Allocate hardware transmit queues: one queue for 404 * beacon frames and one data queue for each QoS 405 * priority. Note that the hal handles reseting 406 * these queues at the needed time. 407 * 408 * XXX PS-Poll 409 */ 410 sc->sc_bhalq = ath_beaconq_setup(ah); 411 if (sc->sc_bhalq == (u_int) -1) { 412 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 413 error = EIO; 414 goto bad2; 415 } 416 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 417 if (sc->sc_cabq == NULL) { 418 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 419 error = EIO; 420 goto bad2; 421 } 422 /* NB: insure BK queue is the lowest priority h/w queue */ 423 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 424 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 425 ieee80211_wme_acnames[WME_AC_BK]); 426 error = EIO; 427 goto bad2; 428 } 429 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 430 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 431 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 432 /* 433 * Not enough hardware tx queues to properly do WME; 434 * just punt and assign them all to the same h/w queue. 435 * We could do a better job of this if, for example, 436 * we allocate queues when we switch from station to 437 * AP mode. 438 */ 439 if (sc->sc_ac2q[WME_AC_VI] != NULL) 440 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 441 if (sc->sc_ac2q[WME_AC_BE] != NULL) 442 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 443 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 444 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 445 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 446 } 447 448 /* 449 * Special case certain configurations. Note the 450 * CAB queue is handled by these specially so don't 451 * include them when checking the txq setup mask. 452 */ 453 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 454 case 0x01: 455 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 456 break; 457 case 0x0f: 458 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 459 break; 460 default: 461 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 462 break; 463 } 464 465 /* 466 * Setup rate control. Some rate control modules 467 * call back to change the anntena state so expose 468 * the necessary entry points. 469 * XXX maybe belongs in struct ath_ratectrl? 470 */ 471 sc->sc_setdefantenna = ath_setdefantenna; 472 sc->sc_rc = ath_rate_attach(sc); 473 if (sc->sc_rc == NULL) { 474 error = EIO; 475 goto bad2; 476 } 477 478 sc->sc_blinking = 0; 479 sc->sc_ledstate = 1; 480 sc->sc_ledon = 0; /* low true */ 481 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 482 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 483 /* 484 * Auto-enable soft led processing for IBM cards and for 485 * 5211 minipci cards. Users can also manually enable/disable 486 * support with a sysctl. 487 */ 488 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 489 if (sc->sc_softled) { 490 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 491 HAL_GPIO_MUX_MAC_NETWORK_LED); 492 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 493 } 494 495 ifp->if_softc = sc; 496 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 497 ifp->if_start = ath_start; 498 ifp->if_stop = ath_stop; 499 ifp->if_watchdog = ath_watchdog; 500 ifp->if_ioctl = ath_ioctl; 501 ifp->if_init = ath_ifinit; 502 IFQ_SET_READY(&ifp->if_snd); 503 504 ic->ic_ifp = ifp; 505 ic->ic_reset = ath_reset; 506 ic->ic_newassoc = ath_newassoc; 507 ic->ic_updateslot = ath_updateslot; 508 ic->ic_wme.wme_update = ath_wme_update; 509 /* XXX not right but it's not used anywhere important */ 510 ic->ic_phytype = IEEE80211_T_OFDM; 511 ic->ic_opmode = IEEE80211_M_STA; 512 ic->ic_caps = 513 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 514 | IEEE80211_C_HOSTAP /* hostap mode */ 515 | IEEE80211_C_MONITOR /* monitor mode */ 516 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 517 | IEEE80211_C_SHSLOT /* short slot time supported */ 518 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 519 | IEEE80211_C_TXFRAG /* handle tx frags */ 520 ; 521 /* 522 * Query the hal to figure out h/w crypto support. 523 */ 524 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 525 ic->ic_caps |= IEEE80211_C_WEP; 526 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 527 ic->ic_caps |= IEEE80211_C_AES; 528 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 529 ic->ic_caps |= IEEE80211_C_AES_CCM; 530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 531 ic->ic_caps |= IEEE80211_C_CKIP; 532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 533 ic->ic_caps |= IEEE80211_C_TKIP; 534 /* 535 * Check if h/w does the MIC and/or whether the 536 * separate key cache entries are required to 537 * handle both tx+rx MIC keys. 538 */ 539 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 540 ic->ic_caps |= IEEE80211_C_TKIPMIC; 541 542 /* 543 * If the h/w supports storing tx+rx MIC keys 544 * in one cache slot automatically enable use. 545 */ 546 if (ath_hal_hastkipsplit(ah) || 547 !ath_hal_settkipsplit(ah, AH_FALSE)) 548 sc->sc_splitmic = 1; 549 550 /* 551 * If the h/w can do TKIP MIC together with WME then 552 * we use it; otherwise we force the MIC to be done 553 * in software by the net80211 layer. 554 */ 555 if (ath_hal_haswmetkipmic(ah)) 556 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 557 } 558 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 559 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 560 /* 561 * Mark key cache slots associated with global keys 562 * as in use. If we knew TKIP was not to be used we 563 * could leave the +32, +64, and +32+64 slots free. 564 */ 565 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 566 setbit(sc->sc_keymap, i); 567 setbit(sc->sc_keymap, i+64); 568 if (sc->sc_splitmic) { 569 setbit(sc->sc_keymap, i+32); 570 setbit(sc->sc_keymap, i+32+64); 571 } 572 } 573 /* 574 * TPC support can be done either with a global cap or 575 * per-packet support. The latter is not available on 576 * all parts. We're a bit pedantic here as all parts 577 * support a global cap. 578 */ 579 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 580 ic->ic_caps |= IEEE80211_C_TXPMGT; 581 582 /* 583 * Mark WME capability only if we have sufficient 584 * hardware queues to do proper priority scheduling. 585 */ 586 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 587 ic->ic_caps |= IEEE80211_C_WME; 588 /* 589 * Check for misc other capabilities. 590 */ 591 if (ath_hal_hasbursting(ah)) 592 ic->ic_caps |= IEEE80211_C_BURST; 593 594 /* 595 * Indicate we need the 802.11 header padded to a 596 * 32-bit boundary for 4-address and QoS frames. 597 */ 598 ic->ic_flags |= IEEE80211_F_DATAPAD; 599 600 /* 601 * Query the hal about antenna support. 602 */ 603 sc->sc_defant = ath_hal_getdefantenna(ah); 604 605 /* 606 * Not all chips have the VEOL support we want to 607 * use with IBSS beacons; check here for it. 608 */ 609 sc->sc_hasveol = ath_hal_hasveol(ah); 610 611 /* get mac address from hardware */ 612 ath_hal_getmac(ah, ic->ic_myaddr); 613 614 if_attach(ifp); 615 /* call MI attach routine. */ 616 ieee80211_ifattach(ic); 617 /* override default methods */ 618 ic->ic_node_alloc = ath_node_alloc; 619 sc->sc_node_free = ic->ic_node_free; 620 ic->ic_node_free = ath_node_free; 621 ic->ic_node_getrssi = ath_node_getrssi; 622 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 623 ic->ic_recv_mgmt = ath_recv_mgmt; 624 sc->sc_newstate = ic->ic_newstate; 625 ic->ic_newstate = ath_newstate; 626 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 627 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 628 ic->ic_crypto.cs_key_delete = ath_key_delete; 629 ic->ic_crypto.cs_key_set = ath_key_set; 630 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 631 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 632 /* complete initialization */ 633 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 634 635 ath_bpfattach(sc); 636 637 sc->sc_flags |= ATH_ATTACHED; 638 639 /* 640 * Setup dynamic sysctl's now that country code and 641 * regdomain are available from the hal. 642 */ 643 ath_sysctlattach(sc); 644 645 ieee80211_announce(ic); 646 ath_announce(sc); 647 return 0; 648 bad2: 649 ath_tx_cleanup(sc); 650 ath_desc_free(sc); 651 bad: 652 if (ah) 653 ath_hal_detach(ah); 654 /* XXX don't get under the abstraction like this */ 655 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 656 return error; 657 } 658 659 int 660 ath_detach(struct ath_softc *sc) 661 { 662 struct ifnet *ifp = &sc->sc_if; 663 int s; 664 665 if ((sc->sc_flags & ATH_ATTACHED) == 0) 666 return (0); 667 668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 669 __func__, ifp->if_flags); 670 671 s = splnet(); 672 ath_stop(ifp, 1); 673 bpf_detach(ifp); 674 /* 675 * NB: the order of these is important: 676 * o call the 802.11 layer before detaching the hal to 677 * insure callbacks into the driver to delete global 678 * key cache entries can be handled 679 * o reclaim the tx queue data structures after calling 680 * the 802.11 layer as we'll get called back to reclaim 681 * node state and potentially want to use them 682 * o to cleanup the tx queues the hal is called, so detach 683 * it last 684 * Other than that, it's straightforward... 685 */ 686 ieee80211_ifdetach(&sc->sc_ic); 687 #ifdef ATH_TX99_DIAG 688 if (sc->sc_tx99 != NULL) 689 sc->sc_tx99->detach(sc->sc_tx99); 690 #endif 691 ath_rate_detach(sc->sc_rc); 692 ath_desc_free(sc); 693 ath_tx_cleanup(sc); 694 sysctl_teardown(&sc->sc_sysctllog); 695 ath_hal_detach(sc->sc_ah); 696 if_detach(ifp); 697 splx(s); 698 699 return 0; 700 } 701 702 void 703 ath_suspend(struct ath_softc *sc) 704 { 705 #if notyet 706 /* 707 * Set the chip in full sleep mode. Note that we are 708 * careful to do this only when bringing the interface 709 * completely to a stop. When the chip is in this state 710 * it must be carefully woken up or references to 711 * registers in the PCI clock domain may freeze the bus 712 * (and system). This varies by chip and is mostly an 713 * issue with newer parts that go to sleep more quickly. 714 */ 715 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 716 #endif 717 } 718 719 bool 720 ath_resume(struct ath_softc *sc) 721 { 722 struct ath_hal *ah = sc->sc_ah; 723 struct ieee80211com *ic = &sc->sc_ic; 724 HAL_STATUS status; 725 int i; 726 727 #if notyet 728 ath_hal_setpower(ah, HAL_PM_AWAKE); 729 #else 730 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 731 #endif 732 733 /* 734 * Reset the key cache since some parts do not 735 * reset the contents on initial power up. 736 */ 737 for (i = 0; i < sc->sc_keymax; i++) 738 ath_hal_keyreset(ah, i); 739 740 ath_hal_resettxqueue(ah, sc->sc_bhalq); 741 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 742 if (ATH_TXQ_SETUP(sc, i)) 743 ath_hal_resettxqueue(ah, i); 744 745 if (sc->sc_softled) { 746 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 747 HAL_GPIO_MUX_MAC_NETWORK_LED); 748 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 749 } 750 return true; 751 } 752 753 /* 754 * Interrupt handler. Most of the actual processing is deferred. 755 */ 756 int 757 ath_intr(void *arg) 758 { 759 struct ath_softc *sc = arg; 760 struct ifnet *ifp = &sc->sc_if; 761 struct ath_hal *ah = sc->sc_ah; 762 HAL_INT status = 0; 763 764 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 765 /* 766 * The hardware is not ready/present, don't touch anything. 767 * Note this can happen early on if the IRQ is shared. 768 */ 769 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 770 return 0; 771 } 772 773 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 774 return 0; 775 776 if ((ifp->if_flags & (IFF_RUNNING |IFF_UP)) != (IFF_RUNNING |IFF_UP)) { 777 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 778 __func__, ifp->if_flags); 779 ath_hal_getisr(ah, &status); /* clear ISR */ 780 ath_hal_intrset(ah, 0); /* disable further intr's */ 781 return 1; /* XXX */ 782 } 783 /* 784 * Figure out the reason(s) for the interrupt. Note 785 * that the hal returns a pseudo-ISR that may include 786 * bits we haven't explicitly enabled so we mask the 787 * value to insure we only process bits we requested. 788 */ 789 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 790 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 791 status &= sc->sc_imask; /* discard unasked for bits */ 792 if (status & HAL_INT_FATAL) { 793 /* 794 * Fatal errors are unrecoverable. Typically 795 * these are caused by DMA errors. Unfortunately 796 * the exact reason is not (presently) returned 797 * by the hal. 798 */ 799 sc->sc_stats.ast_hardware++; 800 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 801 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 802 } else if (status & HAL_INT_RXORN) { 803 sc->sc_stats.ast_rxorn++; 804 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 805 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 806 } else { 807 if (status & HAL_INT_SWBA) { 808 /* 809 * Software beacon alert--time to send a beacon. 810 * Handle beacon transmission directly; deferring 811 * this is too slow to meet timing constraints 812 * under load. 813 */ 814 ath_beacon_proc(sc, 0); 815 } 816 if (status & HAL_INT_RXEOL) { 817 /* 818 * NB: the hardware should re-read the link when 819 * RXE bit is written, but it doesn't work at 820 * least on older hardware revs. 821 */ 822 sc->sc_stats.ast_rxeol++; 823 sc->sc_rxlink = NULL; 824 } 825 if (status & HAL_INT_TXURN) { 826 sc->sc_stats.ast_txurn++; 827 /* bump tx trigger level */ 828 ath_hal_updatetxtriglevel(ah, AH_TRUE); 829 } 830 if (status & HAL_INT_RX) 831 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 832 if (status & HAL_INT_TX) 833 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 834 if (status & HAL_INT_BMISS) { 835 sc->sc_stats.ast_bmiss++; 836 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 837 } 838 if (status & HAL_INT_MIB) { 839 sc->sc_stats.ast_mib++; 840 /* 841 * Disable interrupts until we service the MIB 842 * interrupt; otherwise it will continue to fire. 843 */ 844 ath_hal_intrset(ah, 0); 845 /* 846 * Let the hal handle the event. We assume it will 847 * clear whatever condition caused the interrupt. 848 */ 849 ath_hal_mibevent(ah, &sc->sc_halstats); 850 ath_hal_intrset(ah, sc->sc_imask); 851 } 852 } 853 return 1; 854 } 855 856 /* Swap transmit descriptor. 857 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 858 * function. 859 */ 860 static inline void 861 ath_desc_swap(struct ath_desc *ds) 862 { 863 #ifdef AH_NEED_DESC_SWAP 864 ds->ds_link = htole32(ds->ds_link); 865 ds->ds_data = htole32(ds->ds_data); 866 ds->ds_ctl0 = htole32(ds->ds_ctl0); 867 ds->ds_ctl1 = htole32(ds->ds_ctl1); 868 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 869 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 870 #endif 871 } 872 873 static void 874 ath_fatal_proc(void *arg, int pending) 875 { 876 struct ath_softc *sc = arg; 877 struct ifnet *ifp = &sc->sc_if; 878 #ifdef __NetBSD__ 879 int s; 880 #endif 881 882 if_printf(ifp, "hardware error; resetting\n"); 883 #ifdef __NetBSD__ 884 s = splnet(); 885 #endif 886 ath_reset(ifp); 887 #ifdef __NetBSD__ 888 splx(s); 889 #endif 890 } 891 892 static void 893 ath_rxorn_proc(void *arg, int pending) 894 { 895 struct ath_softc *sc = arg; 896 struct ifnet *ifp = &sc->sc_if; 897 #ifdef __NetBSD__ 898 int s; 899 #endif 900 901 if_printf(ifp, "rx FIFO overrun; resetting\n"); 902 #ifdef __NetBSD__ 903 s = splnet(); 904 #endif 905 ath_reset(ifp); 906 #ifdef __NetBSD__ 907 splx(s); 908 #endif 909 } 910 911 static void 912 ath_bmiss_proc(void *arg, int pending) 913 { 914 struct ath_softc *sc = arg; 915 struct ieee80211com *ic = &sc->sc_ic; 916 NET_LOCK_GIANT_FUNC_INIT(); 917 918 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 919 KASSERTMSG(ic->ic_opmode == IEEE80211_M_STA, 920 "unexpect operating mode %u", ic->ic_opmode); 921 if (ic->ic_state == IEEE80211_S_RUN) { 922 u_int64_t lastrx = sc->sc_lastrx; 923 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 924 925 DPRINTF(sc, ATH_DEBUG_BEACON, 926 "%s: tsf %" PRIu64 " lastrx %" PRId64 927 " (%" PRIu64 ") bmiss %u\n", 928 __func__, tsf, tsf - lastrx, lastrx, 929 ic->ic_bmisstimeout*1024); 930 /* 931 * Workaround phantom bmiss interrupts by sanity-checking 932 * the time of our last rx'd frame. If it is within the 933 * beacon miss interval then ignore the interrupt. If it's 934 * truly a bmiss we'll get another interrupt soon and that'll 935 * be dispatched up for processing. 936 */ 937 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 938 NET_LOCK_GIANT(); 939 ieee80211_beacon_miss(ic); 940 NET_UNLOCK_GIANT(); 941 } else 942 sc->sc_stats.ast_bmiss_phantom++; 943 } 944 } 945 946 static void 947 ath_radar_proc(void *arg, int pending) 948 { 949 #if 0 950 struct ath_softc *sc = arg; 951 struct ifnet *ifp = &sc->sc_if; 952 struct ath_hal *ah = sc->sc_ah; 953 HAL_CHANNEL hchan; 954 955 if (ath_hal_procdfs(ah, &hchan)) { 956 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 957 hchan.channel, hchan.channelFlags, hchan.privFlags); 958 /* 959 * Initiate channel change. 960 */ 961 /* XXX not yet */ 962 } 963 #endif 964 } 965 966 static u_int 967 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 968 { 969 #define N(a) (sizeof(a) / sizeof(a[0])) 970 static const u_int modeflags[] = { 971 0, /* IEEE80211_MODE_AUTO */ 972 CHANNEL_A, /* IEEE80211_MODE_11A */ 973 CHANNEL_B, /* IEEE80211_MODE_11B */ 974 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 975 0, /* IEEE80211_MODE_FH */ 976 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 977 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 978 }; 979 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 980 981 KASSERTMSG(mode < N(modeflags), "unexpected phy mode %u", mode); 982 KASSERTMSG(modeflags[mode] != 0, "mode %u undefined", mode); 983 return modeflags[mode]; 984 #undef N 985 } 986 987 static int 988 ath_ifinit(struct ifnet *ifp) 989 { 990 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 991 992 return ath_init(sc); 993 } 994 995 static void 996 ath_settkipmic(struct ath_softc *sc) 997 { 998 struct ieee80211com *ic = &sc->sc_ic; 999 struct ath_hal *ah = sc->sc_ah; 1000 1001 if ((ic->ic_caps & IEEE80211_C_TKIP) && 1002 !(ic->ic_caps & IEEE80211_C_WME_TKIPMIC)) { 1003 if (ic->ic_flags & IEEE80211_F_WME) { 1004 (void)ath_hal_settkipmic(ah, AH_FALSE); 1005 ic->ic_caps &= ~IEEE80211_C_TKIPMIC; 1006 } else { 1007 (void)ath_hal_settkipmic(ah, AH_TRUE); 1008 ic->ic_caps |= IEEE80211_C_TKIPMIC; 1009 } 1010 } 1011 } 1012 1013 static int 1014 ath_init(struct ath_softc *sc) 1015 { 1016 struct ifnet *ifp = &sc->sc_if; 1017 struct ieee80211com *ic = &sc->sc_ic; 1018 struct ath_hal *ah = sc->sc_ah; 1019 HAL_STATUS status; 1020 int error = 0, s; 1021 1022 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1023 __func__, ifp->if_flags); 1024 1025 if (device_is_active(sc->sc_dev)) { 1026 s = splnet(); 1027 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1028 !device_is_active(sc->sc_dev)) 1029 return 0; 1030 else 1031 s = splnet(); 1032 1033 /* 1034 * Stop anything previously setup. This is safe 1035 * whether this is the first time through or not. 1036 */ 1037 ath_stop_locked(ifp, 0); 1038 1039 /* 1040 * The basic interface to setting the hardware in a good 1041 * state is ``reset''. On return the hardware is known to 1042 * be powered up and with interrupts disabled. This must 1043 * be followed by initialization of the appropriate bits 1044 * and then setup of the interrupt mask. 1045 */ 1046 ath_settkipmic(sc); 1047 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1048 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1049 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1050 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1051 status); 1052 error = EIO; 1053 goto done; 1054 } 1055 1056 /* 1057 * This is needed only to setup initial state 1058 * but it's best done after a reset. 1059 */ 1060 ath_update_txpow(sc); 1061 /* 1062 * Likewise this is set during reset so update 1063 * state cached in the driver. 1064 */ 1065 ath_restore_diversity(sc); 1066 sc->sc_calinterval = 1; 1067 sc->sc_caltries = 0; 1068 1069 /* 1070 * Setup the hardware after reset: the key cache 1071 * is filled as needed and the receive engine is 1072 * set going. Frame transmit is handled entirely 1073 * in the frame output path; there's nothing to do 1074 * here except setup the interrupt mask. 1075 */ 1076 if ((error = ath_startrecv(sc)) != 0) { 1077 if_printf(ifp, "unable to start recv logic\n"); 1078 goto done; 1079 } 1080 1081 /* 1082 * Enable interrupts. 1083 */ 1084 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1085 | HAL_INT_RXEOL | HAL_INT_RXORN 1086 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1087 /* 1088 * Enable MIB interrupts when there are hardware phy counters. 1089 * Note we only do this (at the moment) for station mode. 1090 */ 1091 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1092 sc->sc_imask |= HAL_INT_MIB; 1093 ath_hal_intrset(ah, sc->sc_imask); 1094 1095 ifp->if_flags |= IFF_RUNNING; 1096 ic->ic_state = IEEE80211_S_INIT; 1097 1098 /* 1099 * The hardware should be ready to go now so it's safe 1100 * to kick the 802.11 state machine as it's likely to 1101 * immediately call back to us to send mgmt frames. 1102 */ 1103 ath_chan_change(sc, ic->ic_curchan); 1104 #ifdef ATH_TX99_DIAG 1105 if (sc->sc_tx99 != NULL) 1106 sc->sc_tx99->start(sc->sc_tx99); 1107 else 1108 #endif 1109 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1110 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1111 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1112 } else 1113 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1114 done: 1115 splx(s); 1116 return error; 1117 } 1118 1119 static void 1120 ath_stop_locked(struct ifnet *ifp, int disable) 1121 { 1122 struct ath_softc *sc = ifp->if_softc; 1123 struct ieee80211com *ic = &sc->sc_ic; 1124 struct ath_hal *ah = sc->sc_ah; 1125 1126 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1127 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1128 1129 /* KASSERT() IPL_NET */ 1130 if (ifp->if_flags & IFF_RUNNING) { 1131 /* 1132 * Shutdown the hardware and driver: 1133 * reset 802.11 state machine 1134 * turn off timers 1135 * disable interrupts 1136 * turn off the radio 1137 * clear transmit machinery 1138 * clear receive machinery 1139 * drain and release tx queues 1140 * reclaim beacon resources 1141 * power down hardware 1142 * 1143 * Note that some of this work is not possible if the 1144 * hardware is gone (invalid). 1145 */ 1146 #ifdef ATH_TX99_DIAG 1147 if (sc->sc_tx99 != NULL) 1148 sc->sc_tx99->stop(sc->sc_tx99); 1149 #endif 1150 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1151 ifp->if_flags &= ~IFF_RUNNING; 1152 ifp->if_timer = 0; 1153 if (device_is_enabled(sc->sc_dev)) { 1154 if (sc->sc_softled) { 1155 callout_stop(&sc->sc_ledtimer); 1156 ath_hal_gpioset(ah, sc->sc_ledpin, 1157 !sc->sc_ledon); 1158 sc->sc_blinking = 0; 1159 } 1160 ath_hal_intrset(ah, 0); 1161 } 1162 ath_draintxq(sc); 1163 if (device_is_enabled(sc->sc_dev)) { 1164 ath_stoprecv(sc); 1165 ath_hal_phydisable(ah); 1166 } else 1167 sc->sc_rxlink = NULL; 1168 IF_PURGE(&ifp->if_snd); 1169 ath_beacon_free(sc); 1170 } 1171 if (disable) 1172 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 1173 } 1174 1175 static void 1176 ath_stop(struct ifnet *ifp, int disable) 1177 { 1178 int s; 1179 1180 s = splnet(); 1181 ath_stop_locked(ifp, disable); 1182 splx(s); 1183 } 1184 1185 static void 1186 ath_restore_diversity(struct ath_softc *sc) 1187 { 1188 struct ifnet *ifp = &sc->sc_if; 1189 struct ath_hal *ah = sc->sc_ah; 1190 1191 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1192 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1193 if_printf(ifp, "could not restore diversity setting %d\n", 1194 sc->sc_diversity); 1195 sc->sc_diversity = ath_hal_getdiversity(ah); 1196 } 1197 } 1198 1199 /* 1200 * Reset the hardware w/o losing operational state. This is 1201 * basically a more efficient way of doing ath_stop, ath_init, 1202 * followed by state transitions to the current 802.11 1203 * operational state. Used to recover from various errors and 1204 * to reset or reload hardware state. 1205 */ 1206 int 1207 ath_reset(struct ifnet *ifp) 1208 { 1209 struct ath_softc *sc = ifp->if_softc; 1210 struct ieee80211com *ic = &sc->sc_ic; 1211 struct ath_hal *ah = sc->sc_ah; 1212 struct ieee80211_channel *c; 1213 HAL_STATUS status; 1214 1215 /* 1216 * Convert to a HAL channel description with the flags 1217 * constrained to reflect the current operating mode. 1218 */ 1219 c = ic->ic_curchan; 1220 sc->sc_curchan.channel = c->ic_freq; 1221 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1222 1223 ath_hal_intrset(ah, 0); /* disable interrupts */ 1224 ath_draintxq(sc); /* stop xmit side */ 1225 ath_stoprecv(sc); /* stop recv side */ 1226 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1227 /* NB: indicate channel change so we do a full reset */ 1228 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1229 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1230 __func__, status); 1231 ath_update_txpow(sc); /* update tx power state */ 1232 ath_restore_diversity(sc); 1233 sc->sc_calinterval = 1; 1234 sc->sc_caltries = 0; 1235 if (ath_startrecv(sc) != 0) /* restart recv */ 1236 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1237 /* 1238 * We may be doing a reset in response to an ioctl 1239 * that changes the channel so update any state that 1240 * might change as a result. 1241 */ 1242 ath_chan_change(sc, c); 1243 if (ic->ic_state == IEEE80211_S_RUN) 1244 ath_beacon_config(sc); /* restart beacons */ 1245 ath_hal_intrset(ah, sc->sc_imask); 1246 1247 ath_start(ifp); /* restart xmit */ 1248 return 0; 1249 } 1250 1251 /* 1252 * Cleanup driver resources when we run out of buffers 1253 * while processing fragments; return the tx buffers 1254 * allocated and drop node references. 1255 */ 1256 static void 1257 ath_txfrag_cleanup(struct ath_softc *sc, 1258 ath_bufhead *frags, struct ieee80211_node *ni) 1259 { 1260 struct ath_buf *bf; 1261 1262 ATH_TXBUF_LOCK_ASSERT(sc); 1263 1264 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1265 STAILQ_REMOVE_HEAD(frags, bf_list); 1266 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1267 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1268 ieee80211_node_decref(ni); 1269 } 1270 } 1271 1272 /* 1273 * Setup xmit of a fragmented frame. Allocate a buffer 1274 * for each frag and bump the node reference count to 1275 * reflect the held reference to be setup by ath_tx_start. 1276 */ 1277 static int 1278 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1279 struct mbuf *m0, struct ieee80211_node *ni) 1280 { 1281 struct mbuf *m; 1282 struct ath_buf *bf; 1283 1284 ATH_TXBUF_LOCK(sc); 1285 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1286 bf = STAILQ_FIRST(&sc->sc_txbuf); 1287 if (bf == NULL) { /* out of buffers, cleanup */ 1288 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1289 __func__); 1290 sc->sc_if.if_flags |= IFF_OACTIVE; 1291 ath_txfrag_cleanup(sc, frags, ni); 1292 break; 1293 } 1294 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1295 ieee80211_node_incref(ni); 1296 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1297 } 1298 ATH_TXBUF_UNLOCK(sc); 1299 1300 return !STAILQ_EMPTY(frags); 1301 } 1302 1303 static void 1304 ath_start(struct ifnet *ifp) 1305 { 1306 struct ath_softc *sc = ifp->if_softc; 1307 struct ath_hal *ah = sc->sc_ah; 1308 struct ieee80211com *ic = &sc->sc_ic; 1309 struct ieee80211_node *ni; 1310 struct ath_buf *bf; 1311 struct mbuf *m, *next; 1312 struct ieee80211_frame *wh; 1313 struct ether_header *eh; 1314 ath_bufhead frags; 1315 1316 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1317 !device_is_active(sc->sc_dev)) 1318 return; 1319 1320 if (sc->sc_flags & ATH_KEY_UPDATING) 1321 return; 1322 1323 for (;;) { 1324 /* 1325 * Grab a TX buffer and associated resources. 1326 */ 1327 ATH_TXBUF_LOCK(sc); 1328 bf = STAILQ_FIRST(&sc->sc_txbuf); 1329 if (bf != NULL) 1330 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1331 ATH_TXBUF_UNLOCK(sc); 1332 if (bf == NULL) { 1333 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1334 __func__); 1335 sc->sc_stats.ast_tx_qstop++; 1336 ifp->if_flags |= IFF_OACTIVE; 1337 break; 1338 } 1339 /* 1340 * Poll the management queue for frames; they 1341 * have priority over normal data frames. 1342 */ 1343 IF_DEQUEUE(&ic->ic_mgtq, m); 1344 if (m == NULL) { 1345 /* 1346 * No data frames go out unless we're associated. 1347 */ 1348 if (ic->ic_state != IEEE80211_S_RUN) { 1349 DPRINTF(sc, ATH_DEBUG_XMIT, 1350 "%s: discard data packet, state %s\n", 1351 __func__, 1352 ieee80211_state_name[ic->ic_state]); 1353 sc->sc_stats.ast_tx_discard++; 1354 ATH_TXBUF_LOCK(sc); 1355 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1356 ATH_TXBUF_UNLOCK(sc); 1357 break; 1358 } 1359 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1360 if (m == NULL) { 1361 ATH_TXBUF_LOCK(sc); 1362 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1363 ATH_TXBUF_UNLOCK(sc); 1364 break; 1365 } 1366 STAILQ_INIT(&frags); 1367 /* 1368 * Find the node for the destination so we can do 1369 * things like power save and fast frames aggregation. 1370 */ 1371 if (m->m_len < sizeof(struct ether_header) && 1372 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1373 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1374 ni = NULL; 1375 goto bad; 1376 } 1377 eh = mtod(m, struct ether_header *); 1378 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1379 if (ni == NULL) { 1380 /* NB: ieee80211_find_txnode does stat+msg */ 1381 m_freem(m); 1382 goto bad; 1383 } 1384 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1385 (m->m_flags & M_PWR_SAV) == 0) { 1386 /* 1387 * Station in power save mode; pass the frame 1388 * to the 802.11 layer and continue. We'll get 1389 * the frame back when the time is right. 1390 */ 1391 ieee80211_pwrsave(ic, ni, m); 1392 goto reclaim; 1393 } 1394 /* calculate priority so we can find the tx queue */ 1395 if (ieee80211_classify(ic, m, ni)) { 1396 DPRINTF(sc, ATH_DEBUG_XMIT, 1397 "%s: discard, classification failure\n", 1398 __func__); 1399 m_freem(m); 1400 goto bad; 1401 } 1402 ifp->if_opackets++; 1403 1404 bpf_mtap(ifp, m, BPF_D_OUT); 1405 /* 1406 * Encapsulate the packet in prep for transmission. 1407 */ 1408 m = ieee80211_encap(ic, m, ni); 1409 if (m == NULL) { 1410 DPRINTF(sc, ATH_DEBUG_XMIT, 1411 "%s: encapsulation failure\n", 1412 __func__); 1413 sc->sc_stats.ast_tx_encap++; 1414 goto bad; 1415 } 1416 /* 1417 * Check for fragmentation. If this has frame 1418 * has been broken up verify we have enough 1419 * buffers to send all the fragments so all 1420 * go out or none... 1421 */ 1422 if ((m->m_flags & M_FRAG) && 1423 !ath_txfrag_setup(sc, &frags, m, ni)) { 1424 DPRINTF(sc, ATH_DEBUG_ANY, 1425 "%s: out of txfrag buffers\n", __func__); 1426 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1427 ath_freetx(m); 1428 goto bad; 1429 } 1430 } else { 1431 /* 1432 * Hack! The referenced node pointer is in the 1433 * rcvif field of the packet header. This is 1434 * placed there by ieee80211_mgmt_output because 1435 * we need to hold the reference with the frame 1436 * and there's no other way (other than packet 1437 * tags which we consider too expensive to use) 1438 * to pass it along. 1439 */ 1440 ni = M_GETCTX(m, struct ieee80211_node *); 1441 M_CLEARCTX(m); 1442 1443 wh = mtod(m, struct ieee80211_frame *); 1444 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1445 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1446 /* fill time stamp */ 1447 u_int64_t tsf; 1448 u_int32_t *tstamp; 1449 1450 tsf = ath_hal_gettsf64(ah); 1451 /* XXX: adjust 100us delay to xmit */ 1452 tsf += 100; 1453 tstamp = (u_int32_t *)&wh[1]; 1454 tstamp[0] = htole32(tsf & 0xffffffff); 1455 tstamp[1] = htole32(tsf >> 32); 1456 } 1457 sc->sc_stats.ast_tx_mgmt++; 1458 } 1459 1460 nextfrag: 1461 next = m->m_nextpkt; 1462 if (ath_tx_start(sc, ni, bf, m)) { 1463 bad: 1464 ifp->if_oerrors++; 1465 reclaim: 1466 ATH_TXBUF_LOCK(sc); 1467 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1468 ath_txfrag_cleanup(sc, &frags, ni); 1469 ATH_TXBUF_UNLOCK(sc); 1470 if (ni != NULL) 1471 ieee80211_free_node(ni); 1472 continue; 1473 } 1474 if (next != NULL) { 1475 m = next; 1476 bf = STAILQ_FIRST(&frags); 1477 KASSERTMSG(bf != NULL, "no buf for txfrag"); 1478 STAILQ_REMOVE_HEAD(&frags, bf_list); 1479 goto nextfrag; 1480 } 1481 1482 ifp->if_timer = 1; 1483 } 1484 } 1485 1486 static int 1487 ath_media_change(struct ifnet *ifp) 1488 { 1489 #define IS_UP(ifp) \ 1490 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1491 int error; 1492 1493 error = ieee80211_media_change(ifp); 1494 if (error == ENETRESET) { 1495 if (IS_UP(ifp)) 1496 ath_init(ifp->if_softc); /* XXX lose error */ 1497 error = 0; 1498 } 1499 return error; 1500 #undef IS_UP 1501 } 1502 1503 #ifdef AR_DEBUG 1504 static void 1505 ath_keyprint(const char *tag, u_int ix, 1506 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1507 { 1508 static const char *ciphers[] = { 1509 "WEP", 1510 "AES-OCB", 1511 "AES-CCM", 1512 "CKIP", 1513 "TKIP", 1514 "CLR", 1515 }; 1516 int i, n; 1517 1518 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1519 for (i = 0, n = hk->kv_len; i < n; i++) 1520 printf("%02x", hk->kv_val[i]); 1521 printf(" mac %s", ether_sprintf(mac)); 1522 if (hk->kv_type == HAL_CIPHER_TKIP) { 1523 printf(" mic "); 1524 for (i = 0; i < sizeof(hk->kv_mic); i++) 1525 printf("%02x", hk->kv_mic[i]); 1526 } 1527 printf("\n"); 1528 } 1529 #endif 1530 1531 /* 1532 * Set a TKIP key into the hardware. This handles the 1533 * potential distribution of key state to multiple key 1534 * cache slots for TKIP. 1535 */ 1536 static int 1537 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1538 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1539 { 1540 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1541 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1542 struct ath_hal *ah = sc->sc_ah; 1543 1544 KASSERTMSG(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1545 "got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher); 1546 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1547 if (sc->sc_splitmic) { 1548 /* 1549 * TX key goes at first index, RX key at the rx index. 1550 * The hal handles the MIC keys at index+64. 1551 */ 1552 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1553 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1554 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1555 zerobssid)) 1556 return 0; 1557 1558 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1559 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1560 /* XXX delete tx key on failure? */ 1561 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1562 hk, mac); 1563 } else { 1564 /* 1565 * Room for both TX+RX MIC keys in one key cache 1566 * slot, just set key at the first index; the HAL 1567 * will handle the reset. 1568 */ 1569 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1570 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1571 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1572 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1573 } 1574 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1575 if (sc->sc_splitmic) { 1576 /* 1577 * NB: must pass MIC key in expected location when 1578 * the keycache only holds one MIC key per entry. 1579 */ 1580 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1581 } else 1582 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1583 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1584 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1585 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1586 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1587 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1588 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1589 } 1590 return 0; 1591 #undef IEEE80211_KEY_XR 1592 } 1593 1594 /* 1595 * Set a net80211 key into the hardware. This handles the 1596 * potential distribution of key state to multiple key 1597 * cache slots for TKIP with hardware MIC support. 1598 */ 1599 static int 1600 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1601 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1602 struct ieee80211_node *bss) 1603 { 1604 #define N(a) (sizeof(a)/sizeof(a[0])) 1605 static const u_int8_t ciphermap[] = { 1606 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1607 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1608 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1609 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1610 (u_int8_t) -1, /* 4 is not allocated */ 1611 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1612 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1613 }; 1614 struct ath_hal *ah = sc->sc_ah; 1615 const struct ieee80211_cipher *cip = k->wk_cipher; 1616 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1617 const u_int8_t *mac; 1618 HAL_KEYVAL hk; 1619 1620 memset(&hk, 0, sizeof(hk)); 1621 /* 1622 * Software crypto uses a "clear key" so non-crypto 1623 * state kept in the key cache are maintained and 1624 * so that rx frames have an entry to match. 1625 */ 1626 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1627 KASSERTMSG(cip->ic_cipher < N(ciphermap), 1628 "invalid cipher type %u", cip->ic_cipher); 1629 hk.kv_type = ciphermap[cip->ic_cipher]; 1630 hk.kv_len = k->wk_keylen; 1631 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1632 } else 1633 hk.kv_type = HAL_CIPHER_CLR; 1634 1635 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1636 /* 1637 * Group keys on hardware that supports multicast frame 1638 * key search use a mac that is the sender's address with 1639 * the high bit set instead of the app-specified address. 1640 */ 1641 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1642 gmac[0] |= 0x80; 1643 mac = gmac; 1644 } else 1645 mac = mac0; 1646 1647 if ((hk.kv_type == HAL_CIPHER_TKIP && 1648 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0)) { 1649 return ath_keyset_tkip(sc, k, &hk, mac); 1650 } else { 1651 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1652 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1653 } 1654 #undef N 1655 } 1656 1657 /* 1658 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1659 * each key, one for decrypt/encrypt and the other for the MIC. 1660 */ 1661 static u_int16_t 1662 key_alloc_2pair(struct ath_softc *sc, 1663 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1664 { 1665 #define N(a) (sizeof(a)/sizeof(a[0])) 1666 u_int i, keyix; 1667 1668 KASSERTMSG(sc->sc_splitmic, "key cache !split"); 1669 /* XXX could optimize */ 1670 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1671 u_int8_t b = sc->sc_keymap[i]; 1672 if (b != 0xff) { 1673 /* 1674 * One or more slots in this byte are free. 1675 */ 1676 keyix = i*NBBY; 1677 while (b & 1) { 1678 again: 1679 keyix++; 1680 b >>= 1; 1681 } 1682 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1683 if (isset(sc->sc_keymap, keyix+32) || 1684 isset(sc->sc_keymap, keyix+64) || 1685 isset(sc->sc_keymap, keyix+32+64)) { 1686 /* full pair unavailable */ 1687 /* XXX statistic */ 1688 if (keyix == (i+1)*NBBY) { 1689 /* no slots were appropriate, advance */ 1690 continue; 1691 } 1692 goto again; 1693 } 1694 setbit(sc->sc_keymap, keyix); 1695 setbit(sc->sc_keymap, keyix+64); 1696 setbit(sc->sc_keymap, keyix+32); 1697 setbit(sc->sc_keymap, keyix+32+64); 1698 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1699 "%s: key pair %u,%u %u,%u\n", 1700 __func__, keyix, keyix+64, 1701 keyix+32, keyix+32+64); 1702 *txkeyix = keyix; 1703 *rxkeyix = keyix+32; 1704 return keyix; 1705 } 1706 } 1707 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1708 return IEEE80211_KEYIX_NONE; 1709 #undef N 1710 } 1711 1712 /* 1713 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1714 * each key, one for decrypt/encrypt and the other for the MIC. 1715 */ 1716 static int 1717 key_alloc_pair(struct ath_softc *sc, ieee80211_keyix *txkeyix, 1718 ieee80211_keyix *rxkeyix) 1719 { 1720 #define N(a) (sizeof(a)/sizeof(a[0])) 1721 u_int i, keyix; 1722 1723 KASSERTMSG(!sc->sc_splitmic, "key cache split"); 1724 /* XXX could optimize */ 1725 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1726 uint8_t b = sc->sc_keymap[i]; 1727 if (b != 0xff) { 1728 /* 1729 * One or more slots in this byte are free. 1730 */ 1731 keyix = i*NBBY; 1732 while (b & 1) { 1733 again: 1734 keyix++; 1735 b >>= 1; 1736 } 1737 if (isset(sc->sc_keymap, keyix+64)) { 1738 /* full pair unavailable */ 1739 /* XXX statistic */ 1740 if (keyix == (i+1)*NBBY) { 1741 /* no slots were appropriate, advance */ 1742 continue; 1743 } 1744 goto again; 1745 } 1746 setbit(sc->sc_keymap, keyix); 1747 setbit(sc->sc_keymap, keyix+64); 1748 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1749 "%s: key pair %u,%u\n", 1750 __func__, keyix, keyix+64); 1751 *txkeyix = *rxkeyix = keyix; 1752 return 1; 1753 } 1754 } 1755 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1756 return 0; 1757 #undef N 1758 } 1759 1760 /* 1761 * Allocate a single key cache slot. 1762 */ 1763 static int 1764 key_alloc_single(struct ath_softc *sc, 1765 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1766 { 1767 #define N(a) (sizeof(a)/sizeof(a[0])) 1768 u_int i, keyix; 1769 1770 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1771 for (i = 0; i < N(sc->sc_keymap); i++) { 1772 u_int8_t b = sc->sc_keymap[i]; 1773 if (b != 0xff) { 1774 /* 1775 * One or more slots are free. 1776 */ 1777 keyix = i*NBBY; 1778 while (b & 1) 1779 keyix++, b >>= 1; 1780 setbit(sc->sc_keymap, keyix); 1781 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1782 __func__, keyix); 1783 *txkeyix = *rxkeyix = keyix; 1784 return 1; 1785 } 1786 } 1787 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1788 return 0; 1789 #undef N 1790 } 1791 1792 /* 1793 * Allocate one or more key cache slots for a uniacst key. The 1794 * key itself is needed only to identify the cipher. For hardware 1795 * TKIP with split cipher+MIC keys we allocate two key cache slot 1796 * pairs so that we can setup separate TX and RX MIC keys. Note 1797 * that the MIC key for a TKIP key at slot i is assumed by the 1798 * hardware to be at slot i+64. This limits TKIP keys to the first 1799 * 64 entries. 1800 */ 1801 static int 1802 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1803 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1804 { 1805 struct ath_softc *sc = ic->ic_ifp->if_softc; 1806 1807 /* 1808 * Group key allocation must be handled specially for 1809 * parts that do not support multicast key cache search 1810 * functionality. For those parts the key id must match 1811 * the h/w key index so lookups find the right key. On 1812 * parts w/ the key search facility we install the sender's 1813 * mac address (with the high bit set) and let the hardware 1814 * find the key w/o using the key id. This is preferred as 1815 * it permits us to support multiple users for adhoc and/or 1816 * multi-station operation. 1817 */ 1818 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1819 if (!(&ic->ic_nw_keys[0] <= k && 1820 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1821 /* should not happen */ 1822 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1823 "%s: bogus group key\n", __func__); 1824 return 0; 1825 } 1826 /* 1827 * XXX we pre-allocate the global keys so 1828 * have no way to check if they've already been allocated. 1829 */ 1830 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1831 return 1; 1832 } 1833 1834 /* 1835 * We allocate two pair for TKIP when using the h/w to do 1836 * the MIC. For everything else, including software crypto, 1837 * we allocate a single entry. Note that s/w crypto requires 1838 * a pass-through slot on the 5211 and 5212. The 5210 does 1839 * not support pass-through cache entries and we map all 1840 * those requests to slot 0. 1841 */ 1842 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1843 return key_alloc_single(sc, keyix, rxkeyix); 1844 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1845 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1846 if (sc->sc_splitmic) 1847 return key_alloc_2pair(sc, keyix, rxkeyix); 1848 else 1849 return key_alloc_pair(sc, keyix, rxkeyix); 1850 } else { 1851 return key_alloc_single(sc, keyix, rxkeyix); 1852 } 1853 } 1854 1855 /* 1856 * Delete an entry in the key cache allocated by ath_key_alloc. 1857 */ 1858 static int 1859 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1860 { 1861 struct ath_softc *sc = ic->ic_ifp->if_softc; 1862 struct ath_hal *ah = sc->sc_ah; 1863 const struct ieee80211_cipher *cip = k->wk_cipher; 1864 u_int keyix = k->wk_keyix; 1865 1866 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1867 1868 if (!device_has_power(sc->sc_dev)) { 1869 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1870 k->wk_keyix); 1871 } 1872 1873 ath_hal_keyreset(ah, keyix); 1874 /* 1875 * Handle split tx/rx keying required for TKIP with h/w MIC. 1876 */ 1877 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1878 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1879 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1880 if (keyix >= IEEE80211_WEP_NKID) { 1881 /* 1882 * Don't touch keymap entries for global keys so 1883 * they are never considered for dynamic allocation. 1884 */ 1885 clrbit(sc->sc_keymap, keyix); 1886 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1887 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1888 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1889 if (sc->sc_splitmic) { 1890 /* +32 for RX key, +32+64 for RX key MIC */ 1891 clrbit(sc->sc_keymap, keyix+32); 1892 clrbit(sc->sc_keymap, keyix+32+64); 1893 } 1894 } 1895 } 1896 return 1; 1897 } 1898 1899 /* 1900 * Set the key cache contents for the specified key. Key cache 1901 * slot(s) must already have been allocated by ath_key_alloc. 1902 */ 1903 static int 1904 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1905 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1906 { 1907 struct ath_softc *sc = ic->ic_ifp->if_softc; 1908 1909 if (!device_has_power(sc->sc_dev)) { 1910 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1911 k->wk_keyix); 1912 } 1913 return ath_keyset(sc, k, mac, ic->ic_bss); 1914 } 1915 1916 /* 1917 * Block/unblock tx+rx processing while a key change is done. 1918 * We assume the caller serializes key management operations 1919 * so we only need to worry about synchronization with other 1920 * uses that originate in the driver. 1921 */ 1922 static void 1923 ath_key_update_begin(struct ieee80211com *ic) 1924 { 1925 struct ifnet *ifp = ic->ic_ifp; 1926 struct ath_softc *sc = ifp->if_softc; 1927 1928 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1929 #if 0 1930 tasklet_disable(&sc->sc_rxtq); 1931 #endif 1932 sc->sc_flags |= ATH_KEY_UPDATING; 1933 } 1934 1935 static void 1936 ath_key_update_end(struct ieee80211com *ic) 1937 { 1938 struct ifnet *ifp = ic->ic_ifp; 1939 struct ath_softc *sc = ifp->if_softc; 1940 1941 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1942 sc->sc_flags &= ~ATH_KEY_UPDATING; 1943 #if 0 1944 tasklet_enable(&sc->sc_rxtq); 1945 #endif 1946 } 1947 1948 /* 1949 * Calculate the receive filter according to the 1950 * operating mode and state: 1951 * 1952 * o always accept unicast, broadcast, and multicast traffic 1953 * o maintain current state of phy error reception (the hal 1954 * may enable phy error frames for noise immunity work) 1955 * o probe request frames are accepted only when operating in 1956 * hostap, adhoc, or monitor modes 1957 * o enable promiscuous mode according to the interface state 1958 * o accept beacons: 1959 * - when operating in adhoc mode so the 802.11 layer creates 1960 * node table entries for peers, 1961 * - when operating in station mode for collecting rssi data when 1962 * the station is otherwise quiet, or 1963 * - when scanning 1964 */ 1965 static u_int32_t 1966 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1967 { 1968 struct ieee80211com *ic = &sc->sc_ic; 1969 struct ath_hal *ah = sc->sc_ah; 1970 struct ifnet *ifp = &sc->sc_if; 1971 u_int32_t rfilt; 1972 1973 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1974 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1975 if (ic->ic_opmode != IEEE80211_M_STA) 1976 rfilt |= HAL_RX_FILTER_PROBEREQ; 1977 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1978 (ifp->if_flags & IFF_PROMISC)) 1979 rfilt |= HAL_RX_FILTER_PROM; 1980 if (ifp->if_flags & IFF_PROMISC) 1981 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1982 if (ic->ic_opmode == IEEE80211_M_STA || 1983 ic->ic_opmode == IEEE80211_M_IBSS || 1984 state == IEEE80211_S_SCAN) 1985 rfilt |= HAL_RX_FILTER_BEACON; 1986 return rfilt; 1987 } 1988 1989 static void 1990 ath_mode_init(struct ath_softc *sc) 1991 { 1992 struct ifnet *ifp = &sc->sc_if; 1993 struct ieee80211com *ic = &sc->sc_ic; 1994 struct ath_hal *ah = sc->sc_ah; 1995 struct ether_multi *enm; 1996 struct ether_multistep estep; 1997 u_int32_t rfilt, mfilt[2], val; 1998 int i; 1999 uint8_t pos; 2000 2001 /* configure rx filter */ 2002 rfilt = ath_calcrxfilter(sc, ic->ic_state); 2003 ath_hal_setrxfilter(ah, rfilt); 2004 2005 /* configure operational mode */ 2006 ath_hal_setopmode(ah); 2007 2008 /* Write keys to hardware; it may have been powered down. */ 2009 ath_key_update_begin(ic); 2010 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2011 ath_key_set(ic, 2012 &ic->ic_crypto.cs_nw_keys[i], 2013 ic->ic_myaddr); 2014 } 2015 ath_key_update_end(ic); 2016 2017 /* 2018 * Handle any link-level address change. Note that we only 2019 * need to force ic_myaddr; any other addresses are handled 2020 * as a byproduct of the ifnet code marking the interface 2021 * down then up. 2022 * 2023 * XXX should get from lladdr instead of arpcom but that's more work 2024 */ 2025 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 2026 ath_hal_setmac(ah, ic->ic_myaddr); 2027 2028 /* calculate and install multicast filter */ 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 mfilt[0] = mfilt[1] = 0; 2031 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 2032 while (enm != NULL) { 2033 void *dl; 2034 /* XXX Punt on ranges. */ 2035 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 2036 mfilt[0] = mfilt[1] = 0xffffffff; 2037 ifp->if_flags |= IFF_ALLMULTI; 2038 break; 2039 } 2040 dl = enm->enm_addrlo; 2041 val = LE_READ_4((char *)dl + 0); 2042 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2043 val = LE_READ_4((char *)dl + 3); 2044 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2045 pos &= 0x3f; 2046 mfilt[pos / 32] |= (1 << (pos % 32)); 2047 2048 ETHER_NEXT_MULTI(estep, enm); 2049 } 2050 2051 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 2052 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 2053 __func__, rfilt, mfilt[0], mfilt[1]); 2054 } 2055 2056 /* 2057 * Set the slot time based on the current setting. 2058 */ 2059 static void 2060 ath_setslottime(struct ath_softc *sc) 2061 { 2062 struct ieee80211com *ic = &sc->sc_ic; 2063 struct ath_hal *ah = sc->sc_ah; 2064 2065 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2066 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2067 else 2068 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2069 sc->sc_updateslot = OK; 2070 } 2071 2072 /* 2073 * Callback from the 802.11 layer to update the 2074 * slot time based on the current setting. 2075 */ 2076 static void 2077 ath_updateslot(struct ifnet *ifp) 2078 { 2079 struct ath_softc *sc = ifp->if_softc; 2080 struct ieee80211com *ic = &sc->sc_ic; 2081 2082 /* 2083 * When not coordinating the BSS, change the hardware 2084 * immediately. For other operation we defer the change 2085 * until beacon updates have propagated to the stations. 2086 */ 2087 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2088 sc->sc_updateslot = UPDATE; 2089 else 2090 ath_setslottime(sc); 2091 } 2092 2093 /* 2094 * Setup a h/w transmit queue for beacons. 2095 */ 2096 static int 2097 ath_beaconq_setup(struct ath_hal *ah) 2098 { 2099 HAL_TXQ_INFO qi; 2100 2101 memset(&qi, 0, sizeof(qi)); 2102 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2103 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2104 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2105 /* NB: for dynamic turbo, don't enable any other interrupts */ 2106 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2107 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2108 } 2109 2110 /* 2111 * Setup the transmit queue parameters for the beacon queue. 2112 */ 2113 static int 2114 ath_beaconq_config(struct ath_softc *sc) 2115 { 2116 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2117 struct ieee80211com *ic = &sc->sc_ic; 2118 struct ath_hal *ah = sc->sc_ah; 2119 HAL_TXQ_INFO qi; 2120 2121 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2122 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2123 /* 2124 * Always burst out beacon and CAB traffic. 2125 */ 2126 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2127 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2128 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2129 } else { 2130 struct wmeParams *wmep = 2131 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2132 /* 2133 * Adhoc mode; important thing is to use 2x cwmin. 2134 */ 2135 qi.tqi_aifs = wmep->wmep_aifsn; 2136 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2137 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2138 } 2139 2140 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2141 device_printf(sc->sc_dev, "unable to update parameters for " 2142 "beacon hardware queue!\n"); 2143 return 0; 2144 } else { 2145 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2146 return 1; 2147 } 2148 #undef ATH_EXPONENT_TO_VALUE 2149 } 2150 2151 /* 2152 * Allocate and setup an initial beacon frame. 2153 */ 2154 static int 2155 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2156 { 2157 struct ieee80211com *ic = ni->ni_ic; 2158 struct ath_buf *bf; 2159 struct mbuf *m; 2160 int error; 2161 2162 bf = STAILQ_FIRST(&sc->sc_bbuf); 2163 if (bf == NULL) { 2164 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2165 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2166 return ENOMEM; /* XXX */ 2167 } 2168 /* 2169 * NB: the beacon data buffer must be 32-bit aligned; 2170 * we assume the mbuf routines will return us something 2171 * with this alignment (perhaps should assert). 2172 */ 2173 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2174 if (m == NULL) { 2175 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2176 __func__); 2177 sc->sc_stats.ast_be_nombuf++; 2178 return ENOMEM; 2179 } 2180 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2181 BUS_DMA_NOWAIT); 2182 if (error == 0) { 2183 bf->bf_m = m; 2184 bf->bf_node = ieee80211_ref_node(ni); 2185 } else { 2186 m_freem(m); 2187 } 2188 return error; 2189 } 2190 2191 /* 2192 * Setup the beacon frame for transmit. 2193 */ 2194 static void 2195 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2196 { 2197 #define USE_SHPREAMBLE(_ic) \ 2198 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2199 == IEEE80211_F_SHPREAMBLE) 2200 struct ieee80211_node *ni = bf->bf_node; 2201 struct ieee80211com *ic = ni->ni_ic; 2202 struct mbuf *m = bf->bf_m; 2203 struct ath_hal *ah = sc->sc_ah; 2204 struct ath_desc *ds; 2205 int flags, antenna; 2206 const HAL_RATE_TABLE *rt; 2207 u_int8_t rix, rate; 2208 2209 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2210 __func__, m, m->m_len); 2211 2212 /* setup descriptors */ 2213 ds = bf->bf_desc; 2214 2215 flags = HAL_TXDESC_NOACK; 2216 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2217 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2218 flags |= HAL_TXDESC_VEOL; 2219 /* 2220 * Let hardware handle antenna switching unless 2221 * the user has selected a transmit antenna 2222 * (sc_txantenna is not 0). 2223 */ 2224 antenna = sc->sc_txantenna; 2225 } else { 2226 ds->ds_link = 0; 2227 /* 2228 * Switch antenna every 4 beacons, unless the user 2229 * has selected a transmit antenna (sc_txantenna 2230 * is not 0). 2231 * 2232 * XXX assumes two antenna 2233 */ 2234 if (sc->sc_txantenna == 0) 2235 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2236 else 2237 antenna = sc->sc_txantenna; 2238 } 2239 2240 KASSERTMSG(bf->bf_nseg == 1, 2241 "multi-segment beacon frame; nseg %u", bf->bf_nseg); 2242 ds->ds_data = bf->bf_segs[0].ds_addr; 2243 /* 2244 * Calculate rate code. 2245 * XXX everything at min xmit rate 2246 */ 2247 rix = sc->sc_minrateix; 2248 rt = sc->sc_currates; 2249 rate = rt->info[rix].rateCode; 2250 if (USE_SHPREAMBLE(ic)) 2251 rate |= rt->info[rix].shortPreamble; 2252 ath_hal_setuptxdesc(ah, ds 2253 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2254 , sizeof(struct ieee80211_frame)/* header length */ 2255 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2256 , ni->ni_txpower /* txpower XXX */ 2257 , rate, 1 /* series 0 rate/tries */ 2258 , HAL_TXKEYIX_INVALID /* no encryption */ 2259 , antenna /* antenna mode */ 2260 , flags /* no ack, veol for beacons */ 2261 , 0 /* rts/cts rate */ 2262 , 0 /* rts/cts duration */ 2263 ); 2264 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2265 ath_hal_filltxdesc(ah, ds 2266 , roundup(m->m_len, 4) /* buffer length */ 2267 , AH_TRUE /* first segment */ 2268 , AH_TRUE /* last segment */ 2269 , ds /* first descriptor */ 2270 ); 2271 2272 /* NB: The desc swap function becomes void, if descriptor swapping 2273 * is not enabled 2274 */ 2275 ath_desc_swap(ds); 2276 2277 #undef USE_SHPREAMBLE 2278 } 2279 2280 /* 2281 * Transmit a beacon frame at SWBA. Dynamic updates to the 2282 * frame contents are done as needed and the slot time is 2283 * also adjusted based on current state. 2284 */ 2285 static void 2286 ath_beacon_proc(void *arg, int pending) 2287 { 2288 struct ath_softc *sc = arg; 2289 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2290 struct ieee80211_node *ni = bf->bf_node; 2291 struct ieee80211com *ic = ni->ni_ic; 2292 struct ath_hal *ah = sc->sc_ah; 2293 struct mbuf *m; 2294 int ncabq, error, otherant; 2295 2296 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2297 __func__, pending); 2298 2299 if (ic->ic_opmode == IEEE80211_M_STA || 2300 ic->ic_opmode == IEEE80211_M_MONITOR || 2301 bf == NULL || bf->bf_m == NULL) { 2302 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2303 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2304 return; 2305 } 2306 /* 2307 * Check if the previous beacon has gone out. If 2308 * not don't try to post another, skip this period 2309 * and wait for the next. Missed beacons indicate 2310 * a problem and should not occur. If we miss too 2311 * many consecutive beacons reset the device. 2312 */ 2313 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2314 sc->sc_bmisscount++; 2315 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2316 "%s: missed %u consecutive beacons\n", 2317 __func__, sc->sc_bmisscount); 2318 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2319 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2320 return; 2321 } 2322 if (sc->sc_bmisscount != 0) { 2323 DPRINTF(sc, ATH_DEBUG_BEACON, 2324 "%s: resume beacon xmit after %u misses\n", 2325 __func__, sc->sc_bmisscount); 2326 sc->sc_bmisscount = 0; 2327 } 2328 2329 /* 2330 * Update dynamic beacon contents. If this returns 2331 * non-zero then we need to remap the memory because 2332 * the beacon frame changed size (probably because 2333 * of the TIM bitmap). 2334 */ 2335 m = bf->bf_m; 2336 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2337 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2338 /* XXX too conservative? */ 2339 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2340 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2341 BUS_DMA_NOWAIT); 2342 if (error != 0) { 2343 if_printf(&sc->sc_if, 2344 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2345 __func__, error); 2346 return; 2347 } 2348 } 2349 2350 /* 2351 * Handle slot time change when a non-ERP station joins/leaves 2352 * an 11g network. The 802.11 layer notifies us via callback, 2353 * we mark updateslot, then wait one beacon before effecting 2354 * the change. This gives associated stations at least one 2355 * beacon interval to note the state change. 2356 */ 2357 /* XXX locking */ 2358 if (sc->sc_updateslot == UPDATE) 2359 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2360 else if (sc->sc_updateslot == COMMIT) 2361 ath_setslottime(sc); /* commit change to h/w */ 2362 2363 /* 2364 * Check recent per-antenna transmit statistics and flip 2365 * the default antenna if noticeably more frames went out 2366 * on the non-default antenna. 2367 * XXX assumes 2 anntenae 2368 */ 2369 otherant = sc->sc_defant & 1 ? 2 : 1; 2370 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2371 ath_setdefantenna(sc, otherant); 2372 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2373 2374 /* 2375 * Construct tx descriptor. 2376 */ 2377 ath_beacon_setup(sc, bf); 2378 2379 /* 2380 * Stop any current dma and put the new frame on the queue. 2381 * This should never fail since we check above that no frames 2382 * are still pending on the queue. 2383 */ 2384 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2385 DPRINTF(sc, ATH_DEBUG_ANY, 2386 "%s: beacon queue %u did not stop?\n", 2387 __func__, sc->sc_bhalq); 2388 } 2389 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2390 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2391 2392 /* 2393 * Enable the CAB queue before the beacon queue to 2394 * insure cab frames are triggered by this beacon. 2395 */ 2396 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2397 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2398 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2399 ath_hal_txstart(ah, sc->sc_bhalq); 2400 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2401 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2402 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2403 2404 sc->sc_stats.ast_be_xmit++; 2405 } 2406 2407 /* 2408 * Reset the hardware after detecting beacons have stopped. 2409 */ 2410 static void 2411 ath_bstuck_proc(void *arg, int pending) 2412 { 2413 struct ath_softc *sc = arg; 2414 struct ifnet *ifp = &sc->sc_if; 2415 #ifdef __NetBSD__ 2416 int s; 2417 #endif 2418 2419 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2420 sc->sc_bmisscount); 2421 #ifdef __NetBSD__ 2422 s = splnet(); 2423 #endif 2424 ath_reset(ifp); 2425 #ifdef __NetBSD__ 2426 splx(s); 2427 #endif 2428 } 2429 2430 /* 2431 * Reclaim beacon resources. 2432 */ 2433 static void 2434 ath_beacon_free(struct ath_softc *sc) 2435 { 2436 struct ath_buf *bf; 2437 2438 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2439 if (bf->bf_m != NULL) { 2440 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2441 m_freem(bf->bf_m); 2442 bf->bf_m = NULL; 2443 } 2444 if (bf->bf_node != NULL) { 2445 ieee80211_free_node(bf->bf_node); 2446 bf->bf_node = NULL; 2447 } 2448 } 2449 } 2450 2451 /* 2452 * Configure the beacon and sleep timers. 2453 * 2454 * When operating as an AP this resets the TSF and sets 2455 * up the hardware to notify us when we need to issue beacons. 2456 * 2457 * When operating in station mode this sets up the beacon 2458 * timers according to the timestamp of the last received 2459 * beacon and the current TSF, configures PCF and DTIM 2460 * handling, programs the sleep registers so the hardware 2461 * will wakeup in time to receive beacons, and configures 2462 * the beacon miss handling so we'll receive a BMISS 2463 * interrupt when we stop seeing beacons from the AP 2464 * we've associated with. 2465 */ 2466 static void 2467 ath_beacon_config(struct ath_softc *sc) 2468 { 2469 #define TSF_TO_TU(_h,_l) \ 2470 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2471 #define FUDGE 2 2472 struct ath_hal *ah = sc->sc_ah; 2473 struct ieee80211com *ic = &sc->sc_ic; 2474 struct ieee80211_node *ni = ic->ic_bss; 2475 u_int32_t nexttbtt, intval, tsftu; 2476 u_int64_t tsf; 2477 2478 /* extract tstamp from last beacon and convert to TU */ 2479 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2480 LE_READ_4(ni->ni_tstamp.data)); 2481 /* NB: the beacon interval is kept internally in TU's */ 2482 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2483 if (nexttbtt == 0) /* e.g. for ap mode */ 2484 nexttbtt = intval; 2485 else if (intval) /* NB: can be 0 for monitor mode */ 2486 nexttbtt = roundup(nexttbtt, intval); 2487 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2488 __func__, nexttbtt, intval, ni->ni_intval); 2489 if (ic->ic_opmode == IEEE80211_M_STA) { 2490 HAL_BEACON_STATE bs; 2491 int dtimperiod, dtimcount; 2492 int cfpperiod, cfpcount; 2493 2494 /* 2495 * Setup dtim and cfp parameters according to 2496 * last beacon we received (which may be none). 2497 */ 2498 dtimperiod = ni->ni_dtim_period; 2499 if (dtimperiod <= 0) /* NB: 0 if not known */ 2500 dtimperiod = 1; 2501 dtimcount = ni->ni_dtim_count; 2502 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2503 dtimcount = 0; /* XXX? */ 2504 cfpperiod = 1; /* NB: no PCF support yet */ 2505 cfpcount = 0; 2506 /* 2507 * Pull nexttbtt forward to reflect the current 2508 * TSF and calculate dtim+cfp state for the result. 2509 */ 2510 tsf = ath_hal_gettsf64(ah); 2511 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2512 do { 2513 nexttbtt += intval; 2514 if (--dtimcount < 0) { 2515 dtimcount = dtimperiod - 1; 2516 if (--cfpcount < 0) 2517 cfpcount = cfpperiod - 1; 2518 } 2519 } while (nexttbtt < tsftu); 2520 memset(&bs, 0, sizeof(bs)); 2521 bs.bs_intval = intval; 2522 bs.bs_nexttbtt = nexttbtt; 2523 bs.bs_dtimperiod = dtimperiod*intval; 2524 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2525 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2526 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2527 bs.bs_cfpmaxduration = 0; 2528 #if 0 2529 /* 2530 * The 802.11 layer records the offset to the DTIM 2531 * bitmap while receiving beacons; use it here to 2532 * enable h/w detection of our AID being marked in 2533 * the bitmap vector (to indicate frames for us are 2534 * pending at the AP). 2535 * XXX do DTIM handling in s/w to WAR old h/w bugs 2536 * XXX enable based on h/w rev for newer chips 2537 */ 2538 bs.bs_timoffset = ni->ni_timoff; 2539 #endif 2540 /* 2541 * Calculate the number of consecutive beacons to miss 2542 * before taking a BMISS interrupt. The configuration 2543 * is specified in ms, so we need to convert that to 2544 * TU's and then calculate based on the beacon interval. 2545 * Note that we clamp the result to at most 10 beacons. 2546 */ 2547 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2548 if (bs.bs_bmissthreshold > 10) 2549 bs.bs_bmissthreshold = 10; 2550 else if (bs.bs_bmissthreshold <= 0) 2551 bs.bs_bmissthreshold = 1; 2552 2553 /* 2554 * Calculate sleep duration. The configuration is 2555 * given in ms. We insure a multiple of the beacon 2556 * period is used. Also, if the sleep duration is 2557 * greater than the DTIM period then it makes senses 2558 * to make it a multiple of that. 2559 * 2560 * XXX fixed at 100ms 2561 */ 2562 bs.bs_sleepduration = 2563 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2564 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2565 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2566 2567 DPRINTF(sc, ATH_DEBUG_BEACON, 2568 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2569 , __func__ 2570 , tsf, tsftu 2571 , bs.bs_intval 2572 , bs.bs_nexttbtt 2573 , bs.bs_dtimperiod 2574 , bs.bs_nextdtim 2575 , bs.bs_bmissthreshold 2576 , bs.bs_sleepduration 2577 , bs.bs_cfpperiod 2578 , bs.bs_cfpmaxduration 2579 , bs.bs_cfpnext 2580 , bs.bs_timoffset 2581 ); 2582 ath_hal_intrset(ah, 0); 2583 ath_hal_beacontimers(ah, &bs); 2584 sc->sc_imask |= HAL_INT_BMISS; 2585 ath_hal_intrset(ah, sc->sc_imask); 2586 } else { 2587 ath_hal_intrset(ah, 0); 2588 if (nexttbtt == intval) 2589 intval |= HAL_BEACON_RESET_TSF; 2590 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2591 /* 2592 * In IBSS mode enable the beacon timers but only 2593 * enable SWBA interrupts if we need to manually 2594 * prepare beacon frames. Otherwise we use a 2595 * self-linked tx descriptor and let the hardware 2596 * deal with things. 2597 */ 2598 intval |= HAL_BEACON_ENA; 2599 if (!sc->sc_hasveol) 2600 sc->sc_imask |= HAL_INT_SWBA; 2601 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2602 /* 2603 * Pull nexttbtt forward to reflect 2604 * the current TSF. 2605 */ 2606 tsf = ath_hal_gettsf64(ah); 2607 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2608 do { 2609 nexttbtt += intval; 2610 } while (nexttbtt < tsftu); 2611 } 2612 ath_beaconq_config(sc); 2613 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2614 /* 2615 * In AP mode we enable the beacon timers and 2616 * SWBA interrupts to prepare beacon frames. 2617 */ 2618 intval |= HAL_BEACON_ENA; 2619 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2620 ath_beaconq_config(sc); 2621 } 2622 ath_hal_beaconinit(ah, nexttbtt, intval); 2623 sc->sc_bmisscount = 0; 2624 ath_hal_intrset(ah, sc->sc_imask); 2625 /* 2626 * When using a self-linked beacon descriptor in 2627 * ibss mode load it once here. 2628 */ 2629 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2630 ath_beacon_proc(sc, 0); 2631 } 2632 sc->sc_syncbeacon = 0; 2633 #undef UNDEF 2634 #undef TSF_TO_TU 2635 } 2636 2637 static int 2638 ath_descdma_setup(struct ath_softc *sc, 2639 struct ath_descdma *dd, ath_bufhead *head, 2640 const char *name, int nbuf, int ndesc) 2641 { 2642 #define DS2PHYS(_dd, _ds) \ 2643 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2644 struct ifnet *ifp = &sc->sc_if; 2645 struct ath_desc *ds; 2646 struct ath_buf *bf; 2647 int i, bsize, error; 2648 2649 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2650 __func__, name, nbuf, ndesc); 2651 2652 dd->dd_name = name; 2653 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2654 2655 /* 2656 * Setup DMA descriptor area. 2657 */ 2658 dd->dd_dmat = sc->sc_dmat; 2659 2660 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2661 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2662 2663 if (error != 0) { 2664 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2665 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2666 goto fail0; 2667 } 2668 2669 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2670 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2671 if (error != 0) { 2672 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2673 nbuf * ndesc, dd->dd_name, error); 2674 goto fail1; 2675 } 2676 2677 /* allocate descriptors */ 2678 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2679 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2680 if (error != 0) { 2681 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2682 "error %u\n", dd->dd_name, error); 2683 goto fail2; 2684 } 2685 2686 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2687 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2688 if (error != 0) { 2689 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2690 dd->dd_name, error); 2691 goto fail3; 2692 } 2693 2694 ds = dd->dd_desc; 2695 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2696 DPRINTF(sc, ATH_DEBUG_RESET, 2697 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2698 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2699 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2700 2701 /* allocate rx buffers */ 2702 bsize = sizeof(struct ath_buf) * nbuf; 2703 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2704 if (bf == NULL) { 2705 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2706 dd->dd_name, bsize); 2707 goto fail4; 2708 } 2709 dd->dd_bufptr = bf; 2710 2711 STAILQ_INIT(head); 2712 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2713 bf->bf_desc = ds; 2714 bf->bf_daddr = DS2PHYS(dd, ds); 2715 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2716 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2717 if (error != 0) { 2718 if_printf(ifp, "unable to create dmamap for %s " 2719 "buffer %u, error %u\n", dd->dd_name, i, error); 2720 ath_descdma_cleanup(sc, dd, head); 2721 return error; 2722 } 2723 STAILQ_INSERT_TAIL(head, bf, bf_list); 2724 } 2725 return 0; 2726 fail4: 2727 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2728 fail3: 2729 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2730 fail2: 2731 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2732 fail1: 2733 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2734 fail0: 2735 memset(dd, 0, sizeof(*dd)); 2736 return error; 2737 #undef DS2PHYS 2738 } 2739 2740 static void 2741 ath_descdma_cleanup(struct ath_softc *sc, 2742 struct ath_descdma *dd, ath_bufhead *head) 2743 { 2744 struct ath_buf *bf; 2745 struct ieee80211_node *ni; 2746 2747 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2748 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2749 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2750 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2751 2752 STAILQ_FOREACH(bf, head, bf_list) { 2753 if (bf->bf_m) { 2754 m_freem(bf->bf_m); 2755 bf->bf_m = NULL; 2756 } 2757 if (bf->bf_dmamap != NULL) { 2758 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2759 bf->bf_dmamap = NULL; 2760 } 2761 ni = bf->bf_node; 2762 bf->bf_node = NULL; 2763 if (ni != NULL) { 2764 /* 2765 * Reclaim node reference. 2766 */ 2767 ieee80211_free_node(ni); 2768 } 2769 } 2770 2771 STAILQ_INIT(head); 2772 free(dd->dd_bufptr, M_ATHDEV); 2773 memset(dd, 0, sizeof(*dd)); 2774 } 2775 2776 static int 2777 ath_desc_alloc(struct ath_softc *sc) 2778 { 2779 int error; 2780 2781 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2782 "rx", ath_rxbuf, 1); 2783 if (error != 0) 2784 return error; 2785 2786 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2787 "tx", ath_txbuf, ATH_TXDESC); 2788 if (error != 0) { 2789 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2790 return error; 2791 } 2792 2793 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2794 "beacon", 1, 1); 2795 if (error != 0) { 2796 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2797 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2798 return error; 2799 } 2800 return 0; 2801 } 2802 2803 static void 2804 ath_desc_free(struct ath_softc *sc) 2805 { 2806 2807 if (sc->sc_bdma.dd_desc_len != 0) 2808 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2809 if (sc->sc_txdma.dd_desc_len != 0) 2810 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2811 if (sc->sc_rxdma.dd_desc_len != 0) 2812 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2813 } 2814 2815 static struct ieee80211_node * 2816 ath_node_alloc(struct ieee80211_node_table *nt) 2817 { 2818 struct ieee80211com *ic = nt->nt_ic; 2819 struct ath_softc *sc = ic->ic_ifp->if_softc; 2820 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2821 struct ath_node *an; 2822 2823 an = malloc(space, M_80211_NODE, M_NOWAIT | M_ZERO); 2824 if (an == NULL) { 2825 /* XXX stat+msg */ 2826 return NULL; 2827 } 2828 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2829 ath_rate_node_init(sc, an); 2830 2831 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2832 return &an->an_node; 2833 } 2834 2835 static void 2836 ath_node_free(struct ieee80211_node *ni) 2837 { 2838 struct ieee80211com *ic = ni->ni_ic; 2839 struct ath_softc *sc = ic->ic_ifp->if_softc; 2840 2841 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2842 2843 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2844 sc->sc_node_free(ni); 2845 } 2846 2847 static u_int8_t 2848 ath_node_getrssi(const struct ieee80211_node *ni) 2849 { 2850 #define HAL_EP_RND(x, mul) \ 2851 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2852 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2853 int32_t rssi; 2854 2855 /* 2856 * When only one frame is received there will be no state in 2857 * avgrssi so fallback on the value recorded by the 802.11 layer. 2858 */ 2859 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2860 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2861 else 2862 rssi = ni->ni_rssi; 2863 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2864 #undef HAL_EP_RND 2865 } 2866 2867 static int 2868 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2869 { 2870 struct ath_hal *ah = sc->sc_ah; 2871 int error; 2872 struct mbuf *m; 2873 struct ath_desc *ds; 2874 2875 m = bf->bf_m; 2876 if (m == NULL) { 2877 /* 2878 * NB: by assigning a page to the rx dma buffer we 2879 * implicitly satisfy the Atheros requirement that 2880 * this buffer be cache-line-aligned and sized to be 2881 * multiple of the cache line size. Not doing this 2882 * causes weird stuff to happen (for the 5210 at least). 2883 */ 2884 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2885 if (m == NULL) { 2886 DPRINTF(sc, ATH_DEBUG_ANY, 2887 "%s: no mbuf/cluster\n", __func__); 2888 sc->sc_stats.ast_rx_nombuf++; 2889 return ENOMEM; 2890 } 2891 bf->bf_m = m; 2892 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2893 2894 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2895 bf->bf_dmamap, m, 2896 BUS_DMA_NOWAIT); 2897 if (error != 0) { 2898 DPRINTF(sc, ATH_DEBUG_ANY, 2899 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2900 __func__, error); 2901 sc->sc_stats.ast_rx_busdma++; 2902 return error; 2903 } 2904 KASSERTMSG(bf->bf_nseg == 1, 2905 "multi-segment packet; nseg %u", bf->bf_nseg); 2906 } 2907 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2908 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2909 2910 /* 2911 * Setup descriptors. For receive we always terminate 2912 * the descriptor list with a self-linked entry so we'll 2913 * not get overrun under high load (as can happen with a 2914 * 5212 when ANI processing enables PHY error frames). 2915 * 2916 * To insure the last descriptor is self-linked we create 2917 * each descriptor as self-linked and add it to the end. As 2918 * each additional descriptor is added the previous self-linked 2919 * entry is ``fixed'' naturally. This should be safe even 2920 * if DMA is happening. When processing RX interrupts we 2921 * never remove/process the last, self-linked, entry on the 2922 * descriptor list. This insures the hardware always has 2923 * someplace to write a new frame. 2924 */ 2925 ds = bf->bf_desc; 2926 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2927 ds->ds_data = bf->bf_segs[0].ds_addr; 2928 /* ds->ds_vdata = mtod(m, void *); for radar */ 2929 ath_hal_setuprxdesc(ah, ds 2930 , m->m_len /* buffer size */ 2931 , 0 2932 ); 2933 2934 if (sc->sc_rxlink != NULL) 2935 *sc->sc_rxlink = bf->bf_daddr; 2936 sc->sc_rxlink = &ds->ds_link; 2937 return 0; 2938 } 2939 2940 /* 2941 * Extend 15-bit time stamp from rx descriptor to 2942 * a full 64-bit TSF using the specified TSF. 2943 */ 2944 static inline u_int64_t 2945 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2946 { 2947 if ((tsf & 0x7fff) < rstamp) 2948 tsf -= 0x8000; 2949 return ((tsf &~ 0x7fff) | rstamp); 2950 } 2951 2952 /* 2953 * Intercept management frames to collect beacon rssi data 2954 * and to do ibss merges. 2955 */ 2956 static void 2957 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2958 struct ieee80211_node *ni, 2959 int subtype, int rssi, u_int32_t rstamp) 2960 { 2961 struct ath_softc *sc = ic->ic_ifp->if_softc; 2962 2963 /* 2964 * Call up first so subsequent work can use information 2965 * potentially stored in the node (e.g. for ibss merge). 2966 */ 2967 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2968 switch (subtype) { 2969 case IEEE80211_FC0_SUBTYPE_BEACON: 2970 /* update rssi statistics for use by the hal */ 2971 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2972 if (sc->sc_syncbeacon && 2973 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2974 /* 2975 * Resync beacon timers using the tsf of the beacon 2976 * frame we just received. 2977 */ 2978 ath_beacon_config(sc); 2979 } 2980 /* fall thru... */ 2981 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2982 if (ic->ic_opmode == IEEE80211_M_IBSS && 2983 ic->ic_state == IEEE80211_S_RUN) { 2984 u_int64_t tsf = ath_extend_tsf(rstamp, 2985 ath_hal_gettsf64(sc->sc_ah)); 2986 2987 /* 2988 * Handle ibss merge as needed; check the tsf on the 2989 * frame before attempting the merge. The 802.11 spec 2990 * says the station should change its bssid to match 2991 * the oldest station with the same ssid, where oldest 2992 * is determined by the tsf. Note that hardware 2993 * reconfiguration happens through callback to 2994 * ath_newstate as the state machine will go from 2995 * RUN -> RUN when this happens. 2996 */ 2997 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2998 DPRINTF(sc, ATH_DEBUG_STATE, 2999 "ibss merge, rstamp %u tsf %ju " 3000 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3001 (uintmax_t)ni->ni_tstamp.tsf); 3002 (void) ieee80211_ibss_merge(ni); 3003 } 3004 } 3005 break; 3006 } 3007 } 3008 3009 /* 3010 * Set the default antenna. 3011 */ 3012 static void 3013 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3014 { 3015 struct ath_hal *ah = sc->sc_ah; 3016 3017 /* XXX block beacon interrupts */ 3018 ath_hal_setdefantenna(ah, antenna); 3019 if (sc->sc_defant != antenna) 3020 sc->sc_stats.ast_ant_defswitch++; 3021 sc->sc_defant = antenna; 3022 sc->sc_rxotherant = 0; 3023 } 3024 3025 static void 3026 ath_handle_micerror(struct ieee80211com *ic, 3027 struct ieee80211_frame *wh, int keyix) 3028 { 3029 struct ieee80211_node *ni; 3030 3031 /* XXX recheck MIC to deal w/ chips that lie */ 3032 /* XXX discard MIC errors on !data frames */ 3033 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 3034 if (ni != NULL) { 3035 ieee80211_notify_michael_failure(ic, wh, keyix); 3036 ieee80211_free_node(ni); 3037 } 3038 } 3039 3040 static void 3041 ath_rx_proc(void *arg, int npending) 3042 { 3043 #define PA2DESC(_sc, _pa) \ 3044 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 3045 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3046 struct ath_softc *sc = arg; 3047 struct ath_buf *bf; 3048 struct ieee80211com *ic = &sc->sc_ic; 3049 struct ifnet *ifp = &sc->sc_if; 3050 struct ath_hal *ah = sc->sc_ah; 3051 struct ath_desc *ds; 3052 struct mbuf *m; 3053 struct ieee80211_node *ni; 3054 struct ath_node *an; 3055 int len, ngood, type; 3056 u_int phyerr; 3057 HAL_STATUS status; 3058 int16_t nf; 3059 u_int64_t tsf; 3060 uint8_t rxerr_tap, rxerr_mon; 3061 NET_LOCK_GIANT_FUNC_INIT(); 3062 3063 NET_LOCK_GIANT(); /* XXX */ 3064 3065 rxerr_tap = 3066 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 3067 3068 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 3069 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3070 else if (ifp->if_flags & IFF_PROMISC) 3071 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3072 3073 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3074 ngood = 0; 3075 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3076 tsf = ath_hal_gettsf64(ah); 3077 do { 3078 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3079 if (bf == NULL) { /* NB: shouldn't happen */ 3080 if_printf(ifp, "%s: no buffer!\n", __func__); 3081 break; 3082 } 3083 ds = bf->bf_desc; 3084 if (ds->ds_link == bf->bf_daddr) { 3085 /* NB: never process the self-linked entry at the end */ 3086 break; 3087 } 3088 m = bf->bf_m; 3089 if (m == NULL) { /* NB: shouldn't happen */ 3090 if_printf(ifp, "%s: no mbuf!\n", __func__); 3091 break; 3092 } 3093 /* XXX sync descriptor memory */ 3094 /* 3095 * Must provide the virtual address of the current 3096 * descriptor, the physical address, and the virtual 3097 * address of the next descriptor in the h/w chain. 3098 * This allows the HAL to look ahead to see if the 3099 * hardware is done with a descriptor by checking the 3100 * done bit in the following descriptor and the address 3101 * of the current descriptor the DMA engine is working 3102 * on. All this is necessary because of our use of 3103 * a self-linked list to avoid rx overruns. 3104 */ 3105 status = ath_hal_rxprocdesc(ah, ds, 3106 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 3107 &ds->ds_rxstat); 3108 #ifdef AR_DEBUG 3109 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3110 ath_printrxbuf(bf, status == HAL_OK); 3111 #endif 3112 if (status == HAL_EINPROGRESS) 3113 break; 3114 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3115 if (ds->ds_rxstat.rs_more) { 3116 /* 3117 * Frame spans multiple descriptors; this 3118 * cannot happen yet as we don't support 3119 * jumbograms. If not in monitor mode, 3120 * discard the frame. 3121 */ 3122 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3123 sc->sc_stats.ast_rx_toobig++; 3124 goto rx_next; 3125 } 3126 /* fall thru for monitor mode handling... */ 3127 } else if (ds->ds_rxstat.rs_status != 0) { 3128 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3129 sc->sc_stats.ast_rx_crcerr++; 3130 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3131 sc->sc_stats.ast_rx_fifoerr++; 3132 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3133 sc->sc_stats.ast_rx_phyerr++; 3134 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3135 sc->sc_stats.ast_rx_phy[phyerr]++; 3136 goto rx_next; 3137 } 3138 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3139 /* 3140 * Decrypt error. If the error occurred 3141 * because there was no hardware key, then 3142 * let the frame through so the upper layers 3143 * can process it. This is necessary for 5210 3144 * parts which have no way to setup a ``clear'' 3145 * key cache entry. 3146 * 3147 * XXX do key cache faulting 3148 */ 3149 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3150 goto rx_accept; 3151 sc->sc_stats.ast_rx_badcrypt++; 3152 } 3153 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3154 sc->sc_stats.ast_rx_badmic++; 3155 /* 3156 * Do minimal work required to hand off 3157 * the 802.11 header for notifcation. 3158 */ 3159 /* XXX frag's and qos frames */ 3160 len = ds->ds_rxstat.rs_datalen; 3161 if (len >= sizeof (struct ieee80211_frame)) { 3162 bus_dmamap_sync(sc->sc_dmat, 3163 bf->bf_dmamap, 3164 0, bf->bf_dmamap->dm_mapsize, 3165 BUS_DMASYNC_POSTREAD); 3166 ath_handle_micerror(ic, 3167 mtod(m, struct ieee80211_frame *), 3168 sc->sc_splitmic ? 3169 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3170 } 3171 } 3172 ifp->if_ierrors++; 3173 /* 3174 * Reject error frames, we normally don't want 3175 * to see them in monitor mode (in monitor mode 3176 * allow through packets that have crypto problems). 3177 */ 3178 3179 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3180 goto rx_next; 3181 } 3182 rx_accept: 3183 /* 3184 * Sync and unmap the frame. At this point we're 3185 * committed to passing the mbuf somewhere so clear 3186 * bf_m; this means a new sk_buff must be allocated 3187 * when the rx descriptor is setup again to receive 3188 * another frame. 3189 */ 3190 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3191 0, bf->bf_dmamap->dm_mapsize, 3192 BUS_DMASYNC_POSTREAD); 3193 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3194 bf->bf_m = NULL; 3195 3196 m_set_rcvif(m, ifp); 3197 len = ds->ds_rxstat.rs_datalen; 3198 m->m_pkthdr.len = m->m_len = len; 3199 3200 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3201 3202 if (sc->sc_drvbpf) { 3203 u_int8_t rix; 3204 3205 /* 3206 * Discard anything shorter than an ack or cts. 3207 */ 3208 if (len < IEEE80211_ACK_LEN) { 3209 DPRINTF(sc, ATH_DEBUG_RECV, 3210 "%s: runt packet %d\n", 3211 __func__, len); 3212 sc->sc_stats.ast_rx_tooshort++; 3213 m_freem(m); 3214 goto rx_next; 3215 } 3216 rix = ds->ds_rxstat.rs_rate; 3217 sc->sc_rx_th.wr_tsf = htole64( 3218 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3219 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3220 if (ds->ds_rxstat.rs_status & 3221 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3222 sc->sc_rx_th.wr_flags |= 3223 IEEE80211_RADIOTAP_F_BADFCS; 3224 } 3225 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3226 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3227 sc->sc_rx_th.wr_antnoise = nf; 3228 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3229 3230 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, 3231 sc->sc_rx_th_len, m, BPF_D_IN); 3232 } 3233 3234 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3235 m_freem(m); 3236 goto rx_next; 3237 } 3238 /* 3239 * From this point on we assume the frame is at least 3240 * as large as ieee80211_frame_min; verify that. 3241 */ 3242 if (len < IEEE80211_MIN_LEN) { 3243 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3244 __func__, len); 3245 sc->sc_stats.ast_rx_tooshort++; 3246 m_freem(m); 3247 goto rx_next; 3248 } 3249 3250 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3251 ieee80211_dump_pkt(mtod(m, void *), len, 3252 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3253 ds->ds_rxstat.rs_rssi); 3254 } 3255 3256 m_adj(m, -IEEE80211_CRC_LEN); 3257 3258 /* 3259 * Locate the node for sender, track state, and then 3260 * pass the (referenced) node up to the 802.11 layer 3261 * for its use. 3262 */ 3263 ni = ieee80211_find_rxnode_withkey(ic, 3264 mtod(m, const struct ieee80211_frame_min *), 3265 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3266 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3267 /* 3268 * Track rx rssi and do any rx antenna management. 3269 */ 3270 an = ATH_NODE(ni); 3271 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3272 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3273 /* 3274 * Send frame up for processing. 3275 */ 3276 type = ieee80211_input(ic, m, ni, 3277 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3278 ieee80211_free_node(ni); 3279 if (sc->sc_diversity) { 3280 /* 3281 * When using fast diversity, change the default rx 3282 * antenna if diversity chooses the other antenna 3 3283 * times in a row. 3284 */ 3285 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3286 if (++sc->sc_rxotherant >= 3) 3287 ath_setdefantenna(sc, 3288 ds->ds_rxstat.rs_antenna); 3289 } else 3290 sc->sc_rxotherant = 0; 3291 } 3292 if (sc->sc_softled) { 3293 /* 3294 * Blink for any data frame. Otherwise do a 3295 * heartbeat-style blink when idle. The latter 3296 * is mainly for station mode where we depend on 3297 * periodic beacon frames to trigger the poll event. 3298 */ 3299 if (type == IEEE80211_FC0_TYPE_DATA) { 3300 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3301 ath_led_event(sc, ATH_LED_RX); 3302 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3303 ath_led_event(sc, ATH_LED_POLL); 3304 } 3305 /* 3306 * Arrange to update the last rx timestamp only for 3307 * frames from our ap when operating in station mode. 3308 * This assumes the rx key is always setup when associated. 3309 */ 3310 if (ic->ic_opmode == IEEE80211_M_STA && 3311 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3312 ngood++; 3313 rx_next: 3314 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3315 } while (ath_rxbuf_init(sc, bf) == 0); 3316 3317 /* rx signal state monitoring */ 3318 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3319 #if 0 3320 if (ath_hal_radar_event(ah)) 3321 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3322 #endif 3323 if (ngood) 3324 sc->sc_lastrx = tsf; 3325 3326 #ifdef __NetBSD__ 3327 /* XXX Why isn't this necessary in FreeBSD? */ 3328 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3329 ath_start(ifp); 3330 #endif /* __NetBSD__ */ 3331 3332 NET_UNLOCK_GIANT(); /* XXX */ 3333 #undef PA2DESC 3334 } 3335 3336 /* 3337 * Setup a h/w transmit queue. 3338 */ 3339 static struct ath_txq * 3340 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3341 { 3342 #define N(a) (sizeof(a)/sizeof(a[0])) 3343 struct ath_hal *ah = sc->sc_ah; 3344 HAL_TXQ_INFO qi; 3345 int qnum; 3346 3347 memset(&qi, 0, sizeof(qi)); 3348 qi.tqi_subtype = subtype; 3349 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3350 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3351 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3352 /* 3353 * Enable interrupts only for EOL and DESC conditions. 3354 * We mark tx descriptors to receive a DESC interrupt 3355 * when a tx queue gets deep; otherwise waiting for the 3356 * EOL to reap descriptors. Note that this is done to 3357 * reduce interrupt load and this only defers reaping 3358 * descriptors, never transmitting frames. Aside from 3359 * reducing interrupts this also permits more concurrency. 3360 * The only potential downside is if the tx queue backs 3361 * up in which case the top half of the kernel may backup 3362 * due to a lack of tx descriptors. 3363 */ 3364 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3365 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3366 if (qnum == -1) { 3367 /* 3368 * NB: don't print a message, this happens 3369 * normally on parts with too few tx queues 3370 */ 3371 return NULL; 3372 } 3373 if (qnum >= N(sc->sc_txq)) { 3374 device_printf(sc->sc_dev, 3375 "hal qnum %u out of range, max %zu!\n", 3376 qnum, N(sc->sc_txq)); 3377 ath_hal_releasetxqueue(ah, qnum); 3378 return NULL; 3379 } 3380 if (!ATH_TXQ_SETUP(sc, qnum)) { 3381 struct ath_txq *txq = &sc->sc_txq[qnum]; 3382 3383 txq->axq_qnum = qnum; 3384 txq->axq_depth = 0; 3385 txq->axq_intrcnt = 0; 3386 txq->axq_link = NULL; 3387 STAILQ_INIT(&txq->axq_q); 3388 ATH_TXQ_LOCK_INIT(sc, txq); 3389 sc->sc_txqsetup |= 1<<qnum; 3390 } 3391 return &sc->sc_txq[qnum]; 3392 #undef N 3393 } 3394 3395 /* 3396 * Setup a hardware data transmit queue for the specified 3397 * access control. The hal may not support all requested 3398 * queues in which case it will return a reference to a 3399 * previously setup queue. We record the mapping from ac's 3400 * to h/w queues for use by ath_tx_start and also track 3401 * the set of h/w queues being used to optimize work in the 3402 * transmit interrupt handler and related routines. 3403 */ 3404 static int 3405 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3406 { 3407 #define N(a) (sizeof(a)/sizeof(a[0])) 3408 struct ath_txq *txq; 3409 3410 if (ac >= N(sc->sc_ac2q)) { 3411 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3412 ac, N(sc->sc_ac2q)); 3413 return 0; 3414 } 3415 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3416 if (txq != NULL) { 3417 sc->sc_ac2q[ac] = txq; 3418 return 1; 3419 } else 3420 return 0; 3421 #undef N 3422 } 3423 3424 /* 3425 * Update WME parameters for a transmit queue. 3426 */ 3427 static int 3428 ath_txq_update(struct ath_softc *sc, int ac) 3429 { 3430 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3431 #define ATH_TXOP_TO_US(v) (v<<5) 3432 struct ieee80211com *ic = &sc->sc_ic; 3433 struct ath_txq *txq = sc->sc_ac2q[ac]; 3434 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3435 struct ath_hal *ah = sc->sc_ah; 3436 HAL_TXQ_INFO qi; 3437 3438 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3439 qi.tqi_aifs = wmep->wmep_aifsn; 3440 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3441 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3442 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3443 3444 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3445 device_printf(sc->sc_dev, "unable to update hardware queue " 3446 "parameters for %s traffic!\n", 3447 ieee80211_wme_acnames[ac]); 3448 return 0; 3449 } else { 3450 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3451 return 1; 3452 } 3453 #undef ATH_TXOP_TO_US 3454 #undef ATH_EXPONENT_TO_VALUE 3455 } 3456 3457 /* 3458 * Callback from the 802.11 layer to update WME parameters. 3459 */ 3460 static int 3461 ath_wme_update(struct ieee80211com *ic) 3462 { 3463 struct ath_softc *sc = ic->ic_ifp->if_softc; 3464 3465 return !ath_txq_update(sc, WME_AC_BE) || 3466 !ath_txq_update(sc, WME_AC_BK) || 3467 !ath_txq_update(sc, WME_AC_VI) || 3468 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3469 } 3470 3471 /* 3472 * Reclaim resources for a setup queue. 3473 */ 3474 static void 3475 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3476 { 3477 3478 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3479 ATH_TXQ_LOCK_DESTROY(txq); 3480 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3481 } 3482 3483 /* 3484 * Reclaim all tx queue resources. 3485 */ 3486 static void 3487 ath_tx_cleanup(struct ath_softc *sc) 3488 { 3489 int i; 3490 3491 ATH_TXBUF_LOCK_DESTROY(sc); 3492 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3493 if (ATH_TXQ_SETUP(sc, i)) 3494 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3495 } 3496 3497 /* 3498 * Defragment an mbuf chain, returning at most maxfrags separate 3499 * mbufs+clusters. If this is not possible NULL is returned and 3500 * the original mbuf chain is left in its present (potentially 3501 * modified) state. We use two techniques: collapsing consecutive 3502 * mbufs and replacing consecutive mbufs by a cluster. 3503 */ 3504 static struct mbuf * 3505 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3506 { 3507 struct mbuf *m, *n, *n2, **prev; 3508 u_int curfrags; 3509 3510 /* 3511 * Calculate the current number of frags. 3512 */ 3513 curfrags = 0; 3514 for (m = m0; m != NULL; m = m->m_next) 3515 curfrags++; 3516 /* 3517 * First, try to collapse mbufs. Note that we always collapse 3518 * towards the front so we don't need to deal with moving the 3519 * pkthdr. This may be suboptimal if the first mbuf has much 3520 * less data than the following. 3521 */ 3522 m = m0; 3523 again: 3524 for (;;) { 3525 n = m->m_next; 3526 if (n == NULL) 3527 break; 3528 if (n->m_len < M_TRAILINGSPACE(m)) { 3529 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3530 n->m_len); 3531 m->m_len += n->m_len; 3532 m->m_next = n->m_next; 3533 m_free(n); 3534 if (--curfrags <= maxfrags) 3535 return m0; 3536 } else 3537 m = n; 3538 } 3539 KASSERTMSG(maxfrags > 1, 3540 "maxfrags %u, but normal collapse failed", maxfrags); 3541 /* 3542 * Collapse consecutive mbufs to a cluster. 3543 */ 3544 prev = &m0->m_next; /* NB: not the first mbuf */ 3545 while ((n = *prev) != NULL) { 3546 if ((n2 = n->m_next) != NULL && 3547 n->m_len + n2->m_len < MCLBYTES) { 3548 m = m_getcl(how, MT_DATA, 0); 3549 if (m == NULL) 3550 goto bad; 3551 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3552 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3553 n2->m_len); 3554 m->m_len = n->m_len + n2->m_len; 3555 m->m_next = n2->m_next; 3556 *prev = m; 3557 m_free(n); 3558 m_free(n2); 3559 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3560 return m0; 3561 /* 3562 * Still not there, try the normal collapse 3563 * again before we allocate another cluster. 3564 */ 3565 goto again; 3566 } 3567 prev = &n->m_next; 3568 } 3569 /* 3570 * No place where we can collapse to a cluster; punt. 3571 * This can occur if, for example, you request 2 frags 3572 * but the packet requires that both be clusters (we 3573 * never reallocate the first mbuf to avoid moving the 3574 * packet header). 3575 */ 3576 bad: 3577 return NULL; 3578 } 3579 3580 /* 3581 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3582 */ 3583 static int 3584 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3585 { 3586 int i; 3587 3588 for (i = 0; i < rt->rateCount; i++) 3589 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3590 return i; 3591 return 0; /* NB: lowest rate */ 3592 } 3593 3594 static void 3595 ath_freetx(struct mbuf *m) 3596 { 3597 struct mbuf *next; 3598 3599 do { 3600 next = m->m_nextpkt; 3601 m->m_nextpkt = NULL; 3602 m_freem(m); 3603 } while ((m = next) != NULL); 3604 } 3605 3606 static int 3607 deduct_pad_bytes(int len, int hdrlen) 3608 { 3609 /* XXX I am suspicious that this code, which I extracted 3610 * XXX from ath_tx_start() for reuse, does the right thing. 3611 */ 3612 return len - (hdrlen & 3); 3613 } 3614 3615 static int 3616 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3617 struct mbuf *m0) 3618 { 3619 struct ieee80211com *ic = &sc->sc_ic; 3620 struct ath_hal *ah = sc->sc_ah; 3621 struct ifnet *ifp = &sc->sc_if; 3622 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3623 int i, error, iswep, ismcast, isfrag, ismrr; 3624 int keyix, hdrlen, pktlen, try0; 3625 u_int8_t rix, txrate, ctsrate; 3626 u_int8_t cix = 0xff; /* NB: silence compiler */ 3627 struct ath_desc *ds, *ds0; 3628 struct ath_txq *txq; 3629 struct ieee80211_frame *wh; 3630 u_int subtype, flags, ctsduration; 3631 HAL_PKT_TYPE atype; 3632 const HAL_RATE_TABLE *rt; 3633 HAL_BOOL shortPreamble; 3634 struct ath_node *an; 3635 struct mbuf *m; 3636 u_int pri; 3637 3638 wh = mtod(m0, struct ieee80211_frame *); 3639 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3640 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3641 isfrag = m0->m_flags & M_FRAG; 3642 hdrlen = ieee80211_anyhdrsize(wh); 3643 /* 3644 * Packet length must not include any 3645 * pad bytes; deduct them here. 3646 */ 3647 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3648 3649 if (iswep) { 3650 const struct ieee80211_cipher *cip; 3651 struct ieee80211_key *k; 3652 3653 /* 3654 * Construct the 802.11 header+trailer for an encrypted 3655 * frame. The only reason this can fail is because of an 3656 * unknown or unsupported cipher/key type. 3657 */ 3658 k = ieee80211_crypto_encap(ic, ni, m0); 3659 if (k == NULL) { 3660 /* 3661 * This can happen when the key is yanked after the 3662 * frame was queued. Just discard the frame; the 3663 * 802.11 layer counts failures and provides 3664 * debugging/diagnostics. 3665 */ 3666 ath_freetx(m0); 3667 return EIO; 3668 } 3669 /* 3670 * Adjust the packet + header lengths for the crypto 3671 * additions and calculate the h/w key index. When 3672 * a s/w mic is done the frame will have had any mic 3673 * added to it prior to entry so m0->m_pkthdr.len above will 3674 * account for it. Otherwise we need to add it to the 3675 * packet length. 3676 */ 3677 cip = k->wk_cipher; 3678 hdrlen += cip->ic_header; 3679 pktlen += cip->ic_header + cip->ic_trailer; 3680 /* NB: frags always have any TKIP MIC done in s/w */ 3681 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3682 pktlen += cip->ic_miclen; 3683 keyix = k->wk_keyix; 3684 3685 /* packet header may have moved, reset our local pointer */ 3686 wh = mtod(m0, struct ieee80211_frame *); 3687 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3688 /* 3689 * Use station key cache slot, if assigned. 3690 */ 3691 keyix = ni->ni_ucastkey.wk_keyix; 3692 if (keyix == IEEE80211_KEYIX_NONE) 3693 keyix = HAL_TXKEYIX_INVALID; 3694 } else 3695 keyix = HAL_TXKEYIX_INVALID; 3696 3697 pktlen += IEEE80211_CRC_LEN; 3698 3699 /* 3700 * Load the DMA map so any coalescing is done. This 3701 * also calculates the number of descriptors we need. 3702 */ 3703 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3704 BUS_DMA_NOWAIT); 3705 if (error == EFBIG) { 3706 /* XXX packet requires too many descriptors */ 3707 bf->bf_nseg = ATH_TXDESC+1; 3708 } else if (error != 0) { 3709 sc->sc_stats.ast_tx_busdma++; 3710 ath_freetx(m0); 3711 return error; 3712 } 3713 /* 3714 * Discard null packets and check for packets that 3715 * require too many TX descriptors. We try to convert 3716 * the latter to a cluster. 3717 */ 3718 if (error == EFBIG) { /* too many desc's, linearize */ 3719 sc->sc_stats.ast_tx_linear++; 3720 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3721 if (m == NULL) { 3722 ath_freetx(m0); 3723 sc->sc_stats.ast_tx_nombuf++; 3724 return ENOMEM; 3725 } 3726 m0 = m; 3727 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3728 BUS_DMA_NOWAIT); 3729 if (error != 0) { 3730 sc->sc_stats.ast_tx_busdma++; 3731 ath_freetx(m0); 3732 return error; 3733 } 3734 KASSERTMSG(bf->bf_nseg <= ATH_TXDESC, 3735 "too many segments after defrag; nseg %u", bf->bf_nseg); 3736 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3737 sc->sc_stats.ast_tx_nodata++; 3738 ath_freetx(m0); 3739 return EIO; 3740 } 3741 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3742 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3743 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3744 bf->bf_m = m0; 3745 bf->bf_node = ni; /* NB: held reference */ 3746 3747 /* setup descriptors */ 3748 ds = bf->bf_desc; 3749 rt = sc->sc_currates; 3750 KASSERTMSG(rt != NULL, "no rate table, mode %u", sc->sc_curmode); 3751 3752 /* 3753 * NB: the 802.11 layer marks whether or not we should 3754 * use short preamble based on the current mode and 3755 * negotiated parameters. 3756 */ 3757 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3758 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3759 shortPreamble = AH_TRUE; 3760 sc->sc_stats.ast_tx_shortpre++; 3761 } else { 3762 shortPreamble = AH_FALSE; 3763 } 3764 3765 an = ATH_NODE(ni); 3766 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3767 ismrr = 0; /* default no multi-rate retry*/ 3768 /* 3769 * Calculate Atheros packet type from IEEE80211 packet header, 3770 * setup for rate calculations, and select h/w transmit queue. 3771 */ 3772 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3773 case IEEE80211_FC0_TYPE_MGT: 3774 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3775 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3776 atype = HAL_PKT_TYPE_BEACON; 3777 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3778 atype = HAL_PKT_TYPE_PROBE_RESP; 3779 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3780 atype = HAL_PKT_TYPE_ATIM; 3781 else 3782 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3783 rix = sc->sc_minrateix; 3784 txrate = rt->info[rix].rateCode; 3785 if (shortPreamble) 3786 txrate |= rt->info[rix].shortPreamble; 3787 try0 = ATH_TXMGTTRY; 3788 /* NB: force all management frames to highest queue */ 3789 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3790 /* NB: force all management frames to highest queue */ 3791 pri = WME_AC_VO; 3792 } else 3793 pri = WME_AC_BE; 3794 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3795 break; 3796 case IEEE80211_FC0_TYPE_CTL: 3797 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3798 rix = sc->sc_minrateix; 3799 txrate = rt->info[rix].rateCode; 3800 if (shortPreamble) 3801 txrate |= rt->info[rix].shortPreamble; 3802 try0 = ATH_TXMGTTRY; 3803 /* NB: force all ctl frames to highest queue */ 3804 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3805 /* NB: force all ctl frames to highest queue */ 3806 pri = WME_AC_VO; 3807 } else 3808 pri = WME_AC_BE; 3809 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3810 break; 3811 case IEEE80211_FC0_TYPE_DATA: 3812 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3813 /* 3814 * Data frames: multicast frames go out at a fixed rate, 3815 * otherwise consult the rate control module for the 3816 * rate to use. 3817 */ 3818 if (ismcast) { 3819 /* 3820 * Check mcast rate setting in case it's changed. 3821 * XXX move out of fastpath 3822 */ 3823 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3824 sc->sc_mcastrix = 3825 ath_tx_findrix(rt, ic->ic_mcast_rate); 3826 sc->sc_mcastrate = ic->ic_mcast_rate; 3827 } 3828 rix = sc->sc_mcastrix; 3829 txrate = rt->info[rix].rateCode; 3830 try0 = 1; 3831 } else { 3832 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3833 &rix, &try0, &txrate); 3834 sc->sc_txrate = txrate; /* for LED blinking */ 3835 if (try0 != ATH_TXMAXTRY) 3836 ismrr = 1; 3837 } 3838 pri = M_WME_GETAC(m0); 3839 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3840 flags |= HAL_TXDESC_NOACK; 3841 break; 3842 default: 3843 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3844 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3845 /* XXX statistic */ 3846 ath_freetx(m0); 3847 return EIO; 3848 } 3849 txq = sc->sc_ac2q[pri]; 3850 3851 /* 3852 * When servicing one or more stations in power-save mode 3853 * multicast frames must be buffered until after the beacon. 3854 * We use the CAB queue for that. 3855 */ 3856 if (ismcast && ic->ic_ps_sta) { 3857 txq = sc->sc_cabq; 3858 /* XXX? more bit in 802.11 frame header */ 3859 } 3860 3861 /* 3862 * Calculate miscellaneous flags. 3863 */ 3864 if (ismcast) { 3865 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3866 } else if (pktlen > ic->ic_rtsthreshold) { 3867 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3868 cix = rt->info[rix].controlRate; 3869 sc->sc_stats.ast_tx_rts++; 3870 } 3871 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3872 sc->sc_stats.ast_tx_noack++; 3873 3874 /* 3875 * If 802.11g protection is enabled, determine whether 3876 * to use RTS/CTS or just CTS. Note that this is only 3877 * done for OFDM unicast frames. 3878 */ 3879 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3880 rt->info[rix].phy == IEEE80211_T_OFDM && 3881 (flags & HAL_TXDESC_NOACK) == 0) { 3882 /* XXX fragments must use CCK rates w/ protection */ 3883 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3884 flags |= HAL_TXDESC_RTSENA; 3885 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3886 flags |= HAL_TXDESC_CTSENA; 3887 if (isfrag) { 3888 /* 3889 * For frags it would be desirable to use the 3890 * highest CCK rate for RTS/CTS. But stations 3891 * farther away may detect it at a lower CCK rate 3892 * so use the configured protection rate instead 3893 * (for now). 3894 */ 3895 cix = rt->info[sc->sc_protrix].controlRate; 3896 } else 3897 cix = rt->info[sc->sc_protrix].controlRate; 3898 sc->sc_stats.ast_tx_protect++; 3899 } 3900 3901 /* 3902 * Calculate duration. This logically belongs in the 802.11 3903 * layer but it lacks sufficient information to calculate it. 3904 */ 3905 if ((flags & HAL_TXDESC_NOACK) == 0 && 3906 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3907 u_int16_t dur; 3908 /* 3909 * XXX not right with fragmentation. 3910 */ 3911 if (shortPreamble) 3912 dur = rt->info[rix].spAckDuration; 3913 else 3914 dur = rt->info[rix].lpAckDuration; 3915 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3916 dur += dur; /* additional SIFS+ACK */ 3917 KASSERTMSG(m0->m_nextpkt != NULL, "no fragment"); 3918 /* 3919 * Include the size of next fragment so NAV is 3920 * updated properly. The last fragment uses only 3921 * the ACK duration 3922 */ 3923 dur += ath_hal_computetxtime(ah, rt, 3924 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3925 hdrlen) - 3926 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3927 rix, shortPreamble); 3928 } 3929 if (isfrag) { 3930 /* 3931 * Force hardware to use computed duration for next 3932 * fragment by disabling multi-rate retry which updates 3933 * duration based on the multi-rate duration table. 3934 */ 3935 try0 = ATH_TXMAXTRY; 3936 } 3937 *(u_int16_t *)wh->i_dur = htole16(dur); 3938 } 3939 3940 /* 3941 * Calculate RTS/CTS rate and duration if needed. 3942 */ 3943 ctsduration = 0; 3944 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3945 /* 3946 * CTS transmit rate is derived from the transmit rate 3947 * by looking in the h/w rate table. We must also factor 3948 * in whether or not a short preamble is to be used. 3949 */ 3950 /* NB: cix is set above where RTS/CTS is enabled */ 3951 KASSERTMSG(cix != 0xff, "cix not setup"); 3952 ctsrate = rt->info[cix].rateCode; 3953 /* 3954 * Compute the transmit duration based on the frame 3955 * size and the size of an ACK frame. We call into the 3956 * HAL to do the computation since it depends on the 3957 * characteristics of the actual PHY being used. 3958 * 3959 * NB: CTS is assumed the same size as an ACK so we can 3960 * use the precalculated ACK durations. 3961 */ 3962 if (shortPreamble) { 3963 ctsrate |= rt->info[cix].shortPreamble; 3964 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3965 ctsduration += rt->info[cix].spAckDuration; 3966 ctsduration += ath_hal_computetxtime(ah, 3967 rt, pktlen, rix, AH_TRUE); 3968 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3969 ctsduration += rt->info[rix].spAckDuration; 3970 } else { 3971 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3972 ctsduration += rt->info[cix].lpAckDuration; 3973 ctsduration += ath_hal_computetxtime(ah, 3974 rt, pktlen, rix, AH_FALSE); 3975 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3976 ctsduration += rt->info[rix].lpAckDuration; 3977 } 3978 /* 3979 * Must disable multi-rate retry when using RTS/CTS. 3980 */ 3981 ismrr = 0; 3982 try0 = ATH_TXMGTTRY; /* XXX */ 3983 } else 3984 ctsrate = 0; 3985 3986 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3987 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3988 sc->sc_hwmap[txrate].ieeerate, -1); 3989 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3990 if (sc->sc_drvbpf) { 3991 u_int64_t tsf = ath_hal_gettsf64(ah); 3992 3993 sc->sc_tx_th.wt_tsf = htole64(tsf); 3994 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3995 if (iswep) 3996 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3997 if (isfrag) 3998 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3999 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 4000 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4001 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4002 4003 bpf_mtap2(sc->sc_drvbpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0, 4004 BPF_D_OUT); 4005 } 4006 4007 /* 4008 * Determine if a tx interrupt should be generated for 4009 * this descriptor. We take a tx interrupt to reap 4010 * descriptors when the h/w hits an EOL condition or 4011 * when the descriptor is specifically marked to generate 4012 * an interrupt. We periodically mark descriptors in this 4013 * way to insure timely replenishing of the supply needed 4014 * for sending frames. Defering interrupts reduces system 4015 * load and potentially allows more concurrent work to be 4016 * done but if done to aggressively can cause senders to 4017 * backup. 4018 * 4019 * NB: use >= to deal with sc_txintrperiod changing 4020 * dynamically through sysctl. 4021 */ 4022 if (flags & HAL_TXDESC_INTREQ) { 4023 txq->axq_intrcnt = 0; 4024 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4025 flags |= HAL_TXDESC_INTREQ; 4026 txq->axq_intrcnt = 0; 4027 } 4028 4029 /* 4030 * Formulate first tx descriptor with tx controls. 4031 */ 4032 /* XXX check return value? */ 4033 ath_hal_setuptxdesc(ah, ds 4034 , pktlen /* packet length */ 4035 , hdrlen /* header length */ 4036 , atype /* Atheros packet type */ 4037 , ni->ni_txpower /* txpower */ 4038 , txrate, try0 /* series 0 rate/tries */ 4039 , keyix /* key cache index */ 4040 , sc->sc_txantenna /* antenna mode */ 4041 , flags /* flags */ 4042 , ctsrate /* rts/cts rate */ 4043 , ctsduration /* rts/cts duration */ 4044 ); 4045 bf->bf_flags = flags; 4046 /* 4047 * Setup the multi-rate retry state only when we're 4048 * going to use it. This assumes ath_hal_setuptxdesc 4049 * initializes the descriptors (so we don't have to) 4050 * when the hardware supports multi-rate retry and 4051 * we don't use it. 4052 */ 4053 if (ismrr) 4054 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4055 4056 /* 4057 * Fillin the remainder of the descriptor info. 4058 */ 4059 ds0 = ds; 4060 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4061 ds->ds_data = bf->bf_segs[i].ds_addr; 4062 if (i == bf->bf_nseg - 1) 4063 ds->ds_link = 0; 4064 else 4065 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4066 ath_hal_filltxdesc(ah, ds 4067 , bf->bf_segs[i].ds_len /* segment length */ 4068 , i == 0 /* first segment */ 4069 , i == bf->bf_nseg - 1 /* last segment */ 4070 , ds0 /* first descriptor */ 4071 ); 4072 4073 /* NB: The desc swap function becomes void, 4074 * if descriptor swapping is not enabled 4075 */ 4076 ath_desc_swap(ds); 4077 4078 DPRINTF(sc, ATH_DEBUG_XMIT, 4079 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4080 __func__, i, ds->ds_link, ds->ds_data, 4081 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4082 } 4083 /* 4084 * Insert the frame on the outbound list and 4085 * pass it on to the hardware. 4086 */ 4087 ATH_TXQ_LOCK(txq); 4088 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4089 if (txq->axq_link == NULL) { 4090 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4091 DPRINTF(sc, ATH_DEBUG_XMIT, 4092 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 4093 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 4094 txq->axq_depth); 4095 } else { 4096 *txq->axq_link = HTOAH32(bf->bf_daddr); 4097 DPRINTF(sc, ATH_DEBUG_XMIT, 4098 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 4099 __func__, txq->axq_qnum, txq->axq_link, 4100 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4101 } 4102 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4103 /* 4104 * The CAB queue is started from the SWBA handler since 4105 * frames only go out on DTIM and to avoid possible races. 4106 */ 4107 if (txq != sc->sc_cabq) 4108 ath_hal_txstart(ah, txq->axq_qnum); 4109 ATH_TXQ_UNLOCK(txq); 4110 4111 return 0; 4112 } 4113 4114 /* 4115 * Process completed xmit descriptors from the specified queue. 4116 */ 4117 static int 4118 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4119 { 4120 struct ath_hal *ah = sc->sc_ah; 4121 struct ieee80211com *ic = &sc->sc_ic; 4122 struct ath_buf *bf; 4123 struct ath_desc *ds, *ds0; 4124 struct ieee80211_node *ni; 4125 struct ath_node *an; 4126 int sr, lr, pri, nacked; 4127 HAL_STATUS status; 4128 4129 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4130 __func__, txq->axq_qnum, 4131 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4132 txq->axq_link); 4133 nacked = 0; 4134 for (;;) { 4135 ATH_TXQ_LOCK(txq); 4136 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4137 bf = STAILQ_FIRST(&txq->axq_q); 4138 if (bf == NULL) { 4139 txq->axq_link = NULL; 4140 ATH_TXQ_UNLOCK(txq); 4141 break; 4142 } 4143 ds0 = &bf->bf_desc[0]; 4144 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4145 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4146 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4147 ath_printtxbuf(bf, status == HAL_OK); 4148 if (status == HAL_EINPROGRESS) { 4149 ATH_TXQ_UNLOCK(txq); 4150 break; 4151 } 4152 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4153 ATH_TXQ_UNLOCK(txq); 4154 4155 ni = bf->bf_node; 4156 if (ni != NULL) { 4157 an = ATH_NODE(ni); 4158 if (ds->ds_txstat.ts_status == 0) { 4159 u_int8_t txant = ds->ds_txstat.ts_antenna; 4160 sc->sc_stats.ast_ant_tx[txant]++; 4161 sc->sc_ant_tx[txant]++; 4162 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4163 sc->sc_stats.ast_tx_altrate++; 4164 sc->sc_stats.ast_tx_rssi = 4165 ds->ds_txstat.ts_rssi; 4166 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4167 ds->ds_txstat.ts_rssi); 4168 pri = M_WME_GETAC(bf->bf_m); 4169 if (pri >= WME_AC_VO) 4170 ic->ic_wme.wme_hipri_traffic++; 4171 ni->ni_inact = ni->ni_inact_reload; 4172 } else { 4173 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4174 sc->sc_stats.ast_tx_xretries++; 4175 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4176 sc->sc_stats.ast_tx_fifoerr++; 4177 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4178 sc->sc_stats.ast_tx_filtered++; 4179 } 4180 sr = ds->ds_txstat.ts_shortretry; 4181 lr = ds->ds_txstat.ts_longretry; 4182 sc->sc_stats.ast_tx_shortretry += sr; 4183 sc->sc_stats.ast_tx_longretry += lr; 4184 /* 4185 * Hand the descriptor to the rate control algorithm. 4186 */ 4187 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4188 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4189 /* 4190 * If frame was ack'd update the last rx time 4191 * used to workaround phantom bmiss interrupts. 4192 */ 4193 if (ds->ds_txstat.ts_status == 0) 4194 nacked++; 4195 ath_rate_tx_complete(sc, an, ds, ds0); 4196 } 4197 /* 4198 * Reclaim reference to node. 4199 * 4200 * NB: the node may be reclaimed here if, for example 4201 * this is a DEAUTH message that was sent and the 4202 * node was timed out due to inactivity. 4203 */ 4204 ieee80211_free_node(ni); 4205 } 4206 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4207 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4208 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4209 m_freem(bf->bf_m); 4210 bf->bf_m = NULL; 4211 bf->bf_node = NULL; 4212 4213 ATH_TXBUF_LOCK(sc); 4214 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4215 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4216 ATH_TXBUF_UNLOCK(sc); 4217 } 4218 return nacked; 4219 } 4220 4221 static inline int 4222 txqactive(struct ath_hal *ah, int qnum) 4223 { 4224 u_int32_t txqs = 1<<qnum; 4225 ath_hal_gettxintrtxqs(ah, &txqs); 4226 return (txqs & (1<<qnum)); 4227 } 4228 4229 /* 4230 * Deferred processing of transmit interrupt; special-cased 4231 * for a single hardware transmit queue (e.g. 5210 and 5211). 4232 */ 4233 static void 4234 ath_tx_proc_q0(void *arg, int npending) 4235 { 4236 struct ath_softc *sc = arg; 4237 struct ifnet *ifp = &sc->sc_if; 4238 #ifdef __NetBSD__ 4239 int s; 4240 #endif 4241 4242 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0) 4243 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4244 4245 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4246 ath_tx_processq(sc, sc->sc_cabq); 4247 4248 if (sc->sc_softled) 4249 ath_led_event(sc, ATH_LED_TX); 4250 4251 #ifdef __NetBSD__ 4252 s = splnet(); 4253 #endif 4254 ath_start(ifp); 4255 #ifdef __NetBSD__ 4256 splx(s); 4257 #endif 4258 } 4259 4260 /* 4261 * Deferred processing of transmit interrupt; special-cased 4262 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4263 */ 4264 static void 4265 ath_tx_proc_q0123(void *arg, int npending) 4266 { 4267 struct ath_softc *sc = arg; 4268 struct ifnet *ifp = &sc->sc_if; 4269 int nacked; 4270 #ifdef __NetBSD__ 4271 int s; 4272 #endif 4273 4274 /* 4275 * Process each active queue. 4276 */ 4277 nacked = 0; 4278 if (txqactive(sc->sc_ah, 0)) 4279 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4280 if (txqactive(sc->sc_ah, 1)) 4281 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4282 if (txqactive(sc->sc_ah, 2)) 4283 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4284 if (txqactive(sc->sc_ah, 3)) 4285 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4286 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4287 ath_tx_processq(sc, sc->sc_cabq); 4288 if (nacked) { 4289 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4290 } 4291 4292 if (sc->sc_softled) 4293 ath_led_event(sc, ATH_LED_TX); 4294 4295 #ifdef __NetBSD__ 4296 s = splnet(); 4297 #endif 4298 ath_start(ifp); 4299 #ifdef __NetBSD__ 4300 splx(s); 4301 #endif 4302 } 4303 4304 /* 4305 * Deferred processing of transmit interrupt. 4306 */ 4307 static void 4308 ath_tx_proc(void *arg, int npending) 4309 { 4310 struct ath_softc *sc = arg; 4311 struct ifnet *ifp = &sc->sc_if; 4312 int i, nacked; 4313 #ifdef __NetBSD__ 4314 int s; 4315 #endif 4316 4317 /* 4318 * Process each active queue. 4319 */ 4320 nacked = 0; 4321 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4322 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4323 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4324 if (nacked) { 4325 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4326 } 4327 4328 if (sc->sc_softled) 4329 ath_led_event(sc, ATH_LED_TX); 4330 4331 #ifdef __NetBSD__ 4332 s = splnet(); 4333 #endif 4334 ath_start(ifp); 4335 #ifdef __NetBSD__ 4336 splx(s); 4337 #endif 4338 } 4339 4340 static void 4341 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4342 { 4343 struct ath_hal *ah = sc->sc_ah; 4344 struct ieee80211_node *ni; 4345 struct ath_buf *bf; 4346 struct ath_desc *ds; 4347 4348 /* 4349 * NB: this assumes output has been stopped and 4350 * we do not need to block ath_tx_tasklet 4351 */ 4352 for (;;) { 4353 ATH_TXQ_LOCK(txq); 4354 bf = STAILQ_FIRST(&txq->axq_q); 4355 if (bf == NULL) { 4356 txq->axq_link = NULL; 4357 ATH_TXQ_UNLOCK(txq); 4358 break; 4359 } 4360 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4361 ATH_TXQ_UNLOCK(txq); 4362 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4363 if (sc->sc_debug & ATH_DEBUG_RESET) 4364 ath_printtxbuf(bf, 4365 ath_hal_txprocdesc(ah, bf->bf_desc, 4366 &ds->ds_txstat) == HAL_OK); 4367 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4368 m_freem(bf->bf_m); 4369 bf->bf_m = NULL; 4370 ni = bf->bf_node; 4371 bf->bf_node = NULL; 4372 if (ni != NULL) { 4373 /* 4374 * Reclaim node reference. 4375 */ 4376 ieee80211_free_node(ni); 4377 } 4378 ATH_TXBUF_LOCK(sc); 4379 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4380 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4381 ATH_TXBUF_UNLOCK(sc); 4382 } 4383 } 4384 4385 static void 4386 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4387 { 4388 struct ath_hal *ah = sc->sc_ah; 4389 4390 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4391 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4392 __func__, txq->axq_qnum, 4393 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4394 txq->axq_link); 4395 } 4396 4397 /* 4398 * Drain the transmit queues and reclaim resources. 4399 */ 4400 static void 4401 ath_draintxq(struct ath_softc *sc) 4402 { 4403 struct ath_hal *ah = sc->sc_ah; 4404 int i; 4405 4406 /* XXX return value */ 4407 if (device_is_active(sc->sc_dev)) { 4408 /* don't touch the hardware if marked invalid */ 4409 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4410 DPRINTF(sc, ATH_DEBUG_RESET, 4411 "%s: beacon queue %p\n", __func__, 4412 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4413 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4414 if (ATH_TXQ_SETUP(sc, i)) 4415 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4416 } 4417 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4418 if (ATH_TXQ_SETUP(sc, i)) 4419 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4420 } 4421 4422 /* 4423 * Disable the receive h/w in preparation for a reset. 4424 */ 4425 static void 4426 ath_stoprecv(struct ath_softc *sc) 4427 { 4428 #define PA2DESC(_sc, _pa) \ 4429 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4430 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4431 struct ath_hal *ah = sc->sc_ah; 4432 4433 ath_hal_stoppcurecv(ah); /* disable PCU */ 4434 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4435 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4436 DELAY(3000); /* 3ms is long enough for 1 frame */ 4437 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4438 struct ath_buf *bf; 4439 4440 printf("%s: rx queue %p, link %p\n", __func__, 4441 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4442 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4443 struct ath_desc *ds = bf->bf_desc; 4444 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4445 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4446 &ds->ds_rxstat); 4447 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4448 ath_printrxbuf(bf, status == HAL_OK); 4449 } 4450 } 4451 sc->sc_rxlink = NULL; /* just in case */ 4452 #undef PA2DESC 4453 } 4454 4455 /* 4456 * Enable the receive h/w following a reset. 4457 */ 4458 static int 4459 ath_startrecv(struct ath_softc *sc) 4460 { 4461 struct ath_hal *ah = sc->sc_ah; 4462 struct ath_buf *bf; 4463 4464 sc->sc_rxlink = NULL; 4465 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4466 int error = ath_rxbuf_init(sc, bf); 4467 if (error != 0) { 4468 DPRINTF(sc, ATH_DEBUG_RECV, 4469 "%s: ath_rxbuf_init failed %d\n", 4470 __func__, error); 4471 return error; 4472 } 4473 } 4474 4475 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4476 ath_hal_putrxbuf(ah, bf->bf_daddr); 4477 ath_hal_rxena(ah); /* enable recv descriptors */ 4478 ath_mode_init(sc); /* set filters, etc. */ 4479 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4480 return 0; 4481 } 4482 4483 /* 4484 * Update internal state after a channel change. 4485 */ 4486 static void 4487 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4488 { 4489 struct ieee80211com *ic = &sc->sc_ic; 4490 enum ieee80211_phymode mode; 4491 u_int16_t flags; 4492 4493 /* 4494 * Change channels and update the h/w rate map 4495 * if we're switching; e.g. 11a to 11b/g. 4496 */ 4497 mode = ieee80211_chan2mode(ic, chan); 4498 if (mode != sc->sc_curmode) 4499 ath_setcurmode(sc, mode); 4500 /* 4501 * Update BPF state. NB: ethereal et. al. don't handle 4502 * merged flags well so pick a unique mode for their use. 4503 */ 4504 if (IEEE80211_IS_CHAN_A(chan)) 4505 flags = IEEE80211_CHAN_A; 4506 /* XXX 11g schizophrenia */ 4507 else if (IEEE80211_IS_CHAN_G(chan) || 4508 IEEE80211_IS_CHAN_PUREG(chan)) 4509 flags = IEEE80211_CHAN_G; 4510 else 4511 flags = IEEE80211_CHAN_B; 4512 if (IEEE80211_IS_CHAN_T(chan)) 4513 flags |= IEEE80211_CHAN_TURBO; 4514 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4515 htole16(chan->ic_freq); 4516 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4517 htole16(flags); 4518 } 4519 4520 #if 0 4521 /* 4522 * Poll for a channel clear indication; this is required 4523 * for channels requiring DFS and not previously visited 4524 * and/or with a recent radar detection. 4525 */ 4526 static void 4527 ath_dfswait(void *arg) 4528 { 4529 struct ath_softc *sc = arg; 4530 struct ath_hal *ah = sc->sc_ah; 4531 HAL_CHANNEL hchan; 4532 4533 ath_hal_radar_wait(ah, &hchan); 4534 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4535 if_printf(&sc->sc_if, 4536 "channel %u/0x%x/0x%x has interference\n", 4537 hchan.channel, hchan.channelFlags, hchan.privFlags); 4538 return; 4539 } 4540 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4541 /* XXX should not happen */ 4542 return; 4543 } 4544 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4545 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4546 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4547 if_printf(&sc->sc_if, 4548 "channel %u/0x%x/0x%x marked clear\n", 4549 hchan.channel, hchan.channelFlags, hchan.privFlags); 4550 } else 4551 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4552 } 4553 #endif 4554 4555 /* 4556 * Set/change channels. If the channel is really being changed, 4557 * it's done by reseting the chip. To accomplish this we must 4558 * first cleanup any pending DMA, then restart stuff after a la 4559 * ath_init. 4560 */ 4561 static int 4562 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4563 { 4564 struct ath_hal *ah = sc->sc_ah; 4565 struct ieee80211com *ic = &sc->sc_ic; 4566 HAL_CHANNEL hchan; 4567 4568 /* 4569 * Convert to a HAL channel description with 4570 * the flags constrained to reflect the current 4571 * operating mode. 4572 */ 4573 hchan.channel = chan->ic_freq; 4574 hchan.channelFlags = ath_chan2flags(ic, chan); 4575 4576 DPRINTF(sc, ATH_DEBUG_RESET, 4577 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4578 __func__, 4579 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4580 sc->sc_curchan.channelFlags), 4581 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4582 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4583 hchan.channel, hchan.channelFlags); 4584 if (hchan.channel != sc->sc_curchan.channel || 4585 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4586 HAL_STATUS status; 4587 4588 /* 4589 * To switch channels clear any pending DMA operations; 4590 * wait long enough for the RX fifo to drain, reset the 4591 * hardware at the new frequency, and then re-enable 4592 * the relevant bits of the h/w. 4593 */ 4594 ath_hal_intrset(ah, 0); /* disable interrupts */ 4595 ath_draintxq(sc); /* clear pending tx frames */ 4596 ath_stoprecv(sc); /* turn off frame recv */ 4597 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4598 if_printf(ic->ic_ifp, "%s: unable to reset " 4599 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4600 __func__, ieee80211_chan2ieee(ic, chan), 4601 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4602 return EIO; 4603 } 4604 sc->sc_curchan = hchan; 4605 ath_update_txpow(sc); /* update tx power state */ 4606 ath_restore_diversity(sc); 4607 sc->sc_calinterval = 1; 4608 sc->sc_caltries = 0; 4609 4610 /* 4611 * Re-enable rx framework. 4612 */ 4613 if (ath_startrecv(sc) != 0) { 4614 if_printf(&sc->sc_if, 4615 "%s: unable to restart recv logic\n", __func__); 4616 return EIO; 4617 } 4618 4619 /* 4620 * Change channels and update the h/w rate map 4621 * if we're switching; e.g. 11a to 11b/g. 4622 */ 4623 ic->ic_ibss_chan = chan; 4624 ath_chan_change(sc, chan); 4625 4626 #if 0 4627 /* 4628 * Handle DFS required waiting period to determine 4629 * if channel is clear of radar traffic. 4630 */ 4631 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4632 #define DFS_AND_NOT_CLEAR(_c) \ 4633 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4634 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4635 if_printf(&sc->sc_if, 4636 "wait for DFS clear channel signal\n"); 4637 /* XXX stop sndq */ 4638 sc->sc_if.if_flags |= IFF_OACTIVE; 4639 callout_reset(&sc->sc_dfs_ch, 4640 2 * hz, ath_dfswait, sc); 4641 } else 4642 callout_stop(&sc->sc_dfs_ch); 4643 #undef DFS_NOT_CLEAR 4644 } 4645 #endif 4646 4647 /* 4648 * Re-enable interrupts. 4649 */ 4650 ath_hal_intrset(ah, sc->sc_imask); 4651 } 4652 return 0; 4653 } 4654 4655 static void 4656 ath_next_scan(void *arg) 4657 { 4658 struct ath_softc *sc = arg; 4659 struct ieee80211com *ic = &sc->sc_ic; 4660 int s; 4661 4662 /* don't call ath_start w/o network interrupts blocked */ 4663 s = splnet(); 4664 4665 if (ic->ic_state == IEEE80211_S_SCAN) 4666 ieee80211_next_scan(ic); 4667 splx(s); 4668 } 4669 4670 /* 4671 * Periodically recalibrate the PHY to account 4672 * for temperature/environment changes. 4673 */ 4674 static void 4675 ath_calibrate(void *arg) 4676 { 4677 struct ath_softc *sc = arg; 4678 struct ath_hal *ah = sc->sc_ah; 4679 HAL_BOOL iqCalDone; 4680 int s; 4681 4682 sc->sc_stats.ast_per_cal++; 4683 4684 s = splnet(); 4685 4686 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4687 /* 4688 * Rfgain is out of bounds, reset the chip 4689 * to load new gain values. 4690 */ 4691 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4692 "%s: rfgain change\n", __func__); 4693 sc->sc_stats.ast_per_rfgain++; 4694 ath_reset(&sc->sc_if); 4695 } 4696 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4697 DPRINTF(sc, ATH_DEBUG_ANY, 4698 "%s: calibration of channel %u failed\n", 4699 __func__, sc->sc_curchan.channel); 4700 sc->sc_stats.ast_per_calfail++; 4701 } 4702 /* 4703 * Calibrate noise floor data again in case of change. 4704 */ 4705 ath_hal_process_noisefloor(ah); 4706 /* 4707 * Poll more frequently when the IQ calibration is in 4708 * progress to speedup loading the final settings. 4709 * We temper this aggressive polling with an exponential 4710 * back off after 4 tries up to ath_calinterval. 4711 */ 4712 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4713 sc->sc_caltries = 0; 4714 sc->sc_calinterval = ath_calinterval; 4715 } else if (sc->sc_caltries > 4) { 4716 sc->sc_caltries = 0; 4717 sc->sc_calinterval <<= 1; 4718 if (sc->sc_calinterval > ath_calinterval) 4719 sc->sc_calinterval = ath_calinterval; 4720 } 4721 KASSERTMSG(0 < sc->sc_calinterval && 4722 sc->sc_calinterval <= ath_calinterval, 4723 "bad calibration interval %u", sc->sc_calinterval); 4724 4725 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4726 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4727 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4728 sc->sc_caltries++; 4729 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4730 ath_calibrate, sc); 4731 splx(s); 4732 } 4733 4734 static int 4735 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4736 { 4737 struct ifnet *ifp = ic->ic_ifp; 4738 struct ath_softc *sc = ifp->if_softc; 4739 struct ath_hal *ah = sc->sc_ah; 4740 struct ieee80211_node *ni; 4741 int i, error; 4742 const u_int8_t *bssid; 4743 u_int32_t rfilt; 4744 static const HAL_LED_STATE leds[] = { 4745 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4746 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4747 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4748 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4749 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4750 }; 4751 4752 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4753 ieee80211_state_name[ic->ic_state], 4754 ieee80211_state_name[nstate]); 4755 4756 callout_stop(&sc->sc_scan_ch); 4757 callout_stop(&sc->sc_cal_ch); 4758 #if 0 4759 callout_stop(&sc->sc_dfs_ch); 4760 #endif 4761 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4762 4763 if (nstate == IEEE80211_S_INIT) { 4764 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4765 /* 4766 * NB: disable interrupts so we don't rx frames. 4767 */ 4768 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4769 /* 4770 * Notify the rate control algorithm. 4771 */ 4772 ath_rate_newstate(sc, nstate); 4773 goto done; 4774 } 4775 ni = ic->ic_bss; 4776 error = ath_chan_set(sc, ic->ic_curchan); 4777 if (error != 0) 4778 goto bad; 4779 rfilt = ath_calcrxfilter(sc, nstate); 4780 if (nstate == IEEE80211_S_SCAN) 4781 bssid = ifp->if_broadcastaddr; 4782 else 4783 bssid = ni->ni_bssid; 4784 ath_hal_setrxfilter(ah, rfilt); 4785 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4786 __func__, rfilt, ether_sprintf(bssid)); 4787 4788 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4789 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4790 else 4791 ath_hal_setassocid(ah, bssid, 0); 4792 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4793 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4794 if (ath_hal_keyisvalid(ah, i)) 4795 ath_hal_keysetmac(ah, i, bssid); 4796 } 4797 4798 /* 4799 * Notify the rate control algorithm so rates 4800 * are setup should ath_beacon_alloc be called. 4801 */ 4802 ath_rate_newstate(sc, nstate); 4803 4804 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4805 /* nothing to do */; 4806 } else if (nstate == IEEE80211_S_RUN) { 4807 DPRINTF(sc, ATH_DEBUG_STATE, 4808 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4809 "capinfo=0x%04x chan=%d\n" 4810 , __func__ 4811 , ic->ic_flags 4812 , ni->ni_intval 4813 , ether_sprintf(ni->ni_bssid) 4814 , ni->ni_capinfo 4815 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4816 4817 switch (ic->ic_opmode) { 4818 case IEEE80211_M_HOSTAP: 4819 case IEEE80211_M_IBSS: 4820 /* 4821 * Allocate and setup the beacon frame. 4822 * 4823 * Stop any previous beacon DMA. This may be 4824 * necessary, for example, when an ibss merge 4825 * causes reconfiguration; there will be a state 4826 * transition from RUN->RUN that means we may 4827 * be called with beacon transmission active. 4828 */ 4829 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4830 ath_beacon_free(sc); 4831 error = ath_beacon_alloc(sc, ni); 4832 if (error != 0) 4833 goto bad; 4834 /* 4835 * If joining an adhoc network defer beacon timer 4836 * configuration to the next beacon frame so we 4837 * have a current TSF to use. Otherwise we're 4838 * starting an ibss/bss so there's no need to delay. 4839 */ 4840 if (ic->ic_opmode == IEEE80211_M_IBSS && 4841 ic->ic_bss->ni_tstamp.tsf != 0) 4842 sc->sc_syncbeacon = 1; 4843 else 4844 ath_beacon_config(sc); 4845 break; 4846 case IEEE80211_M_STA: 4847 /* 4848 * Allocate a key cache slot to the station. 4849 */ 4850 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4851 sc->sc_hasclrkey && 4852 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4853 ath_setup_stationkey(ni); 4854 /* 4855 * Defer beacon timer configuration to the next 4856 * beacon frame so we have a current TSF to use 4857 * (any TSF collected when scanning is likely old). 4858 */ 4859 sc->sc_syncbeacon = 1; 4860 break; 4861 default: 4862 break; 4863 } 4864 /* 4865 * Let the hal process statistics collected during a 4866 * scan so it can provide calibrated noise floor data. 4867 */ 4868 ath_hal_process_noisefloor(ah); 4869 /* 4870 * Reset rssi stats; maybe not the best place... 4871 */ 4872 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4873 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4874 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4875 } else { 4876 ath_hal_intrset(ah, 4877 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4878 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4879 } 4880 done: 4881 /* 4882 * Invoke the parent method to complete the work. 4883 */ 4884 error = sc->sc_newstate(ic, nstate, arg); 4885 /* 4886 * Finally, start any timers. 4887 */ 4888 if (nstate == IEEE80211_S_RUN) { 4889 /* start periodic recalibration timer */ 4890 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4891 ath_calibrate, sc); 4892 } else if (nstate == IEEE80211_S_SCAN) { 4893 /* start ap/neighbor scan timer */ 4894 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4895 ath_next_scan, sc); 4896 } 4897 bad: 4898 return error; 4899 } 4900 4901 /* 4902 * Allocate a key cache slot to the station so we can 4903 * setup a mapping from key index to node. The key cache 4904 * slot is needed for managing antenna state and for 4905 * compression when stations do not use crypto. We do 4906 * it uniliaterally here; if crypto is employed this slot 4907 * will be reassigned. 4908 */ 4909 static void 4910 ath_setup_stationkey(struct ieee80211_node *ni) 4911 { 4912 struct ieee80211com *ic = ni->ni_ic; 4913 struct ath_softc *sc = ic->ic_ifp->if_softc; 4914 ieee80211_keyix keyix, rxkeyix; 4915 4916 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4917 /* 4918 * Key cache is full; we'll fall back to doing 4919 * the more expensive lookup in software. Note 4920 * this also means no h/w compression. 4921 */ 4922 /* XXX msg+statistic */ 4923 } else { 4924 /* XXX locking? */ 4925 ni->ni_ucastkey.wk_keyix = keyix; 4926 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4927 /* NB: this will create a pass-thru key entry */ 4928 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4929 } 4930 } 4931 4932 /* 4933 * Setup driver-specific state for a newly associated node. 4934 * Note that we're called also on a re-associate, the isnew 4935 * param tells us if this is the first time or not. 4936 */ 4937 static void 4938 ath_newassoc(struct ieee80211_node *ni, int isnew) 4939 { 4940 struct ieee80211com *ic = ni->ni_ic; 4941 struct ath_softc *sc = ic->ic_ifp->if_softc; 4942 4943 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4944 if (isnew && 4945 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4946 KASSERTMSG(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4947 "new assoc with a unicast key already setup (keyix %u)", 4948 ni->ni_ucastkey.wk_keyix); 4949 ath_setup_stationkey(ni); 4950 } 4951 } 4952 4953 static int 4954 ath_getchannels(struct ath_softc *sc, u_int cc, 4955 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4956 { 4957 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4958 struct ieee80211com *ic = &sc->sc_ic; 4959 struct ifnet *ifp = &sc->sc_if; 4960 struct ath_hal *ah = sc->sc_ah; 4961 HAL_CHANNEL *chans; 4962 int i, ix, nchan; 4963 4964 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4965 M_TEMP, M_NOWAIT); 4966 if (chans == NULL) { 4967 if_printf(ifp, "unable to allocate channel table\n"); 4968 return ENOMEM; 4969 } 4970 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4971 NULL, 0, NULL, 4972 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4973 u_int32_t rd; 4974 4975 (void)ath_hal_getregdomain(ah, &rd); 4976 if_printf(ifp, "unable to collect channel list from hal; " 4977 "regdomain likely %u country code %u\n", rd, cc); 4978 free(chans, M_TEMP); 4979 return EINVAL; 4980 } 4981 4982 /* 4983 * Convert HAL channels to ieee80211 ones and insert 4984 * them in the table according to their channel number. 4985 */ 4986 for (i = 0; i < nchan; i++) { 4987 HAL_CHANNEL *c = &chans[i]; 4988 u_int16_t flags; 4989 4990 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4991 if (ix > IEEE80211_CHAN_MAX) { 4992 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4993 ix, c->channel, c->channelFlags); 4994 continue; 4995 } 4996 if (ix < 0) { 4997 /* XXX can't handle stuff <2400 right now */ 4998 if (bootverbose) 4999 if_printf(ifp, "hal channel %d (%u/%x) " 5000 "cannot be handled; ignored\n", 5001 ix, c->channel, c->channelFlags); 5002 continue; 5003 } 5004 /* 5005 * Calculate net80211 flags; most are compatible 5006 * but some need massaging. Note the static turbo 5007 * conversion can be removed once net80211 is updated 5008 * to understand static vs. dynamic turbo. 5009 */ 5010 flags = c->channelFlags & COMPAT; 5011 if (c->channelFlags & CHANNEL_STURBO) 5012 flags |= IEEE80211_CHAN_TURBO; 5013 if (ic->ic_channels[ix].ic_freq == 0) { 5014 ic->ic_channels[ix].ic_freq = c->channel; 5015 ic->ic_channels[ix].ic_flags = flags; 5016 } else { 5017 /* channels overlap; e.g. 11g and 11b */ 5018 ic->ic_channels[ix].ic_flags |= flags; 5019 } 5020 } 5021 free(chans, M_TEMP); 5022 return 0; 5023 #undef COMPAT 5024 } 5025 5026 static void 5027 ath_led_done(void *arg) 5028 { 5029 struct ath_softc *sc = arg; 5030 5031 sc->sc_blinking = 0; 5032 } 5033 5034 /* 5035 * Turn the LED off: flip the pin and then set a timer so no 5036 * update will happen for the specified duration. 5037 */ 5038 static void 5039 ath_led_off(void *arg) 5040 { 5041 struct ath_softc *sc = arg; 5042 5043 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5044 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5045 } 5046 5047 /* 5048 * Blink the LED according to the specified on/off times. 5049 */ 5050 static void 5051 ath_led_blink(struct ath_softc *sc, int on, int off) 5052 { 5053 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5054 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5055 sc->sc_blinking = 1; 5056 sc->sc_ledoff = off; 5057 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5058 } 5059 5060 static void 5061 ath_led_event(struct ath_softc *sc, int event) 5062 { 5063 5064 sc->sc_ledevent = ticks; /* time of last event */ 5065 if (sc->sc_blinking) /* don't interrupt active blink */ 5066 return; 5067 switch (event) { 5068 case ATH_LED_POLL: 5069 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 5070 sc->sc_hwmap[0].ledoff); 5071 break; 5072 case ATH_LED_TX: 5073 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 5074 sc->sc_hwmap[sc->sc_txrate].ledoff); 5075 break; 5076 case ATH_LED_RX: 5077 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 5078 sc->sc_hwmap[sc->sc_rxrate].ledoff); 5079 break; 5080 } 5081 } 5082 5083 static void 5084 ath_update_txpow(struct ath_softc *sc) 5085 { 5086 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 5087 struct ieee80211com *ic = &sc->sc_ic; 5088 struct ath_hal *ah = sc->sc_ah; 5089 u_int32_t txpow; 5090 5091 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 5092 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 5093 /* read back in case value is clamped */ 5094 (void)ath_hal_gettxpowlimit(ah, &txpow); 5095 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 5096 } 5097 /* 5098 * Fetch max tx power level for status requests. 5099 */ 5100 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 5101 ic->ic_bss->ni_txpower = txpow; 5102 } 5103 5104 static void 5105 rate_setup(struct ath_softc *sc, 5106 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 5107 { 5108 int i, maxrates; 5109 5110 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 5111 DPRINTF(sc, ATH_DEBUG_ANY, 5112 "%s: rate table too small (%u > %u)\n", 5113 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 5114 maxrates = IEEE80211_RATE_MAXSIZE; 5115 } else 5116 maxrates = rt->rateCount; 5117 for (i = 0; i < maxrates; i++) 5118 rs->rs_rates[i] = rt->info[i].dot11Rate; 5119 rs->rs_nrates = maxrates; 5120 } 5121 5122 static int 5123 ath_rate_setup(struct ath_softc *sc, u_int mode) 5124 { 5125 struct ath_hal *ah = sc->sc_ah; 5126 struct ieee80211com *ic = &sc->sc_ic; 5127 const HAL_RATE_TABLE *rt; 5128 5129 switch (mode) { 5130 case IEEE80211_MODE_11A: 5131 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5132 break; 5133 case IEEE80211_MODE_11B: 5134 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5135 break; 5136 case IEEE80211_MODE_11G: 5137 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5138 break; 5139 case IEEE80211_MODE_TURBO_A: 5140 /* XXX until static/dynamic turbo is fixed */ 5141 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5142 break; 5143 case IEEE80211_MODE_TURBO_G: 5144 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5145 break; 5146 default: 5147 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5148 __func__, mode); 5149 return 0; 5150 } 5151 sc->sc_rates[mode] = rt; 5152 if (rt != NULL) { 5153 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5154 return 1; 5155 } else 5156 return 0; 5157 } 5158 5159 static void 5160 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5161 { 5162 #define N(a) (sizeof(a)/sizeof(a[0])) 5163 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5164 static const struct { 5165 u_int rate; /* tx/rx 802.11 rate */ 5166 u_int16_t timeOn; /* LED on time (ms) */ 5167 u_int16_t timeOff; /* LED off time (ms) */ 5168 } blinkrates[] = { 5169 { 108, 40, 10 }, 5170 { 96, 44, 11 }, 5171 { 72, 50, 13 }, 5172 { 48, 57, 14 }, 5173 { 36, 67, 16 }, 5174 { 24, 80, 20 }, 5175 { 22, 100, 25 }, 5176 { 18, 133, 34 }, 5177 { 12, 160, 40 }, 5178 { 10, 200, 50 }, 5179 { 6, 240, 58 }, 5180 { 4, 267, 66 }, 5181 { 2, 400, 100 }, 5182 { 0, 500, 130 }, 5183 }; 5184 const HAL_RATE_TABLE *rt; 5185 int i, j; 5186 5187 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5188 rt = sc->sc_rates[mode]; 5189 KASSERTMSG(rt != NULL, "no h/w rate set for phy mode %u", mode); 5190 for (i = 0; i < rt->rateCount; i++) 5191 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5192 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5193 for (i = 0; i < 32; i++) { 5194 u_int8_t ix = rt->rateCodeToIndex[i]; 5195 if (ix == 0xff) { 5196 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5197 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5198 continue; 5199 } 5200 sc->sc_hwmap[i].ieeerate = 5201 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5202 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5203 if (rt->info[ix].shortPreamble || 5204 rt->info[ix].phy == IEEE80211_T_OFDM) 5205 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5206 /* NB: receive frames include FCS */ 5207 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5208 IEEE80211_RADIOTAP_F_FCS; 5209 /* setup blink rate table to avoid per-packet lookup */ 5210 for (j = 0; j < N(blinkrates)-1; j++) 5211 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5212 break; 5213 /* NB: this uses the last entry if the rate isn't found */ 5214 /* XXX beware of overlow */ 5215 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5216 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5217 } 5218 sc->sc_currates = rt; 5219 sc->sc_curmode = mode; 5220 /* 5221 * All protection frames are transmited at 2Mb/s for 5222 * 11g, otherwise at 1Mb/s. 5223 */ 5224 if (mode == IEEE80211_MODE_11G) 5225 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5226 else 5227 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5228 /* rate index used to send management frames */ 5229 sc->sc_minrateix = 0; 5230 /* 5231 * Setup multicast rate state. 5232 */ 5233 /* XXX layering violation */ 5234 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5235 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5236 /* NB: caller is responsible for reseting rate control state */ 5237 #undef N 5238 } 5239 5240 #ifdef AR_DEBUG 5241 static void 5242 ath_printrxbuf(struct ath_buf *bf, int done) 5243 { 5244 struct ath_desc *ds; 5245 int i; 5246 5247 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5248 printf("R%d (%p %" PRIx64 5249 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5250 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5251 ds->ds_link, ds->ds_data, 5252 ds->ds_ctl0, ds->ds_ctl1, 5253 ds->ds_hw[0], ds->ds_hw[1], 5254 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5255 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5256 } 5257 } 5258 5259 static void 5260 ath_printtxbuf(struct ath_buf *bf, int done) 5261 { 5262 struct ath_desc *ds; 5263 int i; 5264 5265 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5266 printf("T%d (%p %" PRIx64 5267 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5268 i, ds, 5269 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5270 ds->ds_link, ds->ds_data, 5271 ds->ds_ctl0, ds->ds_ctl1, 5272 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5273 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5274 } 5275 } 5276 #endif /* AR_DEBUG */ 5277 5278 static void 5279 ath_watchdog(struct ifnet *ifp) 5280 { 5281 struct ath_softc *sc = ifp->if_softc; 5282 struct ieee80211com *ic = &sc->sc_ic; 5283 struct ath_txq *axq; 5284 int i; 5285 5286 ifp->if_timer = 0; 5287 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5288 !device_is_active(sc->sc_dev)) 5289 return; 5290 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5291 if (!ATH_TXQ_SETUP(sc, i)) 5292 continue; 5293 axq = &sc->sc_txq[i]; 5294 ATH_TXQ_LOCK(axq); 5295 if (axq->axq_timer == 0) 5296 ; 5297 else if (--axq->axq_timer == 0) { 5298 ATH_TXQ_UNLOCK(axq); 5299 if_printf(ifp, "device timeout (txq %d, " 5300 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5301 if (sc->sc_txintrperiod > 1) 5302 sc->sc_txintrperiod--; 5303 ath_reset(ifp); 5304 ifp->if_oerrors++; 5305 sc->sc_stats.ast_watchdog++; 5306 break; 5307 } else 5308 ifp->if_timer = 1; 5309 ATH_TXQ_UNLOCK(axq); 5310 } 5311 ieee80211_watchdog(ic); 5312 } 5313 5314 /* 5315 * Diagnostic interface to the HAL. This is used by various 5316 * tools to do things like retrieve register contents for 5317 * debugging. The mechanism is intentionally opaque so that 5318 * it can change frequently w/o concern for compatiblity. 5319 */ 5320 static int 5321 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5322 { 5323 struct ath_hal *ah = sc->sc_ah; 5324 u_int id = ad->ad_id & ATH_DIAG_ID; 5325 void *indata = NULL; 5326 void *outdata = NULL; 5327 u_int32_t insize = ad->ad_in_size; 5328 u_int32_t outsize = ad->ad_out_size; 5329 int error = 0; 5330 5331 if (ad->ad_id & ATH_DIAG_IN) { 5332 /* 5333 * Copy in data. 5334 */ 5335 indata = malloc(insize, M_TEMP, M_NOWAIT); 5336 if (indata == NULL) { 5337 error = ENOMEM; 5338 goto bad; 5339 } 5340 error = copyin(ad->ad_in_data, indata, insize); 5341 if (error) 5342 goto bad; 5343 } 5344 if (ad->ad_id & ATH_DIAG_DYN) { 5345 /* 5346 * Allocate a buffer for the results (otherwise the HAL 5347 * returns a pointer to a buffer where we can read the 5348 * results). Note that we depend on the HAL leaving this 5349 * pointer for us to use below in reclaiming the buffer; 5350 * may want to be more defensive. 5351 */ 5352 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5353 if (outdata == NULL) { 5354 error = ENOMEM; 5355 goto bad; 5356 } 5357 } 5358 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5359 if (outsize < ad->ad_out_size) 5360 ad->ad_out_size = outsize; 5361 if (outdata != NULL) 5362 error = copyout(outdata, ad->ad_out_data, 5363 ad->ad_out_size); 5364 } else { 5365 error = EINVAL; 5366 } 5367 bad: 5368 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5369 free(indata, M_TEMP); 5370 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5371 free(outdata, M_TEMP); 5372 return error; 5373 } 5374 5375 static int 5376 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5377 { 5378 #define IS_RUNNING(ifp) \ 5379 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5380 struct ath_softc *sc = ifp->if_softc; 5381 struct ieee80211com *ic = &sc->sc_ic; 5382 struct ifreq *ifr = (struct ifreq *)data; 5383 int error = 0, s; 5384 5385 s = splnet(); 5386 switch (cmd) { 5387 case SIOCSIFFLAGS: 5388 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5389 break; 5390 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 5391 case IFF_UP | IFF_RUNNING: 5392 /* 5393 * To avoid rescanning another access point, 5394 * do not call ath_init() here. Instead, 5395 * only reflect promisc mode settings. 5396 */ 5397 ath_mode_init(sc); 5398 break; 5399 case IFF_UP: 5400 /* 5401 * Beware of being called during attach/detach 5402 * to reset promiscuous mode. In that case we 5403 * will still be marked UP but not RUNNING. 5404 * However trying to re-init the interface 5405 * is the wrong thing to do as we've already 5406 * torn down much of our state. There's 5407 * probably a better way to deal with this. 5408 */ 5409 error = ath_init(sc); 5410 break; 5411 case IFF_RUNNING: 5412 ath_stop_locked(ifp, 1); 5413 break; 5414 case 0: 5415 break; 5416 } 5417 break; 5418 case SIOCADDMULTI: 5419 case SIOCDELMULTI: 5420 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5421 if (ifp->if_flags & IFF_RUNNING) 5422 ath_mode_init(sc); 5423 error = 0; 5424 } 5425 break; 5426 case SIOCGATHSTATS: 5427 /* NB: embed these numbers to get a consistent view */ 5428 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5429 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5430 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5431 splx(s); 5432 /* 5433 * NB: Drop the softc lock in case of a page fault; 5434 * we'll accept any potential inconsisentcy in the 5435 * statistics. The alternative is to copy the data 5436 * to a local structure. 5437 */ 5438 return copyout(&sc->sc_stats, 5439 ifr->ifr_data, sizeof (sc->sc_stats)); 5440 case SIOCGATHDIAG: 5441 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5442 break; 5443 default: 5444 error = ieee80211_ioctl(ic, cmd, data); 5445 if (error != ENETRESET) 5446 ; 5447 else if (IS_RUNNING(ifp) && 5448 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5449 error = ath_init(sc); 5450 else 5451 error = 0; 5452 break; 5453 } 5454 splx(s); 5455 return error; 5456 #undef IS_RUNNING 5457 } 5458 5459 static void 5460 ath_bpfattach(struct ath_softc *sc) 5461 { 5462 struct ifnet *ifp = &sc->sc_if; 5463 5464 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 5465 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5466 &sc->sc_drvbpf); 5467 5468 /* 5469 * Initialize constant fields. 5470 * XXX make header lengths a multiple of 32-bits so subsequent 5471 * headers are properly aligned; this is a kludge to keep 5472 * certain applications happy. 5473 * 5474 * NB: the channel is setup each time we transition to the 5475 * RUN state to avoid filling it in for each frame. 5476 */ 5477 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5478 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5479 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5480 5481 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5482 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5483 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5484 } 5485 5486 /* 5487 * Announce various information on device/driver attach. 5488 */ 5489 static void 5490 ath_announce(struct ath_softc *sc) 5491 { 5492 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5493 struct ifnet *ifp = &sc->sc_if; 5494 struct ath_hal *ah = sc->sc_ah; 5495 u_int modes, cc; 5496 5497 if_printf(ifp, "mac %d.%d phy %d.%d", 5498 ah->ah_macVersion, ah->ah_macRev, 5499 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5500 /* 5501 * Print radio revision(s). We check the wireless modes 5502 * to avoid falsely printing revs for inoperable parts. 5503 * Dual-band radio revs are returned in the 5 GHz rev number. 5504 */ 5505 ath_hal_getcountrycode(ah, &cc); 5506 modes = ath_hal_getwirelessmodes(ah, cc); 5507 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5508 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5509 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5510 ah->ah_analog5GhzRev >> 4, 5511 ah->ah_analog5GhzRev & 0xf, 5512 ah->ah_analog2GhzRev >> 4, 5513 ah->ah_analog2GhzRev & 0xf); 5514 else 5515 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5516 ah->ah_analog5GhzRev & 0xf); 5517 } else 5518 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5519 ah->ah_analog5GhzRev & 0xf); 5520 printf("\n"); 5521 if (bootverbose) { 5522 int i; 5523 for (i = 0; i <= WME_AC_VO; i++) { 5524 struct ath_txq *txq = sc->sc_ac2q[i]; 5525 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5526 txq->axq_qnum, ieee80211_wme_acnames[i]); 5527 } 5528 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5529 sc->sc_cabq->axq_qnum); 5530 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5531 } 5532 if (ath_rxbuf != ATH_RXBUF) 5533 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5534 if (ath_txbuf != ATH_TXBUF) 5535 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5536 #undef HAL_MODE_DUALBAND 5537 } 5538
Indexes created Thu Oct 02 07:10:07 GMT 2025