ath.c revision 1.3
1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 #ifdef __FreeBSD__ 39 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.14 2003/09/05 22:22:49 sam Exp $"); 40 #endif 41 #ifdef __NetBSD__ 42 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.3 2003/10/14 17:47:03 ichiro Exp $"); 43 #endif 44 45 /* 46 * Driver for the Atheros Wireless LAN controller. 47 * 48 * This software is derived from work of Atsushi Onoe; his contribution 49 * is greatly appreciated. 50 */ 51 52 #include "opt_inet.h" 53 54 #ifdef __NetBSD__ 55 #include "bpfilter.h" 56 #endif /* __NetBSD__ */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/types.h> 61 #include <sys/sysctl.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/lock.h> 65 #ifdef __FreeBSD__ 66 #include <sys/mutex.h> 67 #endif 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #ifdef __FreeBSD__ 74 #include <sys/bus.h> 75 #else 76 #include <machine/bus.h> 77 #endif 78 #include <sys/endian.h> 79 80 #include <machine/bus.h> 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 #include <net/if_arp.h> 86 #ifdef __FreeBSD__ 87 #include <net/ethernet.h> 88 #else 89 #include <net/if_ether.h> 90 #endif 91 #include <net/if_llc.h> 92 93 #include <net80211/ieee80211_var.h> 94 #include <net80211/ieee80211_compat.h> 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #ifdef INET 101 #include <netinet/in.h> 102 #endif 103 104 #include <dev/ic/athcompat.h> 105 106 #define AR_DEBUG 107 #ifdef __FreeBSD__ 108 #include <dev/ath/if_athvar.h> 109 #include <contrib/dev/ath/ah_desc.h> 110 #else 111 #include <dev/ic/athvar.h> 112 #include <../contrib/sys/dev/ic/athhal_desc.h> 113 #endif 114 115 /* unalligned little endian access */ 116 #define LE_READ_2(p) \ 117 ((u_int16_t) \ 118 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 119 #define LE_READ_4(p) \ 120 ((u_int32_t) \ 121 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 122 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 123 124 #ifdef __FreeBSD__ 125 static void ath_init(void *); 126 #else 127 static int ath_init(struct ifnet *); 128 #endif 129 static int ath_init1(struct ath_softc *); 130 static int ath_intr1(struct ath_softc *); 131 static void ath_stop(struct ifnet *); 132 static void ath_start(struct ifnet *); 133 static void ath_reset(struct ath_softc *); 134 static int ath_media_change(struct ifnet *); 135 static void ath_watchdog(struct ifnet *); 136 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 137 static void ath_fatal_proc(void *, int); 138 static void ath_rxorn_proc(void *, int); 139 static void ath_bmiss_proc(void *, int); 140 static void ath_initkeytable(struct ath_softc *); 141 static void ath_mode_init(struct ath_softc *); 142 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 143 static void ath_beacon_proc(void *, int); 144 static void ath_beacon_free(struct ath_softc *); 145 static void ath_beacon_config(struct ath_softc *); 146 static int ath_desc_alloc(struct ath_softc *); 147 static void ath_desc_free(struct ath_softc *); 148 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 149 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 150 static void ath_node_copy(struct ieee80211com *, 151 struct ieee80211_node *, const struct ieee80211_node *); 152 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 153 static void ath_rx_proc(void *, int); 154 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 155 struct ath_buf *, struct mbuf *); 156 static void ath_tx_proc(void *, int); 157 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 158 static void ath_draintxq(struct ath_softc *); 159 static void ath_stoprecv(struct ath_softc *); 160 static int ath_startrecv(struct ath_softc *); 161 static void ath_next_scan(void *); 162 static void ath_calibrate(void *); 163 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 164 static void ath_newassoc(struct ieee80211com *, 165 struct ieee80211_node *, int); 166 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 167 168 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 169 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 170 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 171 static void ath_rate_ctl(void *, struct ieee80211_node *); 172 173 #ifdef __NetBSD__ 174 int ath_enable(struct ath_softc *); 175 void ath_disable(struct ath_softc *); 176 void ath_power(int, void *); 177 #endif 178 179 #ifdef __FreeBSD__ 180 SYSCTL_DECL(_hw_ath); 181 /* XXX validate sysctl values */ 182 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 183 0, "channel dwell time (ms) for AP/station scanning"); 184 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 185 0, "chip calibration interval (secs)"); 186 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 187 0, "enable/disable outdoor operation"); 188 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 189 0, "country code"); 190 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 191 0, "regulatory domain"); 192 #endif /* __FreeBSD__ */ 193 194 static int ath_dwelltime = 200; /* 5 channels/second */ 195 static int ath_calinterval = 30; /* calibrate every 30 secs */ 196 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 197 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 198 static int ath_regdomain = 0; /* regulatory domain */ 199 200 #ifdef AR_DEBUG 201 int ath_debug = 0; 202 #ifdef __FreeBSD__ 203 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 204 0, "control debugging printfs"); 205 #endif /* __FreeBSD__ */ 206 #define IFF_DUMPPKTS(_ifp) \ 207 (ath_debug || \ 208 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 209 static void ath_printrxbuf(struct ath_buf *bf, int); 210 static void ath_printtxbuf(struct ath_buf *bf, int); 211 #define DPRINTF(X) if (ath_debug) printf X 212 #define DPRINTF2(X) if (ath_debug > 1) printf X 213 #else 214 #define IFF_DUMPPKTS(_ifp) \ 215 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 216 #define DPRINTF(X) 217 #define DPRINTF2(X) 218 #endif 219 220 #ifdef __NetBSD__ 221 int 222 ath_activate(struct device *self, enum devact act) 223 { 224 struct ath_softc *sc = (struct ath_softc *)self; 225 int rv = 0, s; 226 227 s = splnet(); 228 switch (act) { 229 case DVACT_ACTIVATE: 230 rv = EOPNOTSUPP; 231 break; 232 case DVACT_DEACTIVATE: 233 if_deactivate(&sc->sc_ic.ic_if); 234 break; 235 } 236 splx(s); 237 return rv; 238 } 239 240 int 241 ath_enable(struct ath_softc *sc) 242 { 243 if (ATH_IS_ENABLED(sc) == 0) { 244 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 245 printf("%s: device enable failed\n", 246 sc->sc_dev.dv_xname); 247 return (EIO); 248 } 249 sc->sc_flags |= ATH_ENABLED; 250 } 251 return (0); 252 } 253 254 void 255 ath_disable(struct ath_softc *sc) 256 { 257 if (!ATH_IS_ENABLED(sc)) 258 return; 259 if (sc->sc_disable != NULL) 260 (*sc->sc_disable)(sc); 261 sc->sc_flags &= ~ATH_ENABLED; 262 } 263 #endif /* #ifdef __NetBSD__ */ 264 265 int 266 ath_attach(u_int16_t devid, struct ath_softc *sc) 267 { 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ifnet *ifp = &ic->ic_if; 270 struct ath_hal *ah; 271 HAL_STATUS status; 272 int error = 0; 273 274 DPRINTF(("ath_attach: devid 0x%x\n", devid)); 275 276 #ifdef __FreeBSD__ 277 /* set these up early for if_printf use */ 278 ifp->if_unit = device_get_unit(sc->sc_dev); 279 ifp->if_name = "ath"; 280 #else 281 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 282 #endif 283 284 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 285 if (ah == NULL) { 286 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 287 status); 288 error = ENXIO; 289 goto bad; 290 } 291 sc->sc_ah = ah; 292 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 293 294 /* 295 * Collect the channel list using the default country 296 * code and including outdoor channels. The 802.11 layer 297 * is resposible for filtering this list based on settings 298 * like the phy mode. 299 */ 300 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 301 if (error != 0) 302 goto bad; 303 /* 304 * Copy these back; they are set as a side effect 305 * of constructing the channel list. 306 */ 307 ath_regdomain = ath_hal_getregdomain(ah); 308 ath_countrycode = ath_hal_getcountrycode(ah); 309 310 /* 311 * Setup rate tables for all potential media types. 312 */ 313 ath_rate_setup(sc, IEEE80211_MODE_11A); 314 ath_rate_setup(sc, IEEE80211_MODE_11B); 315 ath_rate_setup(sc, IEEE80211_MODE_11G); 316 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 317 318 error = ath_desc_alloc(sc); 319 if (error != 0) { 320 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 321 goto bad; 322 } 323 ATH_CALLOUT_INIT(&sc->sc_scan_ch); 324 ATH_CALLOUT_INIT(&sc->sc_cal_ch); 325 326 #ifdef __FreeBSD__ 327 mtx_init(&sc->sc_txbuflock, 328 device_get_nameunit(sc->sc_dev), "xmit buf q", MTX_DEF); 329 mtx_init(&sc->sc_txqlock, 330 device_get_nameunit(sc->sc_dev), "xmit q", MTX_DEF); 331 #endif 332 333 ATH_TASK_INIT(&sc->sc_txtask, ath_tx_proc, sc); 334 ATH_TASK_INIT(&sc->sc_rxtask, ath_rx_proc, sc); 335 ATH_TASK_INIT(&sc->sc_swbatask, ath_beacon_proc, sc); 336 ATH_TASK_INIT(&sc->sc_rxorntask, ath_rxorn_proc, sc); 337 ATH_TASK_INIT(&sc->sc_fataltask, ath_fatal_proc, sc); 338 ATH_TASK_INIT(&sc->sc_bmisstask, ath_bmiss_proc, sc); 339 340 /* 341 * For now just pre-allocate one data queue and one 342 * beacon queue. Note that the HAL handles resetting 343 * them at the needed time. Eventually we'll want to 344 * allocate more tx queues for splitting management 345 * frames and for QOS support. 346 */ 347 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 348 HAL_TX_QUEUE_DATA, 349 AH_TRUE /* enable interrupts */ 350 ); 351 if (sc->sc_txhalq == (u_int) -1) { 352 if_printf(ifp, "unable to setup a data xmit queue!\n"); 353 goto bad; 354 } 355 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 356 HAL_TX_QUEUE_BEACON, 357 AH_TRUE /* enable interrupts */ 358 ); 359 if (sc->sc_bhalq == (u_int) -1) { 360 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 361 goto bad; 362 } 363 364 ifp->if_softc = sc; 365 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 366 ifp->if_start = ath_start; 367 ifp->if_watchdog = ath_watchdog; 368 ifp->if_ioctl = ath_ioctl; 369 ifp->if_init = ath_init; 370 #ifdef __FreeBSD__ 371 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 372 #else 373 #if 0 374 ifp->if_stop = ath_stop; /* XXX */ 375 #endif 376 IFQ_SET_READY(&ifp->if_snd); 377 #endif 378 379 ic->ic_softc = sc; 380 ic->ic_newassoc = ath_newassoc; 381 /* XXX not right but it's not used anywhere important */ 382 ic->ic_phytype = IEEE80211_T_OFDM; 383 ic->ic_opmode = IEEE80211_M_STA; 384 ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_IBSS | IEEE80211_C_HOSTAP 385 | IEEE80211_C_MONITOR; 386 /* NB: 11g support is identified when we fetch the channel set */ 387 if (sc->sc_have11g) 388 ic->ic_caps |= IEEE80211_C_SHPREAMBLE; 389 390 /* get mac address from hardware */ 391 ath_hal_getmac(ah, ic->ic_myaddr); 392 393 #ifdef __NetBSD__ 394 if_attach(ifp); 395 #endif 396 /* call MI attach routine. */ 397 ieee80211_ifattach(ifp); 398 /* override default methods */ 399 ic->ic_node_alloc = ath_node_alloc; 400 ic->ic_node_free = ath_node_free; 401 ic->ic_node_copy = ath_node_copy; 402 sc->sc_newstate = ic->ic_newstate; 403 ic->ic_newstate = ath_newstate; 404 /* complete initialization */ 405 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 406 407 #if NBPFILTER > 0 408 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 409 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 410 &sc->sc_drvbpf); 411 #endif 412 /* 413 * Initialize constant fields. 414 * 415 * NB: the channel is setup each time we transition to the 416 * RUN state to avoid filling it in for each frame. 417 */ 418 sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); 419 sc->sc_tx_th.wt_ihdr.it_present = ATH_TX_RADIOTAP_PRESENT; 420 421 sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); 422 sc->sc_rx_th.wr_ihdr.it_present = ATH_RX_RADIOTAP_PRESENT; 423 424 if_printf(ifp, "802.11 address: %s\n", ether_sprintf(ic->ic_myaddr)); 425 426 #ifdef __NetBSD__ 427 sc->sc_flags |= ATH_ATTACHED; 428 /* 429 * Make sure the interface is shutdown during reboot. 430 */ 431 #if 0 432 sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 433 if (sc->sc_sdhook == NULL) 434 printf("%s: WARNING: unable to establish shutdown hook\n", 435 sc->sc_dev.dv_xname); 436 #endif 437 sc->sc_powerhook = powerhook_establish(ath_power, sc); 438 if (sc->sc_powerhook == NULL) 439 printf("%s: WARNING: unable to establish power hook\n", 440 sc->sc_dev.dv_xname); 441 #endif 442 return 0; 443 bad: 444 if (ah) 445 ath_hal_detach(ah); 446 sc->sc_invalid = 1; 447 return error; 448 } 449 450 int 451 ath_detach(struct ath_softc *sc) 452 { 453 struct ifnet *ifp = &sc->sc_ic.ic_if; 454 ath_softc_critsect_decl(s); 455 456 DPRINTF(("ath_detach: if_flags %x\n", ifp->if_flags)); 457 if ((sc->sc_flags & ATH_ATTACHED) == 0) 458 return (0); 459 460 ath_softc_critsect_begin(sc, s); 461 ath_stop(ifp); 462 #if NBPFILTER > 0 463 bpfdetach(ifp); 464 #endif 465 ath_desc_free(sc); 466 ath_hal_detach(sc->sc_ah); 467 ieee80211_ifdetach(ifp); 468 #ifdef __NetBSD__ 469 if_detach(ifp); 470 #endif 471 ath_softc_critsect_end(sc, s); 472 return 0; 473 } 474 475 void 476 ath_power(int why, void *arg) 477 { 478 struct ath_softc *sc = arg; 479 int s; 480 481 DPRINTF(("ath_power(%d)\n", why)); 482 483 s = splnet(); 484 switch (why) { 485 case PWR_SUSPEND: 486 case PWR_STANDBY: 487 ath_suspend(sc, why); 488 break; 489 case PWR_RESUME: 490 ath_resume(sc, why); 491 break; 492 case PWR_SOFTSUSPEND: 493 case PWR_SOFTSTANDBY: 494 case PWR_SOFTRESUME: 495 break; 496 } 497 splx(s); 498 } 499 500 void 501 ath_suspend(struct ath_softc *sc, int why) 502 { 503 struct ifnet *ifp = &sc->sc_ic.ic_if; 504 505 DPRINTF(("ath_suspend: if_flags %x\n", ifp->if_flags)); 506 507 ath_stop(ifp); 508 if (sc->sc_power != NULL) 509 (*sc->sc_power)(sc, why); 510 } 511 512 void 513 ath_resume(struct ath_softc *sc, int why) 514 { 515 struct ifnet *ifp = &sc->sc_ic.ic_if; 516 517 DPRINTF(("ath_resume: if_flags %x\n", ifp->if_flags)); 518 519 if (ifp->if_flags & IFF_UP) { 520 ath_init(ifp); 521 #if 0 522 (void)ath_intr(sc); 523 #endif 524 if (sc->sc_power != NULL) 525 (*sc->sc_power)(sc, why); 526 if (ifp->if_flags & IFF_RUNNING) 527 ath_start(ifp); 528 } 529 } 530 531 void 532 ath_shutdown(struct ath_softc *sc) 533 { 534 #if 1 535 return; 536 #else 537 struct ifnet *ifp = &sc->sc_ic.ic_if; 538 539 DPRINTF(("ath_shutdown: if_flags %x\n", ifp->if_flags)); 540 541 ath_stop(ifp); 542 #endif 543 } 544 545 #ifdef __NetBSD__ 546 int 547 ath_intr(void *arg) 548 { 549 return ath_intr1((struct ath_softc *)arg); 550 } 551 #else 552 void 553 ath_intr(void *arg) 554 { 555 (void)ath_intr1((struct ath_softc *)arg); 556 } 557 #endif 558 559 static int 560 ath_intr1(struct ath_softc *sc) 561 { 562 struct ieee80211com *ic = &sc->sc_ic; 563 struct ifnet *ifp = &ic->ic_if; 564 struct ath_hal *ah = sc->sc_ah; 565 HAL_INT status; 566 567 if (sc->sc_invalid) { 568 /* 569 * The hardware is not ready/present, don't touch anything. 570 * Note this can happen early on if the IRQ is shared. 571 */ 572 DPRINTF(("ath_intr: invalid; ignored\n")); 573 return 0; 574 } 575 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 576 DPRINTF(("ath_intr: if_flags 0x%x\n", ifp->if_flags)); 577 ath_hal_getisr(ah, &status); /* clear ISR */ 578 ath_hal_intrset(ah, 0); /* disable further intr's */ 579 return 1; /* XXX */ 580 } 581 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 582 DPRINTF2(("ath_intr: status 0x%x\n", status)); 583 #ifdef AR_DEBUG 584 if (ath_debug && 585 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 586 if_printf(ifp, "ath_intr: status 0x%x\n", status); 587 ath_hal_dumpstate(ah); 588 } 589 #endif /* AR_DEBUG */ 590 if (status & HAL_INT_FATAL) { 591 sc->sc_stats.ast_hardware++; 592 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 593 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 594 } else if (status & HAL_INT_RXORN) { 595 sc->sc_stats.ast_rxorn++; 596 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 597 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 598 } else { 599 if (status & HAL_INT_RXEOL) { 600 /* 601 * NB: the hardware should re-read the link when 602 * RXE bit is written, but it doesn't work at 603 * least on older hardware revs. 604 */ 605 sc->sc_stats.ast_rxeol++; 606 sc->sc_rxlink = NULL; 607 } 608 if (status & HAL_INT_TXURN) { 609 sc->sc_stats.ast_txurn++; 610 /* bump tx trigger level */ 611 ath_hal_updatetxtriglevel(ah, AH_TRUE); 612 } 613 if (status & HAL_INT_RX) 614 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 615 if (status & HAL_INT_TX) 616 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 617 if (status & HAL_INT_SWBA) 618 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_swbatask); 619 if (status & HAL_INT_BMISS) { 620 sc->sc_stats.ast_bmiss++; 621 ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 622 } 623 } 624 return 1; 625 } 626 627 static void 628 ath_fatal_proc(void *arg, int pending) 629 { 630 struct ath_softc *sc = arg; 631 632 device_printf(sc->sc_dev, "hardware error; resetting\n"); 633 ath_reset(sc); 634 } 635 636 static void 637 ath_rxorn_proc(void *arg, int pending) 638 { 639 struct ath_softc *sc = arg; 640 641 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 642 ath_reset(sc); 643 } 644 645 static void 646 ath_bmiss_proc(void *arg, int pending) 647 { 648 struct ath_softc *sc = arg; 649 struct ieee80211com *ic = &sc->sc_ic; 650 651 DPRINTF(("ath_bmiss_proc: pending %u\n", pending)); 652 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 653 ("unexpect operating mode %u", ic->ic_opmode)); 654 if (ic->ic_state == IEEE80211_S_RUN) 655 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 656 } 657 658 static u_int 659 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 660 { 661 static const u_int modeflags[] = { 662 0, /* IEEE80211_MODE_AUTO */ 663 CHANNEL_A, /* IEEE80211_MODE_11A */ 664 CHANNEL_B, /* IEEE80211_MODE_11B */ 665 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 666 CHANNEL_T /* IEEE80211_MODE_TURBO */ 667 }; 668 return modeflags[ieee80211_chan2mode(ic, chan)]; 669 } 670 671 #ifdef __NetBSD__ 672 static int 673 ath_init(struct ifnet *ifp) 674 { 675 return ath_init1((struct ath_softc *)ifp->if_softc); 676 } 677 #else 678 static void 679 ath_init(void *arg) 680 { 681 (void)ath_init1((struct ath_softc *)arg); 682 } 683 #endif 684 685 static int 686 ath_init1(struct ath_softc *sc) 687 { 688 struct ieee80211com *ic = &sc->sc_ic; 689 struct ifnet *ifp = &ic->ic_if; 690 struct ieee80211_node *ni; 691 enum ieee80211_phymode mode; 692 struct ath_hal *ah = sc->sc_ah; 693 HAL_STATUS status; 694 HAL_CHANNEL hchan; 695 int error = 0; 696 ath_softc_critsect_decl(s); 697 698 DPRINTF(("ath_init: if_flags 0x%x\n", ifp->if_flags)); 699 700 #ifdef __NetBSD__ 701 if ((error = ath_enable(sc)) != 0) 702 return error; 703 #endif 704 705 ath_softc_critsect_begin(sc, s); 706 /* 707 * Stop anything previously setup. This is safe 708 * whether this is the first time through or not. 709 */ 710 ath_stop(ifp); 711 712 /* 713 * The basic interface to setting the hardware in a good 714 * state is ``reset''. On return the hardware is known to 715 * be powered up and with interrupts disabled. This must 716 * be followed by initialization of the appropriate bits 717 * and then setup of the interrupt mask. 718 */ 719 hchan.channel = ic->ic_ibss_chan->ic_freq; 720 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 721 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 722 if_printf(ifp, "unable to reset hardware; hal status %u\n", 723 status); 724 error = -1; 725 goto done; 726 } 727 728 /* 729 * Setup the hardware after reset: the key cache 730 * is filled as needed and the receive engine is 731 * set going. Frame transmit is handled entirely 732 * in the frame output path; there's nothing to do 733 * here except setup the interrupt mask. 734 */ 735 if (ic->ic_flags & IEEE80211_F_WEPON) 736 ath_initkeytable(sc); 737 if ((error = ath_startrecv(sc)) != 0) { 738 if_printf(ifp, "unable to start recv logic\n"); 739 goto done; 740 } 741 742 /* 743 * Enable interrupts. 744 */ 745 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 746 | HAL_INT_RXEOL | HAL_INT_RXORN 747 | HAL_INT_FATAL | HAL_INT_GLOBAL; 748 ath_hal_intrset(ah, sc->sc_imask); 749 750 ifp->if_flags |= IFF_RUNNING; 751 ic->ic_state = IEEE80211_S_INIT; 752 753 /* 754 * The hardware should be ready to go now so it's safe 755 * to kick the 802.11 state machine as it's likely to 756 * immediately call back to us to send mgmt frames. 757 */ 758 ni = ic->ic_bss; 759 ni->ni_chan = ic->ic_ibss_chan; 760 mode = ieee80211_chan2mode(ic, ni->ni_chan); 761 if (mode != sc->sc_curmode) 762 ath_setcurmode(sc, mode); 763 if (ic->ic_opmode != IEEE80211_M_MONITOR) 764 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 765 else 766 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 767 done: 768 ath_softc_critsect_end(sc, s); 769 return error; 770 } 771 772 static void 773 ath_stop(struct ifnet *ifp) 774 { 775 struct ieee80211com *ic = (struct ieee80211com *) ifp; 776 struct ath_softc *sc = ifp->if_softc; 777 struct ath_hal *ah = sc->sc_ah; 778 ath_softc_critsect_decl(s); 779 780 DPRINTF(("ath_stop: invalid %u if_flags 0x%x\n", 781 sc->sc_invalid, ifp->if_flags)); 782 783 ath_softc_critsect_begin(sc, s); 784 if (ifp->if_flags & IFF_RUNNING) { 785 /* 786 * Shutdown the hardware and driver: 787 * disable interrupts 788 * turn off timers 789 * clear transmit machinery 790 * clear receive machinery 791 * drain and release tx queues 792 * reclaim beacon resources 793 * reset 802.11 state machine 794 * power down hardware 795 * 796 * Note that some of this work is not possible if the 797 * hardware is gone (invalid). 798 */ 799 ifp->if_flags &= ~IFF_RUNNING; 800 ifp->if_timer = 0; 801 if (!sc->sc_invalid) 802 ath_hal_intrset(ah, 0); 803 ath_draintxq(sc); 804 if (!sc->sc_invalid) 805 ath_stoprecv(sc); 806 else 807 sc->sc_rxlink = NULL; 808 #ifdef __FreeBSD__ 809 IF_DRAIN(&ifp->if_snd); 810 #else 811 IF_PURGE(&ifp->if_snd); 812 #endif 813 ath_beacon_free(sc); 814 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 815 if (!sc->sc_invalid) { 816 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 817 } 818 #ifdef __NetBSD__ 819 ath_disable(sc); 820 #endif 821 } 822 ath_softc_critsect_end(sc, s); 823 } 824 825 /* 826 * Reset the hardware w/o losing operational state. This is 827 * basically a more efficient way of doing ath_stop, ath_init, 828 * followed by state transitions to the current 802.11 829 * operational state. Used to recover from errors rx overrun 830 * and to reset the hardware when rf gain settings must be reset. 831 */ 832 static void 833 ath_reset(struct ath_softc *sc) 834 { 835 struct ieee80211com *ic = &sc->sc_ic; 836 struct ifnet *ifp = &ic->ic_if; 837 struct ath_hal *ah = sc->sc_ah; 838 struct ieee80211_channel *c; 839 HAL_STATUS status; 840 HAL_CHANNEL hchan; 841 842 /* 843 * Convert to a HAL channel description with the flags 844 * constrained to reflect the current operating mode. 845 */ 846 c = ic->ic_ibss_chan; 847 hchan.channel = c->ic_freq; 848 hchan.channelFlags = ath_chan2flags(ic, c); 849 850 ath_hal_intrset(ah, 0); /* disable interrupts */ 851 ath_draintxq(sc); /* stop xmit side */ 852 ath_stoprecv(sc); /* stop recv side */ 853 /* NB: indicate channel change so we do a full reset */ 854 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 855 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 856 __func__, status); 857 ath_hal_intrset(ah, sc->sc_imask); 858 if (ath_startrecv(sc) != 0) /* restart recv */ 859 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 860 ath_start(ifp); /* restart xmit */ 861 if (ic->ic_state == IEEE80211_S_RUN) 862 ath_beacon_config(sc); /* restart beacons */ 863 } 864 865 static void 866 ath_start(struct ifnet *ifp) 867 { 868 struct ath_softc *sc = ifp->if_softc; 869 struct ath_hal *ah = sc->sc_ah; 870 struct ieee80211com *ic = &sc->sc_ic; 871 struct ieee80211_node *ni; 872 struct ath_buf *bf; 873 struct mbuf *m; 874 struct ieee80211_frame *wh; 875 ath_txbuf_critsect_decl(s); 876 877 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 878 return; 879 for (;;) { 880 /* 881 * Grab a TX buffer and associated resources. 882 */ 883 ath_txbuf_critsect_begin(sc, s); 884 bf = TAILQ_FIRST(&sc->sc_txbuf); 885 if (bf != NULL) 886 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 887 ath_txbuf_critsect_end(sc, s); 888 if (bf == NULL) { 889 DPRINTF(("ath_start: out of xmit buffers\n")); 890 sc->sc_stats.ast_tx_qstop++; 891 ifp->if_flags |= IFF_OACTIVE; 892 break; 893 } 894 /* 895 * Poll the management queue for frames; they 896 * have priority over normal data frames. 897 */ 898 IF_DEQUEUE(&ic->ic_mgtq, m); 899 if (m == NULL) { 900 /* 901 * No data frames go out unless we're associated. 902 */ 903 if (ic->ic_state != IEEE80211_S_RUN) { 904 DPRINTF(("ath_start: ignore data packet, " 905 "state %u\n", ic->ic_state)); 906 sc->sc_stats.ast_tx_discard++; 907 ath_txbuf_critsect_begin(sc, s); 908 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 909 ath_txbuf_critsect_end(sc, s); 910 break; 911 } 912 IF_DEQUEUE(&ifp->if_snd, m); 913 if (m == NULL) { 914 ath_txbuf_critsect_begin(sc, s); 915 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 916 ath_txbuf_critsect_end(sc, s); 917 break; 918 } 919 ifp->if_opackets++; 920 921 #ifdef __NetBSD__ 922 #if NBPFILTER > 0 923 if (ifp->if_bpf) 924 bpf_mtap(ifp->if_bpf, m); 925 #endif 926 #endif 927 #ifdef __FreeBSD__ 928 BPF_MTAP(ifp, m); 929 #endif 930 /* 931 * Encapsulate the packet in prep for transmission. 932 */ 933 m = ieee80211_encap(ifp, m, &ni); 934 if (m == NULL) { 935 DPRINTF(("ath_start: encapsulation failure\n")); 936 sc->sc_stats.ast_tx_encap++; 937 goto bad; 938 } 939 wh = mtod(m, struct ieee80211_frame *); 940 if (ic->ic_flags & IEEE80211_F_WEPON) 941 wh->i_fc[1] |= IEEE80211_FC1_WEP; 942 } else { 943 /* 944 * Hack! The referenced node pointer is in the 945 * rcvif field of the packet header. This is 946 * placed there by ieee80211_mgmt_output because 947 * we need to hold the reference with the frame 948 * and there's no other way (other than packet 949 * tags which we consider too expensive to use) 950 * to pass it along. 951 */ 952 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 953 m->m_pkthdr.rcvif = NULL; 954 955 wh = mtod(m, struct ieee80211_frame *); 956 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 957 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 958 /* fill time stamp */ 959 u_int64_t tsf; 960 u_int32_t *tstamp; 961 962 tsf = ath_hal_gettsf64(ah); 963 /* XXX: adjust 100us delay to xmit */ 964 tsf += 100; 965 tstamp = (u_int32_t *)&wh[1]; 966 tstamp[0] = htole32(tsf & 0xffffffff); 967 tstamp[1] = htole32(tsf >> 32); 968 } 969 sc->sc_stats.ast_tx_mgmt++; 970 } 971 #if NBPFILTER > 0 972 if (ic->ic_rawbpf) 973 bpf_mtap(ic->ic_rawbpf, m); 974 #endif 975 976 #if NBPFILTER > 0 977 if (sc->sc_drvbpf) { 978 #ifdef __FreeBSD__ 979 struct mbuf *mb; 980 981 MGETHDR(mb, M_DONTWAIT, m->m_type); 982 if (mb != NULL) { 983 sc->sc_tx_th.wt_rate = 984 ni->ni_rates.rs_rates[ni->ni_txrate]; 985 986 mb->m_next = m; 987 mb->m_data = (caddr_t)&sc->sc_tx_th; 988 mb->m_len = sizeof(sc->sc_tx_th); 989 mb->m_pkthdr.len += mb->m_len; 990 bpf_mtap(sc->sc_drvbpf, mb); 991 m_free(mb); 992 } 993 #else 994 struct mbuf mb; 995 996 M_COPY_PKTHDR(&mb, m); 997 sc->sc_tx_th.wt_rate = 998 ni->ni_rates.rs_rates[ni->ni_txrate]; 999 1000 mb.m_next = m; 1001 mb.m_data = (caddr_t)&sc->sc_tx_th; 1002 mb.m_len = sizeof(sc->sc_tx_th); 1003 mb.m_pkthdr.len += mb.m_len; 1004 bpf_mtap(sc->sc_drvbpf, &mb); 1005 #endif 1006 } 1007 #endif 1008 1009 /* 1010 * TODO: 1011 * The duration field of 802.11 header should be filled. 1012 * XXX This may be done in the ieee80211 layer, but the upper 1013 * doesn't know the detail of parameters such as IFS 1014 * for now.. 1015 */ 1016 if (ath_tx_start(sc, ni, bf, m)) { 1017 bad: 1018 ath_txbuf_critsect_begin(sc, s); 1019 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1020 ath_txbuf_critsect_end(sc, s); 1021 ifp->if_oerrors++; 1022 if (ni && ni != ic->ic_bss) 1023 ieee80211_free_node(ic, ni); 1024 continue; 1025 } 1026 1027 sc->sc_tx_timer = 5; 1028 ifp->if_timer = 1; 1029 } 1030 } 1031 1032 static int 1033 ath_media_change(struct ifnet *ifp) 1034 { 1035 int error; 1036 1037 error = ieee80211_media_change(ifp); 1038 if (error == ENETRESET) { 1039 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 1040 (IFF_RUNNING|IFF_UP)) 1041 ath_init(ifp); /* XXX lose error */ 1042 error = 0; 1043 } 1044 return error; 1045 } 1046 1047 static void 1048 ath_watchdog(struct ifnet *ifp) 1049 { 1050 struct ath_softc *sc = ifp->if_softc; 1051 struct ieee80211com *ic = &sc->sc_ic; 1052 1053 ifp->if_timer = 0; 1054 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1055 return; 1056 if (sc->sc_tx_timer) { 1057 if (--sc->sc_tx_timer == 0) { 1058 if_printf(ifp, "device timeout\n"); 1059 #ifdef AR_DEBUG 1060 if (ath_debug) 1061 ath_hal_dumpstate(sc->sc_ah); 1062 #endif /* AR_DEBUG */ 1063 ath_init(ifp); /* XXX ath_reset??? */ 1064 ifp->if_oerrors++; 1065 sc->sc_stats.ast_watchdog++; 1066 return; 1067 } 1068 ifp->if_timer = 1; 1069 } 1070 if (ic->ic_fixed_rate == -1) { 1071 /* 1072 * Run the rate control algorithm if we're not 1073 * locked at a fixed rate. 1074 */ 1075 if (ic->ic_opmode == IEEE80211_M_STA) 1076 ath_rate_ctl(sc, ic->ic_bss); 1077 else 1078 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 1079 } 1080 ieee80211_watchdog(ifp); 1081 } 1082 1083 static int 1084 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1085 { 1086 struct ath_softc *sc = ifp->if_softc; 1087 struct ifreq *ifr = (struct ifreq *)data; 1088 int error = 0; 1089 ath_softc_critsect_decl(s); 1090 1091 ath_softc_critsect_begin(sc, s); 1092 switch (cmd) { 1093 case SIOCSIFFLAGS: 1094 if (ifp->if_flags & IFF_UP) { 1095 if (ifp->if_flags & IFF_RUNNING) { 1096 /* 1097 * To avoid rescanning another access point, 1098 * do not call ath_init() here. Instead, 1099 * only reflect promisc mode settings. 1100 */ 1101 ath_mode_init(sc); 1102 } else 1103 ath_init(ifp); /* XXX lose error */ 1104 } else 1105 ath_stop(ifp); 1106 break; 1107 case SIOCADDMULTI: 1108 case SIOCDELMULTI: 1109 /* 1110 * The upper layer has already installed/removed 1111 * the multicast address(es), just recalculate the 1112 * multicast filter for the card. 1113 */ 1114 if (ifp->if_flags & IFF_RUNNING) 1115 ath_mode_init(sc); 1116 break; 1117 case SIOCGATHSTATS: 1118 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats)); 1119 break; 1120 default: 1121 error = ieee80211_ioctl(ifp, cmd, data); 1122 if (error == ENETRESET) { 1123 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 1124 (IFF_RUNNING|IFF_UP)) 1125 ath_init(ifp); /* XXX lose error */ 1126 error = 0; 1127 } 1128 break; 1129 } 1130 ath_softc_critsect_end(sc, s); 1131 return error; 1132 } 1133 1134 /* 1135 * Fill the hardware key cache with key entries. 1136 */ 1137 static void 1138 ath_initkeytable(struct ath_softc *sc) 1139 { 1140 struct ieee80211com *ic = &sc->sc_ic; 1141 struct ath_hal *ah = sc->sc_ah; 1142 int i; 1143 1144 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1145 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 1146 if (k->wk_len == 0) 1147 ath_hal_keyreset(ah, i); 1148 else 1149 /* XXX return value */ 1150 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 1151 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 1152 } 1153 } 1154 1155 static void 1156 ath_mcastfilter_accum(caddr_t dl, u_int32_t (*mfilt)[2]) 1157 { 1158 u_int32_t val; 1159 u_int8_t pos; 1160 1161 val = LE_READ_4(dl + 0); 1162 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1163 val = LE_READ_4(dl + 3); 1164 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1165 pos &= 0x3f; 1166 (*mfilt)[pos / 32] |= (1 << (pos % 32)); 1167 } 1168 1169 #ifdef __FreeBSD__ 1170 static void 1171 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t (*mfilt)[2]) 1172 { 1173 struct ieee80211com *ic = &sc->sc_ic; 1174 struct ifnet *ifp = &ic->ic_if; 1175 struct ifmultiaddr *ifma; 1176 1177 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1178 caddr_t dl; 1179 1180 /* calculate XOR of eight 6bit values */ 1181 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1182 ath_mcastfilter_accum(dl, &mfilt); 1183 } 1184 } 1185 #else 1186 static void 1187 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t (*mfilt)[2]) 1188 { 1189 struct ether_multi *enm; 1190 struct ether_multistep estep; 1191 1192 ETHER_FIRST_MULTI(estep, &sc->sc_ic.ic_ec, enm); 1193 while (enm != NULL) { 1194 /* XXX Punt on ranges. */ 1195 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1196 (*mfilt)[0] = (*mfilt)[1] = ~((u_int32_t)0); 1197 break; 1198 } 1199 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1200 ETHER_NEXT_MULTI(estep, enm); 1201 } 1202 } 1203 #endif 1204 1205 static void 1206 ath_mode_init(struct ath_softc *sc) 1207 { 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ath_hal *ah = sc->sc_ah; 1210 struct ifnet *ifp = &ic->ic_if; 1211 u_int32_t rfilt, mfilt[2]; 1212 1213 /* configure operational mode */ 1214 ath_hal_setopmode(ah, ic->ic_opmode); 1215 1216 /* receive filter */ 1217 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1218 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1219 if (ic->ic_opmode != IEEE80211_M_STA) 1220 rfilt |= HAL_RX_FILTER_PROBEREQ; 1221 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1222 (ifp->if_flags & IFF_PROMISC)) 1223 rfilt |= HAL_RX_FILTER_PROM; 1224 if (ic->ic_state == IEEE80211_S_SCAN) 1225 rfilt |= HAL_RX_FILTER_BEACON; 1226 ath_hal_setrxfilter(ah, rfilt); 1227 1228 /* calculate and install multicast filter */ 1229 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1230 mfilt[0] = mfilt[1] = 0; 1231 ath_mcastfilter_compute(sc, &mfilt); 1232 } else { 1233 mfilt[0] = mfilt[1] = ~0; 1234 } 1235 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1236 DPRINTF(("ath_mode_init: RX filter 0x%x, MC filter %08x:%08x\n", 1237 rfilt, mfilt[0], mfilt[1])); 1238 } 1239 1240 #ifdef __FreeBSD__ 1241 static void 1242 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 1243 { 1244 struct ath_buf *bf = arg; 1245 1246 KASSERT(nseg <= ATH_MAX_SCATTER, 1247 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 1248 bf->bf_mapsize = mapsize; 1249 bf->bf_nseg = nseg; 1250 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 1251 } 1252 #endif /* __FreeBSD__ */ 1253 1254 static struct mbuf * 1255 ath_getmbuf(int flags, int type, u_int pktlen) 1256 { 1257 struct mbuf *m; 1258 1259 KASSERT(pktlen <= MCLBYTES, ("802.11 packet too large: %u", pktlen)); 1260 #ifdef __FreeBSD__ 1261 if (pktlen <= MHLEN) 1262 MGETHDR(m, flags, type); 1263 else 1264 m = m_getcl(flags, type, M_PKTHDR); 1265 #else 1266 MGETHDR(m, flags, type); 1267 if (m != NULL && pktlen > MHLEN) 1268 MCLGET(m, flags); 1269 #endif 1270 return m; 1271 } 1272 1273 static int 1274 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1275 { 1276 struct ieee80211com *ic = &sc->sc_ic; 1277 struct ifnet *ifp = &ic->ic_if; 1278 struct ath_hal *ah = sc->sc_ah; 1279 struct ieee80211_frame *wh; 1280 struct ath_buf *bf; 1281 struct ath_desc *ds; 1282 struct mbuf *m; 1283 int error, pktlen; 1284 u_int8_t *frm, rate; 1285 u_int16_t capinfo; 1286 struct ieee80211_rateset *rs; 1287 const HAL_RATE_TABLE *rt; 1288 1289 bf = sc->sc_bcbuf; 1290 if (bf->bf_m != NULL) { 1291 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1292 m_freem(bf->bf_m); 1293 bf->bf_m = NULL; 1294 bf->bf_node = NULL; 1295 } 1296 /* 1297 * NB: the beacon data buffer must be 32-bit aligned; 1298 * we assume the mbuf routines will return us something 1299 * with this alignment (perhaps should assert). 1300 */ 1301 rs = &ni->ni_rates; 1302 pktlen = sizeof (struct ieee80211_frame) 1303 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 6; 1304 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 1305 pktlen += 2; 1306 m = ath_getmbuf(M_DONTWAIT, MT_DATA, pktlen); 1307 if (m == NULL) { 1308 DPRINTF(("ath_beacon_alloc: cannot get mbuf/cluster; size %u\n", 1309 pktlen)); 1310 sc->sc_stats.ast_be_nombuf++; 1311 return ENOMEM; 1312 } 1313 1314 wh = mtod(m, struct ieee80211_frame *); 1315 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1316 IEEE80211_FC0_SUBTYPE_BEACON; 1317 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1318 *(u_int16_t *)wh->i_dur = 0; 1319 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1320 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1321 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1322 *(u_int16_t *)wh->i_seq = 0; 1323 1324 /* 1325 * beacon frame format 1326 * [8] time stamp 1327 * [2] beacon interval 1328 * [2] cabability information 1329 * [tlv] ssid 1330 * [tlv] supported rates 1331 * [tlv] parameter set (IBSS) 1332 * [tlv] extended supported rates 1333 */ 1334 frm = (u_int8_t *)&wh[1]; 1335 memset(frm, 0, 8); /* timestamp is set by hardware */ 1336 frm += 8; 1337 *(u_int16_t *)frm = htole16(ni->ni_intval); 1338 frm += 2; 1339 if (ic->ic_opmode == IEEE80211_M_IBSS) 1340 capinfo = IEEE80211_CAPINFO_IBSS; 1341 else 1342 capinfo = IEEE80211_CAPINFO_ESS; 1343 if (ic->ic_flags & IEEE80211_F_WEPON) 1344 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1345 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1346 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1347 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1348 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1349 *(u_int16_t *)frm = htole16(capinfo); 1350 frm += 2; 1351 *frm++ = IEEE80211_ELEMID_SSID; 1352 *frm++ = ni->ni_esslen; 1353 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1354 frm += ni->ni_esslen; 1355 frm = ieee80211_add_rates(frm, rs); 1356 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1357 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1358 *frm++ = 2; 1359 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1360 } else { 1361 /* TODO: TIM */ 1362 *frm++ = IEEE80211_ELEMID_TIM; 1363 *frm++ = 4; /* length */ 1364 *frm++ = 0; /* DTIM count */ 1365 *frm++ = 1; /* DTIM period */ 1366 *frm++ = 0; /* bitmap control */ 1367 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1368 } 1369 frm = ieee80211_add_xrates(frm, rs); 1370 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1371 KASSERT(m->m_pkthdr.len <= pktlen, 1372 ("beacon bigger than expected, len %u calculated %u", 1373 m->m_pkthdr.len, pktlen)); 1374 1375 DPRINTF2(("ath_beacon_alloc: m %p len %u\n", m, m->m_len)); 1376 error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m, BUS_DMA_NOWAIT); 1377 if (error != 0) { 1378 m_freem(m); 1379 return error; 1380 } 1381 KASSERT(bf->bf_nseg == 1, 1382 ("ath_beacon_alloc: multi-segment packet; nseg %u", 1383 bf->bf_nseg)); 1384 bf->bf_m = m; 1385 1386 /* setup descriptors */ 1387 ds = bf->bf_desc; 1388 1389 ds->ds_link = 0; 1390 ds->ds_data = bf->bf_segs[0].ds_addr; 1391 1392 DPRINTF2(("%s: segaddr %p seglen %u\n", __func__, 1393 (caddr_t)bf->bf_segs[0].ds_addr, (u_int)bf->bf_segs[0].ds_len)); 1394 1395 /* 1396 * Calculate rate code. 1397 * XXX everything at min xmit rate 1398 */ 1399 rt = sc->sc_currates; 1400 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1401 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1402 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1403 else 1404 rate = rt->info[0].rateCode; 1405 if (!ath_hal_setuptxdesc(ah, ds 1406 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1407 , sizeof(struct ieee80211_frame) /* header length */ 1408 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1409 , 0x20 /* txpower XXX */ 1410 , rate, 1 /* series 0 rate/tries */ 1411 , HAL_TXKEYIX_INVALID /* no encryption */ 1412 , 0 /* antenna mode */ 1413 , HAL_TXDESC_NOACK /* no ack for beacons */ 1414 , 0 /* rts/cts rate */ 1415 , 0 /* rts/cts duration */ 1416 )) { 1417 printf("%s: ath_hal_setuptxdesc failed\n", __func__); 1418 return -1; 1419 } 1420 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1421 /* XXX verify mbuf data area covers this roundup */ 1422 if (!ath_hal_filltxdesc(ah, ds 1423 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1424 , AH_TRUE /* first segment */ 1425 , AH_TRUE /* last segment */ 1426 )) { 1427 printf("%s: ath_hal_filltxdesc failed\n", __func__); 1428 return -1; 1429 } 1430 1431 /* XXX it is not appropriate to bus_dmamap_sync? -dcy */ 1432 1433 return 0; 1434 } 1435 1436 static void 1437 ath_beacon_proc(void *arg, int pending) 1438 { 1439 struct ath_softc *sc = arg; 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 struct ath_buf *bf = sc->sc_bcbuf; 1442 struct ath_hal *ah = sc->sc_ah; 1443 1444 DPRINTF2(("%s: pending %u\n", __func__, pending)); 1445 if (ic->ic_opmode == IEEE80211_M_STA || 1446 bf == NULL || bf->bf_m == NULL) { 1447 DPRINTF(("%s: ic_flags=%x bf=%p bf_m=%p\n", 1448 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1449 return; 1450 } 1451 /* TODO: update beacon to reflect PS poll state */ 1452 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1453 DPRINTF(("%s: beacon queue %u did not stop?", 1454 __func__, sc->sc_bhalq)); 1455 return; /* busy, XXX is this right? */ 1456 } 1457 ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREWRITE); 1458 1459 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1460 ath_hal_txstart(ah, sc->sc_bhalq); 1461 DPRINTF2(("%s: BCDP%u = %p (%p)\n", __func__, 1462 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1463 } 1464 1465 static void 1466 ath_beacon_free(struct ath_softc *sc) 1467 { 1468 struct ath_buf *bf = sc->sc_bcbuf; 1469 1470 if (bf->bf_m != NULL) { 1471 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1472 m_freem(bf->bf_m); 1473 bf->bf_m = NULL; 1474 bf->bf_node = NULL; 1475 } 1476 } 1477 1478 /* 1479 * Configure the beacon and sleep timers. 1480 * 1481 * When operating as an AP this resets the TSF and sets 1482 * up the hardware to notify us when we need to issue beacons. 1483 * 1484 * When operating in station mode this sets up the beacon 1485 * timers according to the timestamp of the last received 1486 * beacon and the current TSF, configures PCF and DTIM 1487 * handling, programs the sleep registers so the hardware 1488 * will wakeup in time to receive beacons, and configures 1489 * the beacon miss handling so we'll receive a BMISS 1490 * interrupt when we stop seeing beacons from the AP 1491 * we've associated with. 1492 */ 1493 static void 1494 ath_beacon_config(struct ath_softc *sc) 1495 { 1496 struct ath_hal *ah = sc->sc_ah; 1497 struct ieee80211com *ic = &sc->sc_ic; 1498 struct ieee80211_node *ni = ic->ic_bss; 1499 u_int32_t nexttbtt; 1500 1501 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1502 (LE_READ_4(ni->ni_tstamp) >> 10); 1503 DPRINTF(("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1504 nexttbtt += ni->ni_intval; 1505 if (ic->ic_opmode == IEEE80211_M_STA) { 1506 HAL_BEACON_STATE bs; 1507 u_int32_t bmisstime; 1508 1509 /* NB: no PCF support right now */ 1510 memset(&bs, 0, sizeof(bs)); 1511 bs.bs_intval = ni->ni_intval; 1512 bs.bs_nexttbtt = nexttbtt; 1513 bs.bs_dtimperiod = bs.bs_intval; 1514 bs.bs_nextdtim = nexttbtt; 1515 /* 1516 * Calculate the number of consecutive beacons to miss 1517 * before taking a BMISS interrupt. The configuration 1518 * is specified in ms, so we need to convert that to 1519 * TU's and then calculate based on the beacon interval. 1520 * Note that we clamp the result to at most 10 beacons. 1521 */ 1522 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1523 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1524 if (bs.bs_bmissthreshold > 10) 1525 bs.bs_bmissthreshold = 10; 1526 else if (bs.bs_bmissthreshold <= 0) 1527 bs.bs_bmissthreshold = 1; 1528 1529 /* 1530 * Calculate sleep duration. The configuration is 1531 * given in ms. We insure a multiple of the beacon 1532 * period is used. Also, if the sleep duration is 1533 * greater than the DTIM period then it makes senses 1534 * to make it a multiple of that. 1535 * 1536 * XXX fixed at 100ms 1537 */ 1538 bs.bs_sleepduration = 1539 roundup((100 * 1000) / 1024, bs.bs_intval); 1540 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1541 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1542 1543 DPRINTF(("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1544 , __func__ 1545 , bs.bs_intval 1546 , bs.bs_nexttbtt 1547 , bs.bs_dtimperiod 1548 , bs.bs_nextdtim 1549 , bs.bs_bmissthreshold 1550 , bs.bs_sleepduration 1551 )); 1552 ath_hal_intrset(ah, 0); 1553 /* 1554 * Reset our tsf so the hardware will update the 1555 * tsf register to reflect timestamps found in 1556 * received beacons. 1557 */ 1558 ath_hal_resettsf(ah); 1559 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1560 sc->sc_imask |= HAL_INT_BMISS; 1561 ath_hal_intrset(ah, sc->sc_imask); 1562 } else { 1563 DPRINTF(("%s: intval %u nexttbtt %u\n", 1564 __func__, ni->ni_intval, nexttbtt)); 1565 ath_hal_intrset(ah, 0); 1566 ath_hal_beaconinit(ah, ic->ic_opmode, 1567 nexttbtt, ni->ni_intval); 1568 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1569 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1570 ath_hal_intrset(ah, sc->sc_imask); 1571 } 1572 } 1573 1574 #ifdef __FreeBSD__ 1575 static void 1576 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1577 { 1578 bus_addr_t *paddr = (bus_addr_t*) arg; 1579 *paddr = segs->ds_addr; 1580 } 1581 #endif 1582 1583 #ifdef __FreeBSD__ 1584 static int 1585 ath_desc_alloc(struct ath_softc *sc) 1586 { 1587 int i, bsize, error; 1588 struct ath_desc *ds; 1589 struct ath_buf *bf; 1590 1591 /* allocate descriptors */ 1592 sc->sc_desc_len = sizeof(struct ath_desc) * 1593 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1594 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1595 if (error != 0) 1596 return error; 1597 1598 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1599 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1600 1601 if (error != 0) 1602 goto fail0; 1603 1604 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1605 sc->sc_desc, sc->sc_desc_len, 1606 ath_load_cb, &sc->sc_desc_paddr, 1607 BUS_DMA_NOWAIT); 1608 if (error != 0) 1609 goto fail1; 1610 1611 ds = sc->sc_desc; 1612 DPRINTF(("ath_desc_alloc: DMA map: %p (%d) -> %p (%lu)\n", 1613 ds, sc->sc_desc_len, 1614 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1615 1616 /* allocate buffers */ 1617 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1618 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1619 if (bf == NULL) { 1620 printf("%s: unable to allocate Tx/Rx buffers\n", 1621 sc->sc_dev.dv_xname); 1622 error = -1; 1623 goto fail2; 1624 } 1625 sc->sc_bufptr = bf; 1626 1627 TAILQ_INIT(&sc->sc_rxbuf); 1628 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1629 bf->bf_desc = ds; 1630 bf->bf_daddr = sc->sc_desc_paddr + 1631 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1632 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1633 &bf->bf_dmamap); 1634 if (error != 0) 1635 break; 1636 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1637 } 1638 1639 TAILQ_INIT(&sc->sc_txbuf); 1640 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1641 bf->bf_desc = ds; 1642 bf->bf_daddr = sc->sc_desc_paddr + 1643 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1644 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1645 &bf->bf_dmamap); 1646 if (error != 0) 1647 break; 1648 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1649 } 1650 TAILQ_INIT(&sc->sc_txq); 1651 1652 /* beacon buffer */ 1653 bf->bf_desc = ds; 1654 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1655 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1656 if (error != 0) 1657 return error; 1658 sc->sc_bcbuf = bf; 1659 return 0; 1660 1661 fail2: 1662 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1663 fail1: 1664 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1665 fail0: 1666 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1667 sc->sc_ddmamap = NULL; 1668 return error; 1669 } 1670 #else 1671 static int 1672 ath_desc_alloc(struct ath_softc *sc) 1673 { 1674 int i, bsize, error = -1; 1675 struct ath_desc *ds; 1676 struct ath_buf *bf; 1677 1678 /* allocate descriptors */ 1679 sc->sc_desc_len = sizeof(struct ath_desc) * 1680 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1681 if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_desc_len, PAGE_SIZE, 1682 0, &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 1683 printf("%s: unable to allocate control data, error = %d\n", 1684 sc->sc_dev.dv_xname, error); 1685 goto fail0; 1686 } 1687 1688 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 1689 sc->sc_desc_len, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT)) != 0) { 1690 printf("%s: unable to map control data, error = %d\n", 1691 sc->sc_dev.dv_xname, error); 1692 goto fail1; 1693 } 1694 1695 if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_desc_len, 1, 1696 sc->sc_desc_len, 0, 0, &sc->sc_ddmamap)) != 0) { 1697 printf("%s: unable to create control data DMA map, " 1698 "error = %d\n", sc->sc_dev.dv_xname, error); 1699 goto fail2; 1700 } 1701 1702 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 1703 sc->sc_desc_len, NULL, 0)) != 0) { 1704 printf("%s: unable to load control data DMA map, error = %d\n", 1705 sc->sc_dev.dv_xname, error); 1706 goto fail3; 1707 } 1708 1709 ds = sc->sc_desc; 1710 sc->sc_desc_paddr = sc->sc_ddmamap->dm_segs[0].ds_addr; 1711 1712 DPRINTF(("ath_desc_alloc: DMA map: %p (%lu) -> %p (%lu)\n", 1713 ds, (u_long)sc->sc_desc_len, 1714 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1715 1716 /* allocate buffers */ 1717 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1718 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1719 if (bf == NULL) { 1720 printf("%s: unable to allocate Tx/Rx buffers\n", 1721 sc->sc_dev.dv_xname); 1722 error = ENOMEM; 1723 goto fail3; 1724 } 1725 sc->sc_bufptr = bf; 1726 1727 TAILQ_INIT(&sc->sc_rxbuf); 1728 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1729 bf->bf_desc = ds; 1730 bf->bf_daddr = sc->sc_desc_paddr + 1731 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1732 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1733 MCLBYTES, 0, 0, &bf->bf_dmamap)) != 0) { 1734 printf("%s: unable to create Rx dmamap, error = %d\n", 1735 sc->sc_dev.dv_xname, error); 1736 goto fail4; 1737 } 1738 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1739 } 1740 1741 TAILQ_INIT(&sc->sc_txbuf); 1742 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1743 bf->bf_desc = ds; 1744 bf->bf_daddr = sc->sc_desc_paddr + 1745 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1746 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1747 ATH_TXDESC, MCLBYTES, 0, 0, &bf->bf_dmamap)) != 0) { 1748 printf("%s: unable to create Tx dmamap, error = %d\n", 1749 sc->sc_dev.dv_xname, error); 1750 goto fail5; 1751 } 1752 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1753 } 1754 TAILQ_INIT(&sc->sc_txq); 1755 1756 /* beacon buffer */ 1757 bf->bf_desc = ds; 1758 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1759 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 1760 &bf->bf_dmamap)) != 0) { 1761 printf("%s: unable to create beacon dmamap, error = %d\n", 1762 sc->sc_dev.dv_xname, error); 1763 goto fail5; 1764 } 1765 sc->sc_bcbuf = bf; 1766 return 0; 1767 1768 fail5: 1769 for (i = ATH_RXBUF; i < ATH_RXBUF + ATH_TXBUF; i++) { 1770 if (sc->sc_bufptr[i].bf_dmamap == NULL) 1771 continue; 1772 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufptr[i].bf_dmamap); 1773 } 1774 fail4: 1775 for (i = 0; i < ATH_RXBUF; i++) { 1776 if (sc->sc_bufptr[i].bf_dmamap == NULL) 1777 continue; 1778 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufptr[i].bf_dmamap); 1779 } 1780 fail3: 1781 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1782 fail2: 1783 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1784 sc->sc_ddmamap = NULL; 1785 fail1: 1786 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, sc->sc_desc_len); 1787 fail0: 1788 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 1789 return error; 1790 } 1791 #endif 1792 1793 static void 1794 ath_desc_free(struct ath_softc *sc) 1795 { 1796 struct ath_buf *bf; 1797 1798 #ifdef __FreeBSD__ 1799 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1800 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1801 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1802 #else 1803 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1804 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1805 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 1806 #endif 1807 1808 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1809 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1810 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1811 m_freem(bf->bf_m); 1812 } 1813 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1814 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1815 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1816 if (bf->bf_m) { 1817 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1818 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1819 m_freem(bf->bf_m); 1820 bf->bf_m = NULL; 1821 } 1822 } 1823 if (sc->sc_bcbuf != NULL) { 1824 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1825 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1826 sc->sc_bcbuf = NULL; 1827 } 1828 1829 TAILQ_INIT(&sc->sc_rxbuf); 1830 TAILQ_INIT(&sc->sc_txbuf); 1831 TAILQ_INIT(&sc->sc_txq); 1832 free(sc->sc_bufptr, M_DEVBUF); 1833 sc->sc_bufptr = NULL; 1834 } 1835 1836 static struct ieee80211_node * 1837 ath_node_alloc(struct ieee80211com *ic) 1838 { 1839 struct ath_node *an = 1840 malloc(sizeof(struct ath_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1841 return an ? &an->an_node : NULL; 1842 } 1843 1844 static void 1845 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1846 { 1847 struct ath_softc *sc = ic->ic_if.if_softc; 1848 struct ath_buf *bf; 1849 1850 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1851 if (bf->bf_node == ni) 1852 bf->bf_node = NULL; 1853 } 1854 free(ni, M_DEVBUF); 1855 } 1856 1857 static void 1858 ath_node_copy(struct ieee80211com *ic, 1859 struct ieee80211_node *dst, const struct ieee80211_node *src) 1860 { 1861 *(struct ath_node *)dst = *(const struct ath_node *)src; 1862 } 1863 1864 static int 1865 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1866 { 1867 struct ath_hal *ah = sc->sc_ah; 1868 int error; 1869 struct mbuf *m; 1870 struct ath_desc *ds; 1871 1872 m = bf->bf_m; 1873 if (m == NULL) { 1874 /* 1875 * NB: by assigning a page to the rx dma buffer we 1876 * implicitly satisfy the Atheros requirement that 1877 * this buffer be cache-line-aligned and sized to be 1878 * multiple of the cache line size. Not doing this 1879 * causes weird stuff to happen (for the 5210 at least). 1880 */ 1881 m = ath_getmbuf(M_DONTWAIT, MT_DATA, MCLBYTES); 1882 if (m == NULL) { 1883 DPRINTF(("ath_rxbuf_init: no mbuf/cluster\n")); 1884 sc->sc_stats.ast_rx_nombuf++; 1885 return ENOMEM; 1886 } 1887 bf->bf_m = m; 1888 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1889 1890 error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m, 1891 BUS_DMA_NOWAIT); 1892 if (error != 0) { 1893 DPRINTF(("ath_rxbuf_init: ath_buf_dmamap_load_mbuf failed;" 1894 " error %d\n", error)); 1895 sc->sc_stats.ast_rx_busdma++; 1896 return error; 1897 } 1898 KASSERT(bf->bf_nseg == 1, 1899 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1900 bf->bf_nseg)); 1901 } 1902 ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREREAD); 1903 1904 /* setup descriptors */ 1905 ds = bf->bf_desc; 1906 ds->ds_link = 0; 1907 ds->ds_data = bf->bf_segs[0].ds_addr; 1908 ath_hal_setuprxdesc(ah, ds 1909 , m->m_len /* buffer size */ 1910 , 0 1911 ); 1912 1913 if (sc->sc_rxlink != NULL) 1914 *sc->sc_rxlink = bf->bf_daddr; 1915 sc->sc_rxlink = &ds->ds_link; 1916 return 0; 1917 } 1918 1919 static void 1920 ath_rx_proc(void *arg, int npending) 1921 { 1922 struct ath_softc *sc = arg; 1923 struct ath_buf *bf; 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 struct ifnet *ifp = &ic->ic_if; 1926 struct ath_hal *ah = sc->sc_ah; 1927 struct ath_desc *ds; 1928 struct mbuf *m; 1929 struct ieee80211_frame *wh, whbuf; 1930 struct ieee80211_node *ni; 1931 int len; 1932 u_int phyerr; 1933 HAL_STATUS status; 1934 1935 DPRINTF2(("ath_rx_proc: pending %u\n", npending)); 1936 do { 1937 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1938 if (bf == NULL) { /* NB: shouldn't happen */ 1939 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1940 break; 1941 } 1942 m = bf->bf_m; 1943 if (m == NULL) { /* NB: shouldn't happen */ 1944 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1945 continue; 1946 } 1947 ds = bf->bf_desc; 1948 status = ath_hal_rxprocdesc(ah, ds); 1949 #ifdef AR_DEBUG 1950 if (ath_debug > 1) 1951 ath_printrxbuf(bf, status == HAL_OK); 1952 #endif 1953 if (status == HAL_EINPROGRESS) 1954 break; 1955 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1956 if (ds->ds_rxstat.rs_status != 0) { 1957 ifp->if_ierrors++; 1958 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1959 sc->sc_stats.ast_rx_crcerr++; 1960 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1961 sc->sc_stats.ast_rx_fifoerr++; 1962 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1963 sc->sc_stats.ast_rx_badcrypt++; 1964 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1965 sc->sc_stats.ast_rx_phyerr++; 1966 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1967 sc->sc_stats.ast_rx_phy[phyerr]++; 1968 } 1969 goto rx_next; 1970 } 1971 1972 len = ds->ds_rxstat.rs_datalen; 1973 if (len < sizeof(struct ieee80211_frame)) { 1974 DPRINTF(("ath_rx_proc: short packet %d\n", len)); 1975 sc->sc_stats.ast_rx_tooshort++; 1976 goto rx_next; 1977 } 1978 1979 ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_POSTREAD); 1980 1981 wh = mtod(m, struct ieee80211_frame *); 1982 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1983 IEEE80211_FC0_TYPE_CTL && 1984 ic->ic_opmode != IEEE80211_M_MONITOR) { 1985 /* 1986 * Discard control frame when not in monitor mode. 1987 */ 1988 DPRINTF(("ath_rx_proc: control frame\n")); 1989 sc->sc_stats.ast_rx_ctl++; 1990 goto rx_next; 1991 } 1992 1993 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1994 bf->bf_m = NULL; 1995 m->m_pkthdr.rcvif = ifp; 1996 m->m_pkthdr.len = m->m_len = len; 1997 1998 #if NBPFILTER > 0 1999 if (sc->sc_drvbpf) { 2000 #ifdef __FreeBSD__ 2001 struct mbuf *mb; 2002 2003 /* XXX pre-allocate space when setting up recv's */ 2004 MGETHDR(mb, M_DONTWAIT, m->m_type); 2005 if (mb != NULL) { 2006 sc->sc_rx_th.wr_rate = 2007 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 2008 sc->sc_rx_th.wr_antsignal = 2009 ds->ds_rxstat.rs_rssi; 2010 sc->sc_rx_th.wr_antenna = 2011 ds->ds_rxstat.rs_antenna; 2012 /* XXX TSF */ 2013 2014 (void) m_dup_pkthdr(mb, m, M_DONTWAIT); 2015 mb->m_next = m; 2016 mb->m_data = (caddr_t)&sc->sc_rx_th; 2017 mb->m_len = sizeof(sc->sc_rx_th); 2018 mb->m_pkthdr.len += mb->m_len; 2019 bpf_mtap(sc->sc_drvbpf, mb); 2020 m_free(mb); 2021 } 2022 #else 2023 /* XXX pre-allocate space when setting up recv's */ 2024 struct mbuf mb; 2025 2026 sc->sc_rx_th.wr_rate = 2027 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 2028 sc->sc_rx_th.wr_antsignal = 2029 ds->ds_rxstat.rs_rssi; 2030 sc->sc_rx_th.wr_antenna = 2031 ds->ds_rxstat.rs_antenna; 2032 /* XXX TSF */ 2033 2034 M_COPY_PKTHDR(&mb, m); 2035 mb.m_next = m; 2036 mb.m_data = (caddr_t)&sc->sc_rx_th; 2037 mb.m_len = sizeof(sc->sc_rx_th); 2038 mb.m_pkthdr.len += mb.m_len; 2039 bpf_mtap(sc->sc_drvbpf, &mb); 2040 #endif 2041 } 2042 #endif 2043 2044 m_adj(m, -IEEE80211_CRC_LEN); 2045 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2046 /* 2047 * WEP is decrypted by hardware. Clear WEP bit 2048 * and trim WEP header for ieee80211_input(). 2049 */ 2050 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2051 memcpy(&whbuf, wh, sizeof(whbuf)); 2052 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 2053 memcpy(mtod(m, caddr_t), &whbuf, sizeof(whbuf)); 2054 /* 2055 * Also trim WEP ICV from the tail. 2056 */ 2057 m_adj(m, -IEEE80211_WEP_CRCLEN); 2058 } 2059 2060 /* 2061 * Locate the node for sender, track state, and 2062 * then pass this node (referenced) up to the 802.11 2063 * layer for its use. We are required to pass 2064 * something so we fall back to ic_bss when this frame 2065 * is from an unknown sender. 2066 */ 2067 if (ic->ic_opmode != IEEE80211_M_STA) { 2068 ni = ieee80211_find_node(ic, wh->i_addr2); 2069 if (ni == NULL) 2070 ni = ieee80211_ref_node(ic->ic_bss); 2071 } else 2072 ni = ieee80211_ref_node(ic->ic_bss); 2073 ATH_NODE(ni)->an_rx_antenna = ds->ds_rxstat.rs_antenna; 2074 /* 2075 * Send frame up for processing. 2076 */ 2077 ieee80211_input(ifp, m, ni, 2078 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2079 /* 2080 * The frame may have caused the node to be marked for 2081 * reclamation (e.g. in response to a DEAUTH message) 2082 * so use free_node here instead of unref_node. 2083 */ 2084 if (ni == ic->ic_bss) 2085 ieee80211_unref_node(&ni); 2086 else 2087 ieee80211_free_node(ic, ni); 2088 rx_next: 2089 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2090 } while (ath_rxbuf_init(sc, bf) == 0); 2091 2092 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 2093 ath_hal_rxena(ah); /* in case of RXEOL */ 2094 } 2095 2096 /* 2097 * XXX Size of an ACK control frame in bytes. 2098 */ 2099 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 2100 2101 static int 2102 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 2103 struct mbuf *m0) 2104 { 2105 struct ieee80211com *ic = &sc->sc_ic; 2106 struct ath_hal *ah = sc->sc_ah; 2107 struct ifnet *ifp = &sc->sc_ic.ic_if; 2108 int i, error, iswep, hdrlen, pktlen; 2109 u_int8_t rix, cix, txrate, ctsrate; 2110 struct ath_desc *ds; 2111 struct mbuf *m; 2112 struct ieee80211_frame *wh; 2113 u_int32_t iv; 2114 u_int8_t *ivp; 2115 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 2116 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 2117 u_int subtype, flags, ctsduration, antenna; 2118 HAL_PKT_TYPE atype; 2119 const HAL_RATE_TABLE *rt; 2120 HAL_BOOL shortPreamble; 2121 struct ath_node *an; 2122 ath_txq_critsect_decl(s); 2123 2124 wh = mtod(m0, struct ieee80211_frame *); 2125 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 2126 hdrlen = sizeof(struct ieee80211_frame); 2127 pktlen = m0->m_pkthdr.len; 2128 2129 if (iswep) { 2130 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 2131 m_adj(m0, hdrlen); 2132 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 2133 if (m0 == NULL) { 2134 sc->sc_stats.ast_tx_nombuf++; 2135 return ENOMEM; 2136 } 2137 ivp = hdrbuf + hdrlen; 2138 /* 2139 * XXX 2140 * IV must not duplicate during the lifetime of the key. 2141 * But no mechanism to renew keys is defined in IEEE 802.11 2142 * WEP. And IV may be duplicated between other stations 2143 * because of the session key itself is shared. 2144 * So we use pseudo random IV for now, though it is not the 2145 * right way. 2146 */ 2147 iv = arc4random(); 2148 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 2149 ivp[i] = iv; 2150 iv >>= 8; 2151 } 2152 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 2153 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 2154 /* 2155 * The ICV length must be included into hdrlen and pktlen. 2156 */ 2157 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 2158 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 2159 } 2160 pktlen += IEEE80211_CRC_LEN; 2161 2162 /* 2163 * Load the DMA map so any coalescing is done. This 2164 * also calculates the number of descriptors we need. 2165 */ 2166 error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m0, BUS_DMA_NOWAIT); 2167 if (error != 0) { 2168 sc->sc_stats.ast_tx_busdma++; 2169 m_freem(m0); 2170 return error; 2171 } 2172 /* 2173 * Discard null packets and check for packets that 2174 * require too many TX descriptors. We try to convert 2175 * the latter to a cluster. 2176 */ 2177 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 2178 sc->sc_stats.ast_tx_linear++; 2179 MGETHDR(m, M_DONTWAIT, MT_DATA); 2180 if (m == NULL) { 2181 sc->sc_stats.ast_tx_nombuf++; 2182 m_freem(m0); 2183 return ENOMEM; 2184 } 2185 #ifdef __FreeBSD__ 2186 M_MOVE_PKTHDR(m, m0); 2187 #else 2188 M_COPY_PKTHDR(m, m0); 2189 #endif 2190 MCLGET(m, M_DONTWAIT); 2191 if ((m->m_flags & M_EXT) == 0) { 2192 sc->sc_stats.ast_tx_nomcl++; 2193 m_freem(m0); 2194 m_free(m); 2195 return ENOMEM; 2196 } 2197 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2198 m_freem(m0); 2199 m->m_len = m->m_pkthdr.len; 2200 m0 = m; 2201 error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m0, 2202 BUS_DMA_NOWAIT); 2203 if (error != 0) { 2204 sc->sc_stats.ast_tx_busdma++; 2205 m_freem(m0); 2206 return error; 2207 } 2208 KASSERT(bf->bf_nseg == 1, 2209 ("ath_tx_start: packet not one segment; nseg %u", 2210 bf->bf_nseg)); 2211 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 2212 sc->sc_stats.ast_tx_nodata++; 2213 m_freem(m0); 2214 return EIO; 2215 } 2216 DPRINTF2(("ath_tx_start: m %p len %u\n", m0, pktlen)); 2217 ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREWRITE); 2218 bf->bf_m = m0; 2219 bf->bf_node = ni; /* NB: held reference */ 2220 2221 /* setup descriptors */ 2222 ds = bf->bf_desc; 2223 rt = sc->sc_currates; 2224 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 2225 2226 /* 2227 * Calculate Atheros packet type from IEEE80211 packet header 2228 * and setup for rate calculations. 2229 */ 2230 atype = HAL_PKT_TYPE_NORMAL; /* default */ 2231 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 2232 case IEEE80211_FC0_TYPE_MGT: 2233 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2234 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 2235 atype = HAL_PKT_TYPE_BEACON; 2236 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2237 atype = HAL_PKT_TYPE_PROBE_RESP; 2238 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 2239 atype = HAL_PKT_TYPE_ATIM; 2240 rix = 0; /* XXX lowest rate */ 2241 break; 2242 case IEEE80211_FC0_TYPE_CTL: 2243 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2244 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 2245 atype = HAL_PKT_TYPE_PSPOLL; 2246 rix = 0; /* XXX lowest rate */ 2247 break; 2248 default: 2249 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 2250 IEEE80211_RATE_VAL]; 2251 if (rix == 0xff) { 2252 if_printf(ifp, "bogus xmit rate 0x%x\n", 2253 ni->ni_rates.rs_rates[ni->ni_txrate]); 2254 sc->sc_stats.ast_tx_badrate++; 2255 m_freem(m0); 2256 return EIO; 2257 } 2258 break; 2259 } 2260 /* 2261 * NB: the 802.11 layer marks whether or not we should 2262 * use short preamble based on the current mode and 2263 * negotiated parameters. 2264 */ 2265 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) { 2266 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 2267 shortPreamble = AH_TRUE; 2268 sc->sc_stats.ast_tx_shortpre++; 2269 } else { 2270 txrate = rt->info[rix].rateCode; 2271 shortPreamble = AH_FALSE; 2272 } 2273 2274 /* 2275 * Calculate miscellaneous flags. 2276 */ 2277 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 2278 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2279 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 2280 sc->sc_stats.ast_tx_noack++; 2281 } else if (pktlen > ic->ic_rtsthreshold) { 2282 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 2283 sc->sc_stats.ast_tx_rts++; 2284 } 2285 2286 /* 2287 * Calculate RTS/CTS rate and duration if needed. 2288 */ 2289 ctsduration = 0; 2290 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 2291 /* 2292 * CTS transmit rate is derived from the transmit rate 2293 * by looking in the h/w rate table. We must also factor 2294 * in whether or not a short preamble is to be used. 2295 */ 2296 cix = rt->info[rix].controlRate; 2297 ctsrate = rt->info[cix].rateCode; 2298 if (shortPreamble) 2299 ctsrate |= rt->info[cix].shortPreamble; 2300 /* 2301 * Compute the transmit duration based on the size 2302 * of an ACK frame. We call into the HAL to do the 2303 * computation since it depends on the characteristics 2304 * of the actual PHY being used. 2305 */ 2306 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 2307 ctsduration += ath_hal_computetxtime(ah, 2308 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2309 } 2310 /* SIFS + data */ 2311 ctsduration += ath_hal_computetxtime(ah, 2312 rt, pktlen, rix, shortPreamble); 2313 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 2314 ctsduration += ath_hal_computetxtime(ah, 2315 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2316 } 2317 } else 2318 ctsrate = 0; 2319 2320 /* 2321 * For now use the antenna on which the last good 2322 * frame was received on. We assume this field is 2323 * initialized to 0 which gives us ``auto'' or the 2324 * ``default'' antenna. 2325 */ 2326 an = (struct ath_node *) ni; 2327 if (an->an_tx_antenna) 2328 antenna = an->an_tx_antenna; 2329 else 2330 antenna = an->an_rx_antenna; 2331 2332 /* 2333 * Formulate first tx descriptor with tx controls. 2334 */ 2335 /* XXX check return value? */ 2336 ath_hal_setuptxdesc(ah, ds 2337 , pktlen /* packet length */ 2338 , hdrlen /* header length */ 2339 , atype /* Atheros packet type */ 2340 , 60 /* txpower XXX */ 2341 , txrate, 1+10 /* series 0 rate/tries */ 2342 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 2343 , antenna /* antenna mode */ 2344 , flags /* flags */ 2345 , ctsrate /* rts/cts rate */ 2346 , ctsduration /* rts/cts duration */ 2347 ); 2348 #ifdef notyet 2349 ath_hal_setupxtxdesc(ah, ds 2350 , AH_FALSE /* short preamble */ 2351 , 0, 0 /* series 1 rate/tries */ 2352 , 0, 0 /* series 2 rate/tries */ 2353 , 0, 0 /* series 3 rate/tries */ 2354 ); 2355 #endif 2356 /* 2357 * Fillin the remainder of the descriptor info. 2358 */ 2359 for (i = 0; i < bf->bf_nseg; i++, ds++) { 2360 ds->ds_data = bf->bf_segs[i].ds_addr; 2361 if (i == bf->bf_nseg - 1) 2362 ds->ds_link = 0; 2363 else 2364 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 2365 ath_hal_filltxdesc(ah, ds 2366 , bf->bf_segs[i].ds_len /* segment length */ 2367 , i == 0 /* first segment */ 2368 , i == bf->bf_nseg - 1 /* last segment */ 2369 ); 2370 DPRINTF2(("ath_tx_start: %d: %08x %08x %08x %08x %08x %08x\n", 2371 i, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, 2372 ds->ds_hw[0], ds->ds_hw[1])); 2373 } 2374 2375 /* 2376 * Insert the frame on the outbound list and 2377 * pass it on to the hardware. 2378 */ 2379 ath_txq_critsect_begin(sc, s); 2380 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 2381 if (sc->sc_txlink == NULL) { 2382 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 2383 DPRINTF2(("ath_tx_start: TXDP0 = %p (%p)\n", 2384 (caddr_t)bf->bf_daddr, bf->bf_desc)); 2385 } else { 2386 *sc->sc_txlink = bf->bf_daddr; 2387 DPRINTF2(("ath_tx_start: link(%p)=%p (%p)\n", 2388 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 2389 } 2390 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 2391 ath_txq_critsect_end(sc, s); 2392 2393 ath_hal_txstart(ah, sc->sc_txhalq); 2394 return 0; 2395 } 2396 2397 static void 2398 ath_tx_proc(void *arg, int npending) 2399 { 2400 struct ath_softc *sc = arg; 2401 struct ath_hal *ah = sc->sc_ah; 2402 struct ath_buf *bf; 2403 struct ieee80211com *ic = &sc->sc_ic; 2404 struct ifnet *ifp = &ic->ic_if; 2405 struct ath_desc *ds; 2406 struct ieee80211_node *ni; 2407 struct ath_node *an; 2408 int sr, lr; 2409 HAL_STATUS status; 2410 ath_txq_critsect_decl(s); 2411 ath_txbuf_critsect_decl(s2); 2412 2413 DPRINTF2(("ath_tx_proc: pending %u tx queue %p, link %p\n", 2414 npending, (caddr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 2415 sc->sc_txlink)); 2416 for (;;) { 2417 ath_txq_critsect_begin(sc, s); 2418 bf = TAILQ_FIRST(&sc->sc_txq); 2419 if (bf == NULL) { 2420 sc->sc_txlink = NULL; 2421 ath_txq_critsect_end(sc, s); 2422 break; 2423 } 2424 /* only the last descriptor is needed */ 2425 ds = &bf->bf_desc[bf->bf_nseg - 1]; 2426 status = ath_hal_txprocdesc(ah, ds); 2427 #ifdef AR_DEBUG 2428 if (ath_debug > 1) 2429 ath_printtxbuf(bf, status == HAL_OK); 2430 #endif 2431 if (status == HAL_EINPROGRESS) { 2432 ath_txq_critsect_end(sc, s); 2433 break; 2434 } 2435 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2436 ath_txq_critsect_end(sc, s); 2437 2438 ni = bf->bf_node; 2439 if (ni != NULL) { 2440 an = (struct ath_node *) ni; 2441 if (ds->ds_txstat.ts_status == 0) { 2442 an->an_tx_ok++; 2443 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 2444 } else { 2445 an->an_tx_err++; 2446 ifp->if_oerrors++; 2447 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 2448 sc->sc_stats.ast_tx_xretries++; 2449 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 2450 sc->sc_stats.ast_tx_fifoerr++; 2451 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 2452 sc->sc_stats.ast_tx_filtered++; 2453 an->an_tx_antenna = 0; /* invalidate */ 2454 } 2455 sr = ds->ds_txstat.ts_shortretry; 2456 lr = ds->ds_txstat.ts_longretry; 2457 sc->sc_stats.ast_tx_shortretry += sr; 2458 sc->sc_stats.ast_tx_longretry += lr; 2459 if (sr + lr) 2460 an->an_tx_retr++; 2461 /* 2462 * Reclaim reference to node. 2463 * 2464 * NB: the node may be reclaimed here if, for example 2465 * this is a DEAUTH message that was sent and the 2466 * node was timed out due to inactivity. 2467 */ 2468 if (ni != ic->ic_bss) 2469 ieee80211_free_node(ic, ni); 2470 } 2471 ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_POSTWRITE); 2472 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2473 m_freem(bf->bf_m); 2474 bf->bf_m = NULL; 2475 bf->bf_node = NULL; 2476 2477 ath_txbuf_critsect_begin(sc, s2); 2478 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2479 ath_txbuf_critsect_end(sc, s2); 2480 } 2481 ifp->if_flags &= ~IFF_OACTIVE; 2482 sc->sc_tx_timer = 0; 2483 2484 ath_start(ifp); 2485 } 2486 2487 /* 2488 * Drain the transmit queue and reclaim resources. 2489 */ 2490 static void 2491 ath_draintxq(struct ath_softc *sc) 2492 { 2493 struct ath_hal *ah = sc->sc_ah; 2494 struct ifnet *ifp = &sc->sc_ic.ic_if; 2495 struct ath_buf *bf; 2496 ath_txq_critsect_decl(s); 2497 ath_txbuf_critsect_decl(s2); 2498 2499 /* XXX return value */ 2500 if (!sc->sc_invalid) { 2501 /* don't touch the hardware if marked invalid */ 2502 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2503 DPRINTF(("ath_draintxq: tx queue %p, link %p\n", 2504 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2505 sc->sc_txlink)); 2506 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2507 DPRINTF(("ath_draintxq: beacon queue %p\n", 2508 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2509 } 2510 for (;;) { 2511 ath_txq_critsect_begin(sc, s); 2512 bf = TAILQ_FIRST(&sc->sc_txq); 2513 if (bf == NULL) { 2514 sc->sc_txlink = NULL; 2515 ath_txq_critsect_end(sc, s); 2516 break; 2517 } 2518 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2519 ath_txq_critsect_end(sc, s); 2520 #ifdef AR_DEBUG 2521 if (ath_debug) 2522 ath_printtxbuf(bf, 2523 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2524 #endif /* AR_DEBUG */ 2525 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2526 m_freem(bf->bf_m); 2527 bf->bf_m = NULL; 2528 bf->bf_node = NULL; 2529 ath_txbuf_critsect_begin(sc, s2); 2530 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2531 ath_txbuf_critsect_end(sc, s2); 2532 } 2533 ifp->if_flags &= ~IFF_OACTIVE; 2534 sc->sc_tx_timer = 0; 2535 } 2536 2537 /* 2538 * Disable the receive h/w in preparation for a reset. 2539 */ 2540 static void 2541 ath_stoprecv(struct ath_softc *sc) 2542 { 2543 struct ath_hal *ah = sc->sc_ah; 2544 2545 ath_hal_stoppcurecv(ah); /* disable PCU */ 2546 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2547 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2548 DELAY(3000); /* long enough for 1 frame */ 2549 #ifdef AR_DEBUG 2550 if (ath_debug) { 2551 struct ath_buf *bf; 2552 2553 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n", 2554 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink)); 2555 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2556 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK) 2557 ath_printrxbuf(bf, 1); 2558 } 2559 } 2560 #endif 2561 sc->sc_rxlink = NULL; /* just in case */ 2562 } 2563 2564 /* 2565 * Enable the receive h/w following a reset. 2566 */ 2567 static int 2568 ath_startrecv(struct ath_softc *sc) 2569 { 2570 struct ath_hal *ah = sc->sc_ah; 2571 struct ath_buf *bf; 2572 2573 sc->sc_rxlink = NULL; 2574 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2575 int error = ath_rxbuf_init(sc, bf); 2576 if (error != 0) { 2577 DPRINTF(("ath_startrecv: ath_rxbuf_init failed %d\n", 2578 error)); 2579 return error; 2580 } 2581 } 2582 2583 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2584 ath_hal_putrxbuf(ah, bf->bf_daddr); 2585 ath_hal_rxena(ah); /* enable recv descriptors */ 2586 ath_mode_init(sc); /* set filters, etc. */ 2587 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2588 return 0; 2589 } 2590 2591 /* 2592 * Set/change channels. If the channel is really being changed, 2593 * it's done by resetting the chip. To accomplish this we must 2594 * first cleanup any pending DMA, then restart stuff after a la 2595 * ath_init. 2596 */ 2597 static int 2598 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2599 { 2600 struct ath_hal *ah = sc->sc_ah; 2601 struct ieee80211com *ic = &sc->sc_ic; 2602 2603 DPRINTF(("ath_chan_set: %u (%u MHz) -> %u (%u MHz)\n", 2604 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2605 ic->ic_ibss_chan->ic_freq, 2606 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2607 if (chan != ic->ic_ibss_chan) { 2608 HAL_STATUS status; 2609 HAL_CHANNEL hchan; 2610 enum ieee80211_phymode mode; 2611 2612 /* 2613 * To switch channels clear any pending DMA operations; 2614 * wait long enough for the RX fifo to drain, reset the 2615 * hardware at the new frequency, and then re-enable 2616 * the relevant bits of the h/w. 2617 */ 2618 ath_hal_intrset(ah, 0); /* disable interrupts */ 2619 ath_draintxq(sc); /* clear pending tx frames */ 2620 ath_stoprecv(sc); /* turn off frame recv */ 2621 /* 2622 * Convert to a HAL channel description with 2623 * the flags constrained to reflect the current 2624 * operating mode. 2625 */ 2626 hchan.channel = chan->ic_freq; 2627 hchan.channelFlags = ath_chan2flags(ic, chan); 2628 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2629 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2630 "channel %u (%u Mhz)\n", 2631 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2632 return EIO; 2633 } 2634 /* 2635 * Re-enable rx framework. 2636 */ 2637 if (ath_startrecv(sc) != 0) { 2638 if_printf(&ic->ic_if, 2639 "ath_chan_set: unable to restart recv logic\n"); 2640 return EIO; 2641 } 2642 2643 /* 2644 * Update BPF state. 2645 */ 2646 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2647 htole16(chan->ic_freq); 2648 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2649 htole16(chan->ic_flags); 2650 2651 /* 2652 * Change channels and update the h/w rate map 2653 * if we're switching; e.g. 11a to 11b/g. 2654 */ 2655 ic->ic_ibss_chan = chan; 2656 mode = ieee80211_chan2mode(ic, chan); 2657 if (mode != sc->sc_curmode) 2658 ath_setcurmode(sc, mode); 2659 2660 /* 2661 * Re-enable interrupts. 2662 */ 2663 ath_hal_intrset(ah, sc->sc_imask); 2664 } 2665 return 0; 2666 } 2667 2668 static void 2669 ath_next_scan(void *arg) 2670 { 2671 struct ath_softc *sc = arg; 2672 struct ieee80211com *ic = &sc->sc_ic; 2673 struct ifnet *ifp = &ic->ic_if; 2674 int s; 2675 2676 /* don't call ath_start w/o network interrupts blocked */ 2677 s = splnet(); 2678 2679 if (ic->ic_state == IEEE80211_S_SCAN) 2680 ieee80211_next_scan(ifp); 2681 splx(s); 2682 } 2683 2684 /* 2685 * Periodically recalibrate the PHY to account 2686 * for temperature/environment changes. 2687 */ 2688 static void 2689 ath_calibrate(void *arg) 2690 { 2691 struct ath_softc *sc = arg; 2692 struct ath_hal *ah = sc->sc_ah; 2693 struct ieee80211com *ic = &sc->sc_ic; 2694 struct ieee80211_channel *c; 2695 HAL_CHANNEL hchan; 2696 2697 sc->sc_stats.ast_per_cal++; 2698 2699 /* 2700 * Convert to a HAL channel description with the flags 2701 * constrained to reflect the current operating mode. 2702 */ 2703 c = ic->ic_ibss_chan; 2704 hchan.channel = c->ic_freq; 2705 hchan.channelFlags = ath_chan2flags(ic, c); 2706 2707 DPRINTF(("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2708 2709 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2710 /* 2711 * Rfgain is out of bounds, reset the chip 2712 * to load new gain values. 2713 */ 2714 sc->sc_stats.ast_per_rfgain++; 2715 ath_reset(sc); 2716 } 2717 if (!ath_hal_calibrate(ah, &hchan)) { 2718 DPRINTF(("%s: calibration of channel %u failed\n", 2719 __func__, c->ic_freq)); 2720 sc->sc_stats.ast_per_calfail++; 2721 } 2722 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2723 } 2724 2725 static int 2726 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2727 { 2728 struct ifnet *ifp = &ic->ic_if; 2729 struct ath_softc *sc = ifp->if_softc; 2730 struct ath_hal *ah = sc->sc_ah; 2731 struct ieee80211_node *ni; 2732 int i, error; 2733 u_int8_t *bssid; 2734 u_int32_t rfilt; 2735 static const HAL_LED_STATE leds[] = { 2736 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2737 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2738 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2739 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2740 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2741 }; 2742 2743 DPRINTF(("%s: %s -> %s\n", __func__, 2744 ieee80211_state_name[ic->ic_state], 2745 ieee80211_state_name[nstate])); 2746 2747 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2748 2749 if (nstate == IEEE80211_S_INIT) { 2750 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2751 ath_hal_intrset(ah, sc->sc_imask); 2752 callout_stop(&sc->sc_scan_ch); 2753 callout_stop(&sc->sc_cal_ch); 2754 return (*sc->sc_newstate)(ic, nstate, arg); 2755 } 2756 ni = ic->ic_bss; 2757 error = ath_chan_set(sc, ni->ni_chan); 2758 if (error != 0) 2759 goto bad; 2760 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 2761 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2762 if (ic->ic_opmode != IEEE80211_M_STA) 2763 rfilt |= HAL_RX_FILTER_PROBEREQ; 2764 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2765 (ifp->if_flags & IFF_PROMISC)) 2766 rfilt |= HAL_RX_FILTER_PROM; 2767 if (nstate == IEEE80211_S_SCAN) { 2768 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2769 ath_next_scan, sc); 2770 bssid = ifp->if_broadcastaddr; 2771 rfilt |= HAL_RX_FILTER_BEACON; 2772 } else { 2773 callout_stop(&sc->sc_scan_ch); 2774 bssid = ni->ni_bssid; 2775 } 2776 ath_hal_setrxfilter(ah, rfilt); 2777 DPRINTF(("%s: RX filter 0x%x bssid %s\n", 2778 __func__, rfilt, ether_sprintf(bssid))); 2779 2780 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2781 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2782 else 2783 ath_hal_setassocid(ah, bssid, 0); 2784 if (ic->ic_flags & IEEE80211_F_WEPON) { 2785 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2786 if (ath_hal_keyisvalid(ah, i)) 2787 ath_hal_keysetmac(ah, i, bssid); 2788 } 2789 2790 if (nstate == IEEE80211_S_RUN) { 2791 DPRINTF(("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2792 "capinfo=0x%04x chan=%d\n" 2793 , __func__ 2794 , ic->ic_flags 2795 , ni->ni_intval 2796 , ether_sprintf(ni->ni_bssid) 2797 , ni->ni_capinfo 2798 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2799 2800 /* 2801 * Allocate and setup the beacon frame for AP or adhoc mode. 2802 */ 2803 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2804 ic->ic_opmode == IEEE80211_M_IBSS) { 2805 error = ath_beacon_alloc(sc, ni); 2806 if (error != 0) 2807 goto bad; 2808 } 2809 2810 /* 2811 * Configure the beacon and sleep timers. 2812 */ 2813 ath_beacon_config(sc); 2814 2815 /* start periodic recalibration timer */ 2816 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2817 ath_calibrate, sc); 2818 } else { 2819 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2820 ath_hal_intrset(ah, sc->sc_imask); 2821 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2822 } 2823 /* 2824 * Reset the rate control state. 2825 */ 2826 ath_rate_ctl_reset(sc, nstate); 2827 /* 2828 * Invoke the parent method to complete the work. 2829 */ 2830 return (*sc->sc_newstate)(ic, nstate, arg); 2831 bad: 2832 callout_stop(&sc->sc_scan_ch); 2833 callout_stop(&sc->sc_cal_ch); 2834 /* NB: do not invoke the parent */ 2835 return error; 2836 } 2837 2838 /* 2839 * Setup driver-specific state for a newly associated node. 2840 * Note that we're called also on a re-associate, the isnew 2841 * param tells us if this is the first time or not. 2842 */ 2843 static void 2844 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2845 { 2846 if (isnew) { 2847 struct ath_node *an = (struct ath_node *) ni; 2848 2849 an->an_tx_ok = an->an_tx_err = 2850 an->an_tx_retr = an->an_tx_upper = 0; 2851 /* start with highest negotiated rate */ 2852 /* 2853 * XXX should do otherwise but only when 2854 * the rate control algorithm is better. 2855 */ 2856 KASSERT(ni->ni_rates.rs_nrates > 0, 2857 ("new association w/ no rates!")); 2858 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2859 } 2860 } 2861 2862 static int 2863 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2864 { 2865 struct ieee80211com *ic = &sc->sc_ic; 2866 struct ifnet *ifp = &ic->ic_if; 2867 struct ath_hal *ah = sc->sc_ah; 2868 HAL_CHANNEL *chans; 2869 int i, ix, nchan; 2870 2871 sc->sc_have11g = 0; 2872 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2873 M_TEMP, M_NOWAIT); 2874 if (chans == NULL) { 2875 if_printf(ifp, "unable to allocate channel table\n"); 2876 return ENOMEM; 2877 } 2878 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2879 cc, HAL_MODE_ALL, outdoor)) { 2880 if_printf(ifp, "unable to collect channel list from hal\n"); 2881 free(chans, M_TEMP); 2882 return EINVAL; 2883 } 2884 2885 /* 2886 * Convert HAL channels to ieee80211 ones and insert 2887 * them in the table according to their channel number. 2888 */ 2889 for (i = 0; i < nchan; i++) { 2890 HAL_CHANNEL *c = &chans[i]; 2891 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2892 if (ix > IEEE80211_CHAN_MAX) { 2893 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2894 ix, c->channel, c->channelFlags); 2895 continue; 2896 } 2897 /* NB: flags are known to be compatible */ 2898 if (ic->ic_channels[ix].ic_freq == 0) { 2899 ic->ic_channels[ix].ic_freq = c->channel; 2900 ic->ic_channels[ix].ic_flags = c->channelFlags; 2901 } else { 2902 /* channels overlap; e.g. 11g and 11b */ 2903 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2904 } 2905 if ((c->channelFlags & CHANNEL_G) == CHANNEL_G) 2906 sc->sc_have11g = 1; 2907 } 2908 free(chans, M_TEMP); 2909 return 0; 2910 } 2911 2912 static int 2913 ath_rate_setup(struct ath_softc *sc, u_int mode) 2914 { 2915 struct ath_hal *ah = sc->sc_ah; 2916 struct ieee80211com *ic = &sc->sc_ic; 2917 const HAL_RATE_TABLE *rt; 2918 struct ieee80211_rateset *rs; 2919 int i, maxrates; 2920 2921 switch (mode) { 2922 case IEEE80211_MODE_11A: 2923 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2924 break; 2925 case IEEE80211_MODE_11B: 2926 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2927 break; 2928 case IEEE80211_MODE_11G: 2929 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2930 break; 2931 case IEEE80211_MODE_TURBO: 2932 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2933 break; 2934 default: 2935 DPRINTF(("%s: invalid mode %u\n", __func__, mode)); 2936 return 0; 2937 } 2938 rt = sc->sc_rates[mode]; 2939 if (rt == NULL) 2940 return 0; 2941 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2942 DPRINTF(("%s: rate table too small (%u > %u)\n", 2943 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2944 maxrates = IEEE80211_RATE_MAXSIZE; 2945 } else 2946 maxrates = rt->rateCount; 2947 rs = &ic->ic_sup_rates[mode]; 2948 for (i = 0; i < maxrates; i++) 2949 rs->rs_rates[i] = rt->info[i].dot11Rate; 2950 rs->rs_nrates = maxrates; 2951 return 1; 2952 } 2953 2954 static void 2955 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2956 { 2957 const HAL_RATE_TABLE *rt; 2958 int i; 2959 2960 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2961 rt = sc->sc_rates[mode]; 2962 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2963 for (i = 0; i < rt->rateCount; i++) 2964 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2965 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2966 for (i = 0; i < 32; i++) 2967 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2968 sc->sc_currates = rt; 2969 sc->sc_curmode = mode; 2970 } 2971 2972 /* 2973 * Reset the rate control state for each 802.11 state transition. 2974 */ 2975 static void 2976 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2977 { 2978 struct ieee80211com *ic = &sc->sc_ic; 2979 struct ieee80211_node *ni; 2980 struct ath_node *an; 2981 2982 an = (struct ath_node *) ic->ic_bss; 2983 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2984 if (ic->ic_opmode == IEEE80211_M_STA) { 2985 ni = ic->ic_bss; 2986 if (state == IEEE80211_S_RUN) { 2987 /* start with highest negotiated rate */ 2988 KASSERT(ni->ni_rates.rs_nrates > 0, 2989 ("transition to RUN state w/ no rates!")); 2990 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2991 } else { 2992 /* use lowest rate */ 2993 ni->ni_txrate = 0; 2994 } 2995 } else { 2996 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2997 ni->ni_txrate = 0; /* use lowest rate */ 2998 an = (struct ath_node *) ni; 2999 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 3000 an->an_tx_upper = 0; 3001 } 3002 } 3003 } 3004 3005 /* 3006 * Examine and potentially adjust the transmit rate. 3007 */ 3008 static void 3009 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 3010 { 3011 struct ath_softc *sc = arg; 3012 struct ath_node *an = (struct ath_node *) ni; 3013 struct ieee80211_rateset *rs = &ni->ni_rates; 3014 int mod = 0, orate, enough; 3015 3016 /* 3017 * Rate control 3018 * XXX: very primitive version. 3019 */ 3020 sc->sc_stats.ast_rate_calls++; 3021 3022 enough = (an->an_tx_ok + an->an_tx_err >= 10); 3023 3024 /* no packet reached -> down */ 3025 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 3026 mod = -1; 3027 3028 /* all packets needs retry in average -> down */ 3029 if (enough && an->an_tx_ok < an->an_tx_retr) 3030 mod = -1; 3031 3032 /* no error and less than 10% of packets needs retry -> up */ 3033 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 3034 mod = 1; 3035 3036 orate = ni->ni_txrate; 3037 switch (mod) { 3038 case 0: 3039 if (enough && an->an_tx_upper > 0) 3040 an->an_tx_upper--; 3041 break; 3042 case -1: 3043 if (ni->ni_txrate > 0) { 3044 ni->ni_txrate--; 3045 sc->sc_stats.ast_rate_drop++; 3046 } 3047 an->an_tx_upper = 0; 3048 break; 3049 case 1: 3050 if (++an->an_tx_upper < 2) 3051 break; 3052 an->an_tx_upper = 0; 3053 if (ni->ni_txrate + 1 < rs->rs_nrates) { 3054 ni->ni_txrate++; 3055 sc->sc_stats.ast_rate_raise++; 3056 } 3057 break; 3058 } 3059 3060 if (ni->ni_txrate != orate) { 3061 printf("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 3062 __func__, 3063 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 3064 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 3065 an->an_tx_ok, an->an_tx_err, an->an_tx_retr); 3066 } 3067 if (ni->ni_txrate != orate || enough) 3068 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 3069 } 3070 3071 #ifdef AR_DEBUG 3072 #ifdef __FreeBSD__ 3073 static int 3074 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 3075 { 3076 char dmode[64]; 3077 int error; 3078 3079 strncpy(dmode, "", sizeof(dmode) - 1); 3080 dmode[sizeof(dmode) - 1] = '\0'; 3081 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 3082 3083 if (error == 0 && req->newptr != NULL) { 3084 struct ifnet *ifp; 3085 struct ath_softc *sc; 3086 3087 ifp = ifunit("ath0"); /* XXX */ 3088 if (!ifp) 3089 return EINVAL; 3090 sc = ifp->if_softc; 3091 if (strcmp(dmode, "hal") == 0) 3092 ath_hal_dumpstate(sc->sc_ah); 3093 else if (strcmp(dmode, "eeprom") == 0) 3094 ath_hal_dumpeeprom(sc->sc_ah); 3095 else if (strcmp(dmode, "rfgain") == 0) 3096 ath_hal_dumprfgain(sc->sc_ah); 3097 else if (strcmp(dmode, "ani") == 0) 3098 ath_hal_dumpani(sc->sc_ah); 3099 else 3100 return EINVAL; 3101 } 3102 return error; 3103 } 3104 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 3105 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 3106 #endif /* __FreeBSD__ */ 3107 3108 static void 3109 ath_printrxbuf(struct ath_buf *bf, int done) 3110 { 3111 struct ath_desc *ds; 3112 int i; 3113 3114 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 3115 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 3116 i, ds, (struct ath_desc *)bf->bf_daddr + i, 3117 ds->ds_link, ds->ds_data, 3118 ds->ds_ctl0, ds->ds_ctl1, 3119 ds->ds_hw[0], ds->ds_hw[1], 3120 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 3121 } 3122 } 3123 3124 static void 3125 ath_printtxbuf(struct ath_buf *bf, int done) 3126 { 3127 struct ath_desc *ds; 3128 int i; 3129 3130 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 3131 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 3132 i, ds, (struct ath_desc *)bf->bf_daddr + i, 3133 ds->ds_link, ds->ds_data, 3134 ds->ds_ctl0, ds->ds_ctl1, 3135 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 3136 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 3137 } 3138 } 3139 #endif /* AR_DEBUG */ 3140
Indexes created Thu Oct 02 07:10:07 GMT 2025