ath.c revision 1.47
1 /* $NetBSD: ath.c,v 1.47 2005/06/22 06:15:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.76 2005/01/24 20:31:24 sam Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.47 2005/06/22 06:15:51 dyoung Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <machine/bus.h> 74 #include <sys/endian.h> 75 76 #include <machine/bus.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_arp.h> 82 #include <net/if_ether.h> 83 #include <net/if_llc.h> 84 85 #include <net80211/ieee80211_netbsd.h> 86 #include <net80211/ieee80211_var.h> 87 88 #if NBPFILTER > 0 89 #include <net/bpf.h> 90 #endif 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #endif 95 96 #include <dev/ic/ath_netbsd.h> 97 98 #define AR_DEBUG 99 #include <dev/ic/athvar.h> 100 #include <contrib/dev/ic/athhal_desc.h> 101 #include <contrib/dev/ic/athhal_devid.h> /* XXX for softled */ 102 103 /* unaligned little endian access */ 104 #define LE_READ_2(p) \ 105 ((u_int16_t) \ 106 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 107 #define LE_READ_4(p) \ 108 ((u_int32_t) \ 109 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 110 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 111 112 enum { 113 ATH_LED_TX, 114 ATH_LED_RX, 115 ATH_LED_POLL, 116 }; 117 118 static int ath_init(struct ifnet *); 119 static void ath_stop_locked(struct ifnet *, int); 120 static void ath_stop(struct ifnet *, int); 121 static void ath_start(struct ifnet *); 122 static int ath_media_change(struct ifnet *); 123 static void ath_watchdog(struct ifnet *); 124 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 125 static void ath_fatal_proc(void *, int); 126 static void ath_rxorn_proc(void *, int); 127 static void ath_bmiss_proc(void *, int); 128 static void ath_initkeytable(struct ath_softc *); 129 static int ath_key_alloc(struct ieee80211com *, 130 const struct ieee80211_key *); 131 static int ath_key_delete(struct ieee80211com *, 132 const struct ieee80211_key *); 133 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 134 const u_int8_t mac[IEEE80211_ADDR_LEN]); 135 static void ath_key_update_begin(struct ieee80211com *); 136 static void ath_key_update_end(struct ieee80211com *); 137 static void ath_mode_init(struct ath_softc *); 138 static void ath_setslottime(struct ath_softc *); 139 static void ath_updateslot(struct ifnet *); 140 static int ath_beaconq_setup(struct ath_hal *); 141 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 142 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 143 static void ath_beacon_proc(void *, int); 144 static void ath_bstuck_proc(void *, int); 145 static void ath_beacon_free(struct ath_softc *); 146 static void ath_beacon_config(struct ath_softc *); 147 static void ath_descdma_cleanup(struct ath_softc *sc, 148 struct ath_descdma *, ath_bufhead *); 149 static int ath_desc_alloc(struct ath_softc *); 150 static void ath_desc_free(struct ath_softc *); 151 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 152 static void ath_node_free(struct ieee80211_node *); 153 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 154 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 155 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 156 struct ieee80211_node *ni, 157 int subtype, int rssi, u_int32_t rstamp); 158 static void ath_setdefantenna(struct ath_softc *, u_int); 159 static void ath_rx_proc(void *, int); 160 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 161 static int ath_tx_setup(struct ath_softc *, int, int); 162 static int ath_wme_update(struct ieee80211com *); 163 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 164 static void ath_tx_cleanup(struct ath_softc *); 165 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 166 struct ath_buf *, struct mbuf *); 167 static void ath_tx_proc_q0(void *, int); 168 static void ath_tx_proc_q0123(void *, int); 169 static void ath_tx_proc(void *, int); 170 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 171 static void ath_draintxq(struct ath_softc *); 172 static void ath_stoprecv(struct ath_softc *); 173 static int ath_startrecv(struct ath_softc *); 174 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 175 static void ath_next_scan(void *); 176 static void ath_calibrate(void *); 177 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 178 static void ath_newassoc(struct ieee80211com *, 179 struct ieee80211_node *, int); 180 static int ath_getchannels(struct ath_softc *, u_int cc, 181 HAL_BOOL outdoor, HAL_BOOL xchanmode); 182 static void ath_led_event(struct ath_softc *, int); 183 static void ath_update_txpow(struct ath_softc *); 184 185 static int ath_rate_setup(struct ath_softc *, u_int mode); 186 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 187 188 #ifdef __NetBSD__ 189 int ath_enable(struct ath_softc *); 190 void ath_disable(struct ath_softc *); 191 void ath_power(int, void *); 192 #endif 193 194 static void ath_bpfattach(struct ath_softc *); 195 static void ath_announce(struct ath_softc *); 196 197 int ath_dwelltime = 200; /* 5 channels/second */ 198 int ath_calinterval = 30; /* calibrate every 30 secs */ 199 int ath_outdoor = AH_TRUE; /* outdoor operation */ 200 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 201 int ath_countrycode = CTRY_DEFAULT; /* country code */ 202 int ath_regdomain = 0; /* regulatory domain */ 203 int ath_debug = 0; 204 205 #ifdef AR_DEBUG 206 enum { 207 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 208 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 209 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 210 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 211 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 212 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 213 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 214 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 215 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 216 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 217 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 218 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 219 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 220 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 221 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 222 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 223 ATH_DEBUG_NODE = 0x00080000, /* node management */ 224 ATH_DEBUG_LED = 0x00100000, /* led management */ 225 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 226 ATH_DEBUG_ANY = 0xffffffff 227 }; 228 #define IFF_DUMPPKTS(sc, m) \ 229 ((sc->sc_debug & (m)) || \ 230 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 231 #define DPRINTF(sc, m, fmt, ...) do { \ 232 if (sc->sc_debug & (m)) \ 233 printf(fmt, __VA_ARGS__); \ 234 } while (0) 235 #define KEYPRINTF(sc, ix, hk, mac) do { \ 236 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 237 ath_keyprint(__func__, ix, hk, mac); \ 238 } while (0) 239 static void ath_printrxbuf(struct ath_buf *bf, int); 240 static void ath_printtxbuf(struct ath_buf *bf, int); 241 #else 242 #define IFF_DUMPPKTS(sc, m) \ 243 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 244 #define DPRINTF(m, fmt, ...) 245 #define KEYPRINTF(sc, k, ix, mac) 246 #endif 247 248 #ifdef __NetBSD__ 249 int 250 ath_activate(struct device *self, enum devact act) 251 { 252 struct ath_softc *sc = (struct ath_softc *)self; 253 int rv = 0, s; 254 255 s = splnet(); 256 switch (act) { 257 case DVACT_ACTIVATE: 258 rv = EOPNOTSUPP; 259 break; 260 case DVACT_DEACTIVATE: 261 if_deactivate(&sc->sc_if); 262 break; 263 } 264 splx(s); 265 return rv; 266 } 267 268 int 269 ath_enable(struct ath_softc *sc) 270 { 271 if (ATH_IS_ENABLED(sc) == 0) { 272 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 273 printf("%s: device enable failed\n", 274 sc->sc_dev.dv_xname); 275 return (EIO); 276 } 277 sc->sc_flags |= ATH_ENABLED; 278 } 279 return (0); 280 } 281 282 void 283 ath_disable(struct ath_softc *sc) 284 { 285 if (!ATH_IS_ENABLED(sc)) 286 return; 287 if (sc->sc_disable != NULL) 288 (*sc->sc_disable)(sc); 289 sc->sc_flags &= ~ATH_ENABLED; 290 } 291 #endif /* __NetBSD__ */ 292 293 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 294 295 int 296 ath_attach(u_int16_t devid, struct ath_softc *sc) 297 { 298 struct ifnet *ifp = &sc->sc_if; 299 struct ieee80211com *ic = &sc->sc_ic; 300 struct ath_hal *ah; 301 HAL_STATUS status; 302 int error = 0, i; 303 304 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 305 306 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 307 308 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 309 if (ah == NULL) { 310 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 311 status); 312 error = ENXIO; 313 goto bad; 314 } 315 if (ah->ah_abi != HAL_ABI_VERSION) { 316 if_printf(ifp, "HAL ABI mismatch detected " 317 "(HAL:0x%x != driver:0x%x)\n", 318 ah->ah_abi, HAL_ABI_VERSION); 319 error = ENXIO; 320 goto bad; 321 } 322 sc->sc_ah = ah; 323 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 324 325 /* 326 * Check if the MAC has multi-rate retry support. 327 * We do this by trying to setup a fake extended 328 * descriptor. MAC's that don't have support will 329 * return false w/o doing anything. MAC's that do 330 * support it will return true w/o doing anything. 331 */ 332 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 333 334 /* 335 * Check if the device has hardware counters for PHY 336 * errors. If so we need to enable the MIB interrupt 337 * so we can act on stat triggers. 338 */ 339 if (ath_hal_hwphycounters(ah)) 340 sc->sc_needmib = 1; 341 342 /* 343 * Get the hardware key cache size. 344 */ 345 sc->sc_keymax = ath_hal_keycachesize(ah); 346 if (sc->sc_keymax > sizeof(sc->sc_keymap) * NBBY) { 347 if_printf(ifp, 348 "Warning, using only %zu of %u key cache slots\n", 349 sizeof(sc->sc_keymap) * NBBY, sc->sc_keymax); 350 sc->sc_keymax = sizeof(sc->sc_keymap) * NBBY; 351 } 352 /* 353 * Reset the key cache since some parts do not 354 * reset the contents on initial power up. 355 */ 356 for (i = 0; i < sc->sc_keymax; i++) 357 ath_hal_keyreset(ah, i); 358 /* 359 * Mark key cache slots associated with global keys 360 * as in use. If we knew TKIP was not to be used we 361 * could leave the +32, +64, and +32+64 slots free. 362 * XXX only for splitmic. 363 */ 364 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 365 setbit(sc->sc_keymap, i); 366 setbit(sc->sc_keymap, i+32); 367 setbit(sc->sc_keymap, i+64); 368 setbit(sc->sc_keymap, i+32+64); 369 } 370 371 /* 372 * Collect the channel list using the default country 373 * code and including outdoor channels. The 802.11 layer 374 * is resposible for filtering this list based on settings 375 * like the phy mode. 376 */ 377 error = ath_getchannels(sc, ath_countrycode, 378 ath_outdoor, ath_xchanmode); 379 if (error != 0) 380 goto bad; 381 /* 382 * Setup dynamic sysctl's now that country code and 383 * regdomain are available from the hal. 384 */ 385 ath_sysctlattach(sc); 386 387 /* 388 * Setup rate tables for all potential media types. 389 */ 390 ath_rate_setup(sc, IEEE80211_MODE_11A); 391 ath_rate_setup(sc, IEEE80211_MODE_11B); 392 ath_rate_setup(sc, IEEE80211_MODE_11G); 393 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 394 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 395 /* NB: setup here so ath_rate_update is happy */ 396 ath_setcurmode(sc, IEEE80211_MODE_11A); 397 398 /* 399 * Allocate tx+rx descriptors and populate the lists. 400 */ 401 error = ath_desc_alloc(sc); 402 if (error != 0) { 403 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 404 goto bad; 405 } 406 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 407 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 408 409 ATH_TXBUF_LOCK_INIT(sc); 410 411 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 412 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 413 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 414 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 415 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 416 417 /* 418 * Allocate hardware transmit queues: one queue for 419 * beacon frames and one data queue for each QoS 420 * priority. Note that the hal handles reseting 421 * these queues at the needed time. 422 * 423 * XXX PS-Poll 424 */ 425 sc->sc_bhalq = ath_beaconq_setup(ah); 426 if (sc->sc_bhalq == (u_int) -1) { 427 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 428 error = EIO; 429 goto bad2; 430 } 431 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 432 if (sc->sc_cabq == NULL) { 433 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 434 error = EIO; 435 goto bad2; 436 } 437 /* NB: insure BK queue is the lowest priority h/w queue */ 438 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 439 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 440 ieee80211_wme_acnames[WME_AC_BK]); 441 error = EIO; 442 goto bad2; 443 } 444 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 445 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 446 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 447 /* 448 * Not enough hardware tx queues to properly do WME; 449 * just punt and assign them all to the same h/w queue. 450 * We could do a better job of this if, for example, 451 * we allocate queues when we switch from station to 452 * AP mode. 453 */ 454 if (sc->sc_ac2q[WME_AC_VI] != NULL) 455 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 456 if (sc->sc_ac2q[WME_AC_BE] != NULL) 457 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 458 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 459 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 460 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 461 } 462 463 /* 464 * Special case certain configurations. Note the 465 * CAB queue is handled by these specially so don't 466 * include them when checking the txq setup mask. 467 */ 468 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 469 case 0x01: 470 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 471 break; 472 case 0x0f: 473 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 474 break; 475 default: 476 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 477 break; 478 } 479 480 /* 481 * Setup rate control. Some rate control modules 482 * call back to change the anntena state so expose 483 * the necessary entry points. 484 * XXX maybe belongs in struct ath_ratectrl? 485 */ 486 sc->sc_setdefantenna = ath_setdefantenna; 487 sc->sc_rc = ath_rate_attach(sc); 488 if (sc->sc_rc == NULL) { 489 error = EIO; 490 goto bad2; 491 } 492 493 sc->sc_blinking = 0; 494 sc->sc_ledstate = 1; 495 sc->sc_ledon = 0; /* low true */ 496 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 497 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 498 /* 499 * Auto-enable soft led processing for IBM cards and for 500 * 5211 minipci cards. Users can also manually enable/disable 501 * support with a sysctl. 502 */ 503 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 504 if (sc->sc_softled) { 505 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 506 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 507 } 508 509 ifp->if_softc = sc; 510 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 511 ifp->if_start = ath_start; 512 ifp->if_watchdog = ath_watchdog; 513 ifp->if_ioctl = ath_ioctl; 514 ifp->if_init = ath_init; 515 IFQ_SET_READY(&ifp->if_snd); 516 517 ic->ic_ifp = ifp; 518 ic->ic_reset = ath_reset; 519 ic->ic_newassoc = ath_newassoc; 520 ic->ic_updateslot = ath_updateslot; 521 ic->ic_wme.wme_update = ath_wme_update; 522 /* XXX not right but it's not used anywhere important */ 523 ic->ic_phytype = IEEE80211_T_OFDM; 524 ic->ic_opmode = IEEE80211_M_STA; 525 ic->ic_caps = 526 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 527 | IEEE80211_C_HOSTAP /* hostap mode */ 528 | IEEE80211_C_MONITOR /* monitor mode */ 529 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 530 | IEEE80211_C_SHSLOT /* short slot time supported */ 531 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 532 ; 533 /* 534 * Query the hal to figure out h/w crypto support. 535 */ 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 537 ic->ic_caps |= IEEE80211_C_WEP; 538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 539 ic->ic_caps |= IEEE80211_C_AES; 540 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 541 ic->ic_caps |= IEEE80211_C_AES_CCM; 542 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 543 ic->ic_caps |= IEEE80211_C_CKIP; 544 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 545 ic->ic_caps |= IEEE80211_C_TKIP; 546 /* 547 * Check if h/w does the MIC and/or whether the 548 * separate key cache entries are required to 549 * handle both tx+rx MIC keys. 550 */ 551 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 552 ic->ic_caps |= IEEE80211_C_TKIPMIC; 553 if (ath_hal_tkipsplit(ah)) 554 sc->sc_splitmic = 1; 555 } 556 /* 557 * TPC support can be done either with a global cap or 558 * per-packet support. The latter is not available on 559 * all parts. We're a bit pedantic here as all parts 560 * support a global cap. 561 */ 562 sc->sc_hastpc = ath_hal_hastpc(ah); 563 if (sc->sc_hastpc || ath_hal_hastxpowlimit(ah)) 564 ic->ic_caps |= IEEE80211_C_TXPMGT; 565 566 /* 567 * Mark WME capability only if we have sufficient 568 * hardware queues to do proper priority scheduling. 569 */ 570 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 571 ic->ic_caps |= IEEE80211_C_WME; 572 /* 573 * Check for frame bursting capability. 574 */ 575 if (ath_hal_hasbursting(ah)) 576 ic->ic_caps |= IEEE80211_C_BURST; 577 578 /* 579 * Indicate we need the 802.11 header padded to a 580 * 32-bit boundary for 4-address and QoS frames. 581 */ 582 ic->ic_flags |= IEEE80211_F_DATAPAD; 583 584 /* 585 * Query the hal about antenna support. 586 */ 587 if (ath_hal_hasdiversity(ah)) { 588 sc->sc_hasdiversity = 1; 589 sc->sc_diversity = ath_hal_getdiversity(ah); 590 } 591 sc->sc_defant = ath_hal_getdefantenna(ah); 592 593 /* 594 * Not all chips have the VEOL support we want to 595 * use with IBSS beacons; check here for it. 596 */ 597 sc->sc_hasveol = ath_hal_hasveol(ah); 598 599 /* get mac address from hardware */ 600 ath_hal_getmac(ah, ic->ic_myaddr); 601 602 if_attach(ifp); 603 /* call MI attach routine. */ 604 ieee80211_ifattach(ic); 605 /* override default methods */ 606 ic->ic_node_alloc = ath_node_alloc; 607 sc->sc_node_free = ic->ic_node_free; 608 ic->ic_node_free = ath_node_free; 609 ic->ic_node_getrssi = ath_node_getrssi; 610 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 611 ic->ic_recv_mgmt = ath_recv_mgmt; 612 sc->sc_newstate = ic->ic_newstate; 613 ic->ic_newstate = ath_newstate; 614 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 615 ic->ic_crypto.cs_key_delete = ath_key_delete; 616 ic->ic_crypto.cs_key_set = ath_key_set; 617 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 618 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 619 /* complete initialization */ 620 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 621 622 ath_bpfattach(sc); 623 624 #ifdef __NetBSD__ 625 sc->sc_flags |= ATH_ATTACHED; 626 /* 627 * Make sure the interface is shutdown during reboot. 628 */ 629 sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 630 if (sc->sc_sdhook == NULL) 631 printf("%s: WARNING: unable to establish shutdown hook\n", 632 sc->sc_dev.dv_xname); 633 sc->sc_powerhook = powerhook_establish(ath_power, sc); 634 if (sc->sc_powerhook == NULL) 635 printf("%s: WARNING: unable to establish power hook\n", 636 sc->sc_dev.dv_xname); 637 #endif 638 if (boothowto & AB_VERBOSE) 639 ieee80211_announce(ic); 640 ath_announce(sc); 641 return 0; 642 bad2: 643 ath_tx_cleanup(sc); 644 ath_desc_free(sc); 645 bad: 646 if (ah) 647 ath_hal_detach(ah); 648 sc->sc_invalid = 1; 649 return error; 650 } 651 652 int 653 ath_detach(struct ath_softc *sc) 654 { 655 struct ifnet *ifp = &sc->sc_if; 656 int s; 657 658 if ((sc->sc_flags & ATH_ATTACHED) == 0) 659 return (0); 660 661 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 662 __func__, ifp->if_flags); 663 664 s = splnet(); 665 ath_stop(ifp, 1); 666 #if NBPFILTER > 0 667 bpfdetach(ifp); 668 #endif 669 /* 670 * NB: the order of these is important: 671 * o call the 802.11 layer before detaching the hal to 672 * insure callbacks into the driver to delete global 673 * key cache entries can be handled 674 * o reclaim the tx queue data structures after calling 675 * the 802.11 layer as we'll get called back to reclaim 676 * node state and potentially want to use them 677 * o to cleanup the tx queues the hal is called, so detach 678 * it last 679 * Other than that, it's straightforward... 680 */ 681 ieee80211_ifdetach(&sc->sc_ic); 682 ath_rate_detach(sc->sc_rc); 683 ath_desc_free(sc); 684 ath_tx_cleanup(sc); 685 ath_hal_detach(sc->sc_ah); 686 if_detach(ifp); 687 splx(s); 688 powerhook_disestablish(sc->sc_powerhook); 689 shutdownhook_disestablish(sc->sc_sdhook); 690 691 return 0; 692 } 693 694 #ifdef __NetBSD__ 695 void 696 ath_power(int why, void *arg) 697 { 698 struct ath_softc *sc = arg; 699 int s; 700 701 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 702 703 s = splnet(); 704 switch (why) { 705 case PWR_SUSPEND: 706 case PWR_STANDBY: 707 ath_suspend(sc, why); 708 break; 709 case PWR_RESUME: 710 ath_resume(sc, why); 711 break; 712 case PWR_SOFTSUSPEND: 713 case PWR_SOFTSTANDBY: 714 case PWR_SOFTRESUME: 715 break; 716 } 717 splx(s); 718 } 719 #endif 720 721 void 722 ath_suspend(struct ath_softc *sc, int why) 723 { 724 struct ifnet *ifp = &sc->sc_if; 725 726 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 727 __func__, ifp->if_flags); 728 729 ath_stop(ifp, 1); 730 if (sc->sc_power != NULL) 731 (*sc->sc_power)(sc, why); 732 } 733 734 void 735 ath_resume(struct ath_softc *sc, int why) 736 { 737 struct ifnet *ifp = &sc->sc_if; 738 739 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 740 __func__, ifp->if_flags); 741 742 if (ifp->if_flags & IFF_UP) { 743 ath_init(ifp); 744 #if 0 745 (void)ath_intr(sc); 746 #endif 747 if (sc->sc_power != NULL) 748 (*sc->sc_power)(sc, why); 749 if (ifp->if_flags & IFF_RUNNING) 750 ath_start(ifp); 751 } 752 } 753 754 void 755 ath_shutdown(void *arg) 756 { 757 struct ath_softc *sc = arg; 758 759 ath_stop(&sc->sc_if, 1); 760 } 761 762 /* 763 * Interrupt handler. Most of the actual processing is deferred. 764 */ 765 int 766 ath_intr(void *arg) 767 { 768 struct ath_softc *sc = arg; 769 struct ifnet *ifp = &sc->sc_if; 770 struct ath_hal *ah = sc->sc_ah; 771 HAL_INT status; 772 773 if (sc->sc_invalid) { 774 /* 775 * The hardware is not ready/present, don't touch anything. 776 * Note this can happen early on if the IRQ is shared. 777 */ 778 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 779 return 0; 780 } 781 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 782 return 0; 783 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 784 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 785 __func__, ifp->if_flags); 786 ath_hal_getisr(ah, &status); /* clear ISR */ 787 ath_hal_intrset(ah, 0); /* disable further intr's */ 788 return 1; /* XXX */ 789 } 790 /* 791 * Figure out the reason(s) for the interrupt. Note 792 * that the hal returns a pseudo-ISR that may include 793 * bits we haven't explicitly enabled so we mask the 794 * value to insure we only process bits we requested. 795 */ 796 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 797 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 798 status &= sc->sc_imask; /* discard unasked for bits */ 799 if (status & HAL_INT_FATAL) { 800 /* 801 * Fatal errors are unrecoverable. Typically 802 * these are caused by DMA errors. Unfortunately 803 * the exact reason is not (presently) returned 804 * by the hal. 805 */ 806 sc->sc_stats.ast_hardware++; 807 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 808 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 809 } else if (status & HAL_INT_RXORN) { 810 sc->sc_stats.ast_rxorn++; 811 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 812 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 813 } else { 814 if (status & HAL_INT_SWBA) { 815 /* 816 * Software beacon alert--time to send a beacon. 817 * Handle beacon transmission directly; deferring 818 * this is too slow to meet timing constraints 819 * under load. 820 */ 821 ath_beacon_proc(sc, 0); 822 } 823 if (status & HAL_INT_RXEOL) { 824 /* 825 * NB: the hardware should re-read the link when 826 * RXE bit is written, but it doesn't work at 827 * least on older hardware revs. 828 */ 829 sc->sc_stats.ast_rxeol++; 830 sc->sc_rxlink = NULL; 831 } 832 if (status & HAL_INT_TXURN) { 833 sc->sc_stats.ast_txurn++; 834 /* bump tx trigger level */ 835 ath_hal_updatetxtriglevel(ah, AH_TRUE); 836 } 837 if (status & HAL_INT_RX) 838 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 839 if (status & HAL_INT_TX) 840 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 841 if (status & HAL_INT_BMISS) { 842 sc->sc_stats.ast_bmiss++; 843 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 844 } 845 if (status & HAL_INT_MIB) { 846 sc->sc_stats.ast_mib++; 847 /* 848 * Disable interrupts until we service the MIB 849 * interrupt; otherwise it will continue to fire. 850 */ 851 ath_hal_intrset(ah, 0); 852 /* 853 * Let the hal handle the event. We assume it will 854 * clear whatever condition caused the interrupt. 855 */ 856 ath_hal_mibevent(ah, 857 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 858 ath_hal_intrset(ah, sc->sc_imask); 859 } 860 } 861 return 1; 862 } 863 864 static void 865 ath_fatal_proc(void *arg, int pending) 866 { 867 struct ath_softc *sc = arg; 868 struct ifnet *ifp = &sc->sc_if; 869 870 if_printf(ifp, "hardware error; resetting\n"); 871 ath_reset(ifp); 872 } 873 874 static void 875 ath_rxorn_proc(void *arg, int pending) 876 { 877 struct ath_softc *sc = arg; 878 struct ifnet *ifp = &sc->sc_if; 879 880 if_printf(ifp, "rx FIFO overrun; resetting\n"); 881 ath_reset(ifp); 882 } 883 884 static void 885 ath_bmiss_proc(void *arg, int pending) 886 { 887 struct ath_softc *sc = arg; 888 struct ieee80211com *ic = &sc->sc_ic; 889 890 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 891 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 892 ("unexpect operating mode %u", ic->ic_opmode)); 893 if (ic->ic_state == IEEE80211_S_RUN) { 894 /* 895 * Rather than go directly to scan state, try to 896 * reassociate first. If that fails then the state 897 * machine will drop us into scanning after timing 898 * out waiting for a probe response. 899 */ 900 NET_LOCK_GIANT(); 901 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 902 NET_UNLOCK_GIANT(); 903 } 904 } 905 906 static u_int 907 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 908 { 909 #define N(a) (sizeof(a) / sizeof(a[0])) 910 static const u_int modeflags[] = { 911 0, /* IEEE80211_MODE_AUTO */ 912 CHANNEL_A, /* IEEE80211_MODE_11A */ 913 CHANNEL_B, /* IEEE80211_MODE_11B */ 914 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 915 0, /* IEEE80211_MODE_FH */ 916 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 917 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 918 }; 919 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 920 921 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 922 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 923 return modeflags[mode]; 924 #undef N 925 } 926 927 static int 928 ath_init(struct ifnet *ifp) 929 { 930 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 931 struct ieee80211com *ic = &sc->sc_ic; 932 struct ieee80211_node *ni; 933 struct ath_hal *ah = sc->sc_ah; 934 HAL_STATUS status; 935 int error = 0; 936 937 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 938 __func__, ifp->if_flags); 939 940 ATH_LOCK(sc); 941 942 if ((error = ath_enable(sc)) != 0) 943 return error; 944 945 /* 946 * Stop anything previously setup. This is safe 947 * whether this is the first time through or not. 948 */ 949 ath_stop_locked(ifp, 0); 950 951 /* 952 * The basic interface to setting the hardware in a good 953 * state is ``reset''. On return the hardware is known to 954 * be powered up and with interrupts disabled. This must 955 * be followed by initialization of the appropriate bits 956 * and then setup of the interrupt mask. 957 */ 958 sc->sc_curchan.channel = ic->ic_ibss_chan->ic_freq; 959 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 960 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 961 if_printf(ifp, "unable to reset hardware; hal status %u\n", 962 status); 963 error = EIO; 964 goto done; 965 } 966 967 /* 968 * This is needed only to setup initial state 969 * but it's best done after a reset. 970 */ 971 ath_update_txpow(sc); 972 973 /* 974 * Setup the hardware after reset: the key cache 975 * is filled as needed and the receive engine is 976 * set going. Frame transmit is handled entirely 977 * in the frame output path; there's nothing to do 978 * here except setup the interrupt mask. 979 */ 980 ath_initkeytable(sc); /* XXX still needed? */ 981 if ((error = ath_startrecv(sc)) != 0) { 982 if_printf(ifp, "unable to start recv logic\n"); 983 goto done; 984 } 985 986 /* 987 * Enable interrupts. 988 */ 989 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 990 | HAL_INT_RXEOL | HAL_INT_RXORN 991 | HAL_INT_FATAL | HAL_INT_GLOBAL; 992 /* 993 * Enable MIB interrupts when there are hardware phy counters. 994 * Note we only do this (at the moment) for station mode. 995 */ 996 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 997 sc->sc_imask |= HAL_INT_MIB; 998 ath_hal_intrset(ah, sc->sc_imask); 999 1000 ifp->if_flags |= IFF_RUNNING; 1001 ic->ic_state = IEEE80211_S_INIT; 1002 1003 /* 1004 * The hardware should be ready to go now so it's safe 1005 * to kick the 802.11 state machine as it's likely to 1006 * immediately call back to us to send mgmt frames. 1007 */ 1008 ni = ic->ic_bss; 1009 ni->ni_chan = ic->ic_ibss_chan; 1010 ath_chan_change(sc, ni->ni_chan); 1011 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1012 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1013 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1014 } else 1015 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1016 done: 1017 ATH_UNLOCK(sc); 1018 return error; 1019 } 1020 1021 static void 1022 ath_stop_locked(struct ifnet *ifp, int disable) 1023 { 1024 struct ath_softc *sc = ifp->if_softc; 1025 struct ieee80211com *ic = &sc->sc_ic; 1026 struct ath_hal *ah = sc->sc_ah; 1027 1028 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1029 __func__, sc->sc_invalid, ifp->if_flags); 1030 1031 ATH_LOCK_ASSERT(sc); 1032 if (ifp->if_flags & IFF_RUNNING) { 1033 /* 1034 * Shutdown the hardware and driver: 1035 * reset 802.11 state machine 1036 * turn off timers 1037 * disable interrupts 1038 * turn off the radio 1039 * clear transmit machinery 1040 * clear receive machinery 1041 * drain and release tx queues 1042 * reclaim beacon resources 1043 * power down hardware 1044 * 1045 * Note that some of this work is not possible if the 1046 * hardware is gone (invalid). 1047 */ 1048 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1049 ifp->if_flags &= ~IFF_RUNNING; 1050 ifp->if_timer = 0; 1051 if (!sc->sc_invalid) { 1052 if (sc->sc_softled) { 1053 callout_stop(&sc->sc_ledtimer); 1054 ath_hal_gpioset(ah, sc->sc_ledpin, 1055 !sc->sc_ledon); 1056 sc->sc_blinking = 0; 1057 } 1058 ath_hal_intrset(ah, 0); 1059 } 1060 ath_draintxq(sc); 1061 if (!sc->sc_invalid) { 1062 ath_stoprecv(sc); 1063 ath_hal_phydisable(ah); 1064 } else 1065 sc->sc_rxlink = NULL; 1066 IF_PURGE(&ifp->if_snd); 1067 ath_beacon_free(sc); 1068 if (disable) 1069 ath_disable(sc); 1070 } 1071 } 1072 1073 static void 1074 ath_stop(struct ifnet *ifp, int disable) 1075 { 1076 struct ath_softc *sc = ifp->if_softc; 1077 1078 ATH_LOCK(sc); 1079 ath_stop_locked(ifp, disable); 1080 if (!sc->sc_invalid) { 1081 /* 1082 * Set the chip in full sleep mode. Note that we are 1083 * careful to do this only when bringing the interface 1084 * completely to a stop. When the chip is in this state 1085 * it must be carefully woken up or references to 1086 * registers in the PCI clock domain may freeze the bus 1087 * (and system). This varies by chip and is mostly an 1088 * issue with newer parts that go to sleep more quickly. 1089 */ 1090 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 1091 } 1092 ATH_UNLOCK(sc); 1093 } 1094 1095 /* 1096 * Reset the hardware w/o losing operational state. This is 1097 * basically a more efficient way of doing ath_stop, ath_init, 1098 * followed by state transitions to the current 802.11 1099 * operational state. Used to recover from various errors and 1100 * to reset or reload hardware state. 1101 */ 1102 int 1103 ath_reset(struct ifnet *ifp) 1104 { 1105 struct ath_softc *sc = ifp->if_softc; 1106 struct ieee80211com *ic = &sc->sc_ic; 1107 struct ath_hal *ah = sc->sc_ah; 1108 struct ieee80211_channel *c; 1109 HAL_STATUS status; 1110 1111 /* 1112 * Convert to a HAL channel description with the flags 1113 * constrained to reflect the current operating mode. 1114 */ 1115 c = ic->ic_ibss_chan; 1116 sc->sc_curchan.channel = c->ic_freq; 1117 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1118 1119 ath_hal_intrset(ah, 0); /* disable interrupts */ 1120 ath_draintxq(sc); /* stop xmit side */ 1121 ath_stoprecv(sc); /* stop recv side */ 1122 /* NB: indicate channel change so we do a full reset */ 1123 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1124 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1125 __func__, status); 1126 ath_update_txpow(sc); /* update tx power state */ 1127 if (ath_startrecv(sc) != 0) /* restart recv */ 1128 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1129 /* 1130 * We may be doing a reset in response to an ioctl 1131 * that changes the channel so update any state that 1132 * might change as a result. 1133 */ 1134 ath_chan_change(sc, c); 1135 if (ic->ic_state == IEEE80211_S_RUN) 1136 ath_beacon_config(sc); /* restart beacons */ 1137 ath_hal_intrset(ah, sc->sc_imask); 1138 1139 ath_start(ifp); /* restart xmit */ 1140 return 0; 1141 } 1142 1143 static void 1144 ath_start(struct ifnet *ifp) 1145 { 1146 struct ath_softc *sc = ifp->if_softc; 1147 struct ath_hal *ah = sc->sc_ah; 1148 struct ieee80211com *ic = &sc->sc_ic; 1149 struct ieee80211_node *ni; 1150 struct ath_buf *bf; 1151 struct mbuf *m; 1152 struct ieee80211_frame *wh; 1153 struct ether_header *eh; 1154 1155 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1156 return; 1157 for (;;) { 1158 /* 1159 * Grab a TX buffer and associated resources. 1160 */ 1161 ATH_TXBUF_LOCK(sc); 1162 bf = STAILQ_FIRST(&sc->sc_txbuf); 1163 if (bf != NULL) 1164 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1165 ATH_TXBUF_UNLOCK(sc); 1166 if (bf == NULL) { 1167 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1168 __func__); 1169 sc->sc_stats.ast_tx_qstop++; 1170 ifp->if_flags |= IFF_OACTIVE; 1171 break; 1172 } 1173 /* 1174 * Poll the management queue for frames; they 1175 * have priority over normal data frames. 1176 */ 1177 IF_DEQUEUE(&ic->ic_mgtq, m); 1178 if (m == NULL) { 1179 /* 1180 * No data frames go out unless we're associated. 1181 */ 1182 if (ic->ic_state != IEEE80211_S_RUN) { 1183 DPRINTF(sc, ATH_DEBUG_ANY, 1184 "%s: ignore data packet, state %u\n", 1185 __func__, ic->ic_state); 1186 sc->sc_stats.ast_tx_discard++; 1187 ATH_TXBUF_LOCK(sc); 1188 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1189 ATH_TXBUF_UNLOCK(sc); 1190 break; 1191 } 1192 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1193 if (m == NULL) { 1194 ATH_TXBUF_LOCK(sc); 1195 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1196 ATH_TXBUF_UNLOCK(sc); 1197 break; 1198 } 1199 /* 1200 * Find the node for the destination so we can do 1201 * things like power save and fast frames aggregation. 1202 */ 1203 if (m->m_len < sizeof(struct ether_header) && 1204 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1205 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1206 ni = NULL; 1207 goto bad; 1208 } 1209 eh = mtod(m, struct ether_header *); 1210 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1211 if (ni == NULL) { 1212 /* NB: ieee80211_find_txnode does stat+msg */ 1213 m_freem(m); 1214 goto bad; 1215 } 1216 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1217 (m->m_flags & M_PWR_SAV) == 0) { 1218 /* 1219 * Station in power save mode; pass the frame 1220 * to the 802.11 layer and continue. We'll get 1221 * the frame back when the time is right. 1222 */ 1223 ieee80211_pwrsave(ic, ni, m); 1224 goto reclaim; 1225 } 1226 /* calculate priority so we can find the tx queue */ 1227 if (ieee80211_classify(ic, m, ni)) { 1228 DPRINTF(sc, ATH_DEBUG_XMIT, 1229 "%s: discard, classification failure\n", 1230 __func__); 1231 m_freem(m); 1232 goto bad; 1233 } 1234 ifp->if_opackets++; 1235 1236 #if NBPFILTER > 0 1237 if (ifp->if_bpf) 1238 bpf_mtap(ifp->if_bpf, m); 1239 #endif 1240 /* 1241 * Encapsulate the packet in prep for transmission. 1242 */ 1243 m = ieee80211_encap(ic, m, ni); 1244 if (m == NULL) { 1245 DPRINTF(sc, ATH_DEBUG_ANY, 1246 "%s: encapsulation failure\n", 1247 __func__); 1248 sc->sc_stats.ast_tx_encap++; 1249 goto bad; 1250 } 1251 } else { 1252 /* 1253 * Hack! The referenced node pointer is in the 1254 * rcvif field of the packet header. This is 1255 * placed there by ieee80211_mgmt_output because 1256 * we need to hold the reference with the frame 1257 * and there's no other way (other than packet 1258 * tags which we consider too expensive to use) 1259 * to pass it along. 1260 */ 1261 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1262 m->m_pkthdr.rcvif = NULL; 1263 1264 wh = mtod(m, struct ieee80211_frame *); 1265 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1266 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1267 /* fill time stamp */ 1268 u_int64_t tsf; 1269 u_int32_t *tstamp; 1270 1271 tsf = ath_hal_gettsf64(ah); 1272 /* XXX: adjust 100us delay to xmit */ 1273 tsf += 100; 1274 tstamp = (u_int32_t *)&wh[1]; 1275 tstamp[0] = htole32(tsf & 0xffffffff); 1276 tstamp[1] = htole32(tsf >> 32); 1277 } 1278 sc->sc_stats.ast_tx_mgmt++; 1279 } 1280 1281 if (ath_tx_start(sc, ni, bf, m)) { 1282 bad: 1283 ifp->if_oerrors++; 1284 reclaim: 1285 ATH_TXBUF_LOCK(sc); 1286 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1287 ATH_TXBUF_UNLOCK(sc); 1288 if (ni != NULL) 1289 ieee80211_free_node(ni); 1290 continue; 1291 } 1292 1293 sc->sc_tx_timer = 5; 1294 ifp->if_timer = 1; 1295 } 1296 } 1297 1298 static int 1299 ath_media_change(struct ifnet *ifp) 1300 { 1301 #define IS_UP(ifp) \ 1302 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 1303 int error; 1304 1305 error = ieee80211_media_change(ifp); 1306 if (error == ENETRESET) { 1307 if (IS_UP(ifp)) 1308 ath_init(ifp); /* XXX lose error */ 1309 error = 0; 1310 } 1311 return error; 1312 #undef IS_UP 1313 } 1314 1315 #ifdef AR_DEBUG 1316 static void 1317 ath_keyprint(const char *tag, u_int ix, 1318 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1319 { 1320 static const char *ciphers[] = { 1321 "WEP", 1322 "AES-OCB", 1323 "AES-CCM", 1324 "CKIP", 1325 "TKIP", 1326 "CLR", 1327 }; 1328 int i, n; 1329 1330 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1331 for (i = 0, n = hk->kv_len; i < n; i++) 1332 printf("%02x", hk->kv_val[i]); 1333 printf(" mac %s", ether_sprintf(mac)); 1334 if (hk->kv_type == HAL_CIPHER_TKIP) { 1335 printf(" mic "); 1336 for (i = 0; i < sizeof(hk->kv_mic); i++) 1337 printf("%02x", hk->kv_mic[i]); 1338 } 1339 printf("\n"); 1340 } 1341 #endif 1342 1343 /* 1344 * Set a TKIP key into the hardware. This handles the 1345 * potential distribution of key state to multiple key 1346 * cache slots for TKIP. 1347 */ 1348 static int 1349 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1350 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1351 { 1352 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1353 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1354 struct ath_hal *ah = sc->sc_ah; 1355 1356 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1357 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1358 KASSERT(sc->sc_splitmic, ("key cache !split")); 1359 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1360 /* 1361 * TX key goes at first index, RX key at +32. 1362 * The hal handles the MIC keys at index+64. 1363 */ 1364 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1365 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1366 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1367 return 0; 1368 1369 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1370 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1371 /* XXX delete tx key on failure? */ 1372 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1373 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1374 /* 1375 * TX/RX key goes at first index. 1376 * The hal handles the MIC keys are index+64. 1377 */ 1378 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID, 1379 ("group key at index %u", k->wk_keyix)); 1380 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1381 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1382 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1383 return ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid); 1384 } 1385 /* XXX key w/o xmit/recv; need this for compression? */ 1386 return 0; 1387 #undef IEEE80211_KEY_XR 1388 } 1389 1390 /* 1391 * Set a net80211 key into the hardware. This handles the 1392 * potential distribution of key state to multiple key 1393 * cache slots for TKIP with hardware MIC support. 1394 */ 1395 static int 1396 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1397 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1398 { 1399 #define N(a) (sizeof(a)/sizeof(a[0])) 1400 static const u_int8_t ciphermap[] = { 1401 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1402 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1403 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1404 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1405 (u_int8_t) -1, /* 4 is not allocated */ 1406 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1407 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1408 }; 1409 struct ath_hal *ah = sc->sc_ah; 1410 const struct ieee80211_cipher *cip = k->wk_cipher; 1411 HAL_KEYVAL hk; 1412 1413 memset(&hk, 0, sizeof(hk)); 1414 /* 1415 * Software crypto uses a "clear key" so non-crypto 1416 * state kept in the key cache are maintained and 1417 * so that rx frames have an entry to match. 1418 */ 1419 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1420 KASSERT(cip->ic_cipher < N(ciphermap), 1421 ("invalid cipher type %u", cip->ic_cipher)); 1422 hk.kv_type = ciphermap[cip->ic_cipher]; 1423 hk.kv_len = k->wk_keylen; 1424 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1425 } else 1426 hk.kv_type = HAL_CIPHER_CLR; 1427 1428 if (hk.kv_type == HAL_CIPHER_TKIP && 1429 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1430 sc->sc_splitmic) { 1431 return ath_keyset_tkip(sc, k, &hk, mac); 1432 } else { 1433 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1434 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1435 } 1436 #undef N 1437 } 1438 1439 /* 1440 * Fill the hardware key cache with key entries. 1441 */ 1442 static void 1443 ath_initkeytable(struct ath_softc *sc) 1444 { 1445 struct ieee80211com *ic = &sc->sc_ic; 1446 struct ifnet *ifp = &sc->sc_if; 1447 struct ath_hal *ah = sc->sc_ah; 1448 const u_int8_t *bssid; 1449 int i; 1450 1451 /* XXX maybe should reset all keys when !PRIVACY */ 1452 if (ic->ic_state == IEEE80211_S_SCAN) 1453 bssid = ifp->if_broadcastaddr; 1454 else 1455 bssid = ic->ic_bss->ni_bssid; 1456 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1457 struct ieee80211_key *k = &ic->ic_nw_keys[i]; 1458 1459 if (k->wk_keylen == 0) { 1460 ath_hal_keyreset(ah, i); 1461 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: reset key %u\n", 1462 __func__, i); 1463 } else { 1464 ath_keyset(sc, k, bssid); 1465 } 1466 } 1467 } 1468 1469 /* 1470 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1471 * each key, one for decrypt/encrypt and the other for the MIC. 1472 */ 1473 static u_int16_t 1474 key_alloc_2pair(struct ath_softc *sc) 1475 { 1476 #define N(a) (sizeof(a)/sizeof(a[0])) 1477 u_int i, keyix; 1478 1479 KASSERT(sc->sc_splitmic, ("key cache !split")); 1480 /* XXX could optimize */ 1481 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1482 u_int8_t b = sc->sc_keymap[i]; 1483 if (b != 0xff) { 1484 /* 1485 * One or more slots in this byte are free. 1486 */ 1487 keyix = i*NBBY; 1488 while (b & 1) { 1489 again: 1490 keyix++; 1491 b >>= 1; 1492 } 1493 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1494 if (isset(sc->sc_keymap, keyix+32) || 1495 isset(sc->sc_keymap, keyix+64) || 1496 isset(sc->sc_keymap, keyix+32+64)) { 1497 /* full pair unavailable */ 1498 /* XXX statistic */ 1499 if (keyix == (i+1)*NBBY) { 1500 /* no slots were appropriate, advance */ 1501 continue; 1502 } 1503 goto again; 1504 } 1505 setbit(sc->sc_keymap, keyix); 1506 setbit(sc->sc_keymap, keyix+64); 1507 setbit(sc->sc_keymap, keyix+32); 1508 setbit(sc->sc_keymap, keyix+32+64); 1509 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1510 "%s: key pair %u,%u %u,%u\n", 1511 __func__, keyix, keyix+64, 1512 keyix+32, keyix+32+64); 1513 return keyix; 1514 } 1515 } 1516 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1517 return IEEE80211_KEYIX_NONE; 1518 #undef N 1519 } 1520 1521 /* 1522 * Allocate a single key cache slot. 1523 */ 1524 static u_int16_t 1525 key_alloc_single(struct ath_softc *sc) 1526 { 1527 #define N(a) (sizeof(a)/sizeof(a[0])) 1528 u_int i, keyix; 1529 1530 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1531 for (i = 0; i < N(sc->sc_keymap); i++) { 1532 u_int8_t b = sc->sc_keymap[i]; 1533 if (b != 0xff) { 1534 /* 1535 * One or more slots are free. 1536 */ 1537 keyix = i*NBBY; 1538 while (b & 1) 1539 keyix++, b >>= 1; 1540 setbit(sc->sc_keymap, keyix); 1541 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1542 __func__, keyix); 1543 return keyix; 1544 } 1545 } 1546 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1547 return IEEE80211_KEYIX_NONE; 1548 #undef N 1549 } 1550 1551 /* 1552 * Allocate one or more key cache slots for a uniacst key. The 1553 * key itself is needed only to identify the cipher. For hardware 1554 * TKIP with split cipher+MIC keys we allocate two key cache slot 1555 * pairs so that we can setup separate TX and RX MIC keys. Note 1556 * that the MIC key for a TKIP key at slot i is assumed by the 1557 * hardware to be at slot i+64. This limits TKIP keys to the first 1558 * 64 entries. 1559 */ 1560 static int 1561 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k) 1562 { 1563 struct ath_softc *sc = ic->ic_ifp->if_softc; 1564 1565 /* 1566 * Group key allocation must be handled specially for 1567 * parts that do not support multicast key cache search 1568 * functionality. For those parts the key id must match 1569 * the h/w key index so lookups find the right key. On 1570 * parts w/ the key search facility we install the sender's 1571 * mac address (with the high bit set) and let the hardware 1572 * find the key w/o using the key id. This is preferred as 1573 * it permits us to support multiple users for adhoc and/or 1574 * multi-station operation. 1575 */ 1576 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1577 u_int keyix; 1578 1579 if (!(&ic->ic_nw_keys[0] <= k && 1580 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1581 /* should not happen */ 1582 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1583 "%s: bogus group key\n", __func__); 1584 return IEEE80211_KEYIX_NONE; 1585 } 1586 keyix = k - ic->ic_nw_keys; 1587 /* 1588 * XXX we pre-allocate the global keys so 1589 * have no way to check if they've already been allocated. 1590 */ 1591 return keyix; 1592 } 1593 1594 /* 1595 * We allocate two pair for TKIP when using the h/w to do 1596 * the MIC. For everything else, including software crypto, 1597 * we allocate a single entry. Note that s/w crypto requires 1598 * a pass-through slot on the 5211 and 5212. The 5210 does 1599 * not support pass-through cache entries and we map all 1600 * those requests to slot 0. 1601 */ 1602 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1603 return key_alloc_single(sc); 1604 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1605 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1606 return key_alloc_2pair(sc); 1607 } else { 1608 return key_alloc_single(sc); 1609 } 1610 } 1611 1612 /* 1613 * Delete an entry in the key cache allocated by ath_key_alloc. 1614 */ 1615 static int 1616 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1617 { 1618 struct ath_softc *sc = ic->ic_ifp->if_softc; 1619 struct ath_hal *ah = sc->sc_ah; 1620 const struct ieee80211_cipher *cip = k->wk_cipher; 1621 u_int keyix = k->wk_keyix; 1622 1623 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1624 1625 ath_hal_keyreset(ah, keyix); 1626 /* 1627 * Handle split tx/rx keying required for TKIP with h/w MIC. 1628 */ 1629 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1630 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1631 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1632 if (keyix >= IEEE80211_WEP_NKID) { 1633 /* 1634 * Don't touch keymap entries for global keys so 1635 * they are never considered for dynamic allocation. 1636 */ 1637 clrbit(sc->sc_keymap, keyix); 1638 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1639 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1640 sc->sc_splitmic) { 1641 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1642 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1643 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1644 } 1645 } 1646 return 1; 1647 } 1648 1649 /* 1650 * Set the key cache contents for the specified key. Key cache 1651 * slot(s) must already have been allocated by ath_key_alloc. 1652 */ 1653 static int 1654 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1655 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1656 { 1657 struct ath_softc *sc = ic->ic_ifp->if_softc; 1658 1659 return ath_keyset(sc, k, mac); 1660 } 1661 1662 /* 1663 * Block/unblock tx+rx processing while a key change is done. 1664 * We assume the caller serializes key management operations 1665 * so we only need to worry about synchronization with other 1666 * uses that originate in the driver. 1667 */ 1668 static void 1669 ath_key_update_begin(struct ieee80211com *ic) 1670 { 1671 struct ifnet *ifp = ic->ic_ifp; 1672 struct ath_softc *sc = ifp->if_softc; 1673 1674 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1675 #if 0 1676 tasklet_disable(&sc->sc_rxtq); 1677 #endif 1678 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1679 } 1680 1681 static void 1682 ath_key_update_end(struct ieee80211com *ic) 1683 { 1684 struct ifnet *ifp = ic->ic_ifp; 1685 struct ath_softc *sc = ifp->if_softc; 1686 1687 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1688 IF_UNLOCK(&ifp->if_snd); 1689 #if 0 1690 tasklet_enable(&sc->sc_rxtq); 1691 #endif 1692 } 1693 1694 /* 1695 * Calculate the receive filter according to the 1696 * operating mode and state: 1697 * 1698 * o always accept unicast, broadcast, and multicast traffic 1699 * o maintain current state of phy error reception (the hal 1700 * may enable phy error frames for noise immunity work) 1701 * o probe request frames are accepted only when operating in 1702 * hostap, adhoc, or monitor modes 1703 * o enable promiscuous mode according to the interface state 1704 * o accept beacons: 1705 * - when operating in adhoc mode so the 802.11 layer creates 1706 * node table entries for peers, 1707 * - when operating in station mode for collecting rssi data when 1708 * the station is otherwise quiet, or 1709 * - when scanning 1710 */ 1711 static u_int32_t 1712 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1713 { 1714 struct ieee80211com *ic = &sc->sc_ic; 1715 struct ath_hal *ah = sc->sc_ah; 1716 struct ifnet *ifp = &sc->sc_if; 1717 u_int32_t rfilt; 1718 1719 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1720 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1721 if (ic->ic_opmode != IEEE80211_M_STA) 1722 rfilt |= HAL_RX_FILTER_PROBEREQ; 1723 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1724 (ifp->if_flags & IFF_PROMISC)) 1725 rfilt |= HAL_RX_FILTER_PROM; 1726 if (ic->ic_opmode == IEEE80211_M_STA || 1727 ic->ic_opmode == IEEE80211_M_IBSS || 1728 state == IEEE80211_S_SCAN) 1729 rfilt |= HAL_RX_FILTER_BEACON; 1730 return rfilt; 1731 } 1732 1733 static void 1734 ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1735 { 1736 u_int32_t val; 1737 u_int8_t pos; 1738 1739 /* calculate XOR of eight 6bit values */ 1740 val = LE_READ_4(dl + 0); 1741 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1742 val = LE_READ_4(dl + 3); 1743 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1744 pos &= 0x3f; 1745 mfilt[pos / 32] |= (1 << (pos % 32)); 1746 } 1747 1748 static void 1749 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1750 { 1751 struct ifnet *ifp = &sc->sc_if; 1752 struct ether_multi *enm; 1753 struct ether_multistep estep; 1754 1755 mfilt[0] = mfilt[1] = 0; 1756 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1757 while (enm != NULL) { 1758 /* XXX Punt on ranges. */ 1759 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1760 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1761 ifp->if_flags |= IFF_ALLMULTI; 1762 return; 1763 } 1764 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1765 ETHER_NEXT_MULTI(estep, enm); 1766 } 1767 ifp->if_flags &= ~IFF_ALLMULTI; 1768 } 1769 1770 static void 1771 ath_mode_init(struct ath_softc *sc) 1772 { 1773 struct ieee80211com *ic = &sc->sc_ic; 1774 struct ath_hal *ah = sc->sc_ah; 1775 u_int32_t rfilt, mfilt[2]; 1776 1777 /* configure rx filter */ 1778 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1779 ath_hal_setrxfilter(ah, rfilt); 1780 1781 /* configure operational mode */ 1782 ath_hal_setopmode(ah); 1783 1784 /* 1785 * Handle any link-level address change. Note that we only 1786 * need to force ic_myaddr; any other addresses are handled 1787 * as a byproduct of the ifnet code marking the interface 1788 * down then up. 1789 * 1790 * XXX should get from lladdr instead of arpcom but that's more work 1791 */ 1792 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1793 ath_hal_setmac(ah, ic->ic_myaddr); 1794 1795 /* calculate and install multicast filter */ 1796 #ifdef __FreeBSD__ 1797 if ((sc->sc_if.if_flags & IFF_ALLMULTI) == 0) 1798 ath_mcastfilter_compute(sc, mfilt); 1799 else 1800 mfilt[0] = mfilt[1] = ~0; 1801 #endif 1802 #ifdef __NetBSD__ 1803 ath_mcastfilter_compute(sc, mfilt); 1804 #endif 1805 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1806 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1807 __func__, rfilt, mfilt[0], mfilt[1]); 1808 } 1809 1810 /* 1811 * Set the slot time based on the current setting. 1812 */ 1813 static void 1814 ath_setslottime(struct ath_softc *sc) 1815 { 1816 struct ieee80211com *ic = &sc->sc_ic; 1817 struct ath_hal *ah = sc->sc_ah; 1818 1819 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1820 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1821 else 1822 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1823 sc->sc_updateslot = OK; 1824 } 1825 1826 /* 1827 * Callback from the 802.11 layer to update the 1828 * slot time based on the current setting. 1829 */ 1830 static void 1831 ath_updateslot(struct ifnet *ifp) 1832 { 1833 struct ath_softc *sc = ifp->if_softc; 1834 struct ieee80211com *ic = &sc->sc_ic; 1835 1836 /* 1837 * When not coordinating the BSS, change the hardware 1838 * immediately. For other operation we defer the change 1839 * until beacon updates have propagated to the stations. 1840 */ 1841 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1842 sc->sc_updateslot = UPDATE; 1843 else 1844 ath_setslottime(sc); 1845 } 1846 1847 /* 1848 * Setup a h/w transmit queue for beacons. 1849 */ 1850 static int 1851 ath_beaconq_setup(struct ath_hal *ah) 1852 { 1853 HAL_TXQ_INFO qi; 1854 1855 memset(&qi, 0, sizeof(qi)); 1856 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1857 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1858 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1859 /* NB: don't enable any interrupts */ 1860 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1861 } 1862 1863 /* 1864 * Allocate and setup an initial beacon frame. 1865 */ 1866 static int 1867 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1868 { 1869 struct ieee80211com *ic = ni->ni_ic; 1870 struct ath_buf *bf; 1871 struct mbuf *m; 1872 int error; 1873 1874 bf = STAILQ_FIRST(&sc->sc_bbuf); 1875 if (bf == NULL) { 1876 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1877 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1878 return ENOMEM; /* XXX */ 1879 } 1880 /* 1881 * NB: the beacon data buffer must be 32-bit aligned; 1882 * we assume the mbuf routines will return us something 1883 * with this alignment (perhaps should assert). 1884 */ 1885 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1886 if (m == NULL) { 1887 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1888 __func__); 1889 sc->sc_stats.ast_be_nombuf++; 1890 return ENOMEM; 1891 } 1892 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1893 BUS_DMA_NOWAIT); 1894 if (error == 0) { 1895 bf->bf_m = m; 1896 bf->bf_node = ieee80211_ref_node(ni); 1897 } else { 1898 m_freem(m); 1899 } 1900 return error; 1901 } 1902 1903 /* 1904 * Setup the beacon frame for transmit. 1905 */ 1906 static void 1907 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1908 { 1909 #define USE_SHPREAMBLE(_ic) \ 1910 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1911 == IEEE80211_F_SHPREAMBLE) 1912 struct ieee80211_node *ni = bf->bf_node; 1913 struct ieee80211com *ic = ni->ni_ic; 1914 struct mbuf *m = bf->bf_m; 1915 struct ath_hal *ah = sc->sc_ah; 1916 struct ath_node *an = ATH_NODE(ni); 1917 struct ath_desc *ds; 1918 int flags, antenna; 1919 u_int8_t rate; 1920 1921 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1922 __func__, m, m->m_len); 1923 1924 /* setup descriptors */ 1925 ds = bf->bf_desc; 1926 1927 flags = HAL_TXDESC_NOACK; 1928 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1929 ds->ds_link = bf->bf_daddr; /* self-linked */ 1930 flags |= HAL_TXDESC_VEOL; 1931 /* 1932 * Let hardware handle antenna switching. 1933 */ 1934 antenna = 0; 1935 } else { 1936 ds->ds_link = 0; 1937 /* 1938 * Switch antenna every 4 beacons. 1939 * XXX assumes two antenna 1940 */ 1941 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 1942 } 1943 1944 KASSERT(bf->bf_nseg == 1, 1945 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 1946 ds->ds_data = bf->bf_segs[0].ds_addr; 1947 /* 1948 * Calculate rate code. 1949 * XXX everything at min xmit rate 1950 */ 1951 if (USE_SHPREAMBLE(ic)) 1952 rate = an->an_tx_mgtratesp; 1953 else 1954 rate = an->an_tx_mgtrate; 1955 ath_hal_setuptxdesc(ah, ds 1956 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 1957 , sizeof(struct ieee80211_frame)/* header length */ 1958 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1959 , ni->ni_txpower /* txpower XXX */ 1960 , rate, 1 /* series 0 rate/tries */ 1961 , HAL_TXKEYIX_INVALID /* no encryption */ 1962 , antenna /* antenna mode */ 1963 , flags /* no ack, veol for beacons */ 1964 , 0 /* rts/cts rate */ 1965 , 0 /* rts/cts duration */ 1966 ); 1967 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1968 ath_hal_filltxdesc(ah, ds 1969 , roundup(m->m_len, 4) /* buffer length */ 1970 , AH_TRUE /* first segment */ 1971 , AH_TRUE /* last segment */ 1972 , ds /* first descriptor */ 1973 ); 1974 /* XXX bus_dmamap_sync? -dcy */ 1975 #undef USE_SHPREAMBLE 1976 } 1977 1978 /* 1979 * Transmit a beacon frame at SWBA. Dynamic updates to the 1980 * frame contents are done as needed and the slot time is 1981 * also adjusted based on current state. 1982 */ 1983 static void 1984 ath_beacon_proc(void *arg, int pending) 1985 { 1986 struct ath_softc *sc = arg; 1987 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 1988 struct ieee80211_node *ni = bf->bf_node; 1989 struct ieee80211com *ic = ni->ni_ic; 1990 struct ath_hal *ah = sc->sc_ah; 1991 struct mbuf *m; 1992 int ncabq, error, otherant; 1993 1994 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 1995 __func__, pending); 1996 1997 if (ic->ic_opmode == IEEE80211_M_STA || 1998 ic->ic_opmode == IEEE80211_M_MONITOR || 1999 bf == NULL || bf->bf_m == NULL) { 2000 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2001 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2002 return; 2003 } 2004 /* 2005 * Check if the previous beacon has gone out. If 2006 * not don't don't try to post another, skip this 2007 * period and wait for the next. Missed beacons 2008 * indicate a problem and should not occur. If we 2009 * miss too many consecutive beacons reset the device. 2010 */ 2011 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2012 sc->sc_bmisscount++; 2013 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2014 "%s: missed %u consecutive beacons\n", 2015 __func__, sc->sc_bmisscount); 2016 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2017 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2018 return; 2019 } 2020 if (sc->sc_bmisscount != 0) { 2021 DPRINTF(sc, ATH_DEBUG_BEACON, 2022 "%s: resume beacon xmit after %u misses\n", 2023 __func__, sc->sc_bmisscount); 2024 sc->sc_bmisscount = 0; 2025 } 2026 2027 /* 2028 * Update dynamic beacon contents. If this returns 2029 * non-zero then we need to remap the memory because 2030 * the beacon frame changed size (probably because 2031 * of the TIM bitmap). 2032 */ 2033 m = bf->bf_m; 2034 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2035 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2036 /* XXX too conservative? */ 2037 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2038 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2039 BUS_DMA_NOWAIT); 2040 if (error != 0) { 2041 if_printf(&sc->sc_if, 2042 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2043 __func__, error); 2044 return; 2045 } 2046 } 2047 2048 /* 2049 * Handle slot time change when a non-ERP station joins/leaves 2050 * an 11g network. The 802.11 layer notifies us via callback, 2051 * we mark updateslot, then wait one beacon before effecting 2052 * the change. This gives associated stations at least one 2053 * beacon interval to note the state change. 2054 */ 2055 /* XXX locking */ 2056 if (sc->sc_updateslot == UPDATE) 2057 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2058 else if (sc->sc_updateslot == COMMIT) 2059 ath_setslottime(sc); /* commit change to h/w */ 2060 2061 /* 2062 * Check recent per-antenna transmit statistics and flip 2063 * the default antenna if noticeably more frames went out 2064 * on the non-default antenna. 2065 * XXX assumes 2 anntenae 2066 */ 2067 otherant = sc->sc_defant & 1 ? 2 : 1; 2068 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2069 ath_setdefantenna(sc, otherant); 2070 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2071 2072 /* 2073 * Construct tx descriptor. 2074 */ 2075 ath_beacon_setup(sc, bf); 2076 2077 /* 2078 * Stop any current dma and put the new frame on the queue. 2079 * This should never fail since we check above that no frames 2080 * are still pending on the queue. 2081 */ 2082 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2083 DPRINTF(sc, ATH_DEBUG_ANY, 2084 "%s: beacon queue %u did not stop?\n", 2085 __func__, sc->sc_bhalq); 2086 } 2087 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2088 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2089 2090 /* 2091 * Enable the CAB queue before the beacon queue to 2092 * insure cab frames are triggered by this beacon. 2093 */ 2094 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2095 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2096 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2097 ath_hal_txstart(ah, sc->sc_bhalq); 2098 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2099 "%s: TXDP[%u] = %p (%p)\n", __func__, 2100 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2101 2102 sc->sc_stats.ast_be_xmit++; 2103 } 2104 2105 /* 2106 * Reset the hardware after detecting beacons have stopped. 2107 */ 2108 static void 2109 ath_bstuck_proc(void *arg, int pending) 2110 { 2111 struct ath_softc *sc = arg; 2112 struct ifnet *ifp = &sc->sc_if; 2113 2114 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2115 sc->sc_bmisscount); 2116 ath_reset(ifp); 2117 } 2118 2119 /* 2120 * Reclaim beacon resources. 2121 */ 2122 static void 2123 ath_beacon_free(struct ath_softc *sc) 2124 { 2125 struct ath_buf *bf; 2126 2127 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2128 if (bf->bf_m != NULL) { 2129 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2130 m_freem(bf->bf_m); 2131 bf->bf_m = NULL; 2132 } 2133 if (bf->bf_node != NULL) { 2134 ieee80211_free_node(bf->bf_node); 2135 bf->bf_node = NULL; 2136 } 2137 } 2138 } 2139 2140 /* 2141 * Configure the beacon and sleep timers. 2142 * 2143 * When operating as an AP this resets the TSF and sets 2144 * up the hardware to notify us when we need to issue beacons. 2145 * 2146 * When operating in station mode this sets up the beacon 2147 * timers according to the timestamp of the last received 2148 * beacon and the current TSF, configures PCF and DTIM 2149 * handling, programs the sleep registers so the hardware 2150 * will wakeup in time to receive beacons, and configures 2151 * the beacon miss handling so we'll receive a BMISS 2152 * interrupt when we stop seeing beacons from the AP 2153 * we've associated with. 2154 */ 2155 static void 2156 ath_beacon_config(struct ath_softc *sc) 2157 { 2158 struct ath_hal *ah = sc->sc_ah; 2159 struct ieee80211com *ic = &sc->sc_ic; 2160 struct ieee80211_node *ni = ic->ic_bss; 2161 u_int32_t nexttbtt, intval; 2162 2163 nexttbtt = (LE_READ_4(ni->ni_tstamp.data + 4) << 22) | 2164 (LE_READ_4(ni->ni_tstamp.data) >> 10); 2165 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2166 if (nexttbtt == 0) /* e.g. for ap mode */ 2167 nexttbtt = intval; 2168 else if (intval) /* NB: can be 0 for monitor mode */ 2169 nexttbtt = roundup(nexttbtt, intval); 2170 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2171 __func__, nexttbtt, intval, ni->ni_intval); 2172 if (ic->ic_opmode == IEEE80211_M_STA) { 2173 HAL_BEACON_STATE bs; 2174 2175 /* NB: no PCF support right now */ 2176 memset(&bs, 0, sizeof(bs)); 2177 bs.bs_intval = intval; 2178 bs.bs_nexttbtt = nexttbtt; 2179 bs.bs_dtimperiod = bs.bs_intval; 2180 bs.bs_nextdtim = nexttbtt; 2181 /* 2182 * The 802.11 layer records the offset to the DTIM 2183 * bitmap while receiving beacons; use it here to 2184 * enable h/w detection of our AID being marked in 2185 * the bitmap vector (to indicate frames for us are 2186 * pending at the AP). 2187 */ 2188 bs.bs_timoffset = ni->ni_timoff; 2189 /* 2190 * Calculate the number of consecutive beacons to miss 2191 * before taking a BMISS interrupt. The configuration 2192 * is specified in ms, so we need to convert that to 2193 * TU's and then calculate based on the beacon interval. 2194 * Note that we clamp the result to at most 10 beacons. 2195 */ 2196 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2197 if (bs.bs_bmissthreshold > 10) 2198 bs.bs_bmissthreshold = 10; 2199 else if (bs.bs_bmissthreshold <= 0) 2200 bs.bs_bmissthreshold = 1; 2201 2202 /* 2203 * Calculate sleep duration. The configuration is 2204 * given in ms. We insure a multiple of the beacon 2205 * period is used. Also, if the sleep duration is 2206 * greater than the DTIM period then it makes senses 2207 * to make it a multiple of that. 2208 * 2209 * XXX fixed at 100ms 2210 */ 2211 bs.bs_sleepduration = 2212 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2213 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2214 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2215 2216 DPRINTF(sc, ATH_DEBUG_BEACON, 2217 "%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2218 , __func__ 2219 , bs.bs_intval 2220 , bs.bs_nexttbtt 2221 , bs.bs_dtimperiod 2222 , bs.bs_nextdtim 2223 , bs.bs_bmissthreshold 2224 , bs.bs_sleepduration 2225 , bs.bs_cfpperiod 2226 , bs.bs_cfpmaxduration 2227 , bs.bs_cfpnext 2228 , bs.bs_timoffset 2229 ); 2230 ath_hal_intrset(ah, 0); 2231 ath_hal_beacontimers(ah, &bs); 2232 sc->sc_imask |= HAL_INT_BMISS; 2233 ath_hal_intrset(ah, sc->sc_imask); 2234 } else { 2235 ath_hal_intrset(ah, 0); 2236 if (nexttbtt == intval) 2237 intval |= HAL_BEACON_RESET_TSF; 2238 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2239 /* 2240 * In IBSS mode enable the beacon timers but only 2241 * enable SWBA interrupts if we need to manually 2242 * prepare beacon frames. Otherwise we use a 2243 * self-linked tx descriptor and let the hardware 2244 * deal with things. 2245 */ 2246 intval |= HAL_BEACON_ENA; 2247 if (!sc->sc_hasveol) 2248 sc->sc_imask |= HAL_INT_SWBA; 2249 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2250 /* 2251 * In AP mode we enable the beacon timers and 2252 * SWBA interrupts to prepare beacon frames. 2253 */ 2254 intval |= HAL_BEACON_ENA; 2255 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2256 } 2257 ath_hal_beaconinit(ah, nexttbtt, intval); 2258 sc->sc_bmisscount = 0; 2259 ath_hal_intrset(ah, sc->sc_imask); 2260 /* 2261 * When using a self-linked beacon descriptor in 2262 * ibss mode load it once here. 2263 */ 2264 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2265 ath_beacon_proc(sc, 0); 2266 } 2267 } 2268 2269 static int 2270 ath_descdma_setup(struct ath_softc *sc, 2271 struct ath_descdma *dd, ath_bufhead *head, 2272 const char *name, int nbuf, int ndesc) 2273 { 2274 #define DS2PHYS(_dd, _ds) \ 2275 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2276 struct ifnet *ifp = &sc->sc_if; 2277 struct ath_desc *ds; 2278 struct ath_buf *bf; 2279 int i, bsize, error; 2280 2281 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2282 __func__, name, nbuf, ndesc); 2283 2284 dd->dd_name = name; 2285 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2286 2287 /* 2288 * Setup DMA descriptor area. 2289 */ 2290 dd->dd_dmat = sc->sc_dmat; 2291 2292 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2293 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2294 2295 if (error != 0) { 2296 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2297 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2298 goto fail0; 2299 } 2300 2301 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2302 dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2303 if (error != 0) { 2304 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2305 nbuf * ndesc, dd->dd_name, error); 2306 goto fail1; 2307 } 2308 2309 /* allocate descriptors */ 2310 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2311 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2312 if (error != 0) { 2313 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2314 "error %u\n", dd->dd_name, error); 2315 goto fail2; 2316 } 2317 2318 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2319 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2320 if (error != 0) { 2321 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2322 dd->dd_name, error); 2323 goto fail3; 2324 } 2325 2326 ds = dd->dd_desc; 2327 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2328 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2329 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2330 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2331 2332 /* allocate rx buffers */ 2333 bsize = sizeof(struct ath_buf) * nbuf; 2334 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2335 if (bf == NULL) { 2336 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2337 dd->dd_name, bsize); 2338 goto fail4; 2339 } 2340 dd->dd_bufptr = bf; 2341 2342 STAILQ_INIT(head); 2343 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2344 bf->bf_desc = ds; 2345 bf->bf_daddr = DS2PHYS(dd, ds); 2346 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2347 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2348 if (error != 0) { 2349 if_printf(ifp, "unable to create dmamap for %s " 2350 "buffer %u, error %u\n", dd->dd_name, i, error); 2351 ath_descdma_cleanup(sc, dd, head); 2352 return error; 2353 } 2354 STAILQ_INSERT_TAIL(head, bf, bf_list); 2355 } 2356 return 0; 2357 fail4: 2358 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2359 fail3: 2360 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2361 fail2: 2362 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2363 fail1: 2364 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2365 fail0: 2366 memset(dd, 0, sizeof(*dd)); 2367 return error; 2368 #undef DS2PHYS 2369 } 2370 2371 static void 2372 ath_descdma_cleanup(struct ath_softc *sc, 2373 struct ath_descdma *dd, ath_bufhead *head) 2374 { 2375 struct ath_buf *bf; 2376 struct ieee80211_node *ni; 2377 2378 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2379 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2380 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2381 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2382 2383 STAILQ_FOREACH(bf, head, bf_list) { 2384 if (bf->bf_m) { 2385 m_freem(bf->bf_m); 2386 bf->bf_m = NULL; 2387 } 2388 if (bf->bf_dmamap != NULL) { 2389 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2390 bf->bf_dmamap = NULL; 2391 } 2392 ni = bf->bf_node; 2393 bf->bf_node = NULL; 2394 if (ni != NULL) { 2395 /* 2396 * Reclaim node reference. 2397 */ 2398 ieee80211_free_node(ni); 2399 } 2400 } 2401 2402 STAILQ_INIT(head); 2403 free(dd->dd_bufptr, M_ATHDEV); 2404 memset(dd, 0, sizeof(*dd)); 2405 } 2406 2407 static int 2408 ath_desc_alloc(struct ath_softc *sc) 2409 { 2410 int error; 2411 2412 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2413 "rx", ATH_RXBUF, 1); 2414 if (error != 0) 2415 return error; 2416 2417 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2418 "tx", ATH_TXBUF, ATH_TXDESC); 2419 if (error != 0) { 2420 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2421 return error; 2422 } 2423 2424 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2425 "beacon", 1, 1); 2426 if (error != 0) { 2427 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2428 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2429 return error; 2430 } 2431 return 0; 2432 } 2433 2434 static void 2435 ath_desc_free(struct ath_softc *sc) 2436 { 2437 2438 if (sc->sc_bdma.dd_desc_len != 0) 2439 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2440 if (sc->sc_txdma.dd_desc_len != 0) 2441 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2442 if (sc->sc_rxdma.dd_desc_len != 0) 2443 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2444 } 2445 2446 static struct ieee80211_node * 2447 ath_node_alloc(struct ieee80211_node_table *nt) 2448 { 2449 struct ieee80211com *ic = nt->nt_ic; 2450 struct ath_softc *sc = ic->ic_ifp->if_softc; 2451 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2452 struct ath_node *an; 2453 2454 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2455 if (an == NULL) { 2456 /* XXX stat+msg */ 2457 return NULL; 2458 } 2459 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2460 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2461 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2462 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2463 ath_rate_node_init(sc, an); 2464 2465 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2466 return &an->an_node; 2467 } 2468 2469 static void 2470 ath_node_free(struct ieee80211_node *ni) 2471 { 2472 struct ieee80211com *ic = ni->ni_ic; 2473 struct ath_softc *sc = ic->ic_ifp->if_softc; 2474 2475 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2476 2477 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2478 sc->sc_node_free(ni); 2479 } 2480 2481 static u_int8_t 2482 ath_node_getrssi(const struct ieee80211_node *ni) 2483 { 2484 #define HAL_EP_RND(x, mul) \ 2485 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2486 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2487 int32_t rssi; 2488 2489 /* 2490 * When only one frame is received there will be no state in 2491 * avgrssi so fallback on the value recorded by the 802.11 layer. 2492 */ 2493 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2494 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2495 else 2496 rssi = ni->ni_rssi; 2497 /* NB: theoretically we shouldn't need this, but be paranoid */ 2498 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2499 #undef HAL_EP_RND 2500 } 2501 2502 static int 2503 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2504 { 2505 struct ath_hal *ah = sc->sc_ah; 2506 int error; 2507 struct mbuf *m; 2508 struct ath_desc *ds; 2509 2510 m = bf->bf_m; 2511 if (m == NULL) { 2512 /* 2513 * NB: by assigning a page to the rx dma buffer we 2514 * implicitly satisfy the Atheros requirement that 2515 * this buffer be cache-line-aligned and sized to be 2516 * multiple of the cache line size. Not doing this 2517 * causes weird stuff to happen (for the 5210 at least). 2518 */ 2519 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2520 if (m == NULL) { 2521 DPRINTF(sc, ATH_DEBUG_ANY, 2522 "%s: no mbuf/cluster\n", __func__); 2523 sc->sc_stats.ast_rx_nombuf++; 2524 return ENOMEM; 2525 } 2526 bf->bf_m = m; 2527 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2528 2529 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2530 bf->bf_dmamap, m, 2531 BUS_DMA_NOWAIT); 2532 if (error != 0) { 2533 DPRINTF(sc, ATH_DEBUG_ANY, 2534 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2535 __func__, error); 2536 sc->sc_stats.ast_rx_busdma++; 2537 return error; 2538 } 2539 KASSERT(bf->bf_nseg == 1, 2540 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2541 } 2542 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2543 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2544 2545 /* 2546 * Setup descriptors. For receive we always terminate 2547 * the descriptor list with a self-linked entry so we'll 2548 * not get overrun under high load (as can happen with a 2549 * 5212 when ANI processing enables PHY error frames). 2550 * 2551 * To insure the last descriptor is self-linked we create 2552 * each descriptor as self-linked and add it to the end. As 2553 * each additional descriptor is added the previous self-linked 2554 * entry is ``fixed'' naturally. This should be safe even 2555 * if DMA is happening. When processing RX interrupts we 2556 * never remove/process the last, self-linked, entry on the 2557 * descriptor list. This insures the hardware always has 2558 * someplace to write a new frame. 2559 */ 2560 ds = bf->bf_desc; 2561 ds->ds_link = bf->bf_daddr; /* link to self */ 2562 ds->ds_data = bf->bf_segs[0].ds_addr; 2563 ath_hal_setuprxdesc(ah, ds 2564 , m->m_len /* buffer size */ 2565 , 0 2566 ); 2567 2568 if (sc->sc_rxlink != NULL) 2569 *sc->sc_rxlink = bf->bf_daddr; 2570 sc->sc_rxlink = &ds->ds_link; 2571 return 0; 2572 } 2573 2574 static uint64_t 2575 ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) 2576 { 2577 uint64_t tsf; 2578 2579 KASSERT((rstamp & 0xffff0000) == 0, 2580 ("rx timestamp > 16 bits wide, %" PRIu32, rstamp)); 2581 2582 tsf = ath_hal_gettsf64(ah); 2583 2584 /* Compensate for rollover. */ 2585 if ((tsf & 0xffff) <= rstamp) 2586 tsf -= 0x10000; 2587 2588 return (tsf & ~(uint64_t)0xffff) | rstamp; 2589 } 2590 2591 /* 2592 * Extend 15-bit time stamp from rx descriptor to 2593 * a full 64-bit TSF using the current h/w TSF. 2594 */ 2595 static __inline u_int64_t 2596 ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp) 2597 { 2598 u_int64_t tsf; 2599 2600 tsf = ath_hal_gettsf64(ah); 2601 if ((tsf & 0x7fff) < rstamp) 2602 tsf -= 0x8000; 2603 return ((tsf &~ 0x7fff) | rstamp); 2604 } 2605 2606 /* 2607 * Intercept management frames to collect beacon rssi data 2608 * and to do ibss merges. 2609 */ 2610 static void 2611 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2612 struct ieee80211_node *ni, 2613 int subtype, int rssi, u_int32_t rstamp) 2614 { 2615 struct ath_softc *sc = ic->ic_ifp->if_softc; 2616 2617 /* 2618 * Call up first so subsequent work can use information 2619 * potentially stored in the node (e.g. for ibss merge). 2620 */ 2621 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2622 switch (subtype) { 2623 case IEEE80211_FC0_SUBTYPE_BEACON: 2624 /* update rssi statistics for use by the hal */ 2625 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2626 /* fall thru... */ 2627 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2628 if (ic->ic_opmode == IEEE80211_M_IBSS && 2629 ic->ic_state == IEEE80211_S_RUN) { 2630 u_int64_t tsf = ath_tsf_extend(sc->sc_ah, rstamp); 2631 2632 /* 2633 * Handle ibss merge as needed; check the tsf on the 2634 * frame before attempting the merge. The 802.11 spec 2635 * says the station should change it's bssid to match 2636 * the oldest station with the same ssid, where oldest 2637 * is determined by the tsf. Note that hardware 2638 * reconfiguration happens through callback to 2639 * ath_newstate as the state machine will go from 2640 * RUN -> RUN when this happens. 2641 */ 2642 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2643 DPRINTF(sc, ATH_DEBUG_STATE, 2644 "ibss merge, rstamp %u tsf %ju " 2645 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2646 (uintmax_t)ni->ni_tstamp.tsf); 2647 (void) ieee80211_ibss_merge(ic, ni); 2648 } 2649 } 2650 break; 2651 } 2652 } 2653 2654 /* 2655 * Set the default antenna. 2656 */ 2657 static void 2658 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2659 { 2660 struct ath_hal *ah = sc->sc_ah; 2661 2662 /* XXX block beacon interrupts */ 2663 ath_hal_setdefantenna(ah, antenna); 2664 if (sc->sc_defant != antenna) 2665 sc->sc_stats.ast_ant_defswitch++; 2666 sc->sc_defant = antenna; 2667 sc->sc_rxotherant = 0; 2668 } 2669 2670 static void 2671 ath_rx_proc(void *arg, int npending) 2672 { 2673 #define PA2DESC(_sc, _pa) \ 2674 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2675 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2676 struct ath_softc *sc = arg; 2677 struct ath_buf *bf; 2678 struct ieee80211com *ic = &sc->sc_ic; 2679 struct ifnet *ifp = &sc->sc_if; 2680 struct ath_hal *ah = sc->sc_ah; 2681 struct ath_desc *ds; 2682 struct mbuf *m; 2683 struct ieee80211_node *ni; 2684 struct ath_node *an; 2685 int len, type; 2686 u_int phyerr; 2687 HAL_STATUS status; 2688 2689 NET_LOCK_GIANT(); /* XXX */ 2690 2691 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2692 do { 2693 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2694 if (bf == NULL) { /* NB: shouldn't happen */ 2695 if_printf(ifp, "%s: no buffer!\n", __func__); 2696 break; 2697 } 2698 ds = bf->bf_desc; 2699 if (ds->ds_link == bf->bf_daddr) { 2700 /* NB: never process the self-linked entry at the end */ 2701 break; 2702 } 2703 m = bf->bf_m; 2704 if (m == NULL) { /* NB: shouldn't happen */ 2705 if_printf(ifp, "%s: no mbuf!\n", __func__); 2706 continue; 2707 } 2708 /* XXX sync descriptor memory */ 2709 /* 2710 * Must provide the virtual address of the current 2711 * descriptor, the physical address, and the virtual 2712 * address of the next descriptor in the h/w chain. 2713 * This allows the HAL to look ahead to see if the 2714 * hardware is done with a descriptor by checking the 2715 * done bit in the following descriptor and the address 2716 * of the current descriptor the DMA engine is working 2717 * on. All this is necessary because of our use of 2718 * a self-linked list to avoid rx overruns. 2719 */ 2720 status = ath_hal_rxprocdesc(ah, ds, 2721 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2722 #ifdef AR_DEBUG 2723 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2724 ath_printrxbuf(bf, status == HAL_OK); 2725 #endif 2726 if (status == HAL_EINPROGRESS) 2727 break; 2728 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2729 if (ds->ds_rxstat.rs_more) { 2730 /* 2731 * Frame spans multiple descriptors; this 2732 * cannot happen yet as we don't support 2733 * jumbograms. If not in monitor mode, 2734 * discard the frame. 2735 */ 2736 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2737 sc->sc_stats.ast_rx_toobig++; 2738 goto rx_next; 2739 } 2740 /* fall thru for monitor mode handling... */ 2741 } else if (ds->ds_rxstat.rs_status != 0) { 2742 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2743 sc->sc_stats.ast_rx_crcerr++; 2744 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2745 sc->sc_stats.ast_rx_fifoerr++; 2746 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2747 sc->sc_stats.ast_rx_phyerr++; 2748 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2749 sc->sc_stats.ast_rx_phy[phyerr]++; 2750 goto rx_next; 2751 } 2752 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2753 /* 2754 * Decrypt error. If the error occurred 2755 * because there was no hardware key, then 2756 * let the frame through so the upper layers 2757 * can process it. This is necessary for 5210 2758 * parts which have no way to setup a ``clear'' 2759 * key cache entry. 2760 * 2761 * XXX do key cache faulting 2762 */ 2763 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2764 goto rx_accept; 2765 sc->sc_stats.ast_rx_badcrypt++; 2766 } 2767 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2768 sc->sc_stats.ast_rx_badmic++; 2769 /* 2770 * Do minimal work required to hand off 2771 * the 802.11 header for notifcation. 2772 */ 2773 /* XXX frag's and qos frames */ 2774 len = ds->ds_rxstat.rs_datalen; 2775 if (len >= sizeof (struct ieee80211_frame)) { 2776 bus_dmamap_sync(sc->sc_dmat, 2777 bf->bf_dmamap, 2778 0, bf->bf_dmamap->dm_mapsize, 2779 BUS_DMASYNC_POSTREAD); 2780 ieee80211_notify_michael_failure(ic, 2781 mtod(m, struct ieee80211_frame *), 2782 sc->sc_splitmic ? 2783 ds->ds_rxstat.rs_keyix-32 : 2784 ds->ds_rxstat.rs_keyix 2785 ); 2786 } 2787 } 2788 ifp->if_ierrors++; 2789 /* 2790 * Reject error frames, we normally don't want 2791 * to see them in monitor mode (in monitor mode 2792 * allow through packets that have crypto problems). 2793 */ 2794 if ((ds->ds_rxstat.rs_status &~ 2795 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2796 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2797 goto rx_next; 2798 } 2799 rx_accept: 2800 /* 2801 * Sync and unmap the frame. At this point we're 2802 * committed to passing the mbuf somewhere so clear 2803 * bf_m; this means a new sk_buff must be allocated 2804 * when the rx descriptor is setup again to receive 2805 * another frame. 2806 */ 2807 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2808 0, bf->bf_dmamap->dm_mapsize, 2809 BUS_DMASYNC_POSTREAD); 2810 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2811 bf->bf_m = NULL; 2812 2813 m->m_pkthdr.rcvif = ifp; 2814 len = ds->ds_rxstat.rs_datalen; 2815 m->m_pkthdr.len = m->m_len = len; 2816 2817 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2818 2819 #if NBPFILTER > 0 2820 if (sc->sc_drvbpf) { 2821 u_int8_t rix; 2822 2823 /* 2824 * Discard anything shorter than an ack or cts. 2825 */ 2826 if (len < IEEE80211_ACK_LEN) { 2827 DPRINTF(sc, ATH_DEBUG_RECV, 2828 "%s: runt packet %d\n", 2829 __func__, len); 2830 sc->sc_stats.ast_rx_tooshort++; 2831 m_freem(m); 2832 goto rx_next; 2833 } 2834 rix = ds->ds_rxstat.rs_rate; 2835 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2836 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2837 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2838 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2839 /* XXX TSF */ 2840 2841 bpf_mtap2(sc->sc_drvbpf, 2842 &sc->sc_rx_th, sc->sc_rx_th_len, m); 2843 } 2844 #endif 2845 2846 /* 2847 * From this point on we assume the frame is at least 2848 * as large as ieee80211_frame_min; verify that. 2849 */ 2850 if (len < IEEE80211_MIN_LEN) { 2851 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2852 __func__, len); 2853 sc->sc_stats.ast_rx_tooshort++; 2854 m_freem(m); 2855 goto rx_next; 2856 } 2857 2858 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2859 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2860 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2861 ds->ds_rxstat.rs_rssi); 2862 } 2863 2864 m_adj(m, -IEEE80211_CRC_LEN); 2865 2866 /* 2867 * Locate the node for sender, track state, and then 2868 * pass the (referenced) node up to the 802.11 layer 2869 * for its use. 2870 */ 2871 ni = ieee80211_find_rxnode(ic, 2872 mtod(m, const struct ieee80211_frame_min *)); 2873 2874 /* 2875 * Track rx rssi and do any rx antenna management. 2876 */ 2877 an = ATH_NODE(ni); 2878 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2879 if (sc->sc_diversity) { 2880 /* 2881 * When using fast diversity, change the default rx 2882 * antenna if diversity chooses the other antenna 3 2883 * times in a row. 2884 */ 2885 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2886 if (++sc->sc_rxotherant >= 3) 2887 ath_setdefantenna(sc, 2888 ds->ds_rxstat.rs_antenna); 2889 } else 2890 sc->sc_rxotherant = 0; 2891 } 2892 2893 /* 2894 * Send frame up for processing. 2895 */ 2896 type = ieee80211_input(ic, m, ni, 2897 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2898 2899 if (sc->sc_softled) { 2900 /* 2901 * Blink for any data frame. Otherwise do a 2902 * heartbeat-style blink when idle. The latter 2903 * is mainly for station mode where we depend on 2904 * periodic beacon frames to trigger the poll event. 2905 */ 2906 if (type == IEEE80211_FC0_TYPE_DATA) { 2907 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 2908 ath_led_event(sc, ATH_LED_RX); 2909 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 2910 ath_led_event(sc, ATH_LED_POLL); 2911 } 2912 2913 /* 2914 * Reclaim node reference. 2915 */ 2916 ieee80211_free_node(ni); 2917 rx_next: 2918 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2919 } while (ath_rxbuf_init(sc, bf) == 0); 2920 2921 /* rx signal state monitoring */ 2922 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 2923 2924 #ifdef __NetBSD__ 2925 /* XXX Why isn't this necessary in FreeBSD? */ 2926 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 2927 ath_start(ifp); 2928 #endif /* __NetBSD__ */ 2929 2930 NET_UNLOCK_GIANT(); /* XXX */ 2931 #undef PA2DESC 2932 } 2933 2934 /* 2935 * Setup a h/w transmit queue. 2936 */ 2937 static struct ath_txq * 2938 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 2939 { 2940 #define N(a) (sizeof(a)/sizeof(a[0])) 2941 struct ath_hal *ah = sc->sc_ah; 2942 HAL_TXQ_INFO qi; 2943 int qnum; 2944 2945 memset(&qi, 0, sizeof(qi)); 2946 qi.tqi_subtype = subtype; 2947 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2948 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2949 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2950 /* 2951 * Enable interrupts only for EOL and DESC conditions. 2952 * We mark tx descriptors to receive a DESC interrupt 2953 * when a tx queue gets deep; otherwise waiting for the 2954 * EOL to reap descriptors. Note that this is done to 2955 * reduce interrupt load and this only defers reaping 2956 * descriptors, never transmitting frames. Aside from 2957 * reducing interrupts this also permits more concurrency. 2958 * The only potential downside is if the tx queue backs 2959 * up in which case the top half of the kernel may backup 2960 * due to a lack of tx descriptors. 2961 */ 2962 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 2963 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 2964 if (qnum == -1) { 2965 /* 2966 * NB: don't print a message, this happens 2967 * normally on parts with too few tx queues 2968 */ 2969 return NULL; 2970 } 2971 if (qnum >= N(sc->sc_txq)) { 2972 device_printf(sc->sc_dev, 2973 "hal qnum %u out of range, max %zu!\n", 2974 qnum, N(sc->sc_txq)); 2975 ath_hal_releasetxqueue(ah, qnum); 2976 return NULL; 2977 } 2978 if (!ATH_TXQ_SETUP(sc, qnum)) { 2979 struct ath_txq *txq = &sc->sc_txq[qnum]; 2980 2981 txq->axq_qnum = qnum; 2982 txq->axq_depth = 0; 2983 txq->axq_intrcnt = 0; 2984 txq->axq_link = NULL; 2985 STAILQ_INIT(&txq->axq_q); 2986 ATH_TXQ_LOCK_INIT(sc, txq); 2987 sc->sc_txqsetup |= 1<<qnum; 2988 } 2989 return &sc->sc_txq[qnum]; 2990 #undef N 2991 } 2992 2993 /* 2994 * Setup a hardware data transmit queue for the specified 2995 * access control. The hal may not support all requested 2996 * queues in which case it will return a reference to a 2997 * previously setup queue. We record the mapping from ac's 2998 * to h/w queues for use by ath_tx_start and also track 2999 * the set of h/w queues being used to optimize work in the 3000 * transmit interrupt handler and related routines. 3001 */ 3002 static int 3003 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3004 { 3005 #define N(a) (sizeof(a)/sizeof(a[0])) 3006 struct ath_txq *txq; 3007 3008 if (ac >= N(sc->sc_ac2q)) { 3009 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3010 ac, N(sc->sc_ac2q)); 3011 return 0; 3012 } 3013 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3014 if (txq != NULL) { 3015 sc->sc_ac2q[ac] = txq; 3016 return 1; 3017 } else 3018 return 0; 3019 #undef N 3020 } 3021 3022 /* 3023 * Update WME parameters for a transmit queue. 3024 */ 3025 static int 3026 ath_txq_update(struct ath_softc *sc, int ac) 3027 { 3028 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3029 #define ATH_TXOP_TO_US(v) (v<<5) 3030 struct ieee80211com *ic = &sc->sc_ic; 3031 struct ath_txq *txq = sc->sc_ac2q[ac]; 3032 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3033 struct ath_hal *ah = sc->sc_ah; 3034 HAL_TXQ_INFO qi; 3035 3036 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3037 qi.tqi_aifs = wmep->wmep_aifsn; 3038 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3039 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3040 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3041 3042 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3043 device_printf(sc->sc_dev, "unable to update hardware queue " 3044 "parameters for %s traffic!\n", 3045 ieee80211_wme_acnames[ac]); 3046 return 0; 3047 } else { 3048 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3049 return 1; 3050 } 3051 #undef ATH_TXOP_TO_US 3052 #undef ATH_EXPONENT_TO_VALUE 3053 } 3054 3055 /* 3056 * Callback from the 802.11 layer to update WME parameters. 3057 */ 3058 static int 3059 ath_wme_update(struct ieee80211com *ic) 3060 { 3061 struct ath_softc *sc = ic->ic_ifp->if_softc; 3062 3063 return !ath_txq_update(sc, WME_AC_BE) || 3064 !ath_txq_update(sc, WME_AC_BK) || 3065 !ath_txq_update(sc, WME_AC_VI) || 3066 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3067 } 3068 3069 /* 3070 * Reclaim resources for a setup queue. 3071 */ 3072 static void 3073 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3074 { 3075 3076 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3077 ATH_TXQ_LOCK_DESTROY(txq); 3078 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3079 } 3080 3081 /* 3082 * Reclaim all tx queue resources. 3083 */ 3084 static void 3085 ath_tx_cleanup(struct ath_softc *sc) 3086 { 3087 int i; 3088 3089 ATH_TXBUF_LOCK_DESTROY(sc); 3090 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3091 if (ATH_TXQ_SETUP(sc, i)) 3092 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3093 } 3094 3095 /* 3096 * Defragment an mbuf chain, returning at most maxfrags separate 3097 * mbufs+clusters. If this is not possible NULL is returned and 3098 * the original mbuf chain is left in it's present (potentially 3099 * modified) state. We use two techniques: collapsing consecutive 3100 * mbufs and replacing consecutive mbufs by a cluster. 3101 */ 3102 static struct mbuf * 3103 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3104 { 3105 struct mbuf *m, *n, *n2, **prev; 3106 u_int curfrags; 3107 3108 /* 3109 * Calculate the current number of frags. 3110 */ 3111 curfrags = 0; 3112 for (m = m0; m != NULL; m = m->m_next) 3113 curfrags++; 3114 /* 3115 * First, try to collapse mbufs. Note that we always collapse 3116 * towards the front so we don't need to deal with moving the 3117 * pkthdr. This may be suboptimal if the first mbuf has much 3118 * less data than the following. 3119 */ 3120 m = m0; 3121 again: 3122 for (;;) { 3123 n = m->m_next; 3124 if (n == NULL) 3125 break; 3126 if ((m->m_flags & M_RDONLY) == 0 && 3127 n->m_len < M_TRAILINGSPACE(m)) { 3128 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3129 n->m_len); 3130 m->m_len += n->m_len; 3131 m->m_next = n->m_next; 3132 m_free(n); 3133 if (--curfrags <= maxfrags) 3134 return m0; 3135 } else 3136 m = n; 3137 } 3138 KASSERT(maxfrags > 1, 3139 ("maxfrags %u, but normal collapse failed", maxfrags)); 3140 /* 3141 * Collapse consecutive mbufs to a cluster. 3142 */ 3143 prev = &m0->m_next; /* NB: not the first mbuf */ 3144 while ((n = *prev) != NULL) { 3145 if ((n2 = n->m_next) != NULL && 3146 n->m_len + n2->m_len < MCLBYTES) { 3147 m = m_getcl(how, MT_DATA, 0); 3148 if (m == NULL) 3149 goto bad; 3150 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3151 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3152 n2->m_len); 3153 m->m_len = n->m_len + n2->m_len; 3154 m->m_next = n2->m_next; 3155 *prev = m; 3156 m_free(n); 3157 m_free(n2); 3158 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3159 return m0; 3160 /* 3161 * Still not there, try the normal collapse 3162 * again before we allocate another cluster. 3163 */ 3164 goto again; 3165 } 3166 prev = &n->m_next; 3167 } 3168 /* 3169 * No place where we can collapse to a cluster; punt. 3170 * This can occur if, for example, you request 2 frags 3171 * but the packet requires that both be clusters (we 3172 * never reallocate the first mbuf to avoid moving the 3173 * packet header). 3174 */ 3175 bad: 3176 return NULL; 3177 } 3178 3179 static int 3180 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3181 struct mbuf *m0) 3182 { 3183 #define CTS_DURATION \ 3184 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE) 3185 #define updateCTSForBursting(_ah, _ds, _txq) \ 3186 ath_hal_updateCTSForBursting(_ah, _ds, \ 3187 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ 3188 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ 3189 txopLimit, CTS_DURATION) 3190 struct ieee80211com *ic = &sc->sc_ic; 3191 struct ath_hal *ah = sc->sc_ah; 3192 struct ifnet *ifp = &sc->sc_if; 3193 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3194 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3195 u_int8_t rix, txrate, ctsrate; 3196 u_int8_t cix = 0xff; /* NB: silence compiler */ 3197 struct ath_desc *ds, *ds0; 3198 struct ath_txq *txq; 3199 struct ieee80211_frame *wh; 3200 u_int subtype, flags, ctsduration; 3201 HAL_PKT_TYPE atype; 3202 const HAL_RATE_TABLE *rt; 3203 HAL_BOOL shortPreamble; 3204 struct ath_node *an; 3205 struct mbuf *m; 3206 u_int pri; 3207 3208 wh = mtod(m0, struct ieee80211_frame *); 3209 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3210 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3211 hdrlen = ieee80211_anyhdrsize(wh); 3212 /* 3213 * Packet length must not include any 3214 * pad bytes; deduct them here. 3215 */ 3216 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3217 3218 if (iswep) { 3219 const struct ieee80211_cipher *cip; 3220 struct ieee80211_key *k; 3221 3222 /* 3223 * Construct the 802.11 header+trailer for an encrypted 3224 * frame. The only reason this can fail is because of an 3225 * unknown or unsupported cipher/key type. 3226 */ 3227 k = ieee80211_crypto_encap(ic, ni, m0); 3228 if (k == NULL) { 3229 /* 3230 * This can happen when the key is yanked after the 3231 * frame was queued. Just discard the frame; the 3232 * 802.11 layer counts failures and provides 3233 * debugging/diagnostics. 3234 */ 3235 m_freem(m0); 3236 return EIO; 3237 } 3238 /* 3239 * Adjust the packet + header lengths for the crypto 3240 * additions and calculate the h/w key index. When 3241 * a s/w mic is done the frame will have had any mic 3242 * added to it prior to entry so skb->len above will 3243 * account for it. Otherwise we need to add it to the 3244 * packet length. 3245 */ 3246 cip = k->wk_cipher; 3247 hdrlen += cip->ic_header; 3248 pktlen += cip->ic_header + cip->ic_trailer; 3249 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3250 pktlen += cip->ic_miclen; 3251 keyix = k->wk_keyix; 3252 3253 /* packet header may have moved, reset our local pointer */ 3254 wh = mtod(m0, struct ieee80211_frame *); 3255 } else 3256 keyix = HAL_TXKEYIX_INVALID; 3257 3258 pktlen += IEEE80211_CRC_LEN; 3259 3260 /* 3261 * Load the DMA map so any coalescing is done. This 3262 * also calculates the number of descriptors we need. 3263 */ 3264 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3265 BUS_DMA_NOWAIT); 3266 if (error == EFBIG) { 3267 /* XXX packet requires too many descriptors */ 3268 bf->bf_nseg = ATH_TXDESC+1; 3269 } else if (error != 0) { 3270 sc->sc_stats.ast_tx_busdma++; 3271 m_freem(m0); 3272 return error; 3273 } 3274 /* 3275 * Discard null packets and check for packets that 3276 * require too many TX descriptors. We try to convert 3277 * the latter to a cluster. 3278 */ 3279 if (error == EFBIG) { /* too many desc's, linearize */ 3280 sc->sc_stats.ast_tx_linear++; 3281 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3282 if (m == NULL) { 3283 m_freem(m0); 3284 sc->sc_stats.ast_tx_nombuf++; 3285 return ENOMEM; 3286 } 3287 m0 = m; 3288 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3289 BUS_DMA_NOWAIT); 3290 if (error != 0) { 3291 sc->sc_stats.ast_tx_busdma++; 3292 m_freem(m0); 3293 return error; 3294 } 3295 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3296 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3297 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3298 sc->sc_stats.ast_tx_nodata++; 3299 m_freem(m0); 3300 return EIO; 3301 } 3302 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3303 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3304 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3305 bf->bf_m = m0; 3306 bf->bf_node = ni; /* NB: held reference */ 3307 3308 /* setup descriptors */ 3309 ds = bf->bf_desc; 3310 rt = sc->sc_currates; 3311 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3312 3313 /* 3314 * NB: the 802.11 layer marks whether or not we should 3315 * use short preamble based on the current mode and 3316 * negotiated parameters. 3317 */ 3318 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3319 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3320 shortPreamble = AH_TRUE; 3321 sc->sc_stats.ast_tx_shortpre++; 3322 } else { 3323 shortPreamble = AH_FALSE; 3324 } 3325 3326 an = ATH_NODE(ni); 3327 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3328 /* 3329 * Calculate Atheros packet type from IEEE80211 packet header, 3330 * setup for rate calculations, and select h/w transmit queue. 3331 */ 3332 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3333 case IEEE80211_FC0_TYPE_MGT: 3334 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3335 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3336 atype = HAL_PKT_TYPE_BEACON; 3337 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3338 atype = HAL_PKT_TYPE_PROBE_RESP; 3339 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3340 atype = HAL_PKT_TYPE_ATIM; 3341 else 3342 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3343 rix = 0; /* XXX lowest rate */ 3344 try0 = ATH_TXMAXTRY; 3345 if (shortPreamble) 3346 txrate = an->an_tx_mgtratesp; 3347 else 3348 txrate = an->an_tx_mgtrate; 3349 /* NB: force all management frames to highest queue */ 3350 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3351 /* NB: force all management frames to highest queue */ 3352 pri = WME_AC_VO; 3353 } else 3354 pri = WME_AC_BE; 3355 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3356 break; 3357 case IEEE80211_FC0_TYPE_CTL: 3358 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3359 rix = 0; /* XXX lowest rate */ 3360 try0 = ATH_TXMAXTRY; 3361 if (shortPreamble) 3362 txrate = an->an_tx_mgtratesp; 3363 else 3364 txrate = an->an_tx_mgtrate; 3365 /* NB: force all ctl frames to highest queue */ 3366 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3367 /* NB: force all ctl frames to highest queue */ 3368 pri = WME_AC_VO; 3369 } else 3370 pri = WME_AC_BE; 3371 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3372 break; 3373 case IEEE80211_FC0_TYPE_DATA: 3374 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3375 /* 3376 * Data frames; consult the rate control module. 3377 */ 3378 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3379 &rix, &try0, &txrate); 3380 sc->sc_txrate = txrate; /* for LED blinking */ 3381 /* 3382 * Default all non-QoS traffic to the background queue. 3383 */ 3384 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3385 pri = M_WME_GETAC(m0); 3386 if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3387 flags |= HAL_TXDESC_NOACK; 3388 sc->sc_stats.ast_tx_noack++; 3389 } 3390 } else 3391 pri = WME_AC_BE; 3392 break; 3393 default: 3394 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3395 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3396 /* XXX statistic */ 3397 m_freem(m0); 3398 return EIO; 3399 } 3400 txq = sc->sc_ac2q[pri]; 3401 3402 /* 3403 * When servicing one or more stations in power-save mode 3404 * multicast frames must be buffered until after the beacon. 3405 * We use the CAB queue for that. 3406 */ 3407 if (ismcast && ic->ic_ps_sta) { 3408 txq = sc->sc_cabq; 3409 /* XXX? more bit in 802.11 frame header */ 3410 } 3411 3412 /* 3413 * Calculate miscellaneous flags. 3414 */ 3415 if (ismcast) { 3416 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3417 sc->sc_stats.ast_tx_noack++; 3418 } else if (pktlen > ic->ic_rtsthreshold) { 3419 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3420 cix = rt->info[rix].controlRate; 3421 sc->sc_stats.ast_tx_rts++; 3422 } 3423 3424 /* 3425 * If 802.11g protection is enabled, determine whether 3426 * to use RTS/CTS or just CTS. Note that this is only 3427 * done for OFDM unicast frames. 3428 */ 3429 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3430 rt->info[rix].phy == IEEE80211_T_OFDM && 3431 (flags & HAL_TXDESC_NOACK) == 0) { 3432 /* XXX fragments must use CCK rates w/ protection */ 3433 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3434 flags |= HAL_TXDESC_RTSENA; 3435 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3436 flags |= HAL_TXDESC_CTSENA; 3437 cix = rt->info[sc->sc_protrix].controlRate; 3438 sc->sc_stats.ast_tx_protect++; 3439 } 3440 3441 /* 3442 * Calculate duration. This logically belongs in the 802.11 3443 * layer but it lacks sufficient information to calculate it. 3444 */ 3445 if ((flags & HAL_TXDESC_NOACK) == 0 && 3446 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3447 u_int16_t dur; 3448 /* 3449 * XXX not right with fragmentation. 3450 */ 3451 if (shortPreamble) 3452 dur = rt->info[rix].spAckDuration; 3453 else 3454 dur = rt->info[rix].lpAckDuration; 3455 *(u_int16_t *)wh->i_dur = htole16(dur); 3456 } 3457 3458 /* 3459 * Calculate RTS/CTS rate and duration if needed. 3460 */ 3461 ctsduration = 0; 3462 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3463 /* 3464 * CTS transmit rate is derived from the transmit rate 3465 * by looking in the h/w rate table. We must also factor 3466 * in whether or not a short preamble is to be used. 3467 */ 3468 /* NB: cix is set above where RTS/CTS is enabled */ 3469 KASSERT(cix != 0xff, ("cix not setup")); 3470 ctsrate = rt->info[cix].rateCode; 3471 /* 3472 * Compute the transmit duration based on the frame 3473 * size and the size of an ACK frame. We call into the 3474 * HAL to do the computation since it depends on the 3475 * characteristics of the actual PHY being used. 3476 * 3477 * NB: CTS is assumed the same size as an ACK so we can 3478 * use the precalculated ACK durations. 3479 */ 3480 if (shortPreamble) { 3481 ctsrate |= rt->info[cix].shortPreamble; 3482 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3483 ctsduration += rt->info[cix].spAckDuration; 3484 ctsduration += ath_hal_computetxtime(ah, 3485 rt, pktlen, rix, AH_TRUE); 3486 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3487 ctsduration += rt->info[cix].spAckDuration; 3488 } else { 3489 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3490 ctsduration += rt->info[cix].lpAckDuration; 3491 ctsduration += ath_hal_computetxtime(ah, 3492 rt, pktlen, rix, AH_FALSE); 3493 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3494 ctsduration += rt->info[cix].lpAckDuration; 3495 } 3496 /* 3497 * Must disable multi-rate retry when using RTS/CTS. 3498 */ 3499 try0 = ATH_TXMAXTRY; 3500 } else 3501 ctsrate = 0; 3502 3503 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3504 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3505 sc->sc_hwmap[txrate].ieeerate, -1); 3506 3507 if (ic->ic_rawbpf) 3508 bpf_mtap(ic->ic_rawbpf, m0); 3509 if (sc->sc_drvbpf) { 3510 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3511 if (iswep) 3512 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3513 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3514 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3515 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3516 3517 bpf_mtap2(sc->sc_drvbpf, 3518 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3519 } 3520 3521 /* 3522 * Determine if a tx interrupt should be generated for 3523 * this descriptor. We take a tx interrupt to reap 3524 * descriptors when the h/w hits an EOL condition or 3525 * when the descriptor is specifically marked to generate 3526 * an interrupt. We periodically mark descriptors in this 3527 * way to insure timely replenishing of the supply needed 3528 * for sending frames. Defering interrupts reduces system 3529 * load and potentially allows more concurrent work to be 3530 * done but if done to aggressively can cause senders to 3531 * backup. 3532 * 3533 * NB: use >= to deal with sc_txintrperiod changing 3534 * dynamically through sysctl. 3535 */ 3536 if (flags & HAL_TXDESC_INTREQ) { 3537 txq->axq_intrcnt = 0; 3538 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3539 flags |= HAL_TXDESC_INTREQ; 3540 txq->axq_intrcnt = 0; 3541 } 3542 3543 /* 3544 * Formulate first tx descriptor with tx controls. 3545 */ 3546 /* XXX check return value? */ 3547 ath_hal_setuptxdesc(ah, ds 3548 , pktlen /* packet length */ 3549 , hdrlen /* header length */ 3550 , atype /* Atheros packet type */ 3551 , ni->ni_txpower /* txpower */ 3552 , txrate, try0 /* series 0 rate/tries */ 3553 , keyix /* key cache index */ 3554 , sc->sc_txantenna /* antenna mode */ 3555 , flags /* flags */ 3556 , ctsrate /* rts/cts rate */ 3557 , ctsduration /* rts/cts duration */ 3558 ); 3559 /* 3560 * Setup the multi-rate retry state only when we're 3561 * going to use it. This assumes ath_hal_setuptxdesc 3562 * initializes the descriptors (so we don't have to) 3563 * when the hardware supports multi-rate retry and 3564 * we don't use it. 3565 */ 3566 if (try0 != ATH_TXMAXTRY) 3567 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3568 3569 /* 3570 * Fillin the remainder of the descriptor info. 3571 */ 3572 ds0 = ds; 3573 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3574 ds->ds_data = bf->bf_segs[i].ds_addr; 3575 if (i == bf->bf_nseg - 1) 3576 ds->ds_link = 0; 3577 else 3578 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3579 ath_hal_filltxdesc(ah, ds 3580 , bf->bf_segs[i].ds_len /* segment length */ 3581 , i == 0 /* first segment */ 3582 , i == bf->bf_nseg - 1 /* last segment */ 3583 , ds0 /* first descriptor */ 3584 ); 3585 DPRINTF(sc, ATH_DEBUG_XMIT, 3586 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3587 __func__, i, ds->ds_link, ds->ds_data, 3588 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3589 } 3590 /* 3591 * Insert the frame on the outbound list and 3592 * pass it on to the hardware. 3593 */ 3594 ATH_TXQ_LOCK(txq); 3595 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 3596 u_int32_t txopLimit = IEEE80211_TXOP_TO_US( 3597 cap->cap_wmeParams[pri].wmep_txopLimit); 3598 /* 3599 * When bursting, potentially extend the CTS duration 3600 * of a previously queued frame to cover this frame 3601 * and not exceed the txopLimit. If that can be done 3602 * then disable RTS/CTS on this frame since it's now 3603 * covered (burst extension). Otherwise we must terminate 3604 * the burst before this frame goes out so as not to 3605 * violate the WME parameters. All this is complicated 3606 * as we need to update the state of packets on the 3607 * (live) hardware queue. The logic is buried in the hal 3608 * because it's highly chip-specific. 3609 */ 3610 if (txopLimit != 0) { 3611 sc->sc_stats.ast_tx_ctsburst++; 3612 if (updateCTSForBursting(ah, ds0, txq) == 0) { 3613 /* 3614 * This frame was not covered by RTS/CTS from 3615 * the previous frame in the burst; update the 3616 * descriptor pointers so this frame is now 3617 * treated as the last frame for extending a 3618 * burst. 3619 */ 3620 txq->axq_lastdsWithCTS = ds0; 3621 /* set gating Desc to final desc */ 3622 txq->axq_gatingds = 3623 (struct ath_desc *)txq->axq_link; 3624 } else 3625 sc->sc_stats.ast_tx_ctsext++; 3626 } 3627 } 3628 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3629 if (txq->axq_link == NULL) { 3630 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3631 DPRINTF(sc, ATH_DEBUG_XMIT, 3632 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3633 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3634 txq->axq_depth); 3635 } else { 3636 *txq->axq_link = bf->bf_daddr; 3637 DPRINTF(sc, ATH_DEBUG_XMIT, 3638 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3639 txq->axq_qnum, txq->axq_link, 3640 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3641 } 3642 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3643 /* 3644 * The CAB queue is started from the SWBA handler since 3645 * frames only go out on DTIM and to avoid possible races. 3646 */ 3647 if (txq != sc->sc_cabq) 3648 ath_hal_txstart(ah, txq->axq_qnum); 3649 ATH_TXQ_UNLOCK(txq); 3650 3651 return 0; 3652 #undef updateCTSForBursting 3653 #undef CTS_DURATION 3654 } 3655 3656 /* 3657 * Process completed xmit descriptors from the specified queue. 3658 */ 3659 static void 3660 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3661 { 3662 struct ath_hal *ah = sc->sc_ah; 3663 struct ieee80211com *ic = &sc->sc_ic; 3664 struct ath_buf *bf; 3665 struct ath_desc *ds, *ds0; 3666 struct ieee80211_node *ni; 3667 struct ath_node *an; 3668 int sr, lr, pri; 3669 HAL_STATUS status; 3670 3671 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3672 __func__, txq->axq_qnum, 3673 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3674 txq->axq_link); 3675 for (;;) { 3676 ATH_TXQ_LOCK(txq); 3677 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3678 bf = STAILQ_FIRST(&txq->axq_q); 3679 if (bf == NULL) { 3680 txq->axq_link = NULL; 3681 ATH_TXQ_UNLOCK(txq); 3682 break; 3683 } 3684 ds0 = &bf->bf_desc[0]; 3685 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3686 status = ath_hal_txprocdesc(ah, ds); 3687 #ifdef AR_DEBUG 3688 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3689 ath_printtxbuf(bf, status == HAL_OK); 3690 #endif 3691 if (status == HAL_EINPROGRESS) { 3692 ATH_TXQ_UNLOCK(txq); 3693 break; 3694 } 3695 if (ds0 == txq->axq_lastdsWithCTS) 3696 txq->axq_lastdsWithCTS = NULL; 3697 if (ds == txq->axq_gatingds) 3698 txq->axq_gatingds = NULL; 3699 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3700 ATH_TXQ_UNLOCK(txq); 3701 3702 ni = bf->bf_node; 3703 if (ni != NULL) { 3704 an = ATH_NODE(ni); 3705 if (ds->ds_txstat.ts_status == 0) { 3706 u_int8_t txant = ds->ds_txstat.ts_antenna; 3707 sc->sc_stats.ast_ant_tx[txant]++; 3708 sc->sc_ant_tx[txant]++; 3709 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3710 sc->sc_stats.ast_tx_altrate++; 3711 sc->sc_stats.ast_tx_rssi = 3712 ds->ds_txstat.ts_rssi; 3713 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3714 ds->ds_txstat.ts_rssi); 3715 pri = M_WME_GETAC(bf->bf_m); 3716 if (pri >= WME_AC_VO) 3717 ic->ic_wme.wme_hipri_traffic++; 3718 ni->ni_inact = ni->ni_inact_reload; 3719 } else { 3720 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3721 sc->sc_stats.ast_tx_xretries++; 3722 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3723 sc->sc_stats.ast_tx_fifoerr++; 3724 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3725 sc->sc_stats.ast_tx_filtered++; 3726 } 3727 sr = ds->ds_txstat.ts_shortretry; 3728 lr = ds->ds_txstat.ts_longretry; 3729 sc->sc_stats.ast_tx_shortretry += sr; 3730 sc->sc_stats.ast_tx_longretry += lr; 3731 /* 3732 * Hand the descriptor to the rate control algorithm. 3733 */ 3734 ath_rate_tx_complete(sc, an, ds, ds0); 3735 /* 3736 * Reclaim reference to node. 3737 * 3738 * NB: the node may be reclaimed here if, for example 3739 * this is a DEAUTH message that was sent and the 3740 * node was timed out due to inactivity. 3741 */ 3742 ieee80211_free_node(ni); 3743 } 3744 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3745 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3746 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3747 m_freem(bf->bf_m); 3748 bf->bf_m = NULL; 3749 bf->bf_node = NULL; 3750 3751 ATH_TXBUF_LOCK(sc); 3752 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3753 ATH_TXBUF_UNLOCK(sc); 3754 } 3755 } 3756 3757 /* 3758 * Deferred processing of transmit interrupt; special-cased 3759 * for a single hardware transmit queue (e.g. 5210 and 5211). 3760 */ 3761 static void 3762 ath_tx_proc_q0(void *arg, int npending) 3763 { 3764 struct ath_softc *sc = arg; 3765 struct ifnet *ifp = &sc->sc_if; 3766 3767 ath_tx_processq(sc, &sc->sc_txq[0]); 3768 ath_tx_processq(sc, sc->sc_cabq); 3769 ifp->if_flags &= ~IFF_OACTIVE; 3770 sc->sc_tx_timer = 0; 3771 3772 if (sc->sc_softled) 3773 ath_led_event(sc, ATH_LED_TX); 3774 3775 ath_start(ifp); 3776 } 3777 3778 /* 3779 * Deferred processing of transmit interrupt; special-cased 3780 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3781 */ 3782 static void 3783 ath_tx_proc_q0123(void *arg, int npending) 3784 { 3785 struct ath_softc *sc = arg; 3786 struct ifnet *ifp = &sc->sc_if; 3787 3788 /* 3789 * Process each active queue. 3790 */ 3791 ath_tx_processq(sc, &sc->sc_txq[0]); 3792 ath_tx_processq(sc, &sc->sc_txq[1]); 3793 ath_tx_processq(sc, &sc->sc_txq[2]); 3794 ath_tx_processq(sc, &sc->sc_txq[3]); 3795 ath_tx_processq(sc, sc->sc_cabq); 3796 3797 ifp->if_flags &= ~IFF_OACTIVE; 3798 sc->sc_tx_timer = 0; 3799 3800 if (sc->sc_softled) 3801 ath_led_event(sc, ATH_LED_TX); 3802 3803 ath_start(ifp); 3804 } 3805 3806 /* 3807 * Deferred processing of transmit interrupt. 3808 */ 3809 static void 3810 ath_tx_proc(void *arg, int npending) 3811 { 3812 struct ath_softc *sc = arg; 3813 struct ifnet *ifp = &sc->sc_if; 3814 int i; 3815 3816 /* 3817 * Process each active queue. 3818 */ 3819 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3820 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3821 if (ATH_TXQ_SETUP(sc, i)) 3822 ath_tx_processq(sc, &sc->sc_txq[i]); 3823 3824 ifp->if_flags &= ~IFF_OACTIVE; 3825 sc->sc_tx_timer = 0; 3826 3827 if (sc->sc_softled) 3828 ath_led_event(sc, ATH_LED_TX); 3829 3830 ath_start(ifp); 3831 } 3832 3833 static void 3834 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3835 { 3836 struct ath_hal *ah = sc->sc_ah; 3837 struct ieee80211_node *ni; 3838 struct ath_buf *bf; 3839 3840 /* 3841 * NB: this assumes output has been stopped and 3842 * we do not need to block ath_tx_tasklet 3843 */ 3844 for (;;) { 3845 ATH_TXQ_LOCK(txq); 3846 bf = STAILQ_FIRST(&txq->axq_q); 3847 if (bf == NULL) { 3848 txq->axq_link = NULL; 3849 ATH_TXQ_UNLOCK(txq); 3850 break; 3851 } 3852 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3853 ATH_TXQ_UNLOCK(txq); 3854 #ifdef AR_DEBUG 3855 if (sc->sc_debug & ATH_DEBUG_RESET) 3856 ath_printtxbuf(bf, 3857 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3858 #endif /* AR_DEBUG */ 3859 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3860 m_freem(bf->bf_m); 3861 bf->bf_m = NULL; 3862 ni = bf->bf_node; 3863 bf->bf_node = NULL; 3864 if (ni != NULL) { 3865 /* 3866 * Reclaim node reference. 3867 */ 3868 ieee80211_free_node(ni); 3869 } 3870 ATH_TXBUF_LOCK(sc); 3871 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3872 ATH_TXBUF_UNLOCK(sc); 3873 } 3874 } 3875 3876 static void 3877 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3878 { 3879 struct ath_hal *ah = sc->sc_ah; 3880 3881 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 3882 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3883 __func__, txq->axq_qnum, 3884 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 3885 txq->axq_link); 3886 } 3887 3888 /* 3889 * Drain the transmit queues and reclaim resources. 3890 */ 3891 static void 3892 ath_draintxq(struct ath_softc *sc) 3893 { 3894 struct ath_hal *ah = sc->sc_ah; 3895 struct ifnet *ifp = &sc->sc_if; 3896 int i; 3897 3898 /* XXX return value */ 3899 if (!sc->sc_invalid) { 3900 /* don't touch the hardware if marked invalid */ 3901 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 3902 DPRINTF(sc, ATH_DEBUG_RESET, 3903 "%s: beacon queue %p\n", __func__, 3904 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 3905 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3906 if (ATH_TXQ_SETUP(sc, i)) 3907 ath_tx_stopdma(sc, &sc->sc_txq[i]); 3908 } 3909 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3910 if (ATH_TXQ_SETUP(sc, i)) 3911 ath_tx_draintxq(sc, &sc->sc_txq[i]); 3912 ifp->if_flags &= ~IFF_OACTIVE; 3913 sc->sc_tx_timer = 0; 3914 } 3915 3916 /* 3917 * Disable the receive h/w in preparation for a reset. 3918 */ 3919 static void 3920 ath_stoprecv(struct ath_softc *sc) 3921 { 3922 #define PA2DESC(_sc, _pa) \ 3923 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3924 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3925 struct ath_hal *ah = sc->sc_ah; 3926 3927 ath_hal_stoppcurecv(ah); /* disable PCU */ 3928 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 3929 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 3930 DELAY(3000); /* 3ms is long enough for 1 frame */ 3931 #ifdef AR_DEBUG 3932 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 3933 struct ath_buf *bf; 3934 3935 printf("%s: rx queue %p, link %p\n", __func__, 3936 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 3937 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3938 struct ath_desc *ds = bf->bf_desc; 3939 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 3940 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3941 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 3942 ath_printrxbuf(bf, status == HAL_OK); 3943 } 3944 } 3945 #endif 3946 sc->sc_rxlink = NULL; /* just in case */ 3947 #undef PA2DESC 3948 } 3949 3950 /* 3951 * Enable the receive h/w following a reset. 3952 */ 3953 static int 3954 ath_startrecv(struct ath_softc *sc) 3955 { 3956 struct ath_hal *ah = sc->sc_ah; 3957 struct ath_buf *bf; 3958 3959 sc->sc_rxlink = NULL; 3960 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3961 int error = ath_rxbuf_init(sc, bf); 3962 if (error != 0) { 3963 DPRINTF(sc, ATH_DEBUG_RECV, 3964 "%s: ath_rxbuf_init failed %d\n", 3965 __func__, error); 3966 return error; 3967 } 3968 } 3969 3970 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3971 ath_hal_putrxbuf(ah, bf->bf_daddr); 3972 ath_hal_rxena(ah); /* enable recv descriptors */ 3973 ath_mode_init(sc); /* set filters, etc. */ 3974 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 3975 return 0; 3976 } 3977 3978 /* 3979 * Update internal state after a channel change. 3980 */ 3981 static void 3982 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 3983 { 3984 struct ieee80211com *ic = &sc->sc_ic; 3985 enum ieee80211_phymode mode; 3986 u_int16_t flags; 3987 3988 /* 3989 * Change channels and update the h/w rate map 3990 * if we're switching; e.g. 11a to 11b/g. 3991 */ 3992 mode = ieee80211_chan2mode(ic, chan); 3993 if (mode != sc->sc_curmode) 3994 ath_setcurmode(sc, mode); 3995 /* 3996 * Update BPF state. NB: ethereal et. al. don't handle 3997 * merged flags well so pick a unique mode for their use. 3998 */ 3999 if (IEEE80211_IS_CHAN_A(chan)) 4000 flags = IEEE80211_CHAN_A; 4001 /* XXX 11g schizophrenia */ 4002 else if (IEEE80211_IS_CHAN_G(chan) || 4003 IEEE80211_IS_CHAN_PUREG(chan)) 4004 flags = IEEE80211_CHAN_G; 4005 else 4006 flags = IEEE80211_CHAN_B; 4007 if (IEEE80211_IS_CHAN_T(chan)) 4008 flags |= IEEE80211_CHAN_TURBO; 4009 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4010 htole16(chan->ic_freq); 4011 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4012 htole16(flags); 4013 } 4014 4015 /* 4016 * Set/change channels. If the channel is really being changed, 4017 * it's done by reseting the chip. To accomplish this we must 4018 * first cleanup any pending DMA, then restart stuff after a la 4019 * ath_init. 4020 */ 4021 static int 4022 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4023 { 4024 struct ath_hal *ah = sc->sc_ah; 4025 struct ieee80211com *ic = &sc->sc_ic; 4026 HAL_CHANNEL hchan; 4027 4028 /* 4029 * Convert to a HAL channel description with 4030 * the flags constrained to reflect the current 4031 * operating mode. 4032 */ 4033 hchan.channel = chan->ic_freq; 4034 hchan.channelFlags = ath_chan2flags(ic, chan); 4035 4036 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 4037 __func__, 4038 ath_hal_mhz2ieee(sc->sc_curchan.channel, 4039 sc->sc_curchan.channelFlags), 4040 sc->sc_curchan.channel, 4041 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 4042 if (hchan.channel != sc->sc_curchan.channel || 4043 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4044 HAL_STATUS status; 4045 4046 /* 4047 * To switch channels clear any pending DMA operations; 4048 * wait long enough for the RX fifo to drain, reset the 4049 * hardware at the new frequency, and then re-enable 4050 * the relevant bits of the h/w. 4051 */ 4052 ath_hal_intrset(ah, 0); /* disable interrupts */ 4053 ath_draintxq(sc); /* clear pending tx frames */ 4054 ath_stoprecv(sc); /* turn off frame recv */ 4055 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4056 if_printf(&sc->sc_if, "ath_chan_set: unable to reset " 4057 "channel %u (%u Mhz)\n", 4058 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 4059 return EIO; 4060 } 4061 sc->sc_curchan = hchan; 4062 ath_update_txpow(sc); /* update tx power state */ 4063 4064 /* 4065 * Re-enable rx framework. 4066 */ 4067 if (ath_startrecv(sc) != 0) { 4068 if_printf(&sc->sc_if, 4069 "ath_chan_set: unable to restart recv logic\n"); 4070 return EIO; 4071 } 4072 4073 /* 4074 * Change channels and update the h/w rate map 4075 * if we're switching; e.g. 11a to 11b/g. 4076 */ 4077 ic->ic_ibss_chan = chan; 4078 ath_chan_change(sc, chan); 4079 4080 /* 4081 * Re-enable interrupts. 4082 */ 4083 ath_hal_intrset(ah, sc->sc_imask); 4084 } 4085 return 0; 4086 } 4087 4088 static void 4089 ath_next_scan(void *arg) 4090 { 4091 struct ath_softc *sc = arg; 4092 struct ieee80211com *ic = &sc->sc_ic; 4093 int s; 4094 4095 /* don't call ath_start w/o network interrupts blocked */ 4096 s = splnet(); 4097 4098 if (ic->ic_state == IEEE80211_S_SCAN) 4099 ieee80211_next_scan(ic); 4100 splx(s); 4101 } 4102 4103 /* 4104 * Periodically recalibrate the PHY to account 4105 * for temperature/environment changes. 4106 */ 4107 static void 4108 ath_calibrate(void *arg) 4109 { 4110 struct ath_softc *sc = arg; 4111 struct ath_hal *ah = sc->sc_ah; 4112 4113 sc->sc_stats.ast_per_cal++; 4114 4115 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 4116 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 4117 4118 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4119 /* 4120 * Rfgain is out of bounds, reset the chip 4121 * to load new gain values. 4122 */ 4123 sc->sc_stats.ast_per_rfgain++; 4124 ath_reset(&sc->sc_if); 4125 } 4126 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 4127 DPRINTF(sc, ATH_DEBUG_ANY, 4128 "%s: calibration of channel %u failed\n", 4129 __func__, sc->sc_curchan.channel); 4130 sc->sc_stats.ast_per_calfail++; 4131 } 4132 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 4133 } 4134 4135 static int 4136 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4137 { 4138 struct ifnet *ifp = ic->ic_ifp; 4139 struct ath_softc *sc = ifp->if_softc; 4140 struct ath_hal *ah = sc->sc_ah; 4141 struct ieee80211_node *ni; 4142 int i, error; 4143 const u_int8_t *bssid; 4144 u_int32_t rfilt; 4145 static const HAL_LED_STATE leds[] = { 4146 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4147 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4148 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4149 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4150 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4151 }; 4152 4153 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4154 ieee80211_state_name[ic->ic_state], 4155 ieee80211_state_name[nstate]); 4156 4157 callout_stop(&sc->sc_scan_ch); 4158 callout_stop(&sc->sc_cal_ch); 4159 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4160 4161 if (nstate == IEEE80211_S_INIT) { 4162 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4163 /* 4164 * NB: disable interrupts so we don't rx frames. 4165 */ 4166 ath_hal_intrset(ah, sc->sc_imask &~ ~HAL_INT_GLOBAL); 4167 /* 4168 * Notify the rate control algorithm. 4169 */ 4170 ath_rate_newstate(sc, nstate); 4171 goto done; 4172 } 4173 ni = ic->ic_bss; 4174 error = ath_chan_set(sc, ni->ni_chan); 4175 if (error != 0) 4176 goto bad; 4177 rfilt = ath_calcrxfilter(sc, nstate); 4178 if (nstate == IEEE80211_S_SCAN) 4179 bssid = ifp->if_broadcastaddr; 4180 else 4181 bssid = ni->ni_bssid; 4182 ath_hal_setrxfilter(ah, rfilt); 4183 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4184 __func__, rfilt, ether_sprintf(bssid)); 4185 4186 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4187 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4188 else 4189 ath_hal_setassocid(ah, bssid, 0); 4190 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4191 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4192 if (ath_hal_keyisvalid(ah, i)) 4193 ath_hal_keysetmac(ah, i, bssid); 4194 } 4195 4196 /* 4197 * Notify the rate control algorithm so rates 4198 * are setup should ath_beacon_alloc be called. 4199 */ 4200 ath_rate_newstate(sc, nstate); 4201 4202 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4203 /* nothing to do */; 4204 } else if (nstate == IEEE80211_S_RUN) { 4205 DPRINTF(sc, ATH_DEBUG_STATE, 4206 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4207 "capinfo=0x%04x chan=%d\n" 4208 , __func__ 4209 , ic->ic_flags 4210 , ni->ni_intval 4211 , ether_sprintf(ni->ni_bssid) 4212 , ni->ni_capinfo 4213 , ieee80211_chan2ieee(ic, ni->ni_chan)); 4214 4215 /* 4216 * Allocate and setup the beacon frame for AP or adhoc mode. 4217 */ 4218 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 4219 ic->ic_opmode == IEEE80211_M_IBSS) { 4220 /* 4221 * Stop any previous beacon DMA. This may be 4222 * necessary, for example, when an ibss merge 4223 * causes reconfiguration; there will be a state 4224 * transition from RUN->RUN that means we may 4225 * be called with beacon transmission active. 4226 */ 4227 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4228 ath_beacon_free(sc); 4229 error = ath_beacon_alloc(sc, ni); 4230 if (error != 0) 4231 goto bad; 4232 } 4233 4234 /* 4235 * Configure the beacon and sleep timers. 4236 */ 4237 ath_beacon_config(sc); 4238 } else { 4239 ath_hal_intrset(ah, 4240 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4241 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4242 } 4243 done: 4244 /* 4245 * Invoke the parent method to complete the work. 4246 */ 4247 error = sc->sc_newstate(ic, nstate, arg); 4248 /* 4249 * Finally, start any timers. 4250 */ 4251 if (nstate == IEEE80211_S_RUN) { 4252 /* start periodic recalibration timer */ 4253 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4254 ath_calibrate, sc); 4255 } else if (nstate == IEEE80211_S_SCAN) { 4256 /* start ap/neighbor scan timer */ 4257 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4258 ath_next_scan, sc); 4259 } 4260 bad: 4261 return error; 4262 } 4263 4264 /* 4265 * Setup driver-specific state for a newly associated node. 4266 * Note that we're called also on a re-associate, the isnew 4267 * param tells us if this is the first time or not. 4268 */ 4269 static void 4270 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 4271 { 4272 struct ath_softc *sc = ic->ic_ifp->if_softc; 4273 4274 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4275 } 4276 4277 static int 4278 ath_getchannels(struct ath_softc *sc, u_int cc, 4279 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4280 { 4281 struct ieee80211com *ic = &sc->sc_ic; 4282 struct ifnet *ifp = &sc->sc_if; 4283 struct ath_hal *ah = sc->sc_ah; 4284 HAL_CHANNEL *chans; 4285 int i, ix, nchan; 4286 4287 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4288 M_TEMP, M_NOWAIT); 4289 if (chans == NULL) { 4290 if_printf(ifp, "unable to allocate channel table\n"); 4291 return ENOMEM; 4292 } 4293 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4294 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4295 u_int32_t rd; 4296 4297 ath_hal_getregdomain(ah, &rd); 4298 if_printf(ifp, "unable to collect channel list from hal; " 4299 "regdomain likely %u country code %u\n", rd, cc); 4300 free(chans, M_TEMP); 4301 return EINVAL; 4302 } 4303 4304 /* 4305 * Convert HAL channels to ieee80211 ones and insert 4306 * them in the table according to their channel number. 4307 */ 4308 for (i = 0; i < nchan; i++) { 4309 HAL_CHANNEL *c = &chans[i]; 4310 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4311 if (ix > IEEE80211_CHAN_MAX) { 4312 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4313 ix, c->channel, c->channelFlags); 4314 continue; 4315 } 4316 DPRINTF(sc, ATH_DEBUG_ANY, 4317 "%s: HAL channel %d/%d freq %d flags %#04x idx %d\n", 4318 sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags, 4319 ix); 4320 /* NB: flags are known to be compatible */ 4321 if (ic->ic_channels[ix].ic_freq == 0) { 4322 ic->ic_channels[ix].ic_freq = c->channel; 4323 ic->ic_channels[ix].ic_flags = c->channelFlags; 4324 } else { 4325 /* channels overlap; e.g. 11g and 11b */ 4326 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4327 } 4328 } 4329 free(chans, M_TEMP); 4330 return 0; 4331 } 4332 4333 static void 4334 ath_led_done(void *arg) 4335 { 4336 struct ath_softc *sc = arg; 4337 4338 sc->sc_blinking = 0; 4339 } 4340 4341 /* 4342 * Turn the LED off: flip the pin and then set a timer so no 4343 * update will happen for the specified duration. 4344 */ 4345 static void 4346 ath_led_off(void *arg) 4347 { 4348 struct ath_softc *sc = arg; 4349 4350 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4351 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4352 } 4353 4354 /* 4355 * Blink the LED according to the specified on/off times. 4356 */ 4357 static void 4358 ath_led_blink(struct ath_softc *sc, int on, int off) 4359 { 4360 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4361 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4362 sc->sc_blinking = 1; 4363 sc->sc_ledoff = off; 4364 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4365 } 4366 4367 static void 4368 ath_led_event(struct ath_softc *sc, int event) 4369 { 4370 4371 sc->sc_ledevent = ticks; /* time of last event */ 4372 if (sc->sc_blinking) /* don't interrupt active blink */ 4373 return; 4374 switch (event) { 4375 case ATH_LED_POLL: 4376 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4377 sc->sc_hwmap[0].ledoff); 4378 break; 4379 case ATH_LED_TX: 4380 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4381 sc->sc_hwmap[sc->sc_txrate].ledoff); 4382 break; 4383 case ATH_LED_RX: 4384 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4385 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4386 break; 4387 } 4388 } 4389 4390 static void 4391 ath_update_txpow(struct ath_softc *sc) 4392 { 4393 struct ieee80211com *ic = &sc->sc_ic; 4394 struct ath_hal *ah = sc->sc_ah; 4395 u_int32_t txpow; 4396 4397 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4398 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4399 /* read back in case value is clamped */ 4400 ath_hal_gettxpowlimit(ah, &txpow); 4401 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4402 } 4403 /* 4404 * Fetch max tx power level for status requests. 4405 */ 4406 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4407 ic->ic_bss->ni_txpower = txpow; 4408 } 4409 4410 static int 4411 ath_rate_setup(struct ath_softc *sc, u_int mode) 4412 { 4413 struct ath_hal *ah = sc->sc_ah; 4414 struct ieee80211com *ic = &sc->sc_ic; 4415 const HAL_RATE_TABLE *rt; 4416 struct ieee80211_rateset *rs; 4417 int i, maxrates; 4418 4419 switch (mode) { 4420 case IEEE80211_MODE_11A: 4421 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4422 break; 4423 case IEEE80211_MODE_11B: 4424 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4425 break; 4426 case IEEE80211_MODE_11G: 4427 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4428 break; 4429 case IEEE80211_MODE_TURBO_A: 4430 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4431 break; 4432 case IEEE80211_MODE_TURBO_G: 4433 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4434 break; 4435 default: 4436 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4437 __func__, mode); 4438 return 0; 4439 } 4440 rt = sc->sc_rates[mode]; 4441 if (rt == NULL) 4442 return 0; 4443 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4444 DPRINTF(sc, ATH_DEBUG_ANY, 4445 "%s: rate table too small (%u > %u)\n", 4446 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4447 maxrates = IEEE80211_RATE_MAXSIZE; 4448 } else 4449 maxrates = rt->rateCount; 4450 rs = &ic->ic_sup_rates[mode]; 4451 for (i = 0; i < maxrates; i++) 4452 rs->rs_rates[i] = rt->info[i].dot11Rate; 4453 rs->rs_nrates = maxrates; 4454 return 1; 4455 } 4456 4457 static void 4458 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4459 { 4460 #define N(a) (sizeof(a)/sizeof(a[0])) 4461 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4462 static const struct { 4463 u_int rate; /* tx/rx 802.11 rate */ 4464 u_int16_t timeOn; /* LED on time (ms) */ 4465 u_int16_t timeOff; /* LED off time (ms) */ 4466 } blinkrates[] = { 4467 { 108, 40, 10 }, 4468 { 96, 44, 11 }, 4469 { 72, 50, 13 }, 4470 { 48, 57, 14 }, 4471 { 36, 67, 16 }, 4472 { 24, 80, 20 }, 4473 { 22, 100, 25 }, 4474 { 18, 133, 34 }, 4475 { 12, 160, 40 }, 4476 { 10, 200, 50 }, 4477 { 6, 240, 58 }, 4478 { 4, 267, 66 }, 4479 { 2, 400, 100 }, 4480 { 0, 500, 130 }, 4481 }; 4482 const HAL_RATE_TABLE *rt; 4483 int i, j; 4484 4485 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4486 rt = sc->sc_rates[mode]; 4487 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4488 for (i = 0; i < rt->rateCount; i++) 4489 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4490 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4491 for (i = 0; i < 32; i++) { 4492 u_int8_t ix = rt->rateCodeToIndex[i]; 4493 if (ix == 0xff) { 4494 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4495 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4496 continue; 4497 } 4498 sc->sc_hwmap[i].ieeerate = 4499 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4500 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4501 if (rt->info[ix].shortPreamble || 4502 rt->info[ix].phy == IEEE80211_T_OFDM) 4503 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4504 /* NB: receive frames include FCS */ 4505 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4506 IEEE80211_RADIOTAP_F_FCS; 4507 /* setup blink rate table to avoid per-packet lookup */ 4508 for (j = 0; j < N(blinkrates)-1; j++) 4509 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4510 break; 4511 /* NB: this uses the last entry if the rate isn't found */ 4512 /* XXX beware of overlow */ 4513 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4514 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4515 } 4516 sc->sc_currates = rt; 4517 sc->sc_curmode = mode; 4518 /* 4519 * All protection frames are transmited at 2Mb/s for 4520 * 11g, otherwise at 1Mb/s. 4521 * XXX select protection rate index from rate table. 4522 */ 4523 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4524 /* NB: caller is responsible for reseting rate control state */ 4525 #undef N 4526 } 4527 4528 #ifdef AR_DEBUG 4529 static void 4530 ath_printrxbuf(struct ath_buf *bf, int done) 4531 { 4532 struct ath_desc *ds; 4533 int i; 4534 4535 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4536 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4537 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4538 ds->ds_link, ds->ds_data, 4539 ds->ds_ctl0, ds->ds_ctl1, 4540 ds->ds_hw[0], ds->ds_hw[1], 4541 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4542 } 4543 } 4544 4545 static void 4546 ath_printtxbuf(struct ath_buf *bf, int done) 4547 { 4548 struct ath_desc *ds; 4549 int i; 4550 4551 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4552 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4553 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4554 ds->ds_link, ds->ds_data, 4555 ds->ds_ctl0, ds->ds_ctl1, 4556 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4557 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4558 } 4559 } 4560 #endif /* AR_DEBUG */ 4561 4562 static void 4563 ath_watchdog(struct ifnet *ifp) 4564 { 4565 struct ath_softc *sc = ifp->if_softc; 4566 struct ieee80211com *ic = &sc->sc_ic; 4567 4568 ifp->if_timer = 0; 4569 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4570 return; 4571 if (sc->sc_tx_timer) { 4572 if (--sc->sc_tx_timer == 0) { 4573 if_printf(ifp, "device timeout\n"); 4574 ath_reset(ifp); 4575 ifp->if_oerrors++; 4576 sc->sc_stats.ast_watchdog++; 4577 } else 4578 ifp->if_timer = 1; 4579 } 4580 ieee80211_watchdog(ic); 4581 } 4582 4583 /* 4584 * Diagnostic interface to the HAL. This is used by various 4585 * tools to do things like retrieve register contents for 4586 * debugging. The mechanism is intentionally opaque so that 4587 * it can change frequently w/o concern for compatiblity. 4588 */ 4589 static int 4590 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4591 { 4592 struct ath_hal *ah = sc->sc_ah; 4593 u_int id = ad->ad_id & ATH_DIAG_ID; 4594 void *indata = NULL; 4595 void *outdata = NULL; 4596 u_int32_t insize = ad->ad_in_size; 4597 u_int32_t outsize = ad->ad_out_size; 4598 int error = 0; 4599 4600 if (ad->ad_id & ATH_DIAG_IN) { 4601 /* 4602 * Copy in data. 4603 */ 4604 indata = malloc(insize, M_TEMP, M_NOWAIT); 4605 if (indata == NULL) { 4606 error = ENOMEM; 4607 goto bad; 4608 } 4609 error = copyin(ad->ad_in_data, indata, insize); 4610 if (error) 4611 goto bad; 4612 } 4613 if (ad->ad_id & ATH_DIAG_DYN) { 4614 /* 4615 * Allocate a buffer for the results (otherwise the HAL 4616 * returns a pointer to a buffer where we can read the 4617 * results). Note that we depend on the HAL leaving this 4618 * pointer for us to use below in reclaiming the buffer; 4619 * may want to be more defensive. 4620 */ 4621 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4622 if (outdata == NULL) { 4623 error = ENOMEM; 4624 goto bad; 4625 } 4626 } 4627 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4628 if (outsize < ad->ad_out_size) 4629 ad->ad_out_size = outsize; 4630 if (outdata != NULL) 4631 error = copyout(outdata, ad->ad_out_data, 4632 ad->ad_out_size); 4633 } else { 4634 error = EINVAL; 4635 } 4636 bad: 4637 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4638 free(indata, M_TEMP); 4639 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4640 free(outdata, M_TEMP); 4641 return error; 4642 } 4643 4644 static int 4645 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4646 { 4647 #define IS_RUNNING(ifp) \ 4648 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 4649 struct ath_softc *sc = ifp->if_softc; 4650 struct ieee80211com *ic = &sc->sc_ic; 4651 struct ifreq *ifr = (struct ifreq *)data; 4652 int error = 0; 4653 4654 ATH_LOCK(sc); 4655 switch (cmd) { 4656 case SIOCSIFFLAGS: 4657 if (IS_RUNNING(ifp)) { 4658 /* 4659 * To avoid rescanning another access point, 4660 * do not call ath_init() here. Instead, 4661 * only reflect promisc mode settings. 4662 */ 4663 ath_mode_init(sc); 4664 } else if (ifp->if_flags & IFF_UP) { 4665 /* 4666 * Beware of being called during attach/detach 4667 * to reset promiscuous mode. In that case we 4668 * will still be marked UP but not RUNNING. 4669 * However trying to re-init the interface 4670 * is the wrong thing to do as we've already 4671 * torn down much of our state. There's 4672 * probably a better way to deal with this. 4673 */ 4674 if (!sc->sc_invalid && ic->ic_bss != NULL) 4675 ath_init(ifp); /* XXX lose error */ 4676 } else 4677 ath_stop_locked(ifp, 1); 4678 break; 4679 case SIOCADDMULTI: 4680 case SIOCDELMULTI: 4681 error = (cmd == SIOCADDMULTI) ? 4682 ether_addmulti(ifr, &sc->sc_ec) : 4683 ether_delmulti(ifr, &sc->sc_ec); 4684 if (error == ENETRESET) { 4685 if (ifp->if_flags & IFF_RUNNING) 4686 ath_mode_init(sc); 4687 error = 0; 4688 } 4689 break; 4690 case SIOCGATHSTATS: 4691 /* NB: embed these numbers to get a consistent view */ 4692 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4693 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4694 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4695 ATH_UNLOCK(sc); 4696 /* 4697 * NB: Drop the softc lock in case of a page fault; 4698 * we'll accept any potential inconsisentcy in the 4699 * statistics. The alternative is to copy the data 4700 * to a local structure. 4701 */ 4702 return copyout(&sc->sc_stats, 4703 ifr->ifr_data, sizeof (sc->sc_stats)); 4704 case SIOCGATHDIAG: 4705 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4706 break; 4707 default: 4708 error = ieee80211_ioctl(ic, cmd, data); 4709 if (error == ENETRESET) { 4710 if (IS_RUNNING(ifp) && 4711 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4712 ath_init(ifp); /* XXX lose error */ 4713 error = 0; 4714 } 4715 if (error == ERESTART) 4716 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4717 break; 4718 } 4719 ATH_UNLOCK(sc); 4720 return error; 4721 #undef IS_RUNNING 4722 } 4723 4724 static void 4725 ath_bpfattach(struct ath_softc *sc) 4726 { 4727 struct ifnet *ifp = &sc->sc_if; 4728 4729 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4730 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4731 &sc->sc_drvbpf); 4732 /* 4733 * Initialize constant fields. 4734 * XXX make header lengths a multiple of 32-bits so subsequent 4735 * headers are properly aligned; this is a kludge to keep 4736 * certain applications happy. 4737 * 4738 * NB: the channel is setup each time we transition to the 4739 * RUN state to avoid filling it in for each frame. 4740 */ 4741 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4742 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4743 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4744 4745 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4746 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4747 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4748 } 4749 4750 /* 4751 * Announce various information on device/driver attach. 4752 */ 4753 static void 4754 ath_announce(struct ath_softc *sc) 4755 { 4756 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4757 struct ifnet *ifp = &sc->sc_if; 4758 struct ath_hal *ah = sc->sc_ah; 4759 u_int modes, cc; 4760 4761 if_printf(ifp, "mac %d.%d phy %d.%d", 4762 ah->ah_macVersion, ah->ah_macRev, 4763 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4764 /* 4765 * Print radio revision(s). We check the wireless modes 4766 * to avoid falsely printing revs for inoperable parts. 4767 * Dual-band radio revs are returned in the 5Ghz rev number. 4768 */ 4769 ath_hal_getcountrycode(ah, &cc); 4770 modes = ath_hal_getwirelessmodes(ah, cc); 4771 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4772 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4773 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4774 ah->ah_analog5GhzRev >> 4, 4775 ah->ah_analog5GhzRev & 0xf, 4776 ah->ah_analog2GhzRev >> 4, 4777 ah->ah_analog2GhzRev & 0xf); 4778 else 4779 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4780 ah->ah_analog5GhzRev & 0xf); 4781 } else 4782 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4783 ah->ah_analog5GhzRev & 0xf); 4784 printf("\n"); 4785 if (bootverbose) { 4786 int i; 4787 for (i = 0; i <= WME_AC_VO; i++) { 4788 struct ath_txq *txq = sc->sc_ac2q[i]; 4789 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4790 txq->axq_qnum, ieee80211_wme_acnames[i]); 4791 } 4792 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4793 sc->sc_cabq->axq_qnum); 4794 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4795 } 4796 #undef HAL_MODE_DUALBAND 4797 } 4798
Indexes created Thu Oct 02 07:10:07 GMT 2025