ath.c revision 1.62
1 /* $NetBSD: ath.c,v 1.62 2005/11/23 01:04:37 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.62 2005/11/23 01:04:37 dyoung Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <machine/bus.h> 74 #include <sys/endian.h> 75 76 #include <machine/bus.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/if_ether.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_netbsd.h> 87 #include <net80211/ieee80211_var.h> 88 89 #if NBPFILTER > 0 90 #include <net/bpf.h> 91 #endif 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #endif 96 97 #include <sys/device.h> 98 #include <dev/ic/ath_netbsd.h> 99 100 #define AR_DEBUG 101 #include <dev/ic/athvar.h> 102 #include <contrib/dev/ic/athhal_desc.h> 103 #include <contrib/dev/ic/athhal_devid.h> /* XXX for softled */ 104 105 /* unaligned little endian access */ 106 #define LE_READ_2(p) \ 107 ((u_int16_t) \ 108 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 109 #define LE_READ_4(p) \ 110 ((u_int32_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 112 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 113 114 enum { 115 ATH_LED_TX, 116 ATH_LED_RX, 117 ATH_LED_POLL, 118 }; 119 120 static int ath_ifinit(struct ifnet *); 121 static int ath_init(struct ath_softc *); 122 static void ath_stop_locked(struct ifnet *, int); 123 static void ath_stop(struct ifnet *, int); 124 static void ath_start(struct ifnet *); 125 static int ath_media_change(struct ifnet *); 126 static void ath_watchdog(struct ifnet *); 127 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 128 static void ath_fatal_proc(void *, int); 129 static void ath_rxorn_proc(void *, int); 130 static void ath_bmiss_proc(void *, int); 131 static int ath_key_alloc(struct ieee80211com *, 132 const struct ieee80211_key *, 133 ieee80211_keyix *, ieee80211_keyix *); 134 static int ath_key_delete(struct ieee80211com *, 135 const struct ieee80211_key *); 136 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 137 const u_int8_t mac[IEEE80211_ADDR_LEN]); 138 static void ath_key_update_begin(struct ieee80211com *); 139 static void ath_key_update_end(struct ieee80211com *); 140 static void ath_mode_init(struct ath_softc *); 141 static void ath_setslottime(struct ath_softc *); 142 static void ath_updateslot(struct ifnet *); 143 static int ath_beaconq_setup(struct ath_hal *); 144 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 145 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 146 static void ath_beacon_proc(void *, int); 147 static void ath_bstuck_proc(void *, int); 148 static void ath_beacon_free(struct ath_softc *); 149 static void ath_beacon_config(struct ath_softc *); 150 static void ath_descdma_cleanup(struct ath_softc *sc, 151 struct ath_descdma *, ath_bufhead *); 152 static int ath_desc_alloc(struct ath_softc *); 153 static void ath_desc_free(struct ath_softc *); 154 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 155 static void ath_node_free(struct ieee80211_node *); 156 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 157 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 158 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 159 struct ieee80211_node *ni, 160 int subtype, int rssi, u_int32_t rstamp); 161 static void ath_setdefantenna(struct ath_softc *, u_int); 162 static void ath_rx_proc(void *, int); 163 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 164 static int ath_tx_setup(struct ath_softc *, int, int); 165 static int ath_wme_update(struct ieee80211com *); 166 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 167 static void ath_tx_cleanup(struct ath_softc *); 168 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 169 struct ath_buf *, struct mbuf *); 170 static void ath_tx_proc_q0(void *, int); 171 static void ath_tx_proc_q0123(void *, int); 172 static void ath_tx_proc(void *, int); 173 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 174 static void ath_draintxq(struct ath_softc *); 175 static void ath_stoprecv(struct ath_softc *); 176 static int ath_startrecv(struct ath_softc *); 177 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 178 static void ath_next_scan(void *); 179 static void ath_calibrate(void *); 180 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 181 static void ath_setup_stationkey(struct ieee80211_node *); 182 static void ath_newassoc(struct ieee80211_node *, int); 183 static int ath_getchannels(struct ath_softc *, u_int cc, 184 HAL_BOOL outdoor, HAL_BOOL xchanmode); 185 static void ath_led_event(struct ath_softc *, int); 186 static void ath_update_txpow(struct ath_softc *); 187 188 static int ath_rate_setup(struct ath_softc *, u_int mode); 189 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 190 191 #ifdef __NetBSD__ 192 int ath_enable(struct ath_softc *); 193 void ath_disable(struct ath_softc *); 194 void ath_power(int, void *); 195 #endif 196 197 static void ath_bpfattach(struct ath_softc *); 198 static void ath_announce(struct ath_softc *); 199 200 int ath_dwelltime = 200; /* 5 channels/second */ 201 int ath_calinterval = 30; /* calibrate every 30 secs */ 202 int ath_outdoor = AH_TRUE; /* outdoor operation */ 203 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 204 int ath_countrycode = CTRY_DEFAULT; /* country code */ 205 int ath_regdomain = 0; /* regulatory domain */ 206 int ath_debug = 0; 207 208 #ifdef AR_DEBUG 209 enum { 210 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 211 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 212 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 213 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 214 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 215 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 216 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 217 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 218 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 219 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 220 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 221 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 222 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 223 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 224 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 225 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 226 ATH_DEBUG_NODE = 0x00080000, /* node management */ 227 ATH_DEBUG_LED = 0x00100000, /* led management */ 228 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 229 ATH_DEBUG_ANY = 0xffffffff 230 }; 231 #define IFF_DUMPPKTS(sc, m) \ 232 ((sc->sc_debug & (m)) || \ 233 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 234 #define DPRINTF(sc, m, fmt, ...) do { \ 235 if (sc->sc_debug & (m)) \ 236 printf(fmt, __VA_ARGS__); \ 237 } while (0) 238 #define KEYPRINTF(sc, ix, hk, mac) do { \ 239 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 240 ath_keyprint(__func__, ix, hk, mac); \ 241 } while (0) 242 static void ath_printrxbuf(struct ath_buf *bf, int); 243 static void ath_printtxbuf(struct ath_buf *bf, int); 244 #else 245 #define IFF_DUMPPKTS(sc, m) \ 246 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 247 #define DPRINTF(m, fmt, ...) 248 #define KEYPRINTF(sc, k, ix, mac) 249 #endif 250 251 #ifdef __NetBSD__ 252 int 253 ath_activate(struct device *self, enum devact act) 254 { 255 struct ath_softc *sc = (struct ath_softc *)self; 256 int rv = 0, s; 257 258 s = splnet(); 259 switch (act) { 260 case DVACT_ACTIVATE: 261 rv = EOPNOTSUPP; 262 break; 263 case DVACT_DEACTIVATE: 264 if_deactivate(&sc->sc_if); 265 break; 266 } 267 splx(s); 268 return rv; 269 } 270 271 int 272 ath_enable(struct ath_softc *sc) 273 { 274 if (ATH_IS_ENABLED(sc) == 0) { 275 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 276 printf("%s: device enable failed\n", 277 sc->sc_dev.dv_xname); 278 return (EIO); 279 } 280 sc->sc_flags |= ATH_ENABLED; 281 } 282 return (0); 283 } 284 285 void 286 ath_disable(struct ath_softc *sc) 287 { 288 if (!ATH_IS_ENABLED(sc)) 289 return; 290 if (sc->sc_disable != NULL) 291 (*sc->sc_disable)(sc); 292 sc->sc_flags &= ~ATH_ENABLED; 293 } 294 #endif /* __NetBSD__ */ 295 296 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 297 298 int 299 ath_attach(u_int16_t devid, struct ath_softc *sc) 300 { 301 struct ifnet *ifp = &sc->sc_if; 302 struct ieee80211com *ic = &sc->sc_ic; 303 struct ath_hal *ah = NULL; 304 HAL_STATUS status; 305 int error = 0, i; 306 307 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 308 309 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 310 311 ah = ath_hal_attach(devid, sc, sc->sc_st, ATH_BUSHANDLE2HAL(sc->sc_sh), 312 &status); 313 if (ah == NULL) { 314 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 315 status); 316 error = ENXIO; 317 goto bad; 318 } 319 if (ah->ah_abi != HAL_ABI_VERSION) { 320 if_printf(ifp, "HAL ABI mismatch detected " 321 "(HAL:0x%x != driver:0x%x)\n", 322 ah->ah_abi, HAL_ABI_VERSION); 323 error = ENXIO; 324 goto bad; 325 } 326 sc->sc_ah = ah; 327 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 328 329 /* 330 * Check if the MAC has multi-rate retry support. 331 * We do this by trying to setup a fake extended 332 * descriptor. MAC's that don't have support will 333 * return false w/o doing anything. MAC's that do 334 * support it will return true w/o doing anything. 335 */ 336 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 337 338 /* 339 * Check if the device has hardware counters for PHY 340 * errors. If so we need to enable the MIB interrupt 341 * so we can act on stat triggers. 342 */ 343 if (ath_hal_hwphycounters(ah)) 344 sc->sc_needmib = 1; 345 346 /* 347 * Get the hardware key cache size. 348 */ 349 sc->sc_keymax = ath_hal_keycachesize(ah); 350 if (sc->sc_keymax > ATH_KEYMAX) { 351 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 352 ATH_KEYMAX, sc->sc_keymax); 353 sc->sc_keymax = ATH_KEYMAX; 354 } 355 /* 356 * Reset the key cache since some parts do not 357 * reset the contents on initial power up. 358 */ 359 for (i = 0; i < sc->sc_keymax; i++) 360 ath_hal_keyreset(ah, i); 361 /* 362 * Mark key cache slots associated with global keys 363 * as in use. If we knew TKIP was not to be used we 364 * could leave the +32, +64, and +32+64 slots free. 365 * XXX only for splitmic. 366 */ 367 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 368 setbit(sc->sc_keymap, i); 369 setbit(sc->sc_keymap, i+32); 370 setbit(sc->sc_keymap, i+64); 371 setbit(sc->sc_keymap, i+32+64); 372 } 373 374 /* 375 * Collect the channel list using the default country 376 * code and including outdoor channels. The 802.11 layer 377 * is resposible for filtering this list based on settings 378 * like the phy mode. 379 */ 380 error = ath_getchannels(sc, ath_countrycode, 381 ath_outdoor, ath_xchanmode); 382 if (error != 0) 383 goto bad; 384 385 /* 386 * Setup rate tables for all potential media types. 387 */ 388 ath_rate_setup(sc, IEEE80211_MODE_11A); 389 ath_rate_setup(sc, IEEE80211_MODE_11B); 390 ath_rate_setup(sc, IEEE80211_MODE_11G); 391 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 392 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 393 /* NB: setup here so ath_rate_update is happy */ 394 ath_setcurmode(sc, IEEE80211_MODE_11A); 395 396 /* 397 * Allocate tx+rx descriptors and populate the lists. 398 */ 399 error = ath_desc_alloc(sc); 400 if (error != 0) { 401 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 402 goto bad; 403 } 404 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 405 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 406 407 ATH_TXBUF_LOCK_INIT(sc); 408 409 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 410 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 411 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 412 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 413 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 414 415 /* 416 * Allocate hardware transmit queues: one queue for 417 * beacon frames and one data queue for each QoS 418 * priority. Note that the hal handles reseting 419 * these queues at the needed time. 420 * 421 * XXX PS-Poll 422 */ 423 sc->sc_bhalq = ath_beaconq_setup(ah); 424 if (sc->sc_bhalq == (u_int) -1) { 425 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 426 error = EIO; 427 goto bad2; 428 } 429 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 430 if (sc->sc_cabq == NULL) { 431 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 432 error = EIO; 433 goto bad2; 434 } 435 /* NB: insure BK queue is the lowest priority h/w queue */ 436 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 437 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 438 ieee80211_wme_acnames[WME_AC_BK]); 439 error = EIO; 440 goto bad2; 441 } 442 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 443 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 444 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 445 /* 446 * Not enough hardware tx queues to properly do WME; 447 * just punt and assign them all to the same h/w queue. 448 * We could do a better job of this if, for example, 449 * we allocate queues when we switch from station to 450 * AP mode. 451 */ 452 if (sc->sc_ac2q[WME_AC_VI] != NULL) 453 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 454 if (sc->sc_ac2q[WME_AC_BE] != NULL) 455 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 456 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 457 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 458 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 459 } 460 461 /* 462 * Special case certain configurations. Note the 463 * CAB queue is handled by these specially so don't 464 * include them when checking the txq setup mask. 465 */ 466 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 467 case 0x01: 468 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 469 break; 470 case 0x0f: 471 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 472 break; 473 default: 474 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 475 break; 476 } 477 478 /* 479 * Setup rate control. Some rate control modules 480 * call back to change the anntena state so expose 481 * the necessary entry points. 482 * XXX maybe belongs in struct ath_ratectrl? 483 */ 484 sc->sc_setdefantenna = ath_setdefantenna; 485 sc->sc_rc = ath_rate_attach(sc); 486 if (sc->sc_rc == NULL) { 487 error = EIO; 488 goto bad2; 489 } 490 491 sc->sc_blinking = 0; 492 sc->sc_ledstate = 1; 493 sc->sc_ledon = 0; /* low true */ 494 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 495 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 496 /* 497 * Auto-enable soft led processing for IBM cards and for 498 * 5211 minipci cards. Users can also manually enable/disable 499 * support with a sysctl. 500 */ 501 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 502 if (sc->sc_softled) { 503 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 504 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 505 } 506 507 ifp->if_softc = sc; 508 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 509 ifp->if_start = ath_start; 510 ifp->if_watchdog = ath_watchdog; 511 ifp->if_ioctl = ath_ioctl; 512 ifp->if_init = ath_ifinit; 513 IFQ_SET_READY(&ifp->if_snd); 514 515 ic->ic_ifp = ifp; 516 ic->ic_reset = ath_reset; 517 ic->ic_newassoc = ath_newassoc; 518 ic->ic_updateslot = ath_updateslot; 519 ic->ic_wme.wme_update = ath_wme_update; 520 /* XXX not right but it's not used anywhere important */ 521 ic->ic_phytype = IEEE80211_T_OFDM; 522 ic->ic_opmode = IEEE80211_M_STA; 523 ic->ic_caps = 524 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 525 | IEEE80211_C_HOSTAP /* hostap mode */ 526 | IEEE80211_C_MONITOR /* monitor mode */ 527 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 528 | IEEE80211_C_SHSLOT /* short slot time supported */ 529 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 530 ; 531 /* 532 * Query the hal to figure out h/w crypto support. 533 */ 534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 535 ic->ic_caps |= IEEE80211_C_WEP; 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 537 ic->ic_caps |= IEEE80211_C_AES; 538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 539 ic->ic_caps |= IEEE80211_C_AES_CCM; 540 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 541 ic->ic_caps |= IEEE80211_C_CKIP; 542 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 543 ic->ic_caps |= IEEE80211_C_TKIP; 544 /* 545 * Check if h/w does the MIC and/or whether the 546 * separate key cache entries are required to 547 * handle both tx+rx MIC keys. 548 */ 549 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 550 ic->ic_caps |= IEEE80211_C_TKIPMIC; 551 if (ath_hal_tkipsplit(ah)) 552 sc->sc_splitmic = 1; 553 } 554 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 555 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 556 /* 557 * TPC support can be done either with a global cap or 558 * per-packet support. The latter is not available on 559 * all parts. We're a bit pedantic here as all parts 560 * support a global cap. 561 */ 562 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 563 ic->ic_caps |= IEEE80211_C_TXPMGT; 564 565 /* 566 * Mark WME capability only if we have sufficient 567 * hardware queues to do proper priority scheduling. 568 */ 569 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 570 ic->ic_caps |= IEEE80211_C_WME; 571 /* 572 * Check for misc other capabilities. 573 */ 574 if (ath_hal_hasbursting(ah)) 575 ic->ic_caps |= IEEE80211_C_BURST; 576 577 /* 578 * Indicate we need the 802.11 header padded to a 579 * 32-bit boundary for 4-address and QoS frames. 580 */ 581 ic->ic_flags |= IEEE80211_F_DATAPAD; 582 583 /* 584 * Query the hal about antenna support. 585 */ 586 sc->sc_defant = ath_hal_getdefantenna(ah); 587 588 /* 589 * Not all chips have the VEOL support we want to 590 * use with IBSS beacons; check here for it. 591 */ 592 sc->sc_hasveol = ath_hal_hasveol(ah); 593 594 /* get mac address from hardware */ 595 ath_hal_getmac(ah, ic->ic_myaddr); 596 597 if_attach(ifp); 598 /* call MI attach routine. */ 599 ieee80211_ifattach(ic); 600 /* override default methods */ 601 ic->ic_node_alloc = ath_node_alloc; 602 sc->sc_node_free = ic->ic_node_free; 603 ic->ic_node_free = ath_node_free; 604 ic->ic_node_getrssi = ath_node_getrssi; 605 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 606 ic->ic_recv_mgmt = ath_recv_mgmt; 607 sc->sc_newstate = ic->ic_newstate; 608 ic->ic_newstate = ath_newstate; 609 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 610 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 611 ic->ic_crypto.cs_key_delete = ath_key_delete; 612 ic->ic_crypto.cs_key_set = ath_key_set; 613 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 614 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 615 /* complete initialization */ 616 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 617 618 ath_bpfattach(sc); 619 620 #ifdef __NetBSD__ 621 sc->sc_flags |= ATH_ATTACHED; 622 /* 623 * Make sure the interface is shutdown during reboot. 624 */ 625 sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 626 if (sc->sc_sdhook == NULL) 627 printf("%s: WARNING: unable to establish shutdown hook\n", 628 sc->sc_dev.dv_xname); 629 sc->sc_powerhook = powerhook_establish(ath_power, sc); 630 if (sc->sc_powerhook == NULL) 631 printf("%s: WARNING: unable to establish power hook\n", 632 sc->sc_dev.dv_xname); 633 #endif 634 635 /* 636 * Setup dynamic sysctl's now that country code and 637 * regdomain are available from the hal. 638 */ 639 ath_sysctlattach(sc); 640 641 ieee80211_announce(ic); 642 ath_announce(sc); 643 return 0; 644 bad2: 645 ath_tx_cleanup(sc); 646 ath_desc_free(sc); 647 bad: 648 if (ah) 649 ath_hal_detach(ah); 650 sc->sc_invalid = 1; 651 return error; 652 } 653 654 int 655 ath_detach(struct ath_softc *sc) 656 { 657 struct ifnet *ifp = &sc->sc_if; 658 int s; 659 660 if ((sc->sc_flags & ATH_ATTACHED) == 0) 661 return (0); 662 663 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 664 __func__, ifp->if_flags); 665 666 s = splnet(); 667 ath_stop(ifp, 1); 668 #if NBPFILTER > 0 669 bpfdetach(ifp); 670 #endif 671 /* 672 * NB: the order of these is important: 673 * o call the 802.11 layer before detaching the hal to 674 * insure callbacks into the driver to delete global 675 * key cache entries can be handled 676 * o reclaim the tx queue data structures after calling 677 * the 802.11 layer as we'll get called back to reclaim 678 * node state and potentially want to use them 679 * o to cleanup the tx queues the hal is called, so detach 680 * it last 681 * Other than that, it's straightforward... 682 */ 683 ieee80211_ifdetach(&sc->sc_ic); 684 ath_rate_detach(sc->sc_rc); 685 ath_desc_free(sc); 686 ath_tx_cleanup(sc); 687 sysctl_teardown(&sc->sc_sysctllog); 688 ath_hal_detach(sc->sc_ah); 689 if_detach(ifp); 690 splx(s); 691 powerhook_disestablish(sc->sc_powerhook); 692 shutdownhook_disestablish(sc->sc_sdhook); 693 694 return 0; 695 } 696 697 #ifdef __NetBSD__ 698 void 699 ath_power(int why, void *arg) 700 { 701 struct ath_softc *sc = arg; 702 int s; 703 704 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 705 706 s = splnet(); 707 switch (why) { 708 case PWR_SUSPEND: 709 case PWR_STANDBY: 710 ath_suspend(sc, why); 711 break; 712 case PWR_RESUME: 713 ath_resume(sc, why); 714 break; 715 case PWR_SOFTSUSPEND: 716 case PWR_SOFTSTANDBY: 717 case PWR_SOFTRESUME: 718 break; 719 } 720 splx(s); 721 } 722 #endif 723 724 void 725 ath_suspend(struct ath_softc *sc, int why) 726 { 727 struct ifnet *ifp = &sc->sc_if; 728 729 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 730 __func__, ifp->if_flags); 731 732 ath_stop(ifp, 1); 733 if (sc->sc_power != NULL) 734 (*sc->sc_power)(sc, why); 735 } 736 737 void 738 ath_resume(struct ath_softc *sc, int why) 739 { 740 struct ifnet *ifp = &sc->sc_if; 741 742 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 743 __func__, ifp->if_flags); 744 745 if (ifp->if_flags & IFF_UP) { 746 ath_init(sc); 747 #if 0 748 (void)ath_intr(sc); 749 #endif 750 if (sc->sc_power != NULL) 751 (*sc->sc_power)(sc, why); 752 if (ifp->if_flags & IFF_RUNNING) 753 ath_start(ifp); 754 } 755 if (sc->sc_softled) { 756 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 757 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 758 } 759 } 760 761 void 762 ath_shutdown(void *arg) 763 { 764 struct ath_softc *sc = arg; 765 766 ath_stop(&sc->sc_if, 1); 767 } 768 769 /* 770 * Interrupt handler. Most of the actual processing is deferred. 771 */ 772 int 773 ath_intr(void *arg) 774 { 775 struct ath_softc *sc = arg; 776 struct ifnet *ifp = &sc->sc_if; 777 struct ath_hal *ah = sc->sc_ah; 778 HAL_INT status; 779 780 if (sc->sc_invalid) { 781 /* 782 * The hardware is not ready/present, don't touch anything. 783 * Note this can happen early on if the IRQ is shared. 784 */ 785 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 786 return 0; 787 } 788 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 789 return 0; 790 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 791 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 792 __func__, ifp->if_flags); 793 ath_hal_getisr(ah, &status); /* clear ISR */ 794 ath_hal_intrset(ah, 0); /* disable further intr's */ 795 return 1; /* XXX */ 796 } 797 /* 798 * Figure out the reason(s) for the interrupt. Note 799 * that the hal returns a pseudo-ISR that may include 800 * bits we haven't explicitly enabled so we mask the 801 * value to insure we only process bits we requested. 802 */ 803 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 804 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 805 status &= sc->sc_imask; /* discard unasked for bits */ 806 if (status & HAL_INT_FATAL) { 807 /* 808 * Fatal errors are unrecoverable. Typically 809 * these are caused by DMA errors. Unfortunately 810 * the exact reason is not (presently) returned 811 * by the hal. 812 */ 813 sc->sc_stats.ast_hardware++; 814 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 815 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 816 } else if (status & HAL_INT_RXORN) { 817 sc->sc_stats.ast_rxorn++; 818 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 819 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 820 } else { 821 if (status & HAL_INT_SWBA) { 822 /* 823 * Software beacon alert--time to send a beacon. 824 * Handle beacon transmission directly; deferring 825 * this is too slow to meet timing constraints 826 * under load. 827 */ 828 ath_beacon_proc(sc, 0); 829 } 830 if (status & HAL_INT_RXEOL) { 831 /* 832 * NB: the hardware should re-read the link when 833 * RXE bit is written, but it doesn't work at 834 * least on older hardware revs. 835 */ 836 sc->sc_stats.ast_rxeol++; 837 sc->sc_rxlink = NULL; 838 } 839 if (status & HAL_INT_TXURN) { 840 sc->sc_stats.ast_txurn++; 841 /* bump tx trigger level */ 842 ath_hal_updatetxtriglevel(ah, AH_TRUE); 843 } 844 if (status & HAL_INT_RX) 845 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 846 if (status & HAL_INT_TX) 847 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 848 if (status & HAL_INT_BMISS) { 849 sc->sc_stats.ast_bmiss++; 850 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 851 } 852 if (status & HAL_INT_MIB) { 853 sc->sc_stats.ast_mib++; 854 /* 855 * Disable interrupts until we service the MIB 856 * interrupt; otherwise it will continue to fire. 857 */ 858 ath_hal_intrset(ah, 0); 859 /* 860 * Let the hal handle the event. We assume it will 861 * clear whatever condition caused the interrupt. 862 */ 863 ath_hal_mibevent(ah, 864 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 865 ath_hal_intrset(ah, sc->sc_imask); 866 } 867 } 868 return 1; 869 } 870 871 static void 872 ath_fatal_proc(void *arg, int pending) 873 { 874 struct ath_softc *sc = arg; 875 struct ifnet *ifp = &sc->sc_if; 876 877 if_printf(ifp, "hardware error; resetting\n"); 878 ath_reset(ifp); 879 } 880 881 static void 882 ath_rxorn_proc(void *arg, int pending) 883 { 884 struct ath_softc *sc = arg; 885 struct ifnet *ifp = &sc->sc_if; 886 887 if_printf(ifp, "rx FIFO overrun; resetting\n"); 888 ath_reset(ifp); 889 } 890 891 static void 892 ath_bmiss_proc(void *arg, int pending) 893 { 894 struct ath_softc *sc = arg; 895 struct ieee80211com *ic = &sc->sc_ic; 896 897 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 898 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 899 ("unexpect operating mode %u", ic->ic_opmode)); 900 if (ic->ic_state == IEEE80211_S_RUN) { 901 /* 902 * Rather than go directly to scan state, try to 903 * reassociate first. If that fails then the state 904 * machine will drop us into scanning after timing 905 * out waiting for a probe response. 906 */ 907 NET_LOCK_GIANT(); 908 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 909 NET_UNLOCK_GIANT(); 910 } 911 } 912 913 static u_int 914 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 915 { 916 #define N(a) (sizeof(a) / sizeof(a[0])) 917 static const u_int modeflags[] = { 918 0, /* IEEE80211_MODE_AUTO */ 919 CHANNEL_A, /* IEEE80211_MODE_11A */ 920 CHANNEL_B, /* IEEE80211_MODE_11B */ 921 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 922 0, /* IEEE80211_MODE_FH */ 923 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 924 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 925 }; 926 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 927 928 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 929 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 930 return modeflags[mode]; 931 #undef N 932 } 933 934 static int 935 ath_ifinit(struct ifnet *ifp) 936 { 937 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 938 939 return ath_init(sc); 940 } 941 942 static int 943 ath_init(struct ath_softc *sc) 944 { 945 struct ifnet *ifp = &sc->sc_if; 946 struct ieee80211com *ic = &sc->sc_ic; 947 struct ath_hal *ah = sc->sc_ah; 948 HAL_STATUS status; 949 int error = 0; 950 951 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 952 __func__, ifp->if_flags); 953 954 ATH_LOCK(sc); 955 956 if ((error = ath_enable(sc)) != 0) 957 return error; 958 959 /* 960 * Stop anything previously setup. This is safe 961 * whether this is the first time through or not. 962 */ 963 ath_stop_locked(ifp, 0); 964 965 /* 966 * The basic interface to setting the hardware in a good 967 * state is ``reset''. On return the hardware is known to 968 * be powered up and with interrupts disabled. This must 969 * be followed by initialization of the appropriate bits 970 * and then setup of the interrupt mask. 971 */ 972 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 973 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 974 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 975 if_printf(ifp, "unable to reset hardware; hal status %u\n", 976 status); 977 error = EIO; 978 goto done; 979 } 980 981 /* 982 * This is needed only to setup initial state 983 * but it's best done after a reset. 984 */ 985 ath_update_txpow(sc); 986 /* 987 * Likewise this is set during reset so update 988 * state cached in the driver. 989 */ 990 sc->sc_diversity = ath_hal_getdiversity(ah); 991 992 /* 993 * Setup the hardware after reset: the key cache 994 * is filled as needed and the receive engine is 995 * set going. Frame transmit is handled entirely 996 * in the frame output path; there's nothing to do 997 * here except setup the interrupt mask. 998 */ 999 if ((error = ath_startrecv(sc)) != 0) { 1000 if_printf(ifp, "unable to start recv logic\n"); 1001 goto done; 1002 } 1003 1004 /* 1005 * Enable interrupts. 1006 */ 1007 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1008 | HAL_INT_RXEOL | HAL_INT_RXORN 1009 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1010 /* 1011 * Enable MIB interrupts when there are hardware phy counters. 1012 * Note we only do this (at the moment) for station mode. 1013 */ 1014 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1015 sc->sc_imask |= HAL_INT_MIB; 1016 ath_hal_intrset(ah, sc->sc_imask); 1017 1018 ifp->if_flags |= IFF_RUNNING; 1019 ic->ic_state = IEEE80211_S_INIT; 1020 1021 /* 1022 * The hardware should be ready to go now so it's safe 1023 * to kick the 802.11 state machine as it's likely to 1024 * immediately call back to us to send mgmt frames. 1025 */ 1026 ath_chan_change(sc, ic->ic_curchan); 1027 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1028 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1029 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1030 } else 1031 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1032 done: 1033 ATH_UNLOCK(sc); 1034 return error; 1035 } 1036 1037 static void 1038 ath_stop_locked(struct ifnet *ifp, int disable) 1039 { 1040 struct ath_softc *sc = ifp->if_softc; 1041 struct ieee80211com *ic = &sc->sc_ic; 1042 struct ath_hal *ah = sc->sc_ah; 1043 1044 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1045 __func__, sc->sc_invalid, ifp->if_flags); 1046 1047 ATH_LOCK_ASSERT(sc); 1048 if (ifp->if_flags & IFF_RUNNING) { 1049 /* 1050 * Shutdown the hardware and driver: 1051 * reset 802.11 state machine 1052 * turn off timers 1053 * disable interrupts 1054 * turn off the radio 1055 * clear transmit machinery 1056 * clear receive machinery 1057 * drain and release tx queues 1058 * reclaim beacon resources 1059 * power down hardware 1060 * 1061 * Note that some of this work is not possible if the 1062 * hardware is gone (invalid). 1063 */ 1064 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1065 ifp->if_flags &= ~IFF_RUNNING; 1066 ifp->if_timer = 0; 1067 if (!sc->sc_invalid) { 1068 if (sc->sc_softled) { 1069 callout_stop(&sc->sc_ledtimer); 1070 ath_hal_gpioset(ah, sc->sc_ledpin, 1071 !sc->sc_ledon); 1072 sc->sc_blinking = 0; 1073 } 1074 ath_hal_intrset(ah, 0); 1075 } 1076 ath_draintxq(sc); 1077 if (!sc->sc_invalid) { 1078 ath_stoprecv(sc); 1079 ath_hal_phydisable(ah); 1080 } else 1081 sc->sc_rxlink = NULL; 1082 IF_PURGE(&ifp->if_snd); 1083 ath_beacon_free(sc); 1084 if (disable) 1085 ath_disable(sc); 1086 } 1087 } 1088 1089 static void 1090 ath_stop(struct ifnet *ifp, int disable) 1091 { 1092 struct ath_softc *sc = ifp->if_softc; 1093 1094 ATH_LOCK(sc); 1095 ath_stop_locked(ifp, disable); 1096 if (!sc->sc_invalid) { 1097 /* 1098 * Set the chip in full sleep mode. Note that we are 1099 * careful to do this only when bringing the interface 1100 * completely to a stop. When the chip is in this state 1101 * it must be carefully woken up or references to 1102 * registers in the PCI clock domain may freeze the bus 1103 * (and system). This varies by chip and is mostly an 1104 * issue with newer parts that go to sleep more quickly. 1105 */ 1106 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 1107 } 1108 ATH_UNLOCK(sc); 1109 } 1110 1111 /* 1112 * Reset the hardware w/o losing operational state. This is 1113 * basically a more efficient way of doing ath_stop, ath_init, 1114 * followed by state transitions to the current 802.11 1115 * operational state. Used to recover from various errors and 1116 * to reset or reload hardware state. 1117 */ 1118 int 1119 ath_reset(struct ifnet *ifp) 1120 { 1121 struct ath_softc *sc = ifp->if_softc; 1122 struct ieee80211com *ic = &sc->sc_ic; 1123 struct ath_hal *ah = sc->sc_ah; 1124 struct ieee80211_channel *c; 1125 HAL_STATUS status; 1126 1127 /* 1128 * Convert to a HAL channel description with the flags 1129 * constrained to reflect the current operating mode. 1130 */ 1131 c = ic->ic_curchan; 1132 sc->sc_curchan.channel = c->ic_freq; 1133 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1134 1135 ath_hal_intrset(ah, 0); /* disable interrupts */ 1136 ath_draintxq(sc); /* stop xmit side */ 1137 ath_stoprecv(sc); /* stop recv side */ 1138 /* NB: indicate channel change so we do a full reset */ 1139 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1140 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1141 __func__, status); 1142 ath_update_txpow(sc); /* update tx power state */ 1143 sc->sc_diversity = ath_hal_getdiversity(ah); 1144 if (ath_startrecv(sc) != 0) /* restart recv */ 1145 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1146 /* 1147 * We may be doing a reset in response to an ioctl 1148 * that changes the channel so update any state that 1149 * might change as a result. 1150 */ 1151 ath_chan_change(sc, c); 1152 if (ic->ic_state == IEEE80211_S_RUN) 1153 ath_beacon_config(sc); /* restart beacons */ 1154 ath_hal_intrset(ah, sc->sc_imask); 1155 1156 ath_start(ifp); /* restart xmit */ 1157 return 0; 1158 } 1159 1160 static void 1161 ath_start(struct ifnet *ifp) 1162 { 1163 struct ath_softc *sc = ifp->if_softc; 1164 struct ath_hal *ah = sc->sc_ah; 1165 struct ieee80211com *ic = &sc->sc_ic; 1166 struct ieee80211_node *ni; 1167 struct ath_buf *bf; 1168 struct mbuf *m; 1169 struct ieee80211_frame *wh; 1170 struct ether_header *eh; 1171 1172 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1173 return; 1174 for (;;) { 1175 /* 1176 * Grab a TX buffer and associated resources. 1177 */ 1178 ATH_TXBUF_LOCK(sc); 1179 bf = STAILQ_FIRST(&sc->sc_txbuf); 1180 if (bf != NULL) 1181 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1182 ATH_TXBUF_UNLOCK(sc); 1183 if (bf == NULL) { 1184 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1185 __func__); 1186 sc->sc_stats.ast_tx_qstop++; 1187 ifp->if_flags |= IFF_OACTIVE; 1188 break; 1189 } 1190 /* 1191 * Poll the management queue for frames; they 1192 * have priority over normal data frames. 1193 */ 1194 IF_DEQUEUE(&ic->ic_mgtq, m); 1195 if (m == NULL) { 1196 /* 1197 * No data frames go out unless we're associated. 1198 */ 1199 if (ic->ic_state != IEEE80211_S_RUN) { 1200 DPRINTF(sc, ATH_DEBUG_ANY, 1201 "%s: ignore data packet, state %u\n", 1202 __func__, ic->ic_state); 1203 sc->sc_stats.ast_tx_discard++; 1204 ATH_TXBUF_LOCK(sc); 1205 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1206 ATH_TXBUF_UNLOCK(sc); 1207 break; 1208 } 1209 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1210 if (m == NULL) { 1211 ATH_TXBUF_LOCK(sc); 1212 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1213 ATH_TXBUF_UNLOCK(sc); 1214 break; 1215 } 1216 /* 1217 * Find the node for the destination so we can do 1218 * things like power save and fast frames aggregation. 1219 */ 1220 if (m->m_len < sizeof(struct ether_header) && 1221 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1222 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1223 ni = NULL; 1224 goto bad; 1225 } 1226 eh = mtod(m, struct ether_header *); 1227 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1228 if (ni == NULL) { 1229 /* NB: ieee80211_find_txnode does stat+msg */ 1230 m_freem(m); 1231 goto bad; 1232 } 1233 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1234 (m->m_flags & M_PWR_SAV) == 0) { 1235 /* 1236 * Station in power save mode; pass the frame 1237 * to the 802.11 layer and continue. We'll get 1238 * the frame back when the time is right. 1239 */ 1240 ieee80211_pwrsave(ic, ni, m); 1241 goto reclaim; 1242 } 1243 /* calculate priority so we can find the tx queue */ 1244 if (ieee80211_classify(ic, m, ni)) { 1245 DPRINTF(sc, ATH_DEBUG_XMIT, 1246 "%s: discard, classification failure\n", 1247 __func__); 1248 m_freem(m); 1249 goto bad; 1250 } 1251 ifp->if_opackets++; 1252 1253 #if NBPFILTER > 0 1254 if (ifp->if_bpf) 1255 bpf_mtap(ifp->if_bpf, m); 1256 #endif 1257 /* 1258 * Encapsulate the packet in prep for transmission. 1259 */ 1260 m = ieee80211_encap(ic, m, ni); 1261 if (m == NULL) { 1262 DPRINTF(sc, ATH_DEBUG_ANY, 1263 "%s: encapsulation failure\n", 1264 __func__); 1265 sc->sc_stats.ast_tx_encap++; 1266 goto bad; 1267 } 1268 } else { 1269 /* 1270 * Hack! The referenced node pointer is in the 1271 * rcvif field of the packet header. This is 1272 * placed there by ieee80211_mgmt_output because 1273 * we need to hold the reference with the frame 1274 * and there's no other way (other than packet 1275 * tags which we consider too expensive to use) 1276 * to pass it along. 1277 */ 1278 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1279 m->m_pkthdr.rcvif = NULL; 1280 1281 wh = mtod(m, struct ieee80211_frame *); 1282 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1283 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1284 /* fill time stamp */ 1285 u_int64_t tsf; 1286 u_int32_t *tstamp; 1287 1288 tsf = ath_hal_gettsf64(ah); 1289 /* XXX: adjust 100us delay to xmit */ 1290 tsf += 100; 1291 tstamp = (u_int32_t *)&wh[1]; 1292 tstamp[0] = htole32(tsf & 0xffffffff); 1293 tstamp[1] = htole32(tsf >> 32); 1294 } 1295 sc->sc_stats.ast_tx_mgmt++; 1296 } 1297 1298 if (ath_tx_start(sc, ni, bf, m)) { 1299 bad: 1300 ifp->if_oerrors++; 1301 reclaim: 1302 ATH_TXBUF_LOCK(sc); 1303 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1304 ATH_TXBUF_UNLOCK(sc); 1305 if (ni != NULL) 1306 ieee80211_free_node(ni); 1307 continue; 1308 } 1309 1310 sc->sc_tx_timer = 5; 1311 ifp->if_timer = 1; 1312 } 1313 } 1314 1315 static int 1316 ath_media_change(struct ifnet *ifp) 1317 { 1318 #define IS_UP(ifp) \ 1319 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1320 int error; 1321 1322 error = ieee80211_media_change(ifp); 1323 if (error == ENETRESET) { 1324 if (IS_UP(ifp)) 1325 ath_init(ifp->if_softc); /* XXX lose error */ 1326 error = 0; 1327 } 1328 return error; 1329 #undef IS_UP 1330 } 1331 1332 #ifdef AR_DEBUG 1333 static void 1334 ath_keyprint(const char *tag, u_int ix, 1335 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1336 { 1337 static const char *ciphers[] = { 1338 "WEP", 1339 "AES-OCB", 1340 "AES-CCM", 1341 "CKIP", 1342 "TKIP", 1343 "CLR", 1344 }; 1345 int i, n; 1346 1347 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1348 for (i = 0, n = hk->kv_len; i < n; i++) 1349 printf("%02x", hk->kv_val[i]); 1350 printf(" mac %s", ether_sprintf(mac)); 1351 if (hk->kv_type == HAL_CIPHER_TKIP) { 1352 printf(" mic "); 1353 for (i = 0; i < sizeof(hk->kv_mic); i++) 1354 printf("%02x", hk->kv_mic[i]); 1355 } 1356 printf("\n"); 1357 } 1358 #endif 1359 1360 /* 1361 * Set a TKIP key into the hardware. This handles the 1362 * potential distribution of key state to multiple key 1363 * cache slots for TKIP. 1364 */ 1365 static int 1366 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1367 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1368 { 1369 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1370 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1371 struct ath_hal *ah = sc->sc_ah; 1372 1373 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1374 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1375 KASSERT(sc->sc_splitmic, ("key cache !split")); 1376 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1377 /* 1378 * TX key goes at first index, RX key at the rx index. 1379 * The hal handles the MIC keys at index+64. 1380 */ 1381 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1382 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1383 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1384 return 0; 1385 1386 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1387 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1388 /* XXX delete tx key on failure? */ 1389 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1390 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1391 /* 1392 * TX/RX key goes at first index. 1393 * The hal handles the MIC keys are index+64. 1394 */ 1395 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1396 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1397 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1398 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1399 } 1400 return 0; 1401 #undef IEEE80211_KEY_XR 1402 } 1403 1404 /* 1405 * Set a net80211 key into the hardware. This handles the 1406 * potential distribution of key state to multiple key 1407 * cache slots for TKIP with hardware MIC support. 1408 */ 1409 static int 1410 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1411 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1412 struct ieee80211_node *bss) 1413 { 1414 #define N(a) (sizeof(a)/sizeof(a[0])) 1415 static const u_int8_t ciphermap[] = { 1416 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1417 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1418 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1419 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1420 (u_int8_t) -1, /* 4 is not allocated */ 1421 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1422 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1423 }; 1424 struct ath_hal *ah = sc->sc_ah; 1425 const struct ieee80211_cipher *cip = k->wk_cipher; 1426 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1427 const u_int8_t *mac; 1428 HAL_KEYVAL hk; 1429 1430 memset(&hk, 0, sizeof(hk)); 1431 /* 1432 * Software crypto uses a "clear key" so non-crypto 1433 * state kept in the key cache are maintained and 1434 * so that rx frames have an entry to match. 1435 */ 1436 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1437 KASSERT(cip->ic_cipher < N(ciphermap), 1438 ("invalid cipher type %u", cip->ic_cipher)); 1439 hk.kv_type = ciphermap[cip->ic_cipher]; 1440 hk.kv_len = k->wk_keylen; 1441 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1442 } else 1443 hk.kv_type = HAL_CIPHER_CLR; 1444 1445 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1446 /* 1447 * Group keys on hardware that supports multicast frame 1448 * key search use a mac that is the sender's address with 1449 * the high bit set instead of the app-specified address. 1450 */ 1451 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1452 gmac[0] |= 0x80; 1453 mac = gmac; 1454 } else 1455 mac = mac0; 1456 1457 if (hk.kv_type == HAL_CIPHER_TKIP && 1458 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1459 sc->sc_splitmic) { 1460 return ath_keyset_tkip(sc, k, &hk, mac); 1461 } else { 1462 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1463 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1464 } 1465 #undef N 1466 } 1467 1468 /* 1469 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1470 * each key, one for decrypt/encrypt and the other for the MIC. 1471 */ 1472 static u_int16_t 1473 key_alloc_2pair(struct ath_softc *sc, 1474 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1475 { 1476 #define N(a) (sizeof(a)/sizeof(a[0])) 1477 u_int i, keyix; 1478 1479 KASSERT(sc->sc_splitmic, ("key cache !split")); 1480 /* XXX could optimize */ 1481 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1482 u_int8_t b = sc->sc_keymap[i]; 1483 if (b != 0xff) { 1484 /* 1485 * One or more slots in this byte are free. 1486 */ 1487 keyix = i*NBBY; 1488 while (b & 1) { 1489 again: 1490 keyix++; 1491 b >>= 1; 1492 } 1493 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1494 if (isset(sc->sc_keymap, keyix+32) || 1495 isset(sc->sc_keymap, keyix+64) || 1496 isset(sc->sc_keymap, keyix+32+64)) { 1497 /* full pair unavailable */ 1498 /* XXX statistic */ 1499 if (keyix == (i+1)*NBBY) { 1500 /* no slots were appropriate, advance */ 1501 continue; 1502 } 1503 goto again; 1504 } 1505 setbit(sc->sc_keymap, keyix); 1506 setbit(sc->sc_keymap, keyix+64); 1507 setbit(sc->sc_keymap, keyix+32); 1508 setbit(sc->sc_keymap, keyix+32+64); 1509 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1510 "%s: key pair %u,%u %u,%u\n", 1511 __func__, keyix, keyix+64, 1512 keyix+32, keyix+32+64); 1513 *txkeyix = keyix; 1514 *rxkeyix = keyix+32; 1515 return 1; 1516 } 1517 } 1518 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1519 return 0; 1520 #undef N 1521 } 1522 1523 /* 1524 * Allocate a single key cache slot. 1525 */ 1526 static int 1527 key_alloc_single(struct ath_softc *sc, 1528 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1529 { 1530 #define N(a) (sizeof(a)/sizeof(a[0])) 1531 u_int i, keyix; 1532 1533 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1534 for (i = 0; i < N(sc->sc_keymap); i++) { 1535 u_int8_t b = sc->sc_keymap[i]; 1536 if (b != 0xff) { 1537 /* 1538 * One or more slots are free. 1539 */ 1540 keyix = i*NBBY; 1541 while (b & 1) 1542 keyix++, b >>= 1; 1543 setbit(sc->sc_keymap, keyix); 1544 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1545 __func__, keyix); 1546 *txkeyix = *rxkeyix = keyix; 1547 return 1; 1548 } 1549 } 1550 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1551 return 0; 1552 #undef N 1553 } 1554 1555 /* 1556 * Allocate one or more key cache slots for a uniacst key. The 1557 * key itself is needed only to identify the cipher. For hardware 1558 * TKIP with split cipher+MIC keys we allocate two key cache slot 1559 * pairs so that we can setup separate TX and RX MIC keys. Note 1560 * that the MIC key for a TKIP key at slot i is assumed by the 1561 * hardware to be at slot i+64. This limits TKIP keys to the first 1562 * 64 entries. 1563 */ 1564 static int 1565 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1566 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1567 { 1568 struct ath_softc *sc = ic->ic_ifp->if_softc; 1569 1570 /* 1571 * Group key allocation must be handled specially for 1572 * parts that do not support multicast key cache search 1573 * functionality. For those parts the key id must match 1574 * the h/w key index so lookups find the right key. On 1575 * parts w/ the key search facility we install the sender's 1576 * mac address (with the high bit set) and let the hardware 1577 * find the key w/o using the key id. This is preferred as 1578 * it permits us to support multiple users for adhoc and/or 1579 * multi-station operation. 1580 */ 1581 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1582 if (!(&ic->ic_nw_keys[0] <= k && 1583 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1584 /* should not happen */ 1585 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1586 "%s: bogus group key\n", __func__); 1587 return 0; 1588 } 1589 /* 1590 * XXX we pre-allocate the global keys so 1591 * have no way to check if they've already been allocated. 1592 */ 1593 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1594 return 1; 1595 } 1596 1597 /* 1598 * We allocate two pair for TKIP when using the h/w to do 1599 * the MIC. For everything else, including software crypto, 1600 * we allocate a single entry. Note that s/w crypto requires 1601 * a pass-through slot on the 5211 and 5212. The 5210 does 1602 * not support pass-through cache entries and we map all 1603 * those requests to slot 0. 1604 */ 1605 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1606 return key_alloc_single(sc, keyix, rxkeyix); 1607 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1608 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1609 return key_alloc_2pair(sc, keyix, rxkeyix); 1610 } else { 1611 return key_alloc_single(sc, keyix, rxkeyix); 1612 } 1613 } 1614 1615 /* 1616 * Delete an entry in the key cache allocated by ath_key_alloc. 1617 */ 1618 static int 1619 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1620 { 1621 struct ath_softc *sc = ic->ic_ifp->if_softc; 1622 struct ath_hal *ah = sc->sc_ah; 1623 const struct ieee80211_cipher *cip = k->wk_cipher; 1624 u_int keyix = k->wk_keyix; 1625 1626 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1627 1628 ath_hal_keyreset(ah, keyix); 1629 /* 1630 * Handle split tx/rx keying required for TKIP with h/w MIC. 1631 */ 1632 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1633 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1634 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1635 if (keyix >= IEEE80211_WEP_NKID) { 1636 /* 1637 * Don't touch keymap entries for global keys so 1638 * they are never considered for dynamic allocation. 1639 */ 1640 clrbit(sc->sc_keymap, keyix); 1641 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1642 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1643 sc->sc_splitmic) { 1644 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1645 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1646 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1647 } 1648 } 1649 return 1; 1650 } 1651 1652 /* 1653 * Set the key cache contents for the specified key. Key cache 1654 * slot(s) must already have been allocated by ath_key_alloc. 1655 */ 1656 static int 1657 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1658 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1659 { 1660 struct ath_softc *sc = ic->ic_ifp->if_softc; 1661 1662 return ath_keyset(sc, k, mac, ic->ic_bss); 1663 } 1664 1665 /* 1666 * Block/unblock tx+rx processing while a key change is done. 1667 * We assume the caller serializes key management operations 1668 * so we only need to worry about synchronization with other 1669 * uses that originate in the driver. 1670 */ 1671 static void 1672 ath_key_update_begin(struct ieee80211com *ic) 1673 { 1674 struct ifnet *ifp = ic->ic_ifp; 1675 struct ath_softc *sc = ifp->if_softc; 1676 1677 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1678 #if 0 1679 tasklet_disable(&sc->sc_rxtq); 1680 #endif 1681 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1682 } 1683 1684 static void 1685 ath_key_update_end(struct ieee80211com *ic) 1686 { 1687 struct ifnet *ifp = ic->ic_ifp; 1688 struct ath_softc *sc = ifp->if_softc; 1689 1690 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1691 IF_UNLOCK(&ifp->if_snd); 1692 #if 0 1693 tasklet_enable(&sc->sc_rxtq); 1694 #endif 1695 } 1696 1697 /* 1698 * Calculate the receive filter according to the 1699 * operating mode and state: 1700 * 1701 * o always accept unicast, broadcast, and multicast traffic 1702 * o maintain current state of phy error reception (the hal 1703 * may enable phy error frames for noise immunity work) 1704 * o probe request frames are accepted only when operating in 1705 * hostap, adhoc, or monitor modes 1706 * o enable promiscuous mode according to the interface state 1707 * o accept beacons: 1708 * - when operating in adhoc mode so the 802.11 layer creates 1709 * node table entries for peers, 1710 * - when operating in station mode for collecting rssi data when 1711 * the station is otherwise quiet, or 1712 * - when scanning 1713 */ 1714 static u_int32_t 1715 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1716 { 1717 struct ieee80211com *ic = &sc->sc_ic; 1718 struct ath_hal *ah = sc->sc_ah; 1719 struct ifnet *ifp = &sc->sc_if; 1720 u_int32_t rfilt; 1721 1722 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1723 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1724 if (ic->ic_opmode != IEEE80211_M_STA) 1725 rfilt |= HAL_RX_FILTER_PROBEREQ; 1726 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1727 (ifp->if_flags & IFF_PROMISC)) 1728 rfilt |= HAL_RX_FILTER_PROM; 1729 if (ic->ic_opmode == IEEE80211_M_STA || 1730 ic->ic_opmode == IEEE80211_M_IBSS || 1731 state == IEEE80211_S_SCAN) 1732 rfilt |= HAL_RX_FILTER_BEACON; 1733 return rfilt; 1734 } 1735 1736 static void 1737 ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1738 { 1739 u_int32_t val; 1740 u_int8_t pos; 1741 1742 /* calculate XOR of eight 6bit values */ 1743 val = LE_READ_4(dl + 0); 1744 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1745 val = LE_READ_4(dl + 3); 1746 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1747 pos &= 0x3f; 1748 mfilt[pos / 32] |= (1 << (pos % 32)); 1749 } 1750 1751 static void 1752 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1753 { 1754 struct ifnet *ifp = &sc->sc_if; 1755 struct ether_multi *enm; 1756 struct ether_multistep estep; 1757 1758 mfilt[0] = mfilt[1] = 0; 1759 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1760 while (enm != NULL) { 1761 /* XXX Punt on ranges. */ 1762 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1763 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1764 ifp->if_flags |= IFF_ALLMULTI; 1765 return; 1766 } 1767 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1768 ETHER_NEXT_MULTI(estep, enm); 1769 } 1770 ifp->if_flags &= ~IFF_ALLMULTI; 1771 } 1772 1773 static void 1774 ath_mode_init(struct ath_softc *sc) 1775 { 1776 struct ieee80211com *ic = &sc->sc_ic; 1777 struct ath_hal *ah = sc->sc_ah; 1778 u_int32_t rfilt, mfilt[2]; 1779 int i; 1780 1781 /* configure rx filter */ 1782 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1783 ath_hal_setrxfilter(ah, rfilt); 1784 1785 /* configure operational mode */ 1786 ath_hal_setopmode(ah); 1787 1788 /* Write keys to hardware; it may have been powered down. */ 1789 ath_key_update_begin(ic); 1790 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1791 ath_key_set(ic, 1792 &ic->ic_crypto.cs_nw_keys[i], 1793 ic->ic_myaddr); 1794 } 1795 ath_key_update_end(ic); 1796 1797 /* 1798 * Handle any link-level address change. Note that we only 1799 * need to force ic_myaddr; any other addresses are handled 1800 * as a byproduct of the ifnet code marking the interface 1801 * down then up. 1802 * 1803 * XXX should get from lladdr instead of arpcom but that's more work 1804 */ 1805 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1806 ath_hal_setmac(ah, ic->ic_myaddr); 1807 1808 /* calculate and install multicast filter */ 1809 #ifdef __FreeBSD__ 1810 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1811 mfilt[0] = mfilt[1] = 0; 1812 IF_ADDR_LOCK(ifp); 1813 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1814 caddr_t dl; 1815 1816 /* calculate XOR of eight 6bit values */ 1817 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1818 val = LE_READ_4(dl + 0); 1819 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1820 val = LE_READ_4(dl + 3); 1821 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1822 pos &= 0x3f; 1823 mfilt[pos / 32] |= (1 << (pos % 32)); 1824 } 1825 IF_ADDR_UNLOCK(ifp); 1826 } else { 1827 mfilt[0] = mfilt[1] = ~0; 1828 } 1829 #endif 1830 #ifdef __NetBSD__ 1831 ath_mcastfilter_compute(sc, mfilt); 1832 #endif 1833 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1834 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1835 __func__, rfilt, mfilt[0], mfilt[1]); 1836 } 1837 1838 /* 1839 * Set the slot time based on the current setting. 1840 */ 1841 static void 1842 ath_setslottime(struct ath_softc *sc) 1843 { 1844 struct ieee80211com *ic = &sc->sc_ic; 1845 struct ath_hal *ah = sc->sc_ah; 1846 1847 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1848 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1849 else 1850 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1851 sc->sc_updateslot = OK; 1852 } 1853 1854 /* 1855 * Callback from the 802.11 layer to update the 1856 * slot time based on the current setting. 1857 */ 1858 static void 1859 ath_updateslot(struct ifnet *ifp) 1860 { 1861 struct ath_softc *sc = ifp->if_softc; 1862 struct ieee80211com *ic = &sc->sc_ic; 1863 1864 /* 1865 * When not coordinating the BSS, change the hardware 1866 * immediately. For other operation we defer the change 1867 * until beacon updates have propagated to the stations. 1868 */ 1869 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1870 sc->sc_updateslot = UPDATE; 1871 else 1872 ath_setslottime(sc); 1873 } 1874 1875 /* 1876 * Setup a h/w transmit queue for beacons. 1877 */ 1878 static int 1879 ath_beaconq_setup(struct ath_hal *ah) 1880 { 1881 HAL_TXQ_INFO qi; 1882 1883 memset(&qi, 0, sizeof(qi)); 1884 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1885 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1886 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1887 /* NB: for dynamic turbo, don't enable any other interrupts */ 1888 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1889 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1890 } 1891 1892 /* 1893 * Setup the transmit queue parameters for the beacon queue. 1894 */ 1895 static int 1896 ath_beaconq_config(struct ath_softc *sc) 1897 { 1898 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1899 struct ieee80211com *ic = &sc->sc_ic; 1900 struct ath_hal *ah = sc->sc_ah; 1901 HAL_TXQ_INFO qi; 1902 1903 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1904 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1905 /* 1906 * Always burst out beacon and CAB traffic. 1907 */ 1908 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1909 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1910 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1911 } else { 1912 struct wmeParams *wmep = 1913 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1914 /* 1915 * Adhoc mode; important thing is to use 2x cwmin. 1916 */ 1917 qi.tqi_aifs = wmep->wmep_aifsn; 1918 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1919 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1920 } 1921 1922 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1923 device_printf(sc->sc_dev, "unable to update parameters for " 1924 "beacon hardware queue!\n"); 1925 return 0; 1926 } else { 1927 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1928 return 1; 1929 } 1930 #undef ATH_EXPONENT_TO_VALUE 1931 } 1932 1933 /* 1934 * Allocate and setup an initial beacon frame. 1935 */ 1936 static int 1937 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1938 { 1939 struct ieee80211com *ic = ni->ni_ic; 1940 struct ath_buf *bf; 1941 struct mbuf *m; 1942 int error; 1943 1944 bf = STAILQ_FIRST(&sc->sc_bbuf); 1945 if (bf == NULL) { 1946 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1947 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1948 return ENOMEM; /* XXX */ 1949 } 1950 /* 1951 * NB: the beacon data buffer must be 32-bit aligned; 1952 * we assume the mbuf routines will return us something 1953 * with this alignment (perhaps should assert). 1954 */ 1955 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1956 if (m == NULL) { 1957 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1958 __func__); 1959 sc->sc_stats.ast_be_nombuf++; 1960 return ENOMEM; 1961 } 1962 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1963 BUS_DMA_NOWAIT); 1964 if (error == 0) { 1965 bf->bf_m = m; 1966 bf->bf_node = ieee80211_ref_node(ni); 1967 } else { 1968 m_freem(m); 1969 } 1970 return error; 1971 } 1972 1973 /* 1974 * Setup the beacon frame for transmit. 1975 */ 1976 static void 1977 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1978 { 1979 #define USE_SHPREAMBLE(_ic) \ 1980 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1981 == IEEE80211_F_SHPREAMBLE) 1982 struct ieee80211_node *ni = bf->bf_node; 1983 struct ieee80211com *ic = ni->ni_ic; 1984 struct mbuf *m = bf->bf_m; 1985 struct ath_hal *ah = sc->sc_ah; 1986 struct ath_node *an = ATH_NODE(ni); 1987 struct ath_desc *ds; 1988 int flags, antenna; 1989 u_int8_t rate; 1990 1991 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1992 __func__, m, m->m_len); 1993 1994 /* setup descriptors */ 1995 ds = bf->bf_desc; 1996 1997 flags = HAL_TXDESC_NOACK; 1998 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1999 ds->ds_link = bf->bf_daddr; /* self-linked */ 2000 flags |= HAL_TXDESC_VEOL; 2001 /* 2002 * Let hardware handle antenna switching unless 2003 * the user has selected a transmit antenna 2004 * (sc_txantenna is not 0). 2005 */ 2006 antenna = sc->sc_txantenna; 2007 } else { 2008 ds->ds_link = 0; 2009 /* 2010 * Switch antenna every 4 beacons, unless the user 2011 * has selected a transmit antenna (sc_txantenna 2012 * is not 0). 2013 * 2014 * XXX assumes two antenna 2015 */ 2016 if (sc->sc_txantenna == 0) 2017 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2018 else 2019 antenna = sc->sc_txantenna; 2020 } 2021 2022 KASSERT(bf->bf_nseg == 1, 2023 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2024 ds->ds_data = bf->bf_segs[0].ds_addr; 2025 /* 2026 * Calculate rate code. 2027 * XXX everything at min xmit rate 2028 */ 2029 if (USE_SHPREAMBLE(ic)) 2030 rate = an->an_tx_mgtratesp; 2031 else 2032 rate = an->an_tx_mgtrate; 2033 ath_hal_setuptxdesc(ah, ds 2034 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2035 , sizeof(struct ieee80211_frame)/* header length */ 2036 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2037 , ni->ni_txpower /* txpower XXX */ 2038 , rate, 1 /* series 0 rate/tries */ 2039 , HAL_TXKEYIX_INVALID /* no encryption */ 2040 , antenna /* antenna mode */ 2041 , flags /* no ack, veol for beacons */ 2042 , 0 /* rts/cts rate */ 2043 , 0 /* rts/cts duration */ 2044 ); 2045 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2046 ath_hal_filltxdesc(ah, ds 2047 , roundup(m->m_len, 4) /* buffer length */ 2048 , AH_TRUE /* first segment */ 2049 , AH_TRUE /* last segment */ 2050 , ds /* first descriptor */ 2051 ); 2052 #undef USE_SHPREAMBLE 2053 } 2054 2055 /* 2056 * Transmit a beacon frame at SWBA. Dynamic updates to the 2057 * frame contents are done as needed and the slot time is 2058 * also adjusted based on current state. 2059 */ 2060 static void 2061 ath_beacon_proc(void *arg, int pending) 2062 { 2063 struct ath_softc *sc = arg; 2064 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2065 struct ieee80211_node *ni = bf->bf_node; 2066 struct ieee80211com *ic = ni->ni_ic; 2067 struct ath_hal *ah = sc->sc_ah; 2068 struct mbuf *m; 2069 int ncabq, error, otherant; 2070 2071 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2072 __func__, pending); 2073 2074 if (ic->ic_opmode == IEEE80211_M_STA || 2075 ic->ic_opmode == IEEE80211_M_MONITOR || 2076 bf == NULL || bf->bf_m == NULL) { 2077 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2078 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2079 return; 2080 } 2081 /* 2082 * Check if the previous beacon has gone out. If 2083 * not don't don't try to post another, skip this 2084 * period and wait for the next. Missed beacons 2085 * indicate a problem and should not occur. If we 2086 * miss too many consecutive beacons reset the device. 2087 */ 2088 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2089 sc->sc_bmisscount++; 2090 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2091 "%s: missed %u consecutive beacons\n", 2092 __func__, sc->sc_bmisscount); 2093 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2094 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2095 return; 2096 } 2097 if (sc->sc_bmisscount != 0) { 2098 DPRINTF(sc, ATH_DEBUG_BEACON, 2099 "%s: resume beacon xmit after %u misses\n", 2100 __func__, sc->sc_bmisscount); 2101 sc->sc_bmisscount = 0; 2102 } 2103 2104 /* 2105 * Update dynamic beacon contents. If this returns 2106 * non-zero then we need to remap the memory because 2107 * the beacon frame changed size (probably because 2108 * of the TIM bitmap). 2109 */ 2110 m = bf->bf_m; 2111 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2112 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2113 /* XXX too conservative? */ 2114 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2115 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2116 BUS_DMA_NOWAIT); 2117 if (error != 0) { 2118 if_printf(&sc->sc_if, 2119 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2120 __func__, error); 2121 return; 2122 } 2123 } 2124 2125 /* 2126 * Handle slot time change when a non-ERP station joins/leaves 2127 * an 11g network. The 802.11 layer notifies us via callback, 2128 * we mark updateslot, then wait one beacon before effecting 2129 * the change. This gives associated stations at least one 2130 * beacon interval to note the state change. 2131 */ 2132 /* XXX locking */ 2133 if (sc->sc_updateslot == UPDATE) 2134 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2135 else if (sc->sc_updateslot == COMMIT) 2136 ath_setslottime(sc); /* commit change to h/w */ 2137 2138 /* 2139 * Check recent per-antenna transmit statistics and flip 2140 * the default antenna if noticeably more frames went out 2141 * on the non-default antenna. 2142 * XXX assumes 2 anntenae 2143 */ 2144 otherant = sc->sc_defant & 1 ? 2 : 1; 2145 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2146 ath_setdefantenna(sc, otherant); 2147 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2148 2149 /* 2150 * Construct tx descriptor. 2151 */ 2152 ath_beacon_setup(sc, bf); 2153 2154 /* 2155 * Stop any current dma and put the new frame on the queue. 2156 * This should never fail since we check above that no frames 2157 * are still pending on the queue. 2158 */ 2159 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2160 DPRINTF(sc, ATH_DEBUG_ANY, 2161 "%s: beacon queue %u did not stop?\n", 2162 __func__, sc->sc_bhalq); 2163 } 2164 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2165 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2166 2167 /* 2168 * Enable the CAB queue before the beacon queue to 2169 * insure cab frames are triggered by this beacon. 2170 */ 2171 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2172 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2173 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2174 ath_hal_txstart(ah, sc->sc_bhalq); 2175 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2176 "%s: TXDP[%u] = %p (%p)\n", __func__, 2177 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2178 2179 sc->sc_stats.ast_be_xmit++; 2180 } 2181 2182 /* 2183 * Reset the hardware after detecting beacons have stopped. 2184 */ 2185 static void 2186 ath_bstuck_proc(void *arg, int pending) 2187 { 2188 struct ath_softc *sc = arg; 2189 struct ifnet *ifp = &sc->sc_if; 2190 2191 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2192 sc->sc_bmisscount); 2193 ath_reset(ifp); 2194 } 2195 2196 /* 2197 * Reclaim beacon resources. 2198 */ 2199 static void 2200 ath_beacon_free(struct ath_softc *sc) 2201 { 2202 struct ath_buf *bf; 2203 2204 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2205 if (bf->bf_m != NULL) { 2206 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2207 m_freem(bf->bf_m); 2208 bf->bf_m = NULL; 2209 } 2210 if (bf->bf_node != NULL) { 2211 ieee80211_free_node(bf->bf_node); 2212 bf->bf_node = NULL; 2213 } 2214 } 2215 } 2216 2217 /* 2218 * Configure the beacon and sleep timers. 2219 * 2220 * When operating as an AP this resets the TSF and sets 2221 * up the hardware to notify us when we need to issue beacons. 2222 * 2223 * When operating in station mode this sets up the beacon 2224 * timers according to the timestamp of the last received 2225 * beacon and the current TSF, configures PCF and DTIM 2226 * handling, programs the sleep registers so the hardware 2227 * will wakeup in time to receive beacons, and configures 2228 * the beacon miss handling so we'll receive a BMISS 2229 * interrupt when we stop seeing beacons from the AP 2230 * we've associated with. 2231 */ 2232 static void 2233 ath_beacon_config(struct ath_softc *sc) 2234 { 2235 #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) 2236 struct ath_hal *ah = sc->sc_ah; 2237 struct ieee80211com *ic = &sc->sc_ic; 2238 struct ieee80211_node *ni = ic->ic_bss; 2239 u_int32_t nexttbtt, intval; 2240 2241 /* extract tstamp from last beacon and convert to TU */ 2242 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2243 LE_READ_4(ni->ni_tstamp.data)); 2244 /* NB: the beacon interval is kept internally in TU's */ 2245 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2246 if (nexttbtt == 0) /* e.g. for ap mode */ 2247 nexttbtt = intval; 2248 else if (intval) /* NB: can be 0 for monitor mode */ 2249 nexttbtt = roundup(nexttbtt, intval); 2250 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2251 __func__, nexttbtt, intval, ni->ni_intval); 2252 if (ic->ic_opmode == IEEE80211_M_STA) { 2253 HAL_BEACON_STATE bs; 2254 u_int64_t tsf; 2255 u_int32_t tsftu; 2256 int dtimperiod, dtimcount; 2257 int cfpperiod, cfpcount; 2258 2259 /* 2260 * Setup dtim and cfp parameters according to 2261 * last beacon we received (which may be none). 2262 */ 2263 dtimperiod = ni->ni_dtim_period; 2264 if (dtimperiod <= 0) /* NB: 0 if not known */ 2265 dtimperiod = 1; 2266 dtimcount = ni->ni_dtim_count; 2267 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2268 dtimcount = 0; /* XXX? */ 2269 cfpperiod = 1; /* NB: no PCF support yet */ 2270 cfpcount = 0; 2271 #define FUDGE 2 2272 /* 2273 * Pull nexttbtt forward to reflect the current 2274 * TSF and calculate dtim+cfp state for the result. 2275 */ 2276 tsf = ath_hal_gettsf64(ah); 2277 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE; 2278 do { 2279 nexttbtt += intval; 2280 if (--dtimcount < 0) { 2281 dtimcount = dtimperiod - 1; 2282 if (--cfpcount < 0) 2283 cfpcount = cfpperiod - 1; 2284 } 2285 } while (nexttbtt < tsftu); 2286 #undef FUDGE 2287 memset(&bs, 0, sizeof(bs)); 2288 bs.bs_intval = intval; 2289 bs.bs_nexttbtt = nexttbtt; 2290 bs.bs_dtimperiod = dtimperiod*intval; 2291 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2292 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2293 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2294 bs.bs_cfpmaxduration = 0; 2295 #if 0 2296 /* 2297 * The 802.11 layer records the offset to the DTIM 2298 * bitmap while receiving beacons; use it here to 2299 * enable h/w detection of our AID being marked in 2300 * the bitmap vector (to indicate frames for us are 2301 * pending at the AP). 2302 * XXX do DTIM handling in s/w to WAR old h/w bugs 2303 * XXX enable based on h/w rev for newer chips 2304 */ 2305 bs.bs_timoffset = ni->ni_timoff; 2306 #endif 2307 /* 2308 * Calculate the number of consecutive beacons to miss 2309 * before taking a BMISS interrupt. The configuration 2310 * is specified in ms, so we need to convert that to 2311 * TU's and then calculate based on the beacon interval. 2312 * Note that we clamp the result to at most 10 beacons. 2313 */ 2314 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2315 if (bs.bs_bmissthreshold > 10) 2316 bs.bs_bmissthreshold = 10; 2317 else if (bs.bs_bmissthreshold <= 0) 2318 bs.bs_bmissthreshold = 1; 2319 2320 /* 2321 * Calculate sleep duration. The configuration is 2322 * given in ms. We insure a multiple of the beacon 2323 * period is used. Also, if the sleep duration is 2324 * greater than the DTIM period then it makes senses 2325 * to make it a multiple of that. 2326 * 2327 * XXX fixed at 100ms 2328 */ 2329 bs.bs_sleepduration = 2330 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2331 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2332 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2333 2334 DPRINTF(sc, ATH_DEBUG_BEACON, 2335 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2336 , __func__ 2337 , tsf, tsftu 2338 , bs.bs_intval 2339 , bs.bs_nexttbtt 2340 , bs.bs_dtimperiod 2341 , bs.bs_nextdtim 2342 , bs.bs_bmissthreshold 2343 , bs.bs_sleepduration 2344 , bs.bs_cfpperiod 2345 , bs.bs_cfpmaxduration 2346 , bs.bs_cfpnext 2347 , bs.bs_timoffset 2348 ); 2349 ath_hal_intrset(ah, 0); 2350 ath_hal_beacontimers(ah, &bs); 2351 sc->sc_imask |= HAL_INT_BMISS; 2352 ath_hal_intrset(ah, sc->sc_imask); 2353 } else { 2354 ath_hal_intrset(ah, 0); 2355 if (nexttbtt == intval) 2356 intval |= HAL_BEACON_RESET_TSF; 2357 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2358 /* 2359 * In IBSS mode enable the beacon timers but only 2360 * enable SWBA interrupts if we need to manually 2361 * prepare beacon frames. Otherwise we use a 2362 * self-linked tx descriptor and let the hardware 2363 * deal with things. 2364 */ 2365 intval |= HAL_BEACON_ENA; 2366 if (!sc->sc_hasveol) 2367 sc->sc_imask |= HAL_INT_SWBA; 2368 ath_beaconq_config(sc); 2369 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2370 /* 2371 * In AP mode we enable the beacon timers and 2372 * SWBA interrupts to prepare beacon frames. 2373 */ 2374 intval |= HAL_BEACON_ENA; 2375 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2376 ath_beaconq_config(sc); 2377 } 2378 ath_hal_beaconinit(ah, nexttbtt, intval); 2379 sc->sc_bmisscount = 0; 2380 ath_hal_intrset(ah, sc->sc_imask); 2381 /* 2382 * When using a self-linked beacon descriptor in 2383 * ibss mode load it once here. 2384 */ 2385 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2386 ath_beacon_proc(sc, 0); 2387 } 2388 #undef TSF_TO_TU 2389 } 2390 2391 static int 2392 ath_descdma_setup(struct ath_softc *sc, 2393 struct ath_descdma *dd, ath_bufhead *head, 2394 const char *name, int nbuf, int ndesc) 2395 { 2396 #define DS2PHYS(_dd, _ds) \ 2397 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2398 struct ifnet *ifp = &sc->sc_if; 2399 struct ath_desc *ds; 2400 struct ath_buf *bf; 2401 int i, bsize, error; 2402 2403 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2404 __func__, name, nbuf, ndesc); 2405 2406 dd->dd_name = name; 2407 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2408 2409 /* 2410 * Setup DMA descriptor area. 2411 */ 2412 dd->dd_dmat = sc->sc_dmat; 2413 2414 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2415 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2416 2417 if (error != 0) { 2418 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2419 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2420 goto fail0; 2421 } 2422 2423 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2424 dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2425 if (error != 0) { 2426 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2427 nbuf * ndesc, dd->dd_name, error); 2428 goto fail1; 2429 } 2430 2431 /* allocate descriptors */ 2432 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2433 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2434 if (error != 0) { 2435 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2436 "error %u\n", dd->dd_name, error); 2437 goto fail2; 2438 } 2439 2440 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2441 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2442 if (error != 0) { 2443 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2444 dd->dd_name, error); 2445 goto fail3; 2446 } 2447 2448 ds = dd->dd_desc; 2449 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2450 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2451 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2452 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2453 2454 /* allocate rx buffers */ 2455 bsize = sizeof(struct ath_buf) * nbuf; 2456 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2457 if (bf == NULL) { 2458 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2459 dd->dd_name, bsize); 2460 goto fail4; 2461 } 2462 dd->dd_bufptr = bf; 2463 2464 STAILQ_INIT(head); 2465 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2466 bf->bf_desc = ds; 2467 bf->bf_daddr = DS2PHYS(dd, ds); 2468 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2469 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2470 if (error != 0) { 2471 if_printf(ifp, "unable to create dmamap for %s " 2472 "buffer %u, error %u\n", dd->dd_name, i, error); 2473 ath_descdma_cleanup(sc, dd, head); 2474 return error; 2475 } 2476 STAILQ_INSERT_TAIL(head, bf, bf_list); 2477 } 2478 return 0; 2479 fail4: 2480 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2481 fail3: 2482 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2483 fail2: 2484 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2485 fail1: 2486 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2487 fail0: 2488 memset(dd, 0, sizeof(*dd)); 2489 return error; 2490 #undef DS2PHYS 2491 } 2492 2493 static void 2494 ath_descdma_cleanup(struct ath_softc *sc, 2495 struct ath_descdma *dd, ath_bufhead *head) 2496 { 2497 struct ath_buf *bf; 2498 struct ieee80211_node *ni; 2499 2500 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2501 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2502 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2503 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2504 2505 STAILQ_FOREACH(bf, head, bf_list) { 2506 if (bf->bf_m) { 2507 m_freem(bf->bf_m); 2508 bf->bf_m = NULL; 2509 } 2510 if (bf->bf_dmamap != NULL) { 2511 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2512 bf->bf_dmamap = NULL; 2513 } 2514 ni = bf->bf_node; 2515 bf->bf_node = NULL; 2516 if (ni != NULL) { 2517 /* 2518 * Reclaim node reference. 2519 */ 2520 ieee80211_free_node(ni); 2521 } 2522 } 2523 2524 STAILQ_INIT(head); 2525 free(dd->dd_bufptr, M_ATHDEV); 2526 memset(dd, 0, sizeof(*dd)); 2527 } 2528 2529 static int 2530 ath_desc_alloc(struct ath_softc *sc) 2531 { 2532 int error; 2533 2534 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2535 "rx", ATH_RXBUF, 1); 2536 if (error != 0) 2537 return error; 2538 2539 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2540 "tx", ATH_TXBUF, ATH_TXDESC); 2541 if (error != 0) { 2542 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2543 return error; 2544 } 2545 2546 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2547 "beacon", 1, 1); 2548 if (error != 0) { 2549 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2550 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2551 return error; 2552 } 2553 return 0; 2554 } 2555 2556 static void 2557 ath_desc_free(struct ath_softc *sc) 2558 { 2559 2560 if (sc->sc_bdma.dd_desc_len != 0) 2561 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2562 if (sc->sc_txdma.dd_desc_len != 0) 2563 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2564 if (sc->sc_rxdma.dd_desc_len != 0) 2565 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2566 } 2567 2568 static struct ieee80211_node * 2569 ath_node_alloc(struct ieee80211_node_table *nt) 2570 { 2571 struct ieee80211com *ic = nt->nt_ic; 2572 struct ath_softc *sc = ic->ic_ifp->if_softc; 2573 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2574 struct ath_node *an; 2575 2576 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2577 if (an == NULL) { 2578 /* XXX stat+msg */ 2579 return NULL; 2580 } 2581 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2582 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2583 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2584 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2585 ath_rate_node_init(sc, an); 2586 2587 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2588 return &an->an_node; 2589 } 2590 2591 static void 2592 ath_node_free(struct ieee80211_node *ni) 2593 { 2594 struct ieee80211com *ic = ni->ni_ic; 2595 struct ath_softc *sc = ic->ic_ifp->if_softc; 2596 2597 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2598 2599 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2600 sc->sc_node_free(ni); 2601 } 2602 2603 static u_int8_t 2604 ath_node_getrssi(const struct ieee80211_node *ni) 2605 { 2606 #define HAL_EP_RND(x, mul) \ 2607 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2608 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2609 int32_t rssi; 2610 2611 /* 2612 * When only one frame is received there will be no state in 2613 * avgrssi so fallback on the value recorded by the 802.11 layer. 2614 */ 2615 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2616 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2617 else 2618 rssi = ni->ni_rssi; 2619 /* NB: theoretically we shouldn't need this, but be paranoid */ 2620 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2621 #undef HAL_EP_RND 2622 } 2623 2624 static int 2625 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2626 { 2627 struct ath_hal *ah = sc->sc_ah; 2628 int error; 2629 struct mbuf *m; 2630 struct ath_desc *ds; 2631 2632 m = bf->bf_m; 2633 if (m == NULL) { 2634 /* 2635 * NB: by assigning a page to the rx dma buffer we 2636 * implicitly satisfy the Atheros requirement that 2637 * this buffer be cache-line-aligned and sized to be 2638 * multiple of the cache line size. Not doing this 2639 * causes weird stuff to happen (for the 5210 at least). 2640 */ 2641 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2642 if (m == NULL) { 2643 DPRINTF(sc, ATH_DEBUG_ANY, 2644 "%s: no mbuf/cluster\n", __func__); 2645 sc->sc_stats.ast_rx_nombuf++; 2646 return ENOMEM; 2647 } 2648 bf->bf_m = m; 2649 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2650 2651 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2652 bf->bf_dmamap, m, 2653 BUS_DMA_NOWAIT); 2654 if (error != 0) { 2655 DPRINTF(sc, ATH_DEBUG_ANY, 2656 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2657 __func__, error); 2658 sc->sc_stats.ast_rx_busdma++; 2659 return error; 2660 } 2661 KASSERT(bf->bf_nseg == 1, 2662 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2663 } 2664 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2665 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2666 2667 /* 2668 * Setup descriptors. For receive we always terminate 2669 * the descriptor list with a self-linked entry so we'll 2670 * not get overrun under high load (as can happen with a 2671 * 5212 when ANI processing enables PHY error frames). 2672 * 2673 * To insure the last descriptor is self-linked we create 2674 * each descriptor as self-linked and add it to the end. As 2675 * each additional descriptor is added the previous self-linked 2676 * entry is ``fixed'' naturally. This should be safe even 2677 * if DMA is happening. When processing RX interrupts we 2678 * never remove/process the last, self-linked, entry on the 2679 * descriptor list. This insures the hardware always has 2680 * someplace to write a new frame. 2681 */ 2682 ds = bf->bf_desc; 2683 ds->ds_link = bf->bf_daddr; /* link to self */ 2684 ds->ds_data = bf->bf_segs[0].ds_addr; 2685 ath_hal_setuprxdesc(ah, ds 2686 , m->m_len /* buffer size */ 2687 , 0 2688 ); 2689 2690 if (sc->sc_rxlink != NULL) 2691 *sc->sc_rxlink = bf->bf_daddr; 2692 sc->sc_rxlink = &ds->ds_link; 2693 return 0; 2694 } 2695 2696 /* 2697 * Extend 15-bit time stamp from rx descriptor to 2698 * a full 64-bit TSF using the current h/w TSF. 2699 */ 2700 static __inline u_int64_t 2701 ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp) 2702 { 2703 u_int64_t tsf; 2704 2705 tsf = ath_hal_gettsf64(ah); 2706 if ((tsf & 0x7fff) < rstamp) 2707 tsf -= 0x8000; 2708 return ((tsf &~ 0x7fff) | rstamp); 2709 } 2710 2711 /* 2712 * Intercept management frames to collect beacon rssi data 2713 * and to do ibss merges. 2714 */ 2715 static void 2716 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2717 struct ieee80211_node *ni, 2718 int subtype, int rssi, u_int32_t rstamp) 2719 { 2720 struct ath_softc *sc = ic->ic_ifp->if_softc; 2721 2722 /* 2723 * Call up first so subsequent work can use information 2724 * potentially stored in the node (e.g. for ibss merge). 2725 */ 2726 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2727 switch (subtype) { 2728 case IEEE80211_FC0_SUBTYPE_BEACON: 2729 /* update rssi statistics for use by the hal */ 2730 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2731 /* fall thru... */ 2732 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2733 if (ic->ic_opmode == IEEE80211_M_IBSS && 2734 ic->ic_state == IEEE80211_S_RUN) { 2735 u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp); 2736 2737 /* 2738 * Handle ibss merge as needed; check the tsf on the 2739 * frame before attempting the merge. The 802.11 spec 2740 * says the station should change it's bssid to match 2741 * the oldest station with the same ssid, where oldest 2742 * is determined by the tsf. Note that hardware 2743 * reconfiguration happens through callback to 2744 * ath_newstate as the state machine will go from 2745 * RUN -> RUN when this happens. 2746 */ 2747 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2748 DPRINTF(sc, ATH_DEBUG_STATE, 2749 "ibss merge, rstamp %u tsf %ju " 2750 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2751 (uintmax_t)ni->ni_tstamp.tsf); 2752 (void) ieee80211_ibss_merge(ni); 2753 } 2754 } 2755 break; 2756 } 2757 } 2758 2759 /* 2760 * Set the default antenna. 2761 */ 2762 static void 2763 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2764 { 2765 struct ath_hal *ah = sc->sc_ah; 2766 2767 /* XXX block beacon interrupts */ 2768 ath_hal_setdefantenna(ah, antenna); 2769 if (sc->sc_defant != antenna) 2770 sc->sc_stats.ast_ant_defswitch++; 2771 sc->sc_defant = antenna; 2772 sc->sc_rxotherant = 0; 2773 } 2774 2775 static void 2776 ath_rx_proc(void *arg, int npending) 2777 { 2778 #define PA2DESC(_sc, _pa) \ 2779 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2780 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2781 struct ath_softc *sc = arg; 2782 struct ath_buf *bf; 2783 struct ieee80211com *ic = &sc->sc_ic; 2784 struct ifnet *ifp = &sc->sc_if; 2785 struct ath_hal *ah = sc->sc_ah; 2786 struct ath_desc *ds; 2787 struct mbuf *m; 2788 struct ieee80211_node *ni; 2789 struct ath_node *an; 2790 int len, type; 2791 u_int phyerr; 2792 HAL_STATUS status; 2793 2794 NET_LOCK_GIANT(); /* XXX */ 2795 2796 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2797 do { 2798 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2799 if (bf == NULL) { /* NB: shouldn't happen */ 2800 if_printf(ifp, "%s: no buffer!\n", __func__); 2801 break; 2802 } 2803 ds = bf->bf_desc; 2804 if (ds->ds_link == bf->bf_daddr) { 2805 /* NB: never process the self-linked entry at the end */ 2806 break; 2807 } 2808 m = bf->bf_m; 2809 if (m == NULL) { /* NB: shouldn't happen */ 2810 if_printf(ifp, "%s: no mbuf!\n", __func__); 2811 continue; 2812 } 2813 /* XXX sync descriptor memory */ 2814 /* 2815 * Must provide the virtual address of the current 2816 * descriptor, the physical address, and the virtual 2817 * address of the next descriptor in the h/w chain. 2818 * This allows the HAL to look ahead to see if the 2819 * hardware is done with a descriptor by checking the 2820 * done bit in the following descriptor and the address 2821 * of the current descriptor the DMA engine is working 2822 * on. All this is necessary because of our use of 2823 * a self-linked list to avoid rx overruns. 2824 */ 2825 status = ath_hal_rxprocdesc(ah, ds, 2826 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2827 #ifdef AR_DEBUG 2828 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2829 ath_printrxbuf(bf, status == HAL_OK); 2830 #endif 2831 if (status == HAL_EINPROGRESS) 2832 break; 2833 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2834 if (ds->ds_rxstat.rs_more) { 2835 /* 2836 * Frame spans multiple descriptors; this 2837 * cannot happen yet as we don't support 2838 * jumbograms. If not in monitor mode, 2839 * discard the frame. 2840 */ 2841 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2842 sc->sc_stats.ast_rx_toobig++; 2843 goto rx_next; 2844 } 2845 /* fall thru for monitor mode handling... */ 2846 } else if (ds->ds_rxstat.rs_status != 0) { 2847 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2848 sc->sc_stats.ast_rx_crcerr++; 2849 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2850 sc->sc_stats.ast_rx_fifoerr++; 2851 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2852 sc->sc_stats.ast_rx_phyerr++; 2853 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2854 sc->sc_stats.ast_rx_phy[phyerr]++; 2855 goto rx_next; 2856 } 2857 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2858 /* 2859 * Decrypt error. If the error occurred 2860 * because there was no hardware key, then 2861 * let the frame through so the upper layers 2862 * can process it. This is necessary for 5210 2863 * parts which have no way to setup a ``clear'' 2864 * key cache entry. 2865 * 2866 * XXX do key cache faulting 2867 */ 2868 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2869 goto rx_accept; 2870 sc->sc_stats.ast_rx_badcrypt++; 2871 } 2872 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2873 sc->sc_stats.ast_rx_badmic++; 2874 /* 2875 * Do minimal work required to hand off 2876 * the 802.11 header for notifcation. 2877 */ 2878 /* XXX frag's and qos frames */ 2879 len = ds->ds_rxstat.rs_datalen; 2880 if (len >= sizeof (struct ieee80211_frame)) { 2881 bus_dmamap_sync(sc->sc_dmat, 2882 bf->bf_dmamap, 2883 0, bf->bf_dmamap->dm_mapsize, 2884 BUS_DMASYNC_POSTREAD); 2885 ieee80211_notify_michael_failure(ic, 2886 mtod(m, struct ieee80211_frame *), 2887 sc->sc_splitmic ? 2888 ds->ds_rxstat.rs_keyix-32 : 2889 ds->ds_rxstat.rs_keyix 2890 ); 2891 } 2892 } 2893 ifp->if_ierrors++; 2894 /* 2895 * Reject error frames, we normally don't want 2896 * to see them in monitor mode (in monitor mode 2897 * allow through packets that have crypto problems). 2898 */ 2899 if ((ds->ds_rxstat.rs_status &~ 2900 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2901 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2902 goto rx_next; 2903 } 2904 rx_accept: 2905 /* 2906 * Sync and unmap the frame. At this point we're 2907 * committed to passing the mbuf somewhere so clear 2908 * bf_m; this means a new sk_buff must be allocated 2909 * when the rx descriptor is setup again to receive 2910 * another frame. 2911 */ 2912 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2913 0, bf->bf_dmamap->dm_mapsize, 2914 BUS_DMASYNC_POSTREAD); 2915 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2916 bf->bf_m = NULL; 2917 2918 m->m_pkthdr.rcvif = ifp; 2919 len = ds->ds_rxstat.rs_datalen; 2920 m->m_pkthdr.len = m->m_len = len; 2921 2922 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2923 2924 #if NBPFILTER > 0 2925 if (sc->sc_drvbpf) { 2926 u_int8_t rix; 2927 2928 /* 2929 * Discard anything shorter than an ack or cts. 2930 */ 2931 if (len < IEEE80211_ACK_LEN) { 2932 DPRINTF(sc, ATH_DEBUG_RECV, 2933 "%s: runt packet %d\n", 2934 __func__, len); 2935 sc->sc_stats.ast_rx_tooshort++; 2936 m_freem(m); 2937 goto rx_next; 2938 } 2939 rix = ds->ds_rxstat.rs_rate; 2940 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2941 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2942 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2943 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2944 /* XXX TSF */ 2945 2946 bpf_mtap2(sc->sc_drvbpf, 2947 &sc->sc_rx_th, sc->sc_rx_th_len, m); 2948 } 2949 #endif 2950 2951 /* 2952 * From this point on we assume the frame is at least 2953 * as large as ieee80211_frame_min; verify that. 2954 */ 2955 if (len < IEEE80211_MIN_LEN) { 2956 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2957 __func__, len); 2958 sc->sc_stats.ast_rx_tooshort++; 2959 m_freem(m); 2960 goto rx_next; 2961 } 2962 2963 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2964 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2965 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2966 ds->ds_rxstat.rs_rssi); 2967 } 2968 2969 m_adj(m, -IEEE80211_CRC_LEN); 2970 2971 /* 2972 * Locate the node for sender, track state, and then 2973 * pass the (referenced) node up to the 802.11 layer 2974 * for its use. 2975 */ 2976 ni = ieee80211_find_rxnode_withkey(ic, 2977 mtod(m, const struct ieee80211_frame_min *), 2978 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 2979 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 2980 /* 2981 * Track rx rssi and do any rx antenna management. 2982 */ 2983 an = ATH_NODE(ni); 2984 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2985 /* 2986 * Send frame up for processing. 2987 */ 2988 type = ieee80211_input(ic, m, ni, 2989 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2990 ieee80211_free_node(ni); 2991 if (sc->sc_diversity) { 2992 /* 2993 * When using fast diversity, change the default rx 2994 * antenna if diversity chooses the other antenna 3 2995 * times in a row. 2996 */ 2997 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2998 if (++sc->sc_rxotherant >= 3) 2999 ath_setdefantenna(sc, 3000 ds->ds_rxstat.rs_antenna); 3001 } else 3002 sc->sc_rxotherant = 0; 3003 } 3004 if (sc->sc_softled) { 3005 /* 3006 * Blink for any data frame. Otherwise do a 3007 * heartbeat-style blink when idle. The latter 3008 * is mainly for station mode where we depend on 3009 * periodic beacon frames to trigger the poll event. 3010 */ 3011 if (type == IEEE80211_FC0_TYPE_DATA) { 3012 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3013 ath_led_event(sc, ATH_LED_RX); 3014 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3015 ath_led_event(sc, ATH_LED_POLL); 3016 } 3017 rx_next: 3018 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3019 } while (ath_rxbuf_init(sc, bf) == 0); 3020 3021 /* rx signal state monitoring */ 3022 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 3023 3024 #ifdef __NetBSD__ 3025 /* XXX Why isn't this necessary in FreeBSD? */ 3026 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3027 ath_start(ifp); 3028 #endif /* __NetBSD__ */ 3029 3030 NET_UNLOCK_GIANT(); /* XXX */ 3031 #undef PA2DESC 3032 } 3033 3034 /* 3035 * Setup a h/w transmit queue. 3036 */ 3037 static struct ath_txq * 3038 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3039 { 3040 #define N(a) (sizeof(a)/sizeof(a[0])) 3041 struct ath_hal *ah = sc->sc_ah; 3042 HAL_TXQ_INFO qi; 3043 int qnum; 3044 3045 memset(&qi, 0, sizeof(qi)); 3046 qi.tqi_subtype = subtype; 3047 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3048 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3049 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3050 /* 3051 * Enable interrupts only for EOL and DESC conditions. 3052 * We mark tx descriptors to receive a DESC interrupt 3053 * when a tx queue gets deep; otherwise waiting for the 3054 * EOL to reap descriptors. Note that this is done to 3055 * reduce interrupt load and this only defers reaping 3056 * descriptors, never transmitting frames. Aside from 3057 * reducing interrupts this also permits more concurrency. 3058 * The only potential downside is if the tx queue backs 3059 * up in which case the top half of the kernel may backup 3060 * due to a lack of tx descriptors. 3061 */ 3062 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 3063 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3064 if (qnum == -1) { 3065 /* 3066 * NB: don't print a message, this happens 3067 * normally on parts with too few tx queues 3068 */ 3069 return NULL; 3070 } 3071 if (qnum >= N(sc->sc_txq)) { 3072 device_printf(sc->sc_dev, 3073 "hal qnum %u out of range, max %zu!\n", 3074 qnum, N(sc->sc_txq)); 3075 ath_hal_releasetxqueue(ah, qnum); 3076 return NULL; 3077 } 3078 if (!ATH_TXQ_SETUP(sc, qnum)) { 3079 struct ath_txq *txq = &sc->sc_txq[qnum]; 3080 3081 txq->axq_qnum = qnum; 3082 txq->axq_depth = 0; 3083 txq->axq_intrcnt = 0; 3084 txq->axq_link = NULL; 3085 STAILQ_INIT(&txq->axq_q); 3086 ATH_TXQ_LOCK_INIT(sc, txq); 3087 sc->sc_txqsetup |= 1<<qnum; 3088 } 3089 return &sc->sc_txq[qnum]; 3090 #undef N 3091 } 3092 3093 /* 3094 * Setup a hardware data transmit queue for the specified 3095 * access control. The hal may not support all requested 3096 * queues in which case it will return a reference to a 3097 * previously setup queue. We record the mapping from ac's 3098 * to h/w queues for use by ath_tx_start and also track 3099 * the set of h/w queues being used to optimize work in the 3100 * transmit interrupt handler and related routines. 3101 */ 3102 static int 3103 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3104 { 3105 #define N(a) (sizeof(a)/sizeof(a[0])) 3106 struct ath_txq *txq; 3107 3108 if (ac >= N(sc->sc_ac2q)) { 3109 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3110 ac, N(sc->sc_ac2q)); 3111 return 0; 3112 } 3113 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3114 if (txq != NULL) { 3115 sc->sc_ac2q[ac] = txq; 3116 return 1; 3117 } else 3118 return 0; 3119 #undef N 3120 } 3121 3122 /* 3123 * Update WME parameters for a transmit queue. 3124 */ 3125 static int 3126 ath_txq_update(struct ath_softc *sc, int ac) 3127 { 3128 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3129 #define ATH_TXOP_TO_US(v) (v<<5) 3130 struct ieee80211com *ic = &sc->sc_ic; 3131 struct ath_txq *txq = sc->sc_ac2q[ac]; 3132 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3133 struct ath_hal *ah = sc->sc_ah; 3134 HAL_TXQ_INFO qi; 3135 3136 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3137 qi.tqi_aifs = wmep->wmep_aifsn; 3138 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3139 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3140 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3141 3142 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3143 device_printf(sc->sc_dev, "unable to update hardware queue " 3144 "parameters for %s traffic!\n", 3145 ieee80211_wme_acnames[ac]); 3146 return 0; 3147 } else { 3148 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3149 return 1; 3150 } 3151 #undef ATH_TXOP_TO_US 3152 #undef ATH_EXPONENT_TO_VALUE 3153 } 3154 3155 /* 3156 * Callback from the 802.11 layer to update WME parameters. 3157 */ 3158 static int 3159 ath_wme_update(struct ieee80211com *ic) 3160 { 3161 struct ath_softc *sc = ic->ic_ifp->if_softc; 3162 3163 return !ath_txq_update(sc, WME_AC_BE) || 3164 !ath_txq_update(sc, WME_AC_BK) || 3165 !ath_txq_update(sc, WME_AC_VI) || 3166 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3167 } 3168 3169 /* 3170 * Reclaim resources for a setup queue. 3171 */ 3172 static void 3173 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3174 { 3175 3176 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3177 ATH_TXQ_LOCK_DESTROY(txq); 3178 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3179 } 3180 3181 /* 3182 * Reclaim all tx queue resources. 3183 */ 3184 static void 3185 ath_tx_cleanup(struct ath_softc *sc) 3186 { 3187 int i; 3188 3189 ATH_TXBUF_LOCK_DESTROY(sc); 3190 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3191 if (ATH_TXQ_SETUP(sc, i)) 3192 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3193 } 3194 3195 /* 3196 * Defragment an mbuf chain, returning at most maxfrags separate 3197 * mbufs+clusters. If this is not possible NULL is returned and 3198 * the original mbuf chain is left in it's present (potentially 3199 * modified) state. We use two techniques: collapsing consecutive 3200 * mbufs and replacing consecutive mbufs by a cluster. 3201 */ 3202 static struct mbuf * 3203 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3204 { 3205 struct mbuf *m, *n, *n2, **prev; 3206 u_int curfrags; 3207 3208 /* 3209 * Calculate the current number of frags. 3210 */ 3211 curfrags = 0; 3212 for (m = m0; m != NULL; m = m->m_next) 3213 curfrags++; 3214 /* 3215 * First, try to collapse mbufs. Note that we always collapse 3216 * towards the front so we don't need to deal with moving the 3217 * pkthdr. This may be suboptimal if the first mbuf has much 3218 * less data than the following. 3219 */ 3220 m = m0; 3221 again: 3222 for (;;) { 3223 n = m->m_next; 3224 if (n == NULL) 3225 break; 3226 if ((m->m_flags & M_RDONLY) == 0 && 3227 n->m_len < M_TRAILINGSPACE(m)) { 3228 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3229 n->m_len); 3230 m->m_len += n->m_len; 3231 m->m_next = n->m_next; 3232 m_free(n); 3233 if (--curfrags <= maxfrags) 3234 return m0; 3235 } else 3236 m = n; 3237 } 3238 KASSERT(maxfrags > 1, 3239 ("maxfrags %u, but normal collapse failed", maxfrags)); 3240 /* 3241 * Collapse consecutive mbufs to a cluster. 3242 */ 3243 prev = &m0->m_next; /* NB: not the first mbuf */ 3244 while ((n = *prev) != NULL) { 3245 if ((n2 = n->m_next) != NULL && 3246 n->m_len + n2->m_len < MCLBYTES) { 3247 m = m_getcl(how, MT_DATA, 0); 3248 if (m == NULL) 3249 goto bad; 3250 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3251 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3252 n2->m_len); 3253 m->m_len = n->m_len + n2->m_len; 3254 m->m_next = n2->m_next; 3255 *prev = m; 3256 m_free(n); 3257 m_free(n2); 3258 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3259 return m0; 3260 /* 3261 * Still not there, try the normal collapse 3262 * again before we allocate another cluster. 3263 */ 3264 goto again; 3265 } 3266 prev = &n->m_next; 3267 } 3268 /* 3269 * No place where we can collapse to a cluster; punt. 3270 * This can occur if, for example, you request 2 frags 3271 * but the packet requires that both be clusters (we 3272 * never reallocate the first mbuf to avoid moving the 3273 * packet header). 3274 */ 3275 bad: 3276 return NULL; 3277 } 3278 3279 static int 3280 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3281 struct mbuf *m0) 3282 { 3283 #define CTS_DURATION \ 3284 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE) 3285 #define updateCTSForBursting(_ah, _ds, _txq) \ 3286 ath_hal_updateCTSForBursting(_ah, _ds, \ 3287 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ 3288 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ 3289 txopLimit, CTS_DURATION) 3290 struct ieee80211com *ic = &sc->sc_ic; 3291 struct ath_hal *ah = sc->sc_ah; 3292 struct ifnet *ifp = &sc->sc_if; 3293 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3294 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3295 u_int8_t rix, txrate, ctsrate; 3296 u_int8_t cix = 0xff; /* NB: silence compiler */ 3297 struct ath_desc *ds, *ds0; 3298 struct ath_txq *txq; 3299 struct ieee80211_frame *wh; 3300 u_int subtype, flags, ctsduration; 3301 HAL_PKT_TYPE atype; 3302 const HAL_RATE_TABLE *rt; 3303 HAL_BOOL shortPreamble; 3304 struct ath_node *an; 3305 struct mbuf *m; 3306 u_int pri; 3307 3308 wh = mtod(m0, struct ieee80211_frame *); 3309 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3310 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3311 hdrlen = ieee80211_anyhdrsize(wh); 3312 /* 3313 * Packet length must not include any 3314 * pad bytes; deduct them here. 3315 */ 3316 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3317 3318 if (iswep) { 3319 const struct ieee80211_cipher *cip; 3320 struct ieee80211_key *k; 3321 3322 /* 3323 * Construct the 802.11 header+trailer for an encrypted 3324 * frame. The only reason this can fail is because of an 3325 * unknown or unsupported cipher/key type. 3326 */ 3327 k = ieee80211_crypto_encap(ic, ni, m0); 3328 if (k == NULL) { 3329 /* 3330 * This can happen when the key is yanked after the 3331 * frame was queued. Just discard the frame; the 3332 * 802.11 layer counts failures and provides 3333 * debugging/diagnostics. 3334 */ 3335 m_freem(m0); 3336 return EIO; 3337 } 3338 /* 3339 * Adjust the packet + header lengths for the crypto 3340 * additions and calculate the h/w key index. When 3341 * a s/w mic is done the frame will have had any mic 3342 * added to it prior to entry so skb->len above will 3343 * account for it. Otherwise we need to add it to the 3344 * packet length. 3345 */ 3346 cip = k->wk_cipher; 3347 hdrlen += cip->ic_header; 3348 pktlen += cip->ic_header + cip->ic_trailer; 3349 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3350 pktlen += cip->ic_miclen; 3351 keyix = k->wk_keyix; 3352 3353 /* packet header may have moved, reset our local pointer */ 3354 wh = mtod(m0, struct ieee80211_frame *); 3355 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3356 /* 3357 * Use station key cache slot, if assigned. 3358 */ 3359 keyix = ni->ni_ucastkey.wk_keyix; 3360 if (keyix == IEEE80211_KEYIX_NONE) 3361 keyix = HAL_TXKEYIX_INVALID; 3362 } else 3363 keyix = HAL_TXKEYIX_INVALID; 3364 3365 pktlen += IEEE80211_CRC_LEN; 3366 3367 /* 3368 * Load the DMA map so any coalescing is done. This 3369 * also calculates the number of descriptors we need. 3370 */ 3371 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3372 BUS_DMA_NOWAIT); 3373 if (error == EFBIG) { 3374 /* XXX packet requires too many descriptors */ 3375 bf->bf_nseg = ATH_TXDESC+1; 3376 } else if (error != 0) { 3377 sc->sc_stats.ast_tx_busdma++; 3378 m_freem(m0); 3379 return error; 3380 } 3381 /* 3382 * Discard null packets and check for packets that 3383 * require too many TX descriptors. We try to convert 3384 * the latter to a cluster. 3385 */ 3386 if (error == EFBIG) { /* too many desc's, linearize */ 3387 sc->sc_stats.ast_tx_linear++; 3388 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3389 if (m == NULL) { 3390 m_freem(m0); 3391 sc->sc_stats.ast_tx_nombuf++; 3392 return ENOMEM; 3393 } 3394 m0 = m; 3395 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3396 BUS_DMA_NOWAIT); 3397 if (error != 0) { 3398 sc->sc_stats.ast_tx_busdma++; 3399 m_freem(m0); 3400 return error; 3401 } 3402 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3403 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3404 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3405 sc->sc_stats.ast_tx_nodata++; 3406 m_freem(m0); 3407 return EIO; 3408 } 3409 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3410 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3411 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3412 bf->bf_m = m0; 3413 bf->bf_node = ni; /* NB: held reference */ 3414 3415 /* setup descriptors */ 3416 ds = bf->bf_desc; 3417 rt = sc->sc_currates; 3418 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3419 3420 /* 3421 * NB: the 802.11 layer marks whether or not we should 3422 * use short preamble based on the current mode and 3423 * negotiated parameters. 3424 */ 3425 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3426 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3427 shortPreamble = AH_TRUE; 3428 sc->sc_stats.ast_tx_shortpre++; 3429 } else { 3430 shortPreamble = AH_FALSE; 3431 } 3432 3433 an = ATH_NODE(ni); 3434 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3435 /* 3436 * Calculate Atheros packet type from IEEE80211 packet header, 3437 * setup for rate calculations, and select h/w transmit queue. 3438 */ 3439 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3440 case IEEE80211_FC0_TYPE_MGT: 3441 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3442 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3443 atype = HAL_PKT_TYPE_BEACON; 3444 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3445 atype = HAL_PKT_TYPE_PROBE_RESP; 3446 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3447 atype = HAL_PKT_TYPE_ATIM; 3448 else 3449 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3450 rix = 0; /* XXX lowest rate */ 3451 try0 = ATH_TXMAXTRY; 3452 if (shortPreamble) 3453 txrate = an->an_tx_mgtratesp; 3454 else 3455 txrate = an->an_tx_mgtrate; 3456 /* NB: force all management frames to highest queue */ 3457 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3458 /* NB: force all management frames to highest queue */ 3459 pri = WME_AC_VO; 3460 } else 3461 pri = WME_AC_BE; 3462 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3463 break; 3464 case IEEE80211_FC0_TYPE_CTL: 3465 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3466 rix = 0; /* XXX lowest rate */ 3467 try0 = ATH_TXMAXTRY; 3468 if (shortPreamble) 3469 txrate = an->an_tx_mgtratesp; 3470 else 3471 txrate = an->an_tx_mgtrate; 3472 /* NB: force all ctl frames to highest queue */ 3473 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3474 /* NB: force all ctl frames to highest queue */ 3475 pri = WME_AC_VO; 3476 } else 3477 pri = WME_AC_BE; 3478 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3479 break; 3480 case IEEE80211_FC0_TYPE_DATA: 3481 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3482 /* 3483 * Data frames; consult the rate control module for 3484 * unicast frames. Send multicast frames at the 3485 * lowest rate. 3486 */ 3487 if (!ismcast) { 3488 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3489 &rix, &try0, &txrate); 3490 } else { 3491 rix = 0; 3492 try0 = ATH_TXMAXTRY; 3493 txrate = an->an_tx_mgtrate; 3494 } 3495 sc->sc_txrate = txrate; /* for LED blinking */ 3496 /* 3497 * Default all non-QoS traffic to the background queue. 3498 */ 3499 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3500 pri = M_WME_GETAC(m0); 3501 if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3502 flags |= HAL_TXDESC_NOACK; 3503 sc->sc_stats.ast_tx_noack++; 3504 } 3505 } else 3506 pri = WME_AC_BE; 3507 break; 3508 default: 3509 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3510 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3511 /* XXX statistic */ 3512 m_freem(m0); 3513 return EIO; 3514 } 3515 txq = sc->sc_ac2q[pri]; 3516 3517 /* 3518 * When servicing one or more stations in power-save mode 3519 * multicast frames must be buffered until after the beacon. 3520 * We use the CAB queue for that. 3521 */ 3522 if (ismcast && ic->ic_ps_sta) { 3523 txq = sc->sc_cabq; 3524 /* XXX? more bit in 802.11 frame header */ 3525 } 3526 3527 /* 3528 * Calculate miscellaneous flags. 3529 */ 3530 if (ismcast) { 3531 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3532 sc->sc_stats.ast_tx_noack++; 3533 } else if (pktlen > ic->ic_rtsthreshold) { 3534 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3535 cix = rt->info[rix].controlRate; 3536 sc->sc_stats.ast_tx_rts++; 3537 } 3538 3539 /* 3540 * If 802.11g protection is enabled, determine whether 3541 * to use RTS/CTS or just CTS. Note that this is only 3542 * done for OFDM unicast frames. 3543 */ 3544 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3545 rt->info[rix].phy == IEEE80211_T_OFDM && 3546 (flags & HAL_TXDESC_NOACK) == 0) { 3547 /* XXX fragments must use CCK rates w/ protection */ 3548 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3549 flags |= HAL_TXDESC_RTSENA; 3550 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3551 flags |= HAL_TXDESC_CTSENA; 3552 cix = rt->info[sc->sc_protrix].controlRate; 3553 sc->sc_stats.ast_tx_protect++; 3554 } 3555 3556 /* 3557 * Calculate duration. This logically belongs in the 802.11 3558 * layer but it lacks sufficient information to calculate it. 3559 */ 3560 if ((flags & HAL_TXDESC_NOACK) == 0 && 3561 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3562 u_int16_t dur; 3563 /* 3564 * XXX not right with fragmentation. 3565 */ 3566 if (shortPreamble) 3567 dur = rt->info[rix].spAckDuration; 3568 else 3569 dur = rt->info[rix].lpAckDuration; 3570 *(u_int16_t *)wh->i_dur = htole16(dur); 3571 } 3572 3573 /* 3574 * Calculate RTS/CTS rate and duration if needed. 3575 */ 3576 ctsduration = 0; 3577 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3578 /* 3579 * CTS transmit rate is derived from the transmit rate 3580 * by looking in the h/w rate table. We must also factor 3581 * in whether or not a short preamble is to be used. 3582 */ 3583 /* NB: cix is set above where RTS/CTS is enabled */ 3584 KASSERT(cix != 0xff, ("cix not setup")); 3585 ctsrate = rt->info[cix].rateCode; 3586 /* 3587 * Compute the transmit duration based on the frame 3588 * size and the size of an ACK frame. We call into the 3589 * HAL to do the computation since it depends on the 3590 * characteristics of the actual PHY being used. 3591 * 3592 * NB: CTS is assumed the same size as an ACK so we can 3593 * use the precalculated ACK durations. 3594 */ 3595 if (shortPreamble) { 3596 ctsrate |= rt->info[cix].shortPreamble; 3597 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3598 ctsduration += rt->info[cix].spAckDuration; 3599 ctsduration += ath_hal_computetxtime(ah, 3600 rt, pktlen, rix, AH_TRUE); 3601 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3602 ctsduration += rt->info[rix].spAckDuration; 3603 } else { 3604 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3605 ctsduration += rt->info[cix].lpAckDuration; 3606 ctsduration += ath_hal_computetxtime(ah, 3607 rt, pktlen, rix, AH_FALSE); 3608 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3609 ctsduration += rt->info[rix].lpAckDuration; 3610 } 3611 /* 3612 * Must disable multi-rate retry when using RTS/CTS. 3613 */ 3614 try0 = ATH_TXMAXTRY; 3615 } else 3616 ctsrate = 0; 3617 3618 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3619 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3620 sc->sc_hwmap[txrate].ieeerate, -1); 3621 3622 if (ic->ic_rawbpf) 3623 bpf_mtap(ic->ic_rawbpf, m0); 3624 if (sc->sc_drvbpf) { 3625 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3626 if (iswep) 3627 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3628 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3629 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3630 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3631 3632 bpf_mtap2(sc->sc_drvbpf, 3633 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3634 } 3635 3636 /* 3637 * Determine if a tx interrupt should be generated for 3638 * this descriptor. We take a tx interrupt to reap 3639 * descriptors when the h/w hits an EOL condition or 3640 * when the descriptor is specifically marked to generate 3641 * an interrupt. We periodically mark descriptors in this 3642 * way to insure timely replenishing of the supply needed 3643 * for sending frames. Defering interrupts reduces system 3644 * load and potentially allows more concurrent work to be 3645 * done but if done to aggressively can cause senders to 3646 * backup. 3647 * 3648 * NB: use >= to deal with sc_txintrperiod changing 3649 * dynamically through sysctl. 3650 */ 3651 if (flags & HAL_TXDESC_INTREQ) { 3652 txq->axq_intrcnt = 0; 3653 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3654 flags |= HAL_TXDESC_INTREQ; 3655 txq->axq_intrcnt = 0; 3656 } 3657 3658 /* 3659 * Formulate first tx descriptor with tx controls. 3660 */ 3661 /* XXX check return value? */ 3662 ath_hal_setuptxdesc(ah, ds 3663 , pktlen /* packet length */ 3664 , hdrlen /* header length */ 3665 , atype /* Atheros packet type */ 3666 , ni->ni_txpower /* txpower */ 3667 , txrate, try0 /* series 0 rate/tries */ 3668 , keyix /* key cache index */ 3669 , sc->sc_txantenna /* antenna mode */ 3670 , flags /* flags */ 3671 , ctsrate /* rts/cts rate */ 3672 , ctsduration /* rts/cts duration */ 3673 ); 3674 bf->bf_flags = flags; 3675 /* 3676 * Setup the multi-rate retry state only when we're 3677 * going to use it. This assumes ath_hal_setuptxdesc 3678 * initializes the descriptors (so we don't have to) 3679 * when the hardware supports multi-rate retry and 3680 * we don't use it. 3681 */ 3682 if (try0 != ATH_TXMAXTRY) 3683 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3684 3685 /* 3686 * Fillin the remainder of the descriptor info. 3687 */ 3688 ds0 = ds; 3689 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3690 ds->ds_data = bf->bf_segs[i].ds_addr; 3691 if (i == bf->bf_nseg - 1) 3692 ds->ds_link = 0; 3693 else 3694 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3695 ath_hal_filltxdesc(ah, ds 3696 , bf->bf_segs[i].ds_len /* segment length */ 3697 , i == 0 /* first segment */ 3698 , i == bf->bf_nseg - 1 /* last segment */ 3699 , ds0 /* first descriptor */ 3700 ); 3701 DPRINTF(sc, ATH_DEBUG_XMIT, 3702 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3703 __func__, i, ds->ds_link, ds->ds_data, 3704 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3705 } 3706 /* 3707 * Insert the frame on the outbound list and 3708 * pass it on to the hardware. 3709 */ 3710 ATH_TXQ_LOCK(txq); 3711 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 3712 u_int32_t txopLimit = IEEE80211_TXOP_TO_US( 3713 cap->cap_wmeParams[pri].wmep_txopLimit); 3714 /* 3715 * When bursting, potentially extend the CTS duration 3716 * of a previously queued frame to cover this frame 3717 * and not exceed the txopLimit. If that can be done 3718 * then disable RTS/CTS on this frame since it's now 3719 * covered (burst extension). Otherwise we must terminate 3720 * the burst before this frame goes out so as not to 3721 * violate the WME parameters. All this is complicated 3722 * as we need to update the state of packets on the 3723 * (live) hardware queue. The logic is buried in the hal 3724 * because it's highly chip-specific. 3725 */ 3726 if (txopLimit != 0) { 3727 sc->sc_stats.ast_tx_ctsburst++; 3728 if (updateCTSForBursting(ah, ds0, txq) == 0) { 3729 /* 3730 * This frame was not covered by RTS/CTS from 3731 * the previous frame in the burst; update the 3732 * descriptor pointers so this frame is now 3733 * treated as the last frame for extending a 3734 * burst. 3735 */ 3736 txq->axq_lastdsWithCTS = ds0; 3737 /* set gating Desc to final desc */ 3738 txq->axq_gatingds = 3739 (struct ath_desc *)txq->axq_link; 3740 } else 3741 sc->sc_stats.ast_tx_ctsext++; 3742 } 3743 } 3744 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3745 if (txq->axq_link == NULL) { 3746 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3747 DPRINTF(sc, ATH_DEBUG_XMIT, 3748 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3749 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3750 txq->axq_depth); 3751 } else { 3752 *txq->axq_link = bf->bf_daddr; 3753 DPRINTF(sc, ATH_DEBUG_XMIT, 3754 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3755 txq->axq_qnum, txq->axq_link, 3756 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3757 } 3758 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3759 /* 3760 * The CAB queue is started from the SWBA handler since 3761 * frames only go out on DTIM and to avoid possible races. 3762 */ 3763 if (txq != sc->sc_cabq) 3764 ath_hal_txstart(ah, txq->axq_qnum); 3765 ATH_TXQ_UNLOCK(txq); 3766 3767 return 0; 3768 #undef updateCTSForBursting 3769 #undef CTS_DURATION 3770 } 3771 3772 /* 3773 * Process completed xmit descriptors from the specified queue. 3774 */ 3775 static void 3776 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3777 { 3778 struct ath_hal *ah = sc->sc_ah; 3779 struct ieee80211com *ic = &sc->sc_ic; 3780 struct ath_buf *bf; 3781 struct ath_desc *ds, *ds0; 3782 struct ieee80211_node *ni; 3783 struct ath_node *an; 3784 int sr, lr, pri; 3785 HAL_STATUS status; 3786 3787 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3788 __func__, txq->axq_qnum, 3789 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3790 txq->axq_link); 3791 for (;;) { 3792 ATH_TXQ_LOCK(txq); 3793 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3794 bf = STAILQ_FIRST(&txq->axq_q); 3795 if (bf == NULL) { 3796 txq->axq_link = NULL; 3797 ATH_TXQ_UNLOCK(txq); 3798 break; 3799 } 3800 ds0 = &bf->bf_desc[0]; 3801 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3802 status = ath_hal_txprocdesc(ah, ds); 3803 #ifdef AR_DEBUG 3804 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3805 ath_printtxbuf(bf, status == HAL_OK); 3806 #endif 3807 if (status == HAL_EINPROGRESS) { 3808 ATH_TXQ_UNLOCK(txq); 3809 break; 3810 } 3811 if (ds0 == txq->axq_lastdsWithCTS) 3812 txq->axq_lastdsWithCTS = NULL; 3813 if (ds == txq->axq_gatingds) 3814 txq->axq_gatingds = NULL; 3815 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3816 ATH_TXQ_UNLOCK(txq); 3817 3818 ni = bf->bf_node; 3819 if (ni != NULL) { 3820 an = ATH_NODE(ni); 3821 if (ds->ds_txstat.ts_status == 0) { 3822 u_int8_t txant = ds->ds_txstat.ts_antenna; 3823 sc->sc_stats.ast_ant_tx[txant]++; 3824 sc->sc_ant_tx[txant]++; 3825 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3826 sc->sc_stats.ast_tx_altrate++; 3827 sc->sc_stats.ast_tx_rssi = 3828 ds->ds_txstat.ts_rssi; 3829 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3830 ds->ds_txstat.ts_rssi); 3831 pri = M_WME_GETAC(bf->bf_m); 3832 if (pri >= WME_AC_VO) 3833 ic->ic_wme.wme_hipri_traffic++; 3834 ni->ni_inact = ni->ni_inact_reload; 3835 } else { 3836 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3837 sc->sc_stats.ast_tx_xretries++; 3838 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3839 sc->sc_stats.ast_tx_fifoerr++; 3840 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3841 sc->sc_stats.ast_tx_filtered++; 3842 } 3843 sr = ds->ds_txstat.ts_shortretry; 3844 lr = ds->ds_txstat.ts_longretry; 3845 sc->sc_stats.ast_tx_shortretry += sr; 3846 sc->sc_stats.ast_tx_longretry += lr; 3847 /* 3848 * Hand the descriptor to the rate control algorithm. 3849 */ 3850 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3851 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) 3852 ath_rate_tx_complete(sc, an, ds, ds0); 3853 /* 3854 * Reclaim reference to node. 3855 * 3856 * NB: the node may be reclaimed here if, for example 3857 * this is a DEAUTH message that was sent and the 3858 * node was timed out due to inactivity. 3859 */ 3860 ieee80211_free_node(ni); 3861 } 3862 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3863 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3864 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3865 m_freem(bf->bf_m); 3866 bf->bf_m = NULL; 3867 bf->bf_node = NULL; 3868 3869 ATH_TXBUF_LOCK(sc); 3870 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3871 ATH_TXBUF_UNLOCK(sc); 3872 } 3873 } 3874 3875 /* 3876 * Deferred processing of transmit interrupt; special-cased 3877 * for a single hardware transmit queue (e.g. 5210 and 5211). 3878 */ 3879 static void 3880 ath_tx_proc_q0(void *arg, int npending) 3881 { 3882 struct ath_softc *sc = arg; 3883 struct ifnet *ifp = &sc->sc_if; 3884 3885 ath_tx_processq(sc, &sc->sc_txq[0]); 3886 ath_tx_processq(sc, sc->sc_cabq); 3887 ifp->if_flags &= ~IFF_OACTIVE; 3888 sc->sc_tx_timer = 0; 3889 3890 if (sc->sc_softled) 3891 ath_led_event(sc, ATH_LED_TX); 3892 3893 ath_start(ifp); 3894 } 3895 3896 /* 3897 * Deferred processing of transmit interrupt; special-cased 3898 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3899 */ 3900 static void 3901 ath_tx_proc_q0123(void *arg, int npending) 3902 { 3903 struct ath_softc *sc = arg; 3904 struct ifnet *ifp = &sc->sc_if; 3905 3906 /* 3907 * Process each active queue. 3908 */ 3909 ath_tx_processq(sc, &sc->sc_txq[0]); 3910 ath_tx_processq(sc, &sc->sc_txq[1]); 3911 ath_tx_processq(sc, &sc->sc_txq[2]); 3912 ath_tx_processq(sc, &sc->sc_txq[3]); 3913 ath_tx_processq(sc, sc->sc_cabq); 3914 3915 ifp->if_flags &= ~IFF_OACTIVE; 3916 sc->sc_tx_timer = 0; 3917 3918 if (sc->sc_softled) 3919 ath_led_event(sc, ATH_LED_TX); 3920 3921 ath_start(ifp); 3922 } 3923 3924 /* 3925 * Deferred processing of transmit interrupt. 3926 */ 3927 static void 3928 ath_tx_proc(void *arg, int npending) 3929 { 3930 struct ath_softc *sc = arg; 3931 struct ifnet *ifp = &sc->sc_if; 3932 int i; 3933 3934 /* 3935 * Process each active queue. 3936 */ 3937 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3938 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3939 if (ATH_TXQ_SETUP(sc, i)) 3940 ath_tx_processq(sc, &sc->sc_txq[i]); 3941 3942 ifp->if_flags &= ~IFF_OACTIVE; 3943 sc->sc_tx_timer = 0; 3944 3945 if (sc->sc_softled) 3946 ath_led_event(sc, ATH_LED_TX); 3947 3948 ath_start(ifp); 3949 } 3950 3951 static void 3952 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3953 { 3954 struct ath_hal *ah = sc->sc_ah; 3955 struct ieee80211_node *ni; 3956 struct ath_buf *bf; 3957 3958 /* 3959 * NB: this assumes output has been stopped and 3960 * we do not need to block ath_tx_tasklet 3961 */ 3962 for (;;) { 3963 ATH_TXQ_LOCK(txq); 3964 bf = STAILQ_FIRST(&txq->axq_q); 3965 if (bf == NULL) { 3966 txq->axq_link = NULL; 3967 ATH_TXQ_UNLOCK(txq); 3968 break; 3969 } 3970 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3971 ATH_TXQ_UNLOCK(txq); 3972 #ifdef AR_DEBUG 3973 if (sc->sc_debug & ATH_DEBUG_RESET) 3974 ath_printtxbuf(bf, 3975 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3976 #endif /* AR_DEBUG */ 3977 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3978 m_freem(bf->bf_m); 3979 bf->bf_m = NULL; 3980 ni = bf->bf_node; 3981 bf->bf_node = NULL; 3982 if (ni != NULL) { 3983 /* 3984 * Reclaim node reference. 3985 */ 3986 ieee80211_free_node(ni); 3987 } 3988 ATH_TXBUF_LOCK(sc); 3989 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3990 ATH_TXBUF_UNLOCK(sc); 3991 } 3992 } 3993 3994 static void 3995 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3996 { 3997 struct ath_hal *ah = sc->sc_ah; 3998 3999 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4000 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4001 __func__, txq->axq_qnum, 4002 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4003 txq->axq_link); 4004 } 4005 4006 /* 4007 * Drain the transmit queues and reclaim resources. 4008 */ 4009 static void 4010 ath_draintxq(struct ath_softc *sc) 4011 { 4012 struct ath_hal *ah = sc->sc_ah; 4013 struct ifnet *ifp = &sc->sc_if; 4014 int i; 4015 4016 /* XXX return value */ 4017 if (!sc->sc_invalid) { 4018 /* don't touch the hardware if marked invalid */ 4019 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4020 DPRINTF(sc, ATH_DEBUG_RESET, 4021 "%s: beacon queue %p\n", __func__, 4022 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4023 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4024 if (ATH_TXQ_SETUP(sc, i)) 4025 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4026 } 4027 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4028 if (ATH_TXQ_SETUP(sc, i)) 4029 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4030 ifp->if_flags &= ~IFF_OACTIVE; 4031 sc->sc_tx_timer = 0; 4032 } 4033 4034 /* 4035 * Disable the receive h/w in preparation for a reset. 4036 */ 4037 static void 4038 ath_stoprecv(struct ath_softc *sc) 4039 { 4040 #define PA2DESC(_sc, _pa) \ 4041 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4042 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4043 struct ath_hal *ah = sc->sc_ah; 4044 4045 ath_hal_stoppcurecv(ah); /* disable PCU */ 4046 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4047 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4048 DELAY(3000); /* 3ms is long enough for 1 frame */ 4049 #ifdef AR_DEBUG 4050 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4051 struct ath_buf *bf; 4052 4053 printf("%s: rx queue %p, link %p\n", __func__, 4054 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4055 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4056 struct ath_desc *ds = bf->bf_desc; 4057 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4058 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4059 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4060 ath_printrxbuf(bf, status == HAL_OK); 4061 } 4062 } 4063 #endif 4064 sc->sc_rxlink = NULL; /* just in case */ 4065 #undef PA2DESC 4066 } 4067 4068 /* 4069 * Enable the receive h/w following a reset. 4070 */ 4071 static int 4072 ath_startrecv(struct ath_softc *sc) 4073 { 4074 struct ath_hal *ah = sc->sc_ah; 4075 struct ath_buf *bf; 4076 4077 sc->sc_rxlink = NULL; 4078 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4079 int error = ath_rxbuf_init(sc, bf); 4080 if (error != 0) { 4081 DPRINTF(sc, ATH_DEBUG_RECV, 4082 "%s: ath_rxbuf_init failed %d\n", 4083 __func__, error); 4084 return error; 4085 } 4086 } 4087 4088 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4089 ath_hal_putrxbuf(ah, bf->bf_daddr); 4090 ath_hal_rxena(ah); /* enable recv descriptors */ 4091 ath_mode_init(sc); /* set filters, etc. */ 4092 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4093 return 0; 4094 } 4095 4096 /* 4097 * Update internal state after a channel change. 4098 */ 4099 static void 4100 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4101 { 4102 struct ieee80211com *ic = &sc->sc_ic; 4103 enum ieee80211_phymode mode; 4104 u_int16_t flags; 4105 4106 /* 4107 * Change channels and update the h/w rate map 4108 * if we're switching; e.g. 11a to 11b/g. 4109 */ 4110 mode = ieee80211_chan2mode(ic, chan); 4111 if (mode != sc->sc_curmode) 4112 ath_setcurmode(sc, mode); 4113 /* 4114 * Update BPF state. NB: ethereal et. al. don't handle 4115 * merged flags well so pick a unique mode for their use. 4116 */ 4117 if (IEEE80211_IS_CHAN_A(chan)) 4118 flags = IEEE80211_CHAN_A; 4119 /* XXX 11g schizophrenia */ 4120 else if (IEEE80211_IS_CHAN_G(chan) || 4121 IEEE80211_IS_CHAN_PUREG(chan)) 4122 flags = IEEE80211_CHAN_G; 4123 else 4124 flags = IEEE80211_CHAN_B; 4125 if (IEEE80211_IS_CHAN_T(chan)) 4126 flags |= IEEE80211_CHAN_TURBO; 4127 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4128 htole16(chan->ic_freq); 4129 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4130 htole16(flags); 4131 } 4132 4133 /* 4134 * Set/change channels. If the channel is really being changed, 4135 * it's done by reseting the chip. To accomplish this we must 4136 * first cleanup any pending DMA, then restart stuff after a la 4137 * ath_init. 4138 */ 4139 static int 4140 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4141 { 4142 struct ath_hal *ah = sc->sc_ah; 4143 struct ieee80211com *ic = &sc->sc_ic; 4144 HAL_CHANNEL hchan; 4145 4146 /* 4147 * Convert to a HAL channel description with 4148 * the flags constrained to reflect the current 4149 * operating mode. 4150 */ 4151 hchan.channel = chan->ic_freq; 4152 hchan.channelFlags = ath_chan2flags(ic, chan); 4153 4154 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 4155 __func__, 4156 ath_hal_mhz2ieee(sc->sc_curchan.channel, 4157 sc->sc_curchan.channelFlags), 4158 sc->sc_curchan.channel, 4159 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 4160 if (hchan.channel != sc->sc_curchan.channel || 4161 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4162 HAL_STATUS status; 4163 4164 /* 4165 * To switch channels clear any pending DMA operations; 4166 * wait long enough for the RX fifo to drain, reset the 4167 * hardware at the new frequency, and then re-enable 4168 * the relevant bits of the h/w. 4169 */ 4170 ath_hal_intrset(ah, 0); /* disable interrupts */ 4171 ath_draintxq(sc); /* clear pending tx frames */ 4172 ath_stoprecv(sc); /* turn off frame recv */ 4173 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4174 if_printf(&sc->sc_if, "ath_chan_set: unable to reset " 4175 "channel %u (%u Mhz)\n", 4176 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 4177 return EIO; 4178 } 4179 sc->sc_curchan = hchan; 4180 ath_update_txpow(sc); /* update tx power state */ 4181 sc->sc_diversity = ath_hal_getdiversity(ah); 4182 4183 /* 4184 * Re-enable rx framework. 4185 */ 4186 if (ath_startrecv(sc) != 0) { 4187 if_printf(&sc->sc_if, 4188 "ath_chan_set: unable to restart recv logic\n"); 4189 return EIO; 4190 } 4191 4192 /* 4193 * Change channels and update the h/w rate map 4194 * if we're switching; e.g. 11a to 11b/g. 4195 */ 4196 ic->ic_ibss_chan = chan; 4197 ath_chan_change(sc, chan); 4198 4199 /* 4200 * Re-enable interrupts. 4201 */ 4202 ath_hal_intrset(ah, sc->sc_imask); 4203 } 4204 return 0; 4205 } 4206 4207 static void 4208 ath_next_scan(void *arg) 4209 { 4210 struct ath_softc *sc = arg; 4211 struct ieee80211com *ic = &sc->sc_ic; 4212 int s; 4213 4214 /* don't call ath_start w/o network interrupts blocked */ 4215 s = splnet(); 4216 4217 if (ic->ic_state == IEEE80211_S_SCAN) 4218 ieee80211_next_scan(ic); 4219 splx(s); 4220 } 4221 4222 /* 4223 * Periodically recalibrate the PHY to account 4224 * for temperature/environment changes. 4225 */ 4226 static void 4227 ath_calibrate(void *arg) 4228 { 4229 struct ath_softc *sc = arg; 4230 struct ath_hal *ah = sc->sc_ah; 4231 4232 sc->sc_stats.ast_per_cal++; 4233 4234 ATH_LOCK(sc); 4235 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 4236 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 4237 4238 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4239 /* 4240 * Rfgain is out of bounds, reset the chip 4241 * to load new gain values. 4242 */ 4243 sc->sc_stats.ast_per_rfgain++; 4244 ath_reset(&sc->sc_if); 4245 } 4246 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 4247 DPRINTF(sc, ATH_DEBUG_ANY, 4248 "%s: calibration of channel %u failed\n", 4249 __func__, sc->sc_curchan.channel); 4250 sc->sc_stats.ast_per_calfail++; 4251 } 4252 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 4253 ATH_UNLOCK(sc); 4254 } 4255 4256 static int 4257 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4258 { 4259 struct ifnet *ifp = ic->ic_ifp; 4260 struct ath_softc *sc = ifp->if_softc; 4261 struct ath_hal *ah = sc->sc_ah; 4262 struct ieee80211_node *ni; 4263 int i, error; 4264 const u_int8_t *bssid; 4265 u_int32_t rfilt; 4266 static const HAL_LED_STATE leds[] = { 4267 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4268 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4269 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4270 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4271 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4272 }; 4273 4274 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4275 ieee80211_state_name[ic->ic_state], 4276 ieee80211_state_name[nstate]); 4277 4278 callout_stop(&sc->sc_scan_ch); 4279 callout_stop(&sc->sc_cal_ch); 4280 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4281 4282 if (nstate == IEEE80211_S_INIT) { 4283 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4284 /* 4285 * NB: disable interrupts so we don't rx frames. 4286 */ 4287 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4288 /* 4289 * Notify the rate control algorithm. 4290 */ 4291 ath_rate_newstate(sc, nstate); 4292 goto done; 4293 } 4294 ni = ic->ic_bss; 4295 error = ath_chan_set(sc, ic->ic_curchan); 4296 if (error != 0) 4297 goto bad; 4298 rfilt = ath_calcrxfilter(sc, nstate); 4299 if (nstate == IEEE80211_S_SCAN) 4300 bssid = ifp->if_broadcastaddr; 4301 else 4302 bssid = ni->ni_bssid; 4303 ath_hal_setrxfilter(ah, rfilt); 4304 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4305 __func__, rfilt, ether_sprintf(bssid)); 4306 4307 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4308 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4309 else 4310 ath_hal_setassocid(ah, bssid, 0); 4311 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4312 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4313 if (ath_hal_keyisvalid(ah, i)) 4314 ath_hal_keysetmac(ah, i, bssid); 4315 } 4316 4317 /* 4318 * Notify the rate control algorithm so rates 4319 * are setup should ath_beacon_alloc be called. 4320 */ 4321 ath_rate_newstate(sc, nstate); 4322 4323 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4324 /* nothing to do */; 4325 } else if (nstate == IEEE80211_S_RUN) { 4326 DPRINTF(sc, ATH_DEBUG_STATE, 4327 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4328 "capinfo=0x%04x chan=%d\n" 4329 , __func__ 4330 , ic->ic_flags 4331 , ni->ni_intval 4332 , ether_sprintf(ni->ni_bssid) 4333 , ni->ni_capinfo 4334 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4335 4336 switch (ic->ic_opmode) { 4337 case IEEE80211_M_HOSTAP: 4338 case IEEE80211_M_IBSS: 4339 /* 4340 * Allocate and setup the beacon frame. 4341 * 4342 * Stop any previous beacon DMA. This may be 4343 * necessary, for example, when an ibss merge 4344 * causes reconfiguration; there will be a state 4345 * transition from RUN->RUN that means we may 4346 * be called with beacon transmission active. 4347 */ 4348 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4349 ath_beacon_free(sc); 4350 error = ath_beacon_alloc(sc, ni); 4351 if (error != 0) 4352 goto bad; 4353 break; 4354 case IEEE80211_M_STA: 4355 /* 4356 * Allocate a key cache slot to the station. 4357 */ 4358 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4359 sc->sc_hasclrkey && 4360 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4361 ath_setup_stationkey(ni); 4362 break; 4363 default: 4364 break; 4365 } 4366 4367 /* 4368 * Configure the beacon and sleep timers. 4369 */ 4370 ath_beacon_config(sc); 4371 } else { 4372 ath_hal_intrset(ah, 4373 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4374 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4375 } 4376 done: 4377 /* 4378 * Invoke the parent method to complete the work. 4379 */ 4380 error = sc->sc_newstate(ic, nstate, arg); 4381 /* 4382 * Finally, start any timers. 4383 */ 4384 if (nstate == IEEE80211_S_RUN) { 4385 /* start periodic recalibration timer */ 4386 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4387 ath_calibrate, sc); 4388 } else if (nstate == IEEE80211_S_SCAN) { 4389 /* start ap/neighbor scan timer */ 4390 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4391 ath_next_scan, sc); 4392 } 4393 bad: 4394 return error; 4395 } 4396 4397 /* 4398 * Allocate a key cache slot to the station so we can 4399 * setup a mapping from key index to node. The key cache 4400 * slot is needed for managing antenna state and for 4401 * compression when stations do not use crypto. We do 4402 * it uniliaterally here; if crypto is employed this slot 4403 * will be reassigned. 4404 */ 4405 static void 4406 ath_setup_stationkey(struct ieee80211_node *ni) 4407 { 4408 struct ieee80211com *ic = ni->ni_ic; 4409 struct ath_softc *sc = ic->ic_ifp->if_softc; 4410 ieee80211_keyix keyix, rxkeyix; 4411 4412 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4413 /* 4414 * Key cache is full; we'll fall back to doing 4415 * the more expensive lookup in software. Note 4416 * this also means no h/w compression. 4417 */ 4418 /* XXX msg+statistic */ 4419 } else { 4420 /* XXX locking? */ 4421 ni->ni_ucastkey.wk_keyix = keyix; 4422 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4423 /* NB: this will create a pass-thru key entry */ 4424 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4425 } 4426 } 4427 4428 /* 4429 * Setup driver-specific state for a newly associated node. 4430 * Note that we're called also on a re-associate, the isnew 4431 * param tells us if this is the first time or not. 4432 */ 4433 static void 4434 ath_newassoc(struct ieee80211_node *ni, int isnew) 4435 { 4436 struct ieee80211com *ic = ni->ni_ic; 4437 struct ath_softc *sc = ic->ic_ifp->if_softc; 4438 4439 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4440 if (isnew && 4441 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4442 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4443 ("new assoc with a unicast key already setup (keyix %u)", 4444 ni->ni_ucastkey.wk_keyix)); 4445 ath_setup_stationkey(ni); 4446 } 4447 } 4448 4449 static int 4450 ath_getchannels(struct ath_softc *sc, u_int cc, 4451 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4452 { 4453 struct ieee80211com *ic = &sc->sc_ic; 4454 struct ifnet *ifp = &sc->sc_if; 4455 struct ath_hal *ah = sc->sc_ah; 4456 HAL_CHANNEL *chans; 4457 int i, ix, nchan; 4458 4459 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4460 M_TEMP, M_NOWAIT); 4461 if (chans == NULL) { 4462 if_printf(ifp, "unable to allocate channel table\n"); 4463 return ENOMEM; 4464 } 4465 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4466 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4467 u_int32_t rd; 4468 4469 ath_hal_getregdomain(ah, &rd); 4470 if_printf(ifp, "unable to collect channel list from hal; " 4471 "regdomain likely %u country code %u\n", rd, cc); 4472 free(chans, M_TEMP); 4473 return EINVAL; 4474 } 4475 4476 /* 4477 * Convert HAL channels to ieee80211 ones and insert 4478 * them in the table according to their channel number. 4479 */ 4480 for (i = 0; i < nchan; i++) { 4481 HAL_CHANNEL *c = &chans[i]; 4482 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4483 if (ix > IEEE80211_CHAN_MAX) { 4484 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4485 ix, c->channel, c->channelFlags); 4486 continue; 4487 } 4488 DPRINTF(sc, ATH_DEBUG_ANY, 4489 "%s: HAL channel %d/%d freq %d flags %#04x idx %d\n", 4490 sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags, 4491 ix); 4492 /* NB: flags are known to be compatible */ 4493 if (ic->ic_channels[ix].ic_freq == 0) { 4494 ic->ic_channels[ix].ic_freq = c->channel; 4495 ic->ic_channels[ix].ic_flags = c->channelFlags; 4496 } else { 4497 /* channels overlap; e.g. 11g and 11b */ 4498 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4499 } 4500 } 4501 free(chans, M_TEMP); 4502 return 0; 4503 } 4504 4505 static void 4506 ath_led_done(void *arg) 4507 { 4508 struct ath_softc *sc = arg; 4509 4510 sc->sc_blinking = 0; 4511 } 4512 4513 /* 4514 * Turn the LED off: flip the pin and then set a timer so no 4515 * update will happen for the specified duration. 4516 */ 4517 static void 4518 ath_led_off(void *arg) 4519 { 4520 struct ath_softc *sc = arg; 4521 4522 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4523 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4524 } 4525 4526 /* 4527 * Blink the LED according to the specified on/off times. 4528 */ 4529 static void 4530 ath_led_blink(struct ath_softc *sc, int on, int off) 4531 { 4532 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4533 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4534 sc->sc_blinking = 1; 4535 sc->sc_ledoff = off; 4536 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4537 } 4538 4539 static void 4540 ath_led_event(struct ath_softc *sc, int event) 4541 { 4542 4543 sc->sc_ledevent = ticks; /* time of last event */ 4544 if (sc->sc_blinking) /* don't interrupt active blink */ 4545 return; 4546 switch (event) { 4547 case ATH_LED_POLL: 4548 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4549 sc->sc_hwmap[0].ledoff); 4550 break; 4551 case ATH_LED_TX: 4552 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4553 sc->sc_hwmap[sc->sc_txrate].ledoff); 4554 break; 4555 case ATH_LED_RX: 4556 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4557 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4558 break; 4559 } 4560 } 4561 4562 static void 4563 ath_update_txpow(struct ath_softc *sc) 4564 { 4565 struct ieee80211com *ic = &sc->sc_ic; 4566 struct ath_hal *ah = sc->sc_ah; 4567 u_int32_t txpow; 4568 4569 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4570 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4571 /* read back in case value is clamped */ 4572 ath_hal_gettxpowlimit(ah, &txpow); 4573 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4574 } 4575 /* 4576 * Fetch max tx power level for status requests. 4577 */ 4578 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4579 ic->ic_bss->ni_txpower = txpow; 4580 } 4581 4582 static int 4583 ath_rate_setup(struct ath_softc *sc, u_int mode) 4584 { 4585 struct ath_hal *ah = sc->sc_ah; 4586 struct ieee80211com *ic = &sc->sc_ic; 4587 const HAL_RATE_TABLE *rt; 4588 struct ieee80211_rateset *rs; 4589 int i, maxrates; 4590 4591 switch (mode) { 4592 case IEEE80211_MODE_11A: 4593 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4594 break; 4595 case IEEE80211_MODE_11B: 4596 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4597 break; 4598 case IEEE80211_MODE_11G: 4599 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4600 break; 4601 case IEEE80211_MODE_TURBO_A: 4602 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4603 break; 4604 case IEEE80211_MODE_TURBO_G: 4605 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4606 break; 4607 default: 4608 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4609 __func__, mode); 4610 return 0; 4611 } 4612 rt = sc->sc_rates[mode]; 4613 if (rt == NULL) 4614 return 0; 4615 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4616 DPRINTF(sc, ATH_DEBUG_ANY, 4617 "%s: rate table too small (%u > %u)\n", 4618 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4619 maxrates = IEEE80211_RATE_MAXSIZE; 4620 } else 4621 maxrates = rt->rateCount; 4622 rs = &ic->ic_sup_rates[mode]; 4623 for (i = 0; i < maxrates; i++) 4624 rs->rs_rates[i] = rt->info[i].dot11Rate; 4625 rs->rs_nrates = maxrates; 4626 return 1; 4627 } 4628 4629 static void 4630 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4631 { 4632 #define N(a) (sizeof(a)/sizeof(a[0])) 4633 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4634 static const struct { 4635 u_int rate; /* tx/rx 802.11 rate */ 4636 u_int16_t timeOn; /* LED on time (ms) */ 4637 u_int16_t timeOff; /* LED off time (ms) */ 4638 } blinkrates[] = { 4639 { 108, 40, 10 }, 4640 { 96, 44, 11 }, 4641 { 72, 50, 13 }, 4642 { 48, 57, 14 }, 4643 { 36, 67, 16 }, 4644 { 24, 80, 20 }, 4645 { 22, 100, 25 }, 4646 { 18, 133, 34 }, 4647 { 12, 160, 40 }, 4648 { 10, 200, 50 }, 4649 { 6, 240, 58 }, 4650 { 4, 267, 66 }, 4651 { 2, 400, 100 }, 4652 { 0, 500, 130 }, 4653 }; 4654 const HAL_RATE_TABLE *rt; 4655 int i, j; 4656 4657 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4658 rt = sc->sc_rates[mode]; 4659 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4660 for (i = 0; i < rt->rateCount; i++) 4661 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4662 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4663 for (i = 0; i < 32; i++) { 4664 u_int8_t ix = rt->rateCodeToIndex[i]; 4665 if (ix == 0xff) { 4666 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4667 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4668 continue; 4669 } 4670 sc->sc_hwmap[i].ieeerate = 4671 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4672 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4673 if (rt->info[ix].shortPreamble || 4674 rt->info[ix].phy == IEEE80211_T_OFDM) 4675 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4676 /* NB: receive frames include FCS */ 4677 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4678 IEEE80211_RADIOTAP_F_FCS; 4679 /* setup blink rate table to avoid per-packet lookup */ 4680 for (j = 0; j < N(blinkrates)-1; j++) 4681 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4682 break; 4683 /* NB: this uses the last entry if the rate isn't found */ 4684 /* XXX beware of overlow */ 4685 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4686 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4687 } 4688 sc->sc_currates = rt; 4689 sc->sc_curmode = mode; 4690 /* 4691 * All protection frames are transmited at 2Mb/s for 4692 * 11g, otherwise at 1Mb/s. 4693 * XXX select protection rate index from rate table. 4694 */ 4695 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4696 /* NB: caller is responsible for reseting rate control state */ 4697 #undef N 4698 } 4699 4700 #ifdef AR_DEBUG 4701 static void 4702 ath_printrxbuf(struct ath_buf *bf, int done) 4703 { 4704 struct ath_desc *ds; 4705 int i; 4706 4707 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4708 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4709 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4710 ds->ds_link, ds->ds_data, 4711 ds->ds_ctl0, ds->ds_ctl1, 4712 ds->ds_hw[0], ds->ds_hw[1], 4713 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4714 } 4715 } 4716 4717 static void 4718 ath_printtxbuf(struct ath_buf *bf, int done) 4719 { 4720 struct ath_desc *ds; 4721 int i; 4722 4723 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4724 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4725 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4726 ds->ds_link, ds->ds_data, 4727 ds->ds_ctl0, ds->ds_ctl1, 4728 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4729 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4730 } 4731 } 4732 #endif /* AR_DEBUG */ 4733 4734 static void 4735 ath_watchdog(struct ifnet *ifp) 4736 { 4737 struct ath_softc *sc = ifp->if_softc; 4738 struct ieee80211com *ic = &sc->sc_ic; 4739 4740 ifp->if_timer = 0; 4741 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4742 return; 4743 if (sc->sc_tx_timer) { 4744 if (--sc->sc_tx_timer == 0) { 4745 if_printf(ifp, "device timeout\n"); 4746 ath_reset(ifp); 4747 ifp->if_oerrors++; 4748 sc->sc_stats.ast_watchdog++; 4749 } else 4750 ifp->if_timer = 1; 4751 } 4752 ieee80211_watchdog(ic); 4753 } 4754 4755 /* 4756 * Diagnostic interface to the HAL. This is used by various 4757 * tools to do things like retrieve register contents for 4758 * debugging. The mechanism is intentionally opaque so that 4759 * it can change frequently w/o concern for compatiblity. 4760 */ 4761 static int 4762 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4763 { 4764 struct ath_hal *ah = sc->sc_ah; 4765 u_int id = ad->ad_id & ATH_DIAG_ID; 4766 void *indata = NULL; 4767 void *outdata = NULL; 4768 u_int32_t insize = ad->ad_in_size; 4769 u_int32_t outsize = ad->ad_out_size; 4770 int error = 0; 4771 4772 if (ad->ad_id & ATH_DIAG_IN) { 4773 /* 4774 * Copy in data. 4775 */ 4776 indata = malloc(insize, M_TEMP, M_NOWAIT); 4777 if (indata == NULL) { 4778 error = ENOMEM; 4779 goto bad; 4780 } 4781 error = copyin(ad->ad_in_data, indata, insize); 4782 if (error) 4783 goto bad; 4784 } 4785 if (ad->ad_id & ATH_DIAG_DYN) { 4786 /* 4787 * Allocate a buffer for the results (otherwise the HAL 4788 * returns a pointer to a buffer where we can read the 4789 * results). Note that we depend on the HAL leaving this 4790 * pointer for us to use below in reclaiming the buffer; 4791 * may want to be more defensive. 4792 */ 4793 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4794 if (outdata == NULL) { 4795 error = ENOMEM; 4796 goto bad; 4797 } 4798 } 4799 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4800 if (outsize < ad->ad_out_size) 4801 ad->ad_out_size = outsize; 4802 if (outdata != NULL) 4803 error = copyout(outdata, ad->ad_out_data, 4804 ad->ad_out_size); 4805 } else { 4806 error = EINVAL; 4807 } 4808 bad: 4809 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4810 free(indata, M_TEMP); 4811 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4812 free(outdata, M_TEMP); 4813 return error; 4814 } 4815 4816 static int 4817 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4818 { 4819 #define IS_RUNNING(ifp) \ 4820 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 4821 struct ath_softc *sc = ifp->if_softc; 4822 struct ieee80211com *ic = &sc->sc_ic; 4823 struct ifreq *ifr = (struct ifreq *)data; 4824 int error = 0; 4825 4826 ATH_LOCK(sc); 4827 switch (cmd) { 4828 case SIOCSIFFLAGS: 4829 if (IS_RUNNING(ifp)) { 4830 /* 4831 * To avoid rescanning another access point, 4832 * do not call ath_init() here. Instead, 4833 * only reflect promisc mode settings. 4834 */ 4835 ath_mode_init(sc); 4836 } else if (ifp->if_flags & IFF_UP) { 4837 /* 4838 * Beware of being called during attach/detach 4839 * to reset promiscuous mode. In that case we 4840 * will still be marked UP but not RUNNING. 4841 * However trying to re-init the interface 4842 * is the wrong thing to do as we've already 4843 * torn down much of our state. There's 4844 * probably a better way to deal with this. 4845 */ 4846 if (!sc->sc_invalid && ic->ic_bss != NULL) 4847 ath_init(sc); /* XXX lose error */ 4848 } else 4849 ath_stop_locked(ifp, 1); 4850 break; 4851 case SIOCADDMULTI: 4852 case SIOCDELMULTI: 4853 error = (cmd == SIOCADDMULTI) ? 4854 ether_addmulti(ifr, &sc->sc_ec) : 4855 ether_delmulti(ifr, &sc->sc_ec); 4856 if (error == ENETRESET) { 4857 if (ifp->if_flags & IFF_RUNNING) 4858 ath_mode_init(sc); 4859 error = 0; 4860 } 4861 break; 4862 case SIOCGATHSTATS: 4863 /* NB: embed these numbers to get a consistent view */ 4864 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4865 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4866 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4867 ATH_UNLOCK(sc); 4868 /* 4869 * NB: Drop the softc lock in case of a page fault; 4870 * we'll accept any potential inconsisentcy in the 4871 * statistics. The alternative is to copy the data 4872 * to a local structure. 4873 */ 4874 return copyout(&sc->sc_stats, 4875 ifr->ifr_data, sizeof (sc->sc_stats)); 4876 case SIOCGATHDIAG: 4877 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4878 break; 4879 default: 4880 error = ieee80211_ioctl(ic, cmd, data); 4881 if (error == ENETRESET) { 4882 if (IS_RUNNING(ifp) && 4883 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4884 ath_init(sc); /* XXX lose error */ 4885 error = 0; 4886 } 4887 if (error == ERESTART) 4888 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4889 break; 4890 } 4891 ATH_UNLOCK(sc); 4892 return error; 4893 #undef IS_RUNNING 4894 } 4895 4896 static void 4897 ath_bpfattach(struct ath_softc *sc) 4898 { 4899 struct ifnet *ifp = &sc->sc_if; 4900 4901 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4902 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4903 &sc->sc_drvbpf); 4904 /* 4905 * Initialize constant fields. 4906 * XXX make header lengths a multiple of 32-bits so subsequent 4907 * headers are properly aligned; this is a kludge to keep 4908 * certain applications happy. 4909 * 4910 * NB: the channel is setup each time we transition to the 4911 * RUN state to avoid filling it in for each frame. 4912 */ 4913 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4914 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4915 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4916 4917 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4918 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4919 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4920 } 4921 4922 /* 4923 * Announce various information on device/driver attach. 4924 */ 4925 static void 4926 ath_announce(struct ath_softc *sc) 4927 { 4928 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4929 struct ifnet *ifp = &sc->sc_if; 4930 struct ath_hal *ah = sc->sc_ah; 4931 u_int modes, cc; 4932 4933 if_printf(ifp, "mac %d.%d phy %d.%d", 4934 ah->ah_macVersion, ah->ah_macRev, 4935 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4936 /* 4937 * Print radio revision(s). We check the wireless modes 4938 * to avoid falsely printing revs for inoperable parts. 4939 * Dual-band radio revs are returned in the 5Ghz rev number. 4940 */ 4941 ath_hal_getcountrycode(ah, &cc); 4942 modes = ath_hal_getwirelessmodes(ah, cc); 4943 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4944 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4945 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4946 ah->ah_analog5GhzRev >> 4, 4947 ah->ah_analog5GhzRev & 0xf, 4948 ah->ah_analog2GhzRev >> 4, 4949 ah->ah_analog2GhzRev & 0xf); 4950 else 4951 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4952 ah->ah_analog5GhzRev & 0xf); 4953 } else 4954 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4955 ah->ah_analog5GhzRev & 0xf); 4956 printf("\n"); 4957 if (bootverbose) { 4958 int i; 4959 for (i = 0; i <= WME_AC_VO; i++) { 4960 struct ath_txq *txq = sc->sc_ac2q[i]; 4961 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4962 txq->axq_qnum, ieee80211_wme_acnames[i]); 4963 } 4964 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4965 sc->sc_cabq->axq_qnum); 4966 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4967 } 4968 #undef HAL_MODE_DUALBAND 4969 } 4970
Indexes created Thu Oct 02 07:10:07 GMT 2025