ath.c revision 1.67
1 /* $NetBSD: ath.c,v 1.67 2006/02/27 06:18:47 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.67 2006/02/27 06:18:47 dyoung Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <machine/bus.h> 74 #include <sys/endian.h> 75 76 #include <machine/bus.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/if_ether.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_netbsd.h> 87 #include <net80211/ieee80211_var.h> 88 89 #if NBPFILTER > 0 90 #include <net/bpf.h> 91 #endif 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #endif 96 97 #include <sys/device.h> 98 #include <dev/ic/ath_netbsd.h> 99 100 #define AR_DEBUG 101 #include <dev/ic/athvar.h> 102 #include <contrib/dev/ic/athhal_desc.h> 103 #include <contrib/dev/ic/athhal_devid.h> /* XXX for softled */ 104 105 /* unaligned little endian access */ 106 #define LE_READ_2(p) \ 107 ((u_int16_t) \ 108 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 109 #define LE_READ_4(p) \ 110 ((u_int32_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 112 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 113 114 enum { 115 ATH_LED_TX, 116 ATH_LED_RX, 117 ATH_LED_POLL, 118 }; 119 120 static int ath_ifinit(struct ifnet *); 121 static int ath_init(struct ath_softc *); 122 static void ath_stop_locked(struct ifnet *, int); 123 static void ath_stop(struct ifnet *, int); 124 static void ath_start(struct ifnet *); 125 static int ath_media_change(struct ifnet *); 126 static void ath_watchdog(struct ifnet *); 127 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 128 static void ath_fatal_proc(void *, int); 129 static void ath_rxorn_proc(void *, int); 130 static void ath_bmiss_proc(void *, int); 131 static int ath_key_alloc(struct ieee80211com *, 132 const struct ieee80211_key *, 133 ieee80211_keyix *, ieee80211_keyix *); 134 static int ath_key_delete(struct ieee80211com *, 135 const struct ieee80211_key *); 136 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 137 const u_int8_t mac[IEEE80211_ADDR_LEN]); 138 static void ath_key_update_begin(struct ieee80211com *); 139 static void ath_key_update_end(struct ieee80211com *); 140 static void ath_mode_init(struct ath_softc *); 141 static void ath_setslottime(struct ath_softc *); 142 static void ath_updateslot(struct ifnet *); 143 static int ath_beaconq_setup(struct ath_hal *); 144 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 145 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 146 static void ath_beacon_proc(void *, int); 147 static void ath_bstuck_proc(void *, int); 148 static void ath_beacon_free(struct ath_softc *); 149 static void ath_beacon_config(struct ath_softc *); 150 static void ath_descdma_cleanup(struct ath_softc *sc, 151 struct ath_descdma *, ath_bufhead *); 152 static int ath_desc_alloc(struct ath_softc *); 153 static void ath_desc_free(struct ath_softc *); 154 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 155 static void ath_node_free(struct ieee80211_node *); 156 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 157 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 158 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 159 struct ieee80211_node *ni, 160 int subtype, int rssi, u_int32_t rstamp); 161 static void ath_setdefantenna(struct ath_softc *, u_int); 162 static void ath_rx_proc(void *, int); 163 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 164 static int ath_tx_setup(struct ath_softc *, int, int); 165 static int ath_wme_update(struct ieee80211com *); 166 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 167 static void ath_tx_cleanup(struct ath_softc *); 168 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 169 struct ath_buf *, struct mbuf *); 170 static void ath_tx_proc_q0(void *, int); 171 static void ath_tx_proc_q0123(void *, int); 172 static void ath_tx_proc(void *, int); 173 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 174 static void ath_draintxq(struct ath_softc *); 175 static void ath_stoprecv(struct ath_softc *); 176 static int ath_startrecv(struct ath_softc *); 177 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 178 static void ath_next_scan(void *); 179 static void ath_calibrate(void *); 180 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 181 static void ath_setup_stationkey(struct ieee80211_node *); 182 static void ath_newassoc(struct ieee80211_node *, int); 183 static int ath_getchannels(struct ath_softc *, u_int cc, 184 HAL_BOOL outdoor, HAL_BOOL xchanmode); 185 static void ath_led_event(struct ath_softc *, int); 186 static void ath_update_txpow(struct ath_softc *); 187 188 static int ath_rate_setup(struct ath_softc *, u_int mode); 189 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 190 191 #ifdef __NetBSD__ 192 int ath_enable(struct ath_softc *); 193 void ath_disable(struct ath_softc *); 194 void ath_power(int, void *); 195 #endif 196 197 #if NBPFILTER > 0 198 static void ath_bpfattach(struct ath_softc *); 199 #endif 200 static void ath_announce(struct ath_softc *); 201 202 int ath_dwelltime = 200; /* 5 channels/second */ 203 int ath_calinterval = 30; /* calibrate every 30 secs */ 204 int ath_outdoor = AH_TRUE; /* outdoor operation */ 205 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 206 int ath_countrycode = CTRY_DEFAULT; /* country code */ 207 int ath_regdomain = 0; /* regulatory domain */ 208 int ath_debug = 0; 209 210 #ifdef AR_DEBUG 211 enum { 212 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 213 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 214 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 215 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 216 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 217 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 218 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 219 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 220 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 221 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 222 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 223 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 224 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 225 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 226 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 227 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 228 ATH_DEBUG_NODE = 0x00080000, /* node management */ 229 ATH_DEBUG_LED = 0x00100000, /* led management */ 230 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 231 ATH_DEBUG_ANY = 0xffffffff 232 }; 233 #define IFF_DUMPPKTS(sc, m) \ 234 ((sc->sc_debug & (m)) || \ 235 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 236 #define DPRINTF(sc, m, fmt, ...) do { \ 237 if (sc->sc_debug & (m)) \ 238 printf(fmt, __VA_ARGS__); \ 239 } while (0) 240 #define KEYPRINTF(sc, ix, hk, mac) do { \ 241 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 242 ath_keyprint(__func__, ix, hk, mac); \ 243 } while (0) 244 static void ath_printrxbuf(struct ath_buf *bf, int); 245 static void ath_printtxbuf(struct ath_buf *bf, int); 246 #else 247 #define IFF_DUMPPKTS(sc, m) \ 248 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 249 #define DPRINTF(m, fmt, ...) 250 #define KEYPRINTF(sc, k, ix, mac) 251 #endif 252 253 #ifdef __NetBSD__ 254 int 255 ath_activate(struct device *self, enum devact act) 256 { 257 struct ath_softc *sc = (struct ath_softc *)self; 258 int rv = 0, s; 259 260 s = splnet(); 261 switch (act) { 262 case DVACT_ACTIVATE: 263 rv = EOPNOTSUPP; 264 break; 265 case DVACT_DEACTIVATE: 266 if_deactivate(&sc->sc_if); 267 break; 268 } 269 splx(s); 270 return rv; 271 } 272 273 int 274 ath_enable(struct ath_softc *sc) 275 { 276 if (ATH_IS_ENABLED(sc) == 0) { 277 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 278 printf("%s: device enable failed\n", 279 sc->sc_dev.dv_xname); 280 return (EIO); 281 } 282 sc->sc_flags |= ATH_ENABLED; 283 } 284 return (0); 285 } 286 287 void 288 ath_disable(struct ath_softc *sc) 289 { 290 if (!ATH_IS_ENABLED(sc)) 291 return; 292 if (sc->sc_disable != NULL) 293 (*sc->sc_disable)(sc); 294 sc->sc_flags &= ~ATH_ENABLED; 295 } 296 #endif /* __NetBSD__ */ 297 298 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 299 300 int 301 ath_attach(u_int16_t devid, struct ath_softc *sc) 302 { 303 struct ifnet *ifp = &sc->sc_if; 304 struct ieee80211com *ic = &sc->sc_ic; 305 struct ath_hal *ah = NULL; 306 HAL_STATUS status; 307 int error = 0, i; 308 309 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 310 311 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 312 313 ah = ath_hal_attach(devid, sc, sc->sc_st, ATH_BUSHANDLE2HAL(sc->sc_sh), 314 &status); 315 if (ah == NULL) { 316 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 317 status); 318 error = ENXIO; 319 goto bad; 320 } 321 if (ah->ah_abi != HAL_ABI_VERSION) { 322 if_printf(ifp, "HAL ABI mismatch detected " 323 "(HAL:0x%x != driver:0x%x)\n", 324 ah->ah_abi, HAL_ABI_VERSION); 325 error = ENXIO; 326 goto bad; 327 } 328 sc->sc_ah = ah; 329 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 330 331 /* 332 * Check if the MAC has multi-rate retry support. 333 * We do this by trying to setup a fake extended 334 * descriptor. MAC's that don't have support will 335 * return false w/o doing anything. MAC's that do 336 * support it will return true w/o doing anything. 337 */ 338 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 339 340 /* 341 * Check if the device has hardware counters for PHY 342 * errors. If so we need to enable the MIB interrupt 343 * so we can act on stat triggers. 344 */ 345 if (ath_hal_hwphycounters(ah)) 346 sc->sc_needmib = 1; 347 348 /* 349 * Get the hardware key cache size. 350 */ 351 sc->sc_keymax = ath_hal_keycachesize(ah); 352 if (sc->sc_keymax > ATH_KEYMAX) { 353 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 354 ATH_KEYMAX, sc->sc_keymax); 355 sc->sc_keymax = ATH_KEYMAX; 356 } 357 /* 358 * Reset the key cache since some parts do not 359 * reset the contents on initial power up. 360 */ 361 for (i = 0; i < sc->sc_keymax; i++) 362 ath_hal_keyreset(ah, i); 363 /* 364 * Mark key cache slots associated with global keys 365 * as in use. If we knew TKIP was not to be used we 366 * could leave the +32, +64, and +32+64 slots free. 367 * XXX only for splitmic. 368 */ 369 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 370 setbit(sc->sc_keymap, i); 371 setbit(sc->sc_keymap, i+32); 372 setbit(sc->sc_keymap, i+64); 373 setbit(sc->sc_keymap, i+32+64); 374 } 375 376 /* 377 * Collect the channel list using the default country 378 * code and including outdoor channels. The 802.11 layer 379 * is resposible for filtering this list based on settings 380 * like the phy mode. 381 */ 382 error = ath_getchannels(sc, ath_countrycode, 383 ath_outdoor, ath_xchanmode); 384 if (error != 0) 385 goto bad; 386 387 /* 388 * Setup rate tables for all potential media types. 389 */ 390 ath_rate_setup(sc, IEEE80211_MODE_11A); 391 ath_rate_setup(sc, IEEE80211_MODE_11B); 392 ath_rate_setup(sc, IEEE80211_MODE_11G); 393 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 394 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 395 /* NB: setup here so ath_rate_update is happy */ 396 ath_setcurmode(sc, IEEE80211_MODE_11A); 397 398 /* 399 * Allocate tx+rx descriptors and populate the lists. 400 */ 401 error = ath_desc_alloc(sc); 402 if (error != 0) { 403 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 404 goto bad; 405 } 406 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 407 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 408 409 ATH_TXBUF_LOCK_INIT(sc); 410 411 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 412 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 413 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 414 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 415 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 416 417 /* 418 * Allocate hardware transmit queues: one queue for 419 * beacon frames and one data queue for each QoS 420 * priority. Note that the hal handles reseting 421 * these queues at the needed time. 422 * 423 * XXX PS-Poll 424 */ 425 sc->sc_bhalq = ath_beaconq_setup(ah); 426 if (sc->sc_bhalq == (u_int) -1) { 427 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 428 error = EIO; 429 goto bad2; 430 } 431 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 432 if (sc->sc_cabq == NULL) { 433 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 434 error = EIO; 435 goto bad2; 436 } 437 /* NB: insure BK queue is the lowest priority h/w queue */ 438 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 439 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 440 ieee80211_wme_acnames[WME_AC_BK]); 441 error = EIO; 442 goto bad2; 443 } 444 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 445 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 446 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 447 /* 448 * Not enough hardware tx queues to properly do WME; 449 * just punt and assign them all to the same h/w queue. 450 * We could do a better job of this if, for example, 451 * we allocate queues when we switch from station to 452 * AP mode. 453 */ 454 if (sc->sc_ac2q[WME_AC_VI] != NULL) 455 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 456 if (sc->sc_ac2q[WME_AC_BE] != NULL) 457 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 458 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 459 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 460 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 461 } 462 463 /* 464 * Special case certain configurations. Note the 465 * CAB queue is handled by these specially so don't 466 * include them when checking the txq setup mask. 467 */ 468 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 469 case 0x01: 470 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 471 break; 472 case 0x0f: 473 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 474 break; 475 default: 476 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 477 break; 478 } 479 480 /* 481 * Setup rate control. Some rate control modules 482 * call back to change the anntena state so expose 483 * the necessary entry points. 484 * XXX maybe belongs in struct ath_ratectrl? 485 */ 486 sc->sc_setdefantenna = ath_setdefantenna; 487 sc->sc_rc = ath_rate_attach(sc); 488 if (sc->sc_rc == NULL) { 489 error = EIO; 490 goto bad2; 491 } 492 493 sc->sc_blinking = 0; 494 sc->sc_ledstate = 1; 495 sc->sc_ledon = 0; /* low true */ 496 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 497 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 498 /* 499 * Auto-enable soft led processing for IBM cards and for 500 * 5211 minipci cards. Users can also manually enable/disable 501 * support with a sysctl. 502 */ 503 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 504 if (sc->sc_softled) { 505 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 506 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 507 } 508 509 ifp->if_softc = sc; 510 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 511 ifp->if_start = ath_start; 512 ifp->if_watchdog = ath_watchdog; 513 ifp->if_ioctl = ath_ioctl; 514 ifp->if_init = ath_ifinit; 515 IFQ_SET_READY(&ifp->if_snd); 516 517 ic->ic_ifp = ifp; 518 ic->ic_reset = ath_reset; 519 ic->ic_newassoc = ath_newassoc; 520 ic->ic_updateslot = ath_updateslot; 521 ic->ic_wme.wme_update = ath_wme_update; 522 /* XXX not right but it's not used anywhere important */ 523 ic->ic_phytype = IEEE80211_T_OFDM; 524 ic->ic_opmode = IEEE80211_M_STA; 525 ic->ic_caps = 526 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 527 | IEEE80211_C_HOSTAP /* hostap mode */ 528 | IEEE80211_C_MONITOR /* monitor mode */ 529 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 530 | IEEE80211_C_SHSLOT /* short slot time supported */ 531 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 532 ; 533 /* 534 * Query the hal to figure out h/w crypto support. 535 */ 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 537 ic->ic_caps |= IEEE80211_C_WEP; 538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 539 ic->ic_caps |= IEEE80211_C_AES; 540 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 541 ic->ic_caps |= IEEE80211_C_AES_CCM; 542 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 543 ic->ic_caps |= IEEE80211_C_CKIP; 544 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 545 ic->ic_caps |= IEEE80211_C_TKIP; 546 /* 547 * Check if h/w does the MIC and/or whether the 548 * separate key cache entries are required to 549 * handle both tx+rx MIC keys. 550 */ 551 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 552 ic->ic_caps |= IEEE80211_C_TKIPMIC; 553 if (ath_hal_tkipsplit(ah)) 554 sc->sc_splitmic = 1; 555 } 556 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 557 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 558 /* 559 * TPC support can be done either with a global cap or 560 * per-packet support. The latter is not available on 561 * all parts. We're a bit pedantic here as all parts 562 * support a global cap. 563 */ 564 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 565 ic->ic_caps |= IEEE80211_C_TXPMGT; 566 567 /* 568 * Mark WME capability only if we have sufficient 569 * hardware queues to do proper priority scheduling. 570 */ 571 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 572 ic->ic_caps |= IEEE80211_C_WME; 573 /* 574 * Check for misc other capabilities. 575 */ 576 if (ath_hal_hasbursting(ah)) 577 ic->ic_caps |= IEEE80211_C_BURST; 578 579 /* 580 * Indicate we need the 802.11 header padded to a 581 * 32-bit boundary for 4-address and QoS frames. 582 */ 583 ic->ic_flags |= IEEE80211_F_DATAPAD; 584 585 /* 586 * Query the hal about antenna support. 587 */ 588 sc->sc_defant = ath_hal_getdefantenna(ah); 589 590 /* 591 * Not all chips have the VEOL support we want to 592 * use with IBSS beacons; check here for it. 593 */ 594 sc->sc_hasveol = ath_hal_hasveol(ah); 595 596 /* get mac address from hardware */ 597 ath_hal_getmac(ah, ic->ic_myaddr); 598 599 if_attach(ifp); 600 /* call MI attach routine. */ 601 ieee80211_ifattach(ic); 602 /* override default methods */ 603 ic->ic_node_alloc = ath_node_alloc; 604 sc->sc_node_free = ic->ic_node_free; 605 ic->ic_node_free = ath_node_free; 606 ic->ic_node_getrssi = ath_node_getrssi; 607 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 608 ic->ic_recv_mgmt = ath_recv_mgmt; 609 sc->sc_newstate = ic->ic_newstate; 610 ic->ic_newstate = ath_newstate; 611 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 612 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 613 ic->ic_crypto.cs_key_delete = ath_key_delete; 614 ic->ic_crypto.cs_key_set = ath_key_set; 615 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 616 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 617 /* complete initialization */ 618 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 619 620 #if NBPFILTER > 0 621 ath_bpfattach(sc); 622 #endif 623 624 #ifdef __NetBSD__ 625 sc->sc_flags |= ATH_ATTACHED; 626 /* 627 * Make sure the interface is shutdown during reboot. 628 */ 629 sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 630 if (sc->sc_sdhook == NULL) 631 printf("%s: WARNING: unable to establish shutdown hook\n", 632 sc->sc_dev.dv_xname); 633 sc->sc_powerhook = powerhook_establish(ath_power, sc); 634 if (sc->sc_powerhook == NULL) 635 printf("%s: WARNING: unable to establish power hook\n", 636 sc->sc_dev.dv_xname); 637 #endif 638 639 /* 640 * Setup dynamic sysctl's now that country code and 641 * regdomain are available from the hal. 642 */ 643 ath_sysctlattach(sc); 644 645 ieee80211_announce(ic); 646 ath_announce(sc); 647 return 0; 648 bad2: 649 ath_tx_cleanup(sc); 650 ath_desc_free(sc); 651 bad: 652 if (ah) 653 ath_hal_detach(ah); 654 sc->sc_invalid = 1; 655 return error; 656 } 657 658 int 659 ath_detach(struct ath_softc *sc) 660 { 661 struct ifnet *ifp = &sc->sc_if; 662 int s; 663 664 if ((sc->sc_flags & ATH_ATTACHED) == 0) 665 return (0); 666 667 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 668 __func__, ifp->if_flags); 669 670 s = splnet(); 671 ath_stop(ifp, 1); 672 #if NBPFILTER > 0 673 bpfdetach(ifp); 674 #endif 675 /* 676 * NB: the order of these is important: 677 * o call the 802.11 layer before detaching the hal to 678 * insure callbacks into the driver to delete global 679 * key cache entries can be handled 680 * o reclaim the tx queue data structures after calling 681 * the 802.11 layer as we'll get called back to reclaim 682 * node state and potentially want to use them 683 * o to cleanup the tx queues the hal is called, so detach 684 * it last 685 * Other than that, it's straightforward... 686 */ 687 ieee80211_ifdetach(&sc->sc_ic); 688 ath_rate_detach(sc->sc_rc); 689 ath_desc_free(sc); 690 ath_tx_cleanup(sc); 691 sysctl_teardown(&sc->sc_sysctllog); 692 ath_hal_detach(sc->sc_ah); 693 if_detach(ifp); 694 splx(s); 695 powerhook_disestablish(sc->sc_powerhook); 696 shutdownhook_disestablish(sc->sc_sdhook); 697 698 return 0; 699 } 700 701 #ifdef __NetBSD__ 702 void 703 ath_power(int why, void *arg) 704 { 705 struct ath_softc *sc = arg; 706 int s; 707 708 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 709 710 s = splnet(); 711 switch (why) { 712 case PWR_SUSPEND: 713 case PWR_STANDBY: 714 ath_suspend(sc, why); 715 break; 716 case PWR_RESUME: 717 ath_resume(sc, why); 718 break; 719 case PWR_SOFTSUSPEND: 720 case PWR_SOFTSTANDBY: 721 case PWR_SOFTRESUME: 722 break; 723 } 724 splx(s); 725 } 726 #endif 727 728 void 729 ath_suspend(struct ath_softc *sc, int why) 730 { 731 struct ifnet *ifp = &sc->sc_if; 732 733 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 734 __func__, ifp->if_flags); 735 736 ath_stop(ifp, 1); 737 if (sc->sc_power != NULL) 738 (*sc->sc_power)(sc, why); 739 } 740 741 void 742 ath_resume(struct ath_softc *sc, int why) 743 { 744 struct ifnet *ifp = &sc->sc_if; 745 746 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 747 __func__, ifp->if_flags); 748 749 if (ifp->if_flags & IFF_UP) { 750 ath_init(sc); 751 #if 0 752 (void)ath_intr(sc); 753 #endif 754 if (sc->sc_power != NULL) 755 (*sc->sc_power)(sc, why); 756 if (ifp->if_flags & IFF_RUNNING) 757 ath_start(ifp); 758 } 759 if (sc->sc_softled) { 760 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 761 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 762 } 763 } 764 765 void 766 ath_shutdown(void *arg) 767 { 768 struct ath_softc *sc = arg; 769 770 ath_stop(&sc->sc_if, 1); 771 } 772 773 /* 774 * Interrupt handler. Most of the actual processing is deferred. 775 */ 776 int 777 ath_intr(void *arg) 778 { 779 struct ath_softc *sc = arg; 780 struct ifnet *ifp = &sc->sc_if; 781 struct ath_hal *ah = sc->sc_ah; 782 HAL_INT status; 783 784 if (sc->sc_invalid) { 785 /* 786 * The hardware is not ready/present, don't touch anything. 787 * Note this can happen early on if the IRQ is shared. 788 */ 789 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 790 return 0; 791 } 792 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 793 return 0; 794 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 795 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 796 __func__, ifp->if_flags); 797 ath_hal_getisr(ah, &status); /* clear ISR */ 798 ath_hal_intrset(ah, 0); /* disable further intr's */ 799 return 1; /* XXX */ 800 } 801 /* 802 * Figure out the reason(s) for the interrupt. Note 803 * that the hal returns a pseudo-ISR that may include 804 * bits we haven't explicitly enabled so we mask the 805 * value to insure we only process bits we requested. 806 */ 807 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 808 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 809 status &= sc->sc_imask; /* discard unasked for bits */ 810 if (status & HAL_INT_FATAL) { 811 /* 812 * Fatal errors are unrecoverable. Typically 813 * these are caused by DMA errors. Unfortunately 814 * the exact reason is not (presently) returned 815 * by the hal. 816 */ 817 sc->sc_stats.ast_hardware++; 818 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 819 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 820 } else if (status & HAL_INT_RXORN) { 821 sc->sc_stats.ast_rxorn++; 822 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 823 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 824 } else { 825 if (status & HAL_INT_SWBA) { 826 /* 827 * Software beacon alert--time to send a beacon. 828 * Handle beacon transmission directly; deferring 829 * this is too slow to meet timing constraints 830 * under load. 831 */ 832 ath_beacon_proc(sc, 0); 833 } 834 if (status & HAL_INT_RXEOL) { 835 /* 836 * NB: the hardware should re-read the link when 837 * RXE bit is written, but it doesn't work at 838 * least on older hardware revs. 839 */ 840 sc->sc_stats.ast_rxeol++; 841 sc->sc_rxlink = NULL; 842 } 843 if (status & HAL_INT_TXURN) { 844 sc->sc_stats.ast_txurn++; 845 /* bump tx trigger level */ 846 ath_hal_updatetxtriglevel(ah, AH_TRUE); 847 } 848 if (status & HAL_INT_RX) 849 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 850 if (status & HAL_INT_TX) 851 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 852 if (status & HAL_INT_BMISS) { 853 sc->sc_stats.ast_bmiss++; 854 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 855 } 856 if (status & HAL_INT_MIB) { 857 sc->sc_stats.ast_mib++; 858 /* 859 * Disable interrupts until we service the MIB 860 * interrupt; otherwise it will continue to fire. 861 */ 862 ath_hal_intrset(ah, 0); 863 /* 864 * Let the hal handle the event. We assume it will 865 * clear whatever condition caused the interrupt. 866 */ 867 ath_hal_mibevent(ah, 868 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 869 ath_hal_intrset(ah, sc->sc_imask); 870 } 871 } 872 return 1; 873 } 874 875 static void 876 ath_fatal_proc(void *arg, int pending) 877 { 878 struct ath_softc *sc = arg; 879 struct ifnet *ifp = &sc->sc_if; 880 881 if_printf(ifp, "hardware error; resetting\n"); 882 ath_reset(ifp); 883 } 884 885 static void 886 ath_rxorn_proc(void *arg, int pending) 887 { 888 struct ath_softc *sc = arg; 889 struct ifnet *ifp = &sc->sc_if; 890 891 if_printf(ifp, "rx FIFO overrun; resetting\n"); 892 ath_reset(ifp); 893 } 894 895 static void 896 ath_bmiss_proc(void *arg, int pending) 897 { 898 struct ath_softc *sc = arg; 899 struct ieee80211com *ic = &sc->sc_ic; 900 901 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 902 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 903 ("unexpect operating mode %u", ic->ic_opmode)); 904 if (ic->ic_state == IEEE80211_S_RUN) { 905 /* 906 * Rather than go directly to scan state, try to 907 * reassociate first. If that fails then the state 908 * machine will drop us into scanning after timing 909 * out waiting for a probe response. 910 */ 911 NET_LOCK_GIANT(); 912 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 913 NET_UNLOCK_GIANT(); 914 } 915 } 916 917 static u_int 918 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 919 { 920 #define N(a) (sizeof(a) / sizeof(a[0])) 921 static const u_int modeflags[] = { 922 0, /* IEEE80211_MODE_AUTO */ 923 CHANNEL_A, /* IEEE80211_MODE_11A */ 924 CHANNEL_B, /* IEEE80211_MODE_11B */ 925 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 926 0, /* IEEE80211_MODE_FH */ 927 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 928 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 929 }; 930 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 931 932 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 933 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 934 return modeflags[mode]; 935 #undef N 936 } 937 938 static int 939 ath_ifinit(struct ifnet *ifp) 940 { 941 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 942 943 return ath_init(sc); 944 } 945 946 static int 947 ath_init(struct ath_softc *sc) 948 { 949 struct ifnet *ifp = &sc->sc_if; 950 struct ieee80211com *ic = &sc->sc_ic; 951 struct ath_hal *ah = sc->sc_ah; 952 HAL_STATUS status; 953 int error = 0; 954 955 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 956 __func__, ifp->if_flags); 957 958 ATH_LOCK(sc); 959 960 if ((error = ath_enable(sc)) != 0) 961 return error; 962 963 /* 964 * Stop anything previously setup. This is safe 965 * whether this is the first time through or not. 966 */ 967 ath_stop_locked(ifp, 0); 968 969 /* 970 * The basic interface to setting the hardware in a good 971 * state is ``reset''. On return the hardware is known to 972 * be powered up and with interrupts disabled. This must 973 * be followed by initialization of the appropriate bits 974 * and then setup of the interrupt mask. 975 */ 976 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 977 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 978 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 979 if_printf(ifp, "unable to reset hardware; hal status %u\n", 980 status); 981 error = EIO; 982 goto done; 983 } 984 985 /* 986 * This is needed only to setup initial state 987 * but it's best done after a reset. 988 */ 989 ath_update_txpow(sc); 990 /* 991 * Likewise this is set during reset so update 992 * state cached in the driver. 993 */ 994 sc->sc_diversity = ath_hal_getdiversity(ah); 995 996 /* 997 * Setup the hardware after reset: the key cache 998 * is filled as needed and the receive engine is 999 * set going. Frame transmit is handled entirely 1000 * in the frame output path; there's nothing to do 1001 * here except setup the interrupt mask. 1002 */ 1003 if ((error = ath_startrecv(sc)) != 0) { 1004 if_printf(ifp, "unable to start recv logic\n"); 1005 goto done; 1006 } 1007 1008 /* 1009 * Enable interrupts. 1010 */ 1011 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1012 | HAL_INT_RXEOL | HAL_INT_RXORN 1013 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1014 /* 1015 * Enable MIB interrupts when there are hardware phy counters. 1016 * Note we only do this (at the moment) for station mode. 1017 */ 1018 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1019 sc->sc_imask |= HAL_INT_MIB; 1020 ath_hal_intrset(ah, sc->sc_imask); 1021 1022 ifp->if_flags |= IFF_RUNNING; 1023 ic->ic_state = IEEE80211_S_INIT; 1024 1025 /* 1026 * The hardware should be ready to go now so it's safe 1027 * to kick the 802.11 state machine as it's likely to 1028 * immediately call back to us to send mgmt frames. 1029 */ 1030 ath_chan_change(sc, ic->ic_curchan); 1031 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1032 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1033 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1034 } else 1035 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1036 done: 1037 ATH_UNLOCK(sc); 1038 return error; 1039 } 1040 1041 static void 1042 ath_stop_locked(struct ifnet *ifp, int disable) 1043 { 1044 struct ath_softc *sc = ifp->if_softc; 1045 struct ieee80211com *ic = &sc->sc_ic; 1046 struct ath_hal *ah = sc->sc_ah; 1047 1048 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1049 __func__, sc->sc_invalid, ifp->if_flags); 1050 1051 ATH_LOCK_ASSERT(sc); 1052 if (ifp->if_flags & IFF_RUNNING) { 1053 /* 1054 * Shutdown the hardware and driver: 1055 * reset 802.11 state machine 1056 * turn off timers 1057 * disable interrupts 1058 * turn off the radio 1059 * clear transmit machinery 1060 * clear receive machinery 1061 * drain and release tx queues 1062 * reclaim beacon resources 1063 * power down hardware 1064 * 1065 * Note that some of this work is not possible if the 1066 * hardware is gone (invalid). 1067 */ 1068 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1069 ifp->if_flags &= ~IFF_RUNNING; 1070 ifp->if_timer = 0; 1071 if (!sc->sc_invalid) { 1072 if (sc->sc_softled) { 1073 callout_stop(&sc->sc_ledtimer); 1074 ath_hal_gpioset(ah, sc->sc_ledpin, 1075 !sc->sc_ledon); 1076 sc->sc_blinking = 0; 1077 } 1078 ath_hal_intrset(ah, 0); 1079 } 1080 ath_draintxq(sc); 1081 if (!sc->sc_invalid) { 1082 ath_stoprecv(sc); 1083 ath_hal_phydisable(ah); 1084 } else 1085 sc->sc_rxlink = NULL; 1086 IF_PURGE(&ifp->if_snd); 1087 ath_beacon_free(sc); 1088 if (disable) 1089 ath_disable(sc); 1090 } 1091 } 1092 1093 static void 1094 ath_stop(struct ifnet *ifp, int disable) 1095 { 1096 struct ath_softc *sc = ifp->if_softc; 1097 1098 ATH_LOCK(sc); 1099 ath_stop_locked(ifp, disable); 1100 if (!sc->sc_invalid) { 1101 /* 1102 * Set the chip in full sleep mode. Note that we are 1103 * careful to do this only when bringing the interface 1104 * completely to a stop. When the chip is in this state 1105 * it must be carefully woken up or references to 1106 * registers in the PCI clock domain may freeze the bus 1107 * (and system). This varies by chip and is mostly an 1108 * issue with newer parts that go to sleep more quickly. 1109 */ 1110 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 1111 } 1112 ATH_UNLOCK(sc); 1113 } 1114 1115 /* 1116 * Reset the hardware w/o losing operational state. This is 1117 * basically a more efficient way of doing ath_stop, ath_init, 1118 * followed by state transitions to the current 802.11 1119 * operational state. Used to recover from various errors and 1120 * to reset or reload hardware state. 1121 */ 1122 int 1123 ath_reset(struct ifnet *ifp) 1124 { 1125 struct ath_softc *sc = ifp->if_softc; 1126 struct ieee80211com *ic = &sc->sc_ic; 1127 struct ath_hal *ah = sc->sc_ah; 1128 struct ieee80211_channel *c; 1129 HAL_STATUS status; 1130 1131 /* 1132 * Convert to a HAL channel description with the flags 1133 * constrained to reflect the current operating mode. 1134 */ 1135 c = ic->ic_curchan; 1136 sc->sc_curchan.channel = c->ic_freq; 1137 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1138 1139 ath_hal_intrset(ah, 0); /* disable interrupts */ 1140 ath_draintxq(sc); /* stop xmit side */ 1141 ath_stoprecv(sc); /* stop recv side */ 1142 /* NB: indicate channel change so we do a full reset */ 1143 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1144 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1145 __func__, status); 1146 ath_update_txpow(sc); /* update tx power state */ 1147 sc->sc_diversity = ath_hal_getdiversity(ah); 1148 if (ath_startrecv(sc) != 0) /* restart recv */ 1149 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1150 /* 1151 * We may be doing a reset in response to an ioctl 1152 * that changes the channel so update any state that 1153 * might change as a result. 1154 */ 1155 ath_chan_change(sc, c); 1156 if (ic->ic_state == IEEE80211_S_RUN) 1157 ath_beacon_config(sc); /* restart beacons */ 1158 ath_hal_intrset(ah, sc->sc_imask); 1159 1160 ath_start(ifp); /* restart xmit */ 1161 return 0; 1162 } 1163 1164 static void 1165 ath_start(struct ifnet *ifp) 1166 { 1167 struct ath_softc *sc = ifp->if_softc; 1168 struct ath_hal *ah = sc->sc_ah; 1169 struct ieee80211com *ic = &sc->sc_ic; 1170 struct ieee80211_node *ni; 1171 struct ath_buf *bf; 1172 struct mbuf *m; 1173 struct ieee80211_frame *wh; 1174 struct ether_header *eh; 1175 1176 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1177 return; 1178 for (;;) { 1179 /* 1180 * Grab a TX buffer and associated resources. 1181 */ 1182 ATH_TXBUF_LOCK(sc); 1183 bf = STAILQ_FIRST(&sc->sc_txbuf); 1184 if (bf != NULL) 1185 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1186 ATH_TXBUF_UNLOCK(sc); 1187 if (bf == NULL) { 1188 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1189 __func__); 1190 sc->sc_stats.ast_tx_qstop++; 1191 ifp->if_flags |= IFF_OACTIVE; 1192 break; 1193 } 1194 /* 1195 * Poll the management queue for frames; they 1196 * have priority over normal data frames. 1197 */ 1198 IF_DEQUEUE(&ic->ic_mgtq, m); 1199 if (m == NULL) { 1200 /* 1201 * No data frames go out unless we're associated. 1202 */ 1203 if (ic->ic_state != IEEE80211_S_RUN) { 1204 DPRINTF(sc, ATH_DEBUG_XMIT, 1205 "%s: discard data packet, state %s\n", 1206 __func__, 1207 ieee80211_state_name[ic->ic_state]); 1208 sc->sc_stats.ast_tx_discard++; 1209 ATH_TXBUF_LOCK(sc); 1210 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1211 ATH_TXBUF_UNLOCK(sc); 1212 break; 1213 } 1214 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1215 if (m == NULL) { 1216 ATH_TXBUF_LOCK(sc); 1217 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1218 ATH_TXBUF_UNLOCK(sc); 1219 break; 1220 } 1221 /* 1222 * Find the node for the destination so we can do 1223 * things like power save and fast frames aggregation. 1224 */ 1225 if (m->m_len < sizeof(struct ether_header) && 1226 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1227 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1228 ni = NULL; 1229 goto bad; 1230 } 1231 eh = mtod(m, struct ether_header *); 1232 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1233 if (ni == NULL) { 1234 /* NB: ieee80211_find_txnode does stat+msg */ 1235 m_freem(m); 1236 goto bad; 1237 } 1238 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1239 (m->m_flags & M_PWR_SAV) == 0) { 1240 /* 1241 * Station in power save mode; pass the frame 1242 * to the 802.11 layer and continue. We'll get 1243 * the frame back when the time is right. 1244 */ 1245 ieee80211_pwrsave(ic, ni, m); 1246 goto reclaim; 1247 } 1248 /* calculate priority so we can find the tx queue */ 1249 if (ieee80211_classify(ic, m, ni)) { 1250 DPRINTF(sc, ATH_DEBUG_XMIT, 1251 "%s: discard, classification failure\n", 1252 __func__); 1253 m_freem(m); 1254 goto bad; 1255 } 1256 ifp->if_opackets++; 1257 1258 #if NBPFILTER > 0 1259 if (ifp->if_bpf) 1260 bpf_mtap(ifp->if_bpf, m); 1261 #endif 1262 /* 1263 * Encapsulate the packet in prep for transmission. 1264 */ 1265 m = ieee80211_encap(ic, m, ni); 1266 if (m == NULL) { 1267 DPRINTF(sc, ATH_DEBUG_XMIT, 1268 "%s: encapsulation failure\n", 1269 __func__); 1270 sc->sc_stats.ast_tx_encap++; 1271 goto bad; 1272 } 1273 } else { 1274 /* 1275 * Hack! The referenced node pointer is in the 1276 * rcvif field of the packet header. This is 1277 * placed there by ieee80211_mgmt_output because 1278 * we need to hold the reference with the frame 1279 * and there's no other way (other than packet 1280 * tags which we consider too expensive to use) 1281 * to pass it along. 1282 */ 1283 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1284 m->m_pkthdr.rcvif = NULL; 1285 1286 wh = mtod(m, struct ieee80211_frame *); 1287 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1288 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1289 /* fill time stamp */ 1290 u_int64_t tsf; 1291 u_int32_t *tstamp; 1292 1293 tsf = ath_hal_gettsf64(ah); 1294 /* XXX: adjust 100us delay to xmit */ 1295 tsf += 100; 1296 tstamp = (u_int32_t *)&wh[1]; 1297 tstamp[0] = htole32(tsf & 0xffffffff); 1298 tstamp[1] = htole32(tsf >> 32); 1299 } 1300 sc->sc_stats.ast_tx_mgmt++; 1301 } 1302 1303 if (ath_tx_start(sc, ni, bf, m)) { 1304 bad: 1305 ifp->if_oerrors++; 1306 reclaim: 1307 ATH_TXBUF_LOCK(sc); 1308 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1309 ATH_TXBUF_UNLOCK(sc); 1310 if (ni != NULL) 1311 ieee80211_free_node(ni); 1312 continue; 1313 } 1314 1315 sc->sc_tx_timer = 5; 1316 ifp->if_timer = 1; 1317 } 1318 } 1319 1320 static int 1321 ath_media_change(struct ifnet *ifp) 1322 { 1323 #define IS_UP(ifp) \ 1324 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1325 int error; 1326 1327 error = ieee80211_media_change(ifp); 1328 if (error == ENETRESET) { 1329 if (IS_UP(ifp)) 1330 ath_init(ifp->if_softc); /* XXX lose error */ 1331 error = 0; 1332 } 1333 return error; 1334 #undef IS_UP 1335 } 1336 1337 #ifdef AR_DEBUG 1338 static void 1339 ath_keyprint(const char *tag, u_int ix, 1340 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1341 { 1342 static const char *ciphers[] = { 1343 "WEP", 1344 "AES-OCB", 1345 "AES-CCM", 1346 "CKIP", 1347 "TKIP", 1348 "CLR", 1349 }; 1350 int i, n; 1351 1352 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1353 for (i = 0, n = hk->kv_len; i < n; i++) 1354 printf("%02x", hk->kv_val[i]); 1355 printf(" mac %s", ether_sprintf(mac)); 1356 if (hk->kv_type == HAL_CIPHER_TKIP) { 1357 printf(" mic "); 1358 for (i = 0; i < sizeof(hk->kv_mic); i++) 1359 printf("%02x", hk->kv_mic[i]); 1360 } 1361 printf("\n"); 1362 } 1363 #endif 1364 1365 /* 1366 * Set a TKIP key into the hardware. This handles the 1367 * potential distribution of key state to multiple key 1368 * cache slots for TKIP. 1369 */ 1370 static int 1371 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1372 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1373 { 1374 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1375 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1376 struct ath_hal *ah = sc->sc_ah; 1377 1378 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1379 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1380 KASSERT(sc->sc_splitmic, ("key cache !split")); 1381 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1382 /* 1383 * TX key goes at first index, RX key at the rx index. 1384 * The hal handles the MIC keys at index+64. 1385 */ 1386 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1387 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1388 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1389 return 0; 1390 1391 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1392 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1393 /* XXX delete tx key on failure? */ 1394 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1395 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1396 /* 1397 * TX/RX key goes at first index. 1398 * The hal handles the MIC keys are index+64. 1399 */ 1400 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1401 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1402 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1403 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1404 } 1405 return 0; 1406 #undef IEEE80211_KEY_XR 1407 } 1408 1409 /* 1410 * Set a net80211 key into the hardware. This handles the 1411 * potential distribution of key state to multiple key 1412 * cache slots for TKIP with hardware MIC support. 1413 */ 1414 static int 1415 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1416 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1417 struct ieee80211_node *bss) 1418 { 1419 #define N(a) (sizeof(a)/sizeof(a[0])) 1420 static const u_int8_t ciphermap[] = { 1421 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1422 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1423 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1424 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1425 (u_int8_t) -1, /* 4 is not allocated */ 1426 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1427 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1428 }; 1429 struct ath_hal *ah = sc->sc_ah; 1430 const struct ieee80211_cipher *cip = k->wk_cipher; 1431 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1432 const u_int8_t *mac; 1433 HAL_KEYVAL hk; 1434 1435 memset(&hk, 0, sizeof(hk)); 1436 /* 1437 * Software crypto uses a "clear key" so non-crypto 1438 * state kept in the key cache are maintained and 1439 * so that rx frames have an entry to match. 1440 */ 1441 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1442 KASSERT(cip->ic_cipher < N(ciphermap), 1443 ("invalid cipher type %u", cip->ic_cipher)); 1444 hk.kv_type = ciphermap[cip->ic_cipher]; 1445 hk.kv_len = k->wk_keylen; 1446 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1447 } else 1448 hk.kv_type = HAL_CIPHER_CLR; 1449 1450 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1451 /* 1452 * Group keys on hardware that supports multicast frame 1453 * key search use a mac that is the sender's address with 1454 * the high bit set instead of the app-specified address. 1455 */ 1456 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1457 gmac[0] |= 0x80; 1458 mac = gmac; 1459 } else 1460 mac = mac0; 1461 1462 if (hk.kv_type == HAL_CIPHER_TKIP && 1463 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1464 sc->sc_splitmic) { 1465 return ath_keyset_tkip(sc, k, &hk, mac); 1466 } else { 1467 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1468 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1469 } 1470 #undef N 1471 } 1472 1473 /* 1474 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1475 * each key, one for decrypt/encrypt and the other for the MIC. 1476 */ 1477 static u_int16_t 1478 key_alloc_2pair(struct ath_softc *sc, 1479 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1480 { 1481 #define N(a) (sizeof(a)/sizeof(a[0])) 1482 u_int i, keyix; 1483 1484 KASSERT(sc->sc_splitmic, ("key cache !split")); 1485 /* XXX could optimize */ 1486 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1487 u_int8_t b = sc->sc_keymap[i]; 1488 if (b != 0xff) { 1489 /* 1490 * One or more slots in this byte are free. 1491 */ 1492 keyix = i*NBBY; 1493 while (b & 1) { 1494 again: 1495 keyix++; 1496 b >>= 1; 1497 } 1498 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1499 if (isset(sc->sc_keymap, keyix+32) || 1500 isset(sc->sc_keymap, keyix+64) || 1501 isset(sc->sc_keymap, keyix+32+64)) { 1502 /* full pair unavailable */ 1503 /* XXX statistic */ 1504 if (keyix == (i+1)*NBBY) { 1505 /* no slots were appropriate, advance */ 1506 continue; 1507 } 1508 goto again; 1509 } 1510 setbit(sc->sc_keymap, keyix); 1511 setbit(sc->sc_keymap, keyix+64); 1512 setbit(sc->sc_keymap, keyix+32); 1513 setbit(sc->sc_keymap, keyix+32+64); 1514 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1515 "%s: key pair %u,%u %u,%u\n", 1516 __func__, keyix, keyix+64, 1517 keyix+32, keyix+32+64); 1518 *txkeyix = keyix; 1519 *rxkeyix = keyix+32; 1520 return 1; 1521 } 1522 } 1523 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1524 return 0; 1525 #undef N 1526 } 1527 1528 /* 1529 * Allocate a single key cache slot. 1530 */ 1531 static int 1532 key_alloc_single(struct ath_softc *sc, 1533 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1534 { 1535 #define N(a) (sizeof(a)/sizeof(a[0])) 1536 u_int i, keyix; 1537 1538 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1539 for (i = 0; i < N(sc->sc_keymap); i++) { 1540 u_int8_t b = sc->sc_keymap[i]; 1541 if (b != 0xff) { 1542 /* 1543 * One or more slots are free. 1544 */ 1545 keyix = i*NBBY; 1546 while (b & 1) 1547 keyix++, b >>= 1; 1548 setbit(sc->sc_keymap, keyix); 1549 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1550 __func__, keyix); 1551 *txkeyix = *rxkeyix = keyix; 1552 return 1; 1553 } 1554 } 1555 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1556 return 0; 1557 #undef N 1558 } 1559 1560 /* 1561 * Allocate one or more key cache slots for a uniacst key. The 1562 * key itself is needed only to identify the cipher. For hardware 1563 * TKIP with split cipher+MIC keys we allocate two key cache slot 1564 * pairs so that we can setup separate TX and RX MIC keys. Note 1565 * that the MIC key for a TKIP key at slot i is assumed by the 1566 * hardware to be at slot i+64. This limits TKIP keys to the first 1567 * 64 entries. 1568 */ 1569 static int 1570 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1571 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1572 { 1573 struct ath_softc *sc = ic->ic_ifp->if_softc; 1574 1575 /* 1576 * Group key allocation must be handled specially for 1577 * parts that do not support multicast key cache search 1578 * functionality. For those parts the key id must match 1579 * the h/w key index so lookups find the right key. On 1580 * parts w/ the key search facility we install the sender's 1581 * mac address (with the high bit set) and let the hardware 1582 * find the key w/o using the key id. This is preferred as 1583 * it permits us to support multiple users for adhoc and/or 1584 * multi-station operation. 1585 */ 1586 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1587 if (!(&ic->ic_nw_keys[0] <= k && 1588 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1589 /* should not happen */ 1590 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1591 "%s: bogus group key\n", __func__); 1592 return 0; 1593 } 1594 /* 1595 * XXX we pre-allocate the global keys so 1596 * have no way to check if they've already been allocated. 1597 */ 1598 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1599 return 1; 1600 } 1601 1602 /* 1603 * We allocate two pair for TKIP when using the h/w to do 1604 * the MIC. For everything else, including software crypto, 1605 * we allocate a single entry. Note that s/w crypto requires 1606 * a pass-through slot on the 5211 and 5212. The 5210 does 1607 * not support pass-through cache entries and we map all 1608 * those requests to slot 0. 1609 */ 1610 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1611 return key_alloc_single(sc, keyix, rxkeyix); 1612 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1613 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1614 return key_alloc_2pair(sc, keyix, rxkeyix); 1615 } else { 1616 return key_alloc_single(sc, keyix, rxkeyix); 1617 } 1618 } 1619 1620 /* 1621 * Delete an entry in the key cache allocated by ath_key_alloc. 1622 */ 1623 static int 1624 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1625 { 1626 struct ath_softc *sc = ic->ic_ifp->if_softc; 1627 struct ath_hal *ah = sc->sc_ah; 1628 const struct ieee80211_cipher *cip = k->wk_cipher; 1629 u_int keyix = k->wk_keyix; 1630 1631 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1632 1633 ath_hal_keyreset(ah, keyix); 1634 /* 1635 * Handle split tx/rx keying required for TKIP with h/w MIC. 1636 */ 1637 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1638 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1639 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1640 if (keyix >= IEEE80211_WEP_NKID) { 1641 /* 1642 * Don't touch keymap entries for global keys so 1643 * they are never considered for dynamic allocation. 1644 */ 1645 clrbit(sc->sc_keymap, keyix); 1646 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1647 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1648 sc->sc_splitmic) { 1649 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1650 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1651 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1652 } 1653 } 1654 return 1; 1655 } 1656 1657 /* 1658 * Set the key cache contents for the specified key. Key cache 1659 * slot(s) must already have been allocated by ath_key_alloc. 1660 */ 1661 static int 1662 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1663 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1664 { 1665 struct ath_softc *sc = ic->ic_ifp->if_softc; 1666 1667 return ath_keyset(sc, k, mac, ic->ic_bss); 1668 } 1669 1670 /* 1671 * Block/unblock tx+rx processing while a key change is done. 1672 * We assume the caller serializes key management operations 1673 * so we only need to worry about synchronization with other 1674 * uses that originate in the driver. 1675 */ 1676 static void 1677 ath_key_update_begin(struct ieee80211com *ic) 1678 { 1679 struct ifnet *ifp = ic->ic_ifp; 1680 struct ath_softc *sc = ifp->if_softc; 1681 1682 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1683 #if 0 1684 tasklet_disable(&sc->sc_rxtq); 1685 #endif 1686 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1687 } 1688 1689 static void 1690 ath_key_update_end(struct ieee80211com *ic) 1691 { 1692 struct ifnet *ifp = ic->ic_ifp; 1693 struct ath_softc *sc = ifp->if_softc; 1694 1695 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1696 IF_UNLOCK(&ifp->if_snd); 1697 #if 0 1698 tasklet_enable(&sc->sc_rxtq); 1699 #endif 1700 } 1701 1702 /* 1703 * Calculate the receive filter according to the 1704 * operating mode and state: 1705 * 1706 * o always accept unicast, broadcast, and multicast traffic 1707 * o maintain current state of phy error reception (the hal 1708 * may enable phy error frames for noise immunity work) 1709 * o probe request frames are accepted only when operating in 1710 * hostap, adhoc, or monitor modes 1711 * o enable promiscuous mode according to the interface state 1712 * o accept beacons: 1713 * - when operating in adhoc mode so the 802.11 layer creates 1714 * node table entries for peers, 1715 * - when operating in station mode for collecting rssi data when 1716 * the station is otherwise quiet, or 1717 * - when scanning 1718 */ 1719 static u_int32_t 1720 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1721 { 1722 struct ieee80211com *ic = &sc->sc_ic; 1723 struct ath_hal *ah = sc->sc_ah; 1724 struct ifnet *ifp = &sc->sc_if; 1725 u_int32_t rfilt; 1726 1727 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1728 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1729 if (ic->ic_opmode != IEEE80211_M_STA) 1730 rfilt |= HAL_RX_FILTER_PROBEREQ; 1731 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1732 (ifp->if_flags & IFF_PROMISC)) 1733 rfilt |= HAL_RX_FILTER_PROM; 1734 if (ic->ic_opmode == IEEE80211_M_STA || 1735 ic->ic_opmode == IEEE80211_M_IBSS || 1736 state == IEEE80211_S_SCAN) 1737 rfilt |= HAL_RX_FILTER_BEACON; 1738 return rfilt; 1739 } 1740 1741 static void 1742 ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1743 { 1744 u_int32_t val; 1745 u_int8_t pos; 1746 1747 /* calculate XOR of eight 6bit values */ 1748 val = LE_READ_4(dl + 0); 1749 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1750 val = LE_READ_4(dl + 3); 1751 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1752 pos &= 0x3f; 1753 mfilt[pos / 32] |= (1 << (pos % 32)); 1754 } 1755 1756 static void 1757 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1758 { 1759 struct ifnet *ifp = &sc->sc_if; 1760 struct ether_multi *enm; 1761 struct ether_multistep estep; 1762 1763 mfilt[0] = mfilt[1] = 0; 1764 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1765 while (enm != NULL) { 1766 /* XXX Punt on ranges. */ 1767 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1768 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1769 ifp->if_flags |= IFF_ALLMULTI; 1770 return; 1771 } 1772 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1773 ETHER_NEXT_MULTI(estep, enm); 1774 } 1775 ifp->if_flags &= ~IFF_ALLMULTI; 1776 } 1777 1778 static void 1779 ath_mode_init(struct ath_softc *sc) 1780 { 1781 struct ieee80211com *ic = &sc->sc_ic; 1782 struct ath_hal *ah = sc->sc_ah; 1783 u_int32_t rfilt, mfilt[2]; 1784 int i; 1785 1786 /* configure rx filter */ 1787 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1788 ath_hal_setrxfilter(ah, rfilt); 1789 1790 /* configure operational mode */ 1791 ath_hal_setopmode(ah); 1792 1793 /* Write keys to hardware; it may have been powered down. */ 1794 ath_key_update_begin(ic); 1795 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1796 ath_key_set(ic, 1797 &ic->ic_crypto.cs_nw_keys[i], 1798 ic->ic_myaddr); 1799 } 1800 ath_key_update_end(ic); 1801 1802 /* 1803 * Handle any link-level address change. Note that we only 1804 * need to force ic_myaddr; any other addresses are handled 1805 * as a byproduct of the ifnet code marking the interface 1806 * down then up. 1807 * 1808 * XXX should get from lladdr instead of arpcom but that's more work 1809 */ 1810 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1811 ath_hal_setmac(ah, ic->ic_myaddr); 1812 1813 /* calculate and install multicast filter */ 1814 #ifdef __FreeBSD__ 1815 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1816 mfilt[0] = mfilt[1] = 0; 1817 IF_ADDR_LOCK(ifp); 1818 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1819 caddr_t dl; 1820 1821 /* calculate XOR of eight 6bit values */ 1822 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1823 val = LE_READ_4(dl + 0); 1824 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1825 val = LE_READ_4(dl + 3); 1826 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1827 pos &= 0x3f; 1828 mfilt[pos / 32] |= (1 << (pos % 32)); 1829 } 1830 IF_ADDR_UNLOCK(ifp); 1831 } else { 1832 mfilt[0] = mfilt[1] = ~0; 1833 } 1834 #endif 1835 #ifdef __NetBSD__ 1836 ath_mcastfilter_compute(sc, mfilt); 1837 #endif 1838 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1839 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1840 __func__, rfilt, mfilt[0], mfilt[1]); 1841 } 1842 1843 /* 1844 * Set the slot time based on the current setting. 1845 */ 1846 static void 1847 ath_setslottime(struct ath_softc *sc) 1848 { 1849 struct ieee80211com *ic = &sc->sc_ic; 1850 struct ath_hal *ah = sc->sc_ah; 1851 1852 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1853 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1854 else 1855 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1856 sc->sc_updateslot = OK; 1857 } 1858 1859 /* 1860 * Callback from the 802.11 layer to update the 1861 * slot time based on the current setting. 1862 */ 1863 static void 1864 ath_updateslot(struct ifnet *ifp) 1865 { 1866 struct ath_softc *sc = ifp->if_softc; 1867 struct ieee80211com *ic = &sc->sc_ic; 1868 1869 /* 1870 * When not coordinating the BSS, change the hardware 1871 * immediately. For other operation we defer the change 1872 * until beacon updates have propagated to the stations. 1873 */ 1874 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1875 sc->sc_updateslot = UPDATE; 1876 else 1877 ath_setslottime(sc); 1878 } 1879 1880 /* 1881 * Setup a h/w transmit queue for beacons. 1882 */ 1883 static int 1884 ath_beaconq_setup(struct ath_hal *ah) 1885 { 1886 HAL_TXQ_INFO qi; 1887 1888 memset(&qi, 0, sizeof(qi)); 1889 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1890 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1891 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1892 /* NB: for dynamic turbo, don't enable any other interrupts */ 1893 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1894 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1895 } 1896 1897 /* 1898 * Setup the transmit queue parameters for the beacon queue. 1899 */ 1900 static int 1901 ath_beaconq_config(struct ath_softc *sc) 1902 { 1903 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1904 struct ieee80211com *ic = &sc->sc_ic; 1905 struct ath_hal *ah = sc->sc_ah; 1906 HAL_TXQ_INFO qi; 1907 1908 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1909 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1910 /* 1911 * Always burst out beacon and CAB traffic. 1912 */ 1913 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1914 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1915 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1916 } else { 1917 struct wmeParams *wmep = 1918 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1919 /* 1920 * Adhoc mode; important thing is to use 2x cwmin. 1921 */ 1922 qi.tqi_aifs = wmep->wmep_aifsn; 1923 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1924 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1925 } 1926 1927 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1928 device_printf(sc->sc_dev, "unable to update parameters for " 1929 "beacon hardware queue!\n"); 1930 return 0; 1931 } else { 1932 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1933 return 1; 1934 } 1935 #undef ATH_EXPONENT_TO_VALUE 1936 } 1937 1938 /* 1939 * Allocate and setup an initial beacon frame. 1940 */ 1941 static int 1942 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1943 { 1944 struct ieee80211com *ic = ni->ni_ic; 1945 struct ath_buf *bf; 1946 struct mbuf *m; 1947 int error; 1948 1949 bf = STAILQ_FIRST(&sc->sc_bbuf); 1950 if (bf == NULL) { 1951 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1952 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1953 return ENOMEM; /* XXX */ 1954 } 1955 /* 1956 * NB: the beacon data buffer must be 32-bit aligned; 1957 * we assume the mbuf routines will return us something 1958 * with this alignment (perhaps should assert). 1959 */ 1960 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1961 if (m == NULL) { 1962 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1963 __func__); 1964 sc->sc_stats.ast_be_nombuf++; 1965 return ENOMEM; 1966 } 1967 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1968 BUS_DMA_NOWAIT); 1969 if (error == 0) { 1970 bf->bf_m = m; 1971 bf->bf_node = ieee80211_ref_node(ni); 1972 } else { 1973 m_freem(m); 1974 } 1975 return error; 1976 } 1977 1978 /* 1979 * Setup the beacon frame for transmit. 1980 */ 1981 static void 1982 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1983 { 1984 #define USE_SHPREAMBLE(_ic) \ 1985 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1986 == IEEE80211_F_SHPREAMBLE) 1987 struct ieee80211_node *ni = bf->bf_node; 1988 struct ieee80211com *ic = ni->ni_ic; 1989 struct mbuf *m = bf->bf_m; 1990 struct ath_hal *ah = sc->sc_ah; 1991 struct ath_node *an = ATH_NODE(ni); 1992 struct ath_desc *ds; 1993 int flags, antenna; 1994 u_int8_t rate; 1995 1996 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1997 __func__, m, m->m_len); 1998 1999 /* setup descriptors */ 2000 ds = bf->bf_desc; 2001 2002 flags = HAL_TXDESC_NOACK; 2003 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2004 ds->ds_link = bf->bf_daddr; /* self-linked */ 2005 flags |= HAL_TXDESC_VEOL; 2006 /* 2007 * Let hardware handle antenna switching unless 2008 * the user has selected a transmit antenna 2009 * (sc_txantenna is not 0). 2010 */ 2011 antenna = sc->sc_txantenna; 2012 } else { 2013 ds->ds_link = 0; 2014 /* 2015 * Switch antenna every 4 beacons, unless the user 2016 * has selected a transmit antenna (sc_txantenna 2017 * is not 0). 2018 * 2019 * XXX assumes two antenna 2020 */ 2021 if (sc->sc_txantenna == 0) 2022 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2023 else 2024 antenna = sc->sc_txantenna; 2025 } 2026 2027 KASSERT(bf->bf_nseg == 1, 2028 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2029 ds->ds_data = bf->bf_segs[0].ds_addr; 2030 /* 2031 * Calculate rate code. 2032 * XXX everything at min xmit rate 2033 */ 2034 if (USE_SHPREAMBLE(ic)) 2035 rate = an->an_tx_mgtratesp; 2036 else 2037 rate = an->an_tx_mgtrate; 2038 ath_hal_setuptxdesc(ah, ds 2039 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2040 , sizeof(struct ieee80211_frame)/* header length */ 2041 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2042 , ni->ni_txpower /* txpower XXX */ 2043 , rate, 1 /* series 0 rate/tries */ 2044 , HAL_TXKEYIX_INVALID /* no encryption */ 2045 , antenna /* antenna mode */ 2046 , flags /* no ack, veol for beacons */ 2047 , 0 /* rts/cts rate */ 2048 , 0 /* rts/cts duration */ 2049 ); 2050 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2051 ath_hal_filltxdesc(ah, ds 2052 , roundup(m->m_len, 4) /* buffer length */ 2053 , AH_TRUE /* first segment */ 2054 , AH_TRUE /* last segment */ 2055 , ds /* first descriptor */ 2056 ); 2057 #undef USE_SHPREAMBLE 2058 } 2059 2060 /* 2061 * Transmit a beacon frame at SWBA. Dynamic updates to the 2062 * frame contents are done as needed and the slot time is 2063 * also adjusted based on current state. 2064 */ 2065 static void 2066 ath_beacon_proc(void *arg, int pending) 2067 { 2068 struct ath_softc *sc = arg; 2069 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2070 struct ieee80211_node *ni = bf->bf_node; 2071 struct ieee80211com *ic = ni->ni_ic; 2072 struct ath_hal *ah = sc->sc_ah; 2073 struct mbuf *m; 2074 int ncabq, error, otherant; 2075 2076 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2077 __func__, pending); 2078 2079 if (ic->ic_opmode == IEEE80211_M_STA || 2080 ic->ic_opmode == IEEE80211_M_MONITOR || 2081 bf == NULL || bf->bf_m == NULL) { 2082 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2083 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2084 return; 2085 } 2086 /* 2087 * Check if the previous beacon has gone out. If 2088 * not don't don't try to post another, skip this 2089 * period and wait for the next. Missed beacons 2090 * indicate a problem and should not occur. If we 2091 * miss too many consecutive beacons reset the device. 2092 */ 2093 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2094 sc->sc_bmisscount++; 2095 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2096 "%s: missed %u consecutive beacons\n", 2097 __func__, sc->sc_bmisscount); 2098 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2099 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2100 return; 2101 } 2102 if (sc->sc_bmisscount != 0) { 2103 DPRINTF(sc, ATH_DEBUG_BEACON, 2104 "%s: resume beacon xmit after %u misses\n", 2105 __func__, sc->sc_bmisscount); 2106 sc->sc_bmisscount = 0; 2107 } 2108 2109 /* 2110 * Update dynamic beacon contents. If this returns 2111 * non-zero then we need to remap the memory because 2112 * the beacon frame changed size (probably because 2113 * of the TIM bitmap). 2114 */ 2115 m = bf->bf_m; 2116 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2117 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2118 /* XXX too conservative? */ 2119 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2120 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2121 BUS_DMA_NOWAIT); 2122 if (error != 0) { 2123 if_printf(&sc->sc_if, 2124 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2125 __func__, error); 2126 return; 2127 } 2128 } 2129 2130 /* 2131 * Handle slot time change when a non-ERP station joins/leaves 2132 * an 11g network. The 802.11 layer notifies us via callback, 2133 * we mark updateslot, then wait one beacon before effecting 2134 * the change. This gives associated stations at least one 2135 * beacon interval to note the state change. 2136 */ 2137 /* XXX locking */ 2138 if (sc->sc_updateslot == UPDATE) 2139 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2140 else if (sc->sc_updateslot == COMMIT) 2141 ath_setslottime(sc); /* commit change to h/w */ 2142 2143 /* 2144 * Check recent per-antenna transmit statistics and flip 2145 * the default antenna if noticeably more frames went out 2146 * on the non-default antenna. 2147 * XXX assumes 2 anntenae 2148 */ 2149 otherant = sc->sc_defant & 1 ? 2 : 1; 2150 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2151 ath_setdefantenna(sc, otherant); 2152 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2153 2154 /* 2155 * Construct tx descriptor. 2156 */ 2157 ath_beacon_setup(sc, bf); 2158 2159 /* 2160 * Stop any current dma and put the new frame on the queue. 2161 * This should never fail since we check above that no frames 2162 * are still pending on the queue. 2163 */ 2164 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2165 DPRINTF(sc, ATH_DEBUG_ANY, 2166 "%s: beacon queue %u did not stop?\n", 2167 __func__, sc->sc_bhalq); 2168 } 2169 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2170 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2171 2172 /* 2173 * Enable the CAB queue before the beacon queue to 2174 * insure cab frames are triggered by this beacon. 2175 */ 2176 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2177 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2178 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2179 ath_hal_txstart(ah, sc->sc_bhalq); 2180 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2181 "%s: TXDP[%u] = %p (%p)\n", __func__, 2182 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2183 2184 sc->sc_stats.ast_be_xmit++; 2185 } 2186 2187 /* 2188 * Reset the hardware after detecting beacons have stopped. 2189 */ 2190 static void 2191 ath_bstuck_proc(void *arg, int pending) 2192 { 2193 struct ath_softc *sc = arg; 2194 struct ifnet *ifp = &sc->sc_if; 2195 2196 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2197 sc->sc_bmisscount); 2198 ath_reset(ifp); 2199 } 2200 2201 /* 2202 * Reclaim beacon resources. 2203 */ 2204 static void 2205 ath_beacon_free(struct ath_softc *sc) 2206 { 2207 struct ath_buf *bf; 2208 2209 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2210 if (bf->bf_m != NULL) { 2211 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2212 m_freem(bf->bf_m); 2213 bf->bf_m = NULL; 2214 } 2215 if (bf->bf_node != NULL) { 2216 ieee80211_free_node(bf->bf_node); 2217 bf->bf_node = NULL; 2218 } 2219 } 2220 } 2221 2222 /* 2223 * Configure the beacon and sleep timers. 2224 * 2225 * When operating as an AP this resets the TSF and sets 2226 * up the hardware to notify us when we need to issue beacons. 2227 * 2228 * When operating in station mode this sets up the beacon 2229 * timers according to the timestamp of the last received 2230 * beacon and the current TSF, configures PCF and DTIM 2231 * handling, programs the sleep registers so the hardware 2232 * will wakeup in time to receive beacons, and configures 2233 * the beacon miss handling so we'll receive a BMISS 2234 * interrupt when we stop seeing beacons from the AP 2235 * we've associated with. 2236 */ 2237 static void 2238 ath_beacon_config(struct ath_softc *sc) 2239 { 2240 #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) 2241 struct ath_hal *ah = sc->sc_ah; 2242 struct ieee80211com *ic = &sc->sc_ic; 2243 struct ieee80211_node *ni = ic->ic_bss; 2244 u_int32_t nexttbtt, intval; 2245 2246 /* extract tstamp from last beacon and convert to TU */ 2247 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2248 LE_READ_4(ni->ni_tstamp.data)); 2249 /* NB: the beacon interval is kept internally in TU's */ 2250 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2251 if (nexttbtt == 0) /* e.g. for ap mode */ 2252 nexttbtt = intval; 2253 else if (intval) /* NB: can be 0 for monitor mode */ 2254 nexttbtt = roundup(nexttbtt, intval); 2255 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2256 __func__, nexttbtt, intval, ni->ni_intval); 2257 if (ic->ic_opmode == IEEE80211_M_STA) { 2258 HAL_BEACON_STATE bs; 2259 u_int64_t tsf; 2260 u_int32_t tsftu; 2261 int dtimperiod, dtimcount; 2262 int cfpperiod, cfpcount; 2263 2264 /* 2265 * Setup dtim and cfp parameters according to 2266 * last beacon we received (which may be none). 2267 */ 2268 dtimperiod = ni->ni_dtim_period; 2269 if (dtimperiod <= 0) /* NB: 0 if not known */ 2270 dtimperiod = 1; 2271 dtimcount = ni->ni_dtim_count; 2272 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2273 dtimcount = 0; /* XXX? */ 2274 cfpperiod = 1; /* NB: no PCF support yet */ 2275 cfpcount = 0; 2276 #define FUDGE 2 2277 /* 2278 * Pull nexttbtt forward to reflect the current 2279 * TSF and calculate dtim+cfp state for the result. 2280 */ 2281 tsf = ath_hal_gettsf64(ah); 2282 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE; 2283 do { 2284 nexttbtt += intval; 2285 if (--dtimcount < 0) { 2286 dtimcount = dtimperiod - 1; 2287 if (--cfpcount < 0) 2288 cfpcount = cfpperiod - 1; 2289 } 2290 } while (nexttbtt < tsftu); 2291 #undef FUDGE 2292 memset(&bs, 0, sizeof(bs)); 2293 bs.bs_intval = intval; 2294 bs.bs_nexttbtt = nexttbtt; 2295 bs.bs_dtimperiod = dtimperiod*intval; 2296 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2297 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2298 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2299 bs.bs_cfpmaxduration = 0; 2300 #if 0 2301 /* 2302 * The 802.11 layer records the offset to the DTIM 2303 * bitmap while receiving beacons; use it here to 2304 * enable h/w detection of our AID being marked in 2305 * the bitmap vector (to indicate frames for us are 2306 * pending at the AP). 2307 * XXX do DTIM handling in s/w to WAR old h/w bugs 2308 * XXX enable based on h/w rev for newer chips 2309 */ 2310 bs.bs_timoffset = ni->ni_timoff; 2311 #endif 2312 /* 2313 * Calculate the number of consecutive beacons to miss 2314 * before taking a BMISS interrupt. The configuration 2315 * is specified in ms, so we need to convert that to 2316 * TU's and then calculate based on the beacon interval. 2317 * Note that we clamp the result to at most 10 beacons. 2318 */ 2319 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2320 if (bs.bs_bmissthreshold > 10) 2321 bs.bs_bmissthreshold = 10; 2322 else if (bs.bs_bmissthreshold <= 0) 2323 bs.bs_bmissthreshold = 1; 2324 2325 /* 2326 * Calculate sleep duration. The configuration is 2327 * given in ms. We insure a multiple of the beacon 2328 * period is used. Also, if the sleep duration is 2329 * greater than the DTIM period then it makes senses 2330 * to make it a multiple of that. 2331 * 2332 * XXX fixed at 100ms 2333 */ 2334 bs.bs_sleepduration = 2335 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2336 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2337 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2338 2339 DPRINTF(sc, ATH_DEBUG_BEACON, 2340 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2341 , __func__ 2342 , tsf, tsftu 2343 , bs.bs_intval 2344 , bs.bs_nexttbtt 2345 , bs.bs_dtimperiod 2346 , bs.bs_nextdtim 2347 , bs.bs_bmissthreshold 2348 , bs.bs_sleepduration 2349 , bs.bs_cfpperiod 2350 , bs.bs_cfpmaxduration 2351 , bs.bs_cfpnext 2352 , bs.bs_timoffset 2353 ); 2354 ath_hal_intrset(ah, 0); 2355 ath_hal_beacontimers(ah, &bs); 2356 sc->sc_imask |= HAL_INT_BMISS; 2357 ath_hal_intrset(ah, sc->sc_imask); 2358 } else { 2359 ath_hal_intrset(ah, 0); 2360 if (nexttbtt == intval) 2361 intval |= HAL_BEACON_RESET_TSF; 2362 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2363 /* 2364 * In IBSS mode enable the beacon timers but only 2365 * enable SWBA interrupts if we need to manually 2366 * prepare beacon frames. Otherwise we use a 2367 * self-linked tx descriptor and let the hardware 2368 * deal with things. 2369 */ 2370 intval |= HAL_BEACON_ENA; 2371 if (!sc->sc_hasveol) 2372 sc->sc_imask |= HAL_INT_SWBA; 2373 ath_beaconq_config(sc); 2374 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2375 /* 2376 * In AP mode we enable the beacon timers and 2377 * SWBA interrupts to prepare beacon frames. 2378 */ 2379 intval |= HAL_BEACON_ENA; 2380 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2381 ath_beaconq_config(sc); 2382 } 2383 ath_hal_beaconinit(ah, nexttbtt, intval); 2384 sc->sc_bmisscount = 0; 2385 ath_hal_intrset(ah, sc->sc_imask); 2386 /* 2387 * When using a self-linked beacon descriptor in 2388 * ibss mode load it once here. 2389 */ 2390 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2391 ath_beacon_proc(sc, 0); 2392 } 2393 #undef TSF_TO_TU 2394 } 2395 2396 static int 2397 ath_descdma_setup(struct ath_softc *sc, 2398 struct ath_descdma *dd, ath_bufhead *head, 2399 const char *name, int nbuf, int ndesc) 2400 { 2401 #define DS2PHYS(_dd, _ds) \ 2402 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2403 struct ifnet *ifp = &sc->sc_if; 2404 struct ath_desc *ds; 2405 struct ath_buf *bf; 2406 int i, bsize, error; 2407 2408 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2409 __func__, name, nbuf, ndesc); 2410 2411 dd->dd_name = name; 2412 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2413 2414 /* 2415 * Setup DMA descriptor area. 2416 */ 2417 dd->dd_dmat = sc->sc_dmat; 2418 2419 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2420 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2421 2422 if (error != 0) { 2423 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2424 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2425 goto fail0; 2426 } 2427 2428 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2429 dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2430 if (error != 0) { 2431 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2432 nbuf * ndesc, dd->dd_name, error); 2433 goto fail1; 2434 } 2435 2436 /* allocate descriptors */ 2437 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2438 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2439 if (error != 0) { 2440 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2441 "error %u\n", dd->dd_name, error); 2442 goto fail2; 2443 } 2444 2445 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2446 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2447 if (error != 0) { 2448 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2449 dd->dd_name, error); 2450 goto fail3; 2451 } 2452 2453 ds = dd->dd_desc; 2454 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2455 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2456 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2457 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2458 2459 /* allocate rx buffers */ 2460 bsize = sizeof(struct ath_buf) * nbuf; 2461 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2462 if (bf == NULL) { 2463 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2464 dd->dd_name, bsize); 2465 goto fail4; 2466 } 2467 dd->dd_bufptr = bf; 2468 2469 STAILQ_INIT(head); 2470 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2471 bf->bf_desc = ds; 2472 bf->bf_daddr = DS2PHYS(dd, ds); 2473 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2474 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2475 if (error != 0) { 2476 if_printf(ifp, "unable to create dmamap for %s " 2477 "buffer %u, error %u\n", dd->dd_name, i, error); 2478 ath_descdma_cleanup(sc, dd, head); 2479 return error; 2480 } 2481 STAILQ_INSERT_TAIL(head, bf, bf_list); 2482 } 2483 return 0; 2484 fail4: 2485 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2486 fail3: 2487 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2488 fail2: 2489 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2490 fail1: 2491 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2492 fail0: 2493 memset(dd, 0, sizeof(*dd)); 2494 return error; 2495 #undef DS2PHYS 2496 } 2497 2498 static void 2499 ath_descdma_cleanup(struct ath_softc *sc, 2500 struct ath_descdma *dd, ath_bufhead *head) 2501 { 2502 struct ath_buf *bf; 2503 struct ieee80211_node *ni; 2504 2505 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2506 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2507 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2508 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2509 2510 STAILQ_FOREACH(bf, head, bf_list) { 2511 if (bf->bf_m) { 2512 m_freem(bf->bf_m); 2513 bf->bf_m = NULL; 2514 } 2515 if (bf->bf_dmamap != NULL) { 2516 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2517 bf->bf_dmamap = NULL; 2518 } 2519 ni = bf->bf_node; 2520 bf->bf_node = NULL; 2521 if (ni != NULL) { 2522 /* 2523 * Reclaim node reference. 2524 */ 2525 ieee80211_free_node(ni); 2526 } 2527 } 2528 2529 STAILQ_INIT(head); 2530 free(dd->dd_bufptr, M_ATHDEV); 2531 memset(dd, 0, sizeof(*dd)); 2532 } 2533 2534 static int 2535 ath_desc_alloc(struct ath_softc *sc) 2536 { 2537 int error; 2538 2539 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2540 "rx", ATH_RXBUF, 1); 2541 if (error != 0) 2542 return error; 2543 2544 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2545 "tx", ATH_TXBUF, ATH_TXDESC); 2546 if (error != 0) { 2547 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2548 return error; 2549 } 2550 2551 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2552 "beacon", 1, 1); 2553 if (error != 0) { 2554 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2555 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2556 return error; 2557 } 2558 return 0; 2559 } 2560 2561 static void 2562 ath_desc_free(struct ath_softc *sc) 2563 { 2564 2565 if (sc->sc_bdma.dd_desc_len != 0) 2566 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2567 if (sc->sc_txdma.dd_desc_len != 0) 2568 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2569 if (sc->sc_rxdma.dd_desc_len != 0) 2570 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2571 } 2572 2573 static struct ieee80211_node * 2574 ath_node_alloc(struct ieee80211_node_table *nt) 2575 { 2576 struct ieee80211com *ic = nt->nt_ic; 2577 struct ath_softc *sc = ic->ic_ifp->if_softc; 2578 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2579 struct ath_node *an; 2580 2581 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2582 if (an == NULL) { 2583 /* XXX stat+msg */ 2584 return NULL; 2585 } 2586 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2587 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2588 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2589 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2590 ath_rate_node_init(sc, an); 2591 2592 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2593 return &an->an_node; 2594 } 2595 2596 static void 2597 ath_node_free(struct ieee80211_node *ni) 2598 { 2599 struct ieee80211com *ic = ni->ni_ic; 2600 struct ath_softc *sc = ic->ic_ifp->if_softc; 2601 2602 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2603 2604 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2605 sc->sc_node_free(ni); 2606 } 2607 2608 static u_int8_t 2609 ath_node_getrssi(const struct ieee80211_node *ni) 2610 { 2611 #define HAL_EP_RND(x, mul) \ 2612 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2613 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2614 int32_t rssi; 2615 2616 /* 2617 * When only one frame is received there will be no state in 2618 * avgrssi so fallback on the value recorded by the 802.11 layer. 2619 */ 2620 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2621 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2622 else 2623 rssi = ni->ni_rssi; 2624 /* NB: theoretically we shouldn't need this, but be paranoid */ 2625 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2626 #undef HAL_EP_RND 2627 } 2628 2629 static int 2630 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2631 { 2632 struct ath_hal *ah = sc->sc_ah; 2633 int error; 2634 struct mbuf *m; 2635 struct ath_desc *ds; 2636 2637 m = bf->bf_m; 2638 if (m == NULL) { 2639 /* 2640 * NB: by assigning a page to the rx dma buffer we 2641 * implicitly satisfy the Atheros requirement that 2642 * this buffer be cache-line-aligned and sized to be 2643 * multiple of the cache line size. Not doing this 2644 * causes weird stuff to happen (for the 5210 at least). 2645 */ 2646 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2647 if (m == NULL) { 2648 DPRINTF(sc, ATH_DEBUG_ANY, 2649 "%s: no mbuf/cluster\n", __func__); 2650 sc->sc_stats.ast_rx_nombuf++; 2651 return ENOMEM; 2652 } 2653 bf->bf_m = m; 2654 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2655 2656 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2657 bf->bf_dmamap, m, 2658 BUS_DMA_NOWAIT); 2659 if (error != 0) { 2660 DPRINTF(sc, ATH_DEBUG_ANY, 2661 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2662 __func__, error); 2663 sc->sc_stats.ast_rx_busdma++; 2664 return error; 2665 } 2666 KASSERT(bf->bf_nseg == 1, 2667 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2668 } 2669 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2670 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2671 2672 /* 2673 * Setup descriptors. For receive we always terminate 2674 * the descriptor list with a self-linked entry so we'll 2675 * not get overrun under high load (as can happen with a 2676 * 5212 when ANI processing enables PHY error frames). 2677 * 2678 * To insure the last descriptor is self-linked we create 2679 * each descriptor as self-linked and add it to the end. As 2680 * each additional descriptor is added the previous self-linked 2681 * entry is ``fixed'' naturally. This should be safe even 2682 * if DMA is happening. When processing RX interrupts we 2683 * never remove/process the last, self-linked, entry on the 2684 * descriptor list. This insures the hardware always has 2685 * someplace to write a new frame. 2686 */ 2687 ds = bf->bf_desc; 2688 ds->ds_link = bf->bf_daddr; /* link to self */ 2689 ds->ds_data = bf->bf_segs[0].ds_addr; 2690 ath_hal_setuprxdesc(ah, ds 2691 , m->m_len /* buffer size */ 2692 , 0 2693 ); 2694 2695 if (sc->sc_rxlink != NULL) 2696 *sc->sc_rxlink = bf->bf_daddr; 2697 sc->sc_rxlink = &ds->ds_link; 2698 return 0; 2699 } 2700 2701 /* 2702 * Extend 15-bit time stamp from rx descriptor to 2703 * a full 64-bit TSF using the current h/w TSF. 2704 */ 2705 static inline u_int64_t 2706 ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp) 2707 { 2708 u_int64_t tsf; 2709 2710 tsf = ath_hal_gettsf64(ah); 2711 if ((tsf & 0x7fff) < rstamp) 2712 tsf -= 0x8000; 2713 return ((tsf &~ 0x7fff) | rstamp); 2714 } 2715 2716 /* 2717 * Intercept management frames to collect beacon rssi data 2718 * and to do ibss merges. 2719 */ 2720 static void 2721 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2722 struct ieee80211_node *ni, 2723 int subtype, int rssi, u_int32_t rstamp) 2724 { 2725 struct ath_softc *sc = ic->ic_ifp->if_softc; 2726 2727 /* 2728 * Call up first so subsequent work can use information 2729 * potentially stored in the node (e.g. for ibss merge). 2730 */ 2731 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2732 switch (subtype) { 2733 case IEEE80211_FC0_SUBTYPE_BEACON: 2734 /* update rssi statistics for use by the hal */ 2735 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2736 /* fall thru... */ 2737 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2738 if (ic->ic_opmode == IEEE80211_M_IBSS && 2739 ic->ic_state == IEEE80211_S_RUN) { 2740 u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp); 2741 2742 /* 2743 * Handle ibss merge as needed; check the tsf on the 2744 * frame before attempting the merge. The 802.11 spec 2745 * says the station should change it's bssid to match 2746 * the oldest station with the same ssid, where oldest 2747 * is determined by the tsf. Note that hardware 2748 * reconfiguration happens through callback to 2749 * ath_newstate as the state machine will go from 2750 * RUN -> RUN when this happens. 2751 */ 2752 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2753 DPRINTF(sc, ATH_DEBUG_STATE, 2754 "ibss merge, rstamp %u tsf %ju " 2755 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2756 (uintmax_t)ni->ni_tstamp.tsf); 2757 (void) ieee80211_ibss_merge(ni); 2758 } 2759 } 2760 break; 2761 } 2762 } 2763 2764 /* 2765 * Set the default antenna. 2766 */ 2767 static void 2768 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2769 { 2770 struct ath_hal *ah = sc->sc_ah; 2771 2772 /* XXX block beacon interrupts */ 2773 ath_hal_setdefantenna(ah, antenna); 2774 if (sc->sc_defant != antenna) 2775 sc->sc_stats.ast_ant_defswitch++; 2776 sc->sc_defant = antenna; 2777 sc->sc_rxotherant = 0; 2778 } 2779 2780 static void 2781 ath_rx_proc(void *arg, int npending) 2782 { 2783 #define PA2DESC(_sc, _pa) \ 2784 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2785 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2786 struct ath_softc *sc = arg; 2787 struct ath_buf *bf; 2788 struct ieee80211com *ic = &sc->sc_ic; 2789 struct ifnet *ifp = &sc->sc_if; 2790 struct ath_hal *ah = sc->sc_ah; 2791 struct ath_desc *ds; 2792 struct mbuf *m; 2793 struct ieee80211_node *ni; 2794 struct ath_node *an; 2795 int len, type; 2796 u_int phyerr; 2797 HAL_STATUS status; 2798 2799 NET_LOCK_GIANT(); /* XXX */ 2800 2801 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2802 do { 2803 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2804 if (bf == NULL) { /* NB: shouldn't happen */ 2805 if_printf(ifp, "%s: no buffer!\n", __func__); 2806 break; 2807 } 2808 ds = bf->bf_desc; 2809 if (ds->ds_link == bf->bf_daddr) { 2810 /* NB: never process the self-linked entry at the end */ 2811 break; 2812 } 2813 m = bf->bf_m; 2814 if (m == NULL) { /* NB: shouldn't happen */ 2815 if_printf(ifp, "%s: no mbuf!\n", __func__); 2816 continue; 2817 } 2818 /* XXX sync descriptor memory */ 2819 /* 2820 * Must provide the virtual address of the current 2821 * descriptor, the physical address, and the virtual 2822 * address of the next descriptor in the h/w chain. 2823 * This allows the HAL to look ahead to see if the 2824 * hardware is done with a descriptor by checking the 2825 * done bit in the following descriptor and the address 2826 * of the current descriptor the DMA engine is working 2827 * on. All this is necessary because of our use of 2828 * a self-linked list to avoid rx overruns. 2829 */ 2830 status = ath_hal_rxprocdesc(ah, ds, 2831 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2832 #ifdef AR_DEBUG 2833 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2834 ath_printrxbuf(bf, status == HAL_OK); 2835 #endif 2836 if (status == HAL_EINPROGRESS) 2837 break; 2838 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2839 if (ds->ds_rxstat.rs_more) { 2840 /* 2841 * Frame spans multiple descriptors; this 2842 * cannot happen yet as we don't support 2843 * jumbograms. If not in monitor mode, 2844 * discard the frame. 2845 */ 2846 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2847 sc->sc_stats.ast_rx_toobig++; 2848 goto rx_next; 2849 } 2850 /* fall thru for monitor mode handling... */ 2851 } else if (ds->ds_rxstat.rs_status != 0) { 2852 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2853 sc->sc_stats.ast_rx_crcerr++; 2854 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2855 sc->sc_stats.ast_rx_fifoerr++; 2856 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2857 sc->sc_stats.ast_rx_phyerr++; 2858 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2859 sc->sc_stats.ast_rx_phy[phyerr]++; 2860 goto rx_next; 2861 } 2862 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2863 /* 2864 * Decrypt error. If the error occurred 2865 * because there was no hardware key, then 2866 * let the frame through so the upper layers 2867 * can process it. This is necessary for 5210 2868 * parts which have no way to setup a ``clear'' 2869 * key cache entry. 2870 * 2871 * XXX do key cache faulting 2872 */ 2873 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2874 goto rx_accept; 2875 sc->sc_stats.ast_rx_badcrypt++; 2876 } 2877 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2878 sc->sc_stats.ast_rx_badmic++; 2879 /* 2880 * Do minimal work required to hand off 2881 * the 802.11 header for notifcation. 2882 */ 2883 /* XXX frag's and qos frames */ 2884 len = ds->ds_rxstat.rs_datalen; 2885 if (len >= sizeof (struct ieee80211_frame)) { 2886 bus_dmamap_sync(sc->sc_dmat, 2887 bf->bf_dmamap, 2888 0, bf->bf_dmamap->dm_mapsize, 2889 BUS_DMASYNC_POSTREAD); 2890 ieee80211_notify_michael_failure(ic, 2891 mtod(m, struct ieee80211_frame *), 2892 sc->sc_splitmic ? 2893 ds->ds_rxstat.rs_keyix-32 : 2894 ds->ds_rxstat.rs_keyix 2895 ); 2896 } 2897 } 2898 ifp->if_ierrors++; 2899 /* 2900 * Reject error frames, we normally don't want 2901 * to see them in monitor mode (in monitor mode 2902 * allow through packets that have crypto problems). 2903 */ 2904 if ((ds->ds_rxstat.rs_status &~ 2905 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2906 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2907 goto rx_next; 2908 } 2909 rx_accept: 2910 /* 2911 * Sync and unmap the frame. At this point we're 2912 * committed to passing the mbuf somewhere so clear 2913 * bf_m; this means a new sk_buff must be allocated 2914 * when the rx descriptor is setup again to receive 2915 * another frame. 2916 */ 2917 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2918 0, bf->bf_dmamap->dm_mapsize, 2919 BUS_DMASYNC_POSTREAD); 2920 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2921 bf->bf_m = NULL; 2922 2923 m->m_pkthdr.rcvif = ifp; 2924 len = ds->ds_rxstat.rs_datalen; 2925 m->m_pkthdr.len = m->m_len = len; 2926 2927 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2928 2929 #if NBPFILTER > 0 2930 if (sc->sc_drvbpf) { 2931 u_int8_t rix; 2932 2933 /* 2934 * Discard anything shorter than an ack or cts. 2935 */ 2936 if (len < IEEE80211_ACK_LEN) { 2937 DPRINTF(sc, ATH_DEBUG_RECV, 2938 "%s: runt packet %d\n", 2939 __func__, len); 2940 sc->sc_stats.ast_rx_tooshort++; 2941 m_freem(m); 2942 goto rx_next; 2943 } 2944 rix = ds->ds_rxstat.rs_rate; 2945 sc->sc_rx_th.wr_tsf = ath_extend_tsf(sc->sc_ah, 2946 ds->ds_rxstat.rs_tstamp); 2947 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2948 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2949 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2950 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2951 2952 bpf_mtap2(sc->sc_drvbpf, 2953 &sc->sc_rx_th, sc->sc_rx_th_len, m); 2954 } 2955 #endif 2956 2957 /* 2958 * From this point on we assume the frame is at least 2959 * as large as ieee80211_frame_min; verify that. 2960 */ 2961 if (len < IEEE80211_MIN_LEN) { 2962 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2963 __func__, len); 2964 sc->sc_stats.ast_rx_tooshort++; 2965 m_freem(m); 2966 goto rx_next; 2967 } 2968 2969 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2970 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2971 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2972 ds->ds_rxstat.rs_rssi); 2973 } 2974 2975 m_adj(m, -IEEE80211_CRC_LEN); 2976 2977 /* 2978 * Locate the node for sender, track state, and then 2979 * pass the (referenced) node up to the 802.11 layer 2980 * for its use. 2981 */ 2982 ni = ieee80211_find_rxnode_withkey(ic, 2983 mtod(m, const struct ieee80211_frame_min *), 2984 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 2985 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 2986 /* 2987 * Track rx rssi and do any rx antenna management. 2988 */ 2989 an = ATH_NODE(ni); 2990 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2991 /* 2992 * Send frame up for processing. 2993 */ 2994 type = ieee80211_input(ic, m, ni, 2995 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2996 ieee80211_free_node(ni); 2997 if (sc->sc_diversity) { 2998 /* 2999 * When using fast diversity, change the default rx 3000 * antenna if diversity chooses the other antenna 3 3001 * times in a row. 3002 */ 3003 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3004 if (++sc->sc_rxotherant >= 3) 3005 ath_setdefantenna(sc, 3006 ds->ds_rxstat.rs_antenna); 3007 } else 3008 sc->sc_rxotherant = 0; 3009 } 3010 if (sc->sc_softled) { 3011 /* 3012 * Blink for any data frame. Otherwise do a 3013 * heartbeat-style blink when idle. The latter 3014 * is mainly for station mode where we depend on 3015 * periodic beacon frames to trigger the poll event. 3016 */ 3017 if (type == IEEE80211_FC0_TYPE_DATA) { 3018 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3019 ath_led_event(sc, ATH_LED_RX); 3020 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3021 ath_led_event(sc, ATH_LED_POLL); 3022 } 3023 rx_next: 3024 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3025 } while (ath_rxbuf_init(sc, bf) == 0); 3026 3027 /* rx signal state monitoring */ 3028 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 3029 3030 #ifdef __NetBSD__ 3031 /* XXX Why isn't this necessary in FreeBSD? */ 3032 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3033 ath_start(ifp); 3034 #endif /* __NetBSD__ */ 3035 3036 NET_UNLOCK_GIANT(); /* XXX */ 3037 #undef PA2DESC 3038 } 3039 3040 /* 3041 * Setup a h/w transmit queue. 3042 */ 3043 static struct ath_txq * 3044 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3045 { 3046 #define N(a) (sizeof(a)/sizeof(a[0])) 3047 struct ath_hal *ah = sc->sc_ah; 3048 HAL_TXQ_INFO qi; 3049 int qnum; 3050 3051 memset(&qi, 0, sizeof(qi)); 3052 qi.tqi_subtype = subtype; 3053 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3054 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3055 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3056 /* 3057 * Enable interrupts only for EOL and DESC conditions. 3058 * We mark tx descriptors to receive a DESC interrupt 3059 * when a tx queue gets deep; otherwise waiting for the 3060 * EOL to reap descriptors. Note that this is done to 3061 * reduce interrupt load and this only defers reaping 3062 * descriptors, never transmitting frames. Aside from 3063 * reducing interrupts this also permits more concurrency. 3064 * The only potential downside is if the tx queue backs 3065 * up in which case the top half of the kernel may backup 3066 * due to a lack of tx descriptors. 3067 */ 3068 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 3069 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3070 if (qnum == -1) { 3071 /* 3072 * NB: don't print a message, this happens 3073 * normally on parts with too few tx queues 3074 */ 3075 return NULL; 3076 } 3077 if (qnum >= N(sc->sc_txq)) { 3078 device_printf(sc->sc_dev, 3079 "hal qnum %u out of range, max %zu!\n", 3080 qnum, N(sc->sc_txq)); 3081 ath_hal_releasetxqueue(ah, qnum); 3082 return NULL; 3083 } 3084 if (!ATH_TXQ_SETUP(sc, qnum)) { 3085 struct ath_txq *txq = &sc->sc_txq[qnum]; 3086 3087 txq->axq_qnum = qnum; 3088 txq->axq_depth = 0; 3089 txq->axq_intrcnt = 0; 3090 txq->axq_link = NULL; 3091 STAILQ_INIT(&txq->axq_q); 3092 ATH_TXQ_LOCK_INIT(sc, txq); 3093 sc->sc_txqsetup |= 1<<qnum; 3094 } 3095 return &sc->sc_txq[qnum]; 3096 #undef N 3097 } 3098 3099 /* 3100 * Setup a hardware data transmit queue for the specified 3101 * access control. The hal may not support all requested 3102 * queues in which case it will return a reference to a 3103 * previously setup queue. We record the mapping from ac's 3104 * to h/w queues for use by ath_tx_start and also track 3105 * the set of h/w queues being used to optimize work in the 3106 * transmit interrupt handler and related routines. 3107 */ 3108 static int 3109 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3110 { 3111 #define N(a) (sizeof(a)/sizeof(a[0])) 3112 struct ath_txq *txq; 3113 3114 if (ac >= N(sc->sc_ac2q)) { 3115 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3116 ac, N(sc->sc_ac2q)); 3117 return 0; 3118 } 3119 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3120 if (txq != NULL) { 3121 sc->sc_ac2q[ac] = txq; 3122 return 1; 3123 } else 3124 return 0; 3125 #undef N 3126 } 3127 3128 /* 3129 * Update WME parameters for a transmit queue. 3130 */ 3131 static int 3132 ath_txq_update(struct ath_softc *sc, int ac) 3133 { 3134 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3135 #define ATH_TXOP_TO_US(v) (v<<5) 3136 struct ieee80211com *ic = &sc->sc_ic; 3137 struct ath_txq *txq = sc->sc_ac2q[ac]; 3138 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3139 struct ath_hal *ah = sc->sc_ah; 3140 HAL_TXQ_INFO qi; 3141 3142 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3143 qi.tqi_aifs = wmep->wmep_aifsn; 3144 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3145 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3146 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3147 3148 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3149 device_printf(sc->sc_dev, "unable to update hardware queue " 3150 "parameters for %s traffic!\n", 3151 ieee80211_wme_acnames[ac]); 3152 return 0; 3153 } else { 3154 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3155 return 1; 3156 } 3157 #undef ATH_TXOP_TO_US 3158 #undef ATH_EXPONENT_TO_VALUE 3159 } 3160 3161 /* 3162 * Callback from the 802.11 layer to update WME parameters. 3163 */ 3164 static int 3165 ath_wme_update(struct ieee80211com *ic) 3166 { 3167 struct ath_softc *sc = ic->ic_ifp->if_softc; 3168 3169 return !ath_txq_update(sc, WME_AC_BE) || 3170 !ath_txq_update(sc, WME_AC_BK) || 3171 !ath_txq_update(sc, WME_AC_VI) || 3172 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3173 } 3174 3175 /* 3176 * Reclaim resources for a setup queue. 3177 */ 3178 static void 3179 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3180 { 3181 3182 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3183 ATH_TXQ_LOCK_DESTROY(txq); 3184 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3185 } 3186 3187 /* 3188 * Reclaim all tx queue resources. 3189 */ 3190 static void 3191 ath_tx_cleanup(struct ath_softc *sc) 3192 { 3193 int i; 3194 3195 ATH_TXBUF_LOCK_DESTROY(sc); 3196 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3197 if (ATH_TXQ_SETUP(sc, i)) 3198 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3199 } 3200 3201 /* 3202 * Defragment an mbuf chain, returning at most maxfrags separate 3203 * mbufs+clusters. If this is not possible NULL is returned and 3204 * the original mbuf chain is left in it's present (potentially 3205 * modified) state. We use two techniques: collapsing consecutive 3206 * mbufs and replacing consecutive mbufs by a cluster. 3207 */ 3208 static struct mbuf * 3209 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3210 { 3211 struct mbuf *m, *n, *n2, **prev; 3212 u_int curfrags; 3213 3214 /* 3215 * Calculate the current number of frags. 3216 */ 3217 curfrags = 0; 3218 for (m = m0; m != NULL; m = m->m_next) 3219 curfrags++; 3220 /* 3221 * First, try to collapse mbufs. Note that we always collapse 3222 * towards the front so we don't need to deal with moving the 3223 * pkthdr. This may be suboptimal if the first mbuf has much 3224 * less data than the following. 3225 */ 3226 m = m0; 3227 again: 3228 for (;;) { 3229 n = m->m_next; 3230 if (n == NULL) 3231 break; 3232 if ((m->m_flags & M_RDONLY) == 0 && 3233 n->m_len < M_TRAILINGSPACE(m)) { 3234 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3235 n->m_len); 3236 m->m_len += n->m_len; 3237 m->m_next = n->m_next; 3238 m_free(n); 3239 if (--curfrags <= maxfrags) 3240 return m0; 3241 } else 3242 m = n; 3243 } 3244 KASSERT(maxfrags > 1, 3245 ("maxfrags %u, but normal collapse failed", maxfrags)); 3246 /* 3247 * Collapse consecutive mbufs to a cluster. 3248 */ 3249 prev = &m0->m_next; /* NB: not the first mbuf */ 3250 while ((n = *prev) != NULL) { 3251 if ((n2 = n->m_next) != NULL && 3252 n->m_len + n2->m_len < MCLBYTES) { 3253 m = m_getcl(how, MT_DATA, 0); 3254 if (m == NULL) 3255 goto bad; 3256 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3257 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3258 n2->m_len); 3259 m->m_len = n->m_len + n2->m_len; 3260 m->m_next = n2->m_next; 3261 *prev = m; 3262 m_free(n); 3263 m_free(n2); 3264 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3265 return m0; 3266 /* 3267 * Still not there, try the normal collapse 3268 * again before we allocate another cluster. 3269 */ 3270 goto again; 3271 } 3272 prev = &n->m_next; 3273 } 3274 /* 3275 * No place where we can collapse to a cluster; punt. 3276 * This can occur if, for example, you request 2 frags 3277 * but the packet requires that both be clusters (we 3278 * never reallocate the first mbuf to avoid moving the 3279 * packet header). 3280 */ 3281 bad: 3282 return NULL; 3283 } 3284 3285 static int 3286 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3287 struct mbuf *m0) 3288 { 3289 #define CTS_DURATION \ 3290 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE) 3291 #define updateCTSForBursting(_ah, _ds, _txq) \ 3292 ath_hal_updateCTSForBursting(_ah, _ds, \ 3293 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ 3294 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ 3295 txopLimit, CTS_DURATION) 3296 struct ieee80211com *ic = &sc->sc_ic; 3297 struct ath_hal *ah = sc->sc_ah; 3298 struct ifnet *ifp = &sc->sc_if; 3299 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3300 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3301 u_int8_t rix, txrate, ctsrate; 3302 u_int8_t cix = 0xff; /* NB: silence compiler */ 3303 struct ath_desc *ds, *ds0; 3304 struct ath_txq *txq; 3305 struct ieee80211_frame *wh; 3306 u_int subtype, flags, ctsduration; 3307 HAL_PKT_TYPE atype; 3308 const HAL_RATE_TABLE *rt; 3309 HAL_BOOL shortPreamble; 3310 struct ath_node *an; 3311 struct mbuf *m; 3312 u_int pri; 3313 3314 wh = mtod(m0, struct ieee80211_frame *); 3315 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3316 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3317 hdrlen = ieee80211_anyhdrsize(wh); 3318 /* 3319 * Packet length must not include any 3320 * pad bytes; deduct them here. 3321 */ 3322 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3323 3324 if (iswep) { 3325 const struct ieee80211_cipher *cip; 3326 struct ieee80211_key *k; 3327 3328 /* 3329 * Construct the 802.11 header+trailer for an encrypted 3330 * frame. The only reason this can fail is because of an 3331 * unknown or unsupported cipher/key type. 3332 */ 3333 k = ieee80211_crypto_encap(ic, ni, m0); 3334 if (k == NULL) { 3335 /* 3336 * This can happen when the key is yanked after the 3337 * frame was queued. Just discard the frame; the 3338 * 802.11 layer counts failures and provides 3339 * debugging/diagnostics. 3340 */ 3341 m_freem(m0); 3342 return EIO; 3343 } 3344 /* 3345 * Adjust the packet + header lengths for the crypto 3346 * additions and calculate the h/w key index. When 3347 * a s/w mic is done the frame will have had any mic 3348 * added to it prior to entry so skb->len above will 3349 * account for it. Otherwise we need to add it to the 3350 * packet length. 3351 */ 3352 cip = k->wk_cipher; 3353 hdrlen += cip->ic_header; 3354 pktlen += cip->ic_header + cip->ic_trailer; 3355 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3356 pktlen += cip->ic_miclen; 3357 keyix = k->wk_keyix; 3358 3359 /* packet header may have moved, reset our local pointer */ 3360 wh = mtod(m0, struct ieee80211_frame *); 3361 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3362 /* 3363 * Use station key cache slot, if assigned. 3364 */ 3365 keyix = ni->ni_ucastkey.wk_keyix; 3366 if (keyix == IEEE80211_KEYIX_NONE) 3367 keyix = HAL_TXKEYIX_INVALID; 3368 } else 3369 keyix = HAL_TXKEYIX_INVALID; 3370 3371 pktlen += IEEE80211_CRC_LEN; 3372 3373 /* 3374 * Load the DMA map so any coalescing is done. This 3375 * also calculates the number of descriptors we need. 3376 */ 3377 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3378 BUS_DMA_NOWAIT); 3379 if (error == EFBIG) { 3380 /* XXX packet requires too many descriptors */ 3381 bf->bf_nseg = ATH_TXDESC+1; 3382 } else if (error != 0) { 3383 sc->sc_stats.ast_tx_busdma++; 3384 m_freem(m0); 3385 return error; 3386 } 3387 /* 3388 * Discard null packets and check for packets that 3389 * require too many TX descriptors. We try to convert 3390 * the latter to a cluster. 3391 */ 3392 if (error == EFBIG) { /* too many desc's, linearize */ 3393 sc->sc_stats.ast_tx_linear++; 3394 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3395 if (m == NULL) { 3396 m_freem(m0); 3397 sc->sc_stats.ast_tx_nombuf++; 3398 return ENOMEM; 3399 } 3400 m0 = m; 3401 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3402 BUS_DMA_NOWAIT); 3403 if (error != 0) { 3404 sc->sc_stats.ast_tx_busdma++; 3405 m_freem(m0); 3406 return error; 3407 } 3408 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3409 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3410 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3411 sc->sc_stats.ast_tx_nodata++; 3412 m_freem(m0); 3413 return EIO; 3414 } 3415 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3416 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3417 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3418 bf->bf_m = m0; 3419 bf->bf_node = ni; /* NB: held reference */ 3420 3421 /* setup descriptors */ 3422 ds = bf->bf_desc; 3423 rt = sc->sc_currates; 3424 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3425 3426 /* 3427 * NB: the 802.11 layer marks whether or not we should 3428 * use short preamble based on the current mode and 3429 * negotiated parameters. 3430 */ 3431 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3432 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3433 shortPreamble = AH_TRUE; 3434 sc->sc_stats.ast_tx_shortpre++; 3435 } else { 3436 shortPreamble = AH_FALSE; 3437 } 3438 3439 an = ATH_NODE(ni); 3440 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3441 /* 3442 * Calculate Atheros packet type from IEEE80211 packet header, 3443 * setup for rate calculations, and select h/w transmit queue. 3444 */ 3445 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3446 case IEEE80211_FC0_TYPE_MGT: 3447 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3448 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3449 atype = HAL_PKT_TYPE_BEACON; 3450 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3451 atype = HAL_PKT_TYPE_PROBE_RESP; 3452 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3453 atype = HAL_PKT_TYPE_ATIM; 3454 else 3455 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3456 rix = 0; /* XXX lowest rate */ 3457 try0 = ATH_TXMAXTRY; 3458 if (shortPreamble) 3459 txrate = an->an_tx_mgtratesp; 3460 else 3461 txrate = an->an_tx_mgtrate; 3462 /* NB: force all management frames to highest queue */ 3463 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3464 /* NB: force all management frames to highest queue */ 3465 pri = WME_AC_VO; 3466 } else 3467 pri = WME_AC_BE; 3468 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3469 break; 3470 case IEEE80211_FC0_TYPE_CTL: 3471 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3472 rix = 0; /* XXX lowest rate */ 3473 try0 = ATH_TXMAXTRY; 3474 if (shortPreamble) 3475 txrate = an->an_tx_mgtratesp; 3476 else 3477 txrate = an->an_tx_mgtrate; 3478 /* NB: force all ctl frames to highest queue */ 3479 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3480 /* NB: force all ctl frames to highest queue */ 3481 pri = WME_AC_VO; 3482 } else 3483 pri = WME_AC_BE; 3484 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3485 break; 3486 case IEEE80211_FC0_TYPE_DATA: 3487 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3488 /* 3489 * Data frames; consult the rate control module for 3490 * unicast frames. Send multicast frames at the 3491 * lowest rate. 3492 */ 3493 if (!ismcast) { 3494 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3495 &rix, &try0, &txrate); 3496 } else { 3497 rix = 0; 3498 try0 = ATH_TXMAXTRY; 3499 txrate = an->an_tx_mgtrate; 3500 } 3501 sc->sc_txrate = txrate; /* for LED blinking */ 3502 /* 3503 * Default all non-QoS traffic to the background queue. 3504 */ 3505 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3506 pri = M_WME_GETAC(m0); 3507 if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3508 flags |= HAL_TXDESC_NOACK; 3509 sc->sc_stats.ast_tx_noack++; 3510 } 3511 } else 3512 pri = WME_AC_BE; 3513 break; 3514 default: 3515 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3516 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3517 /* XXX statistic */ 3518 m_freem(m0); 3519 return EIO; 3520 } 3521 txq = sc->sc_ac2q[pri]; 3522 3523 /* 3524 * When servicing one or more stations in power-save mode 3525 * multicast frames must be buffered until after the beacon. 3526 * We use the CAB queue for that. 3527 */ 3528 if (ismcast && ic->ic_ps_sta) { 3529 txq = sc->sc_cabq; 3530 /* XXX? more bit in 802.11 frame header */ 3531 } 3532 3533 /* 3534 * Calculate miscellaneous flags. 3535 */ 3536 if (ismcast) { 3537 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3538 sc->sc_stats.ast_tx_noack++; 3539 } else if (pktlen > ic->ic_rtsthreshold) { 3540 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3541 cix = rt->info[rix].controlRate; 3542 sc->sc_stats.ast_tx_rts++; 3543 } 3544 3545 /* 3546 * If 802.11g protection is enabled, determine whether 3547 * to use RTS/CTS or just CTS. Note that this is only 3548 * done for OFDM unicast frames. 3549 */ 3550 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3551 rt->info[rix].phy == IEEE80211_T_OFDM && 3552 (flags & HAL_TXDESC_NOACK) == 0) { 3553 /* XXX fragments must use CCK rates w/ protection */ 3554 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3555 flags |= HAL_TXDESC_RTSENA; 3556 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3557 flags |= HAL_TXDESC_CTSENA; 3558 cix = rt->info[sc->sc_protrix].controlRate; 3559 sc->sc_stats.ast_tx_protect++; 3560 } 3561 3562 /* 3563 * Calculate duration. This logically belongs in the 802.11 3564 * layer but it lacks sufficient information to calculate it. 3565 */ 3566 if ((flags & HAL_TXDESC_NOACK) == 0 && 3567 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3568 u_int16_t dur; 3569 /* 3570 * XXX not right with fragmentation. 3571 */ 3572 if (shortPreamble) 3573 dur = rt->info[rix].spAckDuration; 3574 else 3575 dur = rt->info[rix].lpAckDuration; 3576 *(u_int16_t *)wh->i_dur = htole16(dur); 3577 } 3578 3579 /* 3580 * Calculate RTS/CTS rate and duration if needed. 3581 */ 3582 ctsduration = 0; 3583 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3584 /* 3585 * CTS transmit rate is derived from the transmit rate 3586 * by looking in the h/w rate table. We must also factor 3587 * in whether or not a short preamble is to be used. 3588 */ 3589 /* NB: cix is set above where RTS/CTS is enabled */ 3590 KASSERT(cix != 0xff, ("cix not setup")); 3591 ctsrate = rt->info[cix].rateCode; 3592 /* 3593 * Compute the transmit duration based on the frame 3594 * size and the size of an ACK frame. We call into the 3595 * HAL to do the computation since it depends on the 3596 * characteristics of the actual PHY being used. 3597 * 3598 * NB: CTS is assumed the same size as an ACK so we can 3599 * use the precalculated ACK durations. 3600 */ 3601 if (shortPreamble) { 3602 ctsrate |= rt->info[cix].shortPreamble; 3603 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3604 ctsduration += rt->info[cix].spAckDuration; 3605 ctsduration += ath_hal_computetxtime(ah, 3606 rt, pktlen, rix, AH_TRUE); 3607 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3608 ctsduration += rt->info[rix].spAckDuration; 3609 } else { 3610 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3611 ctsduration += rt->info[cix].lpAckDuration; 3612 ctsduration += ath_hal_computetxtime(ah, 3613 rt, pktlen, rix, AH_FALSE); 3614 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3615 ctsduration += rt->info[rix].lpAckDuration; 3616 } 3617 /* 3618 * Must disable multi-rate retry when using RTS/CTS. 3619 */ 3620 try0 = ATH_TXMAXTRY; 3621 } else 3622 ctsrate = 0; 3623 3624 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3625 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3626 sc->sc_hwmap[txrate].ieeerate, -1); 3627 #if NBPFILTER > 0 3628 if (ic->ic_rawbpf) 3629 bpf_mtap(ic->ic_rawbpf, m0); 3630 if (sc->sc_drvbpf) { 3631 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3632 if (iswep) 3633 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3634 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3635 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3636 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3637 3638 bpf_mtap2(sc->sc_drvbpf, 3639 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3640 } 3641 #endif 3642 3643 /* 3644 * Determine if a tx interrupt should be generated for 3645 * this descriptor. We take a tx interrupt to reap 3646 * descriptors when the h/w hits an EOL condition or 3647 * when the descriptor is specifically marked to generate 3648 * an interrupt. We periodically mark descriptors in this 3649 * way to insure timely replenishing of the supply needed 3650 * for sending frames. Defering interrupts reduces system 3651 * load and potentially allows more concurrent work to be 3652 * done but if done to aggressively can cause senders to 3653 * backup. 3654 * 3655 * NB: use >= to deal with sc_txintrperiod changing 3656 * dynamically through sysctl. 3657 */ 3658 if (flags & HAL_TXDESC_INTREQ) { 3659 txq->axq_intrcnt = 0; 3660 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3661 flags |= HAL_TXDESC_INTREQ; 3662 txq->axq_intrcnt = 0; 3663 } 3664 3665 /* 3666 * Formulate first tx descriptor with tx controls. 3667 */ 3668 /* XXX check return value? */ 3669 ath_hal_setuptxdesc(ah, ds 3670 , pktlen /* packet length */ 3671 , hdrlen /* header length */ 3672 , atype /* Atheros packet type */ 3673 , ni->ni_txpower /* txpower */ 3674 , txrate, try0 /* series 0 rate/tries */ 3675 , keyix /* key cache index */ 3676 , sc->sc_txantenna /* antenna mode */ 3677 , flags /* flags */ 3678 , ctsrate /* rts/cts rate */ 3679 , ctsduration /* rts/cts duration */ 3680 ); 3681 bf->bf_flags = flags; 3682 /* 3683 * Setup the multi-rate retry state only when we're 3684 * going to use it. This assumes ath_hal_setuptxdesc 3685 * initializes the descriptors (so we don't have to) 3686 * when the hardware supports multi-rate retry and 3687 * we don't use it. 3688 */ 3689 if (try0 != ATH_TXMAXTRY) 3690 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3691 3692 /* 3693 * Fillin the remainder of the descriptor info. 3694 */ 3695 ds0 = ds; 3696 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3697 ds->ds_data = bf->bf_segs[i].ds_addr; 3698 if (i == bf->bf_nseg - 1) 3699 ds->ds_link = 0; 3700 else 3701 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3702 ath_hal_filltxdesc(ah, ds 3703 , bf->bf_segs[i].ds_len /* segment length */ 3704 , i == 0 /* first segment */ 3705 , i == bf->bf_nseg - 1 /* last segment */ 3706 , ds0 /* first descriptor */ 3707 ); 3708 DPRINTF(sc, ATH_DEBUG_XMIT, 3709 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3710 __func__, i, ds->ds_link, ds->ds_data, 3711 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3712 } 3713 /* 3714 * Insert the frame on the outbound list and 3715 * pass it on to the hardware. 3716 */ 3717 ATH_TXQ_LOCK(txq); 3718 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 3719 u_int32_t txopLimit = IEEE80211_TXOP_TO_US( 3720 cap->cap_wmeParams[pri].wmep_txopLimit); 3721 /* 3722 * When bursting, potentially extend the CTS duration 3723 * of a previously queued frame to cover this frame 3724 * and not exceed the txopLimit. If that can be done 3725 * then disable RTS/CTS on this frame since it's now 3726 * covered (burst extension). Otherwise we must terminate 3727 * the burst before this frame goes out so as not to 3728 * violate the WME parameters. All this is complicated 3729 * as we need to update the state of packets on the 3730 * (live) hardware queue. The logic is buried in the hal 3731 * because it's highly chip-specific. 3732 */ 3733 if (txopLimit != 0) { 3734 sc->sc_stats.ast_tx_ctsburst++; 3735 if (updateCTSForBursting(ah, ds0, txq) == 0) { 3736 /* 3737 * This frame was not covered by RTS/CTS from 3738 * the previous frame in the burst; update the 3739 * descriptor pointers so this frame is now 3740 * treated as the last frame for extending a 3741 * burst. 3742 */ 3743 txq->axq_lastdsWithCTS = ds0; 3744 /* set gating Desc to final desc */ 3745 txq->axq_gatingds = 3746 (struct ath_desc *)txq->axq_link; 3747 } else 3748 sc->sc_stats.ast_tx_ctsext++; 3749 } 3750 } 3751 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3752 if (txq->axq_link == NULL) { 3753 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3754 DPRINTF(sc, ATH_DEBUG_XMIT, 3755 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3756 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3757 txq->axq_depth); 3758 } else { 3759 *txq->axq_link = bf->bf_daddr; 3760 DPRINTF(sc, ATH_DEBUG_XMIT, 3761 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3762 txq->axq_qnum, txq->axq_link, 3763 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3764 } 3765 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3766 /* 3767 * The CAB queue is started from the SWBA handler since 3768 * frames only go out on DTIM and to avoid possible races. 3769 */ 3770 if (txq != sc->sc_cabq) 3771 ath_hal_txstart(ah, txq->axq_qnum); 3772 ATH_TXQ_UNLOCK(txq); 3773 3774 return 0; 3775 #undef updateCTSForBursting 3776 #undef CTS_DURATION 3777 } 3778 3779 /* 3780 * Process completed xmit descriptors from the specified queue. 3781 */ 3782 static void 3783 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3784 { 3785 struct ath_hal *ah = sc->sc_ah; 3786 struct ieee80211com *ic = &sc->sc_ic; 3787 struct ath_buf *bf; 3788 struct ath_desc *ds, *ds0; 3789 struct ieee80211_node *ni; 3790 struct ath_node *an; 3791 int sr, lr, pri; 3792 HAL_STATUS status; 3793 3794 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3795 __func__, txq->axq_qnum, 3796 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3797 txq->axq_link); 3798 for (;;) { 3799 ATH_TXQ_LOCK(txq); 3800 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3801 bf = STAILQ_FIRST(&txq->axq_q); 3802 if (bf == NULL) { 3803 txq->axq_link = NULL; 3804 ATH_TXQ_UNLOCK(txq); 3805 break; 3806 } 3807 ds0 = &bf->bf_desc[0]; 3808 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3809 status = ath_hal_txprocdesc(ah, ds); 3810 #ifdef AR_DEBUG 3811 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3812 ath_printtxbuf(bf, status == HAL_OK); 3813 #endif 3814 if (status == HAL_EINPROGRESS) { 3815 ATH_TXQ_UNLOCK(txq); 3816 break; 3817 } 3818 if (ds0 == txq->axq_lastdsWithCTS) 3819 txq->axq_lastdsWithCTS = NULL; 3820 if (ds == txq->axq_gatingds) 3821 txq->axq_gatingds = NULL; 3822 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3823 ATH_TXQ_UNLOCK(txq); 3824 3825 ni = bf->bf_node; 3826 if (ni != NULL) { 3827 an = ATH_NODE(ni); 3828 if (ds->ds_txstat.ts_status == 0) { 3829 u_int8_t txant = ds->ds_txstat.ts_antenna; 3830 sc->sc_stats.ast_ant_tx[txant]++; 3831 sc->sc_ant_tx[txant]++; 3832 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3833 sc->sc_stats.ast_tx_altrate++; 3834 sc->sc_stats.ast_tx_rssi = 3835 ds->ds_txstat.ts_rssi; 3836 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3837 ds->ds_txstat.ts_rssi); 3838 pri = M_WME_GETAC(bf->bf_m); 3839 if (pri >= WME_AC_VO) 3840 ic->ic_wme.wme_hipri_traffic++; 3841 ni->ni_inact = ni->ni_inact_reload; 3842 } else { 3843 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3844 sc->sc_stats.ast_tx_xretries++; 3845 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3846 sc->sc_stats.ast_tx_fifoerr++; 3847 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3848 sc->sc_stats.ast_tx_filtered++; 3849 } 3850 sr = ds->ds_txstat.ts_shortretry; 3851 lr = ds->ds_txstat.ts_longretry; 3852 sc->sc_stats.ast_tx_shortretry += sr; 3853 sc->sc_stats.ast_tx_longretry += lr; 3854 /* 3855 * Hand the descriptor to the rate control algorithm. 3856 */ 3857 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3858 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) 3859 ath_rate_tx_complete(sc, an, ds, ds0); 3860 /* 3861 * Reclaim reference to node. 3862 * 3863 * NB: the node may be reclaimed here if, for example 3864 * this is a DEAUTH message that was sent and the 3865 * node was timed out due to inactivity. 3866 */ 3867 ieee80211_free_node(ni); 3868 } 3869 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3870 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3871 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3872 m_freem(bf->bf_m); 3873 bf->bf_m = NULL; 3874 bf->bf_node = NULL; 3875 3876 ATH_TXBUF_LOCK(sc); 3877 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3878 ATH_TXBUF_UNLOCK(sc); 3879 } 3880 } 3881 3882 /* 3883 * Deferred processing of transmit interrupt; special-cased 3884 * for a single hardware transmit queue (e.g. 5210 and 5211). 3885 */ 3886 static void 3887 ath_tx_proc_q0(void *arg, int npending) 3888 { 3889 struct ath_softc *sc = arg; 3890 struct ifnet *ifp = &sc->sc_if; 3891 3892 ath_tx_processq(sc, &sc->sc_txq[0]); 3893 ath_tx_processq(sc, sc->sc_cabq); 3894 ifp->if_flags &= ~IFF_OACTIVE; 3895 sc->sc_tx_timer = 0; 3896 3897 if (sc->sc_softled) 3898 ath_led_event(sc, ATH_LED_TX); 3899 3900 ath_start(ifp); 3901 } 3902 3903 /* 3904 * Deferred processing of transmit interrupt; special-cased 3905 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3906 */ 3907 static void 3908 ath_tx_proc_q0123(void *arg, int npending) 3909 { 3910 struct ath_softc *sc = arg; 3911 struct ifnet *ifp = &sc->sc_if; 3912 3913 /* 3914 * Process each active queue. 3915 */ 3916 ath_tx_processq(sc, &sc->sc_txq[0]); 3917 ath_tx_processq(sc, &sc->sc_txq[1]); 3918 ath_tx_processq(sc, &sc->sc_txq[2]); 3919 ath_tx_processq(sc, &sc->sc_txq[3]); 3920 ath_tx_processq(sc, sc->sc_cabq); 3921 3922 ifp->if_flags &= ~IFF_OACTIVE; 3923 sc->sc_tx_timer = 0; 3924 3925 if (sc->sc_softled) 3926 ath_led_event(sc, ATH_LED_TX); 3927 3928 ath_start(ifp); 3929 } 3930 3931 /* 3932 * Deferred processing of transmit interrupt. 3933 */ 3934 static void 3935 ath_tx_proc(void *arg, int npending) 3936 { 3937 struct ath_softc *sc = arg; 3938 struct ifnet *ifp = &sc->sc_if; 3939 int i; 3940 3941 /* 3942 * Process each active queue. 3943 */ 3944 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3945 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3946 if (ATH_TXQ_SETUP(sc, i)) 3947 ath_tx_processq(sc, &sc->sc_txq[i]); 3948 3949 ifp->if_flags &= ~IFF_OACTIVE; 3950 sc->sc_tx_timer = 0; 3951 3952 if (sc->sc_softled) 3953 ath_led_event(sc, ATH_LED_TX); 3954 3955 ath_start(ifp); 3956 } 3957 3958 static void 3959 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3960 { 3961 struct ath_hal *ah = sc->sc_ah; 3962 struct ieee80211_node *ni; 3963 struct ath_buf *bf; 3964 3965 /* 3966 * NB: this assumes output has been stopped and 3967 * we do not need to block ath_tx_tasklet 3968 */ 3969 for (;;) { 3970 ATH_TXQ_LOCK(txq); 3971 bf = STAILQ_FIRST(&txq->axq_q); 3972 if (bf == NULL) { 3973 txq->axq_link = NULL; 3974 ATH_TXQ_UNLOCK(txq); 3975 break; 3976 } 3977 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3978 ATH_TXQ_UNLOCK(txq); 3979 #ifdef AR_DEBUG 3980 if (sc->sc_debug & ATH_DEBUG_RESET) 3981 ath_printtxbuf(bf, 3982 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3983 #endif /* AR_DEBUG */ 3984 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3985 m_freem(bf->bf_m); 3986 bf->bf_m = NULL; 3987 ni = bf->bf_node; 3988 bf->bf_node = NULL; 3989 if (ni != NULL) { 3990 /* 3991 * Reclaim node reference. 3992 */ 3993 ieee80211_free_node(ni); 3994 } 3995 ATH_TXBUF_LOCK(sc); 3996 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3997 ATH_TXBUF_UNLOCK(sc); 3998 } 3999 } 4000 4001 static void 4002 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4003 { 4004 struct ath_hal *ah = sc->sc_ah; 4005 4006 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4007 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4008 __func__, txq->axq_qnum, 4009 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4010 txq->axq_link); 4011 } 4012 4013 /* 4014 * Drain the transmit queues and reclaim resources. 4015 */ 4016 static void 4017 ath_draintxq(struct ath_softc *sc) 4018 { 4019 struct ath_hal *ah = sc->sc_ah; 4020 struct ifnet *ifp = &sc->sc_if; 4021 int i; 4022 4023 /* XXX return value */ 4024 if (!sc->sc_invalid) { 4025 /* don't touch the hardware if marked invalid */ 4026 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4027 DPRINTF(sc, ATH_DEBUG_RESET, 4028 "%s: beacon queue %p\n", __func__, 4029 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4030 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4031 if (ATH_TXQ_SETUP(sc, i)) 4032 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4033 } 4034 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4035 if (ATH_TXQ_SETUP(sc, i)) 4036 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4037 ifp->if_flags &= ~IFF_OACTIVE; 4038 sc->sc_tx_timer = 0; 4039 } 4040 4041 /* 4042 * Disable the receive h/w in preparation for a reset. 4043 */ 4044 static void 4045 ath_stoprecv(struct ath_softc *sc) 4046 { 4047 #define PA2DESC(_sc, _pa) \ 4048 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4049 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4050 struct ath_hal *ah = sc->sc_ah; 4051 4052 ath_hal_stoppcurecv(ah); /* disable PCU */ 4053 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4054 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4055 DELAY(3000); /* 3ms is long enough for 1 frame */ 4056 #ifdef AR_DEBUG 4057 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4058 struct ath_buf *bf; 4059 4060 printf("%s: rx queue %p, link %p\n", __func__, 4061 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4062 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4063 struct ath_desc *ds = bf->bf_desc; 4064 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4065 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4066 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4067 ath_printrxbuf(bf, status == HAL_OK); 4068 } 4069 } 4070 #endif 4071 sc->sc_rxlink = NULL; /* just in case */ 4072 #undef PA2DESC 4073 } 4074 4075 /* 4076 * Enable the receive h/w following a reset. 4077 */ 4078 static int 4079 ath_startrecv(struct ath_softc *sc) 4080 { 4081 struct ath_hal *ah = sc->sc_ah; 4082 struct ath_buf *bf; 4083 4084 sc->sc_rxlink = NULL; 4085 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4086 int error = ath_rxbuf_init(sc, bf); 4087 if (error != 0) { 4088 DPRINTF(sc, ATH_DEBUG_RECV, 4089 "%s: ath_rxbuf_init failed %d\n", 4090 __func__, error); 4091 return error; 4092 } 4093 } 4094 4095 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4096 ath_hal_putrxbuf(ah, bf->bf_daddr); 4097 ath_hal_rxena(ah); /* enable recv descriptors */ 4098 ath_mode_init(sc); /* set filters, etc. */ 4099 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4100 return 0; 4101 } 4102 4103 /* 4104 * Update internal state after a channel change. 4105 */ 4106 static void 4107 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4108 { 4109 struct ieee80211com *ic = &sc->sc_ic; 4110 enum ieee80211_phymode mode; 4111 u_int16_t flags; 4112 4113 /* 4114 * Change channels and update the h/w rate map 4115 * if we're switching; e.g. 11a to 11b/g. 4116 */ 4117 mode = ieee80211_chan2mode(ic, chan); 4118 if (mode != sc->sc_curmode) 4119 ath_setcurmode(sc, mode); 4120 /* 4121 * Update BPF state. NB: ethereal et. al. don't handle 4122 * merged flags well so pick a unique mode for their use. 4123 */ 4124 if (IEEE80211_IS_CHAN_A(chan)) 4125 flags = IEEE80211_CHAN_A; 4126 /* XXX 11g schizophrenia */ 4127 else if (IEEE80211_IS_CHAN_G(chan) || 4128 IEEE80211_IS_CHAN_PUREG(chan)) 4129 flags = IEEE80211_CHAN_G; 4130 else 4131 flags = IEEE80211_CHAN_B; 4132 if (IEEE80211_IS_CHAN_T(chan)) 4133 flags |= IEEE80211_CHAN_TURBO; 4134 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4135 htole16(chan->ic_freq); 4136 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4137 htole16(flags); 4138 } 4139 4140 /* 4141 * Set/change channels. If the channel is really being changed, 4142 * it's done by reseting the chip. To accomplish this we must 4143 * first cleanup any pending DMA, then restart stuff after a la 4144 * ath_init. 4145 */ 4146 static int 4147 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4148 { 4149 struct ath_hal *ah = sc->sc_ah; 4150 struct ieee80211com *ic = &sc->sc_ic; 4151 HAL_CHANNEL hchan; 4152 4153 /* 4154 * Convert to a HAL channel description with 4155 * the flags constrained to reflect the current 4156 * operating mode. 4157 */ 4158 hchan.channel = chan->ic_freq; 4159 hchan.channelFlags = ath_chan2flags(ic, chan); 4160 4161 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 4162 __func__, 4163 ath_hal_mhz2ieee(sc->sc_curchan.channel, 4164 sc->sc_curchan.channelFlags), 4165 sc->sc_curchan.channel, 4166 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 4167 if (hchan.channel != sc->sc_curchan.channel || 4168 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4169 HAL_STATUS status; 4170 4171 /* 4172 * To switch channels clear any pending DMA operations; 4173 * wait long enough for the RX fifo to drain, reset the 4174 * hardware at the new frequency, and then re-enable 4175 * the relevant bits of the h/w. 4176 */ 4177 ath_hal_intrset(ah, 0); /* disable interrupts */ 4178 ath_draintxq(sc); /* clear pending tx frames */ 4179 ath_stoprecv(sc); /* turn off frame recv */ 4180 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4181 if_printf(&sc->sc_if, "ath_chan_set: unable to reset " 4182 "channel %u (%u Mhz)\n", 4183 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 4184 return EIO; 4185 } 4186 sc->sc_curchan = hchan; 4187 ath_update_txpow(sc); /* update tx power state */ 4188 sc->sc_diversity = ath_hal_getdiversity(ah); 4189 4190 /* 4191 * Re-enable rx framework. 4192 */ 4193 if (ath_startrecv(sc) != 0) { 4194 if_printf(&sc->sc_if, 4195 "ath_chan_set: unable to restart recv logic\n"); 4196 return EIO; 4197 } 4198 4199 /* 4200 * Change channels and update the h/w rate map 4201 * if we're switching; e.g. 11a to 11b/g. 4202 */ 4203 ic->ic_ibss_chan = chan; 4204 ath_chan_change(sc, chan); 4205 4206 /* 4207 * Re-enable interrupts. 4208 */ 4209 ath_hal_intrset(ah, sc->sc_imask); 4210 } 4211 return 0; 4212 } 4213 4214 static void 4215 ath_next_scan(void *arg) 4216 { 4217 struct ath_softc *sc = arg; 4218 struct ieee80211com *ic = &sc->sc_ic; 4219 int s; 4220 4221 /* don't call ath_start w/o network interrupts blocked */ 4222 s = splnet(); 4223 4224 if (ic->ic_state == IEEE80211_S_SCAN) 4225 ieee80211_next_scan(ic); 4226 splx(s); 4227 } 4228 4229 /* 4230 * Periodically recalibrate the PHY to account 4231 * for temperature/environment changes. 4232 */ 4233 static void 4234 ath_calibrate(void *arg) 4235 { 4236 struct ath_softc *sc = arg; 4237 struct ath_hal *ah = sc->sc_ah; 4238 4239 sc->sc_stats.ast_per_cal++; 4240 4241 ATH_LOCK(sc); 4242 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 4243 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 4244 4245 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4246 /* 4247 * Rfgain is out of bounds, reset the chip 4248 * to load new gain values. 4249 */ 4250 sc->sc_stats.ast_per_rfgain++; 4251 ath_reset(&sc->sc_if); 4252 } 4253 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 4254 DPRINTF(sc, ATH_DEBUG_ANY, 4255 "%s: calibration of channel %u failed\n", 4256 __func__, sc->sc_curchan.channel); 4257 sc->sc_stats.ast_per_calfail++; 4258 } 4259 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 4260 ATH_UNLOCK(sc); 4261 } 4262 4263 static int 4264 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4265 { 4266 struct ifnet *ifp = ic->ic_ifp; 4267 struct ath_softc *sc = ifp->if_softc; 4268 struct ath_hal *ah = sc->sc_ah; 4269 struct ieee80211_node *ni; 4270 int i, error; 4271 const u_int8_t *bssid; 4272 u_int32_t rfilt; 4273 static const HAL_LED_STATE leds[] = { 4274 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4275 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4276 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4277 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4278 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4279 }; 4280 4281 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4282 ieee80211_state_name[ic->ic_state], 4283 ieee80211_state_name[nstate]); 4284 4285 callout_stop(&sc->sc_scan_ch); 4286 callout_stop(&sc->sc_cal_ch); 4287 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4288 4289 if (nstate == IEEE80211_S_INIT) { 4290 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4291 /* 4292 * NB: disable interrupts so we don't rx frames. 4293 */ 4294 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4295 /* 4296 * Notify the rate control algorithm. 4297 */ 4298 ath_rate_newstate(sc, nstate); 4299 goto done; 4300 } 4301 ni = ic->ic_bss; 4302 error = ath_chan_set(sc, ic->ic_curchan); 4303 if (error != 0) 4304 goto bad; 4305 rfilt = ath_calcrxfilter(sc, nstate); 4306 if (nstate == IEEE80211_S_SCAN) 4307 bssid = ifp->if_broadcastaddr; 4308 else 4309 bssid = ni->ni_bssid; 4310 ath_hal_setrxfilter(ah, rfilt); 4311 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4312 __func__, rfilt, ether_sprintf(bssid)); 4313 4314 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4315 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4316 else 4317 ath_hal_setassocid(ah, bssid, 0); 4318 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4319 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4320 if (ath_hal_keyisvalid(ah, i)) 4321 ath_hal_keysetmac(ah, i, bssid); 4322 } 4323 4324 /* 4325 * Notify the rate control algorithm so rates 4326 * are setup should ath_beacon_alloc be called. 4327 */ 4328 ath_rate_newstate(sc, nstate); 4329 4330 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4331 /* nothing to do */; 4332 } else if (nstate == IEEE80211_S_RUN) { 4333 DPRINTF(sc, ATH_DEBUG_STATE, 4334 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4335 "capinfo=0x%04x chan=%d\n" 4336 , __func__ 4337 , ic->ic_flags 4338 , ni->ni_intval 4339 , ether_sprintf(ni->ni_bssid) 4340 , ni->ni_capinfo 4341 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4342 4343 switch (ic->ic_opmode) { 4344 case IEEE80211_M_HOSTAP: 4345 case IEEE80211_M_IBSS: 4346 /* 4347 * Allocate and setup the beacon frame. 4348 * 4349 * Stop any previous beacon DMA. This may be 4350 * necessary, for example, when an ibss merge 4351 * causes reconfiguration; there will be a state 4352 * transition from RUN->RUN that means we may 4353 * be called with beacon transmission active. 4354 */ 4355 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4356 ath_beacon_free(sc); 4357 error = ath_beacon_alloc(sc, ni); 4358 if (error != 0) 4359 goto bad; 4360 break; 4361 case IEEE80211_M_STA: 4362 /* 4363 * Allocate a key cache slot to the station. 4364 */ 4365 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4366 sc->sc_hasclrkey && 4367 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4368 ath_setup_stationkey(ni); 4369 break; 4370 default: 4371 break; 4372 } 4373 4374 /* 4375 * Configure the beacon and sleep timers. 4376 */ 4377 ath_beacon_config(sc); 4378 } else { 4379 ath_hal_intrset(ah, 4380 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4381 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4382 } 4383 done: 4384 /* 4385 * Invoke the parent method to complete the work. 4386 */ 4387 error = sc->sc_newstate(ic, nstate, arg); 4388 /* 4389 * Finally, start any timers. 4390 */ 4391 if (nstate == IEEE80211_S_RUN) { 4392 /* start periodic recalibration timer */ 4393 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4394 ath_calibrate, sc); 4395 } else if (nstate == IEEE80211_S_SCAN) { 4396 /* start ap/neighbor scan timer */ 4397 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4398 ath_next_scan, sc); 4399 } 4400 bad: 4401 return error; 4402 } 4403 4404 /* 4405 * Allocate a key cache slot to the station so we can 4406 * setup a mapping from key index to node. The key cache 4407 * slot is needed for managing antenna state and for 4408 * compression when stations do not use crypto. We do 4409 * it uniliaterally here; if crypto is employed this slot 4410 * will be reassigned. 4411 */ 4412 static void 4413 ath_setup_stationkey(struct ieee80211_node *ni) 4414 { 4415 struct ieee80211com *ic = ni->ni_ic; 4416 struct ath_softc *sc = ic->ic_ifp->if_softc; 4417 ieee80211_keyix keyix, rxkeyix; 4418 4419 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4420 /* 4421 * Key cache is full; we'll fall back to doing 4422 * the more expensive lookup in software. Note 4423 * this also means no h/w compression. 4424 */ 4425 /* XXX msg+statistic */ 4426 } else { 4427 /* XXX locking? */ 4428 ni->ni_ucastkey.wk_keyix = keyix; 4429 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4430 /* NB: this will create a pass-thru key entry */ 4431 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4432 } 4433 } 4434 4435 /* 4436 * Setup driver-specific state for a newly associated node. 4437 * Note that we're called also on a re-associate, the isnew 4438 * param tells us if this is the first time or not. 4439 */ 4440 static void 4441 ath_newassoc(struct ieee80211_node *ni, int isnew) 4442 { 4443 struct ieee80211com *ic = ni->ni_ic; 4444 struct ath_softc *sc = ic->ic_ifp->if_softc; 4445 4446 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4447 if (isnew && 4448 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4449 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4450 ("new assoc with a unicast key already setup (keyix %u)", 4451 ni->ni_ucastkey.wk_keyix)); 4452 ath_setup_stationkey(ni); 4453 } 4454 } 4455 4456 static int 4457 ath_getchannels(struct ath_softc *sc, u_int cc, 4458 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4459 { 4460 struct ieee80211com *ic = &sc->sc_ic; 4461 struct ifnet *ifp = &sc->sc_if; 4462 struct ath_hal *ah = sc->sc_ah; 4463 HAL_CHANNEL *chans; 4464 int i, ix, nchan; 4465 4466 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4467 M_TEMP, M_NOWAIT); 4468 if (chans == NULL) { 4469 if_printf(ifp, "unable to allocate channel table\n"); 4470 return ENOMEM; 4471 } 4472 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4473 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4474 u_int32_t rd; 4475 4476 ath_hal_getregdomain(ah, &rd); 4477 if_printf(ifp, "unable to collect channel list from hal; " 4478 "regdomain likely %u country code %u\n", rd, cc); 4479 free(chans, M_TEMP); 4480 return EINVAL; 4481 } 4482 4483 /* 4484 * Convert HAL channels to ieee80211 ones and insert 4485 * them in the table according to their channel number. 4486 */ 4487 for (i = 0; i < nchan; i++) { 4488 HAL_CHANNEL *c = &chans[i]; 4489 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4490 if (ix > IEEE80211_CHAN_MAX) { 4491 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4492 ix, c->channel, c->channelFlags); 4493 continue; 4494 } 4495 DPRINTF(sc, ATH_DEBUG_ANY, 4496 "%s: HAL channel %d/%d freq %d flags %#04x idx %d\n", 4497 sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags, 4498 ix); 4499 /* NB: flags are known to be compatible */ 4500 if (ic->ic_channels[ix].ic_freq == 0) { 4501 ic->ic_channels[ix].ic_freq = c->channel; 4502 ic->ic_channels[ix].ic_flags = c->channelFlags; 4503 } else { 4504 /* channels overlap; e.g. 11g and 11b */ 4505 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4506 } 4507 } 4508 free(chans, M_TEMP); 4509 return 0; 4510 } 4511 4512 static void 4513 ath_led_done(void *arg) 4514 { 4515 struct ath_softc *sc = arg; 4516 4517 sc->sc_blinking = 0; 4518 } 4519 4520 /* 4521 * Turn the LED off: flip the pin and then set a timer so no 4522 * update will happen for the specified duration. 4523 */ 4524 static void 4525 ath_led_off(void *arg) 4526 { 4527 struct ath_softc *sc = arg; 4528 4529 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4530 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4531 } 4532 4533 /* 4534 * Blink the LED according to the specified on/off times. 4535 */ 4536 static void 4537 ath_led_blink(struct ath_softc *sc, int on, int off) 4538 { 4539 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4540 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4541 sc->sc_blinking = 1; 4542 sc->sc_ledoff = off; 4543 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4544 } 4545 4546 static void 4547 ath_led_event(struct ath_softc *sc, int event) 4548 { 4549 4550 sc->sc_ledevent = ticks; /* time of last event */ 4551 if (sc->sc_blinking) /* don't interrupt active blink */ 4552 return; 4553 switch (event) { 4554 case ATH_LED_POLL: 4555 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4556 sc->sc_hwmap[0].ledoff); 4557 break; 4558 case ATH_LED_TX: 4559 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4560 sc->sc_hwmap[sc->sc_txrate].ledoff); 4561 break; 4562 case ATH_LED_RX: 4563 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4564 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4565 break; 4566 } 4567 } 4568 4569 static void 4570 ath_update_txpow(struct ath_softc *sc) 4571 { 4572 struct ieee80211com *ic = &sc->sc_ic; 4573 struct ath_hal *ah = sc->sc_ah; 4574 u_int32_t txpow; 4575 4576 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4577 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4578 /* read back in case value is clamped */ 4579 ath_hal_gettxpowlimit(ah, &txpow); 4580 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4581 } 4582 /* 4583 * Fetch max tx power level for status requests. 4584 */ 4585 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4586 ic->ic_bss->ni_txpower = txpow; 4587 } 4588 4589 static int 4590 ath_rate_setup(struct ath_softc *sc, u_int mode) 4591 { 4592 struct ath_hal *ah = sc->sc_ah; 4593 struct ieee80211com *ic = &sc->sc_ic; 4594 const HAL_RATE_TABLE *rt; 4595 struct ieee80211_rateset *rs; 4596 int i, maxrates; 4597 4598 switch (mode) { 4599 case IEEE80211_MODE_11A: 4600 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4601 break; 4602 case IEEE80211_MODE_11B: 4603 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4604 break; 4605 case IEEE80211_MODE_11G: 4606 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4607 break; 4608 case IEEE80211_MODE_TURBO_A: 4609 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4610 break; 4611 case IEEE80211_MODE_TURBO_G: 4612 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4613 break; 4614 default: 4615 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4616 __func__, mode); 4617 return 0; 4618 } 4619 rt = sc->sc_rates[mode]; 4620 if (rt == NULL) 4621 return 0; 4622 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4623 DPRINTF(sc, ATH_DEBUG_ANY, 4624 "%s: rate table too small (%u > %u)\n", 4625 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4626 maxrates = IEEE80211_RATE_MAXSIZE; 4627 } else 4628 maxrates = rt->rateCount; 4629 rs = &ic->ic_sup_rates[mode]; 4630 for (i = 0; i < maxrates; i++) 4631 rs->rs_rates[i] = rt->info[i].dot11Rate; 4632 rs->rs_nrates = maxrates; 4633 return 1; 4634 } 4635 4636 static void 4637 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4638 { 4639 #define N(a) (sizeof(a)/sizeof(a[0])) 4640 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4641 static const struct { 4642 u_int rate; /* tx/rx 802.11 rate */ 4643 u_int16_t timeOn; /* LED on time (ms) */ 4644 u_int16_t timeOff; /* LED off time (ms) */ 4645 } blinkrates[] = { 4646 { 108, 40, 10 }, 4647 { 96, 44, 11 }, 4648 { 72, 50, 13 }, 4649 { 48, 57, 14 }, 4650 { 36, 67, 16 }, 4651 { 24, 80, 20 }, 4652 { 22, 100, 25 }, 4653 { 18, 133, 34 }, 4654 { 12, 160, 40 }, 4655 { 10, 200, 50 }, 4656 { 6, 240, 58 }, 4657 { 4, 267, 66 }, 4658 { 2, 400, 100 }, 4659 { 0, 500, 130 }, 4660 }; 4661 const HAL_RATE_TABLE *rt; 4662 int i, j; 4663 4664 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4665 rt = sc->sc_rates[mode]; 4666 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4667 for (i = 0; i < rt->rateCount; i++) 4668 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4669 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4670 for (i = 0; i < 32; i++) { 4671 u_int8_t ix = rt->rateCodeToIndex[i]; 4672 if (ix == 0xff) { 4673 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4674 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4675 continue; 4676 } 4677 sc->sc_hwmap[i].ieeerate = 4678 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4679 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4680 if (rt->info[ix].shortPreamble || 4681 rt->info[ix].phy == IEEE80211_T_OFDM) 4682 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4683 /* NB: receive frames include FCS */ 4684 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4685 IEEE80211_RADIOTAP_F_FCS; 4686 /* setup blink rate table to avoid per-packet lookup */ 4687 for (j = 0; j < N(blinkrates)-1; j++) 4688 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4689 break; 4690 /* NB: this uses the last entry if the rate isn't found */ 4691 /* XXX beware of overlow */ 4692 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4693 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4694 } 4695 sc->sc_currates = rt; 4696 sc->sc_curmode = mode; 4697 /* 4698 * All protection frames are transmited at 2Mb/s for 4699 * 11g, otherwise at 1Mb/s. 4700 * XXX select protection rate index from rate table. 4701 */ 4702 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4703 /* NB: caller is responsible for reseting rate control state */ 4704 #undef N 4705 } 4706 4707 #ifdef AR_DEBUG 4708 static void 4709 ath_printrxbuf(struct ath_buf *bf, int done) 4710 { 4711 struct ath_desc *ds; 4712 int i; 4713 4714 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4715 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4716 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4717 ds->ds_link, ds->ds_data, 4718 ds->ds_ctl0, ds->ds_ctl1, 4719 ds->ds_hw[0], ds->ds_hw[1], 4720 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4721 } 4722 } 4723 4724 static void 4725 ath_printtxbuf(struct ath_buf *bf, int done) 4726 { 4727 struct ath_desc *ds; 4728 int i; 4729 4730 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4731 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4732 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4733 ds->ds_link, ds->ds_data, 4734 ds->ds_ctl0, ds->ds_ctl1, 4735 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4736 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4737 } 4738 } 4739 #endif /* AR_DEBUG */ 4740 4741 static void 4742 ath_watchdog(struct ifnet *ifp) 4743 { 4744 struct ath_softc *sc = ifp->if_softc; 4745 struct ieee80211com *ic = &sc->sc_ic; 4746 4747 ifp->if_timer = 0; 4748 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4749 return; 4750 if (sc->sc_tx_timer) { 4751 if (--sc->sc_tx_timer == 0) { 4752 if_printf(ifp, "device timeout\n"); 4753 ath_reset(ifp); 4754 ifp->if_oerrors++; 4755 sc->sc_stats.ast_watchdog++; 4756 } else 4757 ifp->if_timer = 1; 4758 } 4759 ieee80211_watchdog(ic); 4760 } 4761 4762 /* 4763 * Diagnostic interface to the HAL. This is used by various 4764 * tools to do things like retrieve register contents for 4765 * debugging. The mechanism is intentionally opaque so that 4766 * it can change frequently w/o concern for compatiblity. 4767 */ 4768 static int 4769 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4770 { 4771 struct ath_hal *ah = sc->sc_ah; 4772 u_int id = ad->ad_id & ATH_DIAG_ID; 4773 void *indata = NULL; 4774 void *outdata = NULL; 4775 u_int32_t insize = ad->ad_in_size; 4776 u_int32_t outsize = ad->ad_out_size; 4777 int error = 0; 4778 4779 if (ad->ad_id & ATH_DIAG_IN) { 4780 /* 4781 * Copy in data. 4782 */ 4783 indata = malloc(insize, M_TEMP, M_NOWAIT); 4784 if (indata == NULL) { 4785 error = ENOMEM; 4786 goto bad; 4787 } 4788 error = copyin(ad->ad_in_data, indata, insize); 4789 if (error) 4790 goto bad; 4791 } 4792 if (ad->ad_id & ATH_DIAG_DYN) { 4793 /* 4794 * Allocate a buffer for the results (otherwise the HAL 4795 * returns a pointer to a buffer where we can read the 4796 * results). Note that we depend on the HAL leaving this 4797 * pointer for us to use below in reclaiming the buffer; 4798 * may want to be more defensive. 4799 */ 4800 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4801 if (outdata == NULL) { 4802 error = ENOMEM; 4803 goto bad; 4804 } 4805 } 4806 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4807 if (outsize < ad->ad_out_size) 4808 ad->ad_out_size = outsize; 4809 if (outdata != NULL) 4810 error = copyout(outdata, ad->ad_out_data, 4811 ad->ad_out_size); 4812 } else { 4813 error = EINVAL; 4814 } 4815 bad: 4816 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4817 free(indata, M_TEMP); 4818 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4819 free(outdata, M_TEMP); 4820 return error; 4821 } 4822 4823 static int 4824 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4825 { 4826 #define IS_RUNNING(ifp) \ 4827 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 4828 struct ath_softc *sc = ifp->if_softc; 4829 struct ieee80211com *ic = &sc->sc_ic; 4830 struct ifreq *ifr = (struct ifreq *)data; 4831 int error = 0; 4832 4833 ATH_LOCK(sc); 4834 switch (cmd) { 4835 case SIOCSIFFLAGS: 4836 if (IS_RUNNING(ifp)) { 4837 /* 4838 * To avoid rescanning another access point, 4839 * do not call ath_init() here. Instead, 4840 * only reflect promisc mode settings. 4841 */ 4842 ath_mode_init(sc); 4843 } else if (ifp->if_flags & IFF_UP) { 4844 /* 4845 * Beware of being called during attach/detach 4846 * to reset promiscuous mode. In that case we 4847 * will still be marked UP but not RUNNING. 4848 * However trying to re-init the interface 4849 * is the wrong thing to do as we've already 4850 * torn down much of our state. There's 4851 * probably a better way to deal with this. 4852 */ 4853 if (!sc->sc_invalid && ic->ic_bss != NULL) 4854 ath_init(sc); /* XXX lose error */ 4855 } else 4856 ath_stop_locked(ifp, 1); 4857 break; 4858 case SIOCADDMULTI: 4859 case SIOCDELMULTI: 4860 error = (cmd == SIOCADDMULTI) ? 4861 ether_addmulti(ifr, &sc->sc_ec) : 4862 ether_delmulti(ifr, &sc->sc_ec); 4863 if (error == ENETRESET) { 4864 if (ifp->if_flags & IFF_RUNNING) 4865 ath_mode_init(sc); 4866 error = 0; 4867 } 4868 break; 4869 case SIOCGATHSTATS: 4870 /* NB: embed these numbers to get a consistent view */ 4871 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4872 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4873 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4874 ATH_UNLOCK(sc); 4875 /* 4876 * NB: Drop the softc lock in case of a page fault; 4877 * we'll accept any potential inconsisentcy in the 4878 * statistics. The alternative is to copy the data 4879 * to a local structure. 4880 */ 4881 return copyout(&sc->sc_stats, 4882 ifr->ifr_data, sizeof (sc->sc_stats)); 4883 case SIOCGATHDIAG: 4884 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4885 break; 4886 default: 4887 error = ieee80211_ioctl(ic, cmd, data); 4888 if (error == ENETRESET) { 4889 if (IS_RUNNING(ifp) && 4890 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4891 ath_init(sc); /* XXX lose error */ 4892 error = 0; 4893 } 4894 if (error == ERESTART) 4895 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4896 break; 4897 } 4898 ATH_UNLOCK(sc); 4899 return error; 4900 #undef IS_RUNNING 4901 } 4902 4903 #if NBPFILTER > 0 4904 static void 4905 ath_bpfattach(struct ath_softc *sc) 4906 { 4907 struct ifnet *ifp = &sc->sc_if; 4908 4909 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4910 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4911 &sc->sc_drvbpf); 4912 /* 4913 * Initialize constant fields. 4914 * XXX make header lengths a multiple of 32-bits so subsequent 4915 * headers are properly aligned; this is a kludge to keep 4916 * certain applications happy. 4917 * 4918 * NB: the channel is setup each time we transition to the 4919 * RUN state to avoid filling it in for each frame. 4920 */ 4921 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4922 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4923 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4924 4925 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4926 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4927 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4928 } 4929 #endif 4930 4931 /* 4932 * Announce various information on device/driver attach. 4933 */ 4934 static void 4935 ath_announce(struct ath_softc *sc) 4936 { 4937 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4938 struct ifnet *ifp = &sc->sc_if; 4939 struct ath_hal *ah = sc->sc_ah; 4940 u_int modes, cc; 4941 4942 if_printf(ifp, "mac %d.%d phy %d.%d", 4943 ah->ah_macVersion, ah->ah_macRev, 4944 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4945 /* 4946 * Print radio revision(s). We check the wireless modes 4947 * to avoid falsely printing revs for inoperable parts. 4948 * Dual-band radio revs are returned in the 5Ghz rev number. 4949 */ 4950 ath_hal_getcountrycode(ah, &cc); 4951 modes = ath_hal_getwirelessmodes(ah, cc); 4952 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4953 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4954 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4955 ah->ah_analog5GhzRev >> 4, 4956 ah->ah_analog5GhzRev & 0xf, 4957 ah->ah_analog2GhzRev >> 4, 4958 ah->ah_analog2GhzRev & 0xf); 4959 else 4960 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4961 ah->ah_analog5GhzRev & 0xf); 4962 } else 4963 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4964 ah->ah_analog5GhzRev & 0xf); 4965 printf("\n"); 4966 if (bootverbose) { 4967 int i; 4968 for (i = 0; i <= WME_AC_VO; i++) { 4969 struct ath_txq *txq = sc->sc_ac2q[i]; 4970 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4971 txq->axq_qnum, ieee80211_wme_acnames[i]); 4972 } 4973 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4974 sc->sc_cabq->axq_qnum); 4975 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4976 } 4977 #undef HAL_MODE_DUALBAND 4978 } 4979
Indexes created Thu Oct 02 07:10:07 GMT 2025