ath.c revision 1.76.4.2
1 /* $NetBSD: ath.c,v 1.76.4.2 2007/01/12 00:57:35 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.76.4.2 2007/01/12 00:57:35 ad Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <machine/bus.h> 74 #include <sys/endian.h> 75 76 #include <machine/bus.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/if_ether.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_netbsd.h> 87 #include <net80211/ieee80211_var.h> 88 89 #if NBPFILTER > 0 90 #include <net/bpf.h> 91 #endif 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #endif 96 97 #include <sys/device.h> 98 #include <dev/ic/ath_netbsd.h> 99 100 #define AR_DEBUG 101 #include <dev/ic/athvar.h> 102 #include <contrib/dev/ath/ah_desc.h> 103 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 104 #include "athhal_options.h" 105 106 #ifdef ATH_TX99_DIAG 107 #include <dev/ath/ath_tx99/ath_tx99.h> 108 #endif 109 110 /* unaligned little endian access */ 111 #define LE_READ_2(p) \ 112 ((u_int16_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 114 #define LE_READ_4(p) \ 115 ((u_int32_t) \ 116 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 117 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 118 119 enum { 120 ATH_LED_TX, 121 ATH_LED_RX, 122 ATH_LED_POLL, 123 }; 124 125 #ifdef AH_NEED_DESC_SWAP 126 #define HTOAH32(x) htole32(x) 127 #else 128 #define HTOAH32(x) (x) 129 #endif 130 131 static int ath_ifinit(struct ifnet *); 132 static int ath_init(struct ath_softc *); 133 static void ath_stop_locked(struct ifnet *, int); 134 static void ath_stop(struct ifnet *, int); 135 static void ath_start(struct ifnet *); 136 static int ath_media_change(struct ifnet *); 137 static void ath_watchdog(struct ifnet *); 138 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 139 static void ath_fatal_proc(void *, int); 140 static void ath_rxorn_proc(void *, int); 141 static void ath_bmiss_proc(void *, int); 142 static void ath_radar_proc(void *, int); 143 static int ath_key_alloc(struct ieee80211com *, 144 const struct ieee80211_key *, 145 ieee80211_keyix *, ieee80211_keyix *); 146 static int ath_key_delete(struct ieee80211com *, 147 const struct ieee80211_key *); 148 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 149 const u_int8_t mac[IEEE80211_ADDR_LEN]); 150 static void ath_key_update_begin(struct ieee80211com *); 151 static void ath_key_update_end(struct ieee80211com *); 152 static void ath_mode_init(struct ath_softc *); 153 static void ath_setslottime(struct ath_softc *); 154 static void ath_updateslot(struct ifnet *); 155 static int ath_beaconq_setup(struct ath_hal *); 156 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 157 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 158 static void ath_beacon_proc(void *, int); 159 static void ath_bstuck_proc(void *, int); 160 static void ath_beacon_free(struct ath_softc *); 161 static void ath_beacon_config(struct ath_softc *); 162 static void ath_descdma_cleanup(struct ath_softc *sc, 163 struct ath_descdma *, ath_bufhead *); 164 static int ath_desc_alloc(struct ath_softc *); 165 static void ath_desc_free(struct ath_softc *); 166 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 167 static void ath_node_free(struct ieee80211_node *); 168 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 169 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 170 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 171 struct ieee80211_node *ni, 172 int subtype, int rssi, u_int32_t rstamp); 173 static void ath_setdefantenna(struct ath_softc *, u_int); 174 static void ath_rx_proc(void *, int); 175 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 176 static int ath_tx_setup(struct ath_softc *, int, int); 177 static int ath_wme_update(struct ieee80211com *); 178 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 179 static void ath_tx_cleanup(struct ath_softc *); 180 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 181 struct ath_buf *, struct mbuf *); 182 static void ath_tx_proc_q0(void *, int); 183 static void ath_tx_proc_q0123(void *, int); 184 static void ath_tx_proc(void *, int); 185 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 186 static void ath_draintxq(struct ath_softc *); 187 static void ath_stoprecv(struct ath_softc *); 188 static int ath_startrecv(struct ath_softc *); 189 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 190 static void ath_next_scan(void *); 191 static void ath_calibrate(void *); 192 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 193 static void ath_setup_stationkey(struct ieee80211_node *); 194 static void ath_newassoc(struct ieee80211_node *, int); 195 static int ath_getchannels(struct ath_softc *, u_int cc, 196 HAL_BOOL outdoor, HAL_BOOL xchanmode); 197 static void ath_led_event(struct ath_softc *, int); 198 static void ath_update_txpow(struct ath_softc *); 199 200 static int ath_rate_setup(struct ath_softc *, u_int mode); 201 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 202 203 #ifdef __NetBSD__ 204 int ath_enable(struct ath_softc *); 205 void ath_disable(struct ath_softc *); 206 void ath_power(int, void *); 207 #endif 208 209 #if NBPFILTER > 0 210 static void ath_bpfattach(struct ath_softc *); 211 #endif 212 static void ath_announce(struct ath_softc *); 213 214 int ath_dwelltime = 200; /* 5 channels/second */ 215 int ath_calinterval = 30; /* calibrate every 30 secs */ 216 int ath_outdoor = AH_TRUE; /* outdoor operation */ 217 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 218 int ath_countrycode = CTRY_DEFAULT; /* country code */ 219 int ath_regdomain = 0; /* regulatory domain */ 220 int ath_debug = 0; 221 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 222 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 223 224 #ifdef AR_DEBUG 225 enum { 226 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 227 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 228 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 229 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 230 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 231 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 232 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 233 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 234 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 235 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 236 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 237 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 238 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 239 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 240 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 241 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 242 ATH_DEBUG_NODE = 0x00080000, /* node management */ 243 ATH_DEBUG_LED = 0x00100000, /* led management */ 244 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 245 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 246 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 247 ATH_DEBUG_ANY = 0xffffffff 248 }; 249 #define IFF_DUMPPKTS(sc, m) \ 250 ((sc->sc_debug & (m)) || \ 251 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 252 #define DPRINTF(sc, m, fmt, ...) do { \ 253 if (sc->sc_debug & (m)) \ 254 printf(fmt, __VA_ARGS__); \ 255 } while (0) 256 #define KEYPRINTF(sc, ix, hk, mac) do { \ 257 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 258 ath_keyprint(__func__, ix, hk, mac); \ 259 } while (0) 260 static void ath_printrxbuf(struct ath_buf *bf, int); 261 static void ath_printtxbuf(struct ath_buf *bf, int); 262 #else 263 #define IFF_DUMPPKTS(sc, m) \ 264 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 265 #define DPRINTF(m, fmt, ...) 266 #define KEYPRINTF(sc, k, ix, mac) 267 #endif 268 269 #ifdef __NetBSD__ 270 int 271 ath_activate(struct device *self, enum devact act) 272 { 273 struct ath_softc *sc = (struct ath_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 case DVACT_DEACTIVATE: 282 if_deactivate(&sc->sc_if); 283 break; 284 } 285 splx(s); 286 return rv; 287 } 288 289 int 290 ath_enable(struct ath_softc *sc) 291 { 292 if (ATH_IS_ENABLED(sc) == 0) { 293 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 294 printf("%s: device enable failed\n", 295 sc->sc_dev.dv_xname); 296 return (EIO); 297 } 298 sc->sc_flags |= ATH_ENABLED; 299 } 300 return (0); 301 } 302 303 void 304 ath_disable(struct ath_softc *sc) 305 { 306 if (!ATH_IS_ENABLED(sc)) 307 return; 308 if (sc->sc_disable != NULL) 309 (*sc->sc_disable)(sc); 310 sc->sc_flags &= ~ATH_ENABLED; 311 } 312 #endif /* __NetBSD__ */ 313 314 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 315 316 int 317 ath_attach(u_int16_t devid, struct ath_softc *sc) 318 { 319 struct ifnet *ifp = &sc->sc_if; 320 struct ieee80211com *ic = &sc->sc_ic; 321 struct ath_hal *ah = NULL; 322 HAL_STATUS status; 323 int error = 0, i; 324 325 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 326 327 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 328 329 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 330 if (ah == NULL) { 331 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 332 status); 333 error = ENXIO; 334 goto bad; 335 } 336 if (ah->ah_abi != HAL_ABI_VERSION) { 337 if_printf(ifp, "HAL ABI mismatch detected " 338 "(HAL:0x%x != driver:0x%x)\n", 339 ah->ah_abi, HAL_ABI_VERSION); 340 error = ENXIO; 341 goto bad; 342 } 343 sc->sc_ah = ah; 344 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 345 346 /* 347 * Check if the MAC has multi-rate retry support. 348 * We do this by trying to setup a fake extended 349 * descriptor. MAC's that don't have support will 350 * return false w/o doing anything. MAC's that do 351 * support it will return true w/o doing anything. 352 */ 353 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 354 355 /* 356 * Check if the device has hardware counters for PHY 357 * errors. If so we need to enable the MIB interrupt 358 * so we can act on stat triggers. 359 */ 360 if (ath_hal_hwphycounters(ah)) 361 sc->sc_needmib = 1; 362 363 /* 364 * Get the hardware key cache size. 365 */ 366 sc->sc_keymax = ath_hal_keycachesize(ah); 367 if (sc->sc_keymax > ATH_KEYMAX) { 368 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 369 ATH_KEYMAX, sc->sc_keymax); 370 sc->sc_keymax = ATH_KEYMAX; 371 } 372 /* 373 * Reset the key cache since some parts do not 374 * reset the contents on initial power up. 375 */ 376 for (i = 0; i < sc->sc_keymax; i++) 377 ath_hal_keyreset(ah, i); 378 /* 379 * Mark key cache slots associated with global keys 380 * as in use. If we knew TKIP was not to be used we 381 * could leave the +32, +64, and +32+64 slots free. 382 * XXX only for splitmic. 383 */ 384 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 385 setbit(sc->sc_keymap, i); 386 setbit(sc->sc_keymap, i+32); 387 setbit(sc->sc_keymap, i+64); 388 setbit(sc->sc_keymap, i+32+64); 389 } 390 391 /* 392 * Collect the channel list using the default country 393 * code and including outdoor channels. The 802.11 layer 394 * is resposible for filtering this list based on settings 395 * like the phy mode. 396 */ 397 error = ath_getchannels(sc, ath_countrycode, 398 ath_outdoor, ath_xchanmode); 399 if (error != 0) 400 goto bad; 401 402 /* 403 * Setup rate tables for all potential media types. 404 */ 405 ath_rate_setup(sc, IEEE80211_MODE_11A); 406 ath_rate_setup(sc, IEEE80211_MODE_11B); 407 ath_rate_setup(sc, IEEE80211_MODE_11G); 408 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 409 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 410 /* NB: setup here so ath_rate_update is happy */ 411 ath_setcurmode(sc, IEEE80211_MODE_11A); 412 413 /* 414 * Allocate tx+rx descriptors and populate the lists. 415 */ 416 error = ath_desc_alloc(sc); 417 if (error != 0) { 418 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 419 goto bad; 420 } 421 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 422 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 423 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 424 425 ATH_TXBUF_LOCK_INIT(sc); 426 427 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 428 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 429 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 430 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 431 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 432 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 433 434 /* 435 * Allocate hardware transmit queues: one queue for 436 * beacon frames and one data queue for each QoS 437 * priority. Note that the hal handles reseting 438 * these queues at the needed time. 439 * 440 * XXX PS-Poll 441 */ 442 sc->sc_bhalq = ath_beaconq_setup(ah); 443 if (sc->sc_bhalq == (u_int) -1) { 444 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 445 error = EIO; 446 goto bad2; 447 } 448 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 449 if (sc->sc_cabq == NULL) { 450 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 451 error = EIO; 452 goto bad2; 453 } 454 /* NB: insure BK queue is the lowest priority h/w queue */ 455 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 456 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 457 ieee80211_wme_acnames[WME_AC_BK]); 458 error = EIO; 459 goto bad2; 460 } 461 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 462 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 463 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 464 /* 465 * Not enough hardware tx queues to properly do WME; 466 * just punt and assign them all to the same h/w queue. 467 * We could do a better job of this if, for example, 468 * we allocate queues when we switch from station to 469 * AP mode. 470 */ 471 if (sc->sc_ac2q[WME_AC_VI] != NULL) 472 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 473 if (sc->sc_ac2q[WME_AC_BE] != NULL) 474 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 475 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 476 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 477 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 478 } 479 480 /* 481 * Special case certain configurations. Note the 482 * CAB queue is handled by these specially so don't 483 * include them when checking the txq setup mask. 484 */ 485 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 486 case 0x01: 487 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 488 break; 489 case 0x0f: 490 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 491 break; 492 default: 493 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 494 break; 495 } 496 497 /* 498 * Setup rate control. Some rate control modules 499 * call back to change the anntena state so expose 500 * the necessary entry points. 501 * XXX maybe belongs in struct ath_ratectrl? 502 */ 503 sc->sc_setdefantenna = ath_setdefantenna; 504 sc->sc_rc = ath_rate_attach(sc); 505 if (sc->sc_rc == NULL) { 506 error = EIO; 507 goto bad2; 508 } 509 510 sc->sc_blinking = 0; 511 sc->sc_ledstate = 1; 512 sc->sc_ledon = 0; /* low true */ 513 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 514 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 515 /* 516 * Auto-enable soft led processing for IBM cards and for 517 * 5211 minipci cards. Users can also manually enable/disable 518 * support with a sysctl. 519 */ 520 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 521 if (sc->sc_softled) { 522 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 523 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 524 } 525 526 ifp->if_softc = sc; 527 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 528 ifp->if_start = ath_start; 529 ifp->if_watchdog = ath_watchdog; 530 ifp->if_ioctl = ath_ioctl; 531 ifp->if_init = ath_ifinit; 532 IFQ_SET_READY(&ifp->if_snd); 533 534 ic->ic_ifp = ifp; 535 ic->ic_reset = ath_reset; 536 ic->ic_newassoc = ath_newassoc; 537 ic->ic_updateslot = ath_updateslot; 538 ic->ic_wme.wme_update = ath_wme_update; 539 /* XXX not right but it's not used anywhere important */ 540 ic->ic_phytype = IEEE80211_T_OFDM; 541 ic->ic_opmode = IEEE80211_M_STA; 542 ic->ic_caps = 543 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 544 | IEEE80211_C_HOSTAP /* hostap mode */ 545 | IEEE80211_C_MONITOR /* monitor mode */ 546 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 547 | IEEE80211_C_SHSLOT /* short slot time supported */ 548 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 549 | IEEE80211_C_TXFRAG /* handle tx frags */ 550 ; 551 /* 552 * Query the hal to figure out h/w crypto support. 553 */ 554 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 555 ic->ic_caps |= IEEE80211_C_WEP; 556 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 557 ic->ic_caps |= IEEE80211_C_AES; 558 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 559 ic->ic_caps |= IEEE80211_C_AES_CCM; 560 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 561 ic->ic_caps |= IEEE80211_C_CKIP; 562 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 563 ic->ic_caps |= IEEE80211_C_TKIP; 564 /* 565 * Check if h/w does the MIC and/or whether the 566 * separate key cache entries are required to 567 * handle both tx+rx MIC keys. 568 */ 569 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 570 ic->ic_caps |= IEEE80211_C_TKIPMIC; 571 if (ath_hal_tkipsplit(ah)) 572 sc->sc_splitmic = 1; 573 } 574 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 575 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 576 /* 577 * TPC support can be done either with a global cap or 578 * per-packet support. The latter is not available on 579 * all parts. We're a bit pedantic here as all parts 580 * support a global cap. 581 */ 582 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 583 ic->ic_caps |= IEEE80211_C_TXPMGT; 584 585 /* 586 * Mark WME capability only if we have sufficient 587 * hardware queues to do proper priority scheduling. 588 */ 589 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 590 ic->ic_caps |= IEEE80211_C_WME; 591 /* 592 * Check for misc other capabilities. 593 */ 594 if (ath_hal_hasbursting(ah)) 595 ic->ic_caps |= IEEE80211_C_BURST; 596 597 /* 598 * Indicate we need the 802.11 header padded to a 599 * 32-bit boundary for 4-address and QoS frames. 600 */ 601 ic->ic_flags |= IEEE80211_F_DATAPAD; 602 603 /* 604 * Query the hal about antenna support. 605 */ 606 sc->sc_defant = ath_hal_getdefantenna(ah); 607 608 /* 609 * Not all chips have the VEOL support we want to 610 * use with IBSS beacons; check here for it. 611 */ 612 sc->sc_hasveol = ath_hal_hasveol(ah); 613 614 /* get mac address from hardware */ 615 ath_hal_getmac(ah, ic->ic_myaddr); 616 617 if_attach(ifp); 618 /* call MI attach routine. */ 619 ieee80211_ifattach(ic); 620 /* override default methods */ 621 ic->ic_node_alloc = ath_node_alloc; 622 sc->sc_node_free = ic->ic_node_free; 623 ic->ic_node_free = ath_node_free; 624 ic->ic_node_getrssi = ath_node_getrssi; 625 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 626 ic->ic_recv_mgmt = ath_recv_mgmt; 627 sc->sc_newstate = ic->ic_newstate; 628 ic->ic_newstate = ath_newstate; 629 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 630 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 631 ic->ic_crypto.cs_key_delete = ath_key_delete; 632 ic->ic_crypto.cs_key_set = ath_key_set; 633 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 634 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 635 /* complete initialization */ 636 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 637 638 #if NBPFILTER > 0 639 ath_bpfattach(sc); 640 #endif 641 642 #ifdef __NetBSD__ 643 sc->sc_flags |= ATH_ATTACHED; 644 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 645 ath_power, sc); 646 if (sc->sc_powerhook == NULL) 647 printf("%s: WARNING: unable to establish power hook\n", 648 sc->sc_dev.dv_xname); 649 #endif 650 651 /* 652 * Setup dynamic sysctl's now that country code and 653 * regdomain are available from the hal. 654 */ 655 ath_sysctlattach(sc); 656 657 ieee80211_announce(ic); 658 ath_announce(sc); 659 return 0; 660 bad2: 661 ath_tx_cleanup(sc); 662 ath_desc_free(sc); 663 bad: 664 if (ah) 665 ath_hal_detach(ah); 666 sc->sc_invalid = 1; 667 return error; 668 } 669 670 int 671 ath_detach(struct ath_softc *sc) 672 { 673 struct ifnet *ifp = &sc->sc_if; 674 int s; 675 676 if ((sc->sc_flags & ATH_ATTACHED) == 0) 677 return (0); 678 679 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 680 __func__, ifp->if_flags); 681 682 s = splnet(); 683 ath_stop(ifp, 1); 684 #if NBPFILTER > 0 685 bpfdetach(ifp); 686 #endif 687 /* 688 * NB: the order of these is important: 689 * o call the 802.11 layer before detaching the hal to 690 * insure callbacks into the driver to delete global 691 * key cache entries can be handled 692 * o reclaim the tx queue data structures after calling 693 * the 802.11 layer as we'll get called back to reclaim 694 * node state and potentially want to use them 695 * o to cleanup the tx queues the hal is called, so detach 696 * it last 697 * Other than that, it's straightforward... 698 */ 699 ieee80211_ifdetach(&sc->sc_ic); 700 #ifdef ATH_TX99_DIAG 701 if (sc->sc_tx99 != NULL) 702 sc->sc_tx99->detach(sc->sc_tx99); 703 #endif 704 ath_rate_detach(sc->sc_rc); 705 ath_desc_free(sc); 706 ath_tx_cleanup(sc); 707 sysctl_teardown(&sc->sc_sysctllog); 708 ath_hal_detach(sc->sc_ah); 709 if_detach(ifp); 710 splx(s); 711 powerhook_disestablish(sc->sc_powerhook); 712 713 return 0; 714 } 715 716 #ifdef __NetBSD__ 717 void 718 ath_power(int why, void *arg) 719 { 720 struct ath_softc *sc = arg; 721 int s; 722 723 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 724 725 s = splnet(); 726 switch (why) { 727 case PWR_SUSPEND: 728 case PWR_STANDBY: 729 ath_suspend(sc, why); 730 break; 731 case PWR_RESUME: 732 ath_resume(sc, why); 733 break; 734 case PWR_SOFTSUSPEND: 735 case PWR_SOFTSTANDBY: 736 case PWR_SOFTRESUME: 737 break; 738 } 739 splx(s); 740 } 741 #endif 742 743 void 744 ath_suspend(struct ath_softc *sc, int why) 745 { 746 struct ifnet *ifp = &sc->sc_if; 747 748 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 749 __func__, ifp->if_flags); 750 751 ath_stop(ifp, 1); 752 if (sc->sc_power != NULL) 753 (*sc->sc_power)(sc, why); 754 } 755 756 void 757 ath_resume(struct ath_softc *sc, int why) 758 { 759 struct ifnet *ifp = &sc->sc_if; 760 761 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 762 __func__, ifp->if_flags); 763 764 if (ifp->if_flags & IFF_UP) { 765 ath_init(sc); 766 #if 0 767 (void)ath_intr(sc); 768 #endif 769 if (sc->sc_power != NULL) 770 (*sc->sc_power)(sc, why); 771 if (ifp->if_flags & IFF_RUNNING) 772 ath_start(ifp); 773 } 774 if (sc->sc_softled) { 775 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 776 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 777 } 778 } 779 780 void 781 ath_shutdown(void *arg) 782 { 783 struct ath_softc *sc = arg; 784 785 ath_stop(&sc->sc_if, 1); 786 } 787 788 /* 789 * Interrupt handler. Most of the actual processing is deferred. 790 */ 791 int 792 ath_intr(void *arg) 793 { 794 struct ath_softc *sc = arg; 795 struct ifnet *ifp = &sc->sc_if; 796 struct ath_hal *ah = sc->sc_ah; 797 HAL_INT status; 798 799 if (sc->sc_invalid) { 800 /* 801 * The hardware is not ready/present, don't touch anything. 802 * Note this can happen early on if the IRQ is shared. 803 */ 804 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 805 return 0; 806 } 807 808 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 809 return 0; 810 811 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 812 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 813 __func__, ifp->if_flags); 814 ath_hal_getisr(ah, &status); /* clear ISR */ 815 ath_hal_intrset(ah, 0); /* disable further intr's */ 816 return 1; /* XXX */ 817 } 818 /* 819 * Figure out the reason(s) for the interrupt. Note 820 * that the hal returns a pseudo-ISR that may include 821 * bits we haven't explicitly enabled so we mask the 822 * value to insure we only process bits we requested. 823 */ 824 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 825 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 826 status &= sc->sc_imask; /* discard unasked for bits */ 827 if (status & HAL_INT_FATAL) { 828 /* 829 * Fatal errors are unrecoverable. Typically 830 * these are caused by DMA errors. Unfortunately 831 * the exact reason is not (presently) returned 832 * by the hal. 833 */ 834 sc->sc_stats.ast_hardware++; 835 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 836 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 837 } else if (status & HAL_INT_RXORN) { 838 sc->sc_stats.ast_rxorn++; 839 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 840 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 841 } else { 842 if (status & HAL_INT_SWBA) { 843 /* 844 * Software beacon alert--time to send a beacon. 845 * Handle beacon transmission directly; deferring 846 * this is too slow to meet timing constraints 847 * under load. 848 */ 849 ath_beacon_proc(sc, 0); 850 } 851 if (status & HAL_INT_RXEOL) { 852 /* 853 * NB: the hardware should re-read the link when 854 * RXE bit is written, but it doesn't work at 855 * least on older hardware revs. 856 */ 857 sc->sc_stats.ast_rxeol++; 858 sc->sc_rxlink = NULL; 859 } 860 if (status & HAL_INT_TXURN) { 861 sc->sc_stats.ast_txurn++; 862 /* bump tx trigger level */ 863 ath_hal_updatetxtriglevel(ah, AH_TRUE); 864 } 865 if (status & HAL_INT_RX) 866 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 867 if (status & HAL_INT_TX) 868 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 869 if (status & HAL_INT_BMISS) { 870 sc->sc_stats.ast_bmiss++; 871 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 872 } 873 if (status & HAL_INT_MIB) { 874 sc->sc_stats.ast_mib++; 875 /* 876 * Disable interrupts until we service the MIB 877 * interrupt; otherwise it will continue to fire. 878 */ 879 ath_hal_intrset(ah, 0); 880 /* 881 * Let the hal handle the event. We assume it will 882 * clear whatever condition caused the interrupt. 883 */ 884 ath_hal_mibevent(ah, &sc->sc_halstats); 885 ath_hal_intrset(ah, sc->sc_imask); 886 } 887 } 888 return 1; 889 } 890 891 /* Swap transmit descriptor. 892 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 893 * function. 894 */ 895 static inline void 896 ath_desc_swap(struct ath_desc *ds) 897 { 898 #ifdef AH_NEED_DESC_SWAP 899 ds->ds_link = htole32(ds->ds_link); 900 ds->ds_data = htole32(ds->ds_data); 901 ds->ds_ctl0 = htole32(ds->ds_ctl0); 902 ds->ds_ctl1 = htole32(ds->ds_ctl1); 903 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 904 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 905 #endif 906 } 907 908 static void 909 ath_fatal_proc(void *arg, int pending) 910 { 911 struct ath_softc *sc = arg; 912 struct ifnet *ifp = &sc->sc_if; 913 914 if_printf(ifp, "hardware error; resetting\n"); 915 ath_reset(ifp); 916 } 917 918 static void 919 ath_rxorn_proc(void *arg, int pending) 920 { 921 struct ath_softc *sc = arg; 922 struct ifnet *ifp = &sc->sc_if; 923 924 if_printf(ifp, "rx FIFO overrun; resetting\n"); 925 ath_reset(ifp); 926 } 927 928 static void 929 ath_bmiss_proc(void *arg, int pending) 930 { 931 struct ath_softc *sc = arg; 932 struct ieee80211com *ic = &sc->sc_ic; 933 934 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 935 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 936 ("unexpect operating mode %u", ic->ic_opmode)); 937 if (ic->ic_state == IEEE80211_S_RUN) { 938 u_int64_t lastrx = sc->sc_lastrx; 939 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 940 941 DPRINTF(sc, ATH_DEBUG_BEACON, 942 "%s: tsf %" PRIu64 " lastrx %" PRId64 943 " (%" PRIu64 ") bmiss %u\n", 944 __func__, tsf, tsf - lastrx, lastrx, 945 ic->ic_bmisstimeout*1024); 946 /* 947 * Workaround phantom bmiss interrupts by sanity-checking 948 * the time of our last rx'd frame. If it is within the 949 * beacon miss interval then ignore the interrupt. If it's 950 * truly a bmiss we'll get another interrupt soon and that'll 951 * be dispatched up for processing. 952 */ 953 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 954 NET_LOCK_GIANT(); 955 ieee80211_beacon_miss(ic); 956 NET_UNLOCK_GIANT(); 957 } else 958 sc->sc_stats.ast_bmiss_phantom++; 959 } 960 } 961 962 static void 963 ath_radar_proc(void *arg, int pending) 964 { 965 struct ath_softc *sc = arg; 966 struct ifnet *ifp = &sc->sc_if; 967 struct ath_hal *ah = sc->sc_ah; 968 HAL_CHANNEL hchan; 969 970 if (ath_hal_procdfs(ah, &hchan)) { 971 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 972 hchan.channel, hchan.channelFlags, hchan.privFlags); 973 /* 974 * Initiate channel change. 975 */ 976 /* XXX not yet */ 977 } 978 } 979 980 static u_int 981 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 982 { 983 #define N(a) (sizeof(a) / sizeof(a[0])) 984 static const u_int modeflags[] = { 985 0, /* IEEE80211_MODE_AUTO */ 986 CHANNEL_A, /* IEEE80211_MODE_11A */ 987 CHANNEL_B, /* IEEE80211_MODE_11B */ 988 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 989 0, /* IEEE80211_MODE_FH */ 990 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 991 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 992 }; 993 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 994 995 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 996 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 997 return modeflags[mode]; 998 #undef N 999 } 1000 1001 static int 1002 ath_ifinit(struct ifnet *ifp) 1003 { 1004 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 1005 1006 return ath_init(sc); 1007 } 1008 1009 static int 1010 ath_init(struct ath_softc *sc) 1011 { 1012 struct ifnet *ifp = &sc->sc_if; 1013 struct ieee80211com *ic = &sc->sc_ic; 1014 struct ath_hal *ah = sc->sc_ah; 1015 HAL_STATUS status; 1016 int error = 0; 1017 1018 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1019 __func__, ifp->if_flags); 1020 1021 ATH_LOCK(sc); 1022 1023 if ((error = ath_enable(sc)) != 0) 1024 return error; 1025 1026 /* 1027 * Stop anything previously setup. This is safe 1028 * whether this is the first time through or not. 1029 */ 1030 ath_stop_locked(ifp, 0); 1031 1032 /* 1033 * The basic interface to setting the hardware in a good 1034 * state is ``reset''. On return the hardware is known to 1035 * be powered up and with interrupts disabled. This must 1036 * be followed by initialization of the appropriate bits 1037 * and then setup of the interrupt mask. 1038 */ 1039 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1040 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1041 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1042 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1043 status); 1044 error = EIO; 1045 goto done; 1046 } 1047 1048 /* 1049 * This is needed only to setup initial state 1050 * but it's best done after a reset. 1051 */ 1052 ath_update_txpow(sc); 1053 /* 1054 * Likewise this is set during reset so update 1055 * state cached in the driver. 1056 */ 1057 sc->sc_diversity = ath_hal_getdiversity(ah); 1058 sc->sc_calinterval = 1; 1059 sc->sc_caltries = 0; 1060 1061 /* 1062 * Setup the hardware after reset: the key cache 1063 * is filled as needed and the receive engine is 1064 * set going. Frame transmit is handled entirely 1065 * in the frame output path; there's nothing to do 1066 * here except setup the interrupt mask. 1067 */ 1068 if ((error = ath_startrecv(sc)) != 0) { 1069 if_printf(ifp, "unable to start recv logic\n"); 1070 goto done; 1071 } 1072 1073 /* 1074 * Enable interrupts. 1075 */ 1076 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1077 | HAL_INT_RXEOL | HAL_INT_RXORN 1078 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1079 /* 1080 * Enable MIB interrupts when there are hardware phy counters. 1081 * Note we only do this (at the moment) for station mode. 1082 */ 1083 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1084 sc->sc_imask |= HAL_INT_MIB; 1085 ath_hal_intrset(ah, sc->sc_imask); 1086 1087 ifp->if_flags |= IFF_RUNNING; 1088 ic->ic_state = IEEE80211_S_INIT; 1089 1090 /* 1091 * The hardware should be ready to go now so it's safe 1092 * to kick the 802.11 state machine as it's likely to 1093 * immediately call back to us to send mgmt frames. 1094 */ 1095 ath_chan_change(sc, ic->ic_curchan); 1096 #ifdef ATH_TX99_DIAG 1097 if (sc->sc_tx99 != NULL) 1098 sc->sc_tx99->start(sc->sc_tx99); 1099 else 1100 #endif 1101 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1102 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1103 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1104 } else 1105 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1106 done: 1107 ATH_UNLOCK(sc); 1108 return error; 1109 } 1110 1111 static void 1112 ath_stop_locked(struct ifnet *ifp, int disable) 1113 { 1114 struct ath_softc *sc = ifp->if_softc; 1115 struct ieee80211com *ic = &sc->sc_ic; 1116 struct ath_hal *ah = sc->sc_ah; 1117 1118 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1119 __func__, sc->sc_invalid, ifp->if_flags); 1120 1121 ATH_LOCK_ASSERT(sc); 1122 if (ifp->if_flags & IFF_RUNNING) { 1123 /* 1124 * Shutdown the hardware and driver: 1125 * reset 802.11 state machine 1126 * turn off timers 1127 * disable interrupts 1128 * turn off the radio 1129 * clear transmit machinery 1130 * clear receive machinery 1131 * drain and release tx queues 1132 * reclaim beacon resources 1133 * power down hardware 1134 * 1135 * Note that some of this work is not possible if the 1136 * hardware is gone (invalid). 1137 */ 1138 #ifdef ATH_TX99_DIAG 1139 if (sc->sc_tx99 != NULL) 1140 sc->sc_tx99->stop(sc->sc_tx99); 1141 #endif 1142 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1143 ifp->if_flags &= ~IFF_RUNNING; 1144 ifp->if_timer = 0; 1145 if (!sc->sc_invalid) { 1146 if (sc->sc_softled) { 1147 callout_stop(&sc->sc_ledtimer); 1148 ath_hal_gpioset(ah, sc->sc_ledpin, 1149 !sc->sc_ledon); 1150 sc->sc_blinking = 0; 1151 } 1152 ath_hal_intrset(ah, 0); 1153 } 1154 ath_draintxq(sc); 1155 if (!sc->sc_invalid) { 1156 ath_stoprecv(sc); 1157 ath_hal_phydisable(ah); 1158 } else 1159 sc->sc_rxlink = NULL; 1160 IF_PURGE(&ifp->if_snd); 1161 ath_beacon_free(sc); 1162 if (disable) 1163 ath_disable(sc); 1164 } 1165 } 1166 1167 static void 1168 ath_stop(struct ifnet *ifp, int disable) 1169 { 1170 struct ath_softc *sc = ifp->if_softc; 1171 1172 ATH_LOCK(sc); 1173 ath_stop_locked(ifp, disable); 1174 if (!sc->sc_invalid) { 1175 /* 1176 * Set the chip in full sleep mode. Note that we are 1177 * careful to do this only when bringing the interface 1178 * completely to a stop. When the chip is in this state 1179 * it must be carefully woken up or references to 1180 * registers in the PCI clock domain may freeze the bus 1181 * (and system). This varies by chip and is mostly an 1182 * issue with newer parts that go to sleep more quickly. 1183 */ 1184 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1185 } 1186 ATH_UNLOCK(sc); 1187 } 1188 1189 /* 1190 * Reset the hardware w/o losing operational state. This is 1191 * basically a more efficient way of doing ath_stop, ath_init, 1192 * followed by state transitions to the current 802.11 1193 * operational state. Used to recover from various errors and 1194 * to reset or reload hardware state. 1195 */ 1196 int 1197 ath_reset(struct ifnet *ifp) 1198 { 1199 struct ath_softc *sc = ifp->if_softc; 1200 struct ieee80211com *ic = &sc->sc_ic; 1201 struct ath_hal *ah = sc->sc_ah; 1202 struct ieee80211_channel *c; 1203 HAL_STATUS status; 1204 1205 /* 1206 * Convert to a HAL channel description with the flags 1207 * constrained to reflect the current operating mode. 1208 */ 1209 c = ic->ic_curchan; 1210 sc->sc_curchan.channel = c->ic_freq; 1211 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1212 1213 ath_hal_intrset(ah, 0); /* disable interrupts */ 1214 ath_draintxq(sc); /* stop xmit side */ 1215 ath_stoprecv(sc); /* stop recv side */ 1216 /* NB: indicate channel change so we do a full reset */ 1217 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1218 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1219 __func__, status); 1220 ath_update_txpow(sc); /* update tx power state */ 1221 sc->sc_diversity = ath_hal_getdiversity(ah); 1222 sc->sc_calinterval = 1; 1223 sc->sc_caltries = 0; 1224 if (ath_startrecv(sc) != 0) /* restart recv */ 1225 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1226 /* 1227 * We may be doing a reset in response to an ioctl 1228 * that changes the channel so update any state that 1229 * might change as a result. 1230 */ 1231 ath_chan_change(sc, c); 1232 if (ic->ic_state == IEEE80211_S_RUN) 1233 ath_beacon_config(sc); /* restart beacons */ 1234 ath_hal_intrset(ah, sc->sc_imask); 1235 1236 ath_start(ifp); /* restart xmit */ 1237 return 0; 1238 } 1239 1240 /* 1241 * Cleanup driver resources when we run out of buffers 1242 * while processing fragments; return the tx buffers 1243 * allocated and drop node references. 1244 */ 1245 static void 1246 ath_txfrag_cleanup(struct ath_softc *sc, 1247 ath_bufhead *frags, struct ieee80211_node *ni) 1248 { 1249 struct ath_buf *bf; 1250 1251 ATH_TXBUF_LOCK_ASSERT(sc); 1252 1253 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1254 STAILQ_REMOVE_HEAD(frags, bf_list); 1255 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1256 ieee80211_node_decref(ni); 1257 } 1258 } 1259 1260 /* 1261 * Setup xmit of a fragmented frame. Allocate a buffer 1262 * for each frag and bump the node reference count to 1263 * reflect the held reference to be setup by ath_tx_start. 1264 */ 1265 static int 1266 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1267 struct mbuf *m0, struct ieee80211_node *ni) 1268 { 1269 struct mbuf *m; 1270 struct ath_buf *bf; 1271 1272 ATH_TXBUF_LOCK(sc); 1273 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1274 bf = STAILQ_FIRST(&sc->sc_txbuf); 1275 if (bf == NULL) { /* out of buffers, cleanup */ 1276 ath_txfrag_cleanup(sc, frags, ni); 1277 break; 1278 } 1279 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1280 ieee80211_node_incref(ni); 1281 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1282 } 1283 ATH_TXBUF_UNLOCK(sc); 1284 1285 return !STAILQ_EMPTY(frags); 1286 } 1287 1288 static void 1289 ath_start(struct ifnet *ifp) 1290 { 1291 struct ath_softc *sc = ifp->if_softc; 1292 struct ath_hal *ah = sc->sc_ah; 1293 struct ieee80211com *ic = &sc->sc_ic; 1294 struct ieee80211_node *ni; 1295 struct ath_buf *bf; 1296 struct mbuf *m, *next; 1297 struct ieee80211_frame *wh; 1298 struct ether_header *eh; 1299 ath_bufhead frags; 1300 1301 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1302 return; 1303 for (;;) { 1304 /* 1305 * Grab a TX buffer and associated resources. 1306 */ 1307 ATH_TXBUF_LOCK(sc); 1308 bf = STAILQ_FIRST(&sc->sc_txbuf); 1309 if (bf != NULL) 1310 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1311 ATH_TXBUF_UNLOCK(sc); 1312 if (bf == NULL) { 1313 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1314 __func__); 1315 sc->sc_stats.ast_tx_qstop++; 1316 ifp->if_flags |= IFF_OACTIVE; 1317 break; 1318 } 1319 /* 1320 * Poll the management queue for frames; they 1321 * have priority over normal data frames. 1322 */ 1323 IF_DEQUEUE(&ic->ic_mgtq, m); 1324 if (m == NULL) { 1325 /* 1326 * No data frames go out unless we're associated. 1327 */ 1328 if (ic->ic_state != IEEE80211_S_RUN) { 1329 DPRINTF(sc, ATH_DEBUG_XMIT, 1330 "%s: discard data packet, state %s\n", 1331 __func__, 1332 ieee80211_state_name[ic->ic_state]); 1333 sc->sc_stats.ast_tx_discard++; 1334 ATH_TXBUF_LOCK(sc); 1335 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1336 ATH_TXBUF_UNLOCK(sc); 1337 break; 1338 } 1339 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1340 if (m == NULL) { 1341 ATH_TXBUF_LOCK(sc); 1342 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1343 ATH_TXBUF_UNLOCK(sc); 1344 break; 1345 } 1346 STAILQ_INIT(&frags); 1347 /* 1348 * Find the node for the destination so we can do 1349 * things like power save and fast frames aggregation. 1350 */ 1351 if (m->m_len < sizeof(struct ether_header) && 1352 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1353 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1354 ni = NULL; 1355 goto bad; 1356 } 1357 eh = mtod(m, struct ether_header *); 1358 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1359 if (ni == NULL) { 1360 /* NB: ieee80211_find_txnode does stat+msg */ 1361 m_freem(m); 1362 goto bad; 1363 } 1364 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1365 (m->m_flags & M_PWR_SAV) == 0) { 1366 /* 1367 * Station in power save mode; pass the frame 1368 * to the 802.11 layer and continue. We'll get 1369 * the frame back when the time is right. 1370 */ 1371 ieee80211_pwrsave(ic, ni, m); 1372 goto reclaim; 1373 } 1374 /* calculate priority so we can find the tx queue */ 1375 if (ieee80211_classify(ic, m, ni)) { 1376 DPRINTF(sc, ATH_DEBUG_XMIT, 1377 "%s: discard, classification failure\n", 1378 __func__); 1379 m_freem(m); 1380 goto bad; 1381 } 1382 ifp->if_opackets++; 1383 1384 #if NBPFILTER > 0 1385 if (ifp->if_bpf) 1386 bpf_mtap(ifp->if_bpf, m); 1387 #endif 1388 /* 1389 * Encapsulate the packet in prep for transmission. 1390 */ 1391 m = ieee80211_encap(ic, m, ni); 1392 if (m == NULL) { 1393 DPRINTF(sc, ATH_DEBUG_XMIT, 1394 "%s: encapsulation failure\n", 1395 __func__); 1396 sc->sc_stats.ast_tx_encap++; 1397 goto bad; 1398 } 1399 /* 1400 * Check for fragmentation. If this has frame 1401 * has been broken up verify we have enough 1402 * buffers to send all the fragments so all 1403 * go out or none... 1404 */ 1405 if ((m->m_flags & M_FRAG) && 1406 !ath_txfrag_setup(sc, &frags, m, ni)) { 1407 DPRINTF(sc, ATH_DEBUG_ANY, 1408 "%s: out of txfrag buffers\n", __func__); 1409 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1410 goto bad; 1411 } 1412 } else { 1413 /* 1414 * Hack! The referenced node pointer is in the 1415 * rcvif field of the packet header. This is 1416 * placed there by ieee80211_mgmt_output because 1417 * we need to hold the reference with the frame 1418 * and there's no other way (other than packet 1419 * tags which we consider too expensive to use) 1420 * to pass it along. 1421 */ 1422 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1423 m->m_pkthdr.rcvif = NULL; 1424 1425 wh = mtod(m, struct ieee80211_frame *); 1426 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1427 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1428 /* fill time stamp */ 1429 u_int64_t tsf; 1430 u_int32_t *tstamp; 1431 1432 tsf = ath_hal_gettsf64(ah); 1433 /* XXX: adjust 100us delay to xmit */ 1434 tsf += 100; 1435 tstamp = (u_int32_t *)&wh[1]; 1436 tstamp[0] = htole32(tsf & 0xffffffff); 1437 tstamp[1] = htole32(tsf >> 32); 1438 } 1439 sc->sc_stats.ast_tx_mgmt++; 1440 } 1441 1442 nextfrag: 1443 next = m->m_nextpkt; 1444 if (ath_tx_start(sc, ni, bf, m)) { 1445 bad: 1446 ifp->if_oerrors++; 1447 reclaim: 1448 ATH_TXBUF_LOCK(sc); 1449 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1450 ath_txfrag_cleanup(sc, &frags, ni); 1451 ATH_TXBUF_UNLOCK(sc); 1452 if (ni != NULL) 1453 ieee80211_free_node(ni); 1454 continue; 1455 } 1456 if (next != NULL) { 1457 m = next; 1458 bf = STAILQ_FIRST(&frags); 1459 KASSERT(bf != NULL, ("no buf for txfrag")); 1460 STAILQ_REMOVE_HEAD(&frags, bf_list); 1461 goto nextfrag; 1462 } 1463 1464 sc->sc_tx_timer = 5; 1465 ifp->if_timer = 1; 1466 } 1467 } 1468 1469 static int 1470 ath_media_change(struct ifnet *ifp) 1471 { 1472 #define IS_UP(ifp) \ 1473 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1474 int error; 1475 1476 error = ieee80211_media_change(ifp); 1477 if (error == ENETRESET) { 1478 if (IS_UP(ifp)) 1479 ath_init(ifp->if_softc); /* XXX lose error */ 1480 error = 0; 1481 } 1482 return error; 1483 #undef IS_UP 1484 } 1485 1486 #ifdef AR_DEBUG 1487 static void 1488 ath_keyprint(const char *tag, u_int ix, 1489 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1490 { 1491 static const char *ciphers[] = { 1492 "WEP", 1493 "AES-OCB", 1494 "AES-CCM", 1495 "CKIP", 1496 "TKIP", 1497 "CLR", 1498 }; 1499 int i, n; 1500 1501 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1502 for (i = 0, n = hk->kv_len; i < n; i++) 1503 printf("%02x", hk->kv_val[i]); 1504 printf(" mac %s", ether_sprintf(mac)); 1505 if (hk->kv_type == HAL_CIPHER_TKIP) { 1506 printf(" mic "); 1507 for (i = 0; i < sizeof(hk->kv_mic); i++) 1508 printf("%02x", hk->kv_mic[i]); 1509 } 1510 printf("\n"); 1511 } 1512 #endif 1513 1514 /* 1515 * Set a TKIP key into the hardware. This handles the 1516 * potential distribution of key state to multiple key 1517 * cache slots for TKIP. 1518 */ 1519 static int 1520 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1521 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1522 { 1523 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1524 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1525 struct ath_hal *ah = sc->sc_ah; 1526 1527 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1528 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1529 KASSERT(sc->sc_splitmic, ("key cache !split")); 1530 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1531 /* 1532 * TX key goes at first index, RX key at the rx index. 1533 * The hal handles the MIC keys at index+64. 1534 */ 1535 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1536 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1537 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1538 return 0; 1539 1540 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1541 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1542 /* XXX delete tx key on failure? */ 1543 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1544 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1545 /* 1546 * TX/RX key goes at first index. 1547 * The hal handles the MIC keys are index+64. 1548 */ 1549 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1550 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1551 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1552 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1553 } 1554 return 0; 1555 #undef IEEE80211_KEY_XR 1556 } 1557 1558 /* 1559 * Set a net80211 key into the hardware. This handles the 1560 * potential distribution of key state to multiple key 1561 * cache slots for TKIP with hardware MIC support. 1562 */ 1563 static int 1564 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1565 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1566 struct ieee80211_node *bss) 1567 { 1568 #define N(a) (sizeof(a)/sizeof(a[0])) 1569 static const u_int8_t ciphermap[] = { 1570 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1571 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1572 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1573 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1574 (u_int8_t) -1, /* 4 is not allocated */ 1575 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1576 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1577 }; 1578 struct ath_hal *ah = sc->sc_ah; 1579 const struct ieee80211_cipher *cip = k->wk_cipher; 1580 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1581 const u_int8_t *mac; 1582 HAL_KEYVAL hk; 1583 1584 memset(&hk, 0, sizeof(hk)); 1585 /* 1586 * Software crypto uses a "clear key" so non-crypto 1587 * state kept in the key cache are maintained and 1588 * so that rx frames have an entry to match. 1589 */ 1590 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1591 KASSERT(cip->ic_cipher < N(ciphermap), 1592 ("invalid cipher type %u", cip->ic_cipher)); 1593 hk.kv_type = ciphermap[cip->ic_cipher]; 1594 hk.kv_len = k->wk_keylen; 1595 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1596 } else 1597 hk.kv_type = HAL_CIPHER_CLR; 1598 1599 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1600 /* 1601 * Group keys on hardware that supports multicast frame 1602 * key search use a mac that is the sender's address with 1603 * the high bit set instead of the app-specified address. 1604 */ 1605 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1606 gmac[0] |= 0x80; 1607 mac = gmac; 1608 } else 1609 mac = mac0; 1610 1611 if (hk.kv_type == HAL_CIPHER_TKIP && 1612 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1613 sc->sc_splitmic) { 1614 return ath_keyset_tkip(sc, k, &hk, mac); 1615 } else { 1616 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1617 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1618 } 1619 #undef N 1620 } 1621 1622 /* 1623 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1624 * each key, one for decrypt/encrypt and the other for the MIC. 1625 */ 1626 static u_int16_t 1627 key_alloc_2pair(struct ath_softc *sc, 1628 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1629 { 1630 #define N(a) (sizeof(a)/sizeof(a[0])) 1631 u_int i, keyix; 1632 1633 KASSERT(sc->sc_splitmic, ("key cache !split")); 1634 /* XXX could optimize */ 1635 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1636 u_int8_t b = sc->sc_keymap[i]; 1637 if (b != 0xff) { 1638 /* 1639 * One or more slots in this byte are free. 1640 */ 1641 keyix = i*NBBY; 1642 while (b & 1) { 1643 again: 1644 keyix++; 1645 b >>= 1; 1646 } 1647 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1648 if (isset(sc->sc_keymap, keyix+32) || 1649 isset(sc->sc_keymap, keyix+64) || 1650 isset(sc->sc_keymap, keyix+32+64)) { 1651 /* full pair unavailable */ 1652 /* XXX statistic */ 1653 if (keyix == (i+1)*NBBY) { 1654 /* no slots were appropriate, advance */ 1655 continue; 1656 } 1657 goto again; 1658 } 1659 setbit(sc->sc_keymap, keyix); 1660 setbit(sc->sc_keymap, keyix+64); 1661 setbit(sc->sc_keymap, keyix+32); 1662 setbit(sc->sc_keymap, keyix+32+64); 1663 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1664 "%s: key pair %u,%u %u,%u\n", 1665 __func__, keyix, keyix+64, 1666 keyix+32, keyix+32+64); 1667 *txkeyix = keyix; 1668 *rxkeyix = keyix+32; 1669 return 1; 1670 } 1671 } 1672 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1673 return 0; 1674 #undef N 1675 } 1676 1677 /* 1678 * Allocate a single key cache slot. 1679 */ 1680 static int 1681 key_alloc_single(struct ath_softc *sc, 1682 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1683 { 1684 #define N(a) (sizeof(a)/sizeof(a[0])) 1685 u_int i, keyix; 1686 1687 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1688 for (i = 0; i < N(sc->sc_keymap); i++) { 1689 u_int8_t b = sc->sc_keymap[i]; 1690 if (b != 0xff) { 1691 /* 1692 * One or more slots are free. 1693 */ 1694 keyix = i*NBBY; 1695 while (b & 1) 1696 keyix++, b >>= 1; 1697 setbit(sc->sc_keymap, keyix); 1698 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1699 __func__, keyix); 1700 *txkeyix = *rxkeyix = keyix; 1701 return 1; 1702 } 1703 } 1704 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1705 return 0; 1706 #undef N 1707 } 1708 1709 /* 1710 * Allocate one or more key cache slots for a uniacst key. The 1711 * key itself is needed only to identify the cipher. For hardware 1712 * TKIP with split cipher+MIC keys we allocate two key cache slot 1713 * pairs so that we can setup separate TX and RX MIC keys. Note 1714 * that the MIC key for a TKIP key at slot i is assumed by the 1715 * hardware to be at slot i+64. This limits TKIP keys to the first 1716 * 64 entries. 1717 */ 1718 static int 1719 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1720 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1721 { 1722 struct ath_softc *sc = ic->ic_ifp->if_softc; 1723 1724 /* 1725 * Group key allocation must be handled specially for 1726 * parts that do not support multicast key cache search 1727 * functionality. For those parts the key id must match 1728 * the h/w key index so lookups find the right key. On 1729 * parts w/ the key search facility we install the sender's 1730 * mac address (with the high bit set) and let the hardware 1731 * find the key w/o using the key id. This is preferred as 1732 * it permits us to support multiple users for adhoc and/or 1733 * multi-station operation. 1734 */ 1735 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1736 if (!(&ic->ic_nw_keys[0] <= k && 1737 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1738 /* should not happen */ 1739 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1740 "%s: bogus group key\n", __func__); 1741 return 0; 1742 } 1743 /* 1744 * XXX we pre-allocate the global keys so 1745 * have no way to check if they've already been allocated. 1746 */ 1747 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1748 return 1; 1749 } 1750 1751 /* 1752 * We allocate two pair for TKIP when using the h/w to do 1753 * the MIC. For everything else, including software crypto, 1754 * we allocate a single entry. Note that s/w crypto requires 1755 * a pass-through slot on the 5211 and 5212. The 5210 does 1756 * not support pass-through cache entries and we map all 1757 * those requests to slot 0. 1758 */ 1759 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1760 return key_alloc_single(sc, keyix, rxkeyix); 1761 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1762 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1763 return key_alloc_2pair(sc, keyix, rxkeyix); 1764 } else { 1765 return key_alloc_single(sc, keyix, rxkeyix); 1766 } 1767 } 1768 1769 /* 1770 * Delete an entry in the key cache allocated by ath_key_alloc. 1771 */ 1772 static int 1773 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1774 { 1775 struct ath_softc *sc = ic->ic_ifp->if_softc; 1776 struct ath_hal *ah = sc->sc_ah; 1777 const struct ieee80211_cipher *cip = k->wk_cipher; 1778 u_int keyix = k->wk_keyix; 1779 1780 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1781 1782 ath_hal_keyreset(ah, keyix); 1783 /* 1784 * Handle split tx/rx keying required for TKIP with h/w MIC. 1785 */ 1786 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1787 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1788 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1789 if (keyix >= IEEE80211_WEP_NKID) { 1790 /* 1791 * Don't touch keymap entries for global keys so 1792 * they are never considered for dynamic allocation. 1793 */ 1794 clrbit(sc->sc_keymap, keyix); 1795 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1796 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1797 sc->sc_splitmic) { 1798 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1799 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1800 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1801 } 1802 } 1803 return 1; 1804 } 1805 1806 /* 1807 * Set the key cache contents for the specified key. Key cache 1808 * slot(s) must already have been allocated by ath_key_alloc. 1809 */ 1810 static int 1811 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1812 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1813 { 1814 struct ath_softc *sc = ic->ic_ifp->if_softc; 1815 1816 return ath_keyset(sc, k, mac, ic->ic_bss); 1817 } 1818 1819 /* 1820 * Block/unblock tx+rx processing while a key change is done. 1821 * We assume the caller serializes key management operations 1822 * so we only need to worry about synchronization with other 1823 * uses that originate in the driver. 1824 */ 1825 static void 1826 ath_key_update_begin(struct ieee80211com *ic) 1827 { 1828 struct ifnet *ifp = ic->ic_ifp; 1829 struct ath_softc *sc = ifp->if_softc; 1830 1831 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1832 #if 0 1833 tasklet_disable(&sc->sc_rxtq); 1834 #endif 1835 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1836 } 1837 1838 static void 1839 ath_key_update_end(struct ieee80211com *ic) 1840 { 1841 struct ifnet *ifp = ic->ic_ifp; 1842 struct ath_softc *sc = ifp->if_softc; 1843 1844 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1845 IF_UNLOCK(&ifp->if_snd); 1846 #if 0 1847 tasklet_enable(&sc->sc_rxtq); 1848 #endif 1849 } 1850 1851 /* 1852 * Calculate the receive filter according to the 1853 * operating mode and state: 1854 * 1855 * o always accept unicast, broadcast, and multicast traffic 1856 * o maintain current state of phy error reception (the hal 1857 * may enable phy error frames for noise immunity work) 1858 * o probe request frames are accepted only when operating in 1859 * hostap, adhoc, or monitor modes 1860 * o enable promiscuous mode according to the interface state 1861 * o accept beacons: 1862 * - when operating in adhoc mode so the 802.11 layer creates 1863 * node table entries for peers, 1864 * - when operating in station mode for collecting rssi data when 1865 * the station is otherwise quiet, or 1866 * - when scanning 1867 */ 1868 static u_int32_t 1869 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1870 { 1871 struct ieee80211com *ic = &sc->sc_ic; 1872 struct ath_hal *ah = sc->sc_ah; 1873 struct ifnet *ifp = &sc->sc_if; 1874 u_int32_t rfilt; 1875 1876 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1877 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1878 if (ic->ic_opmode != IEEE80211_M_STA) 1879 rfilt |= HAL_RX_FILTER_PROBEREQ; 1880 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1881 (ifp->if_flags & IFF_PROMISC)) 1882 rfilt |= HAL_RX_FILTER_PROM; 1883 if (ic->ic_opmode == IEEE80211_M_STA || 1884 ic->ic_opmode == IEEE80211_M_IBSS || 1885 state == IEEE80211_S_SCAN) 1886 rfilt |= HAL_RX_FILTER_BEACON; 1887 return rfilt; 1888 } 1889 1890 static void 1891 ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1892 { 1893 u_int32_t val; 1894 u_int8_t pos; 1895 1896 /* calculate XOR of eight 6bit values */ 1897 val = LE_READ_4(dl + 0); 1898 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1899 val = LE_READ_4(dl + 3); 1900 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1901 pos &= 0x3f; 1902 mfilt[pos / 32] |= (1 << (pos % 32)); 1903 } 1904 1905 static void 1906 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1907 { 1908 struct ifnet *ifp = &sc->sc_if; 1909 struct ether_multi *enm; 1910 struct ether_multistep estep; 1911 1912 mfilt[0] = mfilt[1] = 0; 1913 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1914 while (enm != NULL) { 1915 /* XXX Punt on ranges. */ 1916 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1917 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1918 ifp->if_flags |= IFF_ALLMULTI; 1919 return; 1920 } 1921 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1922 ETHER_NEXT_MULTI(estep, enm); 1923 } 1924 ifp->if_flags &= ~IFF_ALLMULTI; 1925 } 1926 1927 static void 1928 ath_mode_init(struct ath_softc *sc) 1929 { 1930 struct ieee80211com *ic = &sc->sc_ic; 1931 struct ath_hal *ah = sc->sc_ah; 1932 u_int32_t rfilt, mfilt[2]; 1933 int i; 1934 1935 /* configure rx filter */ 1936 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1937 ath_hal_setrxfilter(ah, rfilt); 1938 1939 /* configure operational mode */ 1940 ath_hal_setopmode(ah); 1941 1942 /* Write keys to hardware; it may have been powered down. */ 1943 ath_key_update_begin(ic); 1944 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1945 ath_key_set(ic, 1946 &ic->ic_crypto.cs_nw_keys[i], 1947 ic->ic_myaddr); 1948 } 1949 ath_key_update_end(ic); 1950 1951 /* 1952 * Handle any link-level address change. Note that we only 1953 * need to force ic_myaddr; any other addresses are handled 1954 * as a byproduct of the ifnet code marking the interface 1955 * down then up. 1956 * 1957 * XXX should get from lladdr instead of arpcom but that's more work 1958 */ 1959 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1960 ath_hal_setmac(ah, ic->ic_myaddr); 1961 1962 /* calculate and install multicast filter */ 1963 #ifdef __FreeBSD__ 1964 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1965 mfilt[0] = mfilt[1] = 0; 1966 IF_ADDR_LOCK(ifp); 1967 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1968 caddr_t dl; 1969 1970 /* calculate XOR of eight 6bit values */ 1971 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1972 val = LE_READ_4(dl + 0); 1973 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1974 val = LE_READ_4(dl + 3); 1975 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1976 pos &= 0x3f; 1977 mfilt[pos / 32] |= (1 << (pos % 32)); 1978 } 1979 IF_ADDR_UNLOCK(ifp); 1980 } else { 1981 mfilt[0] = mfilt[1] = ~0; 1982 } 1983 #endif 1984 #ifdef __NetBSD__ 1985 ath_mcastfilter_compute(sc, mfilt); 1986 #endif 1987 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1988 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1989 __func__, rfilt, mfilt[0], mfilt[1]); 1990 } 1991 1992 /* 1993 * Set the slot time based on the current setting. 1994 */ 1995 static void 1996 ath_setslottime(struct ath_softc *sc) 1997 { 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ath_hal *ah = sc->sc_ah; 2000 2001 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2002 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2003 else 2004 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2005 sc->sc_updateslot = OK; 2006 } 2007 2008 /* 2009 * Callback from the 802.11 layer to update the 2010 * slot time based on the current setting. 2011 */ 2012 static void 2013 ath_updateslot(struct ifnet *ifp) 2014 { 2015 struct ath_softc *sc = ifp->if_softc; 2016 struct ieee80211com *ic = &sc->sc_ic; 2017 2018 /* 2019 * When not coordinating the BSS, change the hardware 2020 * immediately. For other operation we defer the change 2021 * until beacon updates have propagated to the stations. 2022 */ 2023 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2024 sc->sc_updateslot = UPDATE; 2025 else 2026 ath_setslottime(sc); 2027 } 2028 2029 /* 2030 * Setup a h/w transmit queue for beacons. 2031 */ 2032 static int 2033 ath_beaconq_setup(struct ath_hal *ah) 2034 { 2035 HAL_TXQ_INFO qi; 2036 2037 memset(&qi, 0, sizeof(qi)); 2038 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2039 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2040 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2041 /* NB: for dynamic turbo, don't enable any other interrupts */ 2042 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2043 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2044 } 2045 2046 /* 2047 * Setup the transmit queue parameters for the beacon queue. 2048 */ 2049 static int 2050 ath_beaconq_config(struct ath_softc *sc) 2051 { 2052 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2053 struct ieee80211com *ic = &sc->sc_ic; 2054 struct ath_hal *ah = sc->sc_ah; 2055 HAL_TXQ_INFO qi; 2056 2057 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2058 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2059 /* 2060 * Always burst out beacon and CAB traffic. 2061 */ 2062 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2063 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2064 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2065 } else { 2066 struct wmeParams *wmep = 2067 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2068 /* 2069 * Adhoc mode; important thing is to use 2x cwmin. 2070 */ 2071 qi.tqi_aifs = wmep->wmep_aifsn; 2072 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2073 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2074 } 2075 2076 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2077 device_printf(sc->sc_dev, "unable to update parameters for " 2078 "beacon hardware queue!\n"); 2079 return 0; 2080 } else { 2081 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2082 return 1; 2083 } 2084 #undef ATH_EXPONENT_TO_VALUE 2085 } 2086 2087 /* 2088 * Allocate and setup an initial beacon frame. 2089 */ 2090 static int 2091 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2092 { 2093 struct ieee80211com *ic = ni->ni_ic; 2094 struct ath_buf *bf; 2095 struct mbuf *m; 2096 int error; 2097 2098 bf = STAILQ_FIRST(&sc->sc_bbuf); 2099 if (bf == NULL) { 2100 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2101 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2102 return ENOMEM; /* XXX */ 2103 } 2104 /* 2105 * NB: the beacon data buffer must be 32-bit aligned; 2106 * we assume the mbuf routines will return us something 2107 * with this alignment (perhaps should assert). 2108 */ 2109 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2110 if (m == NULL) { 2111 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2112 __func__); 2113 sc->sc_stats.ast_be_nombuf++; 2114 return ENOMEM; 2115 } 2116 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2117 BUS_DMA_NOWAIT); 2118 if (error == 0) { 2119 bf->bf_m = m; 2120 bf->bf_node = ieee80211_ref_node(ni); 2121 } else { 2122 m_freem(m); 2123 } 2124 return error; 2125 } 2126 2127 /* 2128 * Setup the beacon frame for transmit. 2129 */ 2130 static void 2131 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2132 { 2133 #define USE_SHPREAMBLE(_ic) \ 2134 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2135 == IEEE80211_F_SHPREAMBLE) 2136 struct ieee80211_node *ni = bf->bf_node; 2137 struct ieee80211com *ic = ni->ni_ic; 2138 struct mbuf *m = bf->bf_m; 2139 struct ath_hal *ah = sc->sc_ah; 2140 struct ath_desc *ds; 2141 int flags, antenna; 2142 const HAL_RATE_TABLE *rt; 2143 u_int8_t rix, rate; 2144 2145 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2146 __func__, m, m->m_len); 2147 2148 /* setup descriptors */ 2149 ds = bf->bf_desc; 2150 2151 flags = HAL_TXDESC_NOACK; 2152 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2153 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2154 flags |= HAL_TXDESC_VEOL; 2155 /* 2156 * Let hardware handle antenna switching unless 2157 * the user has selected a transmit antenna 2158 * (sc_txantenna is not 0). 2159 */ 2160 antenna = sc->sc_txantenna; 2161 } else { 2162 ds->ds_link = 0; 2163 /* 2164 * Switch antenna every 4 beacons, unless the user 2165 * has selected a transmit antenna (sc_txantenna 2166 * is not 0). 2167 * 2168 * XXX assumes two antenna 2169 */ 2170 if (sc->sc_txantenna == 0) 2171 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2172 else 2173 antenna = sc->sc_txantenna; 2174 } 2175 2176 KASSERT(bf->bf_nseg == 1, 2177 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2178 ds->ds_data = bf->bf_segs[0].ds_addr; 2179 /* 2180 * Calculate rate code. 2181 * XXX everything at min xmit rate 2182 */ 2183 rix = sc->sc_minrateix; 2184 rt = sc->sc_currates; 2185 rate = rt->info[rix].rateCode; 2186 if (USE_SHPREAMBLE(ic)) 2187 rate |= rt->info[rix].shortPreamble; 2188 ath_hal_setuptxdesc(ah, ds 2189 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2190 , sizeof(struct ieee80211_frame)/* header length */ 2191 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2192 , ni->ni_txpower /* txpower XXX */ 2193 , rate, 1 /* series 0 rate/tries */ 2194 , HAL_TXKEYIX_INVALID /* no encryption */ 2195 , antenna /* antenna mode */ 2196 , flags /* no ack, veol for beacons */ 2197 , 0 /* rts/cts rate */ 2198 , 0 /* rts/cts duration */ 2199 ); 2200 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2201 ath_hal_filltxdesc(ah, ds 2202 , roundup(m->m_len, 4) /* buffer length */ 2203 , AH_TRUE /* first segment */ 2204 , AH_TRUE /* last segment */ 2205 , ds /* first descriptor */ 2206 ); 2207 2208 /* NB: The desc swap function becomes void, 2209 * if descriptor swapping is not enabled 2210 */ 2211 ath_desc_swap(ds); 2212 2213 #undef USE_SHPREAMBLE 2214 } 2215 2216 /* 2217 * Transmit a beacon frame at SWBA. Dynamic updates to the 2218 * frame contents are done as needed and the slot time is 2219 * also adjusted based on current state. 2220 */ 2221 static void 2222 ath_beacon_proc(void *arg, int pending) 2223 { 2224 struct ath_softc *sc = arg; 2225 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2226 struct ieee80211_node *ni = bf->bf_node; 2227 struct ieee80211com *ic = ni->ni_ic; 2228 struct ath_hal *ah = sc->sc_ah; 2229 struct mbuf *m; 2230 int ncabq, error, otherant; 2231 2232 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2233 __func__, pending); 2234 2235 if (ic->ic_opmode == IEEE80211_M_STA || 2236 ic->ic_opmode == IEEE80211_M_MONITOR || 2237 bf == NULL || bf->bf_m == NULL) { 2238 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2239 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2240 return; 2241 } 2242 /* 2243 * Check if the previous beacon has gone out. If 2244 * not don't try to post another, skip this period 2245 * and wait for the next. Missed beacons indicate 2246 * a problem and should not occur. If we miss too 2247 * many consecutive beacons reset the device. 2248 */ 2249 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2250 sc->sc_bmisscount++; 2251 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2252 "%s: missed %u consecutive beacons\n", 2253 __func__, sc->sc_bmisscount); 2254 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2255 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2256 return; 2257 } 2258 if (sc->sc_bmisscount != 0) { 2259 DPRINTF(sc, ATH_DEBUG_BEACON, 2260 "%s: resume beacon xmit after %u misses\n", 2261 __func__, sc->sc_bmisscount); 2262 sc->sc_bmisscount = 0; 2263 } 2264 2265 /* 2266 * Update dynamic beacon contents. If this returns 2267 * non-zero then we need to remap the memory because 2268 * the beacon frame changed size (probably because 2269 * of the TIM bitmap). 2270 */ 2271 m = bf->bf_m; 2272 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2273 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2274 /* XXX too conservative? */ 2275 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2276 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2277 BUS_DMA_NOWAIT); 2278 if (error != 0) { 2279 if_printf(&sc->sc_if, 2280 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2281 __func__, error); 2282 return; 2283 } 2284 } 2285 2286 /* 2287 * Handle slot time change when a non-ERP station joins/leaves 2288 * an 11g network. The 802.11 layer notifies us via callback, 2289 * we mark updateslot, then wait one beacon before effecting 2290 * the change. This gives associated stations at least one 2291 * beacon interval to note the state change. 2292 */ 2293 /* XXX locking */ 2294 if (sc->sc_updateslot == UPDATE) 2295 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2296 else if (sc->sc_updateslot == COMMIT) 2297 ath_setslottime(sc); /* commit change to h/w */ 2298 2299 /* 2300 * Check recent per-antenna transmit statistics and flip 2301 * the default antenna if noticeably more frames went out 2302 * on the non-default antenna. 2303 * XXX assumes 2 anntenae 2304 */ 2305 otherant = sc->sc_defant & 1 ? 2 : 1; 2306 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2307 ath_setdefantenna(sc, otherant); 2308 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2309 2310 /* 2311 * Construct tx descriptor. 2312 */ 2313 ath_beacon_setup(sc, bf); 2314 2315 /* 2316 * Stop any current dma and put the new frame on the queue. 2317 * This should never fail since we check above that no frames 2318 * are still pending on the queue. 2319 */ 2320 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2321 DPRINTF(sc, ATH_DEBUG_ANY, 2322 "%s: beacon queue %u did not stop?\n", 2323 __func__, sc->sc_bhalq); 2324 } 2325 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2326 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2327 2328 /* 2329 * Enable the CAB queue before the beacon queue to 2330 * insure cab frames are triggered by this beacon. 2331 */ 2332 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2333 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2334 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2335 ath_hal_txstart(ah, sc->sc_bhalq); 2336 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2337 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2338 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2339 2340 sc->sc_stats.ast_be_xmit++; 2341 } 2342 2343 /* 2344 * Reset the hardware after detecting beacons have stopped. 2345 */ 2346 static void 2347 ath_bstuck_proc(void *arg, int pending) 2348 { 2349 struct ath_softc *sc = arg; 2350 struct ifnet *ifp = &sc->sc_if; 2351 2352 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2353 sc->sc_bmisscount); 2354 ath_reset(ifp); 2355 } 2356 2357 /* 2358 * Reclaim beacon resources. 2359 */ 2360 static void 2361 ath_beacon_free(struct ath_softc *sc) 2362 { 2363 struct ath_buf *bf; 2364 2365 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2366 if (bf->bf_m != NULL) { 2367 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2368 m_freem(bf->bf_m); 2369 bf->bf_m = NULL; 2370 } 2371 if (bf->bf_node != NULL) { 2372 ieee80211_free_node(bf->bf_node); 2373 bf->bf_node = NULL; 2374 } 2375 } 2376 } 2377 2378 /* 2379 * Configure the beacon and sleep timers. 2380 * 2381 * When operating as an AP this resets the TSF and sets 2382 * up the hardware to notify us when we need to issue beacons. 2383 * 2384 * When operating in station mode this sets up the beacon 2385 * timers according to the timestamp of the last received 2386 * beacon and the current TSF, configures PCF and DTIM 2387 * handling, programs the sleep registers so the hardware 2388 * will wakeup in time to receive beacons, and configures 2389 * the beacon miss handling so we'll receive a BMISS 2390 * interrupt when we stop seeing beacons from the AP 2391 * we've associated with. 2392 */ 2393 static void 2394 ath_beacon_config(struct ath_softc *sc) 2395 { 2396 #define TSF_TO_TU(_h,_l) \ 2397 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2398 #define FUDGE 2 2399 struct ath_hal *ah = sc->sc_ah; 2400 struct ieee80211com *ic = &sc->sc_ic; 2401 struct ieee80211_node *ni = ic->ic_bss; 2402 u_int32_t nexttbtt, intval, tsftu; 2403 u_int64_t tsf; 2404 2405 /* extract tstamp from last beacon and convert to TU */ 2406 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2407 LE_READ_4(ni->ni_tstamp.data)); 2408 /* NB: the beacon interval is kept internally in TU's */ 2409 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2410 if (nexttbtt == 0) /* e.g. for ap mode */ 2411 nexttbtt = intval; 2412 else if (intval) /* NB: can be 0 for monitor mode */ 2413 nexttbtt = roundup(nexttbtt, intval); 2414 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2415 __func__, nexttbtt, intval, ni->ni_intval); 2416 if (ic->ic_opmode == IEEE80211_M_STA) { 2417 HAL_BEACON_STATE bs; 2418 int dtimperiod, dtimcount; 2419 int cfpperiod, cfpcount; 2420 2421 /* 2422 * Setup dtim and cfp parameters according to 2423 * last beacon we received (which may be none). 2424 */ 2425 dtimperiod = ni->ni_dtim_period; 2426 if (dtimperiod <= 0) /* NB: 0 if not known */ 2427 dtimperiod = 1; 2428 dtimcount = ni->ni_dtim_count; 2429 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2430 dtimcount = 0; /* XXX? */ 2431 cfpperiod = 1; /* NB: no PCF support yet */ 2432 cfpcount = 0; 2433 /* 2434 * Pull nexttbtt forward to reflect the current 2435 * TSF and calculate dtim+cfp state for the result. 2436 */ 2437 tsf = ath_hal_gettsf64(ah); 2438 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2439 do { 2440 nexttbtt += intval; 2441 if (--dtimcount < 0) { 2442 dtimcount = dtimperiod - 1; 2443 if (--cfpcount < 0) 2444 cfpcount = cfpperiod - 1; 2445 } 2446 } while (nexttbtt < tsftu); 2447 memset(&bs, 0, sizeof(bs)); 2448 bs.bs_intval = intval; 2449 bs.bs_nexttbtt = nexttbtt; 2450 bs.bs_dtimperiod = dtimperiod*intval; 2451 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2452 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2453 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2454 bs.bs_cfpmaxduration = 0; 2455 #if 0 2456 /* 2457 * The 802.11 layer records the offset to the DTIM 2458 * bitmap while receiving beacons; use it here to 2459 * enable h/w detection of our AID being marked in 2460 * the bitmap vector (to indicate frames for us are 2461 * pending at the AP). 2462 * XXX do DTIM handling in s/w to WAR old h/w bugs 2463 * XXX enable based on h/w rev for newer chips 2464 */ 2465 bs.bs_timoffset = ni->ni_timoff; 2466 #endif 2467 /* 2468 * Calculate the number of consecutive beacons to miss 2469 * before taking a BMISS interrupt. The configuration 2470 * is specified in ms, so we need to convert that to 2471 * TU's and then calculate based on the beacon interval. 2472 * Note that we clamp the result to at most 10 beacons. 2473 */ 2474 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2475 if (bs.bs_bmissthreshold > 10) 2476 bs.bs_bmissthreshold = 10; 2477 else if (bs.bs_bmissthreshold <= 0) 2478 bs.bs_bmissthreshold = 1; 2479 2480 /* 2481 * Calculate sleep duration. The configuration is 2482 * given in ms. We insure a multiple of the beacon 2483 * period is used. Also, if the sleep duration is 2484 * greater than the DTIM period then it makes senses 2485 * to make it a multiple of that. 2486 * 2487 * XXX fixed at 100ms 2488 */ 2489 bs.bs_sleepduration = 2490 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2491 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2492 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2493 2494 DPRINTF(sc, ATH_DEBUG_BEACON, 2495 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2496 , __func__ 2497 , tsf, tsftu 2498 , bs.bs_intval 2499 , bs.bs_nexttbtt 2500 , bs.bs_dtimperiod 2501 , bs.bs_nextdtim 2502 , bs.bs_bmissthreshold 2503 , bs.bs_sleepduration 2504 , bs.bs_cfpperiod 2505 , bs.bs_cfpmaxduration 2506 , bs.bs_cfpnext 2507 , bs.bs_timoffset 2508 ); 2509 ath_hal_intrset(ah, 0); 2510 ath_hal_beacontimers(ah, &bs); 2511 sc->sc_imask |= HAL_INT_BMISS; 2512 ath_hal_intrset(ah, sc->sc_imask); 2513 } else { 2514 ath_hal_intrset(ah, 0); 2515 if (nexttbtt == intval) 2516 intval |= HAL_BEACON_RESET_TSF; 2517 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2518 /* 2519 * In IBSS mode enable the beacon timers but only 2520 * enable SWBA interrupts if we need to manually 2521 * prepare beacon frames. Otherwise we use a 2522 * self-linked tx descriptor and let the hardware 2523 * deal with things. 2524 */ 2525 intval |= HAL_BEACON_ENA; 2526 if (!sc->sc_hasveol) 2527 sc->sc_imask |= HAL_INT_SWBA; 2528 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2529 /* 2530 * Pull nexttbtt forward to reflect 2531 * the current TSF. 2532 */ 2533 tsf = ath_hal_gettsf64(ah); 2534 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2535 do { 2536 nexttbtt += intval; 2537 } while (nexttbtt < tsftu); 2538 } 2539 ath_beaconq_config(sc); 2540 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2541 /* 2542 * In AP mode we enable the beacon timers and 2543 * SWBA interrupts to prepare beacon frames. 2544 */ 2545 intval |= HAL_BEACON_ENA; 2546 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2547 ath_beaconq_config(sc); 2548 } 2549 ath_hal_beaconinit(ah, nexttbtt, intval); 2550 sc->sc_bmisscount = 0; 2551 ath_hal_intrset(ah, sc->sc_imask); 2552 /* 2553 * When using a self-linked beacon descriptor in 2554 * ibss mode load it once here. 2555 */ 2556 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2557 ath_beacon_proc(sc, 0); 2558 } 2559 sc->sc_syncbeacon = 0; 2560 #undef UNDEF 2561 #undef TSF_TO_TU 2562 } 2563 2564 static int 2565 ath_descdma_setup(struct ath_softc *sc, 2566 struct ath_descdma *dd, ath_bufhead *head, 2567 const char *name, int nbuf, int ndesc) 2568 { 2569 #define DS2PHYS(_dd, _ds) \ 2570 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2571 struct ifnet *ifp = &sc->sc_if; 2572 struct ath_desc *ds; 2573 struct ath_buf *bf; 2574 int i, bsize, error; 2575 2576 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2577 __func__, name, nbuf, ndesc); 2578 2579 dd->dd_name = name; 2580 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2581 2582 /* 2583 * Setup DMA descriptor area. 2584 */ 2585 dd->dd_dmat = sc->sc_dmat; 2586 2587 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2588 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2589 2590 if (error != 0) { 2591 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2592 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2593 goto fail0; 2594 } 2595 2596 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2597 dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2598 if (error != 0) { 2599 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2600 nbuf * ndesc, dd->dd_name, error); 2601 goto fail1; 2602 } 2603 2604 /* allocate descriptors */ 2605 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2606 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2607 if (error != 0) { 2608 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2609 "error %u\n", dd->dd_name, error); 2610 goto fail2; 2611 } 2612 2613 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2614 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2615 if (error != 0) { 2616 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2617 dd->dd_name, error); 2618 goto fail3; 2619 } 2620 2621 ds = dd->dd_desc; 2622 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2623 DPRINTF(sc, ATH_DEBUG_RESET, 2624 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2625 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2626 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2627 2628 /* allocate rx buffers */ 2629 bsize = sizeof(struct ath_buf) * nbuf; 2630 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2631 if (bf == NULL) { 2632 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2633 dd->dd_name, bsize); 2634 goto fail4; 2635 } 2636 dd->dd_bufptr = bf; 2637 2638 STAILQ_INIT(head); 2639 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2640 bf->bf_desc = ds; 2641 bf->bf_daddr = DS2PHYS(dd, ds); 2642 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2643 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2644 if (error != 0) { 2645 if_printf(ifp, "unable to create dmamap for %s " 2646 "buffer %u, error %u\n", dd->dd_name, i, error); 2647 ath_descdma_cleanup(sc, dd, head); 2648 return error; 2649 } 2650 STAILQ_INSERT_TAIL(head, bf, bf_list); 2651 } 2652 return 0; 2653 fail4: 2654 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2655 fail3: 2656 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2657 fail2: 2658 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2659 fail1: 2660 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2661 fail0: 2662 memset(dd, 0, sizeof(*dd)); 2663 return error; 2664 #undef DS2PHYS 2665 } 2666 2667 static void 2668 ath_descdma_cleanup(struct ath_softc *sc, 2669 struct ath_descdma *dd, ath_bufhead *head) 2670 { 2671 struct ath_buf *bf; 2672 struct ieee80211_node *ni; 2673 2674 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2675 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2676 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2677 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2678 2679 STAILQ_FOREACH(bf, head, bf_list) { 2680 if (bf->bf_m) { 2681 m_freem(bf->bf_m); 2682 bf->bf_m = NULL; 2683 } 2684 if (bf->bf_dmamap != NULL) { 2685 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2686 bf->bf_dmamap = NULL; 2687 } 2688 ni = bf->bf_node; 2689 bf->bf_node = NULL; 2690 if (ni != NULL) { 2691 /* 2692 * Reclaim node reference. 2693 */ 2694 ieee80211_free_node(ni); 2695 } 2696 } 2697 2698 STAILQ_INIT(head); 2699 free(dd->dd_bufptr, M_ATHDEV); 2700 memset(dd, 0, sizeof(*dd)); 2701 } 2702 2703 static int 2704 ath_desc_alloc(struct ath_softc *sc) 2705 { 2706 int error; 2707 2708 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2709 "rx", ath_rxbuf, 1); 2710 if (error != 0) 2711 return error; 2712 2713 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2714 "tx", ath_txbuf, ATH_TXDESC); 2715 if (error != 0) { 2716 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2717 return error; 2718 } 2719 2720 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2721 "beacon", 1, 1); 2722 if (error != 0) { 2723 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2724 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2725 return error; 2726 } 2727 return 0; 2728 } 2729 2730 static void 2731 ath_desc_free(struct ath_softc *sc) 2732 { 2733 2734 if (sc->sc_bdma.dd_desc_len != 0) 2735 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2736 if (sc->sc_txdma.dd_desc_len != 0) 2737 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2738 if (sc->sc_rxdma.dd_desc_len != 0) 2739 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2740 } 2741 2742 static struct ieee80211_node * 2743 ath_node_alloc(struct ieee80211_node_table *nt) 2744 { 2745 struct ieee80211com *ic = nt->nt_ic; 2746 struct ath_softc *sc = ic->ic_ifp->if_softc; 2747 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2748 struct ath_node *an; 2749 2750 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2751 if (an == NULL) { 2752 /* XXX stat+msg */ 2753 return NULL; 2754 } 2755 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2756 ath_rate_node_init(sc, an); 2757 2758 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2759 return &an->an_node; 2760 } 2761 2762 static void 2763 ath_node_free(struct ieee80211_node *ni) 2764 { 2765 struct ieee80211com *ic = ni->ni_ic; 2766 struct ath_softc *sc = ic->ic_ifp->if_softc; 2767 2768 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2769 2770 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2771 sc->sc_node_free(ni); 2772 } 2773 2774 static u_int8_t 2775 ath_node_getrssi(const struct ieee80211_node *ni) 2776 { 2777 #define HAL_EP_RND(x, mul) \ 2778 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2779 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2780 int32_t rssi; 2781 2782 /* 2783 * When only one frame is received there will be no state in 2784 * avgrssi so fallback on the value recorded by the 802.11 layer. 2785 */ 2786 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2787 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2788 else 2789 rssi = ni->ni_rssi; 2790 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2791 #undef HAL_EP_RND 2792 } 2793 2794 static int 2795 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2796 { 2797 struct ath_hal *ah = sc->sc_ah; 2798 int error; 2799 struct mbuf *m; 2800 struct ath_desc *ds; 2801 2802 m = bf->bf_m; 2803 if (m == NULL) { 2804 /* 2805 * NB: by assigning a page to the rx dma buffer we 2806 * implicitly satisfy the Atheros requirement that 2807 * this buffer be cache-line-aligned and sized to be 2808 * multiple of the cache line size. Not doing this 2809 * causes weird stuff to happen (for the 5210 at least). 2810 */ 2811 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2812 if (m == NULL) { 2813 DPRINTF(sc, ATH_DEBUG_ANY, 2814 "%s: no mbuf/cluster\n", __func__); 2815 sc->sc_stats.ast_rx_nombuf++; 2816 return ENOMEM; 2817 } 2818 bf->bf_m = m; 2819 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2820 2821 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2822 bf->bf_dmamap, m, 2823 BUS_DMA_NOWAIT); 2824 if (error != 0) { 2825 DPRINTF(sc, ATH_DEBUG_ANY, 2826 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2827 __func__, error); 2828 sc->sc_stats.ast_rx_busdma++; 2829 return error; 2830 } 2831 KASSERT(bf->bf_nseg == 1, 2832 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2833 } 2834 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2835 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2836 2837 /* 2838 * Setup descriptors. For receive we always terminate 2839 * the descriptor list with a self-linked entry so we'll 2840 * not get overrun under high load (as can happen with a 2841 * 5212 when ANI processing enables PHY error frames). 2842 * 2843 * To insure the last descriptor is self-linked we create 2844 * each descriptor as self-linked and add it to the end. As 2845 * each additional descriptor is added the previous self-linked 2846 * entry is ``fixed'' naturally. This should be safe even 2847 * if DMA is happening. When processing RX interrupts we 2848 * never remove/process the last, self-linked, entry on the 2849 * descriptor list. This insures the hardware always has 2850 * someplace to write a new frame. 2851 */ 2852 ds = bf->bf_desc; 2853 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2854 ds->ds_data = bf->bf_segs[0].ds_addr; 2855 ds->ds_vdata = mtod(m, void *); /* for radar */ 2856 ath_hal_setuprxdesc(ah, ds 2857 , m->m_len /* buffer size */ 2858 , 0 2859 ); 2860 2861 if (sc->sc_rxlink != NULL) 2862 *sc->sc_rxlink = bf->bf_daddr; 2863 sc->sc_rxlink = &ds->ds_link; 2864 return 0; 2865 } 2866 2867 /* 2868 * Extend 15-bit time stamp from rx descriptor to 2869 * a full 64-bit TSF using the specified TSF. 2870 */ 2871 static inline u_int64_t 2872 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2873 { 2874 if ((tsf & 0x7fff) < rstamp) 2875 tsf -= 0x8000; 2876 return ((tsf &~ 0x7fff) | rstamp); 2877 } 2878 2879 /* 2880 * Intercept management frames to collect beacon rssi data 2881 * and to do ibss merges. 2882 */ 2883 static void 2884 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2885 struct ieee80211_node *ni, 2886 int subtype, int rssi, u_int32_t rstamp) 2887 { 2888 struct ath_softc *sc = ic->ic_ifp->if_softc; 2889 2890 /* 2891 * Call up first so subsequent work can use information 2892 * potentially stored in the node (e.g. for ibss merge). 2893 */ 2894 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2895 switch (subtype) { 2896 case IEEE80211_FC0_SUBTYPE_BEACON: 2897 /* update rssi statistics for use by the hal */ 2898 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2899 if (sc->sc_syncbeacon && 2900 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2901 /* 2902 * Resync beacon timers using the tsf of the beacon 2903 * frame we just received. 2904 */ 2905 ath_beacon_config(sc); 2906 } 2907 /* fall thru... */ 2908 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2909 if (ic->ic_opmode == IEEE80211_M_IBSS && 2910 ic->ic_state == IEEE80211_S_RUN) { 2911 u_int64_t tsf = ath_extend_tsf(rstamp, 2912 ath_hal_gettsf64(sc->sc_ah)); 2913 2914 /* 2915 * Handle ibss merge as needed; check the tsf on the 2916 * frame before attempting the merge. The 802.11 spec 2917 * says the station should change it's bssid to match 2918 * the oldest station with the same ssid, where oldest 2919 * is determined by the tsf. Note that hardware 2920 * reconfiguration happens through callback to 2921 * ath_newstate as the state machine will go from 2922 * RUN -> RUN when this happens. 2923 */ 2924 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2925 DPRINTF(sc, ATH_DEBUG_STATE, 2926 "ibss merge, rstamp %u tsf %ju " 2927 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2928 (uintmax_t)ni->ni_tstamp.tsf); 2929 (void) ieee80211_ibss_merge(ni); 2930 } 2931 } 2932 break; 2933 } 2934 } 2935 2936 /* 2937 * Set the default antenna. 2938 */ 2939 static void 2940 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2941 { 2942 struct ath_hal *ah = sc->sc_ah; 2943 2944 /* XXX block beacon interrupts */ 2945 ath_hal_setdefantenna(ah, antenna); 2946 if (sc->sc_defant != antenna) 2947 sc->sc_stats.ast_ant_defswitch++; 2948 sc->sc_defant = antenna; 2949 sc->sc_rxotherant = 0; 2950 } 2951 2952 static void 2953 ath_rx_proc(void *arg, int npending) 2954 { 2955 #define PA2DESC(_sc, _pa) \ 2956 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2957 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2958 struct ath_softc *sc = arg; 2959 struct ath_buf *bf; 2960 struct ieee80211com *ic = &sc->sc_ic; 2961 struct ifnet *ifp = &sc->sc_if; 2962 struct ath_hal *ah = sc->sc_ah; 2963 struct ath_desc *ds; 2964 struct mbuf *m; 2965 struct ieee80211_node *ni; 2966 struct ath_node *an; 2967 int len, type, ngood; 2968 u_int phyerr; 2969 HAL_STATUS status; 2970 int16_t nf; 2971 u_int64_t tsf; 2972 2973 NET_LOCK_GIANT(); /* XXX */ 2974 2975 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2976 ngood = 0; 2977 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2978 tsf = ath_hal_gettsf64(ah); 2979 do { 2980 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2981 if (bf == NULL) { /* NB: shouldn't happen */ 2982 if_printf(ifp, "%s: no buffer!\n", __func__); 2983 break; 2984 } 2985 ds = bf->bf_desc; 2986 if (ds->ds_link == bf->bf_daddr) { 2987 /* NB: never process the self-linked entry at the end */ 2988 break; 2989 } 2990 m = bf->bf_m; 2991 if (m == NULL) { /* NB: shouldn't happen */ 2992 if_printf(ifp, "%s: no mbuf!\n", __func__); 2993 break; 2994 } 2995 /* XXX sync descriptor memory */ 2996 /* 2997 * Must provide the virtual address of the current 2998 * descriptor, the physical address, and the virtual 2999 * address of the next descriptor in the h/w chain. 3000 * This allows the HAL to look ahead to see if the 3001 * hardware is done with a descriptor by checking the 3002 * done bit in the following descriptor and the address 3003 * of the current descriptor the DMA engine is working 3004 * on. All this is necessary because of our use of 3005 * a self-linked list to avoid rx overruns. 3006 */ 3007 status = ath_hal_rxprocdesc(ah, ds, 3008 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3009 #ifdef AR_DEBUG 3010 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3011 ath_printrxbuf(bf, status == HAL_OK); 3012 #endif 3013 if (status == HAL_EINPROGRESS) 3014 break; 3015 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3016 if (ds->ds_rxstat.rs_more) { 3017 /* 3018 * Frame spans multiple descriptors; this 3019 * cannot happen yet as we don't support 3020 * jumbograms. If not in monitor mode, 3021 * discard the frame. 3022 */ 3023 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3024 sc->sc_stats.ast_rx_toobig++; 3025 goto rx_next; 3026 } 3027 /* fall thru for monitor mode handling... */ 3028 } else if (ds->ds_rxstat.rs_status != 0) { 3029 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3030 sc->sc_stats.ast_rx_crcerr++; 3031 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3032 sc->sc_stats.ast_rx_fifoerr++; 3033 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3034 sc->sc_stats.ast_rx_phyerr++; 3035 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3036 sc->sc_stats.ast_rx_phy[phyerr]++; 3037 goto rx_next; 3038 } 3039 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3040 /* 3041 * Decrypt error. If the error occurred 3042 * because there was no hardware key, then 3043 * let the frame through so the upper layers 3044 * can process it. This is necessary for 5210 3045 * parts which have no way to setup a ``clear'' 3046 * key cache entry. 3047 * 3048 * XXX do key cache faulting 3049 */ 3050 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3051 goto rx_accept; 3052 sc->sc_stats.ast_rx_badcrypt++; 3053 } 3054 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3055 sc->sc_stats.ast_rx_badmic++; 3056 /* 3057 * Do minimal work required to hand off 3058 * the 802.11 header for notifcation. 3059 */ 3060 /* XXX frag's and qos frames */ 3061 len = ds->ds_rxstat.rs_datalen; 3062 if (len >= sizeof (struct ieee80211_frame)) { 3063 bus_dmamap_sync(sc->sc_dmat, 3064 bf->bf_dmamap, 3065 0, bf->bf_dmamap->dm_mapsize, 3066 BUS_DMASYNC_POSTREAD); 3067 ieee80211_notify_michael_failure(ic, 3068 mtod(m, struct ieee80211_frame *), 3069 sc->sc_splitmic ? 3070 ds->ds_rxstat.rs_keyix-32 : 3071 ds->ds_rxstat.rs_keyix 3072 ); 3073 } 3074 } 3075 ifp->if_ierrors++; 3076 /* 3077 * Reject error frames, we normally don't want 3078 * to see them in monitor mode (in monitor mode 3079 * allow through packets that have crypto problems). 3080 */ 3081 if ((ds->ds_rxstat.rs_status &~ 3082 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 3083 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 3084 goto rx_next; 3085 } 3086 rx_accept: 3087 /* 3088 * Sync and unmap the frame. At this point we're 3089 * committed to passing the mbuf somewhere so clear 3090 * bf_m; this means a new sk_buff must be allocated 3091 * when the rx descriptor is setup again to receive 3092 * another frame. 3093 */ 3094 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3095 0, bf->bf_dmamap->dm_mapsize, 3096 BUS_DMASYNC_POSTREAD); 3097 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3098 bf->bf_m = NULL; 3099 3100 m->m_pkthdr.rcvif = ifp; 3101 len = ds->ds_rxstat.rs_datalen; 3102 m->m_pkthdr.len = m->m_len = len; 3103 3104 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3105 3106 #if NBPFILTER > 0 3107 if (sc->sc_drvbpf) { 3108 u_int8_t rix; 3109 3110 /* 3111 * Discard anything shorter than an ack or cts. 3112 */ 3113 if (len < IEEE80211_ACK_LEN) { 3114 DPRINTF(sc, ATH_DEBUG_RECV, 3115 "%s: runt packet %d\n", 3116 __func__, len); 3117 sc->sc_stats.ast_rx_tooshort++; 3118 m_freem(m); 3119 goto rx_next; 3120 } 3121 rix = ds->ds_rxstat.rs_rate; 3122 sc->sc_rx_th.wr_tsf = htole64( 3123 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3124 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3125 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3126 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3127 sc->sc_rx_th.wr_antnoise = nf; 3128 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3129 3130 bpf_mtap2(sc->sc_drvbpf, 3131 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3132 } 3133 #endif 3134 3135 /* 3136 * From this point on we assume the frame is at least 3137 * as large as ieee80211_frame_min; verify that. 3138 */ 3139 if (len < IEEE80211_MIN_LEN) { 3140 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3141 __func__, len); 3142 sc->sc_stats.ast_rx_tooshort++; 3143 m_freem(m); 3144 goto rx_next; 3145 } 3146 3147 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3148 ieee80211_dump_pkt(mtod(m, caddr_t), len, 3149 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3150 ds->ds_rxstat.rs_rssi); 3151 } 3152 3153 m_adj(m, -IEEE80211_CRC_LEN); 3154 3155 /* 3156 * Locate the node for sender, track state, and then 3157 * pass the (referenced) node up to the 802.11 layer 3158 * for its use. 3159 */ 3160 ni = ieee80211_find_rxnode_withkey(ic, 3161 mtod(m, const struct ieee80211_frame_min *), 3162 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3163 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3164 /* 3165 * Track rx rssi and do any rx antenna management. 3166 */ 3167 an = ATH_NODE(ni); 3168 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3169 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3170 /* 3171 * Send frame up for processing. 3172 */ 3173 type = ieee80211_input(ic, m, ni, 3174 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3175 ieee80211_free_node(ni); 3176 if (sc->sc_diversity) { 3177 /* 3178 * When using fast diversity, change the default rx 3179 * antenna if diversity chooses the other antenna 3 3180 * times in a row. 3181 */ 3182 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3183 if (++sc->sc_rxotherant >= 3) 3184 ath_setdefantenna(sc, 3185 ds->ds_rxstat.rs_antenna); 3186 } else 3187 sc->sc_rxotherant = 0; 3188 } 3189 if (sc->sc_softled) { 3190 /* 3191 * Blink for any data frame. Otherwise do a 3192 * heartbeat-style blink when idle. The latter 3193 * is mainly for station mode where we depend on 3194 * periodic beacon frames to trigger the poll event. 3195 */ 3196 if (type == IEEE80211_FC0_TYPE_DATA) { 3197 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3198 ath_led_event(sc, ATH_LED_RX); 3199 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3200 ath_led_event(sc, ATH_LED_POLL); 3201 } 3202 /* 3203 * Arrange to update the last rx timestamp only for 3204 * frames from our ap when operating in station mode. 3205 * This assumes the rx key is always setup when associated. 3206 */ 3207 if (ic->ic_opmode == IEEE80211_M_STA && 3208 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3209 ngood++; 3210 rx_next: 3211 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3212 } while (ath_rxbuf_init(sc, bf) == 0); 3213 3214 /* rx signal state monitoring */ 3215 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3216 if (ath_hal_radar_event(ah)) 3217 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3218 if (ngood) 3219 sc->sc_lastrx = tsf; 3220 3221 #ifdef __NetBSD__ 3222 /* XXX Why isn't this necessary in FreeBSD? */ 3223 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3224 ath_start(ifp); 3225 #endif /* __NetBSD__ */ 3226 3227 NET_UNLOCK_GIANT(); /* XXX */ 3228 #undef PA2DESC 3229 } 3230 3231 /* 3232 * Setup a h/w transmit queue. 3233 */ 3234 static struct ath_txq * 3235 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3236 { 3237 #define N(a) (sizeof(a)/sizeof(a[0])) 3238 struct ath_hal *ah = sc->sc_ah; 3239 HAL_TXQ_INFO qi; 3240 int qnum; 3241 3242 memset(&qi, 0, sizeof(qi)); 3243 qi.tqi_subtype = subtype; 3244 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3245 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3246 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3247 /* 3248 * Enable interrupts only for EOL and DESC conditions. 3249 * We mark tx descriptors to receive a DESC interrupt 3250 * when a tx queue gets deep; otherwise waiting for the 3251 * EOL to reap descriptors. Note that this is done to 3252 * reduce interrupt load and this only defers reaping 3253 * descriptors, never transmitting frames. Aside from 3254 * reducing interrupts this also permits more concurrency. 3255 * The only potential downside is if the tx queue backs 3256 * up in which case the top half of the kernel may backup 3257 * due to a lack of tx descriptors. 3258 */ 3259 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3260 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3261 if (qnum == -1) { 3262 /* 3263 * NB: don't print a message, this happens 3264 * normally on parts with too few tx queues 3265 */ 3266 return NULL; 3267 } 3268 if (qnum >= N(sc->sc_txq)) { 3269 device_printf(sc->sc_dev, 3270 "hal qnum %u out of range, max %zu!\n", 3271 qnum, N(sc->sc_txq)); 3272 ath_hal_releasetxqueue(ah, qnum); 3273 return NULL; 3274 } 3275 if (!ATH_TXQ_SETUP(sc, qnum)) { 3276 struct ath_txq *txq = &sc->sc_txq[qnum]; 3277 3278 txq->axq_qnum = qnum; 3279 txq->axq_depth = 0; 3280 txq->axq_intrcnt = 0; 3281 txq->axq_link = NULL; 3282 STAILQ_INIT(&txq->axq_q); 3283 ATH_TXQ_LOCK_INIT(sc, txq); 3284 sc->sc_txqsetup |= 1<<qnum; 3285 } 3286 return &sc->sc_txq[qnum]; 3287 #undef N 3288 } 3289 3290 /* 3291 * Setup a hardware data transmit queue for the specified 3292 * access control. The hal may not support all requested 3293 * queues in which case it will return a reference to a 3294 * previously setup queue. We record the mapping from ac's 3295 * to h/w queues for use by ath_tx_start and also track 3296 * the set of h/w queues being used to optimize work in the 3297 * transmit interrupt handler and related routines. 3298 */ 3299 static int 3300 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3301 { 3302 #define N(a) (sizeof(a)/sizeof(a[0])) 3303 struct ath_txq *txq; 3304 3305 if (ac >= N(sc->sc_ac2q)) { 3306 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3307 ac, N(sc->sc_ac2q)); 3308 return 0; 3309 } 3310 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3311 if (txq != NULL) { 3312 sc->sc_ac2q[ac] = txq; 3313 return 1; 3314 } else 3315 return 0; 3316 #undef N 3317 } 3318 3319 /* 3320 * Update WME parameters for a transmit queue. 3321 */ 3322 static int 3323 ath_txq_update(struct ath_softc *sc, int ac) 3324 { 3325 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3326 #define ATH_TXOP_TO_US(v) (v<<5) 3327 struct ieee80211com *ic = &sc->sc_ic; 3328 struct ath_txq *txq = sc->sc_ac2q[ac]; 3329 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3330 struct ath_hal *ah = sc->sc_ah; 3331 HAL_TXQ_INFO qi; 3332 3333 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3334 qi.tqi_aifs = wmep->wmep_aifsn; 3335 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3336 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3337 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3338 3339 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3340 device_printf(sc->sc_dev, "unable to update hardware queue " 3341 "parameters for %s traffic!\n", 3342 ieee80211_wme_acnames[ac]); 3343 return 0; 3344 } else { 3345 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3346 return 1; 3347 } 3348 #undef ATH_TXOP_TO_US 3349 #undef ATH_EXPONENT_TO_VALUE 3350 } 3351 3352 /* 3353 * Callback from the 802.11 layer to update WME parameters. 3354 */ 3355 static int 3356 ath_wme_update(struct ieee80211com *ic) 3357 { 3358 struct ath_softc *sc = ic->ic_ifp->if_softc; 3359 3360 return !ath_txq_update(sc, WME_AC_BE) || 3361 !ath_txq_update(sc, WME_AC_BK) || 3362 !ath_txq_update(sc, WME_AC_VI) || 3363 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3364 } 3365 3366 /* 3367 * Reclaim resources for a setup queue. 3368 */ 3369 static void 3370 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3371 { 3372 3373 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3374 ATH_TXQ_LOCK_DESTROY(txq); 3375 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3376 } 3377 3378 /* 3379 * Reclaim all tx queue resources. 3380 */ 3381 static void 3382 ath_tx_cleanup(struct ath_softc *sc) 3383 { 3384 int i; 3385 3386 ATH_TXBUF_LOCK_DESTROY(sc); 3387 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3388 if (ATH_TXQ_SETUP(sc, i)) 3389 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3390 } 3391 3392 /* 3393 * Defragment an mbuf chain, returning at most maxfrags separate 3394 * mbufs+clusters. If this is not possible NULL is returned and 3395 * the original mbuf chain is left in it's present (potentially 3396 * modified) state. We use two techniques: collapsing consecutive 3397 * mbufs and replacing consecutive mbufs by a cluster. 3398 */ 3399 static struct mbuf * 3400 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3401 { 3402 struct mbuf *m, *n, *n2, **prev; 3403 u_int curfrags; 3404 3405 /* 3406 * Calculate the current number of frags. 3407 */ 3408 curfrags = 0; 3409 for (m = m0; m != NULL; m = m->m_next) 3410 curfrags++; 3411 /* 3412 * First, try to collapse mbufs. Note that we always collapse 3413 * towards the front so we don't need to deal with moving the 3414 * pkthdr. This may be suboptimal if the first mbuf has much 3415 * less data than the following. 3416 */ 3417 m = m0; 3418 again: 3419 for (;;) { 3420 n = m->m_next; 3421 if (n == NULL) 3422 break; 3423 if ((m->m_flags & M_RDONLY) == 0 && 3424 n->m_len < M_TRAILINGSPACE(m)) { 3425 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3426 n->m_len); 3427 m->m_len += n->m_len; 3428 m->m_next = n->m_next; 3429 m_free(n); 3430 if (--curfrags <= maxfrags) 3431 return m0; 3432 } else 3433 m = n; 3434 } 3435 KASSERT(maxfrags > 1, 3436 ("maxfrags %u, but normal collapse failed", maxfrags)); 3437 /* 3438 * Collapse consecutive mbufs to a cluster. 3439 */ 3440 prev = &m0->m_next; /* NB: not the first mbuf */ 3441 while ((n = *prev) != NULL) { 3442 if ((n2 = n->m_next) != NULL && 3443 n->m_len + n2->m_len < MCLBYTES) { 3444 m = m_getcl(how, MT_DATA, 0); 3445 if (m == NULL) 3446 goto bad; 3447 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3448 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3449 n2->m_len); 3450 m->m_len = n->m_len + n2->m_len; 3451 m->m_next = n2->m_next; 3452 *prev = m; 3453 m_free(n); 3454 m_free(n2); 3455 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3456 return m0; 3457 /* 3458 * Still not there, try the normal collapse 3459 * again before we allocate another cluster. 3460 */ 3461 goto again; 3462 } 3463 prev = &n->m_next; 3464 } 3465 /* 3466 * No place where we can collapse to a cluster; punt. 3467 * This can occur if, for example, you request 2 frags 3468 * but the packet requires that both be clusters (we 3469 * never reallocate the first mbuf to avoid moving the 3470 * packet header). 3471 */ 3472 bad: 3473 return NULL; 3474 } 3475 3476 /* 3477 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3478 */ 3479 static int 3480 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3481 { 3482 int i; 3483 3484 for (i = 0; i < rt->rateCount; i++) 3485 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3486 return i; 3487 return 0; /* NB: lowest rate */ 3488 } 3489 3490 static void 3491 ath_freetx(struct mbuf *m) 3492 { 3493 struct mbuf *next; 3494 3495 do { 3496 next = m->m_nextpkt; 3497 m->m_nextpkt = NULL; 3498 m_freem(m); 3499 } while ((m = next) != NULL); 3500 } 3501 3502 static int 3503 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3504 struct mbuf *m0) 3505 { 3506 struct ieee80211com *ic = &sc->sc_ic; 3507 struct ath_hal *ah = sc->sc_ah; 3508 struct ifnet *ifp = &sc->sc_if; 3509 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3510 int i, error, iswep, ismcast, isfrag, ismrr; 3511 int keyix, hdrlen, pktlen, try0; 3512 u_int8_t rix, txrate, ctsrate; 3513 u_int8_t cix = 0xff; /* NB: silence compiler */ 3514 struct ath_desc *ds, *ds0; 3515 struct ath_txq *txq; 3516 struct ieee80211_frame *wh; 3517 u_int subtype, flags, ctsduration; 3518 HAL_PKT_TYPE atype; 3519 const HAL_RATE_TABLE *rt; 3520 HAL_BOOL shortPreamble; 3521 struct ath_node *an; 3522 struct mbuf *m; 3523 u_int pri; 3524 3525 wh = mtod(m0, struct ieee80211_frame *); 3526 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3527 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3528 isfrag = m0->m_flags & M_FRAG; 3529 hdrlen = ieee80211_anyhdrsize(wh); 3530 /* 3531 * Packet length must not include any 3532 * pad bytes; deduct them here. 3533 */ 3534 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3535 3536 if (iswep) { 3537 const struct ieee80211_cipher *cip; 3538 struct ieee80211_key *k; 3539 3540 /* 3541 * Construct the 802.11 header+trailer for an encrypted 3542 * frame. The only reason this can fail is because of an 3543 * unknown or unsupported cipher/key type. 3544 */ 3545 k = ieee80211_crypto_encap(ic, ni, m0); 3546 if (k == NULL) { 3547 /* 3548 * This can happen when the key is yanked after the 3549 * frame was queued. Just discard the frame; the 3550 * 802.11 layer counts failures and provides 3551 * debugging/diagnostics. 3552 */ 3553 ath_freetx(m0); 3554 return EIO; 3555 } 3556 /* 3557 * Adjust the packet + header lengths for the crypto 3558 * additions and calculate the h/w key index. When 3559 * a s/w mic is done the frame will have had any mic 3560 * added to it prior to entry so m0->m_pkthdr.len above will 3561 * account for it. Otherwise we need to add it to the 3562 * packet length. 3563 */ 3564 cip = k->wk_cipher; 3565 hdrlen += cip->ic_header; 3566 pktlen += cip->ic_header + cip->ic_trailer; 3567 /* NB: frags always have any TKIP MIC done in s/w */ 3568 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3569 pktlen += cip->ic_miclen; 3570 keyix = k->wk_keyix; 3571 3572 /* packet header may have moved, reset our local pointer */ 3573 wh = mtod(m0, struct ieee80211_frame *); 3574 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3575 /* 3576 * Use station key cache slot, if assigned. 3577 */ 3578 keyix = ni->ni_ucastkey.wk_keyix; 3579 if (keyix == IEEE80211_KEYIX_NONE) 3580 keyix = HAL_TXKEYIX_INVALID; 3581 } else 3582 keyix = HAL_TXKEYIX_INVALID; 3583 3584 pktlen += IEEE80211_CRC_LEN; 3585 3586 /* 3587 * Load the DMA map so any coalescing is done. This 3588 * also calculates the number of descriptors we need. 3589 */ 3590 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3591 BUS_DMA_NOWAIT); 3592 if (error == EFBIG) { 3593 /* XXX packet requires too many descriptors */ 3594 bf->bf_nseg = ATH_TXDESC+1; 3595 } else if (error != 0) { 3596 sc->sc_stats.ast_tx_busdma++; 3597 ath_freetx(m0); 3598 return error; 3599 } 3600 /* 3601 * Discard null packets and check for packets that 3602 * require too many TX descriptors. We try to convert 3603 * the latter to a cluster. 3604 */ 3605 if (error == EFBIG) { /* too many desc's, linearize */ 3606 sc->sc_stats.ast_tx_linear++; 3607 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3608 if (m == NULL) { 3609 ath_freetx(m0); 3610 sc->sc_stats.ast_tx_nombuf++; 3611 return ENOMEM; 3612 } 3613 m0 = m; 3614 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3615 BUS_DMA_NOWAIT); 3616 if (error != 0) { 3617 sc->sc_stats.ast_tx_busdma++; 3618 ath_freetx(m0); 3619 return error; 3620 } 3621 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3622 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3623 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3624 sc->sc_stats.ast_tx_nodata++; 3625 ath_freetx(m0); 3626 return EIO; 3627 } 3628 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3629 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3630 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3631 bf->bf_m = m0; 3632 bf->bf_node = ni; /* NB: held reference */ 3633 3634 /* setup descriptors */ 3635 ds = bf->bf_desc; 3636 rt = sc->sc_currates; 3637 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3638 3639 /* 3640 * NB: the 802.11 layer marks whether or not we should 3641 * use short preamble based on the current mode and 3642 * negotiated parameters. 3643 */ 3644 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3645 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3646 shortPreamble = AH_TRUE; 3647 sc->sc_stats.ast_tx_shortpre++; 3648 } else { 3649 shortPreamble = AH_FALSE; 3650 } 3651 3652 an = ATH_NODE(ni); 3653 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3654 ismrr = 0; /* default no multi-rate retry*/ 3655 /* 3656 * Calculate Atheros packet type from IEEE80211 packet header, 3657 * setup for rate calculations, and select h/w transmit queue. 3658 */ 3659 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3660 case IEEE80211_FC0_TYPE_MGT: 3661 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3662 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3663 atype = HAL_PKT_TYPE_BEACON; 3664 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3665 atype = HAL_PKT_TYPE_PROBE_RESP; 3666 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3667 atype = HAL_PKT_TYPE_ATIM; 3668 else 3669 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3670 rix = sc->sc_minrateix; 3671 txrate = rt->info[rix].rateCode; 3672 if (shortPreamble) 3673 txrate |= rt->info[rix].shortPreamble; 3674 try0 = ATH_TXMGTTRY; 3675 /* NB: force all management frames to highest queue */ 3676 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3677 /* NB: force all management frames to highest queue */ 3678 pri = WME_AC_VO; 3679 } else 3680 pri = WME_AC_BE; 3681 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3682 break; 3683 case IEEE80211_FC0_TYPE_CTL: 3684 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3685 rix = sc->sc_minrateix; 3686 txrate = rt->info[rix].rateCode; 3687 if (shortPreamble) 3688 txrate |= rt->info[rix].shortPreamble; 3689 try0 = ATH_TXMGTTRY; 3690 /* NB: force all ctl frames to highest queue */ 3691 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3692 /* NB: force all ctl frames to highest queue */ 3693 pri = WME_AC_VO; 3694 } else 3695 pri = WME_AC_BE; 3696 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3697 break; 3698 case IEEE80211_FC0_TYPE_DATA: 3699 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3700 /* 3701 * Data frames: multicast frames go out at a fixed rate, 3702 * otherwise consult the rate control module for the 3703 * rate to use. 3704 */ 3705 if (ismcast) { 3706 /* 3707 * Check mcast rate setting in case it's changed. 3708 * XXX move out of fastpath 3709 */ 3710 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3711 sc->sc_mcastrix = 3712 ath_tx_findrix(rt, ic->ic_mcast_rate); 3713 sc->sc_mcastrate = ic->ic_mcast_rate; 3714 } 3715 rix = sc->sc_mcastrix; 3716 txrate = rt->info[rix].rateCode; 3717 try0 = 1; 3718 } else { 3719 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3720 &rix, &try0, &txrate); 3721 sc->sc_txrate = txrate; /* for LED blinking */ 3722 if (try0 != ATH_TXMAXTRY) 3723 ismrr = 1; 3724 } 3725 pri = M_WME_GETAC(m0); 3726 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3727 flags |= HAL_TXDESC_NOACK; 3728 break; 3729 default: 3730 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3731 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3732 /* XXX statistic */ 3733 ath_freetx(m0); 3734 return EIO; 3735 } 3736 txq = sc->sc_ac2q[pri]; 3737 3738 /* 3739 * When servicing one or more stations in power-save mode 3740 * multicast frames must be buffered until after the beacon. 3741 * We use the CAB queue for that. 3742 */ 3743 if (ismcast && ic->ic_ps_sta) { 3744 txq = sc->sc_cabq; 3745 /* XXX? more bit in 802.11 frame header */ 3746 } 3747 3748 /* 3749 * Calculate miscellaneous flags. 3750 */ 3751 if (ismcast) { 3752 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3753 } else if (pktlen > ic->ic_rtsthreshold) { 3754 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3755 cix = rt->info[rix].controlRate; 3756 sc->sc_stats.ast_tx_rts++; 3757 } 3758 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3759 sc->sc_stats.ast_tx_noack++; 3760 3761 /* 3762 * If 802.11g protection is enabled, determine whether 3763 * to use RTS/CTS or just CTS. Note that this is only 3764 * done for OFDM unicast frames. 3765 */ 3766 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3767 rt->info[rix].phy == IEEE80211_T_OFDM && 3768 (flags & HAL_TXDESC_NOACK) == 0) { 3769 /* XXX fragments must use CCK rates w/ protection */ 3770 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3771 flags |= HAL_TXDESC_RTSENA; 3772 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3773 flags |= HAL_TXDESC_CTSENA; 3774 if (isfrag) { 3775 /* 3776 * For frags it would be desirable to use the 3777 * highest CCK rate for RTS/CTS. But stations 3778 * farther away may detect it at a lower CCK rate 3779 * so use the configured protection rate instead 3780 * (for now). 3781 */ 3782 cix = rt->info[sc->sc_protrix].controlRate; 3783 } else 3784 cix = rt->info[sc->sc_protrix].controlRate; 3785 sc->sc_stats.ast_tx_protect++; 3786 } 3787 3788 /* 3789 * Calculate duration. This logically belongs in the 802.11 3790 * layer but it lacks sufficient information to calculate it. 3791 */ 3792 if ((flags & HAL_TXDESC_NOACK) == 0 && 3793 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3794 u_int16_t dur; 3795 /* 3796 * XXX not right with fragmentation. 3797 */ 3798 if (shortPreamble) 3799 dur = rt->info[rix].spAckDuration; 3800 else 3801 dur = rt->info[rix].lpAckDuration; 3802 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3803 dur += dur; /* additional SIFS+ACK */ 3804 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3805 /* 3806 * Include the size of next fragment so NAV is 3807 * updated properly. The last fragment uses only 3808 * the ACK duration 3809 */ 3810 dur += ath_hal_computetxtime(ah, rt, 3811 m0->m_nextpkt->m_pkthdr.len, 3812 rix, shortPreamble); 3813 } 3814 if (isfrag) { 3815 /* 3816 * Force hardware to use computed duration for next 3817 * fragment by disabling multi-rate retry which updates 3818 * duration based on the multi-rate duration table. 3819 */ 3820 try0 = ATH_TXMAXTRY; 3821 } 3822 *(u_int16_t *)wh->i_dur = htole16(dur); 3823 } 3824 3825 /* 3826 * Calculate RTS/CTS rate and duration if needed. 3827 */ 3828 ctsduration = 0; 3829 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3830 /* 3831 * CTS transmit rate is derived from the transmit rate 3832 * by looking in the h/w rate table. We must also factor 3833 * in whether or not a short preamble is to be used. 3834 */ 3835 /* NB: cix is set above where RTS/CTS is enabled */ 3836 KASSERT(cix != 0xff, ("cix not setup")); 3837 ctsrate = rt->info[cix].rateCode; 3838 /* 3839 * Compute the transmit duration based on the frame 3840 * size and the size of an ACK frame. We call into the 3841 * HAL to do the computation since it depends on the 3842 * characteristics of the actual PHY being used. 3843 * 3844 * NB: CTS is assumed the same size as an ACK so we can 3845 * use the precalculated ACK durations. 3846 */ 3847 if (shortPreamble) { 3848 ctsrate |= rt->info[cix].shortPreamble; 3849 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3850 ctsduration += rt->info[cix].spAckDuration; 3851 ctsduration += ath_hal_computetxtime(ah, 3852 rt, pktlen, rix, AH_TRUE); 3853 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3854 ctsduration += rt->info[rix].spAckDuration; 3855 } else { 3856 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3857 ctsduration += rt->info[cix].lpAckDuration; 3858 ctsduration += ath_hal_computetxtime(ah, 3859 rt, pktlen, rix, AH_FALSE); 3860 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3861 ctsduration += rt->info[rix].lpAckDuration; 3862 } 3863 /* 3864 * Must disable multi-rate retry when using RTS/CTS. 3865 */ 3866 ismrr = 0; 3867 try0 = ATH_TXMGTTRY; /* XXX */ 3868 } else 3869 ctsrate = 0; 3870 3871 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3872 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3873 sc->sc_hwmap[txrate].ieeerate, -1); 3874 #if NBPFILTER > 0 3875 if (ic->ic_rawbpf) 3876 bpf_mtap(ic->ic_rawbpf, m0); 3877 if (sc->sc_drvbpf) { 3878 u_int64_t tsf = ath_hal_gettsf64(ah); 3879 3880 sc->sc_tx_th.wt_tsf = htole64(tsf); 3881 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3882 if (iswep) 3883 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3884 if (isfrag) 3885 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3886 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3887 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3888 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3889 3890 bpf_mtap2(sc->sc_drvbpf, 3891 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3892 } 3893 #endif 3894 3895 /* 3896 * Determine if a tx interrupt should be generated for 3897 * this descriptor. We take a tx interrupt to reap 3898 * descriptors when the h/w hits an EOL condition or 3899 * when the descriptor is specifically marked to generate 3900 * an interrupt. We periodically mark descriptors in this 3901 * way to insure timely replenishing of the supply needed 3902 * for sending frames. Defering interrupts reduces system 3903 * load and potentially allows more concurrent work to be 3904 * done but if done to aggressively can cause senders to 3905 * backup. 3906 * 3907 * NB: use >= to deal with sc_txintrperiod changing 3908 * dynamically through sysctl. 3909 */ 3910 if (flags & HAL_TXDESC_INTREQ) { 3911 txq->axq_intrcnt = 0; 3912 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3913 flags |= HAL_TXDESC_INTREQ; 3914 txq->axq_intrcnt = 0; 3915 } 3916 3917 /* 3918 * Formulate first tx descriptor with tx controls. 3919 */ 3920 /* XXX check return value? */ 3921 ath_hal_setuptxdesc(ah, ds 3922 , pktlen /* packet length */ 3923 , hdrlen /* header length */ 3924 , atype /* Atheros packet type */ 3925 , ni->ni_txpower /* txpower */ 3926 , txrate, try0 /* series 0 rate/tries */ 3927 , keyix /* key cache index */ 3928 , sc->sc_txantenna /* antenna mode */ 3929 , flags /* flags */ 3930 , ctsrate /* rts/cts rate */ 3931 , ctsduration /* rts/cts duration */ 3932 ); 3933 bf->bf_flags = flags; 3934 /* 3935 * Setup the multi-rate retry state only when we're 3936 * going to use it. This assumes ath_hal_setuptxdesc 3937 * initializes the descriptors (so we don't have to) 3938 * when the hardware supports multi-rate retry and 3939 * we don't use it. 3940 */ 3941 if (ismrr) 3942 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3943 3944 /* 3945 * Fillin the remainder of the descriptor info. 3946 */ 3947 ds0 = ds; 3948 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3949 ds->ds_data = bf->bf_segs[i].ds_addr; 3950 if (i == bf->bf_nseg - 1) 3951 ds->ds_link = 0; 3952 else 3953 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3954 ath_hal_filltxdesc(ah, ds 3955 , bf->bf_segs[i].ds_len /* segment length */ 3956 , i == 0 /* first segment */ 3957 , i == bf->bf_nseg - 1 /* last segment */ 3958 , ds0 /* first descriptor */ 3959 ); 3960 3961 /* NB: The desc swap function becomes void, 3962 * if descriptor swapping is not enabled 3963 */ 3964 ath_desc_swap(ds); 3965 3966 DPRINTF(sc, ATH_DEBUG_XMIT, 3967 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3968 __func__, i, ds->ds_link, ds->ds_data, 3969 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3970 } 3971 /* 3972 * Insert the frame on the outbound list and 3973 * pass it on to the hardware. 3974 */ 3975 ATH_TXQ_LOCK(txq); 3976 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3977 if (txq->axq_link == NULL) { 3978 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3979 DPRINTF(sc, ATH_DEBUG_XMIT, 3980 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3981 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3982 txq->axq_depth); 3983 } else { 3984 *txq->axq_link = HTOAH32(bf->bf_daddr); 3985 DPRINTF(sc, ATH_DEBUG_XMIT, 3986 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3987 __func__, txq->axq_qnum, txq->axq_link, 3988 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3989 } 3990 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3991 /* 3992 * The CAB queue is started from the SWBA handler since 3993 * frames only go out on DTIM and to avoid possible races. 3994 */ 3995 if (txq != sc->sc_cabq) 3996 ath_hal_txstart(ah, txq->axq_qnum); 3997 ATH_TXQ_UNLOCK(txq); 3998 3999 return 0; 4000 } 4001 4002 /* 4003 * Process completed xmit descriptors from the specified queue. 4004 */ 4005 static int 4006 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4007 { 4008 struct ath_hal *ah = sc->sc_ah; 4009 struct ieee80211com *ic = &sc->sc_ic; 4010 struct ath_buf *bf; 4011 struct ath_desc *ds, *ds0; 4012 struct ieee80211_node *ni; 4013 struct ath_node *an; 4014 int sr, lr, pri, nacked; 4015 HAL_STATUS status; 4016 4017 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4018 __func__, txq->axq_qnum, 4019 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4020 txq->axq_link); 4021 nacked = 0; 4022 for (;;) { 4023 ATH_TXQ_LOCK(txq); 4024 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4025 bf = STAILQ_FIRST(&txq->axq_q); 4026 if (bf == NULL) { 4027 txq->axq_link = NULL; 4028 ATH_TXQ_UNLOCK(txq); 4029 break; 4030 } 4031 ds0 = &bf->bf_desc[0]; 4032 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4033 status = ath_hal_txprocdesc(ah, ds); 4034 #ifdef AR_DEBUG 4035 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4036 ath_printtxbuf(bf, status == HAL_OK); 4037 #endif 4038 if (status == HAL_EINPROGRESS) { 4039 ATH_TXQ_UNLOCK(txq); 4040 break; 4041 } 4042 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4043 ATH_TXQ_UNLOCK(txq); 4044 4045 ni = bf->bf_node; 4046 if (ni != NULL) { 4047 an = ATH_NODE(ni); 4048 if (ds->ds_txstat.ts_status == 0) { 4049 u_int8_t txant = ds->ds_txstat.ts_antenna; 4050 sc->sc_stats.ast_ant_tx[txant]++; 4051 sc->sc_ant_tx[txant]++; 4052 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4053 sc->sc_stats.ast_tx_altrate++; 4054 sc->sc_stats.ast_tx_rssi = 4055 ds->ds_txstat.ts_rssi; 4056 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4057 ds->ds_txstat.ts_rssi); 4058 pri = M_WME_GETAC(bf->bf_m); 4059 if (pri >= WME_AC_VO) 4060 ic->ic_wme.wme_hipri_traffic++; 4061 ni->ni_inact = ni->ni_inact_reload; 4062 } else { 4063 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4064 sc->sc_stats.ast_tx_xretries++; 4065 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4066 sc->sc_stats.ast_tx_fifoerr++; 4067 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4068 sc->sc_stats.ast_tx_filtered++; 4069 } 4070 sr = ds->ds_txstat.ts_shortretry; 4071 lr = ds->ds_txstat.ts_longretry; 4072 sc->sc_stats.ast_tx_shortretry += sr; 4073 sc->sc_stats.ast_tx_longretry += lr; 4074 /* 4075 * Hand the descriptor to the rate control algorithm. 4076 */ 4077 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4078 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4079 /* 4080 * If frame was ack'd update the last rx time 4081 * used to workaround phantom bmiss interrupts. 4082 */ 4083 if (ds->ds_txstat.ts_status == 0) 4084 nacked++; 4085 ath_rate_tx_complete(sc, an, ds, ds0); 4086 } 4087 /* 4088 * Reclaim reference to node. 4089 * 4090 * NB: the node may be reclaimed here if, for example 4091 * this is a DEAUTH message that was sent and the 4092 * node was timed out due to inactivity. 4093 */ 4094 ieee80211_free_node(ni); 4095 } 4096 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4097 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4098 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4099 m_freem(bf->bf_m); 4100 bf->bf_m = NULL; 4101 bf->bf_node = NULL; 4102 4103 ATH_TXBUF_LOCK(sc); 4104 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4105 ATH_TXBUF_UNLOCK(sc); 4106 } 4107 return nacked; 4108 } 4109 4110 static inline int 4111 txqactive(struct ath_hal *ah, int qnum) 4112 { 4113 u_int32_t txqs = 1<<qnum; 4114 ath_hal_gettxintrtxqs(ah, &txqs); 4115 return (txqs & (1<<qnum)); 4116 } 4117 4118 /* 4119 * Deferred processing of transmit interrupt; special-cased 4120 * for a single hardware transmit queue (e.g. 5210 and 5211). 4121 */ 4122 static void 4123 ath_tx_proc_q0(void *arg, int npending) 4124 { 4125 struct ath_softc *sc = arg; 4126 struct ifnet *ifp = &sc->sc_if; 4127 4128 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 4129 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4130 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4131 ath_tx_processq(sc, sc->sc_cabq); 4132 ifp->if_flags &= ~IFF_OACTIVE; 4133 sc->sc_tx_timer = 0; 4134 4135 if (sc->sc_softled) 4136 ath_led_event(sc, ATH_LED_TX); 4137 4138 ath_start(ifp); 4139 } 4140 4141 /* 4142 * Deferred processing of transmit interrupt; special-cased 4143 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4144 */ 4145 static void 4146 ath_tx_proc_q0123(void *arg, int npending) 4147 { 4148 struct ath_softc *sc = arg; 4149 struct ifnet *ifp = &sc->sc_if; 4150 int nacked; 4151 4152 /* 4153 * Process each active queue. 4154 */ 4155 nacked = 0; 4156 if (txqactive(sc->sc_ah, 0)) 4157 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4158 if (txqactive(sc->sc_ah, 1)) 4159 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4160 if (txqactive(sc->sc_ah, 2)) 4161 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4162 if (txqactive(sc->sc_ah, 3)) 4163 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4164 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4165 ath_tx_processq(sc, sc->sc_cabq); 4166 if (nacked) 4167 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4168 ath_tx_processq(sc, sc->sc_cabq); 4169 4170 ifp->if_flags &= ~IFF_OACTIVE; 4171 sc->sc_tx_timer = 0; 4172 4173 if (sc->sc_softled) 4174 ath_led_event(sc, ATH_LED_TX); 4175 4176 ath_start(ifp); 4177 } 4178 4179 /* 4180 * Deferred processing of transmit interrupt. 4181 */ 4182 static void 4183 ath_tx_proc(void *arg, int npending) 4184 { 4185 struct ath_softc *sc = arg; 4186 struct ifnet *ifp = &sc->sc_if; 4187 int i, nacked; 4188 4189 /* 4190 * Process each active queue. 4191 */ 4192 nacked = 0; 4193 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4194 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4195 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4196 if (nacked) 4197 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4198 4199 ifp->if_flags &= ~IFF_OACTIVE; 4200 sc->sc_tx_timer = 0; 4201 4202 if (sc->sc_softled) 4203 ath_led_event(sc, ATH_LED_TX); 4204 4205 ath_start(ifp); 4206 } 4207 4208 static void 4209 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4210 { 4211 struct ath_hal *ah = sc->sc_ah; 4212 struct ieee80211_node *ni; 4213 struct ath_buf *bf; 4214 4215 /* 4216 * NB: this assumes output has been stopped and 4217 * we do not need to block ath_tx_tasklet 4218 */ 4219 for (;;) { 4220 ATH_TXQ_LOCK(txq); 4221 bf = STAILQ_FIRST(&txq->axq_q); 4222 if (bf == NULL) { 4223 txq->axq_link = NULL; 4224 ATH_TXQ_UNLOCK(txq); 4225 break; 4226 } 4227 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4228 ATH_TXQ_UNLOCK(txq); 4229 #ifdef AR_DEBUG 4230 if (sc->sc_debug & ATH_DEBUG_RESET) 4231 ath_printtxbuf(bf, 4232 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4233 #endif /* AR_DEBUG */ 4234 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4235 m_freem(bf->bf_m); 4236 bf->bf_m = NULL; 4237 ni = bf->bf_node; 4238 bf->bf_node = NULL; 4239 if (ni != NULL) { 4240 /* 4241 * Reclaim node reference. 4242 */ 4243 ieee80211_free_node(ni); 4244 } 4245 ATH_TXBUF_LOCK(sc); 4246 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4247 ATH_TXBUF_UNLOCK(sc); 4248 } 4249 } 4250 4251 static void 4252 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4253 { 4254 struct ath_hal *ah = sc->sc_ah; 4255 4256 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4257 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4258 __func__, txq->axq_qnum, 4259 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4260 txq->axq_link); 4261 } 4262 4263 /* 4264 * Drain the transmit queues and reclaim resources. 4265 */ 4266 static void 4267 ath_draintxq(struct ath_softc *sc) 4268 { 4269 struct ath_hal *ah = sc->sc_ah; 4270 struct ifnet *ifp = &sc->sc_if; 4271 int i; 4272 4273 /* XXX return value */ 4274 if (!sc->sc_invalid) { 4275 /* don't touch the hardware if marked invalid */ 4276 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4277 DPRINTF(sc, ATH_DEBUG_RESET, 4278 "%s: beacon queue %p\n", __func__, 4279 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4280 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4281 if (ATH_TXQ_SETUP(sc, i)) 4282 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4283 } 4284 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4285 if (ATH_TXQ_SETUP(sc, i)) 4286 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4287 ifp->if_flags &= ~IFF_OACTIVE; 4288 sc->sc_tx_timer = 0; 4289 } 4290 4291 /* 4292 * Disable the receive h/w in preparation for a reset. 4293 */ 4294 static void 4295 ath_stoprecv(struct ath_softc *sc) 4296 { 4297 #define PA2DESC(_sc, _pa) \ 4298 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4299 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4300 struct ath_hal *ah = sc->sc_ah; 4301 4302 ath_hal_stoppcurecv(ah); /* disable PCU */ 4303 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4304 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4305 DELAY(3000); /* 3ms is long enough for 1 frame */ 4306 #ifdef AR_DEBUG 4307 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4308 struct ath_buf *bf; 4309 4310 printf("%s: rx queue %p, link %p\n", __func__, 4311 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4312 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4313 struct ath_desc *ds = bf->bf_desc; 4314 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4315 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4316 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4317 ath_printrxbuf(bf, status == HAL_OK); 4318 } 4319 } 4320 #endif 4321 sc->sc_rxlink = NULL; /* just in case */ 4322 #undef PA2DESC 4323 } 4324 4325 /* 4326 * Enable the receive h/w following a reset. 4327 */ 4328 static int 4329 ath_startrecv(struct ath_softc *sc) 4330 { 4331 struct ath_hal *ah = sc->sc_ah; 4332 struct ath_buf *bf; 4333 4334 sc->sc_rxlink = NULL; 4335 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4336 int error = ath_rxbuf_init(sc, bf); 4337 if (error != 0) { 4338 DPRINTF(sc, ATH_DEBUG_RECV, 4339 "%s: ath_rxbuf_init failed %d\n", 4340 __func__, error); 4341 return error; 4342 } 4343 } 4344 4345 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4346 ath_hal_putrxbuf(ah, bf->bf_daddr); 4347 ath_hal_rxena(ah); /* enable recv descriptors */ 4348 ath_mode_init(sc); /* set filters, etc. */ 4349 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4350 return 0; 4351 } 4352 4353 /* 4354 * Update internal state after a channel change. 4355 */ 4356 static void 4357 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4358 { 4359 struct ieee80211com *ic = &sc->sc_ic; 4360 enum ieee80211_phymode mode; 4361 u_int16_t flags; 4362 4363 /* 4364 * Change channels and update the h/w rate map 4365 * if we're switching; e.g. 11a to 11b/g. 4366 */ 4367 mode = ieee80211_chan2mode(ic, chan); 4368 if (mode != sc->sc_curmode) 4369 ath_setcurmode(sc, mode); 4370 /* 4371 * Update BPF state. NB: ethereal et. al. don't handle 4372 * merged flags well so pick a unique mode for their use. 4373 */ 4374 if (IEEE80211_IS_CHAN_A(chan)) 4375 flags = IEEE80211_CHAN_A; 4376 /* XXX 11g schizophrenia */ 4377 else if (IEEE80211_IS_CHAN_G(chan) || 4378 IEEE80211_IS_CHAN_PUREG(chan)) 4379 flags = IEEE80211_CHAN_G; 4380 else 4381 flags = IEEE80211_CHAN_B; 4382 if (IEEE80211_IS_CHAN_T(chan)) 4383 flags |= IEEE80211_CHAN_TURBO; 4384 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4385 htole16(chan->ic_freq); 4386 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4387 htole16(flags); 4388 } 4389 4390 /* 4391 * Poll for a channel clear indication; this is required 4392 * for channels requiring DFS and not previously visited 4393 * and/or with a recent radar detection. 4394 */ 4395 static void 4396 ath_dfswait(void *arg) 4397 { 4398 struct ath_softc *sc = arg; 4399 struct ath_hal *ah = sc->sc_ah; 4400 HAL_CHANNEL hchan; 4401 4402 ath_hal_radar_wait(ah, &hchan); 4403 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4404 if_printf(&sc->sc_if, 4405 "channel %u/0x%x/0x%x has interference\n", 4406 hchan.channel, hchan.channelFlags, hchan.privFlags); 4407 return; 4408 } 4409 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4410 /* XXX should not happen */ 4411 return; 4412 } 4413 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4414 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4415 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4416 if_printf(&sc->sc_if, 4417 "channel %u/0x%x/0x%x marked clear\n", 4418 hchan.channel, hchan.channelFlags, hchan.privFlags); 4419 } else 4420 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4421 } 4422 4423 /* 4424 * Set/change channels. If the channel is really being changed, 4425 * it's done by reseting the chip. To accomplish this we must 4426 * first cleanup any pending DMA, then restart stuff after a la 4427 * ath_init. 4428 */ 4429 static int 4430 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4431 { 4432 struct ath_hal *ah = sc->sc_ah; 4433 struct ieee80211com *ic = &sc->sc_ic; 4434 HAL_CHANNEL hchan; 4435 4436 /* 4437 * Convert to a HAL channel description with 4438 * the flags constrained to reflect the current 4439 * operating mode. 4440 */ 4441 hchan.channel = chan->ic_freq; 4442 hchan.channelFlags = ath_chan2flags(ic, chan); 4443 4444 DPRINTF(sc, ATH_DEBUG_RESET, 4445 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4446 __func__, 4447 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4448 sc->sc_curchan.channelFlags), 4449 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4450 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4451 hchan.channel, hchan.channelFlags); 4452 if (hchan.channel != sc->sc_curchan.channel || 4453 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4454 HAL_STATUS status; 4455 4456 /* 4457 * To switch channels clear any pending DMA operations; 4458 * wait long enough for the RX fifo to drain, reset the 4459 * hardware at the new frequency, and then re-enable 4460 * the relevant bits of the h/w. 4461 */ 4462 ath_hal_intrset(ah, 0); /* disable interrupts */ 4463 ath_draintxq(sc); /* clear pending tx frames */ 4464 ath_stoprecv(sc); /* turn off frame recv */ 4465 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4466 if_printf(ic->ic_ifp, "%s: unable to reset " 4467 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4468 __func__, ieee80211_chan2ieee(ic, chan), 4469 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4470 return EIO; 4471 } 4472 sc->sc_curchan = hchan; 4473 ath_update_txpow(sc); /* update tx power state */ 4474 sc->sc_diversity = ath_hal_getdiversity(ah); 4475 sc->sc_calinterval = 1; 4476 sc->sc_caltries = 0; 4477 4478 /* 4479 * Re-enable rx framework. 4480 */ 4481 if (ath_startrecv(sc) != 0) { 4482 if_printf(&sc->sc_if, 4483 "%s: unable to restart recv logic\n", __func__); 4484 return EIO; 4485 } 4486 4487 /* 4488 * Change channels and update the h/w rate map 4489 * if we're switching; e.g. 11a to 11b/g. 4490 */ 4491 ic->ic_ibss_chan = chan; 4492 ath_chan_change(sc, chan); 4493 4494 /* 4495 * Handle DFS required waiting period to determine 4496 * if channel is clear of radar traffic. 4497 */ 4498 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4499 #define DFS_AND_NOT_CLEAR(_c) \ 4500 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4501 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4502 if_printf(&sc->sc_if, 4503 "wait for DFS clear channel signal\n"); 4504 /* XXX stop sndq */ 4505 sc->sc_if.if_flags |= IFF_OACTIVE; 4506 callout_reset(&sc->sc_dfs_ch, 4507 2 * hz, ath_dfswait, sc); 4508 } else 4509 callout_stop(&sc->sc_dfs_ch); 4510 #undef DFS_NOT_CLEAR 4511 } 4512 4513 /* 4514 * Re-enable interrupts. 4515 */ 4516 ath_hal_intrset(ah, sc->sc_imask); 4517 } 4518 return 0; 4519 } 4520 4521 static void 4522 ath_next_scan(void *arg) 4523 { 4524 struct ath_softc *sc = arg; 4525 struct ieee80211com *ic = &sc->sc_ic; 4526 int s; 4527 4528 /* don't call ath_start w/o network interrupts blocked */ 4529 s = splnet(); 4530 4531 if (ic->ic_state == IEEE80211_S_SCAN) 4532 ieee80211_next_scan(ic); 4533 splx(s); 4534 } 4535 4536 /* 4537 * Periodically recalibrate the PHY to account 4538 * for temperature/environment changes. 4539 */ 4540 static void 4541 ath_calibrate(void *arg) 4542 { 4543 struct ath_softc *sc = arg; 4544 struct ath_hal *ah = sc->sc_ah; 4545 HAL_BOOL iqCalDone; 4546 4547 sc->sc_stats.ast_per_cal++; 4548 4549 ATH_LOCK(sc); 4550 4551 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4552 /* 4553 * Rfgain is out of bounds, reset the chip 4554 * to load new gain values. 4555 */ 4556 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4557 "%s: rfgain change\n", __func__); 4558 sc->sc_stats.ast_per_rfgain++; 4559 ath_reset(&sc->sc_if); 4560 } 4561 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4562 DPRINTF(sc, ATH_DEBUG_ANY, 4563 "%s: calibration of channel %u failed\n", 4564 __func__, sc->sc_curchan.channel); 4565 sc->sc_stats.ast_per_calfail++; 4566 } 4567 /* 4568 * Calibrate noise floor data again in case of change. 4569 */ 4570 ath_hal_process_noisefloor(ah); 4571 /* 4572 * Poll more frequently when the IQ calibration is in 4573 * progress to speedup loading the final settings. 4574 * We temper this aggressive polling with an exponential 4575 * back off after 4 tries up to ath_calinterval. 4576 */ 4577 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4578 sc->sc_caltries = 0; 4579 sc->sc_calinterval = ath_calinterval; 4580 } else if (sc->sc_caltries > 4) { 4581 sc->sc_caltries = 0; 4582 sc->sc_calinterval <<= 1; 4583 if (sc->sc_calinterval > ath_calinterval) 4584 sc->sc_calinterval = ath_calinterval; 4585 } 4586 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4587 ("bad calibration interval %u", sc->sc_calinterval)); 4588 4589 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4590 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4591 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4592 sc->sc_caltries++; 4593 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4594 ath_calibrate, sc); 4595 ATH_UNLOCK(sc); 4596 } 4597 4598 static int 4599 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4600 { 4601 struct ifnet *ifp = ic->ic_ifp; 4602 struct ath_softc *sc = ifp->if_softc; 4603 struct ath_hal *ah = sc->sc_ah; 4604 struct ieee80211_node *ni; 4605 int i, error; 4606 const u_int8_t *bssid; 4607 u_int32_t rfilt; 4608 static const HAL_LED_STATE leds[] = { 4609 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4610 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4611 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4612 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4613 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4614 }; 4615 4616 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4617 ieee80211_state_name[ic->ic_state], 4618 ieee80211_state_name[nstate]); 4619 4620 callout_stop(&sc->sc_scan_ch); 4621 callout_stop(&sc->sc_cal_ch); 4622 callout_stop(&sc->sc_dfs_ch); 4623 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4624 4625 if (nstate == IEEE80211_S_INIT) { 4626 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4627 /* 4628 * NB: disable interrupts so we don't rx frames. 4629 */ 4630 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4631 /* 4632 * Notify the rate control algorithm. 4633 */ 4634 ath_rate_newstate(sc, nstate); 4635 goto done; 4636 } 4637 ni = ic->ic_bss; 4638 error = ath_chan_set(sc, ic->ic_curchan); 4639 if (error != 0) 4640 goto bad; 4641 rfilt = ath_calcrxfilter(sc, nstate); 4642 if (nstate == IEEE80211_S_SCAN) 4643 bssid = ifp->if_broadcastaddr; 4644 else 4645 bssid = ni->ni_bssid; 4646 ath_hal_setrxfilter(ah, rfilt); 4647 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4648 __func__, rfilt, ether_sprintf(bssid)); 4649 4650 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4651 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4652 else 4653 ath_hal_setassocid(ah, bssid, 0); 4654 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4655 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4656 if (ath_hal_keyisvalid(ah, i)) 4657 ath_hal_keysetmac(ah, i, bssid); 4658 } 4659 4660 /* 4661 * Notify the rate control algorithm so rates 4662 * are setup should ath_beacon_alloc be called. 4663 */ 4664 ath_rate_newstate(sc, nstate); 4665 4666 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4667 /* nothing to do */; 4668 } else if (nstate == IEEE80211_S_RUN) { 4669 DPRINTF(sc, ATH_DEBUG_STATE, 4670 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4671 "capinfo=0x%04x chan=%d\n" 4672 , __func__ 4673 , ic->ic_flags 4674 , ni->ni_intval 4675 , ether_sprintf(ni->ni_bssid) 4676 , ni->ni_capinfo 4677 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4678 4679 switch (ic->ic_opmode) { 4680 case IEEE80211_M_HOSTAP: 4681 case IEEE80211_M_IBSS: 4682 /* 4683 * Allocate and setup the beacon frame. 4684 * 4685 * Stop any previous beacon DMA. This may be 4686 * necessary, for example, when an ibss merge 4687 * causes reconfiguration; there will be a state 4688 * transition from RUN->RUN that means we may 4689 * be called with beacon transmission active. 4690 */ 4691 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4692 ath_beacon_free(sc); 4693 error = ath_beacon_alloc(sc, ni); 4694 if (error != 0) 4695 goto bad; 4696 /* 4697 * If joining an adhoc network defer beacon timer 4698 * configuration to the next beacon frame so we 4699 * have a current TSF to use. Otherwise we're 4700 * starting an ibss/bss so there's no need to delay. 4701 */ 4702 if (ic->ic_opmode == IEEE80211_M_IBSS && 4703 ic->ic_bss->ni_tstamp.tsf != 0) 4704 sc->sc_syncbeacon = 1; 4705 else 4706 ath_beacon_config(sc); 4707 break; 4708 case IEEE80211_M_STA: 4709 /* 4710 * Allocate a key cache slot to the station. 4711 */ 4712 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4713 sc->sc_hasclrkey && 4714 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4715 ath_setup_stationkey(ni); 4716 /* 4717 * Defer beacon timer configuration to the next 4718 * beacon frame so we have a current TSF to use 4719 * (any TSF collected when scanning is likely old). 4720 */ 4721 sc->sc_syncbeacon = 1; 4722 break; 4723 default: 4724 break; 4725 } 4726 /* 4727 * Let the hal process statistics collected during a 4728 * scan so it can provide calibrated noise floor data. 4729 */ 4730 ath_hal_process_noisefloor(ah); 4731 /* 4732 * Reset rssi stats; maybe not the best place... 4733 */ 4734 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4735 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4736 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4737 } else { 4738 ath_hal_intrset(ah, 4739 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4740 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4741 } 4742 done: 4743 /* 4744 * Invoke the parent method to complete the work. 4745 */ 4746 error = sc->sc_newstate(ic, nstate, arg); 4747 /* 4748 * Finally, start any timers. 4749 */ 4750 if (nstate == IEEE80211_S_RUN) { 4751 /* start periodic recalibration timer */ 4752 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4753 ath_calibrate, sc); 4754 } else if (nstate == IEEE80211_S_SCAN) { 4755 /* start ap/neighbor scan timer */ 4756 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4757 ath_next_scan, sc); 4758 } 4759 bad: 4760 return error; 4761 } 4762 4763 /* 4764 * Allocate a key cache slot to the station so we can 4765 * setup a mapping from key index to node. The key cache 4766 * slot is needed for managing antenna state and for 4767 * compression when stations do not use crypto. We do 4768 * it uniliaterally here; if crypto is employed this slot 4769 * will be reassigned. 4770 */ 4771 static void 4772 ath_setup_stationkey(struct ieee80211_node *ni) 4773 { 4774 struct ieee80211com *ic = ni->ni_ic; 4775 struct ath_softc *sc = ic->ic_ifp->if_softc; 4776 ieee80211_keyix keyix, rxkeyix; 4777 4778 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4779 /* 4780 * Key cache is full; we'll fall back to doing 4781 * the more expensive lookup in software. Note 4782 * this also means no h/w compression. 4783 */ 4784 /* XXX msg+statistic */ 4785 } else { 4786 /* XXX locking? */ 4787 ni->ni_ucastkey.wk_keyix = keyix; 4788 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4789 /* NB: this will create a pass-thru key entry */ 4790 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4791 } 4792 } 4793 4794 /* 4795 * Setup driver-specific state for a newly associated node. 4796 * Note that we're called also on a re-associate, the isnew 4797 * param tells us if this is the first time or not. 4798 */ 4799 static void 4800 ath_newassoc(struct ieee80211_node *ni, int isnew) 4801 { 4802 struct ieee80211com *ic = ni->ni_ic; 4803 struct ath_softc *sc = ic->ic_ifp->if_softc; 4804 4805 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4806 if (isnew && 4807 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4808 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4809 ("new assoc with a unicast key already setup (keyix %u)", 4810 ni->ni_ucastkey.wk_keyix)); 4811 ath_setup_stationkey(ni); 4812 } 4813 } 4814 4815 static int 4816 ath_getchannels(struct ath_softc *sc, u_int cc, 4817 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4818 { 4819 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4820 struct ieee80211com *ic = &sc->sc_ic; 4821 struct ifnet *ifp = &sc->sc_if; 4822 struct ath_hal *ah = sc->sc_ah; 4823 HAL_CHANNEL *chans; 4824 int i, ix, nchan; 4825 4826 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4827 M_TEMP, M_NOWAIT); 4828 if (chans == NULL) { 4829 if_printf(ifp, "unable to allocate channel table\n"); 4830 return ENOMEM; 4831 } 4832 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4833 NULL, 0, NULL, 4834 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4835 u_int32_t rd; 4836 4837 (void)ath_hal_getregdomain(ah, &rd); 4838 if_printf(ifp, "unable to collect channel list from hal; " 4839 "regdomain likely %u country code %u\n", rd, cc); 4840 free(chans, M_TEMP); 4841 return EINVAL; 4842 } 4843 4844 /* 4845 * Convert HAL channels to ieee80211 ones and insert 4846 * them in the table according to their channel number. 4847 */ 4848 for (i = 0; i < nchan; i++) { 4849 HAL_CHANNEL *c = &chans[i]; 4850 u_int16_t flags; 4851 4852 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4853 if (ix > IEEE80211_CHAN_MAX) { 4854 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4855 ix, c->channel, c->channelFlags); 4856 continue; 4857 } 4858 if (ix < 0) { 4859 /* XXX can't handle stuff <2400 right now */ 4860 if (bootverbose) 4861 if_printf(ifp, "hal channel %d (%u/%x) " 4862 "cannot be handled; ignored\n", 4863 ix, c->channel, c->channelFlags); 4864 continue; 4865 } 4866 /* 4867 * Calculate net80211 flags; most are compatible 4868 * but some need massaging. Note the static turbo 4869 * conversion can be removed once net80211 is updated 4870 * to understand static vs. dynamic turbo. 4871 */ 4872 flags = c->channelFlags & COMPAT; 4873 if (c->channelFlags & CHANNEL_STURBO) 4874 flags |= IEEE80211_CHAN_TURBO; 4875 if (ic->ic_channels[ix].ic_freq == 0) { 4876 ic->ic_channels[ix].ic_freq = c->channel; 4877 ic->ic_channels[ix].ic_flags = flags; 4878 } else { 4879 /* channels overlap; e.g. 11g and 11b */ 4880 ic->ic_channels[ix].ic_flags |= flags; 4881 } 4882 } 4883 free(chans, M_TEMP); 4884 return 0; 4885 #undef COMPAT 4886 } 4887 4888 static void 4889 ath_led_done(void *arg) 4890 { 4891 struct ath_softc *sc = arg; 4892 4893 sc->sc_blinking = 0; 4894 } 4895 4896 /* 4897 * Turn the LED off: flip the pin and then set a timer so no 4898 * update will happen for the specified duration. 4899 */ 4900 static void 4901 ath_led_off(void *arg) 4902 { 4903 struct ath_softc *sc = arg; 4904 4905 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4906 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4907 } 4908 4909 /* 4910 * Blink the LED according to the specified on/off times. 4911 */ 4912 static void 4913 ath_led_blink(struct ath_softc *sc, int on, int off) 4914 { 4915 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4916 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4917 sc->sc_blinking = 1; 4918 sc->sc_ledoff = off; 4919 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4920 } 4921 4922 static void 4923 ath_led_event(struct ath_softc *sc, int event) 4924 { 4925 4926 sc->sc_ledevent = ticks; /* time of last event */ 4927 if (sc->sc_blinking) /* don't interrupt active blink */ 4928 return; 4929 switch (event) { 4930 case ATH_LED_POLL: 4931 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4932 sc->sc_hwmap[0].ledoff); 4933 break; 4934 case ATH_LED_TX: 4935 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4936 sc->sc_hwmap[sc->sc_txrate].ledoff); 4937 break; 4938 case ATH_LED_RX: 4939 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4940 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4941 break; 4942 } 4943 } 4944 4945 static void 4946 ath_update_txpow(struct ath_softc *sc) 4947 { 4948 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4949 struct ieee80211com *ic = &sc->sc_ic; 4950 struct ath_hal *ah = sc->sc_ah; 4951 u_int32_t txpow; 4952 4953 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4954 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4955 /* read back in case value is clamped */ 4956 (void)ath_hal_gettxpowlimit(ah, &txpow); 4957 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4958 } 4959 /* 4960 * Fetch max tx power level for status requests. 4961 */ 4962 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4963 ic->ic_bss->ni_txpower = txpow; 4964 } 4965 4966 static void 4967 rate_setup(struct ath_softc *sc, 4968 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4969 { 4970 int i, maxrates; 4971 4972 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4973 DPRINTF(sc, ATH_DEBUG_ANY, 4974 "%s: rate table too small (%u > %u)\n", 4975 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4976 maxrates = IEEE80211_RATE_MAXSIZE; 4977 } else 4978 maxrates = rt->rateCount; 4979 for (i = 0; i < maxrates; i++) 4980 rs->rs_rates[i] = rt->info[i].dot11Rate; 4981 rs->rs_nrates = maxrates; 4982 } 4983 4984 static int 4985 ath_rate_setup(struct ath_softc *sc, u_int mode) 4986 { 4987 struct ath_hal *ah = sc->sc_ah; 4988 struct ieee80211com *ic = &sc->sc_ic; 4989 const HAL_RATE_TABLE *rt; 4990 4991 switch (mode) { 4992 case IEEE80211_MODE_11A: 4993 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4994 break; 4995 case IEEE80211_MODE_11B: 4996 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4997 break; 4998 case IEEE80211_MODE_11G: 4999 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5000 break; 5001 case IEEE80211_MODE_TURBO_A: 5002 /* XXX until static/dynamic turbo is fixed */ 5003 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5004 break; 5005 case IEEE80211_MODE_TURBO_G: 5006 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5007 break; 5008 default: 5009 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5010 __func__, mode); 5011 return 0; 5012 } 5013 sc->sc_rates[mode] = rt; 5014 if (rt != NULL) { 5015 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5016 return 1; 5017 } else 5018 return 0; 5019 } 5020 5021 static void 5022 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5023 { 5024 #define N(a) (sizeof(a)/sizeof(a[0])) 5025 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5026 static const struct { 5027 u_int rate; /* tx/rx 802.11 rate */ 5028 u_int16_t timeOn; /* LED on time (ms) */ 5029 u_int16_t timeOff; /* LED off time (ms) */ 5030 } blinkrates[] = { 5031 { 108, 40, 10 }, 5032 { 96, 44, 11 }, 5033 { 72, 50, 13 }, 5034 { 48, 57, 14 }, 5035 { 36, 67, 16 }, 5036 { 24, 80, 20 }, 5037 { 22, 100, 25 }, 5038 { 18, 133, 34 }, 5039 { 12, 160, 40 }, 5040 { 10, 200, 50 }, 5041 { 6, 240, 58 }, 5042 { 4, 267, 66 }, 5043 { 2, 400, 100 }, 5044 { 0, 500, 130 }, 5045 }; 5046 const HAL_RATE_TABLE *rt; 5047 int i, j; 5048 5049 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5050 rt = sc->sc_rates[mode]; 5051 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5052 for (i = 0; i < rt->rateCount; i++) 5053 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5054 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5055 for (i = 0; i < 32; i++) { 5056 u_int8_t ix = rt->rateCodeToIndex[i]; 5057 if (ix == 0xff) { 5058 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5059 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5060 continue; 5061 } 5062 sc->sc_hwmap[i].ieeerate = 5063 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5064 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5065 if (rt->info[ix].shortPreamble || 5066 rt->info[ix].phy == IEEE80211_T_OFDM) 5067 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5068 /* NB: receive frames include FCS */ 5069 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5070 IEEE80211_RADIOTAP_F_FCS; 5071 /* setup blink rate table to avoid per-packet lookup */ 5072 for (j = 0; j < N(blinkrates)-1; j++) 5073 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5074 break; 5075 /* NB: this uses the last entry if the rate isn't found */ 5076 /* XXX beware of overlow */ 5077 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5078 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5079 } 5080 sc->sc_currates = rt; 5081 sc->sc_curmode = mode; 5082 /* 5083 * All protection frames are transmited at 2Mb/s for 5084 * 11g, otherwise at 1Mb/s. 5085 */ 5086 if (mode == IEEE80211_MODE_11G) 5087 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5088 else 5089 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5090 /* rate index used to send management frames */ 5091 sc->sc_minrateix = 0; 5092 /* 5093 * Setup multicast rate state. 5094 */ 5095 /* XXX layering violation */ 5096 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5097 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5098 /* NB: caller is responsible for reseting rate control state */ 5099 #undef N 5100 } 5101 5102 #ifdef AR_DEBUG 5103 static void 5104 ath_printrxbuf(struct ath_buf *bf, int done) 5105 { 5106 struct ath_desc *ds; 5107 int i; 5108 5109 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5110 printf("R%d (%p %" PRIx64 5111 ") %08x %08x %08x %08x %08x %08x %c\n", i, ds, 5112 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5113 ds->ds_link, ds->ds_data, 5114 ds->ds_ctl0, ds->ds_ctl1, 5115 ds->ds_hw[0], ds->ds_hw[1], 5116 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5117 } 5118 } 5119 5120 static void 5121 ath_printtxbuf(struct ath_buf *bf, int done) 5122 { 5123 struct ath_desc *ds; 5124 int i; 5125 5126 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5127 printf("T%d (%p %" PRIx64 5128 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5129 i, ds, 5130 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5131 ds->ds_link, ds->ds_data, 5132 ds->ds_ctl0, ds->ds_ctl1, 5133 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5134 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5135 } 5136 } 5137 #endif /* AR_DEBUG */ 5138 5139 static void 5140 ath_watchdog(struct ifnet *ifp) 5141 { 5142 struct ath_softc *sc = ifp->if_softc; 5143 struct ieee80211com *ic = &sc->sc_ic; 5144 5145 ifp->if_timer = 0; 5146 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 5147 return; 5148 if (sc->sc_tx_timer) { 5149 if (--sc->sc_tx_timer == 0) { 5150 if_printf(ifp, "device timeout\n"); 5151 ath_reset(ifp); 5152 ifp->if_oerrors++; 5153 sc->sc_stats.ast_watchdog++; 5154 } else 5155 ifp->if_timer = 1; 5156 } 5157 ieee80211_watchdog(ic); 5158 } 5159 5160 /* 5161 * Diagnostic interface to the HAL. This is used by various 5162 * tools to do things like retrieve register contents for 5163 * debugging. The mechanism is intentionally opaque so that 5164 * it can change frequently w/o concern for compatiblity. 5165 */ 5166 static int 5167 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5168 { 5169 struct ath_hal *ah = sc->sc_ah; 5170 u_int id = ad->ad_id & ATH_DIAG_ID; 5171 void *indata = NULL; 5172 void *outdata = NULL; 5173 u_int32_t insize = ad->ad_in_size; 5174 u_int32_t outsize = ad->ad_out_size; 5175 int error = 0; 5176 5177 if (ad->ad_id & ATH_DIAG_IN) { 5178 /* 5179 * Copy in data. 5180 */ 5181 indata = malloc(insize, M_TEMP, M_NOWAIT); 5182 if (indata == NULL) { 5183 error = ENOMEM; 5184 goto bad; 5185 } 5186 error = copyin(ad->ad_in_data, indata, insize); 5187 if (error) 5188 goto bad; 5189 } 5190 if (ad->ad_id & ATH_DIAG_DYN) { 5191 /* 5192 * Allocate a buffer for the results (otherwise the HAL 5193 * returns a pointer to a buffer where we can read the 5194 * results). Note that we depend on the HAL leaving this 5195 * pointer for us to use below in reclaiming the buffer; 5196 * may want to be more defensive. 5197 */ 5198 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5199 if (outdata == NULL) { 5200 error = ENOMEM; 5201 goto bad; 5202 } 5203 } 5204 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5205 if (outsize < ad->ad_out_size) 5206 ad->ad_out_size = outsize; 5207 if (outdata != NULL) 5208 error = copyout(outdata, ad->ad_out_data, 5209 ad->ad_out_size); 5210 } else { 5211 error = EINVAL; 5212 } 5213 bad: 5214 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5215 free(indata, M_TEMP); 5216 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5217 free(outdata, M_TEMP); 5218 return error; 5219 } 5220 5221 static int 5222 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5223 { 5224 #define IS_RUNNING(ifp) \ 5225 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5226 struct ath_softc *sc = ifp->if_softc; 5227 struct ieee80211com *ic = &sc->sc_ic; 5228 struct ifreq *ifr = (struct ifreq *)data; 5229 int error = 0; 5230 5231 ATH_LOCK(sc); 5232 switch (cmd) { 5233 case SIOCSIFFLAGS: 5234 if (IS_RUNNING(ifp)) { 5235 /* 5236 * To avoid rescanning another access point, 5237 * do not call ath_init() here. Instead, 5238 * only reflect promisc mode settings. 5239 */ 5240 ath_mode_init(sc); 5241 } else if (ifp->if_flags & IFF_UP) { 5242 /* 5243 * Beware of being called during attach/detach 5244 * to reset promiscuous mode. In that case we 5245 * will still be marked UP but not RUNNING. 5246 * However trying to re-init the interface 5247 * is the wrong thing to do as we've already 5248 * torn down much of our state. There's 5249 * probably a better way to deal with this. 5250 */ 5251 if (!sc->sc_invalid && ic->ic_bss != NULL) 5252 ath_init(sc); /* XXX lose error */ 5253 } else 5254 ath_stop_locked(ifp, 1); 5255 break; 5256 case SIOCADDMULTI: 5257 case SIOCDELMULTI: 5258 error = (cmd == SIOCADDMULTI) ? 5259 ether_addmulti(ifr, &sc->sc_ec) : 5260 ether_delmulti(ifr, &sc->sc_ec); 5261 if (error == ENETRESET) { 5262 if (ifp->if_flags & IFF_RUNNING) 5263 ath_mode_init(sc); 5264 error = 0; 5265 } 5266 break; 5267 case SIOCGATHSTATS: 5268 /* NB: embed these numbers to get a consistent view */ 5269 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5270 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5271 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5272 ATH_UNLOCK(sc); 5273 /* 5274 * NB: Drop the softc lock in case of a page fault; 5275 * we'll accept any potential inconsisentcy in the 5276 * statistics. The alternative is to copy the data 5277 * to a local structure. 5278 */ 5279 return copyout(&sc->sc_stats, 5280 ifr->ifr_data, sizeof (sc->sc_stats)); 5281 case SIOCGATHDIAG: 5282 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5283 break; 5284 default: 5285 error = ieee80211_ioctl(ic, cmd, data); 5286 if (error == ENETRESET) { 5287 if (IS_RUNNING(ifp) && 5288 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5289 ath_init(sc); /* XXX lose error */ 5290 error = 0; 5291 } 5292 if (error == ERESTART) 5293 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5294 break; 5295 } 5296 ATH_UNLOCK(sc); 5297 return error; 5298 #undef IS_RUNNING 5299 } 5300 5301 #if NBPFILTER > 0 5302 static void 5303 ath_bpfattach(struct ath_softc *sc) 5304 { 5305 struct ifnet *ifp = &sc->sc_if; 5306 5307 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5308 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5309 &sc->sc_drvbpf); 5310 /* 5311 * Initialize constant fields. 5312 * XXX make header lengths a multiple of 32-bits so subsequent 5313 * headers are properly aligned; this is a kludge to keep 5314 * certain applications happy. 5315 * 5316 * NB: the channel is setup each time we transition to the 5317 * RUN state to avoid filling it in for each frame. 5318 */ 5319 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5320 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5321 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5322 5323 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5324 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5325 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5326 } 5327 #endif 5328 5329 /* 5330 * Announce various information on device/driver attach. 5331 */ 5332 static void 5333 ath_announce(struct ath_softc *sc) 5334 { 5335 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5336 struct ifnet *ifp = &sc->sc_if; 5337 struct ath_hal *ah = sc->sc_ah; 5338 u_int modes, cc; 5339 5340 if_printf(ifp, "mac %d.%d phy %d.%d", 5341 ah->ah_macVersion, ah->ah_macRev, 5342 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5343 /* 5344 * Print radio revision(s). We check the wireless modes 5345 * to avoid falsely printing revs for inoperable parts. 5346 * Dual-band radio revs are returned in the 5 GHz rev number. 5347 */ 5348 ath_hal_getcountrycode(ah, &cc); 5349 modes = ath_hal_getwirelessmodes(ah, cc); 5350 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5351 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5352 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5353 ah->ah_analog5GhzRev >> 4, 5354 ah->ah_analog5GhzRev & 0xf, 5355 ah->ah_analog2GhzRev >> 4, 5356 ah->ah_analog2GhzRev & 0xf); 5357 else 5358 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5359 ah->ah_analog5GhzRev & 0xf); 5360 } else 5361 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5362 ah->ah_analog5GhzRev & 0xf); 5363 printf("\n"); 5364 if (bootverbose) { 5365 int i; 5366 for (i = 0; i <= WME_AC_VO; i++) { 5367 struct ath_txq *txq = sc->sc_ac2q[i]; 5368 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5369 txq->axq_qnum, ieee80211_wme_acnames[i]); 5370 } 5371 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5372 sc->sc_cabq->axq_qnum); 5373 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5374 } 5375 if (ath_rxbuf != ATH_RXBUF) 5376 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5377 if (ath_txbuf != ATH_TXBUF) 5378 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5379 #undef HAL_MODE_DUALBAND 5380 } 5381
Indexes created Thu Oct 02 07:10:07 GMT 2025