ath.c revision 1.76.6.2
1 /* $NetBSD: ath.c,v 1.76.6.2 2006/12/10 07:17:04 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.76.6.2 2006/12/10 07:17:04 yamt Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <machine/bus.h> 74 #include <sys/endian.h> 75 76 #include <machine/bus.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/if_ether.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_netbsd.h> 87 #include <net80211/ieee80211_var.h> 88 89 #if NBPFILTER > 0 90 #include <net/bpf.h> 91 #endif 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #endif 96 97 #include <sys/device.h> 98 #include <dev/ic/ath_netbsd.h> 99 100 #define AR_DEBUG 101 #include <dev/ic/athvar.h> 102 #include <contrib/dev/ath/ah_desc.h> 103 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 104 #include "athhal_options.h" 105 106 #ifdef ATH_TX99_DIAG 107 #include <dev/ath/ath_tx99/ath_tx99.h> 108 #endif 109 110 /* unaligned little endian access */ 111 #define LE_READ_2(p) \ 112 ((u_int16_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 114 #define LE_READ_4(p) \ 115 ((u_int32_t) \ 116 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 117 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 118 119 enum { 120 ATH_LED_TX, 121 ATH_LED_RX, 122 ATH_LED_POLL, 123 }; 124 125 #ifdef AH_NEED_DESC_SWAP 126 #define HTOAH32(x) htole32(x) 127 #else 128 #define HTOAH32(x) (x) 129 #endif 130 131 static int ath_ifinit(struct ifnet *); 132 static int ath_init(struct ath_softc *); 133 static void ath_stop_locked(struct ifnet *, int); 134 static void ath_stop(struct ifnet *, int); 135 static void ath_start(struct ifnet *); 136 static int ath_media_change(struct ifnet *); 137 static void ath_watchdog(struct ifnet *); 138 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 139 static void ath_fatal_proc(void *, int); 140 static void ath_rxorn_proc(void *, int); 141 static void ath_bmiss_proc(void *, int); 142 static void ath_radar_proc(void *, int); 143 static int ath_key_alloc(struct ieee80211com *, 144 const struct ieee80211_key *, 145 ieee80211_keyix *, ieee80211_keyix *); 146 static int ath_key_delete(struct ieee80211com *, 147 const struct ieee80211_key *); 148 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 149 const u_int8_t mac[IEEE80211_ADDR_LEN]); 150 static void ath_key_update_begin(struct ieee80211com *); 151 static void ath_key_update_end(struct ieee80211com *); 152 static void ath_mode_init(struct ath_softc *); 153 static void ath_setslottime(struct ath_softc *); 154 static void ath_updateslot(struct ifnet *); 155 static int ath_beaconq_setup(struct ath_hal *); 156 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 157 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 158 static void ath_beacon_proc(void *, int); 159 static void ath_bstuck_proc(void *, int); 160 static void ath_beacon_free(struct ath_softc *); 161 static void ath_beacon_config(struct ath_softc *); 162 static void ath_descdma_cleanup(struct ath_softc *sc, 163 struct ath_descdma *, ath_bufhead *); 164 static int ath_desc_alloc(struct ath_softc *); 165 static void ath_desc_free(struct ath_softc *); 166 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 167 static void ath_node_free(struct ieee80211_node *); 168 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 169 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 170 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 171 struct ieee80211_node *ni, 172 int subtype, int rssi, u_int32_t rstamp); 173 static void ath_setdefantenna(struct ath_softc *, u_int); 174 static void ath_rx_proc(void *, int); 175 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 176 static int ath_tx_setup(struct ath_softc *, int, int); 177 static int ath_wme_update(struct ieee80211com *); 178 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 179 static void ath_tx_cleanup(struct ath_softc *); 180 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 181 struct ath_buf *, struct mbuf *); 182 static void ath_tx_proc_q0(void *, int); 183 static void ath_tx_proc_q0123(void *, int); 184 static void ath_tx_proc(void *, int); 185 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 186 static void ath_draintxq(struct ath_softc *); 187 static void ath_stoprecv(struct ath_softc *); 188 static int ath_startrecv(struct ath_softc *); 189 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 190 static void ath_next_scan(void *); 191 static void ath_calibrate(void *); 192 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 193 static void ath_setup_stationkey(struct ieee80211_node *); 194 static void ath_newassoc(struct ieee80211_node *, int); 195 static int ath_getchannels(struct ath_softc *, u_int cc, 196 HAL_BOOL outdoor, HAL_BOOL xchanmode); 197 static void ath_led_event(struct ath_softc *, int); 198 static void ath_update_txpow(struct ath_softc *); 199 200 static int ath_rate_setup(struct ath_softc *, u_int mode); 201 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 202 203 #ifdef __NetBSD__ 204 int ath_enable(struct ath_softc *); 205 void ath_disable(struct ath_softc *); 206 void ath_power(int, void *); 207 #endif 208 209 #if NBPFILTER > 0 210 static void ath_bpfattach(struct ath_softc *); 211 #endif 212 static void ath_announce(struct ath_softc *); 213 214 int ath_dwelltime = 200; /* 5 channels/second */ 215 int ath_calinterval = 30; /* calibrate every 30 secs */ 216 int ath_outdoor = AH_TRUE; /* outdoor operation */ 217 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 218 int ath_countrycode = CTRY_DEFAULT; /* country code */ 219 int ath_regdomain = 0; /* regulatory domain */ 220 int ath_debug = 0; 221 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 222 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 223 224 #ifdef AR_DEBUG 225 enum { 226 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 227 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 228 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 229 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 230 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 231 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 232 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 233 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 234 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 235 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 236 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 237 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 238 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 239 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 240 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 241 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 242 ATH_DEBUG_NODE = 0x00080000, /* node management */ 243 ATH_DEBUG_LED = 0x00100000, /* led management */ 244 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 245 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 246 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 247 ATH_DEBUG_ANY = 0xffffffff 248 }; 249 #define IFF_DUMPPKTS(sc, m) \ 250 ((sc->sc_debug & (m)) || \ 251 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 252 #define DPRINTF(sc, m, fmt, ...) do { \ 253 if (sc->sc_debug & (m)) \ 254 printf(fmt, __VA_ARGS__); \ 255 } while (0) 256 #define KEYPRINTF(sc, ix, hk, mac) do { \ 257 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 258 ath_keyprint(__func__, ix, hk, mac); \ 259 } while (0) 260 static void ath_printrxbuf(struct ath_buf *bf, int); 261 static void ath_printtxbuf(struct ath_buf *bf, int); 262 #else 263 #define IFF_DUMPPKTS(sc, m) \ 264 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 265 #define DPRINTF(m, fmt, ...) 266 #define KEYPRINTF(sc, k, ix, mac) 267 #endif 268 269 #ifdef __NetBSD__ 270 int 271 ath_activate(struct device *self, enum devact act) 272 { 273 struct ath_softc *sc = (struct ath_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 case DVACT_DEACTIVATE: 282 if_deactivate(&sc->sc_if); 283 break; 284 } 285 splx(s); 286 return rv; 287 } 288 289 int 290 ath_enable(struct ath_softc *sc) 291 { 292 if (ATH_IS_ENABLED(sc) == 0) { 293 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 294 printf("%s: device enable failed\n", 295 sc->sc_dev.dv_xname); 296 return (EIO); 297 } 298 sc->sc_flags |= ATH_ENABLED; 299 } 300 return (0); 301 } 302 303 void 304 ath_disable(struct ath_softc *sc) 305 { 306 if (!ATH_IS_ENABLED(sc)) 307 return; 308 if (sc->sc_disable != NULL) 309 (*sc->sc_disable)(sc); 310 sc->sc_flags &= ~ATH_ENABLED; 311 } 312 #endif /* __NetBSD__ */ 313 314 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 315 316 int 317 ath_attach(u_int16_t devid, struct ath_softc *sc) 318 { 319 struct ifnet *ifp = &sc->sc_if; 320 struct ieee80211com *ic = &sc->sc_ic; 321 struct ath_hal *ah = NULL; 322 HAL_STATUS status; 323 int error = 0, i; 324 325 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 326 327 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 328 329 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 330 if (ah == NULL) { 331 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 332 status); 333 error = ENXIO; 334 goto bad; 335 } 336 if (ah->ah_abi != HAL_ABI_VERSION) { 337 if_printf(ifp, "HAL ABI mismatch detected " 338 "(HAL:0x%x != driver:0x%x)\n", 339 ah->ah_abi, HAL_ABI_VERSION); 340 error = ENXIO; 341 goto bad; 342 } 343 sc->sc_ah = ah; 344 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 345 346 /* 347 * Check if the MAC has multi-rate retry support. 348 * We do this by trying to setup a fake extended 349 * descriptor. MAC's that don't have support will 350 * return false w/o doing anything. MAC's that do 351 * support it will return true w/o doing anything. 352 */ 353 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 354 355 /* 356 * Check if the device has hardware counters for PHY 357 * errors. If so we need to enable the MIB interrupt 358 * so we can act on stat triggers. 359 */ 360 if (ath_hal_hwphycounters(ah)) 361 sc->sc_needmib = 1; 362 363 /* 364 * Get the hardware key cache size. 365 */ 366 sc->sc_keymax = ath_hal_keycachesize(ah); 367 if (sc->sc_keymax > ATH_KEYMAX) { 368 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 369 ATH_KEYMAX, sc->sc_keymax); 370 sc->sc_keymax = ATH_KEYMAX; 371 } 372 /* 373 * Reset the key cache since some parts do not 374 * reset the contents on initial power up. 375 */ 376 for (i = 0; i < sc->sc_keymax; i++) 377 ath_hal_keyreset(ah, i); 378 /* 379 * Mark key cache slots associated with global keys 380 * as in use. If we knew TKIP was not to be used we 381 * could leave the +32, +64, and +32+64 slots free. 382 * XXX only for splitmic. 383 */ 384 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 385 setbit(sc->sc_keymap, i); 386 setbit(sc->sc_keymap, i+32); 387 setbit(sc->sc_keymap, i+64); 388 setbit(sc->sc_keymap, i+32+64); 389 } 390 391 /* 392 * Collect the channel list using the default country 393 * code and including outdoor channels. The 802.11 layer 394 * is resposible for filtering this list based on settings 395 * like the phy mode. 396 */ 397 error = ath_getchannels(sc, ath_countrycode, 398 ath_outdoor, ath_xchanmode); 399 if (error != 0) 400 goto bad; 401 402 /* 403 * Setup rate tables for all potential media types. 404 */ 405 ath_rate_setup(sc, IEEE80211_MODE_11A); 406 ath_rate_setup(sc, IEEE80211_MODE_11B); 407 ath_rate_setup(sc, IEEE80211_MODE_11G); 408 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 409 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 410 /* NB: setup here so ath_rate_update is happy */ 411 ath_setcurmode(sc, IEEE80211_MODE_11A); 412 413 /* 414 * Allocate tx+rx descriptors and populate the lists. 415 */ 416 error = ath_desc_alloc(sc); 417 if (error != 0) { 418 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 419 goto bad; 420 } 421 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 422 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 423 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 424 425 ATH_TXBUF_LOCK_INIT(sc); 426 427 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 428 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 429 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 430 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 431 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 432 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 433 434 /* 435 * Allocate hardware transmit queues: one queue for 436 * beacon frames and one data queue for each QoS 437 * priority. Note that the hal handles reseting 438 * these queues at the needed time. 439 * 440 * XXX PS-Poll 441 */ 442 sc->sc_bhalq = ath_beaconq_setup(ah); 443 if (sc->sc_bhalq == (u_int) -1) { 444 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 445 error = EIO; 446 goto bad2; 447 } 448 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 449 if (sc->sc_cabq == NULL) { 450 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 451 error = EIO; 452 goto bad2; 453 } 454 /* NB: insure BK queue is the lowest priority h/w queue */ 455 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 456 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 457 ieee80211_wme_acnames[WME_AC_BK]); 458 error = EIO; 459 goto bad2; 460 } 461 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 462 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 463 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 464 /* 465 * Not enough hardware tx queues to properly do WME; 466 * just punt and assign them all to the same h/w queue. 467 * We could do a better job of this if, for example, 468 * we allocate queues when we switch from station to 469 * AP mode. 470 */ 471 if (sc->sc_ac2q[WME_AC_VI] != NULL) 472 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 473 if (sc->sc_ac2q[WME_AC_BE] != NULL) 474 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 475 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 476 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 477 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 478 } 479 480 /* 481 * Special case certain configurations. Note the 482 * CAB queue is handled by these specially so don't 483 * include them when checking the txq setup mask. 484 */ 485 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 486 case 0x01: 487 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 488 break; 489 case 0x0f: 490 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 491 break; 492 default: 493 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 494 break; 495 } 496 497 /* 498 * Setup rate control. Some rate control modules 499 * call back to change the anntena state so expose 500 * the necessary entry points. 501 * XXX maybe belongs in struct ath_ratectrl? 502 */ 503 sc->sc_setdefantenna = ath_setdefantenna; 504 sc->sc_rc = ath_rate_attach(sc); 505 if (sc->sc_rc == NULL) { 506 error = EIO; 507 goto bad2; 508 } 509 510 sc->sc_blinking = 0; 511 sc->sc_ledstate = 1; 512 sc->sc_ledon = 0; /* low true */ 513 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 514 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 515 /* 516 * Auto-enable soft led processing for IBM cards and for 517 * 5211 minipci cards. Users can also manually enable/disable 518 * support with a sysctl. 519 */ 520 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 521 if (sc->sc_softled) { 522 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 523 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 524 } 525 526 ifp->if_softc = sc; 527 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 528 ifp->if_start = ath_start; 529 ifp->if_watchdog = ath_watchdog; 530 ifp->if_ioctl = ath_ioctl; 531 ifp->if_init = ath_ifinit; 532 IFQ_SET_READY(&ifp->if_snd); 533 534 ic->ic_ifp = ifp; 535 ic->ic_reset = ath_reset; 536 ic->ic_newassoc = ath_newassoc; 537 ic->ic_updateslot = ath_updateslot; 538 ic->ic_wme.wme_update = ath_wme_update; 539 /* XXX not right but it's not used anywhere important */ 540 ic->ic_phytype = IEEE80211_T_OFDM; 541 ic->ic_opmode = IEEE80211_M_STA; 542 ic->ic_caps = 543 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 544 | IEEE80211_C_HOSTAP /* hostap mode */ 545 | IEEE80211_C_MONITOR /* monitor mode */ 546 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 547 | IEEE80211_C_SHSLOT /* short slot time supported */ 548 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 549 ; 550 /* 551 * Query the hal to figure out h/w crypto support. 552 */ 553 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 554 ic->ic_caps |= IEEE80211_C_WEP; 555 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 556 ic->ic_caps |= IEEE80211_C_AES; 557 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 558 ic->ic_caps |= IEEE80211_C_AES_CCM; 559 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 560 ic->ic_caps |= IEEE80211_C_CKIP; 561 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 562 ic->ic_caps |= IEEE80211_C_TKIP; 563 /* 564 * Check if h/w does the MIC and/or whether the 565 * separate key cache entries are required to 566 * handle both tx+rx MIC keys. 567 */ 568 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 569 ic->ic_caps |= IEEE80211_C_TKIPMIC; 570 if (ath_hal_tkipsplit(ah)) 571 sc->sc_splitmic = 1; 572 } 573 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 574 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 575 /* 576 * TPC support can be done either with a global cap or 577 * per-packet support. The latter is not available on 578 * all parts. We're a bit pedantic here as all parts 579 * support a global cap. 580 */ 581 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 582 ic->ic_caps |= IEEE80211_C_TXPMGT; 583 584 /* 585 * Mark WME capability only if we have sufficient 586 * hardware queues to do proper priority scheduling. 587 */ 588 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 589 ic->ic_caps |= IEEE80211_C_WME; 590 /* 591 * Check for misc other capabilities. 592 */ 593 if (ath_hal_hasbursting(ah)) 594 ic->ic_caps |= IEEE80211_C_BURST; 595 596 /* 597 * Indicate we need the 802.11 header padded to a 598 * 32-bit boundary for 4-address and QoS frames. 599 */ 600 ic->ic_flags |= IEEE80211_F_DATAPAD; 601 602 /* 603 * Query the hal about antenna support. 604 */ 605 sc->sc_defant = ath_hal_getdefantenna(ah); 606 607 /* 608 * Not all chips have the VEOL support we want to 609 * use with IBSS beacons; check here for it. 610 */ 611 sc->sc_hasveol = ath_hal_hasveol(ah); 612 613 /* get mac address from hardware */ 614 ath_hal_getmac(ah, ic->ic_myaddr); 615 616 if_attach(ifp); 617 /* call MI attach routine. */ 618 ieee80211_ifattach(ic); 619 /* override default methods */ 620 ic->ic_node_alloc = ath_node_alloc; 621 sc->sc_node_free = ic->ic_node_free; 622 ic->ic_node_free = ath_node_free; 623 ic->ic_node_getrssi = ath_node_getrssi; 624 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 625 ic->ic_recv_mgmt = ath_recv_mgmt; 626 sc->sc_newstate = ic->ic_newstate; 627 ic->ic_newstate = ath_newstate; 628 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 629 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 630 ic->ic_crypto.cs_key_delete = ath_key_delete; 631 ic->ic_crypto.cs_key_set = ath_key_set; 632 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 633 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 634 /* complete initialization */ 635 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 636 637 #if NBPFILTER > 0 638 ath_bpfattach(sc); 639 #endif 640 641 #ifdef __NetBSD__ 642 sc->sc_flags |= ATH_ATTACHED; 643 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 644 ath_power, sc); 645 if (sc->sc_powerhook == NULL) 646 printf("%s: WARNING: unable to establish power hook\n", 647 sc->sc_dev.dv_xname); 648 #endif 649 650 /* 651 * Setup dynamic sysctl's now that country code and 652 * regdomain are available from the hal. 653 */ 654 ath_sysctlattach(sc); 655 656 ieee80211_announce(ic); 657 ath_announce(sc); 658 return 0; 659 bad2: 660 ath_tx_cleanup(sc); 661 ath_desc_free(sc); 662 bad: 663 if (ah) 664 ath_hal_detach(ah); 665 sc->sc_invalid = 1; 666 return error; 667 } 668 669 int 670 ath_detach(struct ath_softc *sc) 671 { 672 struct ifnet *ifp = &sc->sc_if; 673 int s; 674 675 if ((sc->sc_flags & ATH_ATTACHED) == 0) 676 return (0); 677 678 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 679 __func__, ifp->if_flags); 680 681 s = splnet(); 682 ath_stop(ifp, 1); 683 #if NBPFILTER > 0 684 bpfdetach(ifp); 685 #endif 686 /* 687 * NB: the order of these is important: 688 * o call the 802.11 layer before detaching the hal to 689 * insure callbacks into the driver to delete global 690 * key cache entries can be handled 691 * o reclaim the tx queue data structures after calling 692 * the 802.11 layer as we'll get called back to reclaim 693 * node state and potentially want to use them 694 * o to cleanup the tx queues the hal is called, so detach 695 * it last 696 * Other than that, it's straightforward... 697 */ 698 ieee80211_ifdetach(&sc->sc_ic); 699 #ifdef ATH_TX99_DIAG 700 if (sc->sc_tx99 != NULL) 701 sc->sc_tx99->detach(sc->sc_tx99); 702 #endif 703 ath_rate_detach(sc->sc_rc); 704 ath_desc_free(sc); 705 ath_tx_cleanup(sc); 706 sysctl_teardown(&sc->sc_sysctllog); 707 ath_hal_detach(sc->sc_ah); 708 if_detach(ifp); 709 splx(s); 710 powerhook_disestablish(sc->sc_powerhook); 711 712 return 0; 713 } 714 715 #ifdef __NetBSD__ 716 void 717 ath_power(int why, void *arg) 718 { 719 struct ath_softc *sc = arg; 720 int s; 721 722 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 723 724 s = splnet(); 725 switch (why) { 726 case PWR_SUSPEND: 727 case PWR_STANDBY: 728 ath_suspend(sc, why); 729 break; 730 case PWR_RESUME: 731 ath_resume(sc, why); 732 break; 733 case PWR_SOFTSUSPEND: 734 case PWR_SOFTSTANDBY: 735 case PWR_SOFTRESUME: 736 break; 737 } 738 splx(s); 739 } 740 #endif 741 742 void 743 ath_suspend(struct ath_softc *sc, int why) 744 { 745 struct ifnet *ifp = &sc->sc_if; 746 747 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 748 __func__, ifp->if_flags); 749 750 ath_stop(ifp, 1); 751 if (sc->sc_power != NULL) 752 (*sc->sc_power)(sc, why); 753 } 754 755 void 756 ath_resume(struct ath_softc *sc, int why) 757 { 758 struct ifnet *ifp = &sc->sc_if; 759 760 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 761 __func__, ifp->if_flags); 762 763 if (ifp->if_flags & IFF_UP) { 764 ath_init(sc); 765 #if 0 766 (void)ath_intr(sc); 767 #endif 768 if (sc->sc_power != NULL) 769 (*sc->sc_power)(sc, why); 770 if (ifp->if_flags & IFF_RUNNING) 771 ath_start(ifp); 772 } 773 if (sc->sc_softled) { 774 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 775 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 776 } 777 } 778 779 void 780 ath_shutdown(void *arg) 781 { 782 struct ath_softc *sc = arg; 783 784 ath_stop(&sc->sc_if, 1); 785 } 786 787 /* 788 * Interrupt handler. Most of the actual processing is deferred. 789 */ 790 int 791 ath_intr(void *arg) 792 { 793 struct ath_softc *sc = arg; 794 struct ifnet *ifp = &sc->sc_if; 795 struct ath_hal *ah = sc->sc_ah; 796 HAL_INT status; 797 798 if (sc->sc_invalid) { 799 /* 800 * The hardware is not ready/present, don't touch anything. 801 * Note this can happen early on if the IRQ is shared. 802 */ 803 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 804 return 0; 805 } 806 807 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 808 return 0; 809 810 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 811 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 812 __func__, ifp->if_flags); 813 ath_hal_getisr(ah, &status); /* clear ISR */ 814 ath_hal_intrset(ah, 0); /* disable further intr's */ 815 return 1; /* XXX */ 816 } 817 /* 818 * Figure out the reason(s) for the interrupt. Note 819 * that the hal returns a pseudo-ISR that may include 820 * bits we haven't explicitly enabled so we mask the 821 * value to insure we only process bits we requested. 822 */ 823 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 824 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 825 status &= sc->sc_imask; /* discard unasked for bits */ 826 if (status & HAL_INT_FATAL) { 827 /* 828 * Fatal errors are unrecoverable. Typically 829 * these are caused by DMA errors. Unfortunately 830 * the exact reason is not (presently) returned 831 * by the hal. 832 */ 833 sc->sc_stats.ast_hardware++; 834 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 835 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 836 } else if (status & HAL_INT_RXORN) { 837 sc->sc_stats.ast_rxorn++; 838 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 839 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 840 } else { 841 if (status & HAL_INT_SWBA) { 842 /* 843 * Software beacon alert--time to send a beacon. 844 * Handle beacon transmission directly; deferring 845 * this is too slow to meet timing constraints 846 * under load. 847 */ 848 ath_beacon_proc(sc, 0); 849 } 850 if (status & HAL_INT_RXEOL) { 851 /* 852 * NB: the hardware should re-read the link when 853 * RXE bit is written, but it doesn't work at 854 * least on older hardware revs. 855 */ 856 sc->sc_stats.ast_rxeol++; 857 sc->sc_rxlink = NULL; 858 } 859 if (status & HAL_INT_TXURN) { 860 sc->sc_stats.ast_txurn++; 861 /* bump tx trigger level */ 862 ath_hal_updatetxtriglevel(ah, AH_TRUE); 863 } 864 if (status & HAL_INT_RX) 865 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 866 if (status & HAL_INT_TX) 867 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 868 if (status & HAL_INT_BMISS) { 869 sc->sc_stats.ast_bmiss++; 870 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 871 } 872 if (status & HAL_INT_MIB) { 873 sc->sc_stats.ast_mib++; 874 /* 875 * Disable interrupts until we service the MIB 876 * interrupt; otherwise it will continue to fire. 877 */ 878 ath_hal_intrset(ah, 0); 879 /* 880 * Let the hal handle the event. We assume it will 881 * clear whatever condition caused the interrupt. 882 */ 883 ath_hal_mibevent(ah, &sc->sc_halstats); 884 ath_hal_intrset(ah, sc->sc_imask); 885 } 886 } 887 return 1; 888 } 889 890 /* Swap transmit descriptor. 891 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 892 * function. 893 */ 894 static inline void 895 ath_desc_swap(struct ath_desc *ds) 896 { 897 #ifdef AH_NEED_DESC_SWAP 898 ds->ds_link = htole32(ds->ds_link); 899 ds->ds_data = htole32(ds->ds_data); 900 ds->ds_ctl0 = htole32(ds->ds_ctl0); 901 ds->ds_ctl1 = htole32(ds->ds_ctl1); 902 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 903 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 904 #endif 905 } 906 907 static void 908 ath_fatal_proc(void *arg, int pending) 909 { 910 struct ath_softc *sc = arg; 911 struct ifnet *ifp = &sc->sc_if; 912 913 if_printf(ifp, "hardware error; resetting\n"); 914 ath_reset(ifp); 915 } 916 917 static void 918 ath_rxorn_proc(void *arg, int pending) 919 { 920 struct ath_softc *sc = arg; 921 struct ifnet *ifp = &sc->sc_if; 922 923 if_printf(ifp, "rx FIFO overrun; resetting\n"); 924 ath_reset(ifp); 925 } 926 927 static void 928 ath_bmiss_proc(void *arg, int pending) 929 { 930 struct ath_softc *sc = arg; 931 struct ieee80211com *ic = &sc->sc_ic; 932 933 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 934 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 935 ("unexpect operating mode %u", ic->ic_opmode)); 936 if (ic->ic_state == IEEE80211_S_RUN) { 937 u_int64_t lastrx = sc->sc_lastrx; 938 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 939 940 DPRINTF(sc, ATH_DEBUG_BEACON, 941 "%s: tsf %" PRIu64 " lastrx %" PRId64 942 " (%" PRIu64 ") bmiss %u\n", 943 __func__, tsf, tsf - lastrx, lastrx, 944 ic->ic_bmisstimeout*1024); 945 /* 946 * Workaround phantom bmiss interrupts by sanity-checking 947 * the time of our last rx'd frame. If it is within the 948 * beacon miss interval then ignore the interrupt. If it's 949 * truly a bmiss we'll get another interrupt soon and that'll 950 * be dispatched up for processing. 951 */ 952 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 953 NET_LOCK_GIANT(); 954 ieee80211_beacon_miss(ic); 955 NET_UNLOCK_GIANT(); 956 } else 957 sc->sc_stats.ast_bmiss_phantom++; 958 } 959 } 960 961 static void 962 ath_radar_proc(void *arg, int pending) 963 { 964 struct ath_softc *sc = arg; 965 struct ifnet *ifp = &sc->sc_if; 966 struct ath_hal *ah = sc->sc_ah; 967 HAL_CHANNEL hchan; 968 969 if (ath_hal_procdfs(ah, &hchan)) { 970 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 971 hchan.channel, hchan.channelFlags, hchan.privFlags); 972 /* 973 * Initiate channel change. 974 */ 975 /* XXX not yet */ 976 } 977 } 978 979 static u_int 980 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 981 { 982 #define N(a) (sizeof(a) / sizeof(a[0])) 983 static const u_int modeflags[] = { 984 0, /* IEEE80211_MODE_AUTO */ 985 CHANNEL_A, /* IEEE80211_MODE_11A */ 986 CHANNEL_B, /* IEEE80211_MODE_11B */ 987 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 988 0, /* IEEE80211_MODE_FH */ 989 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 990 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 991 }; 992 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 993 994 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 995 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 996 return modeflags[mode]; 997 #undef N 998 } 999 1000 static int 1001 ath_ifinit(struct ifnet *ifp) 1002 { 1003 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 1004 1005 return ath_init(sc); 1006 } 1007 1008 static int 1009 ath_init(struct ath_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->sc_if; 1012 struct ieee80211com *ic = &sc->sc_ic; 1013 struct ath_hal *ah = sc->sc_ah; 1014 HAL_STATUS status; 1015 int error = 0; 1016 1017 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1018 __func__, ifp->if_flags); 1019 1020 ATH_LOCK(sc); 1021 1022 if ((error = ath_enable(sc)) != 0) 1023 return error; 1024 1025 /* 1026 * Stop anything previously setup. This is safe 1027 * whether this is the first time through or not. 1028 */ 1029 ath_stop_locked(ifp, 0); 1030 1031 /* 1032 * The basic interface to setting the hardware in a good 1033 * state is ``reset''. On return the hardware is known to 1034 * be powered up and with interrupts disabled. This must 1035 * be followed by initialization of the appropriate bits 1036 * and then setup of the interrupt mask. 1037 */ 1038 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1039 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1040 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1041 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1042 status); 1043 error = EIO; 1044 goto done; 1045 } 1046 1047 /* 1048 * This is needed only to setup initial state 1049 * but it's best done after a reset. 1050 */ 1051 ath_update_txpow(sc); 1052 /* 1053 * Likewise this is set during reset so update 1054 * state cached in the driver. 1055 */ 1056 sc->sc_diversity = ath_hal_getdiversity(ah); 1057 sc->sc_calinterval = 1; 1058 sc->sc_caltries = 0; 1059 1060 /* 1061 * Setup the hardware after reset: the key cache 1062 * is filled as needed and the receive engine is 1063 * set going. Frame transmit is handled entirely 1064 * in the frame output path; there's nothing to do 1065 * here except setup the interrupt mask. 1066 */ 1067 if ((error = ath_startrecv(sc)) != 0) { 1068 if_printf(ifp, "unable to start recv logic\n"); 1069 goto done; 1070 } 1071 1072 /* 1073 * Enable interrupts. 1074 */ 1075 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1076 | HAL_INT_RXEOL | HAL_INT_RXORN 1077 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1078 /* 1079 * Enable MIB interrupts when there are hardware phy counters. 1080 * Note we only do this (at the moment) for station mode. 1081 */ 1082 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1083 sc->sc_imask |= HAL_INT_MIB; 1084 ath_hal_intrset(ah, sc->sc_imask); 1085 1086 ifp->if_flags |= IFF_RUNNING; 1087 ic->ic_state = IEEE80211_S_INIT; 1088 1089 /* 1090 * The hardware should be ready to go now so it's safe 1091 * to kick the 802.11 state machine as it's likely to 1092 * immediately call back to us to send mgmt frames. 1093 */ 1094 ath_chan_change(sc, ic->ic_curchan); 1095 #ifdef ATH_TX99_DIAG 1096 if (sc->sc_tx99 != NULL) 1097 sc->sc_tx99->start(sc->sc_tx99); 1098 else 1099 #endif 1100 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1101 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1102 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1103 } else 1104 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1105 done: 1106 ATH_UNLOCK(sc); 1107 return error; 1108 } 1109 1110 static void 1111 ath_stop_locked(struct ifnet *ifp, int disable) 1112 { 1113 struct ath_softc *sc = ifp->if_softc; 1114 struct ieee80211com *ic = &sc->sc_ic; 1115 struct ath_hal *ah = sc->sc_ah; 1116 1117 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1118 __func__, sc->sc_invalid, ifp->if_flags); 1119 1120 ATH_LOCK_ASSERT(sc); 1121 if (ifp->if_flags & IFF_RUNNING) { 1122 /* 1123 * Shutdown the hardware and driver: 1124 * reset 802.11 state machine 1125 * turn off timers 1126 * disable interrupts 1127 * turn off the radio 1128 * clear transmit machinery 1129 * clear receive machinery 1130 * drain and release tx queues 1131 * reclaim beacon resources 1132 * power down hardware 1133 * 1134 * Note that some of this work is not possible if the 1135 * hardware is gone (invalid). 1136 */ 1137 #ifdef ATH_TX99_DIAG 1138 if (sc->sc_tx99 != NULL) 1139 sc->sc_tx99->stop(sc->sc_tx99); 1140 #endif 1141 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1142 ifp->if_flags &= ~IFF_RUNNING; 1143 ifp->if_timer = 0; 1144 if (!sc->sc_invalid) { 1145 if (sc->sc_softled) { 1146 callout_stop(&sc->sc_ledtimer); 1147 ath_hal_gpioset(ah, sc->sc_ledpin, 1148 !sc->sc_ledon); 1149 sc->sc_blinking = 0; 1150 } 1151 ath_hal_intrset(ah, 0); 1152 } 1153 ath_draintxq(sc); 1154 if (!sc->sc_invalid) { 1155 ath_stoprecv(sc); 1156 ath_hal_phydisable(ah); 1157 } else 1158 sc->sc_rxlink = NULL; 1159 IF_PURGE(&ifp->if_snd); 1160 ath_beacon_free(sc); 1161 if (disable) 1162 ath_disable(sc); 1163 } 1164 } 1165 1166 static void 1167 ath_stop(struct ifnet *ifp, int disable) 1168 { 1169 struct ath_softc *sc = ifp->if_softc; 1170 1171 ATH_LOCK(sc); 1172 ath_stop_locked(ifp, disable); 1173 if (!sc->sc_invalid) { 1174 /* 1175 * Set the chip in full sleep mode. Note that we are 1176 * careful to do this only when bringing the interface 1177 * completely to a stop. When the chip is in this state 1178 * it must be carefully woken up or references to 1179 * registers in the PCI clock domain may freeze the bus 1180 * (and system). This varies by chip and is mostly an 1181 * issue with newer parts that go to sleep more quickly. 1182 */ 1183 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1184 } 1185 ATH_UNLOCK(sc); 1186 } 1187 1188 /* 1189 * Reset the hardware w/o losing operational state. This is 1190 * basically a more efficient way of doing ath_stop, ath_init, 1191 * followed by state transitions to the current 802.11 1192 * operational state. Used to recover from various errors and 1193 * to reset or reload hardware state. 1194 */ 1195 int 1196 ath_reset(struct ifnet *ifp) 1197 { 1198 struct ath_softc *sc = ifp->if_softc; 1199 struct ieee80211com *ic = &sc->sc_ic; 1200 struct ath_hal *ah = sc->sc_ah; 1201 struct ieee80211_channel *c; 1202 HAL_STATUS status; 1203 1204 /* 1205 * Convert to a HAL channel description with the flags 1206 * constrained to reflect the current operating mode. 1207 */ 1208 c = ic->ic_curchan; 1209 sc->sc_curchan.channel = c->ic_freq; 1210 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1211 1212 ath_hal_intrset(ah, 0); /* disable interrupts */ 1213 ath_draintxq(sc); /* stop xmit side */ 1214 ath_stoprecv(sc); /* stop recv side */ 1215 /* NB: indicate channel change so we do a full reset */ 1216 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1217 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1218 __func__, status); 1219 ath_update_txpow(sc); /* update tx power state */ 1220 sc->sc_diversity = ath_hal_getdiversity(ah); 1221 sc->sc_calinterval = 1; 1222 sc->sc_caltries = 0; 1223 if (ath_startrecv(sc) != 0) /* restart recv */ 1224 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1225 /* 1226 * We may be doing a reset in response to an ioctl 1227 * that changes the channel so update any state that 1228 * might change as a result. 1229 */ 1230 ath_chan_change(sc, c); 1231 if (ic->ic_state == IEEE80211_S_RUN) 1232 ath_beacon_config(sc); /* restart beacons */ 1233 ath_hal_intrset(ah, sc->sc_imask); 1234 1235 ath_start(ifp); /* restart xmit */ 1236 return 0; 1237 } 1238 1239 static void 1240 ath_start(struct ifnet *ifp) 1241 { 1242 struct ath_softc *sc = ifp->if_softc; 1243 struct ath_hal *ah = sc->sc_ah; 1244 struct ieee80211com *ic = &sc->sc_ic; 1245 struct ieee80211_node *ni; 1246 struct ath_buf *bf; 1247 struct mbuf *m; 1248 struct ieee80211_frame *wh; 1249 struct ether_header *eh; 1250 1251 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1252 return; 1253 for (;;) { 1254 /* 1255 * Grab a TX buffer and associated resources. 1256 */ 1257 ATH_TXBUF_LOCK(sc); 1258 bf = STAILQ_FIRST(&sc->sc_txbuf); 1259 if (bf != NULL) 1260 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1261 ATH_TXBUF_UNLOCK(sc); 1262 if (bf == NULL) { 1263 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1264 __func__); 1265 sc->sc_stats.ast_tx_qstop++; 1266 ifp->if_flags |= IFF_OACTIVE; 1267 break; 1268 } 1269 /* 1270 * Poll the management queue for frames; they 1271 * have priority over normal data frames. 1272 */ 1273 IF_DEQUEUE(&ic->ic_mgtq, m); 1274 if (m == NULL) { 1275 /* 1276 * No data frames go out unless we're associated. 1277 */ 1278 if (ic->ic_state != IEEE80211_S_RUN) { 1279 DPRINTF(sc, ATH_DEBUG_XMIT, 1280 "%s: discard data packet, state %s\n", 1281 __func__, 1282 ieee80211_state_name[ic->ic_state]); 1283 sc->sc_stats.ast_tx_discard++; 1284 ATH_TXBUF_LOCK(sc); 1285 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1286 ATH_TXBUF_UNLOCK(sc); 1287 break; 1288 } 1289 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1290 if (m == NULL) { 1291 ATH_TXBUF_LOCK(sc); 1292 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1293 ATH_TXBUF_UNLOCK(sc); 1294 break; 1295 } 1296 /* 1297 * Find the node for the destination so we can do 1298 * things like power save and fast frames aggregation. 1299 */ 1300 if (m->m_len < sizeof(struct ether_header) && 1301 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1302 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1303 ni = NULL; 1304 goto bad; 1305 } 1306 eh = mtod(m, struct ether_header *); 1307 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1308 if (ni == NULL) { 1309 /* NB: ieee80211_find_txnode does stat+msg */ 1310 m_freem(m); 1311 goto bad; 1312 } 1313 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1314 (m->m_flags & M_PWR_SAV) == 0) { 1315 /* 1316 * Station in power save mode; pass the frame 1317 * to the 802.11 layer and continue. We'll get 1318 * the frame back when the time is right. 1319 */ 1320 ieee80211_pwrsave(ic, ni, m); 1321 goto reclaim; 1322 } 1323 /* calculate priority so we can find the tx queue */ 1324 if (ieee80211_classify(ic, m, ni)) { 1325 DPRINTF(sc, ATH_DEBUG_XMIT, 1326 "%s: discard, classification failure\n", 1327 __func__); 1328 m_freem(m); 1329 goto bad; 1330 } 1331 ifp->if_opackets++; 1332 1333 #if NBPFILTER > 0 1334 if (ifp->if_bpf) 1335 bpf_mtap(ifp->if_bpf, m); 1336 #endif 1337 /* 1338 * Encapsulate the packet in prep for transmission. 1339 */ 1340 m = ieee80211_encap(ic, m, ni); 1341 if (m == NULL) { 1342 DPRINTF(sc, ATH_DEBUG_XMIT, 1343 "%s: encapsulation failure\n", 1344 __func__); 1345 sc->sc_stats.ast_tx_encap++; 1346 goto bad; 1347 } 1348 } else { 1349 /* 1350 * Hack! The referenced node pointer is in the 1351 * rcvif field of the packet header. This is 1352 * placed there by ieee80211_mgmt_output because 1353 * we need to hold the reference with the frame 1354 * and there's no other way (other than packet 1355 * tags which we consider too expensive to use) 1356 * to pass it along. 1357 */ 1358 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1359 m->m_pkthdr.rcvif = NULL; 1360 1361 wh = mtod(m, struct ieee80211_frame *); 1362 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1363 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1364 /* fill time stamp */ 1365 u_int64_t tsf; 1366 u_int32_t *tstamp; 1367 1368 tsf = ath_hal_gettsf64(ah); 1369 /* XXX: adjust 100us delay to xmit */ 1370 tsf += 100; 1371 tstamp = (u_int32_t *)&wh[1]; 1372 tstamp[0] = htole32(tsf & 0xffffffff); 1373 tstamp[1] = htole32(tsf >> 32); 1374 } 1375 sc->sc_stats.ast_tx_mgmt++; 1376 } 1377 1378 if (ath_tx_start(sc, ni, bf, m)) { 1379 bad: 1380 ifp->if_oerrors++; 1381 reclaim: 1382 ATH_TXBUF_LOCK(sc); 1383 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1384 ATH_TXBUF_UNLOCK(sc); 1385 if (ni != NULL) 1386 ieee80211_free_node(ni); 1387 continue; 1388 } 1389 1390 sc->sc_tx_timer = 5; 1391 ifp->if_timer = 1; 1392 } 1393 } 1394 1395 static int 1396 ath_media_change(struct ifnet *ifp) 1397 { 1398 #define IS_UP(ifp) \ 1399 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1400 int error; 1401 1402 error = ieee80211_media_change(ifp); 1403 if (error == ENETRESET) { 1404 if (IS_UP(ifp)) 1405 ath_init(ifp->if_softc); /* XXX lose error */ 1406 error = 0; 1407 } 1408 return error; 1409 #undef IS_UP 1410 } 1411 1412 #ifdef AR_DEBUG 1413 static void 1414 ath_keyprint(const char *tag, u_int ix, 1415 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1416 { 1417 static const char *ciphers[] = { 1418 "WEP", 1419 "AES-OCB", 1420 "AES-CCM", 1421 "CKIP", 1422 "TKIP", 1423 "CLR", 1424 }; 1425 int i, n; 1426 1427 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1428 for (i = 0, n = hk->kv_len; i < n; i++) 1429 printf("%02x", hk->kv_val[i]); 1430 printf(" mac %s", ether_sprintf(mac)); 1431 if (hk->kv_type == HAL_CIPHER_TKIP) { 1432 printf(" mic "); 1433 for (i = 0; i < sizeof(hk->kv_mic); i++) 1434 printf("%02x", hk->kv_mic[i]); 1435 } 1436 printf("\n"); 1437 } 1438 #endif 1439 1440 /* 1441 * Set a TKIP key into the hardware. This handles the 1442 * potential distribution of key state to multiple key 1443 * cache slots for TKIP. 1444 */ 1445 static int 1446 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1447 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1448 { 1449 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1450 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1451 struct ath_hal *ah = sc->sc_ah; 1452 1453 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1454 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1455 KASSERT(sc->sc_splitmic, ("key cache !split")); 1456 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1457 /* 1458 * TX key goes at first index, RX key at the rx index. 1459 * The hal handles the MIC keys at index+64. 1460 */ 1461 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1462 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1463 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1464 return 0; 1465 1466 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1467 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1468 /* XXX delete tx key on failure? */ 1469 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1470 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1471 /* 1472 * TX/RX key goes at first index. 1473 * The hal handles the MIC keys are index+64. 1474 */ 1475 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1476 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1477 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1478 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1479 } 1480 return 0; 1481 #undef IEEE80211_KEY_XR 1482 } 1483 1484 /* 1485 * Set a net80211 key into the hardware. This handles the 1486 * potential distribution of key state to multiple key 1487 * cache slots for TKIP with hardware MIC support. 1488 */ 1489 static int 1490 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1491 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1492 struct ieee80211_node *bss) 1493 { 1494 #define N(a) (sizeof(a)/sizeof(a[0])) 1495 static const u_int8_t ciphermap[] = { 1496 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1497 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1498 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1499 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1500 (u_int8_t) -1, /* 4 is not allocated */ 1501 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1502 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1503 }; 1504 struct ath_hal *ah = sc->sc_ah; 1505 const struct ieee80211_cipher *cip = k->wk_cipher; 1506 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1507 const u_int8_t *mac; 1508 HAL_KEYVAL hk; 1509 1510 memset(&hk, 0, sizeof(hk)); 1511 /* 1512 * Software crypto uses a "clear key" so non-crypto 1513 * state kept in the key cache are maintained and 1514 * so that rx frames have an entry to match. 1515 */ 1516 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1517 KASSERT(cip->ic_cipher < N(ciphermap), 1518 ("invalid cipher type %u", cip->ic_cipher)); 1519 hk.kv_type = ciphermap[cip->ic_cipher]; 1520 hk.kv_len = k->wk_keylen; 1521 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1522 } else 1523 hk.kv_type = HAL_CIPHER_CLR; 1524 1525 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1526 /* 1527 * Group keys on hardware that supports multicast frame 1528 * key search use a mac that is the sender's address with 1529 * the high bit set instead of the app-specified address. 1530 */ 1531 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1532 gmac[0] |= 0x80; 1533 mac = gmac; 1534 } else 1535 mac = mac0; 1536 1537 if (hk.kv_type == HAL_CIPHER_TKIP && 1538 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1539 sc->sc_splitmic) { 1540 return ath_keyset_tkip(sc, k, &hk, mac); 1541 } else { 1542 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1543 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1544 } 1545 #undef N 1546 } 1547 1548 /* 1549 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1550 * each key, one for decrypt/encrypt and the other for the MIC. 1551 */ 1552 static u_int16_t 1553 key_alloc_2pair(struct ath_softc *sc, 1554 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1555 { 1556 #define N(a) (sizeof(a)/sizeof(a[0])) 1557 u_int i, keyix; 1558 1559 KASSERT(sc->sc_splitmic, ("key cache !split")); 1560 /* XXX could optimize */ 1561 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1562 u_int8_t b = sc->sc_keymap[i]; 1563 if (b != 0xff) { 1564 /* 1565 * One or more slots in this byte are free. 1566 */ 1567 keyix = i*NBBY; 1568 while (b & 1) { 1569 again: 1570 keyix++; 1571 b >>= 1; 1572 } 1573 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1574 if (isset(sc->sc_keymap, keyix+32) || 1575 isset(sc->sc_keymap, keyix+64) || 1576 isset(sc->sc_keymap, keyix+32+64)) { 1577 /* full pair unavailable */ 1578 /* XXX statistic */ 1579 if (keyix == (i+1)*NBBY) { 1580 /* no slots were appropriate, advance */ 1581 continue; 1582 } 1583 goto again; 1584 } 1585 setbit(sc->sc_keymap, keyix); 1586 setbit(sc->sc_keymap, keyix+64); 1587 setbit(sc->sc_keymap, keyix+32); 1588 setbit(sc->sc_keymap, keyix+32+64); 1589 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1590 "%s: key pair %u,%u %u,%u\n", 1591 __func__, keyix, keyix+64, 1592 keyix+32, keyix+32+64); 1593 *txkeyix = keyix; 1594 *rxkeyix = keyix+32; 1595 return 1; 1596 } 1597 } 1598 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1599 return 0; 1600 #undef N 1601 } 1602 1603 /* 1604 * Allocate a single key cache slot. 1605 */ 1606 static int 1607 key_alloc_single(struct ath_softc *sc, 1608 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1609 { 1610 #define N(a) (sizeof(a)/sizeof(a[0])) 1611 u_int i, keyix; 1612 1613 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1614 for (i = 0; i < N(sc->sc_keymap); i++) { 1615 u_int8_t b = sc->sc_keymap[i]; 1616 if (b != 0xff) { 1617 /* 1618 * One or more slots are free. 1619 */ 1620 keyix = i*NBBY; 1621 while (b & 1) 1622 keyix++, b >>= 1; 1623 setbit(sc->sc_keymap, keyix); 1624 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1625 __func__, keyix); 1626 *txkeyix = *rxkeyix = keyix; 1627 return 1; 1628 } 1629 } 1630 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1631 return 0; 1632 #undef N 1633 } 1634 1635 /* 1636 * Allocate one or more key cache slots for a uniacst key. The 1637 * key itself is needed only to identify the cipher. For hardware 1638 * TKIP with split cipher+MIC keys we allocate two key cache slot 1639 * pairs so that we can setup separate TX and RX MIC keys. Note 1640 * that the MIC key for a TKIP key at slot i is assumed by the 1641 * hardware to be at slot i+64. This limits TKIP keys to the first 1642 * 64 entries. 1643 */ 1644 static int 1645 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1646 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1647 { 1648 struct ath_softc *sc = ic->ic_ifp->if_softc; 1649 1650 /* 1651 * Group key allocation must be handled specially for 1652 * parts that do not support multicast key cache search 1653 * functionality. For those parts the key id must match 1654 * the h/w key index so lookups find the right key. On 1655 * parts w/ the key search facility we install the sender's 1656 * mac address (with the high bit set) and let the hardware 1657 * find the key w/o using the key id. This is preferred as 1658 * it permits us to support multiple users for adhoc and/or 1659 * multi-station operation. 1660 */ 1661 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1662 if (!(&ic->ic_nw_keys[0] <= k && 1663 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1664 /* should not happen */ 1665 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1666 "%s: bogus group key\n", __func__); 1667 return 0; 1668 } 1669 /* 1670 * XXX we pre-allocate the global keys so 1671 * have no way to check if they've already been allocated. 1672 */ 1673 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1674 return 1; 1675 } 1676 1677 /* 1678 * We allocate two pair for TKIP when using the h/w to do 1679 * the MIC. For everything else, including software crypto, 1680 * we allocate a single entry. Note that s/w crypto requires 1681 * a pass-through slot on the 5211 and 5212. The 5210 does 1682 * not support pass-through cache entries and we map all 1683 * those requests to slot 0. 1684 */ 1685 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1686 return key_alloc_single(sc, keyix, rxkeyix); 1687 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1688 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1689 return key_alloc_2pair(sc, keyix, rxkeyix); 1690 } else { 1691 return key_alloc_single(sc, keyix, rxkeyix); 1692 } 1693 } 1694 1695 /* 1696 * Delete an entry in the key cache allocated by ath_key_alloc. 1697 */ 1698 static int 1699 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1700 { 1701 struct ath_softc *sc = ic->ic_ifp->if_softc; 1702 struct ath_hal *ah = sc->sc_ah; 1703 const struct ieee80211_cipher *cip = k->wk_cipher; 1704 u_int keyix = k->wk_keyix; 1705 1706 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1707 1708 ath_hal_keyreset(ah, keyix); 1709 /* 1710 * Handle split tx/rx keying required for TKIP with h/w MIC. 1711 */ 1712 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1713 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1714 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1715 if (keyix >= IEEE80211_WEP_NKID) { 1716 /* 1717 * Don't touch keymap entries for global keys so 1718 * they are never considered for dynamic allocation. 1719 */ 1720 clrbit(sc->sc_keymap, keyix); 1721 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1722 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1723 sc->sc_splitmic) { 1724 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1725 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1726 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1727 } 1728 } 1729 return 1; 1730 } 1731 1732 /* 1733 * Set the key cache contents for the specified key. Key cache 1734 * slot(s) must already have been allocated by ath_key_alloc. 1735 */ 1736 static int 1737 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1738 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1739 { 1740 struct ath_softc *sc = ic->ic_ifp->if_softc; 1741 1742 return ath_keyset(sc, k, mac, ic->ic_bss); 1743 } 1744 1745 /* 1746 * Block/unblock tx+rx processing while a key change is done. 1747 * We assume the caller serializes key management operations 1748 * so we only need to worry about synchronization with other 1749 * uses that originate in the driver. 1750 */ 1751 static void 1752 ath_key_update_begin(struct ieee80211com *ic) 1753 { 1754 struct ifnet *ifp = ic->ic_ifp; 1755 struct ath_softc *sc = ifp->if_softc; 1756 1757 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1758 #if 0 1759 tasklet_disable(&sc->sc_rxtq); 1760 #endif 1761 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1762 } 1763 1764 static void 1765 ath_key_update_end(struct ieee80211com *ic) 1766 { 1767 struct ifnet *ifp = ic->ic_ifp; 1768 struct ath_softc *sc = ifp->if_softc; 1769 1770 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1771 IF_UNLOCK(&ifp->if_snd); 1772 #if 0 1773 tasklet_enable(&sc->sc_rxtq); 1774 #endif 1775 } 1776 1777 /* 1778 * Calculate the receive filter according to the 1779 * operating mode and state: 1780 * 1781 * o always accept unicast, broadcast, and multicast traffic 1782 * o maintain current state of phy error reception (the hal 1783 * may enable phy error frames for noise immunity work) 1784 * o probe request frames are accepted only when operating in 1785 * hostap, adhoc, or monitor modes 1786 * o enable promiscuous mode according to the interface state 1787 * o accept beacons: 1788 * - when operating in adhoc mode so the 802.11 layer creates 1789 * node table entries for peers, 1790 * - when operating in station mode for collecting rssi data when 1791 * the station is otherwise quiet, or 1792 * - when scanning 1793 */ 1794 static u_int32_t 1795 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1796 { 1797 struct ieee80211com *ic = &sc->sc_ic; 1798 struct ath_hal *ah = sc->sc_ah; 1799 struct ifnet *ifp = &sc->sc_if; 1800 u_int32_t rfilt; 1801 1802 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1803 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1804 if (ic->ic_opmode != IEEE80211_M_STA) 1805 rfilt |= HAL_RX_FILTER_PROBEREQ; 1806 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1807 (ifp->if_flags & IFF_PROMISC)) 1808 rfilt |= HAL_RX_FILTER_PROM; 1809 if (ic->ic_opmode == IEEE80211_M_STA || 1810 ic->ic_opmode == IEEE80211_M_IBSS || 1811 state == IEEE80211_S_SCAN) 1812 rfilt |= HAL_RX_FILTER_BEACON; 1813 return rfilt; 1814 } 1815 1816 static void 1817 ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1818 { 1819 u_int32_t val; 1820 u_int8_t pos; 1821 1822 /* calculate XOR of eight 6bit values */ 1823 val = LE_READ_4(dl + 0); 1824 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1825 val = LE_READ_4(dl + 3); 1826 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1827 pos &= 0x3f; 1828 mfilt[pos / 32] |= (1 << (pos % 32)); 1829 } 1830 1831 static void 1832 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1833 { 1834 struct ifnet *ifp = &sc->sc_if; 1835 struct ether_multi *enm; 1836 struct ether_multistep estep; 1837 1838 mfilt[0] = mfilt[1] = 0; 1839 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1840 while (enm != NULL) { 1841 /* XXX Punt on ranges. */ 1842 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1843 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1844 ifp->if_flags |= IFF_ALLMULTI; 1845 return; 1846 } 1847 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1848 ETHER_NEXT_MULTI(estep, enm); 1849 } 1850 ifp->if_flags &= ~IFF_ALLMULTI; 1851 } 1852 1853 static void 1854 ath_mode_init(struct ath_softc *sc) 1855 { 1856 struct ieee80211com *ic = &sc->sc_ic; 1857 struct ath_hal *ah = sc->sc_ah; 1858 u_int32_t rfilt, mfilt[2]; 1859 int i; 1860 1861 /* configure rx filter */ 1862 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1863 ath_hal_setrxfilter(ah, rfilt); 1864 1865 /* configure operational mode */ 1866 ath_hal_setopmode(ah); 1867 1868 /* Write keys to hardware; it may have been powered down. */ 1869 ath_key_update_begin(ic); 1870 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1871 ath_key_set(ic, 1872 &ic->ic_crypto.cs_nw_keys[i], 1873 ic->ic_myaddr); 1874 } 1875 ath_key_update_end(ic); 1876 1877 /* 1878 * Handle any link-level address change. Note that we only 1879 * need to force ic_myaddr; any other addresses are handled 1880 * as a byproduct of the ifnet code marking the interface 1881 * down then up. 1882 * 1883 * XXX should get from lladdr instead of arpcom but that's more work 1884 */ 1885 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1886 ath_hal_setmac(ah, ic->ic_myaddr); 1887 1888 /* calculate and install multicast filter */ 1889 #ifdef __FreeBSD__ 1890 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1891 mfilt[0] = mfilt[1] = 0; 1892 IF_ADDR_LOCK(ifp); 1893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1894 caddr_t dl; 1895 1896 /* calculate XOR of eight 6bit values */ 1897 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1898 val = LE_READ_4(dl + 0); 1899 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1900 val = LE_READ_4(dl + 3); 1901 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1902 pos &= 0x3f; 1903 mfilt[pos / 32] |= (1 << (pos % 32)); 1904 } 1905 IF_ADDR_UNLOCK(ifp); 1906 } else { 1907 mfilt[0] = mfilt[1] = ~0; 1908 } 1909 #endif 1910 #ifdef __NetBSD__ 1911 ath_mcastfilter_compute(sc, mfilt); 1912 #endif 1913 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1914 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1915 __func__, rfilt, mfilt[0], mfilt[1]); 1916 } 1917 1918 /* 1919 * Set the slot time based on the current setting. 1920 */ 1921 static void 1922 ath_setslottime(struct ath_softc *sc) 1923 { 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 struct ath_hal *ah = sc->sc_ah; 1926 1927 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1928 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1929 else 1930 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1931 sc->sc_updateslot = OK; 1932 } 1933 1934 /* 1935 * Callback from the 802.11 layer to update the 1936 * slot time based on the current setting. 1937 */ 1938 static void 1939 ath_updateslot(struct ifnet *ifp) 1940 { 1941 struct ath_softc *sc = ifp->if_softc; 1942 struct ieee80211com *ic = &sc->sc_ic; 1943 1944 /* 1945 * When not coordinating the BSS, change the hardware 1946 * immediately. For other operation we defer the change 1947 * until beacon updates have propagated to the stations. 1948 */ 1949 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1950 sc->sc_updateslot = UPDATE; 1951 else 1952 ath_setslottime(sc); 1953 } 1954 1955 /* 1956 * Setup a h/w transmit queue for beacons. 1957 */ 1958 static int 1959 ath_beaconq_setup(struct ath_hal *ah) 1960 { 1961 HAL_TXQ_INFO qi; 1962 1963 memset(&qi, 0, sizeof(qi)); 1964 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1965 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1966 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1967 /* NB: for dynamic turbo, don't enable any other interrupts */ 1968 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1969 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1970 } 1971 1972 /* 1973 * Setup the transmit queue parameters for the beacon queue. 1974 */ 1975 static int 1976 ath_beaconq_config(struct ath_softc *sc) 1977 { 1978 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1979 struct ieee80211com *ic = &sc->sc_ic; 1980 struct ath_hal *ah = sc->sc_ah; 1981 HAL_TXQ_INFO qi; 1982 1983 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1984 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1985 /* 1986 * Always burst out beacon and CAB traffic. 1987 */ 1988 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1989 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1990 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1991 } else { 1992 struct wmeParams *wmep = 1993 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1994 /* 1995 * Adhoc mode; important thing is to use 2x cwmin. 1996 */ 1997 qi.tqi_aifs = wmep->wmep_aifsn; 1998 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1999 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2000 } 2001 2002 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2003 device_printf(sc->sc_dev, "unable to update parameters for " 2004 "beacon hardware queue!\n"); 2005 return 0; 2006 } else { 2007 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2008 return 1; 2009 } 2010 #undef ATH_EXPONENT_TO_VALUE 2011 } 2012 2013 /* 2014 * Allocate and setup an initial beacon frame. 2015 */ 2016 static int 2017 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2018 { 2019 struct ieee80211com *ic = ni->ni_ic; 2020 struct ath_buf *bf; 2021 struct mbuf *m; 2022 int error; 2023 2024 bf = STAILQ_FIRST(&sc->sc_bbuf); 2025 if (bf == NULL) { 2026 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2027 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2028 return ENOMEM; /* XXX */ 2029 } 2030 /* 2031 * NB: the beacon data buffer must be 32-bit aligned; 2032 * we assume the mbuf routines will return us something 2033 * with this alignment (perhaps should assert). 2034 */ 2035 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2036 if (m == NULL) { 2037 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2038 __func__); 2039 sc->sc_stats.ast_be_nombuf++; 2040 return ENOMEM; 2041 } 2042 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2043 BUS_DMA_NOWAIT); 2044 if (error == 0) { 2045 bf->bf_m = m; 2046 bf->bf_node = ieee80211_ref_node(ni); 2047 } else { 2048 m_freem(m); 2049 } 2050 return error; 2051 } 2052 2053 /* 2054 * Setup the beacon frame for transmit. 2055 */ 2056 static void 2057 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2058 { 2059 #define USE_SHPREAMBLE(_ic) \ 2060 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2061 == IEEE80211_F_SHPREAMBLE) 2062 struct ieee80211_node *ni = bf->bf_node; 2063 struct ieee80211com *ic = ni->ni_ic; 2064 struct mbuf *m = bf->bf_m; 2065 struct ath_hal *ah = sc->sc_ah; 2066 struct ath_desc *ds; 2067 int flags, antenna; 2068 const HAL_RATE_TABLE *rt; 2069 u_int8_t rix, rate; 2070 2071 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2072 __func__, m, m->m_len); 2073 2074 /* setup descriptors */ 2075 ds = bf->bf_desc; 2076 2077 flags = HAL_TXDESC_NOACK; 2078 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2079 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2080 flags |= HAL_TXDESC_VEOL; 2081 /* 2082 * Let hardware handle antenna switching unless 2083 * the user has selected a transmit antenna 2084 * (sc_txantenna is not 0). 2085 */ 2086 antenna = sc->sc_txantenna; 2087 } else { 2088 ds->ds_link = 0; 2089 /* 2090 * Switch antenna every 4 beacons, unless the user 2091 * has selected a transmit antenna (sc_txantenna 2092 * is not 0). 2093 * 2094 * XXX assumes two antenna 2095 */ 2096 if (sc->sc_txantenna == 0) 2097 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2098 else 2099 antenna = sc->sc_txantenna; 2100 } 2101 2102 KASSERT(bf->bf_nseg == 1, 2103 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2104 ds->ds_data = bf->bf_segs[0].ds_addr; 2105 /* 2106 * Calculate rate code. 2107 * XXX everything at min xmit rate 2108 */ 2109 rix = sc->sc_minrateix; 2110 rt = sc->sc_currates; 2111 rate = rt->info[rix].rateCode; 2112 if (USE_SHPREAMBLE(ic)) 2113 rate |= rt->info[rix].shortPreamble; 2114 ath_hal_setuptxdesc(ah, ds 2115 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2116 , sizeof(struct ieee80211_frame)/* header length */ 2117 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2118 , ni->ni_txpower /* txpower XXX */ 2119 , rate, 1 /* series 0 rate/tries */ 2120 , HAL_TXKEYIX_INVALID /* no encryption */ 2121 , antenna /* antenna mode */ 2122 , flags /* no ack, veol for beacons */ 2123 , 0 /* rts/cts rate */ 2124 , 0 /* rts/cts duration */ 2125 ); 2126 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2127 ath_hal_filltxdesc(ah, ds 2128 , roundup(m->m_len, 4) /* buffer length */ 2129 , AH_TRUE /* first segment */ 2130 , AH_TRUE /* last segment */ 2131 , ds /* first descriptor */ 2132 ); 2133 2134 /* NB: The desc swap function becomes void, 2135 * if descriptor swapping is not enabled 2136 */ 2137 ath_desc_swap(ds); 2138 2139 #undef USE_SHPREAMBLE 2140 } 2141 2142 /* 2143 * Transmit a beacon frame at SWBA. Dynamic updates to the 2144 * frame contents are done as needed and the slot time is 2145 * also adjusted based on current state. 2146 */ 2147 static void 2148 ath_beacon_proc(void *arg, int pending) 2149 { 2150 struct ath_softc *sc = arg; 2151 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2152 struct ieee80211_node *ni = bf->bf_node; 2153 struct ieee80211com *ic = ni->ni_ic; 2154 struct ath_hal *ah = sc->sc_ah; 2155 struct mbuf *m; 2156 int ncabq, error, otherant; 2157 2158 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2159 __func__, pending); 2160 2161 if (ic->ic_opmode == IEEE80211_M_STA || 2162 ic->ic_opmode == IEEE80211_M_MONITOR || 2163 bf == NULL || bf->bf_m == NULL) { 2164 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2165 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2166 return; 2167 } 2168 /* 2169 * Check if the previous beacon has gone out. If 2170 * not don't try to post another, skip this period 2171 * and wait for the next. Missed beacons indicate 2172 * a problem and should not occur. If we miss too 2173 * many consecutive beacons reset the device. 2174 */ 2175 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2176 sc->sc_bmisscount++; 2177 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2178 "%s: missed %u consecutive beacons\n", 2179 __func__, sc->sc_bmisscount); 2180 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2181 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2182 return; 2183 } 2184 if (sc->sc_bmisscount != 0) { 2185 DPRINTF(sc, ATH_DEBUG_BEACON, 2186 "%s: resume beacon xmit after %u misses\n", 2187 __func__, sc->sc_bmisscount); 2188 sc->sc_bmisscount = 0; 2189 } 2190 2191 /* 2192 * Update dynamic beacon contents. If this returns 2193 * non-zero then we need to remap the memory because 2194 * the beacon frame changed size (probably because 2195 * of the TIM bitmap). 2196 */ 2197 m = bf->bf_m; 2198 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2199 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2200 /* XXX too conservative? */ 2201 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2202 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2203 BUS_DMA_NOWAIT); 2204 if (error != 0) { 2205 if_printf(&sc->sc_if, 2206 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2207 __func__, error); 2208 return; 2209 } 2210 } 2211 2212 /* 2213 * Handle slot time change when a non-ERP station joins/leaves 2214 * an 11g network. The 802.11 layer notifies us via callback, 2215 * we mark updateslot, then wait one beacon before effecting 2216 * the change. This gives associated stations at least one 2217 * beacon interval to note the state change. 2218 */ 2219 /* XXX locking */ 2220 if (sc->sc_updateslot == UPDATE) 2221 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2222 else if (sc->sc_updateslot == COMMIT) 2223 ath_setslottime(sc); /* commit change to h/w */ 2224 2225 /* 2226 * Check recent per-antenna transmit statistics and flip 2227 * the default antenna if noticeably more frames went out 2228 * on the non-default antenna. 2229 * XXX assumes 2 anntenae 2230 */ 2231 otherant = sc->sc_defant & 1 ? 2 : 1; 2232 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2233 ath_setdefantenna(sc, otherant); 2234 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2235 2236 /* 2237 * Construct tx descriptor. 2238 */ 2239 ath_beacon_setup(sc, bf); 2240 2241 /* 2242 * Stop any current dma and put the new frame on the queue. 2243 * This should never fail since we check above that no frames 2244 * are still pending on the queue. 2245 */ 2246 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2247 DPRINTF(sc, ATH_DEBUG_ANY, 2248 "%s: beacon queue %u did not stop?\n", 2249 __func__, sc->sc_bhalq); 2250 } 2251 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2252 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2253 2254 /* 2255 * Enable the CAB queue before the beacon queue to 2256 * insure cab frames are triggered by this beacon. 2257 */ 2258 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2259 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2260 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2261 ath_hal_txstart(ah, sc->sc_bhalq); 2262 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2263 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2264 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2265 2266 sc->sc_stats.ast_be_xmit++; 2267 } 2268 2269 /* 2270 * Reset the hardware after detecting beacons have stopped. 2271 */ 2272 static void 2273 ath_bstuck_proc(void *arg, int pending) 2274 { 2275 struct ath_softc *sc = arg; 2276 struct ifnet *ifp = &sc->sc_if; 2277 2278 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2279 sc->sc_bmisscount); 2280 ath_reset(ifp); 2281 } 2282 2283 /* 2284 * Reclaim beacon resources. 2285 */ 2286 static void 2287 ath_beacon_free(struct ath_softc *sc) 2288 { 2289 struct ath_buf *bf; 2290 2291 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2292 if (bf->bf_m != NULL) { 2293 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2294 m_freem(bf->bf_m); 2295 bf->bf_m = NULL; 2296 } 2297 if (bf->bf_node != NULL) { 2298 ieee80211_free_node(bf->bf_node); 2299 bf->bf_node = NULL; 2300 } 2301 } 2302 } 2303 2304 /* 2305 * Configure the beacon and sleep timers. 2306 * 2307 * When operating as an AP this resets the TSF and sets 2308 * up the hardware to notify us when we need to issue beacons. 2309 * 2310 * When operating in station mode this sets up the beacon 2311 * timers according to the timestamp of the last received 2312 * beacon and the current TSF, configures PCF and DTIM 2313 * handling, programs the sleep registers so the hardware 2314 * will wakeup in time to receive beacons, and configures 2315 * the beacon miss handling so we'll receive a BMISS 2316 * interrupt when we stop seeing beacons from the AP 2317 * we've associated with. 2318 */ 2319 static void 2320 ath_beacon_config(struct ath_softc *sc) 2321 { 2322 #define TSF_TO_TU(_h,_l) \ 2323 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2324 #define FUDGE 2 2325 struct ath_hal *ah = sc->sc_ah; 2326 struct ieee80211com *ic = &sc->sc_ic; 2327 struct ieee80211_node *ni = ic->ic_bss; 2328 u_int32_t nexttbtt, intval, tsftu; 2329 u_int64_t tsf; 2330 2331 /* extract tstamp from last beacon and convert to TU */ 2332 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2333 LE_READ_4(ni->ni_tstamp.data)); 2334 /* NB: the beacon interval is kept internally in TU's */ 2335 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2336 if (nexttbtt == 0) /* e.g. for ap mode */ 2337 nexttbtt = intval; 2338 else if (intval) /* NB: can be 0 for monitor mode */ 2339 nexttbtt = roundup(nexttbtt, intval); 2340 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2341 __func__, nexttbtt, intval, ni->ni_intval); 2342 if (ic->ic_opmode == IEEE80211_M_STA) { 2343 HAL_BEACON_STATE bs; 2344 int dtimperiod, dtimcount; 2345 int cfpperiod, cfpcount; 2346 2347 /* 2348 * Setup dtim and cfp parameters according to 2349 * last beacon we received (which may be none). 2350 */ 2351 dtimperiod = ni->ni_dtim_period; 2352 if (dtimperiod <= 0) /* NB: 0 if not known */ 2353 dtimperiod = 1; 2354 dtimcount = ni->ni_dtim_count; 2355 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2356 dtimcount = 0; /* XXX? */ 2357 cfpperiod = 1; /* NB: no PCF support yet */ 2358 cfpcount = 0; 2359 /* 2360 * Pull nexttbtt forward to reflect the current 2361 * TSF and calculate dtim+cfp state for the result. 2362 */ 2363 tsf = ath_hal_gettsf64(ah); 2364 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2365 do { 2366 nexttbtt += intval; 2367 if (--dtimcount < 0) { 2368 dtimcount = dtimperiod - 1; 2369 if (--cfpcount < 0) 2370 cfpcount = cfpperiod - 1; 2371 } 2372 } while (nexttbtt < tsftu); 2373 memset(&bs, 0, sizeof(bs)); 2374 bs.bs_intval = intval; 2375 bs.bs_nexttbtt = nexttbtt; 2376 bs.bs_dtimperiod = dtimperiod*intval; 2377 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2378 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2379 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2380 bs.bs_cfpmaxduration = 0; 2381 #if 0 2382 /* 2383 * The 802.11 layer records the offset to the DTIM 2384 * bitmap while receiving beacons; use it here to 2385 * enable h/w detection of our AID being marked in 2386 * the bitmap vector (to indicate frames for us are 2387 * pending at the AP). 2388 * XXX do DTIM handling in s/w to WAR old h/w bugs 2389 * XXX enable based on h/w rev for newer chips 2390 */ 2391 bs.bs_timoffset = ni->ni_timoff; 2392 #endif 2393 /* 2394 * Calculate the number of consecutive beacons to miss 2395 * before taking a BMISS interrupt. The configuration 2396 * is specified in ms, so we need to convert that to 2397 * TU's and then calculate based on the beacon interval. 2398 * Note that we clamp the result to at most 10 beacons. 2399 */ 2400 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2401 if (bs.bs_bmissthreshold > 10) 2402 bs.bs_bmissthreshold = 10; 2403 else if (bs.bs_bmissthreshold <= 0) 2404 bs.bs_bmissthreshold = 1; 2405 2406 /* 2407 * Calculate sleep duration. The configuration is 2408 * given in ms. We insure a multiple of the beacon 2409 * period is used. Also, if the sleep duration is 2410 * greater than the DTIM period then it makes senses 2411 * to make it a multiple of that. 2412 * 2413 * XXX fixed at 100ms 2414 */ 2415 bs.bs_sleepduration = 2416 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2417 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2418 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2419 2420 DPRINTF(sc, ATH_DEBUG_BEACON, 2421 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2422 , __func__ 2423 , tsf, tsftu 2424 , bs.bs_intval 2425 , bs.bs_nexttbtt 2426 , bs.bs_dtimperiod 2427 , bs.bs_nextdtim 2428 , bs.bs_bmissthreshold 2429 , bs.bs_sleepduration 2430 , bs.bs_cfpperiod 2431 , bs.bs_cfpmaxduration 2432 , bs.bs_cfpnext 2433 , bs.bs_timoffset 2434 ); 2435 ath_hal_intrset(ah, 0); 2436 ath_hal_beacontimers(ah, &bs); 2437 sc->sc_imask |= HAL_INT_BMISS; 2438 ath_hal_intrset(ah, sc->sc_imask); 2439 } else { 2440 ath_hal_intrset(ah, 0); 2441 if (nexttbtt == intval) 2442 intval |= HAL_BEACON_RESET_TSF; 2443 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2444 /* 2445 * In IBSS mode enable the beacon timers but only 2446 * enable SWBA interrupts if we need to manually 2447 * prepare beacon frames. Otherwise we use a 2448 * self-linked tx descriptor and let the hardware 2449 * deal with things. 2450 */ 2451 intval |= HAL_BEACON_ENA; 2452 if (!sc->sc_hasveol) 2453 sc->sc_imask |= HAL_INT_SWBA; 2454 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2455 /* 2456 * Pull nexttbtt forward to reflect 2457 * the current TSF. 2458 */ 2459 tsf = ath_hal_gettsf64(ah); 2460 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2461 do { 2462 nexttbtt += intval; 2463 } while (nexttbtt < tsftu); 2464 } 2465 ath_beaconq_config(sc); 2466 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2467 /* 2468 * In AP mode we enable the beacon timers and 2469 * SWBA interrupts to prepare beacon frames. 2470 */ 2471 intval |= HAL_BEACON_ENA; 2472 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2473 ath_beaconq_config(sc); 2474 } 2475 ath_hal_beaconinit(ah, nexttbtt, intval); 2476 sc->sc_bmisscount = 0; 2477 ath_hal_intrset(ah, sc->sc_imask); 2478 /* 2479 * When using a self-linked beacon descriptor in 2480 * ibss mode load it once here. 2481 */ 2482 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2483 ath_beacon_proc(sc, 0); 2484 } 2485 sc->sc_syncbeacon = 0; 2486 #undef UNDEF 2487 #undef TSF_TO_TU 2488 } 2489 2490 static int 2491 ath_descdma_setup(struct ath_softc *sc, 2492 struct ath_descdma *dd, ath_bufhead *head, 2493 const char *name, int nbuf, int ndesc) 2494 { 2495 #define DS2PHYS(_dd, _ds) \ 2496 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2497 struct ifnet *ifp = &sc->sc_if; 2498 struct ath_desc *ds; 2499 struct ath_buf *bf; 2500 int i, bsize, error; 2501 2502 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2503 __func__, name, nbuf, ndesc); 2504 2505 dd->dd_name = name; 2506 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2507 2508 /* 2509 * Setup DMA descriptor area. 2510 */ 2511 dd->dd_dmat = sc->sc_dmat; 2512 2513 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2514 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2515 2516 if (error != 0) { 2517 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2518 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2519 goto fail0; 2520 } 2521 2522 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2523 dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2524 if (error != 0) { 2525 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2526 nbuf * ndesc, dd->dd_name, error); 2527 goto fail1; 2528 } 2529 2530 /* allocate descriptors */ 2531 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2532 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2533 if (error != 0) { 2534 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2535 "error %u\n", dd->dd_name, error); 2536 goto fail2; 2537 } 2538 2539 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2540 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2541 if (error != 0) { 2542 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2543 dd->dd_name, error); 2544 goto fail3; 2545 } 2546 2547 ds = dd->dd_desc; 2548 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2549 DPRINTF(sc, ATH_DEBUG_RESET, 2550 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2551 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2552 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2553 2554 /* allocate rx buffers */ 2555 bsize = sizeof(struct ath_buf) * nbuf; 2556 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2557 if (bf == NULL) { 2558 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2559 dd->dd_name, bsize); 2560 goto fail4; 2561 } 2562 dd->dd_bufptr = bf; 2563 2564 STAILQ_INIT(head); 2565 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2566 bf->bf_desc = ds; 2567 bf->bf_daddr = DS2PHYS(dd, ds); 2568 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2569 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2570 if (error != 0) { 2571 if_printf(ifp, "unable to create dmamap for %s " 2572 "buffer %u, error %u\n", dd->dd_name, i, error); 2573 ath_descdma_cleanup(sc, dd, head); 2574 return error; 2575 } 2576 STAILQ_INSERT_TAIL(head, bf, bf_list); 2577 } 2578 return 0; 2579 fail4: 2580 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2581 fail3: 2582 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2583 fail2: 2584 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2585 fail1: 2586 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2587 fail0: 2588 memset(dd, 0, sizeof(*dd)); 2589 return error; 2590 #undef DS2PHYS 2591 } 2592 2593 static void 2594 ath_descdma_cleanup(struct ath_softc *sc, 2595 struct ath_descdma *dd, ath_bufhead *head) 2596 { 2597 struct ath_buf *bf; 2598 struct ieee80211_node *ni; 2599 2600 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2601 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2602 bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2603 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2604 2605 STAILQ_FOREACH(bf, head, bf_list) { 2606 if (bf->bf_m) { 2607 m_freem(bf->bf_m); 2608 bf->bf_m = NULL; 2609 } 2610 if (bf->bf_dmamap != NULL) { 2611 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2612 bf->bf_dmamap = NULL; 2613 } 2614 ni = bf->bf_node; 2615 bf->bf_node = NULL; 2616 if (ni != NULL) { 2617 /* 2618 * Reclaim node reference. 2619 */ 2620 ieee80211_free_node(ni); 2621 } 2622 } 2623 2624 STAILQ_INIT(head); 2625 free(dd->dd_bufptr, M_ATHDEV); 2626 memset(dd, 0, sizeof(*dd)); 2627 } 2628 2629 static int 2630 ath_desc_alloc(struct ath_softc *sc) 2631 { 2632 int error; 2633 2634 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2635 "rx", ath_rxbuf, 1); 2636 if (error != 0) 2637 return error; 2638 2639 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2640 "tx", ath_txbuf, ATH_TXDESC); 2641 if (error != 0) { 2642 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2643 return error; 2644 } 2645 2646 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2647 "beacon", 1, 1); 2648 if (error != 0) { 2649 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2650 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2651 return error; 2652 } 2653 return 0; 2654 } 2655 2656 static void 2657 ath_desc_free(struct ath_softc *sc) 2658 { 2659 2660 if (sc->sc_bdma.dd_desc_len != 0) 2661 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2662 if (sc->sc_txdma.dd_desc_len != 0) 2663 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2664 if (sc->sc_rxdma.dd_desc_len != 0) 2665 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2666 } 2667 2668 static struct ieee80211_node * 2669 ath_node_alloc(struct ieee80211_node_table *nt) 2670 { 2671 struct ieee80211com *ic = nt->nt_ic; 2672 struct ath_softc *sc = ic->ic_ifp->if_softc; 2673 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2674 struct ath_node *an; 2675 2676 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2677 if (an == NULL) { 2678 /* XXX stat+msg */ 2679 return NULL; 2680 } 2681 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2682 ath_rate_node_init(sc, an); 2683 2684 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2685 return &an->an_node; 2686 } 2687 2688 static void 2689 ath_node_free(struct ieee80211_node *ni) 2690 { 2691 struct ieee80211com *ic = ni->ni_ic; 2692 struct ath_softc *sc = ic->ic_ifp->if_softc; 2693 2694 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2695 2696 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2697 sc->sc_node_free(ni); 2698 } 2699 2700 static u_int8_t 2701 ath_node_getrssi(const struct ieee80211_node *ni) 2702 { 2703 #define HAL_EP_RND(x, mul) \ 2704 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2705 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2706 int32_t rssi; 2707 2708 /* 2709 * When only one frame is received there will be no state in 2710 * avgrssi so fallback on the value recorded by the 802.11 layer. 2711 */ 2712 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2713 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2714 else 2715 rssi = ni->ni_rssi; 2716 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2717 #undef HAL_EP_RND 2718 } 2719 2720 static int 2721 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2722 { 2723 struct ath_hal *ah = sc->sc_ah; 2724 int error; 2725 struct mbuf *m; 2726 struct ath_desc *ds; 2727 2728 m = bf->bf_m; 2729 if (m == NULL) { 2730 /* 2731 * NB: by assigning a page to the rx dma buffer we 2732 * implicitly satisfy the Atheros requirement that 2733 * this buffer be cache-line-aligned and sized to be 2734 * multiple of the cache line size. Not doing this 2735 * causes weird stuff to happen (for the 5210 at least). 2736 */ 2737 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2738 if (m == NULL) { 2739 DPRINTF(sc, ATH_DEBUG_ANY, 2740 "%s: no mbuf/cluster\n", __func__); 2741 sc->sc_stats.ast_rx_nombuf++; 2742 return ENOMEM; 2743 } 2744 bf->bf_m = m; 2745 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2746 2747 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2748 bf->bf_dmamap, m, 2749 BUS_DMA_NOWAIT); 2750 if (error != 0) { 2751 DPRINTF(sc, ATH_DEBUG_ANY, 2752 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2753 __func__, error); 2754 sc->sc_stats.ast_rx_busdma++; 2755 return error; 2756 } 2757 KASSERT(bf->bf_nseg == 1, 2758 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2759 } 2760 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2761 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2762 2763 /* 2764 * Setup descriptors. For receive we always terminate 2765 * the descriptor list with a self-linked entry so we'll 2766 * not get overrun under high load (as can happen with a 2767 * 5212 when ANI processing enables PHY error frames). 2768 * 2769 * To insure the last descriptor is self-linked we create 2770 * each descriptor as self-linked and add it to the end. As 2771 * each additional descriptor is added the previous self-linked 2772 * entry is ``fixed'' naturally. This should be safe even 2773 * if DMA is happening. When processing RX interrupts we 2774 * never remove/process the last, self-linked, entry on the 2775 * descriptor list. This insures the hardware always has 2776 * someplace to write a new frame. 2777 */ 2778 ds = bf->bf_desc; 2779 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2780 ds->ds_data = bf->bf_segs[0].ds_addr; 2781 ds->ds_vdata = mtod(m, void *); /* for radar */ 2782 ath_hal_setuprxdesc(ah, ds 2783 , m->m_len /* buffer size */ 2784 , 0 2785 ); 2786 2787 if (sc->sc_rxlink != NULL) 2788 *sc->sc_rxlink = bf->bf_daddr; 2789 sc->sc_rxlink = &ds->ds_link; 2790 return 0; 2791 } 2792 2793 /* 2794 * Extend 15-bit time stamp from rx descriptor to 2795 * a full 64-bit TSF using the specified TSF. 2796 */ 2797 static inline u_int64_t 2798 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2799 { 2800 if ((tsf & 0x7fff) < rstamp) 2801 tsf -= 0x8000; 2802 return ((tsf &~ 0x7fff) | rstamp); 2803 } 2804 2805 /* 2806 * Intercept management frames to collect beacon rssi data 2807 * and to do ibss merges. 2808 */ 2809 static void 2810 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2811 struct ieee80211_node *ni, 2812 int subtype, int rssi, u_int32_t rstamp) 2813 { 2814 struct ath_softc *sc = ic->ic_ifp->if_softc; 2815 2816 /* 2817 * Call up first so subsequent work can use information 2818 * potentially stored in the node (e.g. for ibss merge). 2819 */ 2820 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2821 switch (subtype) { 2822 case IEEE80211_FC0_SUBTYPE_BEACON: 2823 /* update rssi statistics for use by the hal */ 2824 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2825 if (sc->sc_syncbeacon && 2826 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2827 /* 2828 * Resync beacon timers using the tsf of the beacon 2829 * frame we just received. 2830 */ 2831 ath_beacon_config(sc); 2832 } 2833 /* fall thru... */ 2834 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2835 if (ic->ic_opmode == IEEE80211_M_IBSS && 2836 ic->ic_state == IEEE80211_S_RUN) { 2837 u_int64_t tsf = ath_extend_tsf(rstamp, 2838 ath_hal_gettsf64(sc->sc_ah)); 2839 2840 /* 2841 * Handle ibss merge as needed; check the tsf on the 2842 * frame before attempting the merge. The 802.11 spec 2843 * says the station should change it's bssid to match 2844 * the oldest station with the same ssid, where oldest 2845 * is determined by the tsf. Note that hardware 2846 * reconfiguration happens through callback to 2847 * ath_newstate as the state machine will go from 2848 * RUN -> RUN when this happens. 2849 */ 2850 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2851 DPRINTF(sc, ATH_DEBUG_STATE, 2852 "ibss merge, rstamp %u tsf %ju " 2853 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2854 (uintmax_t)ni->ni_tstamp.tsf); 2855 (void) ieee80211_ibss_merge(ni); 2856 } 2857 } 2858 break; 2859 } 2860 } 2861 2862 /* 2863 * Set the default antenna. 2864 */ 2865 static void 2866 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2867 { 2868 struct ath_hal *ah = sc->sc_ah; 2869 2870 /* XXX block beacon interrupts */ 2871 ath_hal_setdefantenna(ah, antenna); 2872 if (sc->sc_defant != antenna) 2873 sc->sc_stats.ast_ant_defswitch++; 2874 sc->sc_defant = antenna; 2875 sc->sc_rxotherant = 0; 2876 } 2877 2878 static void 2879 ath_rx_proc(void *arg, int npending) 2880 { 2881 #define PA2DESC(_sc, _pa) \ 2882 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2883 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2884 struct ath_softc *sc = arg; 2885 struct ath_buf *bf; 2886 struct ieee80211com *ic = &sc->sc_ic; 2887 struct ifnet *ifp = &sc->sc_if; 2888 struct ath_hal *ah = sc->sc_ah; 2889 struct ath_desc *ds; 2890 struct mbuf *m; 2891 struct ieee80211_node *ni; 2892 struct ath_node *an; 2893 int len, type, ngood; 2894 u_int phyerr; 2895 HAL_STATUS status; 2896 int16_t nf; 2897 u_int64_t tsf; 2898 2899 NET_LOCK_GIANT(); /* XXX */ 2900 2901 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2902 ngood = 0; 2903 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2904 tsf = ath_hal_gettsf64(ah); 2905 do { 2906 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2907 if (bf == NULL) { /* NB: shouldn't happen */ 2908 if_printf(ifp, "%s: no buffer!\n", __func__); 2909 break; 2910 } 2911 ds = bf->bf_desc; 2912 if (ds->ds_link == bf->bf_daddr) { 2913 /* NB: never process the self-linked entry at the end */ 2914 break; 2915 } 2916 m = bf->bf_m; 2917 if (m == NULL) { /* NB: shouldn't happen */ 2918 if_printf(ifp, "%s: no mbuf!\n", __func__); 2919 break; 2920 } 2921 /* XXX sync descriptor memory */ 2922 /* 2923 * Must provide the virtual address of the current 2924 * descriptor, the physical address, and the virtual 2925 * address of the next descriptor in the h/w chain. 2926 * This allows the HAL to look ahead to see if the 2927 * hardware is done with a descriptor by checking the 2928 * done bit in the following descriptor and the address 2929 * of the current descriptor the DMA engine is working 2930 * on. All this is necessary because of our use of 2931 * a self-linked list to avoid rx overruns. 2932 */ 2933 status = ath_hal_rxprocdesc(ah, ds, 2934 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2935 #ifdef AR_DEBUG 2936 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2937 ath_printrxbuf(bf, status == HAL_OK); 2938 #endif 2939 if (status == HAL_EINPROGRESS) 2940 break; 2941 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2942 if (ds->ds_rxstat.rs_more) { 2943 /* 2944 * Frame spans multiple descriptors; this 2945 * cannot happen yet as we don't support 2946 * jumbograms. If not in monitor mode, 2947 * discard the frame. 2948 */ 2949 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2950 sc->sc_stats.ast_rx_toobig++; 2951 goto rx_next; 2952 } 2953 /* fall thru for monitor mode handling... */ 2954 } else if (ds->ds_rxstat.rs_status != 0) { 2955 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2956 sc->sc_stats.ast_rx_crcerr++; 2957 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2958 sc->sc_stats.ast_rx_fifoerr++; 2959 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2960 sc->sc_stats.ast_rx_phyerr++; 2961 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2962 sc->sc_stats.ast_rx_phy[phyerr]++; 2963 goto rx_next; 2964 } 2965 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2966 /* 2967 * Decrypt error. If the error occurred 2968 * because there was no hardware key, then 2969 * let the frame through so the upper layers 2970 * can process it. This is necessary for 5210 2971 * parts which have no way to setup a ``clear'' 2972 * key cache entry. 2973 * 2974 * XXX do key cache faulting 2975 */ 2976 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2977 goto rx_accept; 2978 sc->sc_stats.ast_rx_badcrypt++; 2979 } 2980 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2981 sc->sc_stats.ast_rx_badmic++; 2982 /* 2983 * Do minimal work required to hand off 2984 * the 802.11 header for notifcation. 2985 */ 2986 /* XXX frag's and qos frames */ 2987 len = ds->ds_rxstat.rs_datalen; 2988 if (len >= sizeof (struct ieee80211_frame)) { 2989 bus_dmamap_sync(sc->sc_dmat, 2990 bf->bf_dmamap, 2991 0, bf->bf_dmamap->dm_mapsize, 2992 BUS_DMASYNC_POSTREAD); 2993 ieee80211_notify_michael_failure(ic, 2994 mtod(m, struct ieee80211_frame *), 2995 sc->sc_splitmic ? 2996 ds->ds_rxstat.rs_keyix-32 : 2997 ds->ds_rxstat.rs_keyix 2998 ); 2999 } 3000 } 3001 ifp->if_ierrors++; 3002 /* 3003 * Reject error frames, we normally don't want 3004 * to see them in monitor mode (in monitor mode 3005 * allow through packets that have crypto problems). 3006 */ 3007 if ((ds->ds_rxstat.rs_status &~ 3008 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 3009 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 3010 goto rx_next; 3011 } 3012 rx_accept: 3013 /* 3014 * Sync and unmap the frame. At this point we're 3015 * committed to passing the mbuf somewhere so clear 3016 * bf_m; this means a new sk_buff must be allocated 3017 * when the rx descriptor is setup again to receive 3018 * another frame. 3019 */ 3020 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3021 0, bf->bf_dmamap->dm_mapsize, 3022 BUS_DMASYNC_POSTREAD); 3023 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3024 bf->bf_m = NULL; 3025 3026 m->m_pkthdr.rcvif = ifp; 3027 len = ds->ds_rxstat.rs_datalen; 3028 m->m_pkthdr.len = m->m_len = len; 3029 3030 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3031 3032 #if NBPFILTER > 0 3033 if (sc->sc_drvbpf) { 3034 u_int8_t rix; 3035 3036 /* 3037 * Discard anything shorter than an ack or cts. 3038 */ 3039 if (len < IEEE80211_ACK_LEN) { 3040 DPRINTF(sc, ATH_DEBUG_RECV, 3041 "%s: runt packet %d\n", 3042 __func__, len); 3043 sc->sc_stats.ast_rx_tooshort++; 3044 m_freem(m); 3045 goto rx_next; 3046 } 3047 rix = ds->ds_rxstat.rs_rate; 3048 sc->sc_rx_th.wr_tsf = htole64( 3049 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3050 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3051 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3052 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3053 sc->sc_rx_th.wr_antnoise = nf; 3054 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3055 3056 bpf_mtap2(sc->sc_drvbpf, 3057 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3058 } 3059 #endif 3060 3061 /* 3062 * From this point on we assume the frame is at least 3063 * as large as ieee80211_frame_min; verify that. 3064 */ 3065 if (len < IEEE80211_MIN_LEN) { 3066 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3067 __func__, len); 3068 sc->sc_stats.ast_rx_tooshort++; 3069 m_freem(m); 3070 goto rx_next; 3071 } 3072 3073 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3074 ieee80211_dump_pkt(mtod(m, caddr_t), len, 3075 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3076 ds->ds_rxstat.rs_rssi); 3077 } 3078 3079 m_adj(m, -IEEE80211_CRC_LEN); 3080 3081 /* 3082 * Locate the node for sender, track state, and then 3083 * pass the (referenced) node up to the 802.11 layer 3084 * for its use. 3085 */ 3086 ni = ieee80211_find_rxnode_withkey(ic, 3087 mtod(m, const struct ieee80211_frame_min *), 3088 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3089 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3090 /* 3091 * Track rx rssi and do any rx antenna management. 3092 */ 3093 an = ATH_NODE(ni); 3094 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3095 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3096 /* 3097 * Send frame up for processing. 3098 */ 3099 type = ieee80211_input(ic, m, ni, 3100 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3101 ieee80211_free_node(ni); 3102 if (sc->sc_diversity) { 3103 /* 3104 * When using fast diversity, change the default rx 3105 * antenna if diversity chooses the other antenna 3 3106 * times in a row. 3107 */ 3108 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3109 if (++sc->sc_rxotherant >= 3) 3110 ath_setdefantenna(sc, 3111 ds->ds_rxstat.rs_antenna); 3112 } else 3113 sc->sc_rxotherant = 0; 3114 } 3115 if (sc->sc_softled) { 3116 /* 3117 * Blink for any data frame. Otherwise do a 3118 * heartbeat-style blink when idle. The latter 3119 * is mainly for station mode where we depend on 3120 * periodic beacon frames to trigger the poll event. 3121 */ 3122 if (type == IEEE80211_FC0_TYPE_DATA) { 3123 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3124 ath_led_event(sc, ATH_LED_RX); 3125 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3126 ath_led_event(sc, ATH_LED_POLL); 3127 } 3128 /* 3129 * Arrange to update the last rx timestamp only for 3130 * frames from our ap when operating in station mode. 3131 * This assumes the rx key is always setup when associated. 3132 */ 3133 if (ic->ic_opmode == IEEE80211_M_STA && 3134 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3135 ngood++; 3136 rx_next: 3137 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3138 } while (ath_rxbuf_init(sc, bf) == 0); 3139 3140 /* rx signal state monitoring */ 3141 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3142 if (ath_hal_radar_event(ah)) 3143 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3144 if (ngood) 3145 sc->sc_lastrx = tsf; 3146 3147 #ifdef __NetBSD__ 3148 /* XXX Why isn't this necessary in FreeBSD? */ 3149 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3150 ath_start(ifp); 3151 #endif /* __NetBSD__ */ 3152 3153 NET_UNLOCK_GIANT(); /* XXX */ 3154 #undef PA2DESC 3155 } 3156 3157 /* 3158 * Setup a h/w transmit queue. 3159 */ 3160 static struct ath_txq * 3161 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3162 { 3163 #define N(a) (sizeof(a)/sizeof(a[0])) 3164 struct ath_hal *ah = sc->sc_ah; 3165 HAL_TXQ_INFO qi; 3166 int qnum; 3167 3168 memset(&qi, 0, sizeof(qi)); 3169 qi.tqi_subtype = subtype; 3170 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3171 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3172 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3173 /* 3174 * Enable interrupts only for EOL and DESC conditions. 3175 * We mark tx descriptors to receive a DESC interrupt 3176 * when a tx queue gets deep; otherwise waiting for the 3177 * EOL to reap descriptors. Note that this is done to 3178 * reduce interrupt load and this only defers reaping 3179 * descriptors, never transmitting frames. Aside from 3180 * reducing interrupts this also permits more concurrency. 3181 * The only potential downside is if the tx queue backs 3182 * up in which case the top half of the kernel may backup 3183 * due to a lack of tx descriptors. 3184 */ 3185 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3186 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3187 if (qnum == -1) { 3188 /* 3189 * NB: don't print a message, this happens 3190 * normally on parts with too few tx queues 3191 */ 3192 return NULL; 3193 } 3194 if (qnum >= N(sc->sc_txq)) { 3195 device_printf(sc->sc_dev, 3196 "hal qnum %u out of range, max %zu!\n", 3197 qnum, N(sc->sc_txq)); 3198 ath_hal_releasetxqueue(ah, qnum); 3199 return NULL; 3200 } 3201 if (!ATH_TXQ_SETUP(sc, qnum)) { 3202 struct ath_txq *txq = &sc->sc_txq[qnum]; 3203 3204 txq->axq_qnum = qnum; 3205 txq->axq_depth = 0; 3206 txq->axq_intrcnt = 0; 3207 txq->axq_link = NULL; 3208 STAILQ_INIT(&txq->axq_q); 3209 ATH_TXQ_LOCK_INIT(sc, txq); 3210 sc->sc_txqsetup |= 1<<qnum; 3211 } 3212 return &sc->sc_txq[qnum]; 3213 #undef N 3214 } 3215 3216 /* 3217 * Setup a hardware data transmit queue for the specified 3218 * access control. The hal may not support all requested 3219 * queues in which case it will return a reference to a 3220 * previously setup queue. We record the mapping from ac's 3221 * to h/w queues for use by ath_tx_start and also track 3222 * the set of h/w queues being used to optimize work in the 3223 * transmit interrupt handler and related routines. 3224 */ 3225 static int 3226 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3227 { 3228 #define N(a) (sizeof(a)/sizeof(a[0])) 3229 struct ath_txq *txq; 3230 3231 if (ac >= N(sc->sc_ac2q)) { 3232 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3233 ac, N(sc->sc_ac2q)); 3234 return 0; 3235 } 3236 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3237 if (txq != NULL) { 3238 sc->sc_ac2q[ac] = txq; 3239 return 1; 3240 } else 3241 return 0; 3242 #undef N 3243 } 3244 3245 /* 3246 * Update WME parameters for a transmit queue. 3247 */ 3248 static int 3249 ath_txq_update(struct ath_softc *sc, int ac) 3250 { 3251 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3252 #define ATH_TXOP_TO_US(v) (v<<5) 3253 struct ieee80211com *ic = &sc->sc_ic; 3254 struct ath_txq *txq = sc->sc_ac2q[ac]; 3255 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3256 struct ath_hal *ah = sc->sc_ah; 3257 HAL_TXQ_INFO qi; 3258 3259 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3260 qi.tqi_aifs = wmep->wmep_aifsn; 3261 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3262 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3263 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3264 3265 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3266 device_printf(sc->sc_dev, "unable to update hardware queue " 3267 "parameters for %s traffic!\n", 3268 ieee80211_wme_acnames[ac]); 3269 return 0; 3270 } else { 3271 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3272 return 1; 3273 } 3274 #undef ATH_TXOP_TO_US 3275 #undef ATH_EXPONENT_TO_VALUE 3276 } 3277 3278 /* 3279 * Callback from the 802.11 layer to update WME parameters. 3280 */ 3281 static int 3282 ath_wme_update(struct ieee80211com *ic) 3283 { 3284 struct ath_softc *sc = ic->ic_ifp->if_softc; 3285 3286 return !ath_txq_update(sc, WME_AC_BE) || 3287 !ath_txq_update(sc, WME_AC_BK) || 3288 !ath_txq_update(sc, WME_AC_VI) || 3289 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3290 } 3291 3292 /* 3293 * Reclaim resources for a setup queue. 3294 */ 3295 static void 3296 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3297 { 3298 3299 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3300 ATH_TXQ_LOCK_DESTROY(txq); 3301 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3302 } 3303 3304 /* 3305 * Reclaim all tx queue resources. 3306 */ 3307 static void 3308 ath_tx_cleanup(struct ath_softc *sc) 3309 { 3310 int i; 3311 3312 ATH_TXBUF_LOCK_DESTROY(sc); 3313 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3314 if (ATH_TXQ_SETUP(sc, i)) 3315 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3316 } 3317 3318 /* 3319 * Defragment an mbuf chain, returning at most maxfrags separate 3320 * mbufs+clusters. If this is not possible NULL is returned and 3321 * the original mbuf chain is left in it's present (potentially 3322 * modified) state. We use two techniques: collapsing consecutive 3323 * mbufs and replacing consecutive mbufs by a cluster. 3324 */ 3325 static struct mbuf * 3326 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3327 { 3328 struct mbuf *m, *n, *n2, **prev; 3329 u_int curfrags; 3330 3331 /* 3332 * Calculate the current number of frags. 3333 */ 3334 curfrags = 0; 3335 for (m = m0; m != NULL; m = m->m_next) 3336 curfrags++; 3337 /* 3338 * First, try to collapse mbufs. Note that we always collapse 3339 * towards the front so we don't need to deal with moving the 3340 * pkthdr. This may be suboptimal if the first mbuf has much 3341 * less data than the following. 3342 */ 3343 m = m0; 3344 again: 3345 for (;;) { 3346 n = m->m_next; 3347 if (n == NULL) 3348 break; 3349 if ((m->m_flags & M_RDONLY) == 0 && 3350 n->m_len < M_TRAILINGSPACE(m)) { 3351 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3352 n->m_len); 3353 m->m_len += n->m_len; 3354 m->m_next = n->m_next; 3355 m_free(n); 3356 if (--curfrags <= maxfrags) 3357 return m0; 3358 } else 3359 m = n; 3360 } 3361 KASSERT(maxfrags > 1, 3362 ("maxfrags %u, but normal collapse failed", maxfrags)); 3363 /* 3364 * Collapse consecutive mbufs to a cluster. 3365 */ 3366 prev = &m0->m_next; /* NB: not the first mbuf */ 3367 while ((n = *prev) != NULL) { 3368 if ((n2 = n->m_next) != NULL && 3369 n->m_len + n2->m_len < MCLBYTES) { 3370 m = m_getcl(how, MT_DATA, 0); 3371 if (m == NULL) 3372 goto bad; 3373 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3374 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3375 n2->m_len); 3376 m->m_len = n->m_len + n2->m_len; 3377 m->m_next = n2->m_next; 3378 *prev = m; 3379 m_free(n); 3380 m_free(n2); 3381 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3382 return m0; 3383 /* 3384 * Still not there, try the normal collapse 3385 * again before we allocate another cluster. 3386 */ 3387 goto again; 3388 } 3389 prev = &n->m_next; 3390 } 3391 /* 3392 * No place where we can collapse to a cluster; punt. 3393 * This can occur if, for example, you request 2 frags 3394 * but the packet requires that both be clusters (we 3395 * never reallocate the first mbuf to avoid moving the 3396 * packet header). 3397 */ 3398 bad: 3399 return NULL; 3400 } 3401 3402 /* 3403 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3404 */ 3405 static int 3406 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3407 { 3408 int i; 3409 3410 for (i = 0; i < rt->rateCount; i++) 3411 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3412 return i; 3413 return 0; /* NB: lowest rate */ 3414 } 3415 3416 static int 3417 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3418 struct mbuf *m0) 3419 { 3420 struct ieee80211com *ic = &sc->sc_ic; 3421 struct ath_hal *ah = sc->sc_ah; 3422 struct ifnet *ifp = &sc->sc_if; 3423 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3424 int i, error, iswep, ismcast, ismrr; 3425 int keyix, hdrlen, pktlen, try0; 3426 u_int8_t rix, txrate, ctsrate; 3427 u_int8_t cix = 0xff; /* NB: silence compiler */ 3428 struct ath_desc *ds, *ds0; 3429 struct ath_txq *txq; 3430 struct ieee80211_frame *wh; 3431 u_int subtype, flags, ctsduration; 3432 HAL_PKT_TYPE atype; 3433 const HAL_RATE_TABLE *rt; 3434 HAL_BOOL shortPreamble; 3435 struct ath_node *an; 3436 struct mbuf *m; 3437 u_int pri; 3438 3439 wh = mtod(m0, struct ieee80211_frame *); 3440 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3441 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3442 hdrlen = ieee80211_anyhdrsize(wh); 3443 /* 3444 * Packet length must not include any 3445 * pad bytes; deduct them here. 3446 */ 3447 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3448 3449 if (iswep) { 3450 const struct ieee80211_cipher *cip; 3451 struct ieee80211_key *k; 3452 3453 /* 3454 * Construct the 802.11 header+trailer for an encrypted 3455 * frame. The only reason this can fail is because of an 3456 * unknown or unsupported cipher/key type. 3457 */ 3458 k = ieee80211_crypto_encap(ic, ni, m0); 3459 if (k == NULL) { 3460 /* 3461 * This can happen when the key is yanked after the 3462 * frame was queued. Just discard the frame; the 3463 * 802.11 layer counts failures and provides 3464 * debugging/diagnostics. 3465 */ 3466 m_freem(m0); 3467 return EIO; 3468 } 3469 /* 3470 * Adjust the packet + header lengths for the crypto 3471 * additions and calculate the h/w key index. When 3472 * a s/w mic is done the frame will have had any mic 3473 * added to it prior to entry so skb->len above will 3474 * account for it. Otherwise we need to add it to the 3475 * packet length. 3476 */ 3477 cip = k->wk_cipher; 3478 hdrlen += cip->ic_header; 3479 pktlen += cip->ic_header + cip->ic_trailer; 3480 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3481 pktlen += cip->ic_miclen; 3482 keyix = k->wk_keyix; 3483 3484 /* packet header may have moved, reset our local pointer */ 3485 wh = mtod(m0, struct ieee80211_frame *); 3486 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3487 /* 3488 * Use station key cache slot, if assigned. 3489 */ 3490 keyix = ni->ni_ucastkey.wk_keyix; 3491 if (keyix == IEEE80211_KEYIX_NONE) 3492 keyix = HAL_TXKEYIX_INVALID; 3493 } else 3494 keyix = HAL_TXKEYIX_INVALID; 3495 3496 pktlen += IEEE80211_CRC_LEN; 3497 3498 /* 3499 * Load the DMA map so any coalescing is done. This 3500 * also calculates the number of descriptors we need. 3501 */ 3502 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3503 BUS_DMA_NOWAIT); 3504 if (error == EFBIG) { 3505 /* XXX packet requires too many descriptors */ 3506 bf->bf_nseg = ATH_TXDESC+1; 3507 } else if (error != 0) { 3508 sc->sc_stats.ast_tx_busdma++; 3509 m_freem(m0); 3510 return error; 3511 } 3512 /* 3513 * Discard null packets and check for packets that 3514 * require too many TX descriptors. We try to convert 3515 * the latter to a cluster. 3516 */ 3517 if (error == EFBIG) { /* too many desc's, linearize */ 3518 sc->sc_stats.ast_tx_linear++; 3519 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3520 if (m == NULL) { 3521 m_freem(m0); 3522 sc->sc_stats.ast_tx_nombuf++; 3523 return ENOMEM; 3524 } 3525 m0 = m; 3526 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3527 BUS_DMA_NOWAIT); 3528 if (error != 0) { 3529 sc->sc_stats.ast_tx_busdma++; 3530 m_freem(m0); 3531 return error; 3532 } 3533 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3534 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3535 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3536 sc->sc_stats.ast_tx_nodata++; 3537 m_freem(m0); 3538 return EIO; 3539 } 3540 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3541 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3542 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3543 bf->bf_m = m0; 3544 bf->bf_node = ni; /* NB: held reference */ 3545 3546 /* setup descriptors */ 3547 ds = bf->bf_desc; 3548 rt = sc->sc_currates; 3549 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3550 3551 /* 3552 * NB: the 802.11 layer marks whether or not we should 3553 * use short preamble based on the current mode and 3554 * negotiated parameters. 3555 */ 3556 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3557 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3558 shortPreamble = AH_TRUE; 3559 sc->sc_stats.ast_tx_shortpre++; 3560 } else { 3561 shortPreamble = AH_FALSE; 3562 } 3563 3564 an = ATH_NODE(ni); 3565 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3566 ismrr = 0; /* default no multi-rate retry*/ 3567 /* 3568 * Calculate Atheros packet type from IEEE80211 packet header, 3569 * setup for rate calculations, and select h/w transmit queue. 3570 */ 3571 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3572 case IEEE80211_FC0_TYPE_MGT: 3573 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3574 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3575 atype = HAL_PKT_TYPE_BEACON; 3576 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3577 atype = HAL_PKT_TYPE_PROBE_RESP; 3578 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3579 atype = HAL_PKT_TYPE_ATIM; 3580 else 3581 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3582 rix = sc->sc_minrateix; 3583 txrate = rt->info[rix].rateCode; 3584 if (shortPreamble) 3585 txrate |= rt->info[rix].shortPreamble; 3586 try0 = ATH_TXMGTTRY; 3587 /* NB: force all management frames to highest queue */ 3588 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3589 /* NB: force all management frames to highest queue */ 3590 pri = WME_AC_VO; 3591 } else 3592 pri = WME_AC_BE; 3593 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3594 break; 3595 case IEEE80211_FC0_TYPE_CTL: 3596 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3597 rix = sc->sc_minrateix; 3598 txrate = rt->info[rix].rateCode; 3599 if (shortPreamble) 3600 txrate |= rt->info[rix].shortPreamble; 3601 try0 = ATH_TXMGTTRY; 3602 /* NB: force all ctl frames to highest queue */ 3603 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3604 /* NB: force all ctl frames to highest queue */ 3605 pri = WME_AC_VO; 3606 } else 3607 pri = WME_AC_BE; 3608 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3609 break; 3610 case IEEE80211_FC0_TYPE_DATA: 3611 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3612 /* 3613 * Data frames: multicast frames go out at a fixed rate, 3614 * otherwise consult the rate control module for the 3615 * rate to use. 3616 */ 3617 if (ismcast) { 3618 /* 3619 * Check mcast rate setting in case it's changed. 3620 * XXX move out of fastpath 3621 */ 3622 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3623 sc->sc_mcastrix = 3624 ath_tx_findrix(rt, ic->ic_mcast_rate); 3625 sc->sc_mcastrate = ic->ic_mcast_rate; 3626 } 3627 rix = sc->sc_mcastrix; 3628 txrate = rt->info[rix].rateCode; 3629 try0 = 1; 3630 } else { 3631 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3632 &rix, &try0, &txrate); 3633 sc->sc_txrate = txrate; /* for LED blinking */ 3634 if (try0 != ATH_TXMAXTRY) 3635 ismrr = 1; 3636 } 3637 pri = M_WME_GETAC(m0); 3638 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3639 flags |= HAL_TXDESC_NOACK; 3640 break; 3641 default: 3642 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3643 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3644 /* XXX statistic */ 3645 m_freem(m0); 3646 return EIO; 3647 } 3648 txq = sc->sc_ac2q[pri]; 3649 3650 /* 3651 * When servicing one or more stations in power-save mode 3652 * multicast frames must be buffered until after the beacon. 3653 * We use the CAB queue for that. 3654 */ 3655 if (ismcast && ic->ic_ps_sta) { 3656 txq = sc->sc_cabq; 3657 /* XXX? more bit in 802.11 frame header */ 3658 } 3659 3660 /* 3661 * Calculate miscellaneous flags. 3662 */ 3663 if (ismcast) { 3664 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3665 } else if (pktlen > ic->ic_rtsthreshold) { 3666 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3667 cix = rt->info[rix].controlRate; 3668 sc->sc_stats.ast_tx_rts++; 3669 } 3670 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3671 sc->sc_stats.ast_tx_noack++; 3672 3673 /* 3674 * If 802.11g protection is enabled, determine whether 3675 * to use RTS/CTS or just CTS. Note that this is only 3676 * done for OFDM unicast frames. 3677 */ 3678 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3679 rt->info[rix].phy == IEEE80211_T_OFDM && 3680 (flags & HAL_TXDESC_NOACK) == 0) { 3681 /* XXX fragments must use CCK rates w/ protection */ 3682 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3683 flags |= HAL_TXDESC_RTSENA; 3684 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3685 flags |= HAL_TXDESC_CTSENA; 3686 cix = rt->info[sc->sc_protrix].controlRate; 3687 sc->sc_stats.ast_tx_protect++; 3688 } 3689 3690 /* 3691 * Calculate duration. This logically belongs in the 802.11 3692 * layer but it lacks sufficient information to calculate it. 3693 */ 3694 if ((flags & HAL_TXDESC_NOACK) == 0 && 3695 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3696 u_int16_t dur; 3697 /* 3698 * XXX not right with fragmentation. 3699 */ 3700 if (shortPreamble) 3701 dur = rt->info[rix].spAckDuration; 3702 else 3703 dur = rt->info[rix].lpAckDuration; 3704 *(u_int16_t *)wh->i_dur = htole16(dur); 3705 } 3706 3707 /* 3708 * Calculate RTS/CTS rate and duration if needed. 3709 */ 3710 ctsduration = 0; 3711 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3712 /* 3713 * CTS transmit rate is derived from the transmit rate 3714 * by looking in the h/w rate table. We must also factor 3715 * in whether or not a short preamble is to be used. 3716 */ 3717 /* NB: cix is set above where RTS/CTS is enabled */ 3718 KASSERT(cix != 0xff, ("cix not setup")); 3719 ctsrate = rt->info[cix].rateCode; 3720 /* 3721 * Compute the transmit duration based on the frame 3722 * size and the size of an ACK frame. We call into the 3723 * HAL to do the computation since it depends on the 3724 * characteristics of the actual PHY being used. 3725 * 3726 * NB: CTS is assumed the same size as an ACK so we can 3727 * use the precalculated ACK durations. 3728 */ 3729 if (shortPreamble) { 3730 ctsrate |= rt->info[cix].shortPreamble; 3731 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3732 ctsduration += rt->info[cix].spAckDuration; 3733 ctsduration += ath_hal_computetxtime(ah, 3734 rt, pktlen, rix, AH_TRUE); 3735 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3736 ctsduration += rt->info[rix].spAckDuration; 3737 } else { 3738 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3739 ctsduration += rt->info[cix].lpAckDuration; 3740 ctsduration += ath_hal_computetxtime(ah, 3741 rt, pktlen, rix, AH_FALSE); 3742 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3743 ctsduration += rt->info[rix].lpAckDuration; 3744 } 3745 /* 3746 * Must disable multi-rate retry when using RTS/CTS. 3747 */ 3748 ismrr = 0; 3749 try0 = ATH_TXMGTTRY; /* XXX */ 3750 } else 3751 ctsrate = 0; 3752 3753 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3754 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3755 sc->sc_hwmap[txrate].ieeerate, -1); 3756 #if NBPFILTER > 0 3757 if (ic->ic_rawbpf) 3758 bpf_mtap(ic->ic_rawbpf, m0); 3759 if (sc->sc_drvbpf) { 3760 u_int64_t tsf = ath_hal_gettsf64(ah); 3761 3762 sc->sc_tx_th.wt_tsf = htole64(tsf); 3763 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3764 if (iswep) 3765 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3766 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3767 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3768 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3769 3770 bpf_mtap2(sc->sc_drvbpf, 3771 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3772 } 3773 #endif 3774 3775 /* 3776 * Determine if a tx interrupt should be generated for 3777 * this descriptor. We take a tx interrupt to reap 3778 * descriptors when the h/w hits an EOL condition or 3779 * when the descriptor is specifically marked to generate 3780 * an interrupt. We periodically mark descriptors in this 3781 * way to insure timely replenishing of the supply needed 3782 * for sending frames. Defering interrupts reduces system 3783 * load and potentially allows more concurrent work to be 3784 * done but if done to aggressively can cause senders to 3785 * backup. 3786 * 3787 * NB: use >= to deal with sc_txintrperiod changing 3788 * dynamically through sysctl. 3789 */ 3790 if (flags & HAL_TXDESC_INTREQ) { 3791 txq->axq_intrcnt = 0; 3792 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3793 flags |= HAL_TXDESC_INTREQ; 3794 txq->axq_intrcnt = 0; 3795 } 3796 3797 /* 3798 * Formulate first tx descriptor with tx controls. 3799 */ 3800 /* XXX check return value? */ 3801 ath_hal_setuptxdesc(ah, ds 3802 , pktlen /* packet length */ 3803 , hdrlen /* header length */ 3804 , atype /* Atheros packet type */ 3805 , ni->ni_txpower /* txpower */ 3806 , txrate, try0 /* series 0 rate/tries */ 3807 , keyix /* key cache index */ 3808 , sc->sc_txantenna /* antenna mode */ 3809 , flags /* flags */ 3810 , ctsrate /* rts/cts rate */ 3811 , ctsduration /* rts/cts duration */ 3812 ); 3813 bf->bf_flags = flags; 3814 /* 3815 * Setup the multi-rate retry state only when we're 3816 * going to use it. This assumes ath_hal_setuptxdesc 3817 * initializes the descriptors (so we don't have to) 3818 * when the hardware supports multi-rate retry and 3819 * we don't use it. 3820 */ 3821 if (ismrr) 3822 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3823 3824 /* 3825 * Fillin the remainder of the descriptor info. 3826 */ 3827 ds0 = ds; 3828 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3829 ds->ds_data = bf->bf_segs[i].ds_addr; 3830 if (i == bf->bf_nseg - 1) 3831 ds->ds_link = 0; 3832 else 3833 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3834 ath_hal_filltxdesc(ah, ds 3835 , bf->bf_segs[i].ds_len /* segment length */ 3836 , i == 0 /* first segment */ 3837 , i == bf->bf_nseg - 1 /* last segment */ 3838 , ds0 /* first descriptor */ 3839 ); 3840 3841 /* NB: The desc swap function becomes void, 3842 * if descriptor swapping is not enabled 3843 */ 3844 ath_desc_swap(ds); 3845 3846 DPRINTF(sc, ATH_DEBUG_XMIT, 3847 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3848 __func__, i, ds->ds_link, ds->ds_data, 3849 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3850 } 3851 /* 3852 * Insert the frame on the outbound list and 3853 * pass it on to the hardware. 3854 */ 3855 ATH_TXQ_LOCK(txq); 3856 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3857 if (txq->axq_link == NULL) { 3858 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3859 DPRINTF(sc, ATH_DEBUG_XMIT, 3860 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3861 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3862 txq->axq_depth); 3863 } else { 3864 *txq->axq_link = HTOAH32(bf->bf_daddr); 3865 DPRINTF(sc, ATH_DEBUG_XMIT, 3866 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3867 __func__, txq->axq_qnum, txq->axq_link, 3868 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3869 } 3870 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3871 /* 3872 * The CAB queue is started from the SWBA handler since 3873 * frames only go out on DTIM and to avoid possible races. 3874 */ 3875 if (txq != sc->sc_cabq) 3876 ath_hal_txstart(ah, txq->axq_qnum); 3877 ATH_TXQ_UNLOCK(txq); 3878 3879 return 0; 3880 } 3881 3882 /* 3883 * Process completed xmit descriptors from the specified queue. 3884 */ 3885 static int 3886 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3887 { 3888 struct ath_hal *ah = sc->sc_ah; 3889 struct ieee80211com *ic = &sc->sc_ic; 3890 struct ath_buf *bf; 3891 struct ath_desc *ds, *ds0; 3892 struct ieee80211_node *ni; 3893 struct ath_node *an; 3894 int sr, lr, pri, nacked; 3895 HAL_STATUS status; 3896 3897 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3898 __func__, txq->axq_qnum, 3899 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3900 txq->axq_link); 3901 nacked = 0; 3902 for (;;) { 3903 ATH_TXQ_LOCK(txq); 3904 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3905 bf = STAILQ_FIRST(&txq->axq_q); 3906 if (bf == NULL) { 3907 txq->axq_link = NULL; 3908 ATH_TXQ_UNLOCK(txq); 3909 break; 3910 } 3911 ds0 = &bf->bf_desc[0]; 3912 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3913 status = ath_hal_txprocdesc(ah, ds); 3914 #ifdef AR_DEBUG 3915 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3916 ath_printtxbuf(bf, status == HAL_OK); 3917 #endif 3918 if (status == HAL_EINPROGRESS) { 3919 ATH_TXQ_UNLOCK(txq); 3920 break; 3921 } 3922 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3923 ATH_TXQ_UNLOCK(txq); 3924 3925 ni = bf->bf_node; 3926 if (ni != NULL) { 3927 an = ATH_NODE(ni); 3928 if (ds->ds_txstat.ts_status == 0) { 3929 u_int8_t txant = ds->ds_txstat.ts_antenna; 3930 sc->sc_stats.ast_ant_tx[txant]++; 3931 sc->sc_ant_tx[txant]++; 3932 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3933 sc->sc_stats.ast_tx_altrate++; 3934 sc->sc_stats.ast_tx_rssi = 3935 ds->ds_txstat.ts_rssi; 3936 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3937 ds->ds_txstat.ts_rssi); 3938 pri = M_WME_GETAC(bf->bf_m); 3939 if (pri >= WME_AC_VO) 3940 ic->ic_wme.wme_hipri_traffic++; 3941 ni->ni_inact = ni->ni_inact_reload; 3942 } else { 3943 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3944 sc->sc_stats.ast_tx_xretries++; 3945 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3946 sc->sc_stats.ast_tx_fifoerr++; 3947 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3948 sc->sc_stats.ast_tx_filtered++; 3949 } 3950 sr = ds->ds_txstat.ts_shortretry; 3951 lr = ds->ds_txstat.ts_longretry; 3952 sc->sc_stats.ast_tx_shortretry += sr; 3953 sc->sc_stats.ast_tx_longretry += lr; 3954 /* 3955 * Hand the descriptor to the rate control algorithm. 3956 */ 3957 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3958 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 3959 /* 3960 * If frame was ack'd update the last rx time 3961 * used to workaround phantom bmiss interrupts. 3962 */ 3963 if (ds->ds_txstat.ts_status == 0) 3964 nacked++; 3965 ath_rate_tx_complete(sc, an, ds, ds0); 3966 } 3967 /* 3968 * Reclaim reference to node. 3969 * 3970 * NB: the node may be reclaimed here if, for example 3971 * this is a DEAUTH message that was sent and the 3972 * node was timed out due to inactivity. 3973 */ 3974 ieee80211_free_node(ni); 3975 } 3976 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3977 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3978 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3979 m_freem(bf->bf_m); 3980 bf->bf_m = NULL; 3981 bf->bf_node = NULL; 3982 3983 ATH_TXBUF_LOCK(sc); 3984 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3985 ATH_TXBUF_UNLOCK(sc); 3986 } 3987 return nacked; 3988 } 3989 3990 static inline int 3991 txqactive(struct ath_hal *ah, int qnum) 3992 { 3993 u_int32_t txqs = 1<<qnum; 3994 ath_hal_gettxintrtxqs(ah, &txqs); 3995 return (txqs & (1<<qnum)); 3996 } 3997 3998 /* 3999 * Deferred processing of transmit interrupt; special-cased 4000 * for a single hardware transmit queue (e.g. 5210 and 5211). 4001 */ 4002 static void 4003 ath_tx_proc_q0(void *arg, int npending) 4004 { 4005 struct ath_softc *sc = arg; 4006 struct ifnet *ifp = &sc->sc_if; 4007 4008 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 4009 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4010 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4011 ath_tx_processq(sc, sc->sc_cabq); 4012 ifp->if_flags &= ~IFF_OACTIVE; 4013 sc->sc_tx_timer = 0; 4014 4015 if (sc->sc_softled) 4016 ath_led_event(sc, ATH_LED_TX); 4017 4018 ath_start(ifp); 4019 } 4020 4021 /* 4022 * Deferred processing of transmit interrupt; special-cased 4023 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4024 */ 4025 static void 4026 ath_tx_proc_q0123(void *arg, int npending) 4027 { 4028 struct ath_softc *sc = arg; 4029 struct ifnet *ifp = &sc->sc_if; 4030 int nacked; 4031 4032 /* 4033 * Process each active queue. 4034 */ 4035 nacked = 0; 4036 if (txqactive(sc->sc_ah, 0)) 4037 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4038 if (txqactive(sc->sc_ah, 1)) 4039 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4040 if (txqactive(sc->sc_ah, 2)) 4041 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4042 if (txqactive(sc->sc_ah, 3)) 4043 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4044 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4045 ath_tx_processq(sc, sc->sc_cabq); 4046 if (nacked) 4047 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4048 ath_tx_processq(sc, sc->sc_cabq); 4049 4050 ifp->if_flags &= ~IFF_OACTIVE; 4051 sc->sc_tx_timer = 0; 4052 4053 if (sc->sc_softled) 4054 ath_led_event(sc, ATH_LED_TX); 4055 4056 ath_start(ifp); 4057 } 4058 4059 /* 4060 * Deferred processing of transmit interrupt. 4061 */ 4062 static void 4063 ath_tx_proc(void *arg, int npending) 4064 { 4065 struct ath_softc *sc = arg; 4066 struct ifnet *ifp = &sc->sc_if; 4067 int i, nacked; 4068 4069 /* 4070 * Process each active queue. 4071 */ 4072 nacked = 0; 4073 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4074 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4075 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4076 if (nacked) 4077 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4078 4079 ifp->if_flags &= ~IFF_OACTIVE; 4080 sc->sc_tx_timer = 0; 4081 4082 if (sc->sc_softled) 4083 ath_led_event(sc, ATH_LED_TX); 4084 4085 ath_start(ifp); 4086 } 4087 4088 static void 4089 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4090 { 4091 struct ath_hal *ah = sc->sc_ah; 4092 struct ieee80211_node *ni; 4093 struct ath_buf *bf; 4094 4095 /* 4096 * NB: this assumes output has been stopped and 4097 * we do not need to block ath_tx_tasklet 4098 */ 4099 for (;;) { 4100 ATH_TXQ_LOCK(txq); 4101 bf = STAILQ_FIRST(&txq->axq_q); 4102 if (bf == NULL) { 4103 txq->axq_link = NULL; 4104 ATH_TXQ_UNLOCK(txq); 4105 break; 4106 } 4107 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4108 ATH_TXQ_UNLOCK(txq); 4109 #ifdef AR_DEBUG 4110 if (sc->sc_debug & ATH_DEBUG_RESET) 4111 ath_printtxbuf(bf, 4112 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4113 #endif /* AR_DEBUG */ 4114 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4115 m_freem(bf->bf_m); 4116 bf->bf_m = NULL; 4117 ni = bf->bf_node; 4118 bf->bf_node = NULL; 4119 if (ni != NULL) { 4120 /* 4121 * Reclaim node reference. 4122 */ 4123 ieee80211_free_node(ni); 4124 } 4125 ATH_TXBUF_LOCK(sc); 4126 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4127 ATH_TXBUF_UNLOCK(sc); 4128 } 4129 } 4130 4131 static void 4132 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4133 { 4134 struct ath_hal *ah = sc->sc_ah; 4135 4136 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4137 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4138 __func__, txq->axq_qnum, 4139 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4140 txq->axq_link); 4141 } 4142 4143 /* 4144 * Drain the transmit queues and reclaim resources. 4145 */ 4146 static void 4147 ath_draintxq(struct ath_softc *sc) 4148 { 4149 struct ath_hal *ah = sc->sc_ah; 4150 struct ifnet *ifp = &sc->sc_if; 4151 int i; 4152 4153 /* XXX return value */ 4154 if (!sc->sc_invalid) { 4155 /* don't touch the hardware if marked invalid */ 4156 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4157 DPRINTF(sc, ATH_DEBUG_RESET, 4158 "%s: beacon queue %p\n", __func__, 4159 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4160 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4161 if (ATH_TXQ_SETUP(sc, i)) 4162 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4163 } 4164 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4165 if (ATH_TXQ_SETUP(sc, i)) 4166 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4167 ifp->if_flags &= ~IFF_OACTIVE; 4168 sc->sc_tx_timer = 0; 4169 } 4170 4171 /* 4172 * Disable the receive h/w in preparation for a reset. 4173 */ 4174 static void 4175 ath_stoprecv(struct ath_softc *sc) 4176 { 4177 #define PA2DESC(_sc, _pa) \ 4178 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4179 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4180 struct ath_hal *ah = sc->sc_ah; 4181 4182 ath_hal_stoppcurecv(ah); /* disable PCU */ 4183 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4184 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4185 DELAY(3000); /* 3ms is long enough for 1 frame */ 4186 #ifdef AR_DEBUG 4187 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4188 struct ath_buf *bf; 4189 4190 printf("%s: rx queue %p, link %p\n", __func__, 4191 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4192 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4193 struct ath_desc *ds = bf->bf_desc; 4194 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4195 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4196 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4197 ath_printrxbuf(bf, status == HAL_OK); 4198 } 4199 } 4200 #endif 4201 sc->sc_rxlink = NULL; /* just in case */ 4202 #undef PA2DESC 4203 } 4204 4205 /* 4206 * Enable the receive h/w following a reset. 4207 */ 4208 static int 4209 ath_startrecv(struct ath_softc *sc) 4210 { 4211 struct ath_hal *ah = sc->sc_ah; 4212 struct ath_buf *bf; 4213 4214 sc->sc_rxlink = NULL; 4215 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4216 int error = ath_rxbuf_init(sc, bf); 4217 if (error != 0) { 4218 DPRINTF(sc, ATH_DEBUG_RECV, 4219 "%s: ath_rxbuf_init failed %d\n", 4220 __func__, error); 4221 return error; 4222 } 4223 } 4224 4225 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4226 ath_hal_putrxbuf(ah, bf->bf_daddr); 4227 ath_hal_rxena(ah); /* enable recv descriptors */ 4228 ath_mode_init(sc); /* set filters, etc. */ 4229 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4230 return 0; 4231 } 4232 4233 /* 4234 * Update internal state after a channel change. 4235 */ 4236 static void 4237 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4238 { 4239 struct ieee80211com *ic = &sc->sc_ic; 4240 enum ieee80211_phymode mode; 4241 u_int16_t flags; 4242 4243 /* 4244 * Change channels and update the h/w rate map 4245 * if we're switching; e.g. 11a to 11b/g. 4246 */ 4247 mode = ieee80211_chan2mode(ic, chan); 4248 if (mode != sc->sc_curmode) 4249 ath_setcurmode(sc, mode); 4250 /* 4251 * Update BPF state. NB: ethereal et. al. don't handle 4252 * merged flags well so pick a unique mode for their use. 4253 */ 4254 if (IEEE80211_IS_CHAN_A(chan)) 4255 flags = IEEE80211_CHAN_A; 4256 /* XXX 11g schizophrenia */ 4257 else if (IEEE80211_IS_CHAN_G(chan) || 4258 IEEE80211_IS_CHAN_PUREG(chan)) 4259 flags = IEEE80211_CHAN_G; 4260 else 4261 flags = IEEE80211_CHAN_B; 4262 if (IEEE80211_IS_CHAN_T(chan)) 4263 flags |= IEEE80211_CHAN_TURBO; 4264 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4265 htole16(chan->ic_freq); 4266 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4267 htole16(flags); 4268 } 4269 4270 /* 4271 * Poll for a channel clear indication; this is required 4272 * for channels requiring DFS and not previously visited 4273 * and/or with a recent radar detection. 4274 */ 4275 static void 4276 ath_dfswait(void *arg) 4277 { 4278 struct ath_softc *sc = arg; 4279 struct ath_hal *ah = sc->sc_ah; 4280 HAL_CHANNEL hchan; 4281 4282 ath_hal_radar_wait(ah, &hchan); 4283 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4284 if_printf(&sc->sc_if, 4285 "channel %u/0x%x/0x%x has interference\n", 4286 hchan.channel, hchan.channelFlags, hchan.privFlags); 4287 return; 4288 } 4289 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4290 /* XXX should not happen */ 4291 return; 4292 } 4293 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4294 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4295 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4296 if_printf(&sc->sc_if, 4297 "channel %u/0x%x/0x%x marked clear\n", 4298 hchan.channel, hchan.channelFlags, hchan.privFlags); 4299 } else 4300 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4301 } 4302 4303 /* 4304 * Set/change channels. If the channel is really being changed, 4305 * it's done by reseting the chip. To accomplish this we must 4306 * first cleanup any pending DMA, then restart stuff after a la 4307 * ath_init. 4308 */ 4309 static int 4310 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4311 { 4312 struct ath_hal *ah = sc->sc_ah; 4313 struct ieee80211com *ic = &sc->sc_ic; 4314 HAL_CHANNEL hchan; 4315 4316 /* 4317 * Convert to a HAL channel description with 4318 * the flags constrained to reflect the current 4319 * operating mode. 4320 */ 4321 hchan.channel = chan->ic_freq; 4322 hchan.channelFlags = ath_chan2flags(ic, chan); 4323 4324 DPRINTF(sc, ATH_DEBUG_RESET, 4325 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4326 __func__, 4327 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4328 sc->sc_curchan.channelFlags), 4329 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4330 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4331 hchan.channel, hchan.channelFlags); 4332 if (hchan.channel != sc->sc_curchan.channel || 4333 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4334 HAL_STATUS status; 4335 4336 /* 4337 * To switch channels clear any pending DMA operations; 4338 * wait long enough for the RX fifo to drain, reset the 4339 * hardware at the new frequency, and then re-enable 4340 * the relevant bits of the h/w. 4341 */ 4342 ath_hal_intrset(ah, 0); /* disable interrupts */ 4343 ath_draintxq(sc); /* clear pending tx frames */ 4344 ath_stoprecv(sc); /* turn off frame recv */ 4345 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4346 if_printf(ic->ic_ifp, "%s: unable to reset " 4347 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4348 __func__, ieee80211_chan2ieee(ic, chan), 4349 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4350 return EIO; 4351 } 4352 sc->sc_curchan = hchan; 4353 ath_update_txpow(sc); /* update tx power state */ 4354 sc->sc_diversity = ath_hal_getdiversity(ah); 4355 sc->sc_calinterval = 1; 4356 sc->sc_caltries = 0; 4357 4358 /* 4359 * Re-enable rx framework. 4360 */ 4361 if (ath_startrecv(sc) != 0) { 4362 if_printf(&sc->sc_if, 4363 "%s: unable to restart recv logic\n", __func__); 4364 return EIO; 4365 } 4366 4367 /* 4368 * Change channels and update the h/w rate map 4369 * if we're switching; e.g. 11a to 11b/g. 4370 */ 4371 ic->ic_ibss_chan = chan; 4372 ath_chan_change(sc, chan); 4373 4374 /* 4375 * Handle DFS required waiting period to determine 4376 * if channel is clear of radar traffic. 4377 */ 4378 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4379 #define DFS_AND_NOT_CLEAR(_c) \ 4380 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4381 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4382 if_printf(&sc->sc_if, 4383 "wait for DFS clear channel signal\n"); 4384 /* XXX stop sndq */ 4385 sc->sc_if.if_flags |= IFF_OACTIVE; 4386 callout_reset(&sc->sc_dfs_ch, 4387 2 * hz, ath_dfswait, sc); 4388 } else 4389 callout_stop(&sc->sc_dfs_ch); 4390 #undef DFS_NOT_CLEAR 4391 } 4392 4393 /* 4394 * Re-enable interrupts. 4395 */ 4396 ath_hal_intrset(ah, sc->sc_imask); 4397 } 4398 return 0; 4399 } 4400 4401 static void 4402 ath_next_scan(void *arg) 4403 { 4404 struct ath_softc *sc = arg; 4405 struct ieee80211com *ic = &sc->sc_ic; 4406 int s; 4407 4408 /* don't call ath_start w/o network interrupts blocked */ 4409 s = splnet(); 4410 4411 if (ic->ic_state == IEEE80211_S_SCAN) 4412 ieee80211_next_scan(ic); 4413 splx(s); 4414 } 4415 4416 /* 4417 * Periodically recalibrate the PHY to account 4418 * for temperature/environment changes. 4419 */ 4420 static void 4421 ath_calibrate(void *arg) 4422 { 4423 struct ath_softc *sc = arg; 4424 struct ath_hal *ah = sc->sc_ah; 4425 HAL_BOOL iqCalDone; 4426 4427 sc->sc_stats.ast_per_cal++; 4428 4429 ATH_LOCK(sc); 4430 4431 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4432 /* 4433 * Rfgain is out of bounds, reset the chip 4434 * to load new gain values. 4435 */ 4436 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4437 "%s: rfgain change\n", __func__); 4438 sc->sc_stats.ast_per_rfgain++; 4439 ath_reset(&sc->sc_if); 4440 } 4441 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4442 DPRINTF(sc, ATH_DEBUG_ANY, 4443 "%s: calibration of channel %u failed\n", 4444 __func__, sc->sc_curchan.channel); 4445 sc->sc_stats.ast_per_calfail++; 4446 } 4447 /* 4448 * Calibrate noise floor data again in case of change. 4449 */ 4450 ath_hal_process_noisefloor(ah); 4451 /* 4452 * Poll more frequently when the IQ calibration is in 4453 * progress to speedup loading the final settings. 4454 * We temper this aggressive polling with an exponential 4455 * back off after 4 tries up to ath_calinterval. 4456 */ 4457 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4458 sc->sc_caltries = 0; 4459 sc->sc_calinterval = ath_calinterval; 4460 } else if (sc->sc_caltries > 4) { 4461 sc->sc_caltries = 0; 4462 sc->sc_calinterval <<= 1; 4463 if (sc->sc_calinterval > ath_calinterval) 4464 sc->sc_calinterval = ath_calinterval; 4465 } 4466 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4467 ("bad calibration interval %u", sc->sc_calinterval)); 4468 4469 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4470 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4471 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4472 sc->sc_caltries++; 4473 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4474 ath_calibrate, sc); 4475 ATH_UNLOCK(sc); 4476 } 4477 4478 static int 4479 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4480 { 4481 struct ifnet *ifp = ic->ic_ifp; 4482 struct ath_softc *sc = ifp->if_softc; 4483 struct ath_hal *ah = sc->sc_ah; 4484 struct ieee80211_node *ni; 4485 int i, error; 4486 const u_int8_t *bssid; 4487 u_int32_t rfilt; 4488 static const HAL_LED_STATE leds[] = { 4489 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4490 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4491 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4492 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4493 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4494 }; 4495 4496 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4497 ieee80211_state_name[ic->ic_state], 4498 ieee80211_state_name[nstate]); 4499 4500 callout_stop(&sc->sc_scan_ch); 4501 callout_stop(&sc->sc_cal_ch); 4502 callout_stop(&sc->sc_dfs_ch); 4503 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4504 4505 if (nstate == IEEE80211_S_INIT) { 4506 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4507 /* 4508 * NB: disable interrupts so we don't rx frames. 4509 */ 4510 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4511 /* 4512 * Notify the rate control algorithm. 4513 */ 4514 ath_rate_newstate(sc, nstate); 4515 goto done; 4516 } 4517 ni = ic->ic_bss; 4518 error = ath_chan_set(sc, ic->ic_curchan); 4519 if (error != 0) 4520 goto bad; 4521 rfilt = ath_calcrxfilter(sc, nstate); 4522 if (nstate == IEEE80211_S_SCAN) 4523 bssid = ifp->if_broadcastaddr; 4524 else 4525 bssid = ni->ni_bssid; 4526 ath_hal_setrxfilter(ah, rfilt); 4527 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4528 __func__, rfilt, ether_sprintf(bssid)); 4529 4530 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4531 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4532 else 4533 ath_hal_setassocid(ah, bssid, 0); 4534 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4535 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4536 if (ath_hal_keyisvalid(ah, i)) 4537 ath_hal_keysetmac(ah, i, bssid); 4538 } 4539 4540 /* 4541 * Notify the rate control algorithm so rates 4542 * are setup should ath_beacon_alloc be called. 4543 */ 4544 ath_rate_newstate(sc, nstate); 4545 4546 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4547 /* nothing to do */; 4548 } else if (nstate == IEEE80211_S_RUN) { 4549 DPRINTF(sc, ATH_DEBUG_STATE, 4550 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4551 "capinfo=0x%04x chan=%d\n" 4552 , __func__ 4553 , ic->ic_flags 4554 , ni->ni_intval 4555 , ether_sprintf(ni->ni_bssid) 4556 , ni->ni_capinfo 4557 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4558 4559 switch (ic->ic_opmode) { 4560 case IEEE80211_M_HOSTAP: 4561 case IEEE80211_M_IBSS: 4562 /* 4563 * Allocate and setup the beacon frame. 4564 * 4565 * Stop any previous beacon DMA. This may be 4566 * necessary, for example, when an ibss merge 4567 * causes reconfiguration; there will be a state 4568 * transition from RUN->RUN that means we may 4569 * be called with beacon transmission active. 4570 */ 4571 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4572 ath_beacon_free(sc); 4573 error = ath_beacon_alloc(sc, ni); 4574 if (error != 0) 4575 goto bad; 4576 /* 4577 * If joining an adhoc network defer beacon timer 4578 * configuration to the next beacon frame so we 4579 * have a current TSF to use. Otherwise we're 4580 * starting an ibss/bss so there's no need to delay. 4581 */ 4582 if (ic->ic_opmode == IEEE80211_M_IBSS && 4583 ic->ic_bss->ni_tstamp.tsf != 0) 4584 sc->sc_syncbeacon = 1; 4585 else 4586 ath_beacon_config(sc); 4587 break; 4588 case IEEE80211_M_STA: 4589 /* 4590 * Allocate a key cache slot to the station. 4591 */ 4592 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4593 sc->sc_hasclrkey && 4594 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4595 ath_setup_stationkey(ni); 4596 /* 4597 * Defer beacon timer configuration to the next 4598 * beacon frame so we have a current TSF to use 4599 * (any TSF collected when scanning is likely old). 4600 */ 4601 sc->sc_syncbeacon = 1; 4602 break; 4603 default: 4604 break; 4605 } 4606 /* 4607 * Let the hal process statistics collected during a 4608 * scan so it can provide calibrated noise floor data. 4609 */ 4610 ath_hal_process_noisefloor(ah); 4611 /* 4612 * Reset rssi stats; maybe not the best place... 4613 */ 4614 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4615 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4616 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4617 } else { 4618 ath_hal_intrset(ah, 4619 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4620 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4621 } 4622 done: 4623 /* 4624 * Invoke the parent method to complete the work. 4625 */ 4626 error = sc->sc_newstate(ic, nstate, arg); 4627 /* 4628 * Finally, start any timers. 4629 */ 4630 if (nstate == IEEE80211_S_RUN) { 4631 /* start periodic recalibration timer */ 4632 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4633 ath_calibrate, sc); 4634 } else if (nstate == IEEE80211_S_SCAN) { 4635 /* start ap/neighbor scan timer */ 4636 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4637 ath_next_scan, sc); 4638 } 4639 bad: 4640 return error; 4641 } 4642 4643 /* 4644 * Allocate a key cache slot to the station so we can 4645 * setup a mapping from key index to node. The key cache 4646 * slot is needed for managing antenna state and for 4647 * compression when stations do not use crypto. We do 4648 * it uniliaterally here; if crypto is employed this slot 4649 * will be reassigned. 4650 */ 4651 static void 4652 ath_setup_stationkey(struct ieee80211_node *ni) 4653 { 4654 struct ieee80211com *ic = ni->ni_ic; 4655 struct ath_softc *sc = ic->ic_ifp->if_softc; 4656 ieee80211_keyix keyix, rxkeyix; 4657 4658 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4659 /* 4660 * Key cache is full; we'll fall back to doing 4661 * the more expensive lookup in software. Note 4662 * this also means no h/w compression. 4663 */ 4664 /* XXX msg+statistic */ 4665 } else { 4666 /* XXX locking? */ 4667 ni->ni_ucastkey.wk_keyix = keyix; 4668 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4669 /* NB: this will create a pass-thru key entry */ 4670 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4671 } 4672 } 4673 4674 /* 4675 * Setup driver-specific state for a newly associated node. 4676 * Note that we're called also on a re-associate, the isnew 4677 * param tells us if this is the first time or not. 4678 */ 4679 static void 4680 ath_newassoc(struct ieee80211_node *ni, int isnew) 4681 { 4682 struct ieee80211com *ic = ni->ni_ic; 4683 struct ath_softc *sc = ic->ic_ifp->if_softc; 4684 4685 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4686 if (isnew && 4687 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4688 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4689 ("new assoc with a unicast key already setup (keyix %u)", 4690 ni->ni_ucastkey.wk_keyix)); 4691 ath_setup_stationkey(ni); 4692 } 4693 } 4694 4695 static int 4696 ath_getchannels(struct ath_softc *sc, u_int cc, 4697 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4698 { 4699 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4700 struct ieee80211com *ic = &sc->sc_ic; 4701 struct ifnet *ifp = &sc->sc_if; 4702 struct ath_hal *ah = sc->sc_ah; 4703 HAL_CHANNEL *chans; 4704 int i, ix, nchan; 4705 4706 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4707 M_TEMP, M_NOWAIT); 4708 if (chans == NULL) { 4709 if_printf(ifp, "unable to allocate channel table\n"); 4710 return ENOMEM; 4711 } 4712 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4713 NULL, 0, NULL, 4714 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4715 u_int32_t rd; 4716 4717 (void)ath_hal_getregdomain(ah, &rd); 4718 if_printf(ifp, "unable to collect channel list from hal; " 4719 "regdomain likely %u country code %u\n", rd, cc); 4720 free(chans, M_TEMP); 4721 return EINVAL; 4722 } 4723 4724 /* 4725 * Convert HAL channels to ieee80211 ones and insert 4726 * them in the table according to their channel number. 4727 */ 4728 for (i = 0; i < nchan; i++) { 4729 HAL_CHANNEL *c = &chans[i]; 4730 u_int16_t flags; 4731 4732 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4733 if (ix > IEEE80211_CHAN_MAX) { 4734 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4735 ix, c->channel, c->channelFlags); 4736 continue; 4737 } 4738 if (ix < 0) { 4739 /* XXX can't handle stuff <2400 right now */ 4740 if (bootverbose) 4741 if_printf(ifp, "hal channel %d (%u/%x) " 4742 "cannot be handled; ignored\n", 4743 ix, c->channel, c->channelFlags); 4744 continue; 4745 } 4746 /* 4747 * Calculate net80211 flags; most are compatible 4748 * but some need massaging. Note the static turbo 4749 * conversion can be removed once net80211 is updated 4750 * to understand static vs. dynamic turbo. 4751 */ 4752 flags = c->channelFlags & COMPAT; 4753 if (c->channelFlags & CHANNEL_STURBO) 4754 flags |= IEEE80211_CHAN_TURBO; 4755 if (ic->ic_channels[ix].ic_freq == 0) { 4756 ic->ic_channels[ix].ic_freq = c->channel; 4757 ic->ic_channels[ix].ic_flags = flags; 4758 } else { 4759 /* channels overlap; e.g. 11g and 11b */ 4760 ic->ic_channels[ix].ic_flags |= flags; 4761 } 4762 } 4763 free(chans, M_TEMP); 4764 return 0; 4765 #undef COMPAT 4766 } 4767 4768 static void 4769 ath_led_done(void *arg) 4770 { 4771 struct ath_softc *sc = arg; 4772 4773 sc->sc_blinking = 0; 4774 } 4775 4776 /* 4777 * Turn the LED off: flip the pin and then set a timer so no 4778 * update will happen for the specified duration. 4779 */ 4780 static void 4781 ath_led_off(void *arg) 4782 { 4783 struct ath_softc *sc = arg; 4784 4785 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4786 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4787 } 4788 4789 /* 4790 * Blink the LED according to the specified on/off times. 4791 */ 4792 static void 4793 ath_led_blink(struct ath_softc *sc, int on, int off) 4794 { 4795 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4796 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4797 sc->sc_blinking = 1; 4798 sc->sc_ledoff = off; 4799 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4800 } 4801 4802 static void 4803 ath_led_event(struct ath_softc *sc, int event) 4804 { 4805 4806 sc->sc_ledevent = ticks; /* time of last event */ 4807 if (sc->sc_blinking) /* don't interrupt active blink */ 4808 return; 4809 switch (event) { 4810 case ATH_LED_POLL: 4811 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4812 sc->sc_hwmap[0].ledoff); 4813 break; 4814 case ATH_LED_TX: 4815 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4816 sc->sc_hwmap[sc->sc_txrate].ledoff); 4817 break; 4818 case ATH_LED_RX: 4819 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4820 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4821 break; 4822 } 4823 } 4824 4825 static void 4826 ath_update_txpow(struct ath_softc *sc) 4827 { 4828 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4829 struct ieee80211com *ic = &sc->sc_ic; 4830 struct ath_hal *ah = sc->sc_ah; 4831 u_int32_t txpow; 4832 4833 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4834 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4835 /* read back in case value is clamped */ 4836 (void)ath_hal_gettxpowlimit(ah, &txpow); 4837 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4838 } 4839 /* 4840 * Fetch max tx power level for status requests. 4841 */ 4842 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4843 ic->ic_bss->ni_txpower = txpow; 4844 } 4845 4846 static void 4847 rate_setup(struct ath_softc *sc, 4848 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4849 { 4850 int i, maxrates; 4851 4852 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4853 DPRINTF(sc, ATH_DEBUG_ANY, 4854 "%s: rate table too small (%u > %u)\n", 4855 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4856 maxrates = IEEE80211_RATE_MAXSIZE; 4857 } else 4858 maxrates = rt->rateCount; 4859 for (i = 0; i < maxrates; i++) 4860 rs->rs_rates[i] = rt->info[i].dot11Rate; 4861 rs->rs_nrates = maxrates; 4862 } 4863 4864 static int 4865 ath_rate_setup(struct ath_softc *sc, u_int mode) 4866 { 4867 struct ath_hal *ah = sc->sc_ah; 4868 struct ieee80211com *ic = &sc->sc_ic; 4869 const HAL_RATE_TABLE *rt; 4870 4871 switch (mode) { 4872 case IEEE80211_MODE_11A: 4873 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4874 break; 4875 case IEEE80211_MODE_11B: 4876 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4877 break; 4878 case IEEE80211_MODE_11G: 4879 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4880 break; 4881 case IEEE80211_MODE_TURBO_A: 4882 /* XXX until static/dynamic turbo is fixed */ 4883 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4884 break; 4885 case IEEE80211_MODE_TURBO_G: 4886 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4887 break; 4888 default: 4889 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4890 __func__, mode); 4891 return 0; 4892 } 4893 sc->sc_rates[mode] = rt; 4894 if (rt != NULL) { 4895 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 4896 return 1; 4897 } else 4898 return 0; 4899 } 4900 4901 static void 4902 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4903 { 4904 #define N(a) (sizeof(a)/sizeof(a[0])) 4905 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4906 static const struct { 4907 u_int rate; /* tx/rx 802.11 rate */ 4908 u_int16_t timeOn; /* LED on time (ms) */ 4909 u_int16_t timeOff; /* LED off time (ms) */ 4910 } blinkrates[] = { 4911 { 108, 40, 10 }, 4912 { 96, 44, 11 }, 4913 { 72, 50, 13 }, 4914 { 48, 57, 14 }, 4915 { 36, 67, 16 }, 4916 { 24, 80, 20 }, 4917 { 22, 100, 25 }, 4918 { 18, 133, 34 }, 4919 { 12, 160, 40 }, 4920 { 10, 200, 50 }, 4921 { 6, 240, 58 }, 4922 { 4, 267, 66 }, 4923 { 2, 400, 100 }, 4924 { 0, 500, 130 }, 4925 }; 4926 const HAL_RATE_TABLE *rt; 4927 int i, j; 4928 4929 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4930 rt = sc->sc_rates[mode]; 4931 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4932 for (i = 0; i < rt->rateCount; i++) 4933 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4934 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4935 for (i = 0; i < 32; i++) { 4936 u_int8_t ix = rt->rateCodeToIndex[i]; 4937 if (ix == 0xff) { 4938 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4939 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4940 continue; 4941 } 4942 sc->sc_hwmap[i].ieeerate = 4943 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4944 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4945 if (rt->info[ix].shortPreamble || 4946 rt->info[ix].phy == IEEE80211_T_OFDM) 4947 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4948 /* NB: receive frames include FCS */ 4949 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4950 IEEE80211_RADIOTAP_F_FCS; 4951 /* setup blink rate table to avoid per-packet lookup */ 4952 for (j = 0; j < N(blinkrates)-1; j++) 4953 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4954 break; 4955 /* NB: this uses the last entry if the rate isn't found */ 4956 /* XXX beware of overlow */ 4957 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4958 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4959 } 4960 sc->sc_currates = rt; 4961 sc->sc_curmode = mode; 4962 /* 4963 * All protection frames are transmited at 2Mb/s for 4964 * 11g, otherwise at 1Mb/s. 4965 */ 4966 if (mode == IEEE80211_MODE_11G) 4967 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 4968 else 4969 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 4970 /* rate index used to send management frames */ 4971 sc->sc_minrateix = 0; 4972 /* 4973 * Setup multicast rate state. 4974 */ 4975 /* XXX layering violation */ 4976 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 4977 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 4978 /* NB: caller is responsible for reseting rate control state */ 4979 #undef N 4980 } 4981 4982 #ifdef AR_DEBUG 4983 static void 4984 ath_printrxbuf(struct ath_buf *bf, int done) 4985 { 4986 struct ath_desc *ds; 4987 int i; 4988 4989 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4990 printf("R%d (%p %" PRIx64 4991 ") %08x %08x %08x %08x %08x %08x %c\n", i, ds, 4992 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 4993 ds->ds_link, ds->ds_data, 4994 ds->ds_ctl0, ds->ds_ctl1, 4995 ds->ds_hw[0], ds->ds_hw[1], 4996 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4997 } 4998 } 4999 5000 static void 5001 ath_printtxbuf(struct ath_buf *bf, int done) 5002 { 5003 struct ath_desc *ds; 5004 int i; 5005 5006 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5007 printf("T%d (%p %" PRIx64 5008 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5009 i, ds, 5010 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5011 ds->ds_link, ds->ds_data, 5012 ds->ds_ctl0, ds->ds_ctl1, 5013 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5014 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5015 } 5016 } 5017 #endif /* AR_DEBUG */ 5018 5019 static void 5020 ath_watchdog(struct ifnet *ifp) 5021 { 5022 struct ath_softc *sc = ifp->if_softc; 5023 struct ieee80211com *ic = &sc->sc_ic; 5024 5025 ifp->if_timer = 0; 5026 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 5027 return; 5028 if (sc->sc_tx_timer) { 5029 if (--sc->sc_tx_timer == 0) { 5030 if_printf(ifp, "device timeout\n"); 5031 ath_reset(ifp); 5032 ifp->if_oerrors++; 5033 sc->sc_stats.ast_watchdog++; 5034 } else 5035 ifp->if_timer = 1; 5036 } 5037 ieee80211_watchdog(ic); 5038 } 5039 5040 /* 5041 * Diagnostic interface to the HAL. This is used by various 5042 * tools to do things like retrieve register contents for 5043 * debugging. The mechanism is intentionally opaque so that 5044 * it can change frequently w/o concern for compatiblity. 5045 */ 5046 static int 5047 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5048 { 5049 struct ath_hal *ah = sc->sc_ah; 5050 u_int id = ad->ad_id & ATH_DIAG_ID; 5051 void *indata = NULL; 5052 void *outdata = NULL; 5053 u_int32_t insize = ad->ad_in_size; 5054 u_int32_t outsize = ad->ad_out_size; 5055 int error = 0; 5056 5057 if (ad->ad_id & ATH_DIAG_IN) { 5058 /* 5059 * Copy in data. 5060 */ 5061 indata = malloc(insize, M_TEMP, M_NOWAIT); 5062 if (indata == NULL) { 5063 error = ENOMEM; 5064 goto bad; 5065 } 5066 error = copyin(ad->ad_in_data, indata, insize); 5067 if (error) 5068 goto bad; 5069 } 5070 if (ad->ad_id & ATH_DIAG_DYN) { 5071 /* 5072 * Allocate a buffer for the results (otherwise the HAL 5073 * returns a pointer to a buffer where we can read the 5074 * results). Note that we depend on the HAL leaving this 5075 * pointer for us to use below in reclaiming the buffer; 5076 * may want to be more defensive. 5077 */ 5078 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5079 if (outdata == NULL) { 5080 error = ENOMEM; 5081 goto bad; 5082 } 5083 } 5084 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5085 if (outsize < ad->ad_out_size) 5086 ad->ad_out_size = outsize; 5087 if (outdata != NULL) 5088 error = copyout(outdata, ad->ad_out_data, 5089 ad->ad_out_size); 5090 } else { 5091 error = EINVAL; 5092 } 5093 bad: 5094 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5095 free(indata, M_TEMP); 5096 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5097 free(outdata, M_TEMP); 5098 return error; 5099 } 5100 5101 static int 5102 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5103 { 5104 #define IS_RUNNING(ifp) \ 5105 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5106 struct ath_softc *sc = ifp->if_softc; 5107 struct ieee80211com *ic = &sc->sc_ic; 5108 struct ifreq *ifr = (struct ifreq *)data; 5109 int error = 0; 5110 5111 ATH_LOCK(sc); 5112 switch (cmd) { 5113 case SIOCSIFFLAGS: 5114 if (IS_RUNNING(ifp)) { 5115 /* 5116 * To avoid rescanning another access point, 5117 * do not call ath_init() here. Instead, 5118 * only reflect promisc mode settings. 5119 */ 5120 ath_mode_init(sc); 5121 } else if (ifp->if_flags & IFF_UP) { 5122 /* 5123 * Beware of being called during attach/detach 5124 * to reset promiscuous mode. In that case we 5125 * will still be marked UP but not RUNNING. 5126 * However trying to re-init the interface 5127 * is the wrong thing to do as we've already 5128 * torn down much of our state. There's 5129 * probably a better way to deal with this. 5130 */ 5131 if (!sc->sc_invalid && ic->ic_bss != NULL) 5132 ath_init(sc); /* XXX lose error */ 5133 } else 5134 ath_stop_locked(ifp, 1); 5135 break; 5136 case SIOCADDMULTI: 5137 case SIOCDELMULTI: 5138 error = (cmd == SIOCADDMULTI) ? 5139 ether_addmulti(ifr, &sc->sc_ec) : 5140 ether_delmulti(ifr, &sc->sc_ec); 5141 if (error == ENETRESET) { 5142 if (ifp->if_flags & IFF_RUNNING) 5143 ath_mode_init(sc); 5144 error = 0; 5145 } 5146 break; 5147 case SIOCGATHSTATS: 5148 /* NB: embed these numbers to get a consistent view */ 5149 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5150 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5151 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5152 ATH_UNLOCK(sc); 5153 /* 5154 * NB: Drop the softc lock in case of a page fault; 5155 * we'll accept any potential inconsisentcy in the 5156 * statistics. The alternative is to copy the data 5157 * to a local structure. 5158 */ 5159 return copyout(&sc->sc_stats, 5160 ifr->ifr_data, sizeof (sc->sc_stats)); 5161 case SIOCGATHDIAG: 5162 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5163 break; 5164 default: 5165 error = ieee80211_ioctl(ic, cmd, data); 5166 if (error == ENETRESET) { 5167 if (IS_RUNNING(ifp) && 5168 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5169 ath_init(sc); /* XXX lose error */ 5170 error = 0; 5171 } 5172 if (error == ERESTART) 5173 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5174 break; 5175 } 5176 ATH_UNLOCK(sc); 5177 return error; 5178 #undef IS_RUNNING 5179 } 5180 5181 #if NBPFILTER > 0 5182 static void 5183 ath_bpfattach(struct ath_softc *sc) 5184 { 5185 struct ifnet *ifp = &sc->sc_if; 5186 5187 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5188 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5189 &sc->sc_drvbpf); 5190 /* 5191 * Initialize constant fields. 5192 * XXX make header lengths a multiple of 32-bits so subsequent 5193 * headers are properly aligned; this is a kludge to keep 5194 * certain applications happy. 5195 * 5196 * NB: the channel is setup each time we transition to the 5197 * RUN state to avoid filling it in for each frame. 5198 */ 5199 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5200 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5201 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5202 5203 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5204 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5205 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5206 } 5207 #endif 5208 5209 /* 5210 * Announce various information on device/driver attach. 5211 */ 5212 static void 5213 ath_announce(struct ath_softc *sc) 5214 { 5215 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5216 struct ifnet *ifp = &sc->sc_if; 5217 struct ath_hal *ah = sc->sc_ah; 5218 u_int modes, cc; 5219 5220 if_printf(ifp, "mac %d.%d phy %d.%d", 5221 ah->ah_macVersion, ah->ah_macRev, 5222 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5223 /* 5224 * Print radio revision(s). We check the wireless modes 5225 * to avoid falsely printing revs for inoperable parts. 5226 * Dual-band radio revs are returned in the 5 GHz rev number. 5227 */ 5228 ath_hal_getcountrycode(ah, &cc); 5229 modes = ath_hal_getwirelessmodes(ah, cc); 5230 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5231 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5232 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5233 ah->ah_analog5GhzRev >> 4, 5234 ah->ah_analog5GhzRev & 0xf, 5235 ah->ah_analog2GhzRev >> 4, 5236 ah->ah_analog2GhzRev & 0xf); 5237 else 5238 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5239 ah->ah_analog5GhzRev & 0xf); 5240 } else 5241 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5242 ah->ah_analog5GhzRev & 0xf); 5243 printf("\n"); 5244 if (bootverbose) { 5245 int i; 5246 for (i = 0; i <= WME_AC_VO; i++) { 5247 struct ath_txq *txq = sc->sc_ac2q[i]; 5248 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5249 txq->axq_qnum, ieee80211_wme_acnames[i]); 5250 } 5251 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5252 sc->sc_cabq->axq_qnum); 5253 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5254 } 5255 if (ath_rxbuf != ATH_RXBUF) 5256 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5257 if (ath_txbuf != ATH_TXBUF) 5258 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5259 #undef HAL_MODE_DUALBAND 5260 } 5261
Indexes created Thu Oct 02 07:10:07 GMT 2025