ath.c revision 1.99.4.4
1 /* $NetBSD: ath.c,v 1.99.4.4 2010/03/11 15:03:28 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.99.4.4 2010/03/11 15:03:28 yamt Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #include <sys/param.h> 57 #include <sys/reboot.h> 58 #include <sys/systm.h> 59 #include <sys/types.h> 60 #include <sys/sysctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/sockio.h> 66 #include <sys/errno.h> 67 #include <sys/callout.h> 68 #include <sys/bus.h> 69 #include <sys/endian.h> 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_arp.h> 76 #include <net/if_ether.h> 77 #include <net/if_llc.h> 78 79 #include <net80211/ieee80211_netbsd.h> 80 #include <net80211/ieee80211_var.h> 81 82 #include <net/bpf.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #endif 87 88 #include <sys/device.h> 89 #include <dev/ic/ath_netbsd.h> 90 91 #define AR_DEBUG 92 #include <dev/ic/athvar.h> 93 #include "ah_desc.h" 94 #include "ah_devid.h" /* XXX for softled */ 95 #include "opt_ah.h" 96 97 #ifdef ATH_TX99_DIAG 98 #include <dev/ath/ath_tx99/ath_tx99.h> 99 #endif 100 101 /* unaligned little endian access */ 102 #define LE_READ_2(p) \ 103 ((u_int16_t) \ 104 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 105 #define LE_READ_4(p) \ 106 ((u_int32_t) \ 107 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 108 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 109 110 enum { 111 ATH_LED_TX, 112 ATH_LED_RX, 113 ATH_LED_POLL, 114 }; 115 116 #ifdef AH_NEED_DESC_SWAP 117 #define HTOAH32(x) htole32(x) 118 #else 119 #define HTOAH32(x) (x) 120 #endif 121 122 static int ath_ifinit(struct ifnet *); 123 static int ath_init(struct ath_softc *); 124 static void ath_stop_locked(struct ifnet *, int); 125 static void ath_stop(struct ifnet *, int); 126 static void ath_start(struct ifnet *); 127 static int ath_media_change(struct ifnet *); 128 static void ath_watchdog(struct ifnet *); 129 static int ath_ioctl(struct ifnet *, u_long, void *); 130 static void ath_fatal_proc(void *, int); 131 static void ath_rxorn_proc(void *, int); 132 static void ath_bmiss_proc(void *, int); 133 static void ath_radar_proc(void *, int); 134 static int ath_key_alloc(struct ieee80211com *, 135 const struct ieee80211_key *, 136 ieee80211_keyix *, ieee80211_keyix *); 137 static int ath_key_delete(struct ieee80211com *, 138 const struct ieee80211_key *); 139 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 140 const u_int8_t mac[IEEE80211_ADDR_LEN]); 141 static void ath_key_update_begin(struct ieee80211com *); 142 static void ath_key_update_end(struct ieee80211com *); 143 static void ath_mode_init(struct ath_softc *); 144 static void ath_setslottime(struct ath_softc *); 145 static void ath_updateslot(struct ifnet *); 146 static int ath_beaconq_setup(struct ath_hal *); 147 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 148 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 149 static void ath_beacon_proc(void *, int); 150 static void ath_bstuck_proc(void *, int); 151 static void ath_beacon_free(struct ath_softc *); 152 static void ath_beacon_config(struct ath_softc *); 153 static void ath_descdma_cleanup(struct ath_softc *sc, 154 struct ath_descdma *, ath_bufhead *); 155 static int ath_desc_alloc(struct ath_softc *); 156 static void ath_desc_free(struct ath_softc *); 157 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 158 static void ath_node_free(struct ieee80211_node *); 159 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 160 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 161 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 162 struct ieee80211_node *ni, 163 int subtype, int rssi, u_int32_t rstamp); 164 static void ath_setdefantenna(struct ath_softc *, u_int); 165 static void ath_rx_proc(void *, int); 166 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 167 static int ath_tx_setup(struct ath_softc *, int, int); 168 static int ath_wme_update(struct ieee80211com *); 169 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 170 static void ath_tx_cleanup(struct ath_softc *); 171 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 172 struct ath_buf *, struct mbuf *); 173 static void ath_tx_proc_q0(void *, int); 174 static void ath_tx_proc_q0123(void *, int); 175 static void ath_tx_proc(void *, int); 176 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 177 static void ath_draintxq(struct ath_softc *); 178 static void ath_stoprecv(struct ath_softc *); 179 static int ath_startrecv(struct ath_softc *); 180 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 181 static void ath_next_scan(void *); 182 static void ath_calibrate(void *); 183 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 184 static void ath_setup_stationkey(struct ieee80211_node *); 185 static void ath_newassoc(struct ieee80211_node *, int); 186 static int ath_getchannels(struct ath_softc *, u_int cc, 187 HAL_BOOL outdoor, HAL_BOOL xchanmode); 188 static void ath_led_event(struct ath_softc *, int); 189 static void ath_update_txpow(struct ath_softc *); 190 static void ath_freetx(struct mbuf *); 191 static void ath_restore_diversity(struct ath_softc *); 192 193 static int ath_rate_setup(struct ath_softc *, u_int mode); 194 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 195 196 static void ath_bpfattach(struct ath_softc *); 197 static void ath_announce(struct ath_softc *); 198 199 int ath_dwelltime = 200; /* 5 channels/second */ 200 int ath_calinterval = 30; /* calibrate every 30 secs */ 201 int ath_outdoor = AH_TRUE; /* outdoor operation */ 202 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 203 int ath_countrycode = CTRY_DEFAULT; /* country code */ 204 int ath_regdomain = 0; /* regulatory domain */ 205 int ath_debug = 0; 206 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 207 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 208 209 #ifdef AR_DEBUG 210 enum { 211 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 212 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 213 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 214 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 215 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 216 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 217 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 218 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 219 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 220 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 221 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 222 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 223 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 224 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 225 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 226 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 227 ATH_DEBUG_NODE = 0x00080000, /* node management */ 228 ATH_DEBUG_LED = 0x00100000, /* led management */ 229 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 230 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 231 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 232 ATH_DEBUG_ANY = 0xffffffff 233 }; 234 #define IFF_DUMPPKTS(sc, m) \ 235 ((sc->sc_debug & (m)) || \ 236 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 237 #define DPRINTF(sc, m, fmt, ...) do { \ 238 if (sc->sc_debug & (m)) \ 239 printf(fmt, __VA_ARGS__); \ 240 } while (0) 241 #define KEYPRINTF(sc, ix, hk, mac) do { \ 242 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 243 ath_keyprint(__func__, ix, hk, mac); \ 244 } while (0) 245 static void ath_printrxbuf(struct ath_buf *bf, int); 246 static void ath_printtxbuf(struct ath_buf *bf, int); 247 #else 248 #define IFF_DUMPPKTS(sc, m) \ 249 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 250 #define DPRINTF(m, fmt, ...) 251 #define KEYPRINTF(sc, k, ix, mac) 252 #endif 253 254 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 255 256 int 257 ath_attach(u_int16_t devid, struct ath_softc *sc) 258 { 259 struct ifnet *ifp = &sc->sc_if; 260 struct ieee80211com *ic = &sc->sc_ic; 261 struct ath_hal *ah = NULL; 262 HAL_STATUS status; 263 int error = 0, i; 264 265 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 266 267 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 268 269 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 270 271 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 272 if (ah == NULL) { 273 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 274 status); 275 error = ENXIO; 276 goto bad; 277 } 278 if (ah->ah_abi != HAL_ABI_VERSION) { 279 if_printf(ifp, "HAL ABI mismatch detected " 280 "(HAL:0x%x != driver:0x%x)\n", 281 ah->ah_abi, HAL_ABI_VERSION); 282 error = ENXIO; 283 goto bad; 284 } 285 sc->sc_ah = ah; 286 287 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 288 "pmf-powerdown", false)) 289 goto bad; 290 291 /* 292 * Check if the MAC has multi-rate retry support. 293 * We do this by trying to setup a fake extended 294 * descriptor. MAC's that don't have support will 295 * return false w/o doing anything. MAC's that do 296 * support it will return true w/o doing anything. 297 */ 298 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 299 300 /* 301 * Check if the device has hardware counters for PHY 302 * errors. If so we need to enable the MIB interrupt 303 * so we can act on stat triggers. 304 */ 305 if (ath_hal_hwphycounters(ah)) 306 sc->sc_needmib = 1; 307 308 /* 309 * Get the hardware key cache size. 310 */ 311 sc->sc_keymax = ath_hal_keycachesize(ah); 312 if (sc->sc_keymax > ATH_KEYMAX) { 313 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 314 ATH_KEYMAX, sc->sc_keymax); 315 sc->sc_keymax = ATH_KEYMAX; 316 } 317 /* 318 * Reset the key cache since some parts do not 319 * reset the contents on initial power up. 320 */ 321 for (i = 0; i < sc->sc_keymax; i++) 322 ath_hal_keyreset(ah, i); 323 /* 324 * Mark key cache slots associated with global keys 325 * as in use. If we knew TKIP was not to be used we 326 * could leave the +32, +64, and +32+64 slots free. 327 * XXX only for splitmic. 328 */ 329 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 330 setbit(sc->sc_keymap, i); 331 setbit(sc->sc_keymap, i+32); 332 setbit(sc->sc_keymap, i+64); 333 setbit(sc->sc_keymap, i+32+64); 334 } 335 336 /* 337 * Collect the channel list using the default country 338 * code and including outdoor channels. The 802.11 layer 339 * is resposible for filtering this list based on settings 340 * like the phy mode. 341 */ 342 error = ath_getchannels(sc, ath_countrycode, 343 ath_outdoor, ath_xchanmode); 344 if (error != 0) 345 goto bad; 346 347 /* 348 * Setup rate tables for all potential media types. 349 */ 350 ath_rate_setup(sc, IEEE80211_MODE_11A); 351 ath_rate_setup(sc, IEEE80211_MODE_11B); 352 ath_rate_setup(sc, IEEE80211_MODE_11G); 353 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 354 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 355 /* NB: setup here so ath_rate_update is happy */ 356 ath_setcurmode(sc, IEEE80211_MODE_11A); 357 358 /* 359 * Allocate tx+rx descriptors and populate the lists. 360 */ 361 error = ath_desc_alloc(sc); 362 if (error != 0) { 363 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 364 goto bad; 365 } 366 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 367 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 368 #if 0 369 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 370 #endif 371 372 ATH_TXBUF_LOCK_INIT(sc); 373 374 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 375 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 376 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 377 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 378 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 379 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 380 381 /* 382 * Allocate hardware transmit queues: one queue for 383 * beacon frames and one data queue for each QoS 384 * priority. Note that the hal handles reseting 385 * these queues at the needed time. 386 * 387 * XXX PS-Poll 388 */ 389 sc->sc_bhalq = ath_beaconq_setup(ah); 390 if (sc->sc_bhalq == (u_int) -1) { 391 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 392 error = EIO; 393 goto bad2; 394 } 395 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 396 if (sc->sc_cabq == NULL) { 397 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 398 error = EIO; 399 goto bad2; 400 } 401 /* NB: insure BK queue is the lowest priority h/w queue */ 402 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 403 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 404 ieee80211_wme_acnames[WME_AC_BK]); 405 error = EIO; 406 goto bad2; 407 } 408 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 409 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 410 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 411 /* 412 * Not enough hardware tx queues to properly do WME; 413 * just punt and assign them all to the same h/w queue. 414 * We could do a better job of this if, for example, 415 * we allocate queues when we switch from station to 416 * AP mode. 417 */ 418 if (sc->sc_ac2q[WME_AC_VI] != NULL) 419 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 420 if (sc->sc_ac2q[WME_AC_BE] != NULL) 421 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 422 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 423 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 424 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 425 } 426 427 /* 428 * Special case certain configurations. Note the 429 * CAB queue is handled by these specially so don't 430 * include them when checking the txq setup mask. 431 */ 432 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 433 case 0x01: 434 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 435 break; 436 case 0x0f: 437 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 438 break; 439 default: 440 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 441 break; 442 } 443 444 /* 445 * Setup rate control. Some rate control modules 446 * call back to change the anntena state so expose 447 * the necessary entry points. 448 * XXX maybe belongs in struct ath_ratectrl? 449 */ 450 sc->sc_setdefantenna = ath_setdefantenna; 451 sc->sc_rc = ath_rate_attach(sc); 452 if (sc->sc_rc == NULL) { 453 error = EIO; 454 goto bad2; 455 } 456 457 sc->sc_blinking = 0; 458 sc->sc_ledstate = 1; 459 sc->sc_ledon = 0; /* low true */ 460 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 461 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 462 /* 463 * Auto-enable soft led processing for IBM cards and for 464 * 5211 minipci cards. Users can also manually enable/disable 465 * support with a sysctl. 466 */ 467 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 468 if (sc->sc_softled) { 469 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 470 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 471 } 472 473 ifp->if_softc = sc; 474 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 475 ifp->if_start = ath_start; 476 ifp->if_stop = ath_stop; 477 ifp->if_watchdog = ath_watchdog; 478 ifp->if_ioctl = ath_ioctl; 479 ifp->if_init = ath_ifinit; 480 IFQ_SET_READY(&ifp->if_snd); 481 482 ic->ic_ifp = ifp; 483 ic->ic_reset = ath_reset; 484 ic->ic_newassoc = ath_newassoc; 485 ic->ic_updateslot = ath_updateslot; 486 ic->ic_wme.wme_update = ath_wme_update; 487 /* XXX not right but it's not used anywhere important */ 488 ic->ic_phytype = IEEE80211_T_OFDM; 489 ic->ic_opmode = IEEE80211_M_STA; 490 ic->ic_caps = 491 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 492 | IEEE80211_C_HOSTAP /* hostap mode */ 493 | IEEE80211_C_MONITOR /* monitor mode */ 494 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 495 | IEEE80211_C_SHSLOT /* short slot time supported */ 496 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 497 | IEEE80211_C_TXFRAG /* handle tx frags */ 498 ; 499 /* 500 * Query the hal to figure out h/w crypto support. 501 */ 502 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 503 ic->ic_caps |= IEEE80211_C_WEP; 504 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 505 ic->ic_caps |= IEEE80211_C_AES; 506 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 507 ic->ic_caps |= IEEE80211_C_AES_CCM; 508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 509 ic->ic_caps |= IEEE80211_C_CKIP; 510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 511 ic->ic_caps |= IEEE80211_C_TKIP; 512 /* 513 * Check if h/w does the MIC and/or whether the 514 * separate key cache entries are required to 515 * handle both tx+rx MIC keys. 516 */ 517 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 518 ic->ic_caps |= IEEE80211_C_TKIPMIC; 519 520 /* 521 * If the h/w supports storing tx+rx MIC keys 522 * in one cache slot automatically enable use. 523 */ 524 if (ath_hal_hastkipsplit(ah) || 525 !ath_hal_settkipsplit(ah, AH_FALSE)) 526 sc->sc_splitmic = 1; 527 528 /* 529 * If the h/w can do TKIP MIC together with WME then 530 * we use it; otherwise we force the MIC to be done 531 * in software by the net80211 layer. 532 */ 533 if (ath_hal_haswmetkipmic(ah)) 534 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 535 } 536 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 537 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 538 /* 539 * Mark key cache slots associated with global keys 540 * as in use. If we knew TKIP was not to be used we 541 * could leave the +32, +64, and +32+64 slots free. 542 */ 543 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 544 setbit(sc->sc_keymap, i); 545 setbit(sc->sc_keymap, i+64); 546 if (sc->sc_splitmic) { 547 setbit(sc->sc_keymap, i+32); 548 setbit(sc->sc_keymap, i+32+64); 549 } 550 } 551 /* 552 * TPC support can be done either with a global cap or 553 * per-packet support. The latter is not available on 554 * all parts. We're a bit pedantic here as all parts 555 * support a global cap. 556 */ 557 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 558 ic->ic_caps |= IEEE80211_C_TXPMGT; 559 560 /* 561 * Mark WME capability only if we have sufficient 562 * hardware queues to do proper priority scheduling. 563 */ 564 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 565 ic->ic_caps |= IEEE80211_C_WME; 566 /* 567 * Check for misc other capabilities. 568 */ 569 if (ath_hal_hasbursting(ah)) 570 ic->ic_caps |= IEEE80211_C_BURST; 571 572 /* 573 * Indicate we need the 802.11 header padded to a 574 * 32-bit boundary for 4-address and QoS frames. 575 */ 576 ic->ic_flags |= IEEE80211_F_DATAPAD; 577 578 /* 579 * Query the hal about antenna support. 580 */ 581 sc->sc_defant = ath_hal_getdefantenna(ah); 582 583 /* 584 * Not all chips have the VEOL support we want to 585 * use with IBSS beacons; check here for it. 586 */ 587 sc->sc_hasveol = ath_hal_hasveol(ah); 588 589 /* get mac address from hardware */ 590 ath_hal_getmac(ah, ic->ic_myaddr); 591 592 if_attach(ifp); 593 /* call MI attach routine. */ 594 ieee80211_ifattach(ic); 595 /* override default methods */ 596 ic->ic_node_alloc = ath_node_alloc; 597 sc->sc_node_free = ic->ic_node_free; 598 ic->ic_node_free = ath_node_free; 599 ic->ic_node_getrssi = ath_node_getrssi; 600 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 601 ic->ic_recv_mgmt = ath_recv_mgmt; 602 sc->sc_newstate = ic->ic_newstate; 603 ic->ic_newstate = ath_newstate; 604 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 605 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 606 ic->ic_crypto.cs_key_delete = ath_key_delete; 607 ic->ic_crypto.cs_key_set = ath_key_set; 608 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 609 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 610 /* complete initialization */ 611 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 612 613 ath_bpfattach(sc); 614 615 sc->sc_flags |= ATH_ATTACHED; 616 617 /* 618 * Setup dynamic sysctl's now that country code and 619 * regdomain are available from the hal. 620 */ 621 ath_sysctlattach(sc); 622 623 ieee80211_announce(ic); 624 ath_announce(sc); 625 return 0; 626 bad2: 627 ath_tx_cleanup(sc); 628 ath_desc_free(sc); 629 bad: 630 if (ah) 631 ath_hal_detach(ah); 632 /* XXX don't get under the abstraction like this */ 633 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 634 return error; 635 } 636 637 int 638 ath_detach(struct ath_softc *sc) 639 { 640 struct ifnet *ifp = &sc->sc_if; 641 int s; 642 643 if ((sc->sc_flags & ATH_ATTACHED) == 0) 644 return (0); 645 646 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 647 __func__, ifp->if_flags); 648 649 s = splnet(); 650 ath_stop(ifp, 1); 651 bpf_ops->bpf_detach(ifp); 652 /* 653 * NB: the order of these is important: 654 * o call the 802.11 layer before detaching the hal to 655 * insure callbacks into the driver to delete global 656 * key cache entries can be handled 657 * o reclaim the tx queue data structures after calling 658 * the 802.11 layer as we'll get called back to reclaim 659 * node state and potentially want to use them 660 * o to cleanup the tx queues the hal is called, so detach 661 * it last 662 * Other than that, it's straightforward... 663 */ 664 ieee80211_ifdetach(&sc->sc_ic); 665 #ifdef ATH_TX99_DIAG 666 if (sc->sc_tx99 != NULL) 667 sc->sc_tx99->detach(sc->sc_tx99); 668 #endif 669 ath_rate_detach(sc->sc_rc); 670 ath_desc_free(sc); 671 ath_tx_cleanup(sc); 672 sysctl_teardown(&sc->sc_sysctllog); 673 ath_hal_detach(sc->sc_ah); 674 if_detach(ifp); 675 splx(s); 676 677 return 0; 678 } 679 680 void 681 ath_suspend(struct ath_softc *sc) 682 { 683 #if notyet 684 /* 685 * Set the chip in full sleep mode. Note that we are 686 * careful to do this only when bringing the interface 687 * completely to a stop. When the chip is in this state 688 * it must be carefully woken up or references to 689 * registers in the PCI clock domain may freeze the bus 690 * (and system). This varies by chip and is mostly an 691 * issue with newer parts that go to sleep more quickly. 692 */ 693 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 694 #endif 695 } 696 697 bool 698 ath_resume(struct ath_softc *sc) 699 { 700 struct ath_hal *ah = sc->sc_ah; 701 struct ieee80211com *ic = &sc->sc_ic; 702 HAL_STATUS status; 703 int i; 704 705 #if notyet 706 ath_hal_setpower(ah, HAL_PM_AWAKE); 707 #else 708 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 709 #endif 710 711 /* 712 * Reset the key cache since some parts do not 713 * reset the contents on initial power up. 714 */ 715 for (i = 0; i < sc->sc_keymax; i++) 716 ath_hal_keyreset(ah, i); 717 718 ath_hal_resettxqueue(ah, sc->sc_bhalq); 719 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 720 if (ATH_TXQ_SETUP(sc, i)) 721 ath_hal_resettxqueue(ah, i); 722 723 if (sc->sc_softled) { 724 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 725 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 726 } 727 return true; 728 } 729 730 /* 731 * Interrupt handler. Most of the actual processing is deferred. 732 */ 733 int 734 ath_intr(void *arg) 735 { 736 struct ath_softc *sc = arg; 737 struct ifnet *ifp = &sc->sc_if; 738 struct ath_hal *ah = sc->sc_ah; 739 HAL_INT status; 740 741 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 742 /* 743 * The hardware is not ready/present, don't touch anything. 744 * Note this can happen early on if the IRQ is shared. 745 */ 746 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 747 return 0; 748 } 749 750 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 751 return 0; 752 753 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 754 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 755 __func__, ifp->if_flags); 756 ath_hal_getisr(ah, &status); /* clear ISR */ 757 ath_hal_intrset(ah, 0); /* disable further intr's */ 758 return 1; /* XXX */ 759 } 760 /* 761 * Figure out the reason(s) for the interrupt. Note 762 * that the hal returns a pseudo-ISR that may include 763 * bits we haven't explicitly enabled so we mask the 764 * value to insure we only process bits we requested. 765 */ 766 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 767 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 768 status &= sc->sc_imask; /* discard unasked for bits */ 769 if (status & HAL_INT_FATAL) { 770 /* 771 * Fatal errors are unrecoverable. Typically 772 * these are caused by DMA errors. Unfortunately 773 * the exact reason is not (presently) returned 774 * by the hal. 775 */ 776 sc->sc_stats.ast_hardware++; 777 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 778 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 779 } else if (status & HAL_INT_RXORN) { 780 sc->sc_stats.ast_rxorn++; 781 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 782 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 783 } else { 784 if (status & HAL_INT_SWBA) { 785 /* 786 * Software beacon alert--time to send a beacon. 787 * Handle beacon transmission directly; deferring 788 * this is too slow to meet timing constraints 789 * under load. 790 */ 791 ath_beacon_proc(sc, 0); 792 } 793 if (status & HAL_INT_RXEOL) { 794 /* 795 * NB: the hardware should re-read the link when 796 * RXE bit is written, but it doesn't work at 797 * least on older hardware revs. 798 */ 799 sc->sc_stats.ast_rxeol++; 800 sc->sc_rxlink = NULL; 801 } 802 if (status & HAL_INT_TXURN) { 803 sc->sc_stats.ast_txurn++; 804 /* bump tx trigger level */ 805 ath_hal_updatetxtriglevel(ah, AH_TRUE); 806 } 807 if (status & HAL_INT_RX) 808 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 809 if (status & HAL_INT_TX) 810 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 811 if (status & HAL_INT_BMISS) { 812 sc->sc_stats.ast_bmiss++; 813 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 814 } 815 if (status & HAL_INT_MIB) { 816 sc->sc_stats.ast_mib++; 817 /* 818 * Disable interrupts until we service the MIB 819 * interrupt; otherwise it will continue to fire. 820 */ 821 ath_hal_intrset(ah, 0); 822 /* 823 * Let the hal handle the event. We assume it will 824 * clear whatever condition caused the interrupt. 825 */ 826 ath_hal_mibevent(ah, &sc->sc_halstats); 827 ath_hal_intrset(ah, sc->sc_imask); 828 } 829 } 830 return 1; 831 } 832 833 /* Swap transmit descriptor. 834 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 835 * function. 836 */ 837 static inline void 838 ath_desc_swap(struct ath_desc *ds) 839 { 840 #ifdef AH_NEED_DESC_SWAP 841 ds->ds_link = htole32(ds->ds_link); 842 ds->ds_data = htole32(ds->ds_data); 843 ds->ds_ctl0 = htole32(ds->ds_ctl0); 844 ds->ds_ctl1 = htole32(ds->ds_ctl1); 845 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 846 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 847 #endif 848 } 849 850 static void 851 ath_fatal_proc(void *arg, int pending) 852 { 853 struct ath_softc *sc = arg; 854 struct ifnet *ifp = &sc->sc_if; 855 856 if_printf(ifp, "hardware error; resetting\n"); 857 ath_reset(ifp); 858 } 859 860 static void 861 ath_rxorn_proc(void *arg, int pending) 862 { 863 struct ath_softc *sc = arg; 864 struct ifnet *ifp = &sc->sc_if; 865 866 if_printf(ifp, "rx FIFO overrun; resetting\n"); 867 ath_reset(ifp); 868 } 869 870 static void 871 ath_bmiss_proc(void *arg, int pending) 872 { 873 struct ath_softc *sc = arg; 874 struct ieee80211com *ic = &sc->sc_ic; 875 876 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 877 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 878 ("unexpect operating mode %u", ic->ic_opmode)); 879 if (ic->ic_state == IEEE80211_S_RUN) { 880 u_int64_t lastrx = sc->sc_lastrx; 881 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 882 883 DPRINTF(sc, ATH_DEBUG_BEACON, 884 "%s: tsf %" PRIu64 " lastrx %" PRId64 885 " (%" PRIu64 ") bmiss %u\n", 886 __func__, tsf, tsf - lastrx, lastrx, 887 ic->ic_bmisstimeout*1024); 888 /* 889 * Workaround phantom bmiss interrupts by sanity-checking 890 * the time of our last rx'd frame. If it is within the 891 * beacon miss interval then ignore the interrupt. If it's 892 * truly a bmiss we'll get another interrupt soon and that'll 893 * be dispatched up for processing. 894 */ 895 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 896 NET_LOCK_GIANT(); 897 ieee80211_beacon_miss(ic); 898 NET_UNLOCK_GIANT(); 899 } else 900 sc->sc_stats.ast_bmiss_phantom++; 901 } 902 } 903 904 static void 905 ath_radar_proc(void *arg, int pending) 906 { 907 #if 0 908 struct ath_softc *sc = arg; 909 struct ifnet *ifp = &sc->sc_if; 910 struct ath_hal *ah = sc->sc_ah; 911 HAL_CHANNEL hchan; 912 913 if (ath_hal_procdfs(ah, &hchan)) { 914 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 915 hchan.channel, hchan.channelFlags, hchan.privFlags); 916 /* 917 * Initiate channel change. 918 */ 919 /* XXX not yet */ 920 } 921 #endif 922 } 923 924 static u_int 925 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 926 { 927 #define N(a) (sizeof(a) / sizeof(a[0])) 928 static const u_int modeflags[] = { 929 0, /* IEEE80211_MODE_AUTO */ 930 CHANNEL_A, /* IEEE80211_MODE_11A */ 931 CHANNEL_B, /* IEEE80211_MODE_11B */ 932 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 933 0, /* IEEE80211_MODE_FH */ 934 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 935 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 936 }; 937 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 938 939 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 940 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 941 return modeflags[mode]; 942 #undef N 943 } 944 945 static int 946 ath_ifinit(struct ifnet *ifp) 947 { 948 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 949 950 return ath_init(sc); 951 } 952 953 static void 954 ath_settkipmic(struct ath_softc *sc) 955 { 956 struct ieee80211com *ic = &sc->sc_ic; 957 struct ath_hal *ah = sc->sc_ah; 958 959 if ((ic->ic_caps & IEEE80211_C_TKIP) && 960 !(ic->ic_caps & IEEE80211_C_WME_TKIPMIC)) { 961 if (ic->ic_flags & IEEE80211_F_WME) { 962 (void)ath_hal_settkipmic(ah, AH_FALSE); 963 ic->ic_caps &= ~IEEE80211_C_TKIPMIC; 964 } else { 965 (void)ath_hal_settkipmic(ah, AH_TRUE); 966 ic->ic_caps |= IEEE80211_C_TKIPMIC; 967 } 968 } 969 } 970 971 static int 972 ath_init(struct ath_softc *sc) 973 { 974 struct ifnet *ifp = &sc->sc_if; 975 struct ieee80211com *ic = &sc->sc_ic; 976 struct ath_hal *ah = sc->sc_ah; 977 HAL_STATUS status; 978 int error = 0; 979 980 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 981 __func__, ifp->if_flags); 982 983 if (device_is_active(sc->sc_dev)) { 984 ATH_LOCK(sc); 985 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 986 !device_is_active(sc->sc_dev)) 987 return 0; 988 else 989 ATH_LOCK(sc); 990 991 /* 992 * Stop anything previously setup. This is safe 993 * whether this is the first time through or not. 994 */ 995 ath_stop_locked(ifp, 0); 996 997 /* 998 * The basic interface to setting the hardware in a good 999 * state is ``reset''. On return the hardware is known to 1000 * be powered up and with interrupts disabled. This must 1001 * be followed by initialization of the appropriate bits 1002 * and then setup of the interrupt mask. 1003 */ 1004 ath_settkipmic(sc); 1005 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1006 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1007 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1008 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1009 status); 1010 error = EIO; 1011 goto done; 1012 } 1013 1014 /* 1015 * This is needed only to setup initial state 1016 * but it's best done after a reset. 1017 */ 1018 ath_update_txpow(sc); 1019 /* 1020 * Likewise this is set during reset so update 1021 * state cached in the driver. 1022 */ 1023 ath_restore_diversity(sc); 1024 sc->sc_calinterval = 1; 1025 sc->sc_caltries = 0; 1026 1027 /* 1028 * Setup the hardware after reset: the key cache 1029 * is filled as needed and the receive engine is 1030 * set going. Frame transmit is handled entirely 1031 * in the frame output path; there's nothing to do 1032 * here except setup the interrupt mask. 1033 */ 1034 if ((error = ath_startrecv(sc)) != 0) { 1035 if_printf(ifp, "unable to start recv logic\n"); 1036 goto done; 1037 } 1038 1039 /* 1040 * Enable interrupts. 1041 */ 1042 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1043 | HAL_INT_RXEOL | HAL_INT_RXORN 1044 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1045 /* 1046 * Enable MIB interrupts when there are hardware phy counters. 1047 * Note we only do this (at the moment) for station mode. 1048 */ 1049 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1050 sc->sc_imask |= HAL_INT_MIB; 1051 ath_hal_intrset(ah, sc->sc_imask); 1052 1053 ifp->if_flags |= IFF_RUNNING; 1054 ic->ic_state = IEEE80211_S_INIT; 1055 1056 /* 1057 * The hardware should be ready to go now so it's safe 1058 * to kick the 802.11 state machine as it's likely to 1059 * immediately call back to us to send mgmt frames. 1060 */ 1061 ath_chan_change(sc, ic->ic_curchan); 1062 #ifdef ATH_TX99_DIAG 1063 if (sc->sc_tx99 != NULL) 1064 sc->sc_tx99->start(sc->sc_tx99); 1065 else 1066 #endif 1067 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1068 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1069 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1070 } else 1071 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1072 done: 1073 ATH_UNLOCK(sc); 1074 return error; 1075 } 1076 1077 static void 1078 ath_stop_locked(struct ifnet *ifp, int disable) 1079 { 1080 struct ath_softc *sc = ifp->if_softc; 1081 struct ieee80211com *ic = &sc->sc_ic; 1082 struct ath_hal *ah = sc->sc_ah; 1083 1084 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1085 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1086 1087 ATH_LOCK_ASSERT(sc); 1088 if (ifp->if_flags & IFF_RUNNING) { 1089 /* 1090 * Shutdown the hardware and driver: 1091 * reset 802.11 state machine 1092 * turn off timers 1093 * disable interrupts 1094 * turn off the radio 1095 * clear transmit machinery 1096 * clear receive machinery 1097 * drain and release tx queues 1098 * reclaim beacon resources 1099 * power down hardware 1100 * 1101 * Note that some of this work is not possible if the 1102 * hardware is gone (invalid). 1103 */ 1104 #ifdef ATH_TX99_DIAG 1105 if (sc->sc_tx99 != NULL) 1106 sc->sc_tx99->stop(sc->sc_tx99); 1107 #endif 1108 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1109 ifp->if_flags &= ~IFF_RUNNING; 1110 ifp->if_timer = 0; 1111 if (device_is_enabled(sc->sc_dev)) { 1112 if (sc->sc_softled) { 1113 callout_stop(&sc->sc_ledtimer); 1114 ath_hal_gpioset(ah, sc->sc_ledpin, 1115 !sc->sc_ledon); 1116 sc->sc_blinking = 0; 1117 } 1118 ath_hal_intrset(ah, 0); 1119 } 1120 ath_draintxq(sc); 1121 if (device_is_enabled(sc->sc_dev)) { 1122 ath_stoprecv(sc); 1123 ath_hal_phydisable(ah); 1124 } else 1125 sc->sc_rxlink = NULL; 1126 IF_PURGE(&ifp->if_snd); 1127 ath_beacon_free(sc); 1128 } 1129 if (disable) 1130 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 1131 } 1132 1133 static void 1134 ath_stop(struct ifnet *ifp, int disable) 1135 { 1136 struct ath_softc *sc = ifp->if_softc; 1137 1138 ATH_LOCK(sc); 1139 ath_stop_locked(ifp, disable); 1140 ATH_UNLOCK(sc); 1141 } 1142 1143 static void 1144 ath_restore_diversity(struct ath_softc *sc) 1145 { 1146 struct ifnet *ifp = &sc->sc_if; 1147 struct ath_hal *ah = sc->sc_ah; 1148 1149 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1150 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1151 if_printf(ifp, "could not restore diversity setting %d\n", 1152 sc->sc_diversity); 1153 sc->sc_diversity = ath_hal_getdiversity(ah); 1154 } 1155 } 1156 1157 /* 1158 * Reset the hardware w/o losing operational state. This is 1159 * basically a more efficient way of doing ath_stop, ath_init, 1160 * followed by state transitions to the current 802.11 1161 * operational state. Used to recover from various errors and 1162 * to reset or reload hardware state. 1163 */ 1164 int 1165 ath_reset(struct ifnet *ifp) 1166 { 1167 struct ath_softc *sc = ifp->if_softc; 1168 struct ieee80211com *ic = &sc->sc_ic; 1169 struct ath_hal *ah = sc->sc_ah; 1170 struct ieee80211_channel *c; 1171 HAL_STATUS status; 1172 1173 /* 1174 * Convert to a HAL channel description with the flags 1175 * constrained to reflect the current operating mode. 1176 */ 1177 c = ic->ic_curchan; 1178 sc->sc_curchan.channel = c->ic_freq; 1179 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1180 1181 ath_hal_intrset(ah, 0); /* disable interrupts */ 1182 ath_draintxq(sc); /* stop xmit side */ 1183 ath_stoprecv(sc); /* stop recv side */ 1184 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1185 /* NB: indicate channel change so we do a full reset */ 1186 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1187 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1188 __func__, status); 1189 ath_update_txpow(sc); /* update tx power state */ 1190 ath_restore_diversity(sc); 1191 sc->sc_calinterval = 1; 1192 sc->sc_caltries = 0; 1193 if (ath_startrecv(sc) != 0) /* restart recv */ 1194 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1195 /* 1196 * We may be doing a reset in response to an ioctl 1197 * that changes the channel so update any state that 1198 * might change as a result. 1199 */ 1200 ath_chan_change(sc, c); 1201 if (ic->ic_state == IEEE80211_S_RUN) 1202 ath_beacon_config(sc); /* restart beacons */ 1203 ath_hal_intrset(ah, sc->sc_imask); 1204 1205 ath_start(ifp); /* restart xmit */ 1206 return 0; 1207 } 1208 1209 /* 1210 * Cleanup driver resources when we run out of buffers 1211 * while processing fragments; return the tx buffers 1212 * allocated and drop node references. 1213 */ 1214 static void 1215 ath_txfrag_cleanup(struct ath_softc *sc, 1216 ath_bufhead *frags, struct ieee80211_node *ni) 1217 { 1218 struct ath_buf *bf; 1219 1220 ATH_TXBUF_LOCK_ASSERT(sc); 1221 1222 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1223 STAILQ_REMOVE_HEAD(frags, bf_list); 1224 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1225 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1226 ieee80211_node_decref(ni); 1227 } 1228 } 1229 1230 /* 1231 * Setup xmit of a fragmented frame. Allocate a buffer 1232 * for each frag and bump the node reference count to 1233 * reflect the held reference to be setup by ath_tx_start. 1234 */ 1235 static int 1236 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1237 struct mbuf *m0, struct ieee80211_node *ni) 1238 { 1239 struct mbuf *m; 1240 struct ath_buf *bf; 1241 1242 ATH_TXBUF_LOCK(sc); 1243 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1244 bf = STAILQ_FIRST(&sc->sc_txbuf); 1245 if (bf == NULL) { /* out of buffers, cleanup */ 1246 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1247 __func__); 1248 sc->sc_if.if_flags |= IFF_OACTIVE; 1249 ath_txfrag_cleanup(sc, frags, ni); 1250 break; 1251 } 1252 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1253 ieee80211_node_incref(ni); 1254 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1255 } 1256 ATH_TXBUF_UNLOCK(sc); 1257 1258 return !STAILQ_EMPTY(frags); 1259 } 1260 1261 static void 1262 ath_start(struct ifnet *ifp) 1263 { 1264 struct ath_softc *sc = ifp->if_softc; 1265 struct ath_hal *ah = sc->sc_ah; 1266 struct ieee80211com *ic = &sc->sc_ic; 1267 struct ieee80211_node *ni; 1268 struct ath_buf *bf; 1269 struct mbuf *m, *next; 1270 struct ieee80211_frame *wh; 1271 struct ether_header *eh; 1272 ath_bufhead frags; 1273 1274 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1275 !device_is_active(sc->sc_dev)) 1276 return; 1277 for (;;) { 1278 /* 1279 * Grab a TX buffer and associated resources. 1280 */ 1281 ATH_TXBUF_LOCK(sc); 1282 bf = STAILQ_FIRST(&sc->sc_txbuf); 1283 if (bf != NULL) 1284 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1285 ATH_TXBUF_UNLOCK(sc); 1286 if (bf == NULL) { 1287 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1288 __func__); 1289 sc->sc_stats.ast_tx_qstop++; 1290 ifp->if_flags |= IFF_OACTIVE; 1291 break; 1292 } 1293 /* 1294 * Poll the management queue for frames; they 1295 * have priority over normal data frames. 1296 */ 1297 IF_DEQUEUE(&ic->ic_mgtq, m); 1298 if (m == NULL) { 1299 /* 1300 * No data frames go out unless we're associated. 1301 */ 1302 if (ic->ic_state != IEEE80211_S_RUN) { 1303 DPRINTF(sc, ATH_DEBUG_XMIT, 1304 "%s: discard data packet, state %s\n", 1305 __func__, 1306 ieee80211_state_name[ic->ic_state]); 1307 sc->sc_stats.ast_tx_discard++; 1308 ATH_TXBUF_LOCK(sc); 1309 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1310 ATH_TXBUF_UNLOCK(sc); 1311 break; 1312 } 1313 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1314 if (m == NULL) { 1315 ATH_TXBUF_LOCK(sc); 1316 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1317 ATH_TXBUF_UNLOCK(sc); 1318 break; 1319 } 1320 STAILQ_INIT(&frags); 1321 /* 1322 * Find the node for the destination so we can do 1323 * things like power save and fast frames aggregation. 1324 */ 1325 if (m->m_len < sizeof(struct ether_header) && 1326 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1327 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1328 ni = NULL; 1329 goto bad; 1330 } 1331 eh = mtod(m, struct ether_header *); 1332 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1333 if (ni == NULL) { 1334 /* NB: ieee80211_find_txnode does stat+msg */ 1335 m_freem(m); 1336 goto bad; 1337 } 1338 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1339 (m->m_flags & M_PWR_SAV) == 0) { 1340 /* 1341 * Station in power save mode; pass the frame 1342 * to the 802.11 layer and continue. We'll get 1343 * the frame back when the time is right. 1344 */ 1345 ieee80211_pwrsave(ic, ni, m); 1346 goto reclaim; 1347 } 1348 /* calculate priority so we can find the tx queue */ 1349 if (ieee80211_classify(ic, m, ni)) { 1350 DPRINTF(sc, ATH_DEBUG_XMIT, 1351 "%s: discard, classification failure\n", 1352 __func__); 1353 m_freem(m); 1354 goto bad; 1355 } 1356 ifp->if_opackets++; 1357 1358 if (ifp->if_bpf) 1359 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1360 /* 1361 * Encapsulate the packet in prep for transmission. 1362 */ 1363 m = ieee80211_encap(ic, m, ni); 1364 if (m == NULL) { 1365 DPRINTF(sc, ATH_DEBUG_XMIT, 1366 "%s: encapsulation failure\n", 1367 __func__); 1368 sc->sc_stats.ast_tx_encap++; 1369 goto bad; 1370 } 1371 /* 1372 * Check for fragmentation. If this has frame 1373 * has been broken up verify we have enough 1374 * buffers to send all the fragments so all 1375 * go out or none... 1376 */ 1377 if ((m->m_flags & M_FRAG) && 1378 !ath_txfrag_setup(sc, &frags, m, ni)) { 1379 DPRINTF(sc, ATH_DEBUG_ANY, 1380 "%s: out of txfrag buffers\n", __func__); 1381 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1382 ath_freetx(m); 1383 goto bad; 1384 } 1385 } else { 1386 /* 1387 * Hack! The referenced node pointer is in the 1388 * rcvif field of the packet header. This is 1389 * placed there by ieee80211_mgmt_output because 1390 * we need to hold the reference with the frame 1391 * and there's no other way (other than packet 1392 * tags which we consider too expensive to use) 1393 * to pass it along. 1394 */ 1395 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1396 m->m_pkthdr.rcvif = NULL; 1397 1398 wh = mtod(m, struct ieee80211_frame *); 1399 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1400 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1401 /* fill time stamp */ 1402 u_int64_t tsf; 1403 u_int32_t *tstamp; 1404 1405 tsf = ath_hal_gettsf64(ah); 1406 /* XXX: adjust 100us delay to xmit */ 1407 tsf += 100; 1408 tstamp = (u_int32_t *)&wh[1]; 1409 tstamp[0] = htole32(tsf & 0xffffffff); 1410 tstamp[1] = htole32(tsf >> 32); 1411 } 1412 sc->sc_stats.ast_tx_mgmt++; 1413 } 1414 1415 nextfrag: 1416 next = m->m_nextpkt; 1417 if (ath_tx_start(sc, ni, bf, m)) { 1418 bad: 1419 ifp->if_oerrors++; 1420 reclaim: 1421 ATH_TXBUF_LOCK(sc); 1422 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1423 ath_txfrag_cleanup(sc, &frags, ni); 1424 ATH_TXBUF_UNLOCK(sc); 1425 if (ni != NULL) 1426 ieee80211_free_node(ni); 1427 continue; 1428 } 1429 if (next != NULL) { 1430 m = next; 1431 bf = STAILQ_FIRST(&frags); 1432 KASSERT(bf != NULL, ("no buf for txfrag")); 1433 STAILQ_REMOVE_HEAD(&frags, bf_list); 1434 goto nextfrag; 1435 } 1436 1437 ifp->if_timer = 1; 1438 } 1439 } 1440 1441 static int 1442 ath_media_change(struct ifnet *ifp) 1443 { 1444 #define IS_UP(ifp) \ 1445 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1446 int error; 1447 1448 error = ieee80211_media_change(ifp); 1449 if (error == ENETRESET) { 1450 if (IS_UP(ifp)) 1451 ath_init(ifp->if_softc); /* XXX lose error */ 1452 error = 0; 1453 } 1454 return error; 1455 #undef IS_UP 1456 } 1457 1458 #ifdef AR_DEBUG 1459 static void 1460 ath_keyprint(const char *tag, u_int ix, 1461 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1462 { 1463 static const char *ciphers[] = { 1464 "WEP", 1465 "AES-OCB", 1466 "AES-CCM", 1467 "CKIP", 1468 "TKIP", 1469 "CLR", 1470 }; 1471 int i, n; 1472 1473 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1474 for (i = 0, n = hk->kv_len; i < n; i++) 1475 printf("%02x", hk->kv_val[i]); 1476 printf(" mac %s", ether_sprintf(mac)); 1477 if (hk->kv_type == HAL_CIPHER_TKIP) { 1478 printf(" mic "); 1479 for (i = 0; i < sizeof(hk->kv_mic); i++) 1480 printf("%02x", hk->kv_mic[i]); 1481 } 1482 printf("\n"); 1483 } 1484 #endif 1485 1486 /* 1487 * Set a TKIP key into the hardware. This handles the 1488 * potential distribution of key state to multiple key 1489 * cache slots for TKIP. 1490 */ 1491 static int 1492 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1493 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1494 { 1495 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1496 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1497 struct ath_hal *ah = sc->sc_ah; 1498 1499 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1500 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1501 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1502 if (sc->sc_splitmic) { 1503 /* 1504 * TX key goes at first index, RX key at the rx index. 1505 * The hal handles the MIC keys at index+64. 1506 */ 1507 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1508 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1509 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1510 zerobssid)) 1511 return 0; 1512 1513 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1514 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1515 /* XXX delete tx key on failure? */ 1516 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1517 hk, mac); 1518 } else { 1519 /* 1520 * Room for both TX+RX MIC keys in one key cache 1521 * slot, just set key at the first index; the HAL 1522 * will handle the reset. 1523 */ 1524 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1525 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1526 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1527 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1528 } 1529 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1530 if (sc->sc_splitmic) { 1531 /* 1532 * NB: must pass MIC key in expected location when 1533 * the keycache only holds one MIC key per entry. 1534 */ 1535 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1536 } else 1537 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1538 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1539 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1540 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1541 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1542 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1543 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1544 } 1545 return 0; 1546 #undef IEEE80211_KEY_XR 1547 } 1548 1549 /* 1550 * Set a net80211 key into the hardware. This handles the 1551 * potential distribution of key state to multiple key 1552 * cache slots for TKIP with hardware MIC support. 1553 */ 1554 static int 1555 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1556 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1557 struct ieee80211_node *bss) 1558 { 1559 #define N(a) (sizeof(a)/sizeof(a[0])) 1560 static const u_int8_t ciphermap[] = { 1561 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1562 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1563 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1564 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1565 (u_int8_t) -1, /* 4 is not allocated */ 1566 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1567 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1568 }; 1569 struct ath_hal *ah = sc->sc_ah; 1570 const struct ieee80211_cipher *cip = k->wk_cipher; 1571 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1572 const u_int8_t *mac; 1573 HAL_KEYVAL hk; 1574 1575 memset(&hk, 0, sizeof(hk)); 1576 /* 1577 * Software crypto uses a "clear key" so non-crypto 1578 * state kept in the key cache are maintained and 1579 * so that rx frames have an entry to match. 1580 */ 1581 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1582 KASSERT(cip->ic_cipher < N(ciphermap), 1583 ("invalid cipher type %u", cip->ic_cipher)); 1584 hk.kv_type = ciphermap[cip->ic_cipher]; 1585 hk.kv_len = k->wk_keylen; 1586 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1587 } else 1588 hk.kv_type = HAL_CIPHER_CLR; 1589 1590 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1591 /* 1592 * Group keys on hardware that supports multicast frame 1593 * key search use a mac that is the sender's address with 1594 * the high bit set instead of the app-specified address. 1595 */ 1596 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1597 gmac[0] |= 0x80; 1598 mac = gmac; 1599 } else 1600 mac = mac0; 1601 1602 if ((hk.kv_type == HAL_CIPHER_TKIP && 1603 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0)) { 1604 return ath_keyset_tkip(sc, k, &hk, mac); 1605 } else { 1606 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1607 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1608 } 1609 #undef N 1610 } 1611 1612 /* 1613 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1614 * each key, one for decrypt/encrypt and the other for the MIC. 1615 */ 1616 static u_int16_t 1617 key_alloc_2pair(struct ath_softc *sc, 1618 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1619 { 1620 #define N(a) (sizeof(a)/sizeof(a[0])) 1621 u_int i, keyix; 1622 1623 KASSERT(sc->sc_splitmic, ("key cache !split")); 1624 /* XXX could optimize */ 1625 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1626 u_int8_t b = sc->sc_keymap[i]; 1627 if (b != 0xff) { 1628 /* 1629 * One or more slots in this byte are free. 1630 */ 1631 keyix = i*NBBY; 1632 while (b & 1) { 1633 again: 1634 keyix++; 1635 b >>= 1; 1636 } 1637 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1638 if (isset(sc->sc_keymap, keyix+32) || 1639 isset(sc->sc_keymap, keyix+64) || 1640 isset(sc->sc_keymap, keyix+32+64)) { 1641 /* full pair unavailable */ 1642 /* XXX statistic */ 1643 if (keyix == (i+1)*NBBY) { 1644 /* no slots were appropriate, advance */ 1645 continue; 1646 } 1647 goto again; 1648 } 1649 setbit(sc->sc_keymap, keyix); 1650 setbit(sc->sc_keymap, keyix+64); 1651 setbit(sc->sc_keymap, keyix+32); 1652 setbit(sc->sc_keymap, keyix+32+64); 1653 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1654 "%s: key pair %u,%u %u,%u\n", 1655 __func__, keyix, keyix+64, 1656 keyix+32, keyix+32+64); 1657 *txkeyix = keyix; 1658 *rxkeyix = keyix+32; 1659 return keyix; 1660 } 1661 } 1662 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1663 return IEEE80211_KEYIX_NONE; 1664 #undef N 1665 } 1666 1667 /* 1668 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1669 * each key, one for decrypt/encrypt and the other for the MIC. 1670 */ 1671 static int 1672 key_alloc_pair(struct ath_softc *sc, ieee80211_keyix *txkeyix, 1673 ieee80211_keyix *rxkeyix) 1674 { 1675 #define N(a) (sizeof(a)/sizeof(a[0])) 1676 u_int i, keyix; 1677 1678 KASSERT(!sc->sc_splitmic, ("key cache split")); 1679 /* XXX could optimize */ 1680 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1681 uint8_t b = sc->sc_keymap[i]; 1682 if (b != 0xff) { 1683 /* 1684 * One or more slots in this byte are free. 1685 */ 1686 keyix = i*NBBY; 1687 while (b & 1) { 1688 again: 1689 keyix++; 1690 b >>= 1; 1691 } 1692 if (isset(sc->sc_keymap, keyix+64)) { 1693 /* full pair unavailable */ 1694 /* XXX statistic */ 1695 if (keyix == (i+1)*NBBY) { 1696 /* no slots were appropriate, advance */ 1697 continue; 1698 } 1699 goto again; 1700 } 1701 setbit(sc->sc_keymap, keyix); 1702 setbit(sc->sc_keymap, keyix+64); 1703 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1704 "%s: key pair %u,%u\n", 1705 __func__, keyix, keyix+64); 1706 *txkeyix = *rxkeyix = keyix; 1707 return 1; 1708 } 1709 } 1710 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1711 return 0; 1712 #undef N 1713 } 1714 1715 /* 1716 * Allocate a single key cache slot. 1717 */ 1718 static int 1719 key_alloc_single(struct ath_softc *sc, 1720 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1721 { 1722 #define N(a) (sizeof(a)/sizeof(a[0])) 1723 u_int i, keyix; 1724 1725 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1726 for (i = 0; i < N(sc->sc_keymap); i++) { 1727 u_int8_t b = sc->sc_keymap[i]; 1728 if (b != 0xff) { 1729 /* 1730 * One or more slots are free. 1731 */ 1732 keyix = i*NBBY; 1733 while (b & 1) 1734 keyix++, b >>= 1; 1735 setbit(sc->sc_keymap, keyix); 1736 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1737 __func__, keyix); 1738 *txkeyix = *rxkeyix = keyix; 1739 return 1; 1740 } 1741 } 1742 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1743 return 0; 1744 #undef N 1745 } 1746 1747 /* 1748 * Allocate one or more key cache slots for a uniacst key. The 1749 * key itself is needed only to identify the cipher. For hardware 1750 * TKIP with split cipher+MIC keys we allocate two key cache slot 1751 * pairs so that we can setup separate TX and RX MIC keys. Note 1752 * that the MIC key for a TKIP key at slot i is assumed by the 1753 * hardware to be at slot i+64. This limits TKIP keys to the first 1754 * 64 entries. 1755 */ 1756 static int 1757 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1758 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1759 { 1760 struct ath_softc *sc = ic->ic_ifp->if_softc; 1761 1762 /* 1763 * Group key allocation must be handled specially for 1764 * parts that do not support multicast key cache search 1765 * functionality. For those parts the key id must match 1766 * the h/w key index so lookups find the right key. On 1767 * parts w/ the key search facility we install the sender's 1768 * mac address (with the high bit set) and let the hardware 1769 * find the key w/o using the key id. This is preferred as 1770 * it permits us to support multiple users for adhoc and/or 1771 * multi-station operation. 1772 */ 1773 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1774 if (!(&ic->ic_nw_keys[0] <= k && 1775 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1776 /* should not happen */ 1777 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1778 "%s: bogus group key\n", __func__); 1779 return 0; 1780 } 1781 /* 1782 * XXX we pre-allocate the global keys so 1783 * have no way to check if they've already been allocated. 1784 */ 1785 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1786 return 1; 1787 } 1788 1789 /* 1790 * We allocate two pair for TKIP when using the h/w to do 1791 * the MIC. For everything else, including software crypto, 1792 * we allocate a single entry. Note that s/w crypto requires 1793 * a pass-through slot on the 5211 and 5212. The 5210 does 1794 * not support pass-through cache entries and we map all 1795 * those requests to slot 0. 1796 */ 1797 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1798 return key_alloc_single(sc, keyix, rxkeyix); 1799 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1800 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1801 if (sc->sc_splitmic) 1802 return key_alloc_2pair(sc, keyix, rxkeyix); 1803 else 1804 return key_alloc_pair(sc, keyix, rxkeyix); 1805 } else { 1806 return key_alloc_single(sc, keyix, rxkeyix); 1807 } 1808 } 1809 1810 /* 1811 * Delete an entry in the key cache allocated by ath_key_alloc. 1812 */ 1813 static int 1814 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1815 { 1816 struct ath_softc *sc = ic->ic_ifp->if_softc; 1817 struct ath_hal *ah = sc->sc_ah; 1818 const struct ieee80211_cipher *cip = k->wk_cipher; 1819 u_int keyix = k->wk_keyix; 1820 1821 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1822 1823 if (!device_has_power(sc->sc_dev)) { 1824 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1825 k->wk_keyix); 1826 } 1827 1828 ath_hal_keyreset(ah, keyix); 1829 /* 1830 * Handle split tx/rx keying required for TKIP with h/w MIC. 1831 */ 1832 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1833 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1834 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1835 if (keyix >= IEEE80211_WEP_NKID) { 1836 /* 1837 * Don't touch keymap entries for global keys so 1838 * they are never considered for dynamic allocation. 1839 */ 1840 clrbit(sc->sc_keymap, keyix); 1841 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1842 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1843 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1844 if (sc->sc_splitmic) { 1845 /* +32 for RX key, +32+64 for RX key MIC */ 1846 clrbit(sc->sc_keymap, keyix+32); 1847 clrbit(sc->sc_keymap, keyix+32+64); 1848 } 1849 } 1850 } 1851 return 1; 1852 } 1853 1854 /* 1855 * Set the key cache contents for the specified key. Key cache 1856 * slot(s) must already have been allocated by ath_key_alloc. 1857 */ 1858 static int 1859 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1860 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1861 { 1862 struct ath_softc *sc = ic->ic_ifp->if_softc; 1863 1864 if (!device_has_power(sc->sc_dev)) { 1865 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1866 k->wk_keyix); 1867 } 1868 return ath_keyset(sc, k, mac, ic->ic_bss); 1869 } 1870 1871 /* 1872 * Block/unblock tx+rx processing while a key change is done. 1873 * We assume the caller serializes key management operations 1874 * so we only need to worry about synchronization with other 1875 * uses that originate in the driver. 1876 */ 1877 static void 1878 ath_key_update_begin(struct ieee80211com *ic) 1879 { 1880 struct ifnet *ifp = ic->ic_ifp; 1881 struct ath_softc *sc = ifp->if_softc; 1882 1883 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1884 #if 0 1885 tasklet_disable(&sc->sc_rxtq); 1886 #endif 1887 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1888 } 1889 1890 static void 1891 ath_key_update_end(struct ieee80211com *ic) 1892 { 1893 struct ifnet *ifp = ic->ic_ifp; 1894 struct ath_softc *sc = ifp->if_softc; 1895 1896 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1897 IF_UNLOCK(&ifp->if_snd); 1898 #if 0 1899 tasklet_enable(&sc->sc_rxtq); 1900 #endif 1901 } 1902 1903 /* 1904 * Calculate the receive filter according to the 1905 * operating mode and state: 1906 * 1907 * o always accept unicast, broadcast, and multicast traffic 1908 * o maintain current state of phy error reception (the hal 1909 * may enable phy error frames for noise immunity work) 1910 * o probe request frames are accepted only when operating in 1911 * hostap, adhoc, or monitor modes 1912 * o enable promiscuous mode according to the interface state 1913 * o accept beacons: 1914 * - when operating in adhoc mode so the 802.11 layer creates 1915 * node table entries for peers, 1916 * - when operating in station mode for collecting rssi data when 1917 * the station is otherwise quiet, or 1918 * - when scanning 1919 */ 1920 static u_int32_t 1921 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1922 { 1923 struct ieee80211com *ic = &sc->sc_ic; 1924 struct ath_hal *ah = sc->sc_ah; 1925 struct ifnet *ifp = &sc->sc_if; 1926 u_int32_t rfilt; 1927 1928 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1929 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1930 if (ic->ic_opmode != IEEE80211_M_STA) 1931 rfilt |= HAL_RX_FILTER_PROBEREQ; 1932 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1933 (ifp->if_flags & IFF_PROMISC)) 1934 rfilt |= HAL_RX_FILTER_PROM; 1935 if (ifp->if_flags & IFF_PROMISC) 1936 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1937 if (ic->ic_opmode == IEEE80211_M_STA || 1938 ic->ic_opmode == IEEE80211_M_IBSS || 1939 state == IEEE80211_S_SCAN) 1940 rfilt |= HAL_RX_FILTER_BEACON; 1941 return rfilt; 1942 } 1943 1944 static void 1945 ath_mode_init(struct ath_softc *sc) 1946 { 1947 struct ifnet *ifp = &sc->sc_if; 1948 struct ieee80211com *ic = &sc->sc_ic; 1949 struct ath_hal *ah = sc->sc_ah; 1950 struct ether_multi *enm; 1951 struct ether_multistep estep; 1952 u_int32_t rfilt, mfilt[2], val; 1953 int i; 1954 uint8_t pos; 1955 1956 /* configure rx filter */ 1957 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1958 ath_hal_setrxfilter(ah, rfilt); 1959 1960 /* configure operational mode */ 1961 ath_hal_setopmode(ah); 1962 1963 /* Write keys to hardware; it may have been powered down. */ 1964 ath_key_update_begin(ic); 1965 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1966 ath_key_set(ic, 1967 &ic->ic_crypto.cs_nw_keys[i], 1968 ic->ic_myaddr); 1969 } 1970 ath_key_update_end(ic); 1971 1972 /* 1973 * Handle any link-level address change. Note that we only 1974 * need to force ic_myaddr; any other addresses are handled 1975 * as a byproduct of the ifnet code marking the interface 1976 * down then up. 1977 * 1978 * XXX should get from lladdr instead of arpcom but that's more work 1979 */ 1980 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1981 ath_hal_setmac(ah, ic->ic_myaddr); 1982 1983 /* calculate and install multicast filter */ 1984 ifp->if_flags &= ~IFF_ALLMULTI; 1985 mfilt[0] = mfilt[1] = 0; 1986 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1987 while (enm != NULL) { 1988 void *dl; 1989 /* XXX Punt on ranges. */ 1990 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1991 mfilt[0] = mfilt[1] = 0xffffffff; 1992 ifp->if_flags |= IFF_ALLMULTI; 1993 break; 1994 } 1995 dl = enm->enm_addrlo; 1996 val = LE_READ_4((char *)dl + 0); 1997 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1998 val = LE_READ_4((char *)dl + 3); 1999 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2000 pos &= 0x3f; 2001 mfilt[pos / 32] |= (1 << (pos % 32)); 2002 2003 ETHER_NEXT_MULTI(estep, enm); 2004 } 2005 2006 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 2007 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 2008 __func__, rfilt, mfilt[0], mfilt[1]); 2009 } 2010 2011 /* 2012 * Set the slot time based on the current setting. 2013 */ 2014 static void 2015 ath_setslottime(struct ath_softc *sc) 2016 { 2017 struct ieee80211com *ic = &sc->sc_ic; 2018 struct ath_hal *ah = sc->sc_ah; 2019 2020 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2021 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2022 else 2023 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2024 sc->sc_updateslot = OK; 2025 } 2026 2027 /* 2028 * Callback from the 802.11 layer to update the 2029 * slot time based on the current setting. 2030 */ 2031 static void 2032 ath_updateslot(struct ifnet *ifp) 2033 { 2034 struct ath_softc *sc = ifp->if_softc; 2035 struct ieee80211com *ic = &sc->sc_ic; 2036 2037 /* 2038 * When not coordinating the BSS, change the hardware 2039 * immediately. For other operation we defer the change 2040 * until beacon updates have propagated to the stations. 2041 */ 2042 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2043 sc->sc_updateslot = UPDATE; 2044 else 2045 ath_setslottime(sc); 2046 } 2047 2048 /* 2049 * Setup a h/w transmit queue for beacons. 2050 */ 2051 static int 2052 ath_beaconq_setup(struct ath_hal *ah) 2053 { 2054 HAL_TXQ_INFO qi; 2055 2056 memset(&qi, 0, sizeof(qi)); 2057 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2058 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2059 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2060 /* NB: for dynamic turbo, don't enable any other interrupts */ 2061 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2062 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2063 } 2064 2065 /* 2066 * Setup the transmit queue parameters for the beacon queue. 2067 */ 2068 static int 2069 ath_beaconq_config(struct ath_softc *sc) 2070 { 2071 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2072 struct ieee80211com *ic = &sc->sc_ic; 2073 struct ath_hal *ah = sc->sc_ah; 2074 HAL_TXQ_INFO qi; 2075 2076 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2077 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2078 /* 2079 * Always burst out beacon and CAB traffic. 2080 */ 2081 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2082 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2083 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2084 } else { 2085 struct wmeParams *wmep = 2086 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2087 /* 2088 * Adhoc mode; important thing is to use 2x cwmin. 2089 */ 2090 qi.tqi_aifs = wmep->wmep_aifsn; 2091 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2092 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2093 } 2094 2095 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2096 device_printf(sc->sc_dev, "unable to update parameters for " 2097 "beacon hardware queue!\n"); 2098 return 0; 2099 } else { 2100 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2101 return 1; 2102 } 2103 #undef ATH_EXPONENT_TO_VALUE 2104 } 2105 2106 /* 2107 * Allocate and setup an initial beacon frame. 2108 */ 2109 static int 2110 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2111 { 2112 struct ieee80211com *ic = ni->ni_ic; 2113 struct ath_buf *bf; 2114 struct mbuf *m; 2115 int error; 2116 2117 bf = STAILQ_FIRST(&sc->sc_bbuf); 2118 if (bf == NULL) { 2119 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2120 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2121 return ENOMEM; /* XXX */ 2122 } 2123 /* 2124 * NB: the beacon data buffer must be 32-bit aligned; 2125 * we assume the mbuf routines will return us something 2126 * with this alignment (perhaps should assert). 2127 */ 2128 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2129 if (m == NULL) { 2130 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2131 __func__); 2132 sc->sc_stats.ast_be_nombuf++; 2133 return ENOMEM; 2134 } 2135 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2136 BUS_DMA_NOWAIT); 2137 if (error == 0) { 2138 bf->bf_m = m; 2139 bf->bf_node = ieee80211_ref_node(ni); 2140 } else { 2141 m_freem(m); 2142 } 2143 return error; 2144 } 2145 2146 /* 2147 * Setup the beacon frame for transmit. 2148 */ 2149 static void 2150 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2151 { 2152 #define USE_SHPREAMBLE(_ic) \ 2153 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2154 == IEEE80211_F_SHPREAMBLE) 2155 struct ieee80211_node *ni = bf->bf_node; 2156 struct ieee80211com *ic = ni->ni_ic; 2157 struct mbuf *m = bf->bf_m; 2158 struct ath_hal *ah = sc->sc_ah; 2159 struct ath_desc *ds; 2160 int flags, antenna; 2161 const HAL_RATE_TABLE *rt; 2162 u_int8_t rix, rate; 2163 2164 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2165 __func__, m, m->m_len); 2166 2167 /* setup descriptors */ 2168 ds = bf->bf_desc; 2169 2170 flags = HAL_TXDESC_NOACK; 2171 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2172 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2173 flags |= HAL_TXDESC_VEOL; 2174 /* 2175 * Let hardware handle antenna switching unless 2176 * the user has selected a transmit antenna 2177 * (sc_txantenna is not 0). 2178 */ 2179 antenna = sc->sc_txantenna; 2180 } else { 2181 ds->ds_link = 0; 2182 /* 2183 * Switch antenna every 4 beacons, unless the user 2184 * has selected a transmit antenna (sc_txantenna 2185 * is not 0). 2186 * 2187 * XXX assumes two antenna 2188 */ 2189 if (sc->sc_txantenna == 0) 2190 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2191 else 2192 antenna = sc->sc_txantenna; 2193 } 2194 2195 KASSERT(bf->bf_nseg == 1, 2196 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2197 ds->ds_data = bf->bf_segs[0].ds_addr; 2198 /* 2199 * Calculate rate code. 2200 * XXX everything at min xmit rate 2201 */ 2202 rix = sc->sc_minrateix; 2203 rt = sc->sc_currates; 2204 rate = rt->info[rix].rateCode; 2205 if (USE_SHPREAMBLE(ic)) 2206 rate |= rt->info[rix].shortPreamble; 2207 ath_hal_setuptxdesc(ah, ds 2208 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2209 , sizeof(struct ieee80211_frame)/* header length */ 2210 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2211 , ni->ni_txpower /* txpower XXX */ 2212 , rate, 1 /* series 0 rate/tries */ 2213 , HAL_TXKEYIX_INVALID /* no encryption */ 2214 , antenna /* antenna mode */ 2215 , flags /* no ack, veol for beacons */ 2216 , 0 /* rts/cts rate */ 2217 , 0 /* rts/cts duration */ 2218 ); 2219 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2220 ath_hal_filltxdesc(ah, ds 2221 , roundup(m->m_len, 4) /* buffer length */ 2222 , AH_TRUE /* first segment */ 2223 , AH_TRUE /* last segment */ 2224 , ds /* first descriptor */ 2225 ); 2226 2227 /* NB: The desc swap function becomes void, if descriptor swapping 2228 * is not enabled 2229 */ 2230 ath_desc_swap(ds); 2231 2232 #undef USE_SHPREAMBLE 2233 } 2234 2235 /* 2236 * Transmit a beacon frame at SWBA. Dynamic updates to the 2237 * frame contents are done as needed and the slot time is 2238 * also adjusted based on current state. 2239 */ 2240 static void 2241 ath_beacon_proc(void *arg, int pending) 2242 { 2243 struct ath_softc *sc = arg; 2244 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2245 struct ieee80211_node *ni = bf->bf_node; 2246 struct ieee80211com *ic = ni->ni_ic; 2247 struct ath_hal *ah = sc->sc_ah; 2248 struct mbuf *m; 2249 int ncabq, error, otherant; 2250 2251 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2252 __func__, pending); 2253 2254 if (ic->ic_opmode == IEEE80211_M_STA || 2255 ic->ic_opmode == IEEE80211_M_MONITOR || 2256 bf == NULL || bf->bf_m == NULL) { 2257 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2258 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2259 return; 2260 } 2261 /* 2262 * Check if the previous beacon has gone out. If 2263 * not don't try to post another, skip this period 2264 * and wait for the next. Missed beacons indicate 2265 * a problem and should not occur. If we miss too 2266 * many consecutive beacons reset the device. 2267 */ 2268 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2269 sc->sc_bmisscount++; 2270 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2271 "%s: missed %u consecutive beacons\n", 2272 __func__, sc->sc_bmisscount); 2273 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2274 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2275 return; 2276 } 2277 if (sc->sc_bmisscount != 0) { 2278 DPRINTF(sc, ATH_DEBUG_BEACON, 2279 "%s: resume beacon xmit after %u misses\n", 2280 __func__, sc->sc_bmisscount); 2281 sc->sc_bmisscount = 0; 2282 } 2283 2284 /* 2285 * Update dynamic beacon contents. If this returns 2286 * non-zero then we need to remap the memory because 2287 * the beacon frame changed size (probably because 2288 * of the TIM bitmap). 2289 */ 2290 m = bf->bf_m; 2291 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2292 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2293 /* XXX too conservative? */ 2294 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2295 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2296 BUS_DMA_NOWAIT); 2297 if (error != 0) { 2298 if_printf(&sc->sc_if, 2299 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2300 __func__, error); 2301 return; 2302 } 2303 } 2304 2305 /* 2306 * Handle slot time change when a non-ERP station joins/leaves 2307 * an 11g network. The 802.11 layer notifies us via callback, 2308 * we mark updateslot, then wait one beacon before effecting 2309 * the change. This gives associated stations at least one 2310 * beacon interval to note the state change. 2311 */ 2312 /* XXX locking */ 2313 if (sc->sc_updateslot == UPDATE) 2314 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2315 else if (sc->sc_updateslot == COMMIT) 2316 ath_setslottime(sc); /* commit change to h/w */ 2317 2318 /* 2319 * Check recent per-antenna transmit statistics and flip 2320 * the default antenna if noticeably more frames went out 2321 * on the non-default antenna. 2322 * XXX assumes 2 anntenae 2323 */ 2324 otherant = sc->sc_defant & 1 ? 2 : 1; 2325 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2326 ath_setdefantenna(sc, otherant); 2327 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2328 2329 /* 2330 * Construct tx descriptor. 2331 */ 2332 ath_beacon_setup(sc, bf); 2333 2334 /* 2335 * Stop any current dma and put the new frame on the queue. 2336 * This should never fail since we check above that no frames 2337 * are still pending on the queue. 2338 */ 2339 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2340 DPRINTF(sc, ATH_DEBUG_ANY, 2341 "%s: beacon queue %u did not stop?\n", 2342 __func__, sc->sc_bhalq); 2343 } 2344 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2345 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2346 2347 /* 2348 * Enable the CAB queue before the beacon queue to 2349 * insure cab frames are triggered by this beacon. 2350 */ 2351 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2352 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2353 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2354 ath_hal_txstart(ah, sc->sc_bhalq); 2355 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2356 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2357 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2358 2359 sc->sc_stats.ast_be_xmit++; 2360 } 2361 2362 /* 2363 * Reset the hardware after detecting beacons have stopped. 2364 */ 2365 static void 2366 ath_bstuck_proc(void *arg, int pending) 2367 { 2368 struct ath_softc *sc = arg; 2369 struct ifnet *ifp = &sc->sc_if; 2370 2371 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2372 sc->sc_bmisscount); 2373 ath_reset(ifp); 2374 } 2375 2376 /* 2377 * Reclaim beacon resources. 2378 */ 2379 static void 2380 ath_beacon_free(struct ath_softc *sc) 2381 { 2382 struct ath_buf *bf; 2383 2384 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2385 if (bf->bf_m != NULL) { 2386 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2387 m_freem(bf->bf_m); 2388 bf->bf_m = NULL; 2389 } 2390 if (bf->bf_node != NULL) { 2391 ieee80211_free_node(bf->bf_node); 2392 bf->bf_node = NULL; 2393 } 2394 } 2395 } 2396 2397 /* 2398 * Configure the beacon and sleep timers. 2399 * 2400 * When operating as an AP this resets the TSF and sets 2401 * up the hardware to notify us when we need to issue beacons. 2402 * 2403 * When operating in station mode this sets up the beacon 2404 * timers according to the timestamp of the last received 2405 * beacon and the current TSF, configures PCF and DTIM 2406 * handling, programs the sleep registers so the hardware 2407 * will wakeup in time to receive beacons, and configures 2408 * the beacon miss handling so we'll receive a BMISS 2409 * interrupt when we stop seeing beacons from the AP 2410 * we've associated with. 2411 */ 2412 static void 2413 ath_beacon_config(struct ath_softc *sc) 2414 { 2415 #define TSF_TO_TU(_h,_l) \ 2416 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2417 #define FUDGE 2 2418 struct ath_hal *ah = sc->sc_ah; 2419 struct ieee80211com *ic = &sc->sc_ic; 2420 struct ieee80211_node *ni = ic->ic_bss; 2421 u_int32_t nexttbtt, intval, tsftu; 2422 u_int64_t tsf; 2423 2424 /* extract tstamp from last beacon and convert to TU */ 2425 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2426 LE_READ_4(ni->ni_tstamp.data)); 2427 /* NB: the beacon interval is kept internally in TU's */ 2428 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2429 if (nexttbtt == 0) /* e.g. for ap mode */ 2430 nexttbtt = intval; 2431 else if (intval) /* NB: can be 0 for monitor mode */ 2432 nexttbtt = roundup(nexttbtt, intval); 2433 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2434 __func__, nexttbtt, intval, ni->ni_intval); 2435 if (ic->ic_opmode == IEEE80211_M_STA) { 2436 HAL_BEACON_STATE bs; 2437 int dtimperiod, dtimcount; 2438 int cfpperiod, cfpcount; 2439 2440 /* 2441 * Setup dtim and cfp parameters according to 2442 * last beacon we received (which may be none). 2443 */ 2444 dtimperiod = ni->ni_dtim_period; 2445 if (dtimperiod <= 0) /* NB: 0 if not known */ 2446 dtimperiod = 1; 2447 dtimcount = ni->ni_dtim_count; 2448 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2449 dtimcount = 0; /* XXX? */ 2450 cfpperiod = 1; /* NB: no PCF support yet */ 2451 cfpcount = 0; 2452 /* 2453 * Pull nexttbtt forward to reflect the current 2454 * TSF and calculate dtim+cfp state for the result. 2455 */ 2456 tsf = ath_hal_gettsf64(ah); 2457 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2458 do { 2459 nexttbtt += intval; 2460 if (--dtimcount < 0) { 2461 dtimcount = dtimperiod - 1; 2462 if (--cfpcount < 0) 2463 cfpcount = cfpperiod - 1; 2464 } 2465 } while (nexttbtt < tsftu); 2466 memset(&bs, 0, sizeof(bs)); 2467 bs.bs_intval = intval; 2468 bs.bs_nexttbtt = nexttbtt; 2469 bs.bs_dtimperiod = dtimperiod*intval; 2470 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2471 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2472 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2473 bs.bs_cfpmaxduration = 0; 2474 #if 0 2475 /* 2476 * The 802.11 layer records the offset to the DTIM 2477 * bitmap while receiving beacons; use it here to 2478 * enable h/w detection of our AID being marked in 2479 * the bitmap vector (to indicate frames for us are 2480 * pending at the AP). 2481 * XXX do DTIM handling in s/w to WAR old h/w bugs 2482 * XXX enable based on h/w rev for newer chips 2483 */ 2484 bs.bs_timoffset = ni->ni_timoff; 2485 #endif 2486 /* 2487 * Calculate the number of consecutive beacons to miss 2488 * before taking a BMISS interrupt. The configuration 2489 * is specified in ms, so we need to convert that to 2490 * TU's and then calculate based on the beacon interval. 2491 * Note that we clamp the result to at most 10 beacons. 2492 */ 2493 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2494 if (bs.bs_bmissthreshold > 10) 2495 bs.bs_bmissthreshold = 10; 2496 else if (bs.bs_bmissthreshold <= 0) 2497 bs.bs_bmissthreshold = 1; 2498 2499 /* 2500 * Calculate sleep duration. The configuration is 2501 * given in ms. We insure a multiple of the beacon 2502 * period is used. Also, if the sleep duration is 2503 * greater than the DTIM period then it makes senses 2504 * to make it a multiple of that. 2505 * 2506 * XXX fixed at 100ms 2507 */ 2508 bs.bs_sleepduration = 2509 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2510 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2511 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2512 2513 DPRINTF(sc, ATH_DEBUG_BEACON, 2514 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2515 , __func__ 2516 , tsf, tsftu 2517 , bs.bs_intval 2518 , bs.bs_nexttbtt 2519 , bs.bs_dtimperiod 2520 , bs.bs_nextdtim 2521 , bs.bs_bmissthreshold 2522 , bs.bs_sleepduration 2523 , bs.bs_cfpperiod 2524 , bs.bs_cfpmaxduration 2525 , bs.bs_cfpnext 2526 , bs.bs_timoffset 2527 ); 2528 ath_hal_intrset(ah, 0); 2529 ath_hal_beacontimers(ah, &bs); 2530 sc->sc_imask |= HAL_INT_BMISS; 2531 ath_hal_intrset(ah, sc->sc_imask); 2532 } else { 2533 ath_hal_intrset(ah, 0); 2534 if (nexttbtt == intval) 2535 intval |= HAL_BEACON_RESET_TSF; 2536 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2537 /* 2538 * In IBSS mode enable the beacon timers but only 2539 * enable SWBA interrupts if we need to manually 2540 * prepare beacon frames. Otherwise we use a 2541 * self-linked tx descriptor and let the hardware 2542 * deal with things. 2543 */ 2544 intval |= HAL_BEACON_ENA; 2545 if (!sc->sc_hasveol) 2546 sc->sc_imask |= HAL_INT_SWBA; 2547 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2548 /* 2549 * Pull nexttbtt forward to reflect 2550 * the current TSF. 2551 */ 2552 tsf = ath_hal_gettsf64(ah); 2553 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2554 do { 2555 nexttbtt += intval; 2556 } while (nexttbtt < tsftu); 2557 } 2558 ath_beaconq_config(sc); 2559 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2560 /* 2561 * In AP mode we enable the beacon timers and 2562 * SWBA interrupts to prepare beacon frames. 2563 */ 2564 intval |= HAL_BEACON_ENA; 2565 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2566 ath_beaconq_config(sc); 2567 } 2568 ath_hal_beaconinit(ah, nexttbtt, intval); 2569 sc->sc_bmisscount = 0; 2570 ath_hal_intrset(ah, sc->sc_imask); 2571 /* 2572 * When using a self-linked beacon descriptor in 2573 * ibss mode load it once here. 2574 */ 2575 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2576 ath_beacon_proc(sc, 0); 2577 } 2578 sc->sc_syncbeacon = 0; 2579 #undef UNDEF 2580 #undef TSF_TO_TU 2581 } 2582 2583 static int 2584 ath_descdma_setup(struct ath_softc *sc, 2585 struct ath_descdma *dd, ath_bufhead *head, 2586 const char *name, int nbuf, int ndesc) 2587 { 2588 #define DS2PHYS(_dd, _ds) \ 2589 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2590 struct ifnet *ifp = &sc->sc_if; 2591 struct ath_desc *ds; 2592 struct ath_buf *bf; 2593 int i, bsize, error; 2594 2595 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2596 __func__, name, nbuf, ndesc); 2597 2598 dd->dd_name = name; 2599 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2600 2601 /* 2602 * Setup DMA descriptor area. 2603 */ 2604 dd->dd_dmat = sc->sc_dmat; 2605 2606 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2607 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2608 2609 if (error != 0) { 2610 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2611 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2612 goto fail0; 2613 } 2614 2615 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2616 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2617 if (error != 0) { 2618 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2619 nbuf * ndesc, dd->dd_name, error); 2620 goto fail1; 2621 } 2622 2623 /* allocate descriptors */ 2624 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2625 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2626 if (error != 0) { 2627 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2628 "error %u\n", dd->dd_name, error); 2629 goto fail2; 2630 } 2631 2632 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2633 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2634 if (error != 0) { 2635 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2636 dd->dd_name, error); 2637 goto fail3; 2638 } 2639 2640 ds = dd->dd_desc; 2641 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2642 DPRINTF(sc, ATH_DEBUG_RESET, 2643 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2644 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2645 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2646 2647 /* allocate rx buffers */ 2648 bsize = sizeof(struct ath_buf) * nbuf; 2649 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2650 if (bf == NULL) { 2651 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2652 dd->dd_name, bsize); 2653 goto fail4; 2654 } 2655 dd->dd_bufptr = bf; 2656 2657 STAILQ_INIT(head); 2658 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2659 bf->bf_desc = ds; 2660 bf->bf_daddr = DS2PHYS(dd, ds); 2661 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2662 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2663 if (error != 0) { 2664 if_printf(ifp, "unable to create dmamap for %s " 2665 "buffer %u, error %u\n", dd->dd_name, i, error); 2666 ath_descdma_cleanup(sc, dd, head); 2667 return error; 2668 } 2669 STAILQ_INSERT_TAIL(head, bf, bf_list); 2670 } 2671 return 0; 2672 fail4: 2673 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2674 fail3: 2675 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2676 fail2: 2677 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2678 fail1: 2679 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2680 fail0: 2681 memset(dd, 0, sizeof(*dd)); 2682 return error; 2683 #undef DS2PHYS 2684 } 2685 2686 static void 2687 ath_descdma_cleanup(struct ath_softc *sc, 2688 struct ath_descdma *dd, ath_bufhead *head) 2689 { 2690 struct ath_buf *bf; 2691 struct ieee80211_node *ni; 2692 2693 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2694 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2695 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2696 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2697 2698 STAILQ_FOREACH(bf, head, bf_list) { 2699 if (bf->bf_m) { 2700 m_freem(bf->bf_m); 2701 bf->bf_m = NULL; 2702 } 2703 if (bf->bf_dmamap != NULL) { 2704 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2705 bf->bf_dmamap = NULL; 2706 } 2707 ni = bf->bf_node; 2708 bf->bf_node = NULL; 2709 if (ni != NULL) { 2710 /* 2711 * Reclaim node reference. 2712 */ 2713 ieee80211_free_node(ni); 2714 } 2715 } 2716 2717 STAILQ_INIT(head); 2718 free(dd->dd_bufptr, M_ATHDEV); 2719 memset(dd, 0, sizeof(*dd)); 2720 } 2721 2722 static int 2723 ath_desc_alloc(struct ath_softc *sc) 2724 { 2725 int error; 2726 2727 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2728 "rx", ath_rxbuf, 1); 2729 if (error != 0) 2730 return error; 2731 2732 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2733 "tx", ath_txbuf, ATH_TXDESC); 2734 if (error != 0) { 2735 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2736 return error; 2737 } 2738 2739 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2740 "beacon", 1, 1); 2741 if (error != 0) { 2742 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2743 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2744 return error; 2745 } 2746 return 0; 2747 } 2748 2749 static void 2750 ath_desc_free(struct ath_softc *sc) 2751 { 2752 2753 if (sc->sc_bdma.dd_desc_len != 0) 2754 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2755 if (sc->sc_txdma.dd_desc_len != 0) 2756 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2757 if (sc->sc_rxdma.dd_desc_len != 0) 2758 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2759 } 2760 2761 static struct ieee80211_node * 2762 ath_node_alloc(struct ieee80211_node_table *nt) 2763 { 2764 struct ieee80211com *ic = nt->nt_ic; 2765 struct ath_softc *sc = ic->ic_ifp->if_softc; 2766 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2767 struct ath_node *an; 2768 2769 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2770 if (an == NULL) { 2771 /* XXX stat+msg */ 2772 return NULL; 2773 } 2774 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2775 ath_rate_node_init(sc, an); 2776 2777 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2778 return &an->an_node; 2779 } 2780 2781 static void 2782 ath_node_free(struct ieee80211_node *ni) 2783 { 2784 struct ieee80211com *ic = ni->ni_ic; 2785 struct ath_softc *sc = ic->ic_ifp->if_softc; 2786 2787 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2788 2789 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2790 sc->sc_node_free(ni); 2791 } 2792 2793 static u_int8_t 2794 ath_node_getrssi(const struct ieee80211_node *ni) 2795 { 2796 #define HAL_EP_RND(x, mul) \ 2797 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2798 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2799 int32_t rssi; 2800 2801 /* 2802 * When only one frame is received there will be no state in 2803 * avgrssi so fallback on the value recorded by the 802.11 layer. 2804 */ 2805 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2806 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2807 else 2808 rssi = ni->ni_rssi; 2809 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2810 #undef HAL_EP_RND 2811 } 2812 2813 static int 2814 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2815 { 2816 struct ath_hal *ah = sc->sc_ah; 2817 int error; 2818 struct mbuf *m; 2819 struct ath_desc *ds; 2820 2821 m = bf->bf_m; 2822 if (m == NULL) { 2823 /* 2824 * NB: by assigning a page to the rx dma buffer we 2825 * implicitly satisfy the Atheros requirement that 2826 * this buffer be cache-line-aligned and sized to be 2827 * multiple of the cache line size. Not doing this 2828 * causes weird stuff to happen (for the 5210 at least). 2829 */ 2830 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2831 if (m == NULL) { 2832 DPRINTF(sc, ATH_DEBUG_ANY, 2833 "%s: no mbuf/cluster\n", __func__); 2834 sc->sc_stats.ast_rx_nombuf++; 2835 return ENOMEM; 2836 } 2837 bf->bf_m = m; 2838 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2839 2840 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2841 bf->bf_dmamap, m, 2842 BUS_DMA_NOWAIT); 2843 if (error != 0) { 2844 DPRINTF(sc, ATH_DEBUG_ANY, 2845 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2846 __func__, error); 2847 sc->sc_stats.ast_rx_busdma++; 2848 return error; 2849 } 2850 KASSERT(bf->bf_nseg == 1, 2851 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2852 } 2853 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2854 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2855 2856 /* 2857 * Setup descriptors. For receive we always terminate 2858 * the descriptor list with a self-linked entry so we'll 2859 * not get overrun under high load (as can happen with a 2860 * 5212 when ANI processing enables PHY error frames). 2861 * 2862 * To insure the last descriptor is self-linked we create 2863 * each descriptor as self-linked and add it to the end. As 2864 * each additional descriptor is added the previous self-linked 2865 * entry is ``fixed'' naturally. This should be safe even 2866 * if DMA is happening. When processing RX interrupts we 2867 * never remove/process the last, self-linked, entry on the 2868 * descriptor list. This insures the hardware always has 2869 * someplace to write a new frame. 2870 */ 2871 ds = bf->bf_desc; 2872 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2873 ds->ds_data = bf->bf_segs[0].ds_addr; 2874 /* ds->ds_vdata = mtod(m, void *); for radar */ 2875 ath_hal_setuprxdesc(ah, ds 2876 , m->m_len /* buffer size */ 2877 , 0 2878 ); 2879 2880 if (sc->sc_rxlink != NULL) 2881 *sc->sc_rxlink = bf->bf_daddr; 2882 sc->sc_rxlink = &ds->ds_link; 2883 return 0; 2884 } 2885 2886 /* 2887 * Extend 15-bit time stamp from rx descriptor to 2888 * a full 64-bit TSF using the specified TSF. 2889 */ 2890 static inline u_int64_t 2891 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2892 { 2893 if ((tsf & 0x7fff) < rstamp) 2894 tsf -= 0x8000; 2895 return ((tsf &~ 0x7fff) | rstamp); 2896 } 2897 2898 /* 2899 * Intercept management frames to collect beacon rssi data 2900 * and to do ibss merges. 2901 */ 2902 static void 2903 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2904 struct ieee80211_node *ni, 2905 int subtype, int rssi, u_int32_t rstamp) 2906 { 2907 struct ath_softc *sc = ic->ic_ifp->if_softc; 2908 2909 /* 2910 * Call up first so subsequent work can use information 2911 * potentially stored in the node (e.g. for ibss merge). 2912 */ 2913 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2914 switch (subtype) { 2915 case IEEE80211_FC0_SUBTYPE_BEACON: 2916 /* update rssi statistics for use by the hal */ 2917 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2918 if (sc->sc_syncbeacon && 2919 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2920 /* 2921 * Resync beacon timers using the tsf of the beacon 2922 * frame we just received. 2923 */ 2924 ath_beacon_config(sc); 2925 } 2926 /* fall thru... */ 2927 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2928 if (ic->ic_opmode == IEEE80211_M_IBSS && 2929 ic->ic_state == IEEE80211_S_RUN) { 2930 u_int64_t tsf = ath_extend_tsf(rstamp, 2931 ath_hal_gettsf64(sc->sc_ah)); 2932 2933 /* 2934 * Handle ibss merge as needed; check the tsf on the 2935 * frame before attempting the merge. The 802.11 spec 2936 * says the station should change it's bssid to match 2937 * the oldest station with the same ssid, where oldest 2938 * is determined by the tsf. Note that hardware 2939 * reconfiguration happens through callback to 2940 * ath_newstate as the state machine will go from 2941 * RUN -> RUN when this happens. 2942 */ 2943 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2944 DPRINTF(sc, ATH_DEBUG_STATE, 2945 "ibss merge, rstamp %u tsf %ju " 2946 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2947 (uintmax_t)ni->ni_tstamp.tsf); 2948 (void) ieee80211_ibss_merge(ni); 2949 } 2950 } 2951 break; 2952 } 2953 } 2954 2955 /* 2956 * Set the default antenna. 2957 */ 2958 static void 2959 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2960 { 2961 struct ath_hal *ah = sc->sc_ah; 2962 2963 /* XXX block beacon interrupts */ 2964 ath_hal_setdefantenna(ah, antenna); 2965 if (sc->sc_defant != antenna) 2966 sc->sc_stats.ast_ant_defswitch++; 2967 sc->sc_defant = antenna; 2968 sc->sc_rxotherant = 0; 2969 } 2970 2971 static void 2972 ath_handle_micerror(struct ieee80211com *ic, 2973 struct ieee80211_frame *wh, int keyix) 2974 { 2975 struct ieee80211_node *ni; 2976 2977 /* XXX recheck MIC to deal w/ chips that lie */ 2978 /* XXX discard MIC errors on !data frames */ 2979 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 2980 if (ni != NULL) { 2981 ieee80211_notify_michael_failure(ic, wh, keyix); 2982 ieee80211_free_node(ni); 2983 } 2984 } 2985 2986 static void 2987 ath_rx_proc(void *arg, int npending) 2988 { 2989 #define PA2DESC(_sc, _pa) \ 2990 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2991 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2992 struct ath_softc *sc = arg; 2993 struct ath_buf *bf; 2994 struct ieee80211com *ic = &sc->sc_ic; 2995 struct ifnet *ifp = &sc->sc_if; 2996 struct ath_hal *ah = sc->sc_ah; 2997 struct ath_desc *ds; 2998 struct mbuf *m; 2999 struct ieee80211_node *ni; 3000 struct ath_node *an; 3001 int len, ngood, type; 3002 u_int phyerr; 3003 HAL_STATUS status; 3004 int16_t nf; 3005 u_int64_t tsf; 3006 uint8_t rxerr_tap, rxerr_mon; 3007 3008 NET_LOCK_GIANT(); /* XXX */ 3009 3010 rxerr_tap = 3011 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 3012 3013 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 3014 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3015 else if (ifp->if_flags & IFF_PROMISC) 3016 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3017 3018 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3019 ngood = 0; 3020 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3021 tsf = ath_hal_gettsf64(ah); 3022 do { 3023 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3024 if (bf == NULL) { /* NB: shouldn't happen */ 3025 if_printf(ifp, "%s: no buffer!\n", __func__); 3026 break; 3027 } 3028 ds = bf->bf_desc; 3029 if (ds->ds_link == bf->bf_daddr) { 3030 /* NB: never process the self-linked entry at the end */ 3031 break; 3032 } 3033 m = bf->bf_m; 3034 if (m == NULL) { /* NB: shouldn't happen */ 3035 if_printf(ifp, "%s: no mbuf!\n", __func__); 3036 break; 3037 } 3038 /* XXX sync descriptor memory */ 3039 /* 3040 * Must provide the virtual address of the current 3041 * descriptor, the physical address, and the virtual 3042 * address of the next descriptor in the h/w chain. 3043 * This allows the HAL to look ahead to see if the 3044 * hardware is done with a descriptor by checking the 3045 * done bit in the following descriptor and the address 3046 * of the current descriptor the DMA engine is working 3047 * on. All this is necessary because of our use of 3048 * a self-linked list to avoid rx overruns. 3049 */ 3050 status = ath_hal_rxprocdesc(ah, ds, 3051 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 3052 &ds->ds_rxstat); 3053 #ifdef AR_DEBUG 3054 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3055 ath_printrxbuf(bf, status == HAL_OK); 3056 #endif 3057 if (status == HAL_EINPROGRESS) 3058 break; 3059 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3060 if (ds->ds_rxstat.rs_more) { 3061 /* 3062 * Frame spans multiple descriptors; this 3063 * cannot happen yet as we don't support 3064 * jumbograms. If not in monitor mode, 3065 * discard the frame. 3066 */ 3067 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3068 sc->sc_stats.ast_rx_toobig++; 3069 goto rx_next; 3070 } 3071 /* fall thru for monitor mode handling... */ 3072 } else if (ds->ds_rxstat.rs_status != 0) { 3073 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3074 sc->sc_stats.ast_rx_crcerr++; 3075 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3076 sc->sc_stats.ast_rx_fifoerr++; 3077 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3078 sc->sc_stats.ast_rx_phyerr++; 3079 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3080 sc->sc_stats.ast_rx_phy[phyerr]++; 3081 goto rx_next; 3082 } 3083 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3084 /* 3085 * Decrypt error. If the error occurred 3086 * because there was no hardware key, then 3087 * let the frame through so the upper layers 3088 * can process it. This is necessary for 5210 3089 * parts which have no way to setup a ``clear'' 3090 * key cache entry. 3091 * 3092 * XXX do key cache faulting 3093 */ 3094 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3095 goto rx_accept; 3096 sc->sc_stats.ast_rx_badcrypt++; 3097 } 3098 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3099 sc->sc_stats.ast_rx_badmic++; 3100 /* 3101 * Do minimal work required to hand off 3102 * the 802.11 header for notifcation. 3103 */ 3104 /* XXX frag's and qos frames */ 3105 len = ds->ds_rxstat.rs_datalen; 3106 if (len >= sizeof (struct ieee80211_frame)) { 3107 bus_dmamap_sync(sc->sc_dmat, 3108 bf->bf_dmamap, 3109 0, bf->bf_dmamap->dm_mapsize, 3110 BUS_DMASYNC_POSTREAD); 3111 ath_handle_micerror(ic, 3112 mtod(m, struct ieee80211_frame *), 3113 sc->sc_splitmic ? 3114 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3115 } 3116 } 3117 ifp->if_ierrors++; 3118 /* 3119 * Reject error frames, we normally don't want 3120 * to see them in monitor mode (in monitor mode 3121 * allow through packets that have crypto problems). 3122 */ 3123 3124 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3125 goto rx_next; 3126 } 3127 rx_accept: 3128 /* 3129 * Sync and unmap the frame. At this point we're 3130 * committed to passing the mbuf somewhere so clear 3131 * bf_m; this means a new sk_buff must be allocated 3132 * when the rx descriptor is setup again to receive 3133 * another frame. 3134 */ 3135 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3136 0, bf->bf_dmamap->dm_mapsize, 3137 BUS_DMASYNC_POSTREAD); 3138 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3139 bf->bf_m = NULL; 3140 3141 m->m_pkthdr.rcvif = ifp; 3142 len = ds->ds_rxstat.rs_datalen; 3143 m->m_pkthdr.len = m->m_len = len; 3144 3145 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3146 3147 if (sc->sc_drvbpf) { 3148 u_int8_t rix; 3149 3150 /* 3151 * Discard anything shorter than an ack or cts. 3152 */ 3153 if (len < IEEE80211_ACK_LEN) { 3154 DPRINTF(sc, ATH_DEBUG_RECV, 3155 "%s: runt packet %d\n", 3156 __func__, len); 3157 sc->sc_stats.ast_rx_tooshort++; 3158 m_freem(m); 3159 goto rx_next; 3160 } 3161 rix = ds->ds_rxstat.rs_rate; 3162 sc->sc_rx_th.wr_tsf = htole64( 3163 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3164 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3165 if (ds->ds_rxstat.rs_status & 3166 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3167 sc->sc_rx_th.wr_flags |= 3168 IEEE80211_RADIOTAP_F_BADFCS; 3169 } 3170 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3171 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3172 sc->sc_rx_th.wr_antnoise = nf; 3173 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3174 3175 bpf_ops->bpf_mtap2(sc->sc_drvbpf, 3176 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3177 } 3178 3179 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3180 m_freem(m); 3181 goto rx_next; 3182 } 3183 /* 3184 * From this point on we assume the frame is at least 3185 * as large as ieee80211_frame_min; verify that. 3186 */ 3187 if (len < IEEE80211_MIN_LEN) { 3188 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3189 __func__, len); 3190 sc->sc_stats.ast_rx_tooshort++; 3191 m_freem(m); 3192 goto rx_next; 3193 } 3194 3195 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3196 ieee80211_dump_pkt(mtod(m, void *), len, 3197 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3198 ds->ds_rxstat.rs_rssi); 3199 } 3200 3201 m_adj(m, -IEEE80211_CRC_LEN); 3202 3203 /* 3204 * Locate the node for sender, track state, and then 3205 * pass the (referenced) node up to the 802.11 layer 3206 * for its use. 3207 */ 3208 ni = ieee80211_find_rxnode_withkey(ic, 3209 mtod(m, const struct ieee80211_frame_min *), 3210 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3211 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3212 /* 3213 * Track rx rssi and do any rx antenna management. 3214 */ 3215 an = ATH_NODE(ni); 3216 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3217 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3218 /* 3219 * Send frame up for processing. 3220 */ 3221 type = ieee80211_input(ic, m, ni, 3222 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3223 ieee80211_free_node(ni); 3224 if (sc->sc_diversity) { 3225 /* 3226 * When using fast diversity, change the default rx 3227 * antenna if diversity chooses the other antenna 3 3228 * times in a row. 3229 */ 3230 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3231 if (++sc->sc_rxotherant >= 3) 3232 ath_setdefantenna(sc, 3233 ds->ds_rxstat.rs_antenna); 3234 } else 3235 sc->sc_rxotherant = 0; 3236 } 3237 if (sc->sc_softled) { 3238 /* 3239 * Blink for any data frame. Otherwise do a 3240 * heartbeat-style blink when idle. The latter 3241 * is mainly for station mode where we depend on 3242 * periodic beacon frames to trigger the poll event. 3243 */ 3244 if (type == IEEE80211_FC0_TYPE_DATA) { 3245 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3246 ath_led_event(sc, ATH_LED_RX); 3247 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3248 ath_led_event(sc, ATH_LED_POLL); 3249 } 3250 /* 3251 * Arrange to update the last rx timestamp only for 3252 * frames from our ap when operating in station mode. 3253 * This assumes the rx key is always setup when associated. 3254 */ 3255 if (ic->ic_opmode == IEEE80211_M_STA && 3256 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3257 ngood++; 3258 rx_next: 3259 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3260 } while (ath_rxbuf_init(sc, bf) == 0); 3261 3262 /* rx signal state monitoring */ 3263 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3264 #if 0 3265 if (ath_hal_radar_event(ah)) 3266 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3267 #endif 3268 if (ngood) 3269 sc->sc_lastrx = tsf; 3270 3271 #ifdef __NetBSD__ 3272 /* XXX Why isn't this necessary in FreeBSD? */ 3273 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3274 ath_start(ifp); 3275 #endif /* __NetBSD__ */ 3276 3277 NET_UNLOCK_GIANT(); /* XXX */ 3278 #undef PA2DESC 3279 } 3280 3281 /* 3282 * Setup a h/w transmit queue. 3283 */ 3284 static struct ath_txq * 3285 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3286 { 3287 #define N(a) (sizeof(a)/sizeof(a[0])) 3288 struct ath_hal *ah = sc->sc_ah; 3289 HAL_TXQ_INFO qi; 3290 int qnum; 3291 3292 memset(&qi, 0, sizeof(qi)); 3293 qi.tqi_subtype = subtype; 3294 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3295 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3296 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3297 /* 3298 * Enable interrupts only for EOL and DESC conditions. 3299 * We mark tx descriptors to receive a DESC interrupt 3300 * when a tx queue gets deep; otherwise waiting for the 3301 * EOL to reap descriptors. Note that this is done to 3302 * reduce interrupt load and this only defers reaping 3303 * descriptors, never transmitting frames. Aside from 3304 * reducing interrupts this also permits more concurrency. 3305 * The only potential downside is if the tx queue backs 3306 * up in which case the top half of the kernel may backup 3307 * due to a lack of tx descriptors. 3308 */ 3309 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3310 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3311 if (qnum == -1) { 3312 /* 3313 * NB: don't print a message, this happens 3314 * normally on parts with too few tx queues 3315 */ 3316 return NULL; 3317 } 3318 if (qnum >= N(sc->sc_txq)) { 3319 device_printf(sc->sc_dev, 3320 "hal qnum %u out of range, max %zu!\n", 3321 qnum, N(sc->sc_txq)); 3322 ath_hal_releasetxqueue(ah, qnum); 3323 return NULL; 3324 } 3325 if (!ATH_TXQ_SETUP(sc, qnum)) { 3326 struct ath_txq *txq = &sc->sc_txq[qnum]; 3327 3328 txq->axq_qnum = qnum; 3329 txq->axq_depth = 0; 3330 txq->axq_intrcnt = 0; 3331 txq->axq_link = NULL; 3332 STAILQ_INIT(&txq->axq_q); 3333 ATH_TXQ_LOCK_INIT(sc, txq); 3334 sc->sc_txqsetup |= 1<<qnum; 3335 } 3336 return &sc->sc_txq[qnum]; 3337 #undef N 3338 } 3339 3340 /* 3341 * Setup a hardware data transmit queue for the specified 3342 * access control. The hal may not support all requested 3343 * queues in which case it will return a reference to a 3344 * previously setup queue. We record the mapping from ac's 3345 * to h/w queues for use by ath_tx_start and also track 3346 * the set of h/w queues being used to optimize work in the 3347 * transmit interrupt handler and related routines. 3348 */ 3349 static int 3350 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3351 { 3352 #define N(a) (sizeof(a)/sizeof(a[0])) 3353 struct ath_txq *txq; 3354 3355 if (ac >= N(sc->sc_ac2q)) { 3356 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3357 ac, N(sc->sc_ac2q)); 3358 return 0; 3359 } 3360 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3361 if (txq != NULL) { 3362 sc->sc_ac2q[ac] = txq; 3363 return 1; 3364 } else 3365 return 0; 3366 #undef N 3367 } 3368 3369 /* 3370 * Update WME parameters for a transmit queue. 3371 */ 3372 static int 3373 ath_txq_update(struct ath_softc *sc, int ac) 3374 { 3375 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3376 #define ATH_TXOP_TO_US(v) (v<<5) 3377 struct ieee80211com *ic = &sc->sc_ic; 3378 struct ath_txq *txq = sc->sc_ac2q[ac]; 3379 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3380 struct ath_hal *ah = sc->sc_ah; 3381 HAL_TXQ_INFO qi; 3382 3383 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3384 qi.tqi_aifs = wmep->wmep_aifsn; 3385 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3386 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3387 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3388 3389 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3390 device_printf(sc->sc_dev, "unable to update hardware queue " 3391 "parameters for %s traffic!\n", 3392 ieee80211_wme_acnames[ac]); 3393 return 0; 3394 } else { 3395 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3396 return 1; 3397 } 3398 #undef ATH_TXOP_TO_US 3399 #undef ATH_EXPONENT_TO_VALUE 3400 } 3401 3402 /* 3403 * Callback from the 802.11 layer to update WME parameters. 3404 */ 3405 static int 3406 ath_wme_update(struct ieee80211com *ic) 3407 { 3408 struct ath_softc *sc = ic->ic_ifp->if_softc; 3409 3410 return !ath_txq_update(sc, WME_AC_BE) || 3411 !ath_txq_update(sc, WME_AC_BK) || 3412 !ath_txq_update(sc, WME_AC_VI) || 3413 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3414 } 3415 3416 /* 3417 * Reclaim resources for a setup queue. 3418 */ 3419 static void 3420 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3421 { 3422 3423 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3424 ATH_TXQ_LOCK_DESTROY(txq); 3425 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3426 } 3427 3428 /* 3429 * Reclaim all tx queue resources. 3430 */ 3431 static void 3432 ath_tx_cleanup(struct ath_softc *sc) 3433 { 3434 int i; 3435 3436 ATH_TXBUF_LOCK_DESTROY(sc); 3437 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3438 if (ATH_TXQ_SETUP(sc, i)) 3439 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3440 } 3441 3442 /* 3443 * Defragment an mbuf chain, returning at most maxfrags separate 3444 * mbufs+clusters. If this is not possible NULL is returned and 3445 * the original mbuf chain is left in it's present (potentially 3446 * modified) state. We use two techniques: collapsing consecutive 3447 * mbufs and replacing consecutive mbufs by a cluster. 3448 */ 3449 static struct mbuf * 3450 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3451 { 3452 struct mbuf *m, *n, *n2, **prev; 3453 u_int curfrags; 3454 3455 /* 3456 * Calculate the current number of frags. 3457 */ 3458 curfrags = 0; 3459 for (m = m0; m != NULL; m = m->m_next) 3460 curfrags++; 3461 /* 3462 * First, try to collapse mbufs. Note that we always collapse 3463 * towards the front so we don't need to deal with moving the 3464 * pkthdr. This may be suboptimal if the first mbuf has much 3465 * less data than the following. 3466 */ 3467 m = m0; 3468 again: 3469 for (;;) { 3470 n = m->m_next; 3471 if (n == NULL) 3472 break; 3473 if (n->m_len < M_TRAILINGSPACE(m)) { 3474 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3475 n->m_len); 3476 m->m_len += n->m_len; 3477 m->m_next = n->m_next; 3478 m_free(n); 3479 if (--curfrags <= maxfrags) 3480 return m0; 3481 } else 3482 m = n; 3483 } 3484 KASSERT(maxfrags > 1, 3485 ("maxfrags %u, but normal collapse failed", maxfrags)); 3486 /* 3487 * Collapse consecutive mbufs to a cluster. 3488 */ 3489 prev = &m0->m_next; /* NB: not the first mbuf */ 3490 while ((n = *prev) != NULL) { 3491 if ((n2 = n->m_next) != NULL && 3492 n->m_len + n2->m_len < MCLBYTES) { 3493 m = m_getcl(how, MT_DATA, 0); 3494 if (m == NULL) 3495 goto bad; 3496 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3497 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3498 n2->m_len); 3499 m->m_len = n->m_len + n2->m_len; 3500 m->m_next = n2->m_next; 3501 *prev = m; 3502 m_free(n); 3503 m_free(n2); 3504 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3505 return m0; 3506 /* 3507 * Still not there, try the normal collapse 3508 * again before we allocate another cluster. 3509 */ 3510 goto again; 3511 } 3512 prev = &n->m_next; 3513 } 3514 /* 3515 * No place where we can collapse to a cluster; punt. 3516 * This can occur if, for example, you request 2 frags 3517 * but the packet requires that both be clusters (we 3518 * never reallocate the first mbuf to avoid moving the 3519 * packet header). 3520 */ 3521 bad: 3522 return NULL; 3523 } 3524 3525 /* 3526 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3527 */ 3528 static int 3529 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3530 { 3531 int i; 3532 3533 for (i = 0; i < rt->rateCount; i++) 3534 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3535 return i; 3536 return 0; /* NB: lowest rate */ 3537 } 3538 3539 static void 3540 ath_freetx(struct mbuf *m) 3541 { 3542 struct mbuf *next; 3543 3544 do { 3545 next = m->m_nextpkt; 3546 m->m_nextpkt = NULL; 3547 m_freem(m); 3548 } while ((m = next) != NULL); 3549 } 3550 3551 static int 3552 deduct_pad_bytes(int len, int hdrlen) 3553 { 3554 /* XXX I am suspicious that this code, which I extracted 3555 * XXX from ath_tx_start() for reuse, does the right thing. 3556 */ 3557 return len - (hdrlen & 3); 3558 } 3559 3560 static int 3561 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3562 struct mbuf *m0) 3563 { 3564 struct ieee80211com *ic = &sc->sc_ic; 3565 struct ath_hal *ah = sc->sc_ah; 3566 struct ifnet *ifp = &sc->sc_if; 3567 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3568 int i, error, iswep, ismcast, isfrag, ismrr; 3569 int keyix, hdrlen, pktlen, try0; 3570 u_int8_t rix, txrate, ctsrate; 3571 u_int8_t cix = 0xff; /* NB: silence compiler */ 3572 struct ath_desc *ds, *ds0; 3573 struct ath_txq *txq; 3574 struct ieee80211_frame *wh; 3575 u_int subtype, flags, ctsduration; 3576 HAL_PKT_TYPE atype; 3577 const HAL_RATE_TABLE *rt; 3578 HAL_BOOL shortPreamble; 3579 struct ath_node *an; 3580 struct mbuf *m; 3581 u_int pri; 3582 3583 wh = mtod(m0, struct ieee80211_frame *); 3584 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3585 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3586 isfrag = m0->m_flags & M_FRAG; 3587 hdrlen = ieee80211_anyhdrsize(wh); 3588 /* 3589 * Packet length must not include any 3590 * pad bytes; deduct them here. 3591 */ 3592 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3593 3594 if (iswep) { 3595 const struct ieee80211_cipher *cip; 3596 struct ieee80211_key *k; 3597 3598 /* 3599 * Construct the 802.11 header+trailer for an encrypted 3600 * frame. The only reason this can fail is because of an 3601 * unknown or unsupported cipher/key type. 3602 */ 3603 k = ieee80211_crypto_encap(ic, ni, m0); 3604 if (k == NULL) { 3605 /* 3606 * This can happen when the key is yanked after the 3607 * frame was queued. Just discard the frame; the 3608 * 802.11 layer counts failures and provides 3609 * debugging/diagnostics. 3610 */ 3611 ath_freetx(m0); 3612 return EIO; 3613 } 3614 /* 3615 * Adjust the packet + header lengths for the crypto 3616 * additions and calculate the h/w key index. When 3617 * a s/w mic is done the frame will have had any mic 3618 * added to it prior to entry so m0->m_pkthdr.len above will 3619 * account for it. Otherwise we need to add it to the 3620 * packet length. 3621 */ 3622 cip = k->wk_cipher; 3623 hdrlen += cip->ic_header; 3624 pktlen += cip->ic_header + cip->ic_trailer; 3625 /* NB: frags always have any TKIP MIC done in s/w */ 3626 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3627 pktlen += cip->ic_miclen; 3628 keyix = k->wk_keyix; 3629 3630 /* packet header may have moved, reset our local pointer */ 3631 wh = mtod(m0, struct ieee80211_frame *); 3632 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3633 /* 3634 * Use station key cache slot, if assigned. 3635 */ 3636 keyix = ni->ni_ucastkey.wk_keyix; 3637 if (keyix == IEEE80211_KEYIX_NONE) 3638 keyix = HAL_TXKEYIX_INVALID; 3639 } else 3640 keyix = HAL_TXKEYIX_INVALID; 3641 3642 pktlen += IEEE80211_CRC_LEN; 3643 3644 /* 3645 * Load the DMA map so any coalescing is done. This 3646 * also calculates the number of descriptors we need. 3647 */ 3648 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3649 BUS_DMA_NOWAIT); 3650 if (error == EFBIG) { 3651 /* XXX packet requires too many descriptors */ 3652 bf->bf_nseg = ATH_TXDESC+1; 3653 } else if (error != 0) { 3654 sc->sc_stats.ast_tx_busdma++; 3655 ath_freetx(m0); 3656 return error; 3657 } 3658 /* 3659 * Discard null packets and check for packets that 3660 * require too many TX descriptors. We try to convert 3661 * the latter to a cluster. 3662 */ 3663 if (error == EFBIG) { /* too many desc's, linearize */ 3664 sc->sc_stats.ast_tx_linear++; 3665 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3666 if (m == NULL) { 3667 ath_freetx(m0); 3668 sc->sc_stats.ast_tx_nombuf++; 3669 return ENOMEM; 3670 } 3671 m0 = m; 3672 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3673 BUS_DMA_NOWAIT); 3674 if (error != 0) { 3675 sc->sc_stats.ast_tx_busdma++; 3676 ath_freetx(m0); 3677 return error; 3678 } 3679 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3680 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3681 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3682 sc->sc_stats.ast_tx_nodata++; 3683 ath_freetx(m0); 3684 return EIO; 3685 } 3686 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3687 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3688 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3689 bf->bf_m = m0; 3690 bf->bf_node = ni; /* NB: held reference */ 3691 3692 /* setup descriptors */ 3693 ds = bf->bf_desc; 3694 rt = sc->sc_currates; 3695 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3696 3697 /* 3698 * NB: the 802.11 layer marks whether or not we should 3699 * use short preamble based on the current mode and 3700 * negotiated parameters. 3701 */ 3702 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3703 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3704 shortPreamble = AH_TRUE; 3705 sc->sc_stats.ast_tx_shortpre++; 3706 } else { 3707 shortPreamble = AH_FALSE; 3708 } 3709 3710 an = ATH_NODE(ni); 3711 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3712 ismrr = 0; /* default no multi-rate retry*/ 3713 /* 3714 * Calculate Atheros packet type from IEEE80211 packet header, 3715 * setup for rate calculations, and select h/w transmit queue. 3716 */ 3717 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3718 case IEEE80211_FC0_TYPE_MGT: 3719 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3720 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3721 atype = HAL_PKT_TYPE_BEACON; 3722 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3723 atype = HAL_PKT_TYPE_PROBE_RESP; 3724 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3725 atype = HAL_PKT_TYPE_ATIM; 3726 else 3727 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3728 rix = sc->sc_minrateix; 3729 txrate = rt->info[rix].rateCode; 3730 if (shortPreamble) 3731 txrate |= rt->info[rix].shortPreamble; 3732 try0 = ATH_TXMGTTRY; 3733 /* NB: force all management frames to highest queue */ 3734 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3735 /* NB: force all management frames to highest queue */ 3736 pri = WME_AC_VO; 3737 } else 3738 pri = WME_AC_BE; 3739 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3740 break; 3741 case IEEE80211_FC0_TYPE_CTL: 3742 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3743 rix = sc->sc_minrateix; 3744 txrate = rt->info[rix].rateCode; 3745 if (shortPreamble) 3746 txrate |= rt->info[rix].shortPreamble; 3747 try0 = ATH_TXMGTTRY; 3748 /* NB: force all ctl frames to highest queue */ 3749 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3750 /* NB: force all ctl frames to highest queue */ 3751 pri = WME_AC_VO; 3752 } else 3753 pri = WME_AC_BE; 3754 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3755 break; 3756 case IEEE80211_FC0_TYPE_DATA: 3757 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3758 /* 3759 * Data frames: multicast frames go out at a fixed rate, 3760 * otherwise consult the rate control module for the 3761 * rate to use. 3762 */ 3763 if (ismcast) { 3764 /* 3765 * Check mcast rate setting in case it's changed. 3766 * XXX move out of fastpath 3767 */ 3768 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3769 sc->sc_mcastrix = 3770 ath_tx_findrix(rt, ic->ic_mcast_rate); 3771 sc->sc_mcastrate = ic->ic_mcast_rate; 3772 } 3773 rix = sc->sc_mcastrix; 3774 txrate = rt->info[rix].rateCode; 3775 try0 = 1; 3776 } else { 3777 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3778 &rix, &try0, &txrate); 3779 sc->sc_txrate = txrate; /* for LED blinking */ 3780 if (try0 != ATH_TXMAXTRY) 3781 ismrr = 1; 3782 } 3783 pri = M_WME_GETAC(m0); 3784 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3785 flags |= HAL_TXDESC_NOACK; 3786 break; 3787 default: 3788 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3789 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3790 /* XXX statistic */ 3791 ath_freetx(m0); 3792 return EIO; 3793 } 3794 txq = sc->sc_ac2q[pri]; 3795 3796 /* 3797 * When servicing one or more stations in power-save mode 3798 * multicast frames must be buffered until after the beacon. 3799 * We use the CAB queue for that. 3800 */ 3801 if (ismcast && ic->ic_ps_sta) { 3802 txq = sc->sc_cabq; 3803 /* XXX? more bit in 802.11 frame header */ 3804 } 3805 3806 /* 3807 * Calculate miscellaneous flags. 3808 */ 3809 if (ismcast) { 3810 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3811 } else if (pktlen > ic->ic_rtsthreshold) { 3812 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3813 cix = rt->info[rix].controlRate; 3814 sc->sc_stats.ast_tx_rts++; 3815 } 3816 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3817 sc->sc_stats.ast_tx_noack++; 3818 3819 /* 3820 * If 802.11g protection is enabled, determine whether 3821 * to use RTS/CTS or just CTS. Note that this is only 3822 * done for OFDM unicast frames. 3823 */ 3824 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3825 rt->info[rix].phy == IEEE80211_T_OFDM && 3826 (flags & HAL_TXDESC_NOACK) == 0) { 3827 /* XXX fragments must use CCK rates w/ protection */ 3828 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3829 flags |= HAL_TXDESC_RTSENA; 3830 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3831 flags |= HAL_TXDESC_CTSENA; 3832 if (isfrag) { 3833 /* 3834 * For frags it would be desirable to use the 3835 * highest CCK rate for RTS/CTS. But stations 3836 * farther away may detect it at a lower CCK rate 3837 * so use the configured protection rate instead 3838 * (for now). 3839 */ 3840 cix = rt->info[sc->sc_protrix].controlRate; 3841 } else 3842 cix = rt->info[sc->sc_protrix].controlRate; 3843 sc->sc_stats.ast_tx_protect++; 3844 } 3845 3846 /* 3847 * Calculate duration. This logically belongs in the 802.11 3848 * layer but it lacks sufficient information to calculate it. 3849 */ 3850 if ((flags & HAL_TXDESC_NOACK) == 0 && 3851 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3852 u_int16_t dur; 3853 /* 3854 * XXX not right with fragmentation. 3855 */ 3856 if (shortPreamble) 3857 dur = rt->info[rix].spAckDuration; 3858 else 3859 dur = rt->info[rix].lpAckDuration; 3860 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3861 dur += dur; /* additional SIFS+ACK */ 3862 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3863 /* 3864 * Include the size of next fragment so NAV is 3865 * updated properly. The last fragment uses only 3866 * the ACK duration 3867 */ 3868 dur += ath_hal_computetxtime(ah, rt, 3869 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3870 hdrlen) - 3871 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3872 rix, shortPreamble); 3873 } 3874 if (isfrag) { 3875 /* 3876 * Force hardware to use computed duration for next 3877 * fragment by disabling multi-rate retry which updates 3878 * duration based on the multi-rate duration table. 3879 */ 3880 try0 = ATH_TXMAXTRY; 3881 } 3882 *(u_int16_t *)wh->i_dur = htole16(dur); 3883 } 3884 3885 /* 3886 * Calculate RTS/CTS rate and duration if needed. 3887 */ 3888 ctsduration = 0; 3889 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3890 /* 3891 * CTS transmit rate is derived from the transmit rate 3892 * by looking in the h/w rate table. We must also factor 3893 * in whether or not a short preamble is to be used. 3894 */ 3895 /* NB: cix is set above where RTS/CTS is enabled */ 3896 KASSERT(cix != 0xff, ("cix not setup")); 3897 ctsrate = rt->info[cix].rateCode; 3898 /* 3899 * Compute the transmit duration based on the frame 3900 * size and the size of an ACK frame. We call into the 3901 * HAL to do the computation since it depends on the 3902 * characteristics of the actual PHY being used. 3903 * 3904 * NB: CTS is assumed the same size as an ACK so we can 3905 * use the precalculated ACK durations. 3906 */ 3907 if (shortPreamble) { 3908 ctsrate |= rt->info[cix].shortPreamble; 3909 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3910 ctsduration += rt->info[cix].spAckDuration; 3911 ctsduration += ath_hal_computetxtime(ah, 3912 rt, pktlen, rix, AH_TRUE); 3913 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3914 ctsduration += rt->info[rix].spAckDuration; 3915 } else { 3916 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3917 ctsduration += rt->info[cix].lpAckDuration; 3918 ctsduration += ath_hal_computetxtime(ah, 3919 rt, pktlen, rix, AH_FALSE); 3920 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3921 ctsduration += rt->info[rix].lpAckDuration; 3922 } 3923 /* 3924 * Must disable multi-rate retry when using RTS/CTS. 3925 */ 3926 ismrr = 0; 3927 try0 = ATH_TXMGTTRY; /* XXX */ 3928 } else 3929 ctsrate = 0; 3930 3931 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3932 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3933 sc->sc_hwmap[txrate].ieeerate, -1); 3934 if (ic->ic_rawbpf) 3935 bpf_ops->bpf_mtap(ic->ic_rawbpf, m0); 3936 if (sc->sc_drvbpf) { 3937 u_int64_t tsf = ath_hal_gettsf64(ah); 3938 3939 sc->sc_tx_th.wt_tsf = htole64(tsf); 3940 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3941 if (iswep) 3942 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3943 if (isfrag) 3944 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3945 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3946 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3947 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3948 3949 bpf_ops->bpf_mtap2(sc->sc_drvbpf, 3950 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3951 } 3952 3953 /* 3954 * Determine if a tx interrupt should be generated for 3955 * this descriptor. We take a tx interrupt to reap 3956 * descriptors when the h/w hits an EOL condition or 3957 * when the descriptor is specifically marked to generate 3958 * an interrupt. We periodically mark descriptors in this 3959 * way to insure timely replenishing of the supply needed 3960 * for sending frames. Defering interrupts reduces system 3961 * load and potentially allows more concurrent work to be 3962 * done but if done to aggressively can cause senders to 3963 * backup. 3964 * 3965 * NB: use >= to deal with sc_txintrperiod changing 3966 * dynamically through sysctl. 3967 */ 3968 if (flags & HAL_TXDESC_INTREQ) { 3969 txq->axq_intrcnt = 0; 3970 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3971 flags |= HAL_TXDESC_INTREQ; 3972 txq->axq_intrcnt = 0; 3973 } 3974 3975 /* 3976 * Formulate first tx descriptor with tx controls. 3977 */ 3978 /* XXX check return value? */ 3979 ath_hal_setuptxdesc(ah, ds 3980 , pktlen /* packet length */ 3981 , hdrlen /* header length */ 3982 , atype /* Atheros packet type */ 3983 , ni->ni_txpower /* txpower */ 3984 , txrate, try0 /* series 0 rate/tries */ 3985 , keyix /* key cache index */ 3986 , sc->sc_txantenna /* antenna mode */ 3987 , flags /* flags */ 3988 , ctsrate /* rts/cts rate */ 3989 , ctsduration /* rts/cts duration */ 3990 ); 3991 bf->bf_flags = flags; 3992 /* 3993 * Setup the multi-rate retry state only when we're 3994 * going to use it. This assumes ath_hal_setuptxdesc 3995 * initializes the descriptors (so we don't have to) 3996 * when the hardware supports multi-rate retry and 3997 * we don't use it. 3998 */ 3999 if (ismrr) 4000 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4001 4002 /* 4003 * Fillin the remainder of the descriptor info. 4004 */ 4005 ds0 = ds; 4006 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4007 ds->ds_data = bf->bf_segs[i].ds_addr; 4008 if (i == bf->bf_nseg - 1) 4009 ds->ds_link = 0; 4010 else 4011 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4012 ath_hal_filltxdesc(ah, ds 4013 , bf->bf_segs[i].ds_len /* segment length */ 4014 , i == 0 /* first segment */ 4015 , i == bf->bf_nseg - 1 /* last segment */ 4016 , ds0 /* first descriptor */ 4017 ); 4018 4019 /* NB: The desc swap function becomes void, 4020 * if descriptor swapping is not enabled 4021 */ 4022 ath_desc_swap(ds); 4023 4024 DPRINTF(sc, ATH_DEBUG_XMIT, 4025 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4026 __func__, i, ds->ds_link, ds->ds_data, 4027 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4028 } 4029 /* 4030 * Insert the frame on the outbound list and 4031 * pass it on to the hardware. 4032 */ 4033 ATH_TXQ_LOCK(txq); 4034 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4035 if (txq->axq_link == NULL) { 4036 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4037 DPRINTF(sc, ATH_DEBUG_XMIT, 4038 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 4039 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 4040 txq->axq_depth); 4041 } else { 4042 *txq->axq_link = HTOAH32(bf->bf_daddr); 4043 DPRINTF(sc, ATH_DEBUG_XMIT, 4044 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 4045 __func__, txq->axq_qnum, txq->axq_link, 4046 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4047 } 4048 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4049 /* 4050 * The CAB queue is started from the SWBA handler since 4051 * frames only go out on DTIM and to avoid possible races. 4052 */ 4053 if (txq != sc->sc_cabq) 4054 ath_hal_txstart(ah, txq->axq_qnum); 4055 ATH_TXQ_UNLOCK(txq); 4056 4057 return 0; 4058 } 4059 4060 /* 4061 * Process completed xmit descriptors from the specified queue. 4062 */ 4063 static int 4064 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4065 { 4066 struct ath_hal *ah = sc->sc_ah; 4067 struct ieee80211com *ic = &sc->sc_ic; 4068 struct ath_buf *bf; 4069 struct ath_desc *ds, *ds0; 4070 struct ieee80211_node *ni; 4071 struct ath_node *an; 4072 int sr, lr, pri, nacked; 4073 HAL_STATUS status; 4074 4075 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4076 __func__, txq->axq_qnum, 4077 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4078 txq->axq_link); 4079 nacked = 0; 4080 for (;;) { 4081 ATH_TXQ_LOCK(txq); 4082 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4083 bf = STAILQ_FIRST(&txq->axq_q); 4084 if (bf == NULL) { 4085 txq->axq_link = NULL; 4086 ATH_TXQ_UNLOCK(txq); 4087 break; 4088 } 4089 ds0 = &bf->bf_desc[0]; 4090 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4091 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4092 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4093 ath_printtxbuf(bf, status == HAL_OK); 4094 if (status == HAL_EINPROGRESS) { 4095 ATH_TXQ_UNLOCK(txq); 4096 break; 4097 } 4098 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4099 ATH_TXQ_UNLOCK(txq); 4100 4101 ni = bf->bf_node; 4102 if (ni != NULL) { 4103 an = ATH_NODE(ni); 4104 if (ds->ds_txstat.ts_status == 0) { 4105 u_int8_t txant = ds->ds_txstat.ts_antenna; 4106 sc->sc_stats.ast_ant_tx[txant]++; 4107 sc->sc_ant_tx[txant]++; 4108 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4109 sc->sc_stats.ast_tx_altrate++; 4110 sc->sc_stats.ast_tx_rssi = 4111 ds->ds_txstat.ts_rssi; 4112 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4113 ds->ds_txstat.ts_rssi); 4114 pri = M_WME_GETAC(bf->bf_m); 4115 if (pri >= WME_AC_VO) 4116 ic->ic_wme.wme_hipri_traffic++; 4117 ni->ni_inact = ni->ni_inact_reload; 4118 } else { 4119 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4120 sc->sc_stats.ast_tx_xretries++; 4121 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4122 sc->sc_stats.ast_tx_fifoerr++; 4123 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4124 sc->sc_stats.ast_tx_filtered++; 4125 } 4126 sr = ds->ds_txstat.ts_shortretry; 4127 lr = ds->ds_txstat.ts_longretry; 4128 sc->sc_stats.ast_tx_shortretry += sr; 4129 sc->sc_stats.ast_tx_longretry += lr; 4130 /* 4131 * Hand the descriptor to the rate control algorithm. 4132 */ 4133 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4134 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4135 /* 4136 * If frame was ack'd update the last rx time 4137 * used to workaround phantom bmiss interrupts. 4138 */ 4139 if (ds->ds_txstat.ts_status == 0) 4140 nacked++; 4141 ath_rate_tx_complete(sc, an, ds, ds0); 4142 } 4143 /* 4144 * Reclaim reference to node. 4145 * 4146 * NB: the node may be reclaimed here if, for example 4147 * this is a DEAUTH message that was sent and the 4148 * node was timed out due to inactivity. 4149 */ 4150 ieee80211_free_node(ni); 4151 } 4152 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4153 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4154 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4155 m_freem(bf->bf_m); 4156 bf->bf_m = NULL; 4157 bf->bf_node = NULL; 4158 4159 ATH_TXBUF_LOCK(sc); 4160 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4161 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4162 ATH_TXBUF_UNLOCK(sc); 4163 } 4164 return nacked; 4165 } 4166 4167 static inline int 4168 txqactive(struct ath_hal *ah, int qnum) 4169 { 4170 u_int32_t txqs = 1<<qnum; 4171 ath_hal_gettxintrtxqs(ah, &txqs); 4172 return (txqs & (1<<qnum)); 4173 } 4174 4175 /* 4176 * Deferred processing of transmit interrupt; special-cased 4177 * for a single hardware transmit queue (e.g. 5210 and 5211). 4178 */ 4179 static void 4180 ath_tx_proc_q0(void *arg, int npending) 4181 { 4182 struct ath_softc *sc = arg; 4183 struct ifnet *ifp = &sc->sc_if; 4184 4185 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4186 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4187 } 4188 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4189 ath_tx_processq(sc, sc->sc_cabq); 4190 4191 if (sc->sc_softled) 4192 ath_led_event(sc, ATH_LED_TX); 4193 4194 ath_start(ifp); 4195 } 4196 4197 /* 4198 * Deferred processing of transmit interrupt; special-cased 4199 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4200 */ 4201 static void 4202 ath_tx_proc_q0123(void *arg, int npending) 4203 { 4204 struct ath_softc *sc = arg; 4205 struct ifnet *ifp = &sc->sc_if; 4206 int nacked; 4207 4208 /* 4209 * Process each active queue. 4210 */ 4211 nacked = 0; 4212 if (txqactive(sc->sc_ah, 0)) 4213 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4214 if (txqactive(sc->sc_ah, 1)) 4215 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4216 if (txqactive(sc->sc_ah, 2)) 4217 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4218 if (txqactive(sc->sc_ah, 3)) 4219 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4220 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4221 ath_tx_processq(sc, sc->sc_cabq); 4222 if (nacked) { 4223 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4224 } 4225 4226 if (sc->sc_softled) 4227 ath_led_event(sc, ATH_LED_TX); 4228 4229 ath_start(ifp); 4230 } 4231 4232 /* 4233 * Deferred processing of transmit interrupt. 4234 */ 4235 static void 4236 ath_tx_proc(void *arg, int npending) 4237 { 4238 struct ath_softc *sc = arg; 4239 struct ifnet *ifp = &sc->sc_if; 4240 int i, nacked; 4241 4242 /* 4243 * Process each active queue. 4244 */ 4245 nacked = 0; 4246 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4247 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4248 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4249 if (nacked) { 4250 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4251 } 4252 4253 if (sc->sc_softled) 4254 ath_led_event(sc, ATH_LED_TX); 4255 4256 ath_start(ifp); 4257 } 4258 4259 static void 4260 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4261 { 4262 struct ath_hal *ah = sc->sc_ah; 4263 struct ieee80211_node *ni; 4264 struct ath_buf *bf; 4265 struct ath_desc *ds; 4266 4267 /* 4268 * NB: this assumes output has been stopped and 4269 * we do not need to block ath_tx_tasklet 4270 */ 4271 for (;;) { 4272 ATH_TXQ_LOCK(txq); 4273 bf = STAILQ_FIRST(&txq->axq_q); 4274 if (bf == NULL) { 4275 txq->axq_link = NULL; 4276 ATH_TXQ_UNLOCK(txq); 4277 break; 4278 } 4279 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4280 ATH_TXQ_UNLOCK(txq); 4281 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4282 if (sc->sc_debug & ATH_DEBUG_RESET) 4283 ath_printtxbuf(bf, 4284 ath_hal_txprocdesc(ah, bf->bf_desc, 4285 &ds->ds_txstat) == HAL_OK); 4286 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4287 m_freem(bf->bf_m); 4288 bf->bf_m = NULL; 4289 ni = bf->bf_node; 4290 bf->bf_node = NULL; 4291 if (ni != NULL) { 4292 /* 4293 * Reclaim node reference. 4294 */ 4295 ieee80211_free_node(ni); 4296 } 4297 ATH_TXBUF_LOCK(sc); 4298 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4299 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4300 ATH_TXBUF_UNLOCK(sc); 4301 } 4302 } 4303 4304 static void 4305 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4306 { 4307 struct ath_hal *ah = sc->sc_ah; 4308 4309 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4310 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4311 __func__, txq->axq_qnum, 4312 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4313 txq->axq_link); 4314 } 4315 4316 /* 4317 * Drain the transmit queues and reclaim resources. 4318 */ 4319 static void 4320 ath_draintxq(struct ath_softc *sc) 4321 { 4322 struct ath_hal *ah = sc->sc_ah; 4323 int i; 4324 4325 /* XXX return value */ 4326 if (device_is_active(sc->sc_dev)) { 4327 /* don't touch the hardware if marked invalid */ 4328 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4329 DPRINTF(sc, ATH_DEBUG_RESET, 4330 "%s: beacon queue %p\n", __func__, 4331 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4332 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4333 if (ATH_TXQ_SETUP(sc, i)) 4334 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4335 } 4336 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4337 if (ATH_TXQ_SETUP(sc, i)) 4338 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4339 } 4340 4341 /* 4342 * Disable the receive h/w in preparation for a reset. 4343 */ 4344 static void 4345 ath_stoprecv(struct ath_softc *sc) 4346 { 4347 #define PA2DESC(_sc, _pa) \ 4348 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4349 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4350 struct ath_hal *ah = sc->sc_ah; 4351 u_int64_t tsf; 4352 4353 ath_hal_stoppcurecv(ah); /* disable PCU */ 4354 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4355 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4356 DELAY(3000); /* 3ms is long enough for 1 frame */ 4357 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4358 struct ath_buf *bf; 4359 4360 printf("%s: rx queue %p, link %p\n", __func__, 4361 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4362 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4363 struct ath_desc *ds = bf->bf_desc; 4364 tsf = ath_hal_gettsf64(sc->sc_ah); 4365 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4366 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4367 &ds->ds_rxstat); 4368 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4369 ath_printrxbuf(bf, status == HAL_OK); 4370 } 4371 } 4372 sc->sc_rxlink = NULL; /* just in case */ 4373 #undef PA2DESC 4374 } 4375 4376 /* 4377 * Enable the receive h/w following a reset. 4378 */ 4379 static int 4380 ath_startrecv(struct ath_softc *sc) 4381 { 4382 struct ath_hal *ah = sc->sc_ah; 4383 struct ath_buf *bf; 4384 4385 sc->sc_rxlink = NULL; 4386 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4387 int error = ath_rxbuf_init(sc, bf); 4388 if (error != 0) { 4389 DPRINTF(sc, ATH_DEBUG_RECV, 4390 "%s: ath_rxbuf_init failed %d\n", 4391 __func__, error); 4392 return error; 4393 } 4394 } 4395 4396 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4397 ath_hal_putrxbuf(ah, bf->bf_daddr); 4398 ath_hal_rxena(ah); /* enable recv descriptors */ 4399 ath_mode_init(sc); /* set filters, etc. */ 4400 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4401 return 0; 4402 } 4403 4404 /* 4405 * Update internal state after a channel change. 4406 */ 4407 static void 4408 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4409 { 4410 struct ieee80211com *ic = &sc->sc_ic; 4411 enum ieee80211_phymode mode; 4412 u_int16_t flags; 4413 4414 /* 4415 * Change channels and update the h/w rate map 4416 * if we're switching; e.g. 11a to 11b/g. 4417 */ 4418 mode = ieee80211_chan2mode(ic, chan); 4419 if (mode != sc->sc_curmode) 4420 ath_setcurmode(sc, mode); 4421 /* 4422 * Update BPF state. NB: ethereal et. al. don't handle 4423 * merged flags well so pick a unique mode for their use. 4424 */ 4425 if (IEEE80211_IS_CHAN_A(chan)) 4426 flags = IEEE80211_CHAN_A; 4427 /* XXX 11g schizophrenia */ 4428 else if (IEEE80211_IS_CHAN_G(chan) || 4429 IEEE80211_IS_CHAN_PUREG(chan)) 4430 flags = IEEE80211_CHAN_G; 4431 else 4432 flags = IEEE80211_CHAN_B; 4433 if (IEEE80211_IS_CHAN_T(chan)) 4434 flags |= IEEE80211_CHAN_TURBO; 4435 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4436 htole16(chan->ic_freq); 4437 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4438 htole16(flags); 4439 } 4440 4441 #if 0 4442 /* 4443 * Poll for a channel clear indication; this is required 4444 * for channels requiring DFS and not previously visited 4445 * and/or with a recent radar detection. 4446 */ 4447 static void 4448 ath_dfswait(void *arg) 4449 { 4450 struct ath_softc *sc = arg; 4451 struct ath_hal *ah = sc->sc_ah; 4452 HAL_CHANNEL hchan; 4453 4454 ath_hal_radar_wait(ah, &hchan); 4455 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4456 if_printf(&sc->sc_if, 4457 "channel %u/0x%x/0x%x has interference\n", 4458 hchan.channel, hchan.channelFlags, hchan.privFlags); 4459 return; 4460 } 4461 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4462 /* XXX should not happen */ 4463 return; 4464 } 4465 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4466 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4467 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4468 if_printf(&sc->sc_if, 4469 "channel %u/0x%x/0x%x marked clear\n", 4470 hchan.channel, hchan.channelFlags, hchan.privFlags); 4471 } else 4472 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4473 } 4474 #endif 4475 4476 /* 4477 * Set/change channels. If the channel is really being changed, 4478 * it's done by reseting the chip. To accomplish this we must 4479 * first cleanup any pending DMA, then restart stuff after a la 4480 * ath_init. 4481 */ 4482 static int 4483 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4484 { 4485 struct ath_hal *ah = sc->sc_ah; 4486 struct ieee80211com *ic = &sc->sc_ic; 4487 HAL_CHANNEL hchan; 4488 4489 /* 4490 * Convert to a HAL channel description with 4491 * the flags constrained to reflect the current 4492 * operating mode. 4493 */ 4494 hchan.channel = chan->ic_freq; 4495 hchan.channelFlags = ath_chan2flags(ic, chan); 4496 4497 DPRINTF(sc, ATH_DEBUG_RESET, 4498 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4499 __func__, 4500 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4501 sc->sc_curchan.channelFlags), 4502 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4503 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4504 hchan.channel, hchan.channelFlags); 4505 if (hchan.channel != sc->sc_curchan.channel || 4506 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4507 HAL_STATUS status; 4508 4509 /* 4510 * To switch channels clear any pending DMA operations; 4511 * wait long enough for the RX fifo to drain, reset the 4512 * hardware at the new frequency, and then re-enable 4513 * the relevant bits of the h/w. 4514 */ 4515 ath_hal_intrset(ah, 0); /* disable interrupts */ 4516 ath_draintxq(sc); /* clear pending tx frames */ 4517 ath_stoprecv(sc); /* turn off frame recv */ 4518 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4519 if_printf(ic->ic_ifp, "%s: unable to reset " 4520 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4521 __func__, ieee80211_chan2ieee(ic, chan), 4522 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4523 return EIO; 4524 } 4525 sc->sc_curchan = hchan; 4526 ath_update_txpow(sc); /* update tx power state */ 4527 ath_restore_diversity(sc); 4528 sc->sc_calinterval = 1; 4529 sc->sc_caltries = 0; 4530 4531 /* 4532 * Re-enable rx framework. 4533 */ 4534 if (ath_startrecv(sc) != 0) { 4535 if_printf(&sc->sc_if, 4536 "%s: unable to restart recv logic\n", __func__); 4537 return EIO; 4538 } 4539 4540 /* 4541 * Change channels and update the h/w rate map 4542 * if we're switching; e.g. 11a to 11b/g. 4543 */ 4544 ic->ic_ibss_chan = chan; 4545 ath_chan_change(sc, chan); 4546 4547 #if 0 4548 /* 4549 * Handle DFS required waiting period to determine 4550 * if channel is clear of radar traffic. 4551 */ 4552 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4553 #define DFS_AND_NOT_CLEAR(_c) \ 4554 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4555 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4556 if_printf(&sc->sc_if, 4557 "wait for DFS clear channel signal\n"); 4558 /* XXX stop sndq */ 4559 sc->sc_if.if_flags |= IFF_OACTIVE; 4560 callout_reset(&sc->sc_dfs_ch, 4561 2 * hz, ath_dfswait, sc); 4562 } else 4563 callout_stop(&sc->sc_dfs_ch); 4564 #undef DFS_NOT_CLEAR 4565 } 4566 #endif 4567 4568 /* 4569 * Re-enable interrupts. 4570 */ 4571 ath_hal_intrset(ah, sc->sc_imask); 4572 } 4573 return 0; 4574 } 4575 4576 static void 4577 ath_next_scan(void *arg) 4578 { 4579 struct ath_softc *sc = arg; 4580 struct ieee80211com *ic = &sc->sc_ic; 4581 int s; 4582 4583 /* don't call ath_start w/o network interrupts blocked */ 4584 s = splnet(); 4585 4586 if (ic->ic_state == IEEE80211_S_SCAN) 4587 ieee80211_next_scan(ic); 4588 splx(s); 4589 } 4590 4591 /* 4592 * Periodically recalibrate the PHY to account 4593 * for temperature/environment changes. 4594 */ 4595 static void 4596 ath_calibrate(void *arg) 4597 { 4598 struct ath_softc *sc = arg; 4599 struct ath_hal *ah = sc->sc_ah; 4600 HAL_BOOL iqCalDone; 4601 4602 sc->sc_stats.ast_per_cal++; 4603 4604 ATH_LOCK(sc); 4605 4606 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4607 /* 4608 * Rfgain is out of bounds, reset the chip 4609 * to load new gain values. 4610 */ 4611 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4612 "%s: rfgain change\n", __func__); 4613 sc->sc_stats.ast_per_rfgain++; 4614 ath_reset(&sc->sc_if); 4615 } 4616 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4617 DPRINTF(sc, ATH_DEBUG_ANY, 4618 "%s: calibration of channel %u failed\n", 4619 __func__, sc->sc_curchan.channel); 4620 sc->sc_stats.ast_per_calfail++; 4621 } 4622 /* 4623 * Calibrate noise floor data again in case of change. 4624 */ 4625 ath_hal_process_noisefloor(ah); 4626 /* 4627 * Poll more frequently when the IQ calibration is in 4628 * progress to speedup loading the final settings. 4629 * We temper this aggressive polling with an exponential 4630 * back off after 4 tries up to ath_calinterval. 4631 */ 4632 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4633 sc->sc_caltries = 0; 4634 sc->sc_calinterval = ath_calinterval; 4635 } else if (sc->sc_caltries > 4) { 4636 sc->sc_caltries = 0; 4637 sc->sc_calinterval <<= 1; 4638 if (sc->sc_calinterval > ath_calinterval) 4639 sc->sc_calinterval = ath_calinterval; 4640 } 4641 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4642 ("bad calibration interval %u", sc->sc_calinterval)); 4643 4644 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4645 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4646 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4647 sc->sc_caltries++; 4648 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4649 ath_calibrate, sc); 4650 ATH_UNLOCK(sc); 4651 } 4652 4653 static int 4654 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4655 { 4656 struct ifnet *ifp = ic->ic_ifp; 4657 struct ath_softc *sc = ifp->if_softc; 4658 struct ath_hal *ah = sc->sc_ah; 4659 struct ieee80211_node *ni; 4660 int i, error; 4661 const u_int8_t *bssid; 4662 u_int32_t rfilt; 4663 static const HAL_LED_STATE leds[] = { 4664 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4665 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4666 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4667 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4668 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4669 }; 4670 4671 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4672 ieee80211_state_name[ic->ic_state], 4673 ieee80211_state_name[nstate]); 4674 4675 callout_stop(&sc->sc_scan_ch); 4676 callout_stop(&sc->sc_cal_ch); 4677 #if 0 4678 callout_stop(&sc->sc_dfs_ch); 4679 #endif 4680 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4681 4682 if (nstate == IEEE80211_S_INIT) { 4683 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4684 /* 4685 * NB: disable interrupts so we don't rx frames. 4686 */ 4687 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4688 /* 4689 * Notify the rate control algorithm. 4690 */ 4691 ath_rate_newstate(sc, nstate); 4692 goto done; 4693 } 4694 ni = ic->ic_bss; 4695 error = ath_chan_set(sc, ic->ic_curchan); 4696 if (error != 0) 4697 goto bad; 4698 rfilt = ath_calcrxfilter(sc, nstate); 4699 if (nstate == IEEE80211_S_SCAN) 4700 bssid = ifp->if_broadcastaddr; 4701 else 4702 bssid = ni->ni_bssid; 4703 ath_hal_setrxfilter(ah, rfilt); 4704 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4705 __func__, rfilt, ether_sprintf(bssid)); 4706 4707 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4708 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4709 else 4710 ath_hal_setassocid(ah, bssid, 0); 4711 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4712 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4713 if (ath_hal_keyisvalid(ah, i)) 4714 ath_hal_keysetmac(ah, i, bssid); 4715 } 4716 4717 /* 4718 * Notify the rate control algorithm so rates 4719 * are setup should ath_beacon_alloc be called. 4720 */ 4721 ath_rate_newstate(sc, nstate); 4722 4723 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4724 /* nothing to do */; 4725 } else if (nstate == IEEE80211_S_RUN) { 4726 DPRINTF(sc, ATH_DEBUG_STATE, 4727 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4728 "capinfo=0x%04x chan=%d\n" 4729 , __func__ 4730 , ic->ic_flags 4731 , ni->ni_intval 4732 , ether_sprintf(ni->ni_bssid) 4733 , ni->ni_capinfo 4734 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4735 4736 switch (ic->ic_opmode) { 4737 case IEEE80211_M_HOSTAP: 4738 case IEEE80211_M_IBSS: 4739 /* 4740 * Allocate and setup the beacon frame. 4741 * 4742 * Stop any previous beacon DMA. This may be 4743 * necessary, for example, when an ibss merge 4744 * causes reconfiguration; there will be a state 4745 * transition from RUN->RUN that means we may 4746 * be called with beacon transmission active. 4747 */ 4748 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4749 ath_beacon_free(sc); 4750 error = ath_beacon_alloc(sc, ni); 4751 if (error != 0) 4752 goto bad; 4753 /* 4754 * If joining an adhoc network defer beacon timer 4755 * configuration to the next beacon frame so we 4756 * have a current TSF to use. Otherwise we're 4757 * starting an ibss/bss so there's no need to delay. 4758 */ 4759 if (ic->ic_opmode == IEEE80211_M_IBSS && 4760 ic->ic_bss->ni_tstamp.tsf != 0) 4761 sc->sc_syncbeacon = 1; 4762 else 4763 ath_beacon_config(sc); 4764 break; 4765 case IEEE80211_M_STA: 4766 /* 4767 * Allocate a key cache slot to the station. 4768 */ 4769 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4770 sc->sc_hasclrkey && 4771 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4772 ath_setup_stationkey(ni); 4773 /* 4774 * Defer beacon timer configuration to the next 4775 * beacon frame so we have a current TSF to use 4776 * (any TSF collected when scanning is likely old). 4777 */ 4778 sc->sc_syncbeacon = 1; 4779 break; 4780 default: 4781 break; 4782 } 4783 /* 4784 * Let the hal process statistics collected during a 4785 * scan so it can provide calibrated noise floor data. 4786 */ 4787 ath_hal_process_noisefloor(ah); 4788 /* 4789 * Reset rssi stats; maybe not the best place... 4790 */ 4791 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4792 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4793 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4794 } else { 4795 ath_hal_intrset(ah, 4796 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4797 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4798 } 4799 done: 4800 /* 4801 * Invoke the parent method to complete the work. 4802 */ 4803 error = sc->sc_newstate(ic, nstate, arg); 4804 /* 4805 * Finally, start any timers. 4806 */ 4807 if (nstate == IEEE80211_S_RUN) { 4808 /* start periodic recalibration timer */ 4809 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4810 ath_calibrate, sc); 4811 } else if (nstate == IEEE80211_S_SCAN) { 4812 /* start ap/neighbor scan timer */ 4813 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4814 ath_next_scan, sc); 4815 } 4816 bad: 4817 return error; 4818 } 4819 4820 /* 4821 * Allocate a key cache slot to the station so we can 4822 * setup a mapping from key index to node. The key cache 4823 * slot is needed for managing antenna state and for 4824 * compression when stations do not use crypto. We do 4825 * it uniliaterally here; if crypto is employed this slot 4826 * will be reassigned. 4827 */ 4828 static void 4829 ath_setup_stationkey(struct ieee80211_node *ni) 4830 { 4831 struct ieee80211com *ic = ni->ni_ic; 4832 struct ath_softc *sc = ic->ic_ifp->if_softc; 4833 ieee80211_keyix keyix, rxkeyix; 4834 4835 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4836 /* 4837 * Key cache is full; we'll fall back to doing 4838 * the more expensive lookup in software. Note 4839 * this also means no h/w compression. 4840 */ 4841 /* XXX msg+statistic */ 4842 } else { 4843 /* XXX locking? */ 4844 ni->ni_ucastkey.wk_keyix = keyix; 4845 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4846 /* NB: this will create a pass-thru key entry */ 4847 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4848 } 4849 } 4850 4851 /* 4852 * Setup driver-specific state for a newly associated node. 4853 * Note that we're called also on a re-associate, the isnew 4854 * param tells us if this is the first time or not. 4855 */ 4856 static void 4857 ath_newassoc(struct ieee80211_node *ni, int isnew) 4858 { 4859 struct ieee80211com *ic = ni->ni_ic; 4860 struct ath_softc *sc = ic->ic_ifp->if_softc; 4861 4862 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4863 if (isnew && 4864 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4865 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4866 ("new assoc with a unicast key already setup (keyix %u)", 4867 ni->ni_ucastkey.wk_keyix)); 4868 ath_setup_stationkey(ni); 4869 } 4870 } 4871 4872 static int 4873 ath_getchannels(struct ath_softc *sc, u_int cc, 4874 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4875 { 4876 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4877 struct ieee80211com *ic = &sc->sc_ic; 4878 struct ifnet *ifp = &sc->sc_if; 4879 struct ath_hal *ah = sc->sc_ah; 4880 HAL_CHANNEL *chans; 4881 int i, ix, nchan; 4882 4883 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4884 M_TEMP, M_NOWAIT); 4885 if (chans == NULL) { 4886 if_printf(ifp, "unable to allocate channel table\n"); 4887 return ENOMEM; 4888 } 4889 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4890 NULL, 0, NULL, 4891 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4892 u_int32_t rd; 4893 4894 (void)ath_hal_getregdomain(ah, &rd); 4895 if_printf(ifp, "unable to collect channel list from hal; " 4896 "regdomain likely %u country code %u\n", rd, cc); 4897 free(chans, M_TEMP); 4898 return EINVAL; 4899 } 4900 4901 /* 4902 * Convert HAL channels to ieee80211 ones and insert 4903 * them in the table according to their channel number. 4904 */ 4905 for (i = 0; i < nchan; i++) { 4906 HAL_CHANNEL *c = &chans[i]; 4907 u_int16_t flags; 4908 4909 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4910 if (ix > IEEE80211_CHAN_MAX) { 4911 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4912 ix, c->channel, c->channelFlags); 4913 continue; 4914 } 4915 if (ix < 0) { 4916 /* XXX can't handle stuff <2400 right now */ 4917 if (bootverbose) 4918 if_printf(ifp, "hal channel %d (%u/%x) " 4919 "cannot be handled; ignored\n", 4920 ix, c->channel, c->channelFlags); 4921 continue; 4922 } 4923 /* 4924 * Calculate net80211 flags; most are compatible 4925 * but some need massaging. Note the static turbo 4926 * conversion can be removed once net80211 is updated 4927 * to understand static vs. dynamic turbo. 4928 */ 4929 flags = c->channelFlags & COMPAT; 4930 if (c->channelFlags & CHANNEL_STURBO) 4931 flags |= IEEE80211_CHAN_TURBO; 4932 if (ic->ic_channels[ix].ic_freq == 0) { 4933 ic->ic_channels[ix].ic_freq = c->channel; 4934 ic->ic_channels[ix].ic_flags = flags; 4935 } else { 4936 /* channels overlap; e.g. 11g and 11b */ 4937 ic->ic_channels[ix].ic_flags |= flags; 4938 } 4939 } 4940 free(chans, M_TEMP); 4941 return 0; 4942 #undef COMPAT 4943 } 4944 4945 static void 4946 ath_led_done(void *arg) 4947 { 4948 struct ath_softc *sc = arg; 4949 4950 sc->sc_blinking = 0; 4951 } 4952 4953 /* 4954 * Turn the LED off: flip the pin and then set a timer so no 4955 * update will happen for the specified duration. 4956 */ 4957 static void 4958 ath_led_off(void *arg) 4959 { 4960 struct ath_softc *sc = arg; 4961 4962 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4963 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4964 } 4965 4966 /* 4967 * Blink the LED according to the specified on/off times. 4968 */ 4969 static void 4970 ath_led_blink(struct ath_softc *sc, int on, int off) 4971 { 4972 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4973 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4974 sc->sc_blinking = 1; 4975 sc->sc_ledoff = off; 4976 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4977 } 4978 4979 static void 4980 ath_led_event(struct ath_softc *sc, int event) 4981 { 4982 4983 sc->sc_ledevent = ticks; /* time of last event */ 4984 if (sc->sc_blinking) /* don't interrupt active blink */ 4985 return; 4986 switch (event) { 4987 case ATH_LED_POLL: 4988 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4989 sc->sc_hwmap[0].ledoff); 4990 break; 4991 case ATH_LED_TX: 4992 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4993 sc->sc_hwmap[sc->sc_txrate].ledoff); 4994 break; 4995 case ATH_LED_RX: 4996 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4997 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4998 break; 4999 } 5000 } 5001 5002 static void 5003 ath_update_txpow(struct ath_softc *sc) 5004 { 5005 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 5006 struct ieee80211com *ic = &sc->sc_ic; 5007 struct ath_hal *ah = sc->sc_ah; 5008 u_int32_t txpow; 5009 5010 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 5011 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 5012 /* read back in case value is clamped */ 5013 (void)ath_hal_gettxpowlimit(ah, &txpow); 5014 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 5015 } 5016 /* 5017 * Fetch max tx power level for status requests. 5018 */ 5019 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 5020 ic->ic_bss->ni_txpower = txpow; 5021 } 5022 5023 static void 5024 rate_setup(struct ath_softc *sc, 5025 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 5026 { 5027 int i, maxrates; 5028 5029 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 5030 DPRINTF(sc, ATH_DEBUG_ANY, 5031 "%s: rate table too small (%u > %u)\n", 5032 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 5033 maxrates = IEEE80211_RATE_MAXSIZE; 5034 } else 5035 maxrates = rt->rateCount; 5036 for (i = 0; i < maxrates; i++) 5037 rs->rs_rates[i] = rt->info[i].dot11Rate; 5038 rs->rs_nrates = maxrates; 5039 } 5040 5041 static int 5042 ath_rate_setup(struct ath_softc *sc, u_int mode) 5043 { 5044 struct ath_hal *ah = sc->sc_ah; 5045 struct ieee80211com *ic = &sc->sc_ic; 5046 const HAL_RATE_TABLE *rt; 5047 5048 switch (mode) { 5049 case IEEE80211_MODE_11A: 5050 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5051 break; 5052 case IEEE80211_MODE_11B: 5053 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5054 break; 5055 case IEEE80211_MODE_11G: 5056 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5057 break; 5058 case IEEE80211_MODE_TURBO_A: 5059 /* XXX until static/dynamic turbo is fixed */ 5060 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5061 break; 5062 case IEEE80211_MODE_TURBO_G: 5063 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5064 break; 5065 default: 5066 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5067 __func__, mode); 5068 return 0; 5069 } 5070 sc->sc_rates[mode] = rt; 5071 if (rt != NULL) { 5072 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5073 return 1; 5074 } else 5075 return 0; 5076 } 5077 5078 static void 5079 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5080 { 5081 #define N(a) (sizeof(a)/sizeof(a[0])) 5082 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5083 static const struct { 5084 u_int rate; /* tx/rx 802.11 rate */ 5085 u_int16_t timeOn; /* LED on time (ms) */ 5086 u_int16_t timeOff; /* LED off time (ms) */ 5087 } blinkrates[] = { 5088 { 108, 40, 10 }, 5089 { 96, 44, 11 }, 5090 { 72, 50, 13 }, 5091 { 48, 57, 14 }, 5092 { 36, 67, 16 }, 5093 { 24, 80, 20 }, 5094 { 22, 100, 25 }, 5095 { 18, 133, 34 }, 5096 { 12, 160, 40 }, 5097 { 10, 200, 50 }, 5098 { 6, 240, 58 }, 5099 { 4, 267, 66 }, 5100 { 2, 400, 100 }, 5101 { 0, 500, 130 }, 5102 }; 5103 const HAL_RATE_TABLE *rt; 5104 int i, j; 5105 5106 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5107 rt = sc->sc_rates[mode]; 5108 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5109 for (i = 0; i < rt->rateCount; i++) 5110 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5111 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5112 for (i = 0; i < 32; i++) { 5113 u_int8_t ix = rt->rateCodeToIndex[i]; 5114 if (ix == 0xff) { 5115 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5116 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5117 continue; 5118 } 5119 sc->sc_hwmap[i].ieeerate = 5120 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5121 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5122 if (rt->info[ix].shortPreamble || 5123 rt->info[ix].phy == IEEE80211_T_OFDM) 5124 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5125 /* NB: receive frames include FCS */ 5126 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5127 IEEE80211_RADIOTAP_F_FCS; 5128 /* setup blink rate table to avoid per-packet lookup */ 5129 for (j = 0; j < N(blinkrates)-1; j++) 5130 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5131 break; 5132 /* NB: this uses the last entry if the rate isn't found */ 5133 /* XXX beware of overlow */ 5134 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5135 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5136 } 5137 sc->sc_currates = rt; 5138 sc->sc_curmode = mode; 5139 /* 5140 * All protection frames are transmited at 2Mb/s for 5141 * 11g, otherwise at 1Mb/s. 5142 */ 5143 if (mode == IEEE80211_MODE_11G) 5144 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5145 else 5146 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5147 /* rate index used to send management frames */ 5148 sc->sc_minrateix = 0; 5149 /* 5150 * Setup multicast rate state. 5151 */ 5152 /* XXX layering violation */ 5153 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5154 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5155 /* NB: caller is responsible for reseting rate control state */ 5156 #undef N 5157 } 5158 5159 #ifdef AR_DEBUG 5160 static void 5161 ath_printrxbuf(struct ath_buf *bf, int done) 5162 { 5163 struct ath_desc *ds; 5164 int i; 5165 5166 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5167 printf("R%d (%p %" PRIx64 5168 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5169 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5170 ds->ds_link, ds->ds_data, 5171 ds->ds_ctl0, ds->ds_ctl1, 5172 ds->ds_hw[0], ds->ds_hw[1], 5173 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5174 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5175 } 5176 } 5177 5178 static void 5179 ath_printtxbuf(struct ath_buf *bf, int done) 5180 { 5181 struct ath_desc *ds; 5182 int i; 5183 5184 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5185 printf("T%d (%p %" PRIx64 5186 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5187 i, ds, 5188 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5189 ds->ds_link, ds->ds_data, 5190 ds->ds_ctl0, ds->ds_ctl1, 5191 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5192 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5193 } 5194 } 5195 #endif /* AR_DEBUG */ 5196 5197 static void 5198 ath_watchdog(struct ifnet *ifp) 5199 { 5200 struct ath_softc *sc = ifp->if_softc; 5201 struct ieee80211com *ic = &sc->sc_ic; 5202 struct ath_txq *axq; 5203 int i; 5204 5205 ifp->if_timer = 0; 5206 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5207 !device_is_active(sc->sc_dev)) 5208 return; 5209 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5210 if (!ATH_TXQ_SETUP(sc, i)) 5211 continue; 5212 axq = &sc->sc_txq[i]; 5213 ATH_TXQ_LOCK(axq); 5214 if (axq->axq_timer == 0) 5215 ; 5216 else if (--axq->axq_timer == 0) { 5217 ATH_TXQ_UNLOCK(axq); 5218 if_printf(ifp, "device timeout (txq %d, " 5219 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5220 if (sc->sc_txintrperiod > 1) 5221 sc->sc_txintrperiod--; 5222 ath_reset(ifp); 5223 ifp->if_oerrors++; 5224 sc->sc_stats.ast_watchdog++; 5225 break; 5226 } else 5227 ifp->if_timer = 1; 5228 ATH_TXQ_UNLOCK(axq); 5229 } 5230 ieee80211_watchdog(ic); 5231 } 5232 5233 /* 5234 * Diagnostic interface to the HAL. This is used by various 5235 * tools to do things like retrieve register contents for 5236 * debugging. The mechanism is intentionally opaque so that 5237 * it can change frequently w/o concern for compatiblity. 5238 */ 5239 static int 5240 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5241 { 5242 struct ath_hal *ah = sc->sc_ah; 5243 u_int id = ad->ad_id & ATH_DIAG_ID; 5244 void *indata = NULL; 5245 void *outdata = NULL; 5246 u_int32_t insize = ad->ad_in_size; 5247 u_int32_t outsize = ad->ad_out_size; 5248 int error = 0; 5249 5250 if (ad->ad_id & ATH_DIAG_IN) { 5251 /* 5252 * Copy in data. 5253 */ 5254 indata = malloc(insize, M_TEMP, M_NOWAIT); 5255 if (indata == NULL) { 5256 error = ENOMEM; 5257 goto bad; 5258 } 5259 error = copyin(ad->ad_in_data, indata, insize); 5260 if (error) 5261 goto bad; 5262 } 5263 if (ad->ad_id & ATH_DIAG_DYN) { 5264 /* 5265 * Allocate a buffer for the results (otherwise the HAL 5266 * returns a pointer to a buffer where we can read the 5267 * results). Note that we depend on the HAL leaving this 5268 * pointer for us to use below in reclaiming the buffer; 5269 * may want to be more defensive. 5270 */ 5271 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5272 if (outdata == NULL) { 5273 error = ENOMEM; 5274 goto bad; 5275 } 5276 } 5277 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5278 if (outsize < ad->ad_out_size) 5279 ad->ad_out_size = outsize; 5280 if (outdata != NULL) 5281 error = copyout(outdata, ad->ad_out_data, 5282 ad->ad_out_size); 5283 } else { 5284 error = EINVAL; 5285 } 5286 bad: 5287 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5288 free(indata, M_TEMP); 5289 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5290 free(outdata, M_TEMP); 5291 return error; 5292 } 5293 5294 static int 5295 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5296 { 5297 #define IS_RUNNING(ifp) \ 5298 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5299 struct ath_softc *sc = ifp->if_softc; 5300 struct ieee80211com *ic = &sc->sc_ic; 5301 struct ifreq *ifr = (struct ifreq *)data; 5302 int error = 0; 5303 5304 ATH_LOCK(sc); 5305 switch (cmd) { 5306 case SIOCSIFFLAGS: 5307 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5308 break; 5309 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 5310 case IFF_UP|IFF_RUNNING: 5311 /* 5312 * To avoid rescanning another access point, 5313 * do not call ath_init() here. Instead, 5314 * only reflect promisc mode settings. 5315 */ 5316 ath_mode_init(sc); 5317 break; 5318 case IFF_UP: 5319 /* 5320 * Beware of being called during attach/detach 5321 * to reset promiscuous mode. In that case we 5322 * will still be marked UP but not RUNNING. 5323 * However trying to re-init the interface 5324 * is the wrong thing to do as we've already 5325 * torn down much of our state. There's 5326 * probably a better way to deal with this. 5327 */ 5328 error = ath_init(sc); 5329 break; 5330 case IFF_RUNNING: 5331 ath_stop_locked(ifp, 1); 5332 break; 5333 case 0: 5334 break; 5335 } 5336 break; 5337 case SIOCADDMULTI: 5338 case SIOCDELMULTI: 5339 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5340 if (ifp->if_flags & IFF_RUNNING) 5341 ath_mode_init(sc); 5342 error = 0; 5343 } 5344 break; 5345 case SIOCGATHSTATS: 5346 /* NB: embed these numbers to get a consistent view */ 5347 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5348 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5349 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5350 ATH_UNLOCK(sc); 5351 /* 5352 * NB: Drop the softc lock in case of a page fault; 5353 * we'll accept any potential inconsisentcy in the 5354 * statistics. The alternative is to copy the data 5355 * to a local structure. 5356 */ 5357 return copyout(&sc->sc_stats, 5358 ifr->ifr_data, sizeof (sc->sc_stats)); 5359 case SIOCGATHDIAG: 5360 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5361 break; 5362 default: 5363 error = ieee80211_ioctl(ic, cmd, data); 5364 if (error != ENETRESET) 5365 ; 5366 else if (IS_RUNNING(ifp) && 5367 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5368 error = ath_init(sc); 5369 else 5370 error = 0; 5371 break; 5372 } 5373 ATH_UNLOCK(sc); 5374 return error; 5375 #undef IS_RUNNING 5376 } 5377 5378 static void 5379 ath_bpfattach(struct ath_softc *sc) 5380 { 5381 struct ifnet *ifp = &sc->sc_if; 5382 5383 bpf_ops->bpf_attach(ifp, DLT_IEEE802_11_RADIO, 5384 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5385 &sc->sc_drvbpf); 5386 5387 /* 5388 * Initialize constant fields. 5389 * XXX make header lengths a multiple of 32-bits so subsequent 5390 * headers are properly aligned; this is a kludge to keep 5391 * certain applications happy. 5392 * 5393 * NB: the channel is setup each time we transition to the 5394 * RUN state to avoid filling it in for each frame. 5395 */ 5396 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5397 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5398 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5399 5400 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5401 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5402 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5403 } 5404 5405 /* 5406 * Announce various information on device/driver attach. 5407 */ 5408 static void 5409 ath_announce(struct ath_softc *sc) 5410 { 5411 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5412 struct ifnet *ifp = &sc->sc_if; 5413 struct ath_hal *ah = sc->sc_ah; 5414 u_int modes, cc; 5415 5416 if_printf(ifp, "mac %d.%d phy %d.%d", 5417 ah->ah_macVersion, ah->ah_macRev, 5418 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5419 /* 5420 * Print radio revision(s). We check the wireless modes 5421 * to avoid falsely printing revs for inoperable parts. 5422 * Dual-band radio revs are returned in the 5 GHz rev number. 5423 */ 5424 ath_hal_getcountrycode(ah, &cc); 5425 modes = ath_hal_getwirelessmodes(ah, cc); 5426 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5427 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5428 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5429 ah->ah_analog5GhzRev >> 4, 5430 ah->ah_analog5GhzRev & 0xf, 5431 ah->ah_analog2GhzRev >> 4, 5432 ah->ah_analog2GhzRev & 0xf); 5433 else 5434 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5435 ah->ah_analog5GhzRev & 0xf); 5436 } else 5437 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5438 ah->ah_analog5GhzRev & 0xf); 5439 printf("\n"); 5440 if (bootverbose) { 5441 int i; 5442 for (i = 0; i <= WME_AC_VO; i++) { 5443 struct ath_txq *txq = sc->sc_ac2q[i]; 5444 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5445 txq->axq_qnum, ieee80211_wme_acnames[i]); 5446 } 5447 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5448 sc->sc_cabq->axq_qnum); 5449 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5450 } 5451 if (ath_rxbuf != ATH_RXBUF) 5452 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5453 if (ath_txbuf != ATH_TXBUF) 5454 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5455 #undef HAL_MODE_DUALBAND 5456 } 5457
Indexes created Thu Oct 02 07:10:07 GMT 2025