athn.c revision 1.26 1 1.26 riastrad /* $NetBSD: athn.c,v 1.26 2022/03/18 23:32:24 riastradh Exp $ */
2 1.9 christos /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */
3 1.1 christos
4 1.1 christos /*-
5 1.1 christos * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr>
6 1.1 christos * Copyright (c) 2008-2010 Atheros Communications Inc.
7 1.1 christos *
8 1.1 christos * Permission to use, copy, modify, and/or distribute this software for any
9 1.1 christos * purpose with or without fee is hereby granted, provided that the above
10 1.1 christos * copyright notice and this permission notice appear in all copies.
11 1.1 christos *
12 1.1 christos * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 1.1 christos * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 1.1 christos * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 1.1 christos * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 1.1 christos * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 1.1 christos * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 1.1 christos * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 1.1 christos */
20 1.1 christos
21 1.1 christos /*
22 1.1 christos * Driver for Atheros 802.11a/g/n chipsets.
23 1.1 christos */
24 1.1 christos
25 1.1 christos #include <sys/cdefs.h>
26 1.26 riastrad __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.26 2022/03/18 23:32:24 riastradh Exp $");
27 1.1 christos
28 1.1 christos #ifndef _MODULE
29 1.1 christos #include "athn_usb.h" /* for NATHN_USB */
30 1.1 christos #endif
31 1.1 christos
32 1.1 christos #include <sys/param.h>
33 1.1 christos #include <sys/sockio.h>
34 1.1 christos #include <sys/mbuf.h>
35 1.1 christos #include <sys/kernel.h>
36 1.1 christos #include <sys/socket.h>
37 1.1 christos #include <sys/systm.h>
38 1.1 christos #include <sys/malloc.h>
39 1.1 christos #include <sys/queue.h>
40 1.1 christos #include <sys/callout.h>
41 1.1 christos #include <sys/conf.h>
42 1.4 martin #include <sys/cpu.h>
43 1.1 christos #include <sys/device.h>
44 1.1 christos
45 1.1 christos #include <sys/bus.h>
46 1.1 christos #include <sys/endian.h>
47 1.1 christos #include <sys/intr.h>
48 1.1 christos
49 1.1 christos #include <net/bpf.h>
50 1.1 christos #include <net/if.h>
51 1.1 christos #include <net/if_arp.h>
52 1.1 christos #include <net/if_dl.h>
53 1.1 christos #include <net/if_ether.h>
54 1.1 christos #include <net/if_media.h>
55 1.1 christos #include <net/if_types.h>
56 1.1 christos
57 1.1 christos #include <netinet/in.h>
58 1.1 christos #include <netinet/in_systm.h>
59 1.1 christos #include <netinet/in_var.h>
60 1.1 christos #include <netinet/ip.h>
61 1.1 christos
62 1.1 christos #include <net80211/ieee80211_var.h>
63 1.1 christos #include <net80211/ieee80211_amrr.h>
64 1.1 christos #include <net80211/ieee80211_radiotap.h>
65 1.1 christos
66 1.1 christos #include <dev/ic/athnreg.h>
67 1.1 christos #include <dev/ic/athnvar.h>
68 1.1 christos #include <dev/ic/arn5008.h>
69 1.1 christos #include <dev/ic/arn5416.h>
70 1.1 christos #include <dev/ic/arn9003.h>
71 1.1 christos #include <dev/ic/arn9280.h>
72 1.1 christos #include <dev/ic/arn9285.h>
73 1.1 christos #include <dev/ic/arn9287.h>
74 1.1 christos #include <dev/ic/arn9380.h>
75 1.1 christos
76 1.1 christos #define Static static
77 1.1 christos
78 1.1 christos #define IS_UP_AND_RUNNING(ifp) \
79 1.1 christos (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING))
80 1.1 christos
81 1.1 christos #ifdef ATHN_DEBUG
82 1.1 christos int athn_debug = 0;
83 1.1 christos #endif
84 1.1 christos
85 1.1 christos Static int athn_clock_rate(struct athn_softc *);
86 1.1 christos Static const char *
87 1.1 christos athn_get_mac_name(struct athn_softc *);
88 1.1 christos Static const char *
89 1.1 christos athn_get_rf_name(struct athn_softc *);
90 1.1 christos Static int athn_init(struct ifnet *);
91 1.1 christos Static int athn_init_calib(struct athn_softc *,
92 1.1 christos struct ieee80211_channel *, struct ieee80211_channel *);
93 1.1 christos Static int athn_ioctl(struct ifnet *, u_long, void *);
94 1.1 christos Static int athn_media_change(struct ifnet *);
95 1.1 christos Static int athn_newstate(struct ieee80211com *, enum ieee80211_state,
96 1.1 christos int);
97 1.1 christos Static struct ieee80211_node *
98 1.1 christos athn_node_alloc(struct ieee80211_node_table *);
99 1.1 christos Static int athn_reset_power_on(struct athn_softc *);
100 1.1 christos Static int athn_stop_rx_dma(struct athn_softc *);
101 1.1 christos Static int athn_switch_chan(struct athn_softc *,
102 1.1 christos struct ieee80211_channel *, struct ieee80211_channel *);
103 1.1 christos Static void athn_calib_to(void *);
104 1.1 christos Static void athn_disable_interrupts(struct athn_softc *);
105 1.1 christos Static void athn_enable_interrupts(struct athn_softc *);
106 1.1 christos Static void athn_get_chanlist(struct athn_softc *);
107 1.1 christos Static void athn_get_chipid(struct athn_softc *);
108 1.1 christos Static void athn_init_dma(struct athn_softc *);
109 1.1 christos Static void athn_init_qos(struct athn_softc *);
110 1.1 christos Static void athn_init_tx_queues(struct athn_softc *);
111 1.1 christos Static void athn_iter_func(void *, struct ieee80211_node *);
112 1.1 christos Static void athn_newassoc(struct ieee80211_node *, int);
113 1.1 christos Static void athn_next_scan(void *);
114 1.5 christos Static void athn_pmf_wlan_off(device_t self);
115 1.1 christos Static void athn_radiotap_attach(struct athn_softc *);
116 1.1 christos Static void athn_start(struct ifnet *);
117 1.1 christos Static void athn_tx_reclaim(struct athn_softc *, int);
118 1.1 christos Static void athn_watchdog(struct ifnet *);
119 1.1 christos Static void athn_write_serdes(struct athn_softc *,
120 1.1 christos const struct athn_serdes *);
121 1.15 nonaka Static void athn_softintr(void *);
122 1.1 christos
123 1.1 christos #ifdef ATHN_BT_COEXISTENCE
124 1.5 christos Static void athn_btcoex_disable(struct athn_softc *);
125 1.1 christos Static void athn_btcoex_enable(struct athn_softc *);
126 1.1 christos #endif
127 1.1 christos
128 1.1 christos #ifdef unused
129 1.1 christos Static int32_t athn_ani_get_rssi(struct athn_softc *);
130 1.1 christos Static int athn_rx_abort(struct athn_softc *);
131 1.1 christos #endif
132 1.1 christos
133 1.1 christos #ifdef notyet
134 1.5 christos Static void athn_ani_cck_err_trigger(struct athn_softc *);
135 1.5 christos Static void athn_ani_lower_immunity(struct athn_softc *);
136 1.1 christos Static void athn_ani_monitor(struct athn_softc *);
137 1.1 christos Static void athn_ani_ofdm_err_trigger(struct athn_softc *);
138 1.1 christos Static void athn_ani_restart(struct athn_softc *);
139 1.20 msaitoh #endif /* notyet */
140 1.1 christos Static void athn_set_multi(struct athn_softc *);
141 1.1 christos
142 1.1 christos PUBLIC int
143 1.1 christos athn_attach(struct athn_softc *sc)
144 1.1 christos {
145 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
146 1.1 christos struct ifnet *ifp = &sc->sc_if;
147 1.1 christos size_t max_nnodes;
148 1.1 christos int error;
149 1.1 christos
150 1.1 christos /* Read hardware revision. */
151 1.1 christos athn_get_chipid(sc);
152 1.1 christos
153 1.1 christos if ((error = athn_reset_power_on(sc)) != 0) {
154 1.1 christos aprint_error_dev(sc->sc_dev, "could not reset chip\n");
155 1.1 christos return error;
156 1.1 christos }
157 1.1 christos
158 1.1 christos if ((error = athn_set_power_awake(sc)) != 0) {
159 1.1 christos aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
160 1.1 christos return error;
161 1.1 christos }
162 1.1 christos
163 1.1 christos if (AR_SREV_5416(sc) || AR_SREV_9160(sc))
164 1.1 christos error = ar5416_attach(sc);
165 1.1 christos else if (AR_SREV_9280(sc))
166 1.1 christos error = ar9280_attach(sc);
167 1.1 christos else if (AR_SREV_9285(sc))
168 1.1 christos error = ar9285_attach(sc);
169 1.1 christos #if NATHN_USB > 0
170 1.1 christos else if (AR_SREV_9271(sc))
171 1.1 christos error = ar9285_attach(sc);
172 1.1 christos #endif
173 1.1 christos else if (AR_SREV_9287(sc))
174 1.1 christos error = ar9287_attach(sc);
175 1.1 christos else if (AR_SREV_9380(sc) || AR_SREV_9485(sc))
176 1.1 christos error = ar9380_attach(sc);
177 1.1 christos else
178 1.1 christos error = ENOTSUP;
179 1.1 christos if (error != 0) {
180 1.1 christos aprint_error_dev(sc->sc_dev, "could not attach chip\n");
181 1.1 christos return error;
182 1.1 christos }
183 1.1 christos
184 1.1 christos pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual);
185 1.3 martin pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off,
186 1.3 martin false);
187 1.1 christos
188 1.1 christos /* We can put the chip in sleep state now. */
189 1.1 christos athn_set_power_sleep(sc);
190 1.1 christos
191 1.1 christos if (!(sc->sc_flags & ATHN_FLAG_USB)) {
192 1.15 nonaka sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr,
193 1.15 nonaka sc);
194 1.15 nonaka if (sc->sc_soft_ih == NULL) {
195 1.15 nonaka aprint_error_dev(sc->sc_dev,
196 1.15 nonaka "could not establish softint\n");
197 1.15 nonaka return EINVAL;
198 1.15 nonaka }
199 1.15 nonaka
200 1.1 christos error = sc->sc_ops.dma_alloc(sc);
201 1.1 christos if (error != 0) {
202 1.1 christos aprint_error_dev(sc->sc_dev,
203 1.1 christos "could not allocate DMA resources\n");
204 1.1 christos return error;
205 1.1 christos }
206 1.1 christos /* Steal one Tx buffer for beacons. */
207 1.1 christos sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs);
208 1.1 christos SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list);
209 1.1 christos }
210 1.1 christos
211 1.1 christos if (sc->sc_flags & ATHN_FLAG_RFSILENT) {
212 1.1 christos DPRINTFN(DBG_INIT, sc,
213 1.1 christos "found RF switch connected to GPIO pin %d\n",
214 1.1 christos sc->sc_rfsilent_pin);
215 1.1 christos }
216 1.1 christos DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries);
217 1.1 christos
218 1.1 christos /*
219 1.1 christos * In HostAP mode, the number of STAs that we can handle is
220 1.1 christos * limited by the number of entries in the HW key cache.
221 1.1 christos * TKIP keys consume 2 entries in the cache.
222 1.1 christos */
223 1.1 christos KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID);
224 1.1 christos max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID;
225 1.1 christos if (sc->sc_max_aid != 0) /* we have an override */
226 1.1 christos ic->ic_max_aid = sc->sc_max_aid;
227 1.1 christos if (ic->ic_max_aid > max_nnodes)
228 1.1 christos ic->ic_max_aid = max_nnodes;
229 1.1 christos
230 1.1 christos DPRINTFN(DBG_INIT, sc, "using %s loop power control\n",
231 1.1 christos (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed");
232 1.1 christos DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n",
233 1.1 christos sc->sc_txchainmask, sc->sc_rxchainmask);
234 1.1 christos
235 1.1 christos /* Count the number of bits set (in lowest 3 bits). */
236 1.1 christos sc->sc_ntxchains =
237 1.1 christos ((sc->sc_txchainmask >> 2) & 1) +
238 1.1 christos ((sc->sc_txchainmask >> 1) & 1) +
239 1.1 christos ((sc->sc_txchainmask >> 0) & 1);
240 1.1 christos sc->sc_nrxchains =
241 1.1 christos ((sc->sc_rxchainmask >> 2) & 1) +
242 1.1 christos ((sc->sc_rxchainmask >> 1) & 1) +
243 1.1 christos ((sc->sc_rxchainmask >> 0) & 1);
244 1.1 christos
245 1.1 christos if (AR_SINGLE_CHIP(sc)) {
246 1.12 jakllsch aprint_normal(": Atheros %s\n", athn_get_mac_name(sc));
247 1.2 martin aprint_verbose_dev(sc->sc_dev,
248 1.2 martin "rev %d (%dT%dR), ROM rev %d, address %s\n",
249 1.2 martin sc->sc_mac_rev,
250 1.1 christos sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev,
251 1.1 christos ether_sprintf(ic->ic_myaddr));
252 1.19 msaitoh } else {
253 1.12 jakllsch aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc),
254 1.2 martin athn_get_rf_name(sc));
255 1.2 martin aprint_verbose_dev(sc->sc_dev,
256 1.2 martin "rev %d (%dT%dR), ROM rev %d, address %s\n",
257 1.2 martin sc->sc_mac_rev,
258 1.2 martin sc->sc_ntxchains, sc->sc_nrxchains,
259 1.1 christos sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr));
260 1.1 christos }
261 1.1 christos
262 1.1 christos callout_init(&sc->sc_scan_to, 0);
263 1.1 christos callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc);
264 1.1 christos callout_init(&sc->sc_calib_to, 0);
265 1.1 christos callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc);
266 1.1 christos
267 1.1 christos sc->sc_amrr.amrr_min_success_threshold = 1;
268 1.1 christos sc->sc_amrr.amrr_max_success_threshold = 15;
269 1.1 christos
270 1.1 christos ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
271 1.1 christos ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
272 1.1 christos ic->ic_state = IEEE80211_S_INIT;
273 1.1 christos
274 1.1 christos /* Set device capabilities. */
275 1.1 christos ic->ic_caps =
276 1.1 christos IEEE80211_C_WPA | /* 802.11i */
277 1.1 christos #ifndef IEEE80211_STA_ONLY
278 1.1 christos IEEE80211_C_HOSTAP | /* Host AP mode supported. */
279 1.1 christos // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */
280 1.1 christos #endif
281 1.1 christos IEEE80211_C_MONITOR | /* Monitor mode supported. */
282 1.1 christos IEEE80211_C_SHSLOT | /* Short slot time supported. */
283 1.1 christos IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
284 1.1 christos IEEE80211_C_PMGT; /* Power saving supported. */
285 1.1 christos
286 1.1 christos #ifndef IEEE80211_NO_HT
287 1.1 christos if (sc->sc_flags & ATHN_FLAG_11N) {
288 1.1 christos int i, ntxstreams, nrxstreams;
289 1.1 christos
290 1.1 christos /* Set HT capabilities. */
291 1.1 christos ic->ic_htcaps =
292 1.1 christos IEEE80211_HTCAP_SMPS_DIS |
293 1.1 christos IEEE80211_HTCAP_CBW20_40 |
294 1.1 christos IEEE80211_HTCAP_SGI40 |
295 1.1 christos IEEE80211_HTCAP_DSSSCCK40;
296 1.1 christos if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc))
297 1.1 christos ic->ic_htcaps |= IEEE80211_HTCAP_SGI20;
298 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc))
299 1.1 christos ic->ic_htcaps |= IEEE80211_HTCAP_LDPC;
300 1.1 christos if (AR_SREV_9280_10_OR_LATER(sc)) {
301 1.1 christos ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
302 1.1 christos ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT;
303 1.1 christos }
304 1.1 christos ntxstreams = sc->sc_ntxchains;
305 1.1 christos nrxstreams = sc->sc_nrxchains;
306 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc)) {
307 1.1 christos ntxstreams = MIN(ntxstreams, 2);
308 1.1 christos nrxstreams = MIN(nrxstreams, 2);
309 1.1 christos }
310 1.1 christos /* Set supported HT rates. */
311 1.1 christos for (i = 0; i < nrxstreams; i++)
312 1.1 christos ic->ic_sup_mcs[i] = 0xff;
313 1.1 christos /* Set the "Tx MCS Set Defined" bit. */
314 1.1 christos ic->ic_sup_mcs[12] |= 0x01;
315 1.1 christos if (ntxstreams != nrxstreams) {
316 1.1 christos /* Set "Tx Rx MCS Set Not Equal" bit. */
317 1.1 christos ic->ic_sup_mcs[12] |= 0x02;
318 1.1 christos ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2;
319 1.1 christos }
320 1.1 christos }
321 1.1 christos #endif
322 1.1 christos
323 1.1 christos /* Set supported rates. */
324 1.1 christos if (sc->sc_flags & ATHN_FLAG_11G) {
325 1.1 christos ic->ic_sup_rates[IEEE80211_MODE_11B] =
326 1.1 christos ieee80211_std_rateset_11b;
327 1.1 christos ic->ic_sup_rates[IEEE80211_MODE_11G] =
328 1.1 christos ieee80211_std_rateset_11g;
329 1.1 christos }
330 1.1 christos if (sc->sc_flags & ATHN_FLAG_11A) {
331 1.1 christos ic->ic_sup_rates[IEEE80211_MODE_11A] =
332 1.1 christos ieee80211_std_rateset_11a;
333 1.1 christos }
334 1.1 christos
335 1.1 christos /* Get the list of authorized/supported channels. */
336 1.1 christos athn_get_chanlist(sc);
337 1.1 christos
338 1.1 christos ifp->if_softc = sc;
339 1.1 christos ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
340 1.14 skrll if (!ifp->if_init)
341 1.14 skrll ifp->if_init = athn_init;
342 1.14 skrll if (!ifp->if_ioctl)
343 1.14 skrll ifp->if_ioctl = athn_ioctl;
344 1.14 skrll if (!ifp->if_start)
345 1.14 skrll ifp->if_start = athn_start;
346 1.14 skrll if (!ifp->if_watchdog)
347 1.14 skrll ifp->if_watchdog = athn_watchdog;
348 1.1 christos IFQ_SET_READY(&ifp->if_snd);
349 1.1 christos memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
350 1.1 christos
351 1.25 riastrad if_initialize(ifp);
352 1.1 christos ieee80211_ifattach(ic);
353 1.15 nonaka /* Use common softint-based if_input */
354 1.15 nonaka ifp->if_percpuq = if_percpuq_create(ifp);
355 1.15 nonaka if_register(ifp);
356 1.1 christos
357 1.1 christos ic->ic_node_alloc = athn_node_alloc;
358 1.1 christos ic->ic_newassoc = athn_newassoc;
359 1.1 christos if (ic->ic_updateslot == NULL)
360 1.1 christos ic->ic_updateslot = athn_updateslot;
361 1.1 christos #ifdef notyet_edca
362 1.1 christos ic->ic_updateedca = athn_updateedca;
363 1.1 christos #endif
364 1.1 christos #ifdef notyet
365 1.1 christos ic->ic_set_key = athn_set_key;
366 1.1 christos ic->ic_delete_key = athn_delete_key;
367 1.1 christos #endif
368 1.1 christos
369 1.1 christos /* Override 802.11 state transition machine. */
370 1.1 christos sc->sc_newstate = ic->ic_newstate;
371 1.1 christos ic->ic_newstate = athn_newstate;
372 1.1 christos
373 1.1 christos if (sc->sc_media_change == NULL)
374 1.1 christos sc->sc_media_change = athn_media_change;
375 1.1 christos ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status);
376 1.1 christos
377 1.1 christos athn_radiotap_attach(sc);
378 1.1 christos return 0;
379 1.1 christos }
380 1.1 christos
381 1.1 christos PUBLIC void
382 1.1 christos athn_detach(struct athn_softc *sc)
383 1.1 christos {
384 1.1 christos struct ifnet *ifp = &sc->sc_if;
385 1.1 christos int qid;
386 1.1 christos
387 1.1 christos callout_halt(&sc->sc_scan_to, NULL);
388 1.1 christos callout_halt(&sc->sc_calib_to, NULL);
389 1.1 christos
390 1.1 christos if (!(sc->sc_flags & ATHN_FLAG_USB)) {
391 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
392 1.1 christos athn_tx_reclaim(sc, qid);
393 1.1 christos
394 1.1 christos /* Free Tx/Rx DMA resources. */
395 1.1 christos sc->sc_ops.dma_free(sc);
396 1.15 nonaka
397 1.15 nonaka if (sc->sc_soft_ih != NULL) {
398 1.15 nonaka softint_disestablish(sc->sc_soft_ih);
399 1.15 nonaka sc->sc_soft_ih = NULL;
400 1.15 nonaka }
401 1.1 christos }
402 1.1 christos /* Free ROM copy. */
403 1.1 christos if (sc->sc_eep != NULL) {
404 1.1 christos free(sc->sc_eep, M_DEVBUF);
405 1.1 christos sc->sc_eep = NULL;
406 1.1 christos }
407 1.1 christos
408 1.1 christos bpf_detach(ifp);
409 1.1 christos ieee80211_ifdetach(&sc->sc_ic);
410 1.1 christos if_detach(ifp);
411 1.1 christos
412 1.1 christos callout_destroy(&sc->sc_scan_to);
413 1.1 christos callout_destroy(&sc->sc_calib_to);
414 1.17 msaitoh
415 1.17 msaitoh pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off,
416 1.17 msaitoh false);
417 1.1 christos }
418 1.1 christos
419 1.1 christos /*
420 1.1 christos * Attach the interface to 802.11 radiotap.
421 1.1 christos */
422 1.1 christos Static void
423 1.1 christos athn_radiotap_attach(struct athn_softc *sc)
424 1.1 christos {
425 1.1 christos
426 1.1 christos bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO,
427 1.1 christos sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
428 1.1 christos &sc->sc_drvbpf);
429 1.1 christos
430 1.1 christos sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
431 1.1 christos sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
432 1.1 christos sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT);
433 1.1 christos
434 1.1 christos sc->sc_txtap_len = sizeof(sc->sc_txtapu);
435 1.1 christos sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
436 1.1 christos sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT);
437 1.1 christos }
438 1.1 christos
439 1.1 christos Static void
440 1.1 christos athn_get_chanlist(struct athn_softc *sc)
441 1.1 christos {
442 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
443 1.1 christos uint8_t chan;
444 1.1 christos size_t i;
445 1.1 christos
446 1.1 christos if (sc->sc_flags & ATHN_FLAG_11G) {
447 1.1 christos for (i = 1; i <= 14; i++) {
448 1.1 christos chan = i;
449 1.1 christos ic->ic_channels[chan].ic_freq =
450 1.1 christos ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
451 1.1 christos ic->ic_channels[chan].ic_flags =
452 1.1 christos IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
453 1.1 christos IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
454 1.1 christos }
455 1.1 christos }
456 1.1 christos if (sc->sc_flags & ATHN_FLAG_11A) {
457 1.1 christos for (i = 0; i < __arraycount(athn_5ghz_chans); i++) {
458 1.1 christos chan = athn_5ghz_chans[i];
459 1.1 christos ic->ic_channels[chan].ic_freq =
460 1.1 christos ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
461 1.1 christos ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
462 1.1 christos }
463 1.1 christos }
464 1.1 christos }
465 1.1 christos
466 1.1 christos PUBLIC void
467 1.1 christos athn_rx_start(struct athn_softc *sc)
468 1.1 christos {
469 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
470 1.1 christos uint32_t rfilt;
471 1.1 christos
472 1.1 christos /* Setup Rx DMA descriptors. */
473 1.1 christos sc->sc_ops.rx_enable(sc);
474 1.1 christos
475 1.1 christos /* Set Rx filter. */
476 1.1 christos rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST;
477 1.1 christos #ifndef IEEE80211_NO_HT
478 1.1 christos /* Want Compressed Block Ack Requests. */
479 1.1 christos rfilt |= AR_RX_FILTER_COMPR_BAR;
480 1.1 christos #endif
481 1.1 christos rfilt |= AR_RX_FILTER_BEACON;
482 1.1 christos if (ic->ic_opmode != IEEE80211_M_STA) {
483 1.1 christos rfilt |= AR_RX_FILTER_PROBEREQ;
484 1.1 christos if (ic->ic_opmode == IEEE80211_M_MONITOR)
485 1.1 christos rfilt |= AR_RX_FILTER_PROM;
486 1.1 christos #ifndef IEEE80211_STA_ONLY
487 1.1 christos if (AR_SREV_9280_10_OR_LATER(sc) &&
488 1.1 christos ic->ic_opmode == IEEE80211_M_HOSTAP)
489 1.1 christos rfilt |= AR_RX_FILTER_PSPOLL;
490 1.1 christos #endif
491 1.1 christos }
492 1.1 christos athn_set_rxfilter(sc, rfilt);
493 1.1 christos
494 1.1 christos /* Set BSSID mask. */
495 1.1 christos AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
496 1.1 christos AR_WRITE(sc, AR_BSSMSKU, 0xffff);
497 1.1 christos
498 1.1 christos athn_set_opmode(sc);
499 1.1 christos
500 1.1 christos /* Set multicast filter. */
501 1.1 christos AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
502 1.1 christos AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
503 1.1 christos
504 1.1 christos AR_WRITE(sc, AR_FILT_OFDM, 0);
505 1.1 christos AR_WRITE(sc, AR_FILT_CCK, 0);
506 1.1 christos AR_WRITE(sc, AR_MIBC, 0);
507 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
508 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
509 1.1 christos
510 1.1 christos /* XXX ANI. */
511 1.1 christos AR_WRITE(sc, AR_PHY_ERR_1, 0);
512 1.1 christos AR_WRITE(sc, AR_PHY_ERR_2, 0);
513 1.1 christos
514 1.1 christos /* Disable HW crypto for now. */
515 1.1 christos AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS);
516 1.1 christos
517 1.1 christos /* Start PCU Rx. */
518 1.1 christos AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
519 1.1 christos AR_WRITE_BARRIER(sc);
520 1.1 christos }
521 1.1 christos
522 1.1 christos PUBLIC void
523 1.1 christos athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)
524 1.1 christos {
525 1.1 christos
526 1.1 christos AR_WRITE(sc, AR_RX_FILTER, rfilt);
527 1.1 christos #ifdef notyet
528 1.1 christos reg = AR_READ(sc, AR_PHY_ERR);
529 1.1 christos reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING |
530 1.1 christos AR_PHY_ERR_CCK_TIMING);
531 1.1 christos AR_WRITE(sc, AR_PHY_ERR, reg);
532 1.1 christos if (reg != 0)
533 1.1 christos AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
534 1.1 christos else
535 1.1 christos AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
536 1.1 christos #else
537 1.1 christos AR_WRITE(sc, AR_PHY_ERR, 0);
538 1.1 christos AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
539 1.1 christos #endif
540 1.1 christos AR_WRITE_BARRIER(sc);
541 1.1 christos }
542 1.1 christos
543 1.1 christos PUBLIC int
544 1.1 christos athn_intr(void *xsc)
545 1.1 christos {
546 1.1 christos struct athn_softc *sc = xsc;
547 1.1 christos struct ifnet *ifp = &sc->sc_if;
548 1.1 christos
549 1.1 christos if (!IS_UP_AND_RUNNING(ifp))
550 1.1 christos return 0;
551 1.1 christos
552 1.4 martin if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
553 1.4 martin /*
554 1.4 martin * The hardware is not ready/present, don't touch anything.
555 1.4 martin * Note this can happen early on if the IRQ is shared.
556 1.4 martin */
557 1.4 martin return 0;
558 1.4 martin
559 1.15 nonaka if (!sc->sc_ops.intr_status(sc))
560 1.15 nonaka return 0;
561 1.15 nonaka
562 1.16 jmcneill AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0);
563 1.16 jmcneill AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
564 1.16 jmcneill AR_WRITE_BARRIER(sc);
565 1.16 jmcneill
566 1.15 nonaka softint_schedule(sc->sc_soft_ih);
567 1.16 jmcneill
568 1.15 nonaka return 1;
569 1.15 nonaka }
570 1.15 nonaka
571 1.15 nonaka Static void
572 1.15 nonaka athn_softintr(void *xsc)
573 1.15 nonaka {
574 1.15 nonaka struct athn_softc *sc = xsc;
575 1.15 nonaka struct ifnet *ifp = &sc->sc_if;
576 1.15 nonaka
577 1.15 nonaka if (!IS_UP_AND_RUNNING(ifp))
578 1.15 nonaka return;
579 1.15 nonaka
580 1.15 nonaka if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
581 1.15 nonaka /*
582 1.15 nonaka * The hardware is not ready/present, don't touch anything.
583 1.15 nonaka * Note this can happen early on if the IRQ is shared.
584 1.15 nonaka */
585 1.15 nonaka return;
586 1.15 nonaka
587 1.15 nonaka sc->sc_ops.intr(sc);
588 1.16 jmcneill
589 1.16 jmcneill AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
590 1.16 jmcneill AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
591 1.16 jmcneill AR_WRITE_BARRIER(sc);
592 1.1 christos }
593 1.1 christos
594 1.1 christos Static void
595 1.1 christos athn_get_chipid(struct athn_softc *sc)
596 1.1 christos {
597 1.1 christos uint32_t reg;
598 1.1 christos
599 1.1 christos reg = AR_READ(sc, AR_SREV);
600 1.1 christos if (MS(reg, AR_SREV_ID) == 0xff) {
601 1.1 christos sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2);
602 1.1 christos sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2);
603 1.1 christos if (!(reg & AR_SREV_TYPE2_HOST_MODE))
604 1.1 christos sc->sc_flags |= ATHN_FLAG_PCIE;
605 1.19 msaitoh } else {
606 1.1 christos sc->sc_mac_ver = MS(reg, AR_SREV_VERSION);
607 1.1 christos sc->sc_mac_rev = MS(reg, AR_SREV_REVISION);
608 1.1 christos if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE)
609 1.1 christos sc->sc_flags |= ATHN_FLAG_PCIE;
610 1.1 christos }
611 1.1 christos }
612 1.1 christos
613 1.1 christos Static const char *
614 1.1 christos athn_get_mac_name(struct athn_softc *sc)
615 1.1 christos {
616 1.1 christos
617 1.1 christos switch (sc->sc_mac_ver) {
618 1.1 christos case AR_SREV_VERSION_5416_PCI:
619 1.1 christos return "AR5416";
620 1.1 christos case AR_SREV_VERSION_5416_PCIE:
621 1.1 christos return "AR5418";
622 1.1 christos case AR_SREV_VERSION_9160:
623 1.1 christos return "AR9160";
624 1.1 christos case AR_SREV_VERSION_9280:
625 1.1 christos return "AR9280";
626 1.1 christos case AR_SREV_VERSION_9285:
627 1.1 christos return "AR9285";
628 1.1 christos case AR_SREV_VERSION_9271:
629 1.1 christos return "AR9271";
630 1.1 christos case AR_SREV_VERSION_9287:
631 1.1 christos return "AR9287";
632 1.1 christos case AR_SREV_VERSION_9380:
633 1.1 christos return "AR9380";
634 1.1 christos case AR_SREV_VERSION_9485:
635 1.1 christos return "AR9485";
636 1.1 christos default:
637 1.1 christos return "unknown";
638 1.1 christos }
639 1.1 christos }
640 1.1 christos
641 1.1 christos /*
642 1.1 christos * Return RF chip name (not for single-chip solutions).
643 1.1 christos */
644 1.1 christos Static const char *
645 1.1 christos athn_get_rf_name(struct athn_softc *sc)
646 1.1 christos {
647 1.1 christos
648 1.1 christos KASSERT(!AR_SINGLE_CHIP(sc));
649 1.1 christos
650 1.1 christos switch (sc->sc_rf_rev) {
651 1.1 christos case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */
652 1.1 christos return "AR5133";
653 1.1 christos case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */
654 1.1 christos return "AR2133";
655 1.1 christos case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */
656 1.1 christos return "AR5122";
657 1.1 christos case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */
658 1.1 christos return "AR2122";
659 1.1 christos default:
660 1.1 christos return "unknown";
661 1.1 christos }
662 1.1 christos }
663 1.1 christos
664 1.1 christos PUBLIC int
665 1.1 christos athn_reset_power_on(struct athn_softc *sc)
666 1.1 christos {
667 1.1 christos int ntries;
668 1.1 christos
669 1.1 christos /* Set force wake. */
670 1.1 christos AR_WRITE(sc, AR_RTC_FORCE_WAKE,
671 1.1 christos AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
672 1.1 christos
673 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc)) {
674 1.1 christos /* Make sure no DMA is active by doing an AHB reset. */
675 1.1 christos AR_WRITE(sc, AR_RC, AR_RC_AHB);
676 1.1 christos }
677 1.1 christos /* RTC reset and clear. */
678 1.1 christos AR_WRITE(sc, AR_RTC_RESET, 0);
679 1.1 christos AR_WRITE_BARRIER(sc);
680 1.1 christos DELAY(2);
681 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc))
682 1.1 christos AR_WRITE(sc, AR_RC, 0);
683 1.1 christos AR_WRITE(sc, AR_RTC_RESET, 1);
684 1.1 christos
685 1.1 christos /* Poll until RTC is ON. */
686 1.1 christos for (ntries = 0; ntries < 1000; ntries++) {
687 1.1 christos if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
688 1.1 christos AR_RTC_STATUS_ON)
689 1.1 christos break;
690 1.1 christos DELAY(10);
691 1.1 christos }
692 1.1 christos if (ntries == 1000) {
693 1.1 christos DPRINTFN(DBG_INIT, sc, "RTC not waking up\n");
694 1.1 christos return ETIMEDOUT;
695 1.1 christos }
696 1.1 christos return athn_reset(sc, 0);
697 1.1 christos }
698 1.1 christos
699 1.1 christos PUBLIC int
700 1.1 christos athn_reset(struct athn_softc *sc, int cold_reset)
701 1.1 christos {
702 1.1 christos int ntries;
703 1.1 christos
704 1.1 christos /* Set force wake. */
705 1.1 christos AR_WRITE(sc, AR_RTC_FORCE_WAKE,
706 1.1 christos AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
707 1.1 christos
708 1.1 christos if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
709 1.1 christos (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
710 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
711 1.1 christos AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
712 1.1 christos (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0));
713 1.19 msaitoh } else if (!AR_SREV_9380_10_OR_LATER(sc))
714 1.1 christos AR_WRITE(sc, AR_RC, AR_RC_AHB);
715 1.1 christos
716 1.1 christos AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
717 1.1 christos (cold_reset ? AR_RTC_RC_MAC_COLD : 0));
718 1.1 christos AR_WRITE_BARRIER(sc);
719 1.1 christos DELAY(50);
720 1.1 christos AR_WRITE(sc, AR_RTC_RC, 0);
721 1.1 christos for (ntries = 0; ntries < 1000; ntries++) {
722 1.1 christos if (!(AR_READ(sc, AR_RTC_RC) &
723 1.1 christos (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD)))
724 1.1 christos break;
725 1.1 christos DELAY(10);
726 1.1 christos }
727 1.1 christos if (ntries == 1000) {
728 1.1 christos DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n");
729 1.1 christos return ETIMEDOUT;
730 1.1 christos }
731 1.1 christos AR_WRITE(sc, AR_RC, 0);
732 1.1 christos AR_WRITE_BARRIER(sc);
733 1.1 christos return 0;
734 1.1 christos }
735 1.1 christos
736 1.1 christos PUBLIC int
737 1.1 christos athn_set_power_awake(struct athn_softc *sc)
738 1.1 christos {
739 1.1 christos int ntries, error;
740 1.1 christos
741 1.1 christos /* Do a Power-On-Reset if shutdown. */
742 1.1 christos if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
743 1.1 christos AR_RTC_STATUS_SHUTDOWN) {
744 1.1 christos if ((error = athn_reset_power_on(sc)) != 0)
745 1.1 christos return error;
746 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc))
747 1.1 christos athn_init_pll(sc, NULL);
748 1.1 christos }
749 1.1 christos AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
750 1.1 christos AR_WRITE_BARRIER(sc);
751 1.1 christos DELAY(50); /* Give chip the chance to awake. */
752 1.1 christos
753 1.1 christos /* Poll until RTC is ON. */
754 1.1 christos for (ntries = 0; ntries < 4000; ntries++) {
755 1.1 christos if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
756 1.1 christos AR_RTC_STATUS_ON)
757 1.1 christos break;
758 1.1 christos DELAY(50);
759 1.1 christos AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
760 1.1 christos }
761 1.1 christos if (ntries == 4000) {
762 1.1 christos DPRINTFN(DBG_INIT, sc, "RTC not waking up\n");
763 1.1 christos return ETIMEDOUT;
764 1.1 christos }
765 1.1 christos
766 1.1 christos AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
767 1.1 christos AR_WRITE_BARRIER(sc);
768 1.1 christos return 0;
769 1.1 christos }
770 1.1 christos
771 1.1 christos PUBLIC void
772 1.1 christos athn_set_power_sleep(struct athn_softc *sc)
773 1.1 christos {
774 1.1 christos
775 1.1 christos AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
776 1.1 christos /* Allow the MAC to go to sleep. */
777 1.1 christos AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
778 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc))
779 1.1 christos AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
780 1.1 christos /*
781 1.1 christos * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
782 1.1 christos * results in high power consumption on AR5416 chipsets.
783 1.1 christos */
784 1.1 christos if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc))
785 1.1 christos AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN);
786 1.1 christos AR_WRITE_BARRIER(sc);
787 1.1 christos }
788 1.1 christos
789 1.1 christos PUBLIC void
790 1.1 christos athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
791 1.1 christos {
792 1.1 christos uint32_t pll;
793 1.1 christos
794 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc)) {
795 1.1 christos if (AR_SREV_9485(sc))
796 1.1 christos AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
797 1.1 christos pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
798 1.1 christos pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
799 1.19 msaitoh } else if (AR_SREV_9280_10_OR_LATER(sc)) {
800 1.1 christos pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
801 1.1 christos if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) {
802 1.1 christos if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)
803 1.1 christos pll = 0x142c;
804 1.1 christos else if (AR_SREV_9280_20(sc))
805 1.1 christos pll = 0x2850;
806 1.1 christos else
807 1.1 christos pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);
808 1.19 msaitoh } else
809 1.1 christos pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
810 1.19 msaitoh } else if (AR_SREV_9160_10_OR_LATER(sc)) {
811 1.1 christos pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
812 1.1 christos if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
813 1.1 christos pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);
814 1.1 christos else
815 1.1 christos pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);
816 1.19 msaitoh } else {
817 1.1 christos pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
818 1.1 christos if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
819 1.1 christos pll |= SM(AR_RTC_PLL_DIV, 0x0a);
820 1.1 christos else
821 1.1 christos pll |= SM(AR_RTC_PLL_DIV, 0x0b);
822 1.1 christos }
823 1.1 christos DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll);
824 1.1 christos AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
825 1.1 christos if (AR_SREV_9271(sc)) {
826 1.1 christos /* Switch core clock to 117MHz. */
827 1.1 christos AR_WRITE_BARRIER(sc);
828 1.1 christos DELAY(500);
829 1.1 christos AR_WRITE(sc, 0x50050, 0x304);
830 1.1 christos }
831 1.1 christos AR_WRITE_BARRIER(sc);
832 1.1 christos DELAY(100);
833 1.1 christos AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
834 1.1 christos AR_WRITE_BARRIER(sc);
835 1.1 christos }
836 1.1 christos
837 1.1 christos Static void
838 1.1 christos athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes)
839 1.1 christos {
840 1.1 christos int i;
841 1.1 christos
842 1.1 christos /* Write sequence to Serializer/Deserializer. */
843 1.1 christos for (i = 0; i < serdes->nvals; i++)
844 1.1 christos AR_WRITE(sc, serdes->regs[i], serdes->vals[i]);
845 1.1 christos AR_WRITE_BARRIER(sc);
846 1.1 christos }
847 1.1 christos
848 1.1 christos PUBLIC void
849 1.1 christos athn_config_pcie(struct athn_softc *sc)
850 1.1 christos {
851 1.1 christos
852 1.1 christos /* Disable PLL when in L0s as well as receiver clock when in L1. */
853 1.1 christos athn_write_serdes(sc, sc->sc_serdes);
854 1.1 christos
855 1.1 christos DELAY(1000);
856 1.1 christos /* Allow forcing of PCIe core into L1 state. */
857 1.1 christos AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
858 1.1 christos
859 1.1 christos #ifndef ATHN_PCIE_WAEN
860 1.1 christos AR_WRITE(sc, AR_WA, sc->sc_workaround);
861 1.1 christos #else
862 1.1 christos AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
863 1.1 christos #endif
864 1.1 christos AR_WRITE_BARRIER(sc);
865 1.1 christos }
866 1.1 christos
867 1.1 christos /*
868 1.1 christos * Serializer/Deserializer programming for non-PCIe devices.
869 1.1 christos */
870 1.1 christos static const uint32_t ar_nonpcie_serdes_regs[] = {
871 1.1 christos AR_PCIE_SERDES,
872 1.1 christos AR_PCIE_SERDES,
873 1.1 christos AR_PCIE_SERDES,
874 1.1 christos AR_PCIE_SERDES,
875 1.1 christos AR_PCIE_SERDES,
876 1.1 christos AR_PCIE_SERDES,
877 1.1 christos AR_PCIE_SERDES,
878 1.1 christos AR_PCIE_SERDES,
879 1.1 christos AR_PCIE_SERDES,
880 1.1 christos AR_PCIE_SERDES2,
881 1.1 christos };
882 1.1 christos
883 1.1 christos static const uint32_t ar_nonpcie_serdes_vals[] = {
884 1.1 christos 0x9248fc00,
885 1.1 christos 0x24924924,
886 1.1 christos 0x28000029,
887 1.1 christos 0x57160824,
888 1.1 christos 0x25980579,
889 1.1 christos 0x00000000,
890 1.1 christos 0x1aaabe40,
891 1.1 christos 0xbe105554,
892 1.1 christos 0x000e1007,
893 1.1 christos 0x00000000
894 1.1 christos };
895 1.1 christos
896 1.1 christos static const struct athn_serdes ar_nonpcie_serdes = {
897 1.1 christos __arraycount(ar_nonpcie_serdes_vals),
898 1.1 christos ar_nonpcie_serdes_regs,
899 1.1 christos ar_nonpcie_serdes_vals
900 1.1 christos };
901 1.1 christos
902 1.1 christos PUBLIC void
903 1.1 christos athn_config_nonpcie(struct athn_softc *sc)
904 1.1 christos {
905 1.1 christos
906 1.1 christos athn_write_serdes(sc, &ar_nonpcie_serdes);
907 1.1 christos }
908 1.1 christos
909 1.1 christos PUBLIC int
910 1.1 christos athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan,
911 1.1 christos struct ieee80211_channel *extchan)
912 1.1 christos {
913 1.1 christos struct athn_ops *ops = &sc->sc_ops;
914 1.1 christos int error, qid;
915 1.1 christos
916 1.1 christos /* Check that Tx is stopped, otherwise RF Bus grant will not work. */
917 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
918 1.1 christos if (athn_tx_pending(sc, qid))
919 1.1 christos return EBUSY;
920 1.1 christos
921 1.1 christos /* Request RF Bus grant. */
922 1.1 christos if ((error = ops->rf_bus_request(sc)) != 0)
923 1.1 christos return error;
924 1.1 christos
925 1.1 christos ops->set_phy(sc, curchan, extchan);
926 1.1 christos
927 1.1 christos /* Change the synthesizer. */
928 1.1 christos if ((error = ops->set_synth(sc, curchan, extchan)) != 0)
929 1.1 christos return error;
930 1.1 christos
931 1.1 christos sc->sc_curchan = curchan;
932 1.1 christos sc->sc_curchanext = extchan;
933 1.1 christos
934 1.1 christos /* Set transmit power values for new channel. */
935 1.1 christos ops->set_txpower(sc, curchan, extchan);
936 1.1 christos
937 1.1 christos /* Release the RF Bus grant. */
938 1.1 christos ops->rf_bus_release(sc);
939 1.1 christos
940 1.1 christos /* Write delta slope coeffs for modes where OFDM may be used. */
941 1.1 christos if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B)
942 1.1 christos ops->set_delta_slope(sc, curchan, extchan);
943 1.1 christos
944 1.1 christos ops->spur_mitigate(sc, curchan, extchan);
945 1.1 christos /* XXX Load noisefloor values and start calibration. */
946 1.1 christos
947 1.1 christos return 0;
948 1.1 christos }
949 1.1 christos
950 1.1 christos Static int
951 1.1 christos athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan,
952 1.1 christos struct ieee80211_channel *extchan)
953 1.1 christos {
954 1.1 christos int error, qid;
955 1.1 christos
956 1.1 christos /* Disable interrupts. */
957 1.1 christos athn_disable_interrupts(sc);
958 1.1 christos
959 1.1 christos /* Stop all Tx queues. */
960 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
961 1.1 christos athn_stop_tx_dma(sc, qid);
962 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
963 1.1 christos athn_tx_reclaim(sc, qid);
964 1.1 christos
965 1.1 christos /* Stop Rx. */
966 1.1 christos AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
967 1.1 christos AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
968 1.1 christos AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
969 1.1 christos AR_WRITE(sc, AR_FILT_OFDM, 0);
970 1.1 christos AR_WRITE(sc, AR_FILT_CCK, 0);
971 1.1 christos athn_set_rxfilter(sc, 0);
972 1.1 christos error = athn_stop_rx_dma(sc);
973 1.1 christos if (error != 0)
974 1.1 christos goto reset;
975 1.1 christos
976 1.1 christos #ifdef notyet
977 1.1 christos /* AR9280 needs a full reset. */
978 1.1 christos if (AR_SREV_9280(sc))
979 1.1 christos #endif
980 1.1 christos goto reset;
981 1.1 christos
982 1.1 christos /* If band or bandwidth changes, we need to do a full reset. */
983 1.1 christos if (curchan->ic_flags != sc->sc_curchan->ic_flags ||
984 1.1 christos ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) {
985 1.1 christos DPRINTFN(DBG_RF, sc, "channel band switch\n");
986 1.1 christos goto reset;
987 1.1 christos }
988 1.1 christos error = athn_set_power_awake(sc);
989 1.1 christos if (error != 0)
990 1.1 christos goto reset;
991 1.1 christos
992 1.1 christos error = athn_set_chan(sc, curchan, extchan);
993 1.1 christos if (error != 0) {
994 1.1 christos reset: /* Error found, try a full reset. */
995 1.1 christos DPRINTFN(DBG_RF, sc, "needs a full reset\n");
996 1.1 christos error = athn_hw_reset(sc, curchan, extchan, 0);
997 1.1 christos if (error != 0) /* Hopeless case. */
998 1.1 christos return error;
999 1.1 christos }
1000 1.1 christos athn_rx_start(sc);
1001 1.1 christos
1002 1.1 christos /* Re-enable interrupts. */
1003 1.1 christos athn_enable_interrupts(sc);
1004 1.1 christos return 0;
1005 1.1 christos }
1006 1.1 christos
1007 1.1 christos PUBLIC void
1008 1.1 christos athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)
1009 1.1 christos {
1010 1.1 christos #define COEFF_SCALE_SHIFT 24
1011 1.1 christos uint32_t exp, man;
1012 1.1 christos
1013 1.1 christos /* exponent = 14 - floor(log2(coeff)) */
1014 1.1 christos for (exp = 31; exp > 0; exp--)
1015 1.22 msaitoh if (coeff & (1U << exp))
1016 1.1 christos break;
1017 1.1 christos exp = 14 - (exp - COEFF_SCALE_SHIFT);
1018 1.1 christos
1019 1.1 christos /* mantissa = floor(coeff * 2^exponent + 0.5) */
1020 1.1 christos man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1));
1021 1.1 christos
1022 1.1 christos *mantissa = man >> (COEFF_SCALE_SHIFT - exp);
1023 1.1 christos *exponent = exp - 16;
1024 1.1 christos #undef COEFF_SCALE_SHIFT
1025 1.1 christos }
1026 1.1 christos
1027 1.1 christos PUBLIC void
1028 1.1 christos athn_reset_key(struct athn_softc *sc, int entry)
1029 1.1 christos {
1030 1.1 christos
1031 1.1 christos /*
1032 1.1 christos * NB: Key cache registers access special memory area that requires
1033 1.1 christos * two 32-bit writes to actually update the values in the internal
1034 1.1 christos * memory. Consequently, writes must be grouped by pair.
1035 1.1 christos */
1036 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0);
1037 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0);
1038 1.1 christos
1039 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0);
1040 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0);
1041 1.1 christos
1042 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0);
1043 1.1 christos AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1044 1.1 christos
1045 1.1 christos AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
1046 1.1 christos AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
1047 1.1 christos
1048 1.1 christos AR_WRITE_BARRIER(sc);
1049 1.1 christos }
1050 1.1 christos
1051 1.1 christos #ifdef notyet
1052 1.1 christos Static int
1053 1.1 christos athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1054 1.1 christos struct ieee80211_key *k)
1055 1.1 christos {
1056 1.1 christos struct athn_softc *sc = ic->ic_ifp->if_softc;
1057 1.1 christos const uint8_t *txmic, *rxmic, *key, *addr;
1058 1.1 christos uintptr_t entry, micentry;
1059 1.1 christos uint32_t type, lo, hi;
1060 1.1 christos
1061 1.1 christos switch (k->k_cipher) {
1062 1.1 christos case IEEE80211_CIPHER_WEP40:
1063 1.1 christos type = AR_KEYTABLE_TYPE_40;
1064 1.1 christos break;
1065 1.1 christos case IEEE80211_CIPHER_WEP104:
1066 1.1 christos type = AR_KEYTABLE_TYPE_104;
1067 1.1 christos break;
1068 1.1 christos case IEEE80211_CIPHER_TKIP:
1069 1.1 christos type = AR_KEYTABLE_TYPE_TKIP;
1070 1.1 christos break;
1071 1.1 christos case IEEE80211_CIPHER_CCMP:
1072 1.1 christos type = AR_KEYTABLE_TYPE_CCM;
1073 1.1 christos break;
1074 1.1 christos default:
1075 1.1 christos /* Fallback to software crypto for other ciphers. */
1076 1.1 christos return ieee80211_set_key(ic, ni, k);
1077 1.1 christos }
1078 1.1 christos
1079 1.1 christos if (!(k->k_flags & IEEE80211_KEY_GROUP))
1080 1.1 christos entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd);
1081 1.1 christos else
1082 1.1 christos entry = k->k_id;
1083 1.1 christos k->k_priv = (void *)entry;
1084 1.1 christos
1085 1.1 christos /* NB: See note about key cache registers access above. */
1086 1.1 christos key = k->k_key;
1087 1.1 christos if (type == AR_KEYTABLE_TYPE_TKIP) {
1088 1.1 christos #ifndef IEEE80211_STA_ONLY
1089 1.1 christos if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1090 1.1 christos txmic = &key[16];
1091 1.1 christos rxmic = &key[24];
1092 1.19 msaitoh } else
1093 1.1 christos #endif
1094 1.1 christos {
1095 1.1 christos rxmic = &key[16];
1096 1.1 christos txmic = &key[24];
1097 1.1 christos }
1098 1.1 christos /* Tx+Rx MIC key is at entry + 64. */
1099 1.1 christos micentry = entry + 64;
1100 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0]));
1101 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2]));
1102 1.1 christos
1103 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4]));
1104 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0]));
1105 1.1 christos
1106 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4]));
1107 1.1 christos AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR);
1108 1.1 christos }
1109 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]));
1110 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]));
1111 1.1 christos
1112 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]));
1113 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]));
1114 1.1 christos
1115 1.1 christos AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]));
1116 1.1 christos AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type);
1117 1.1 christos
1118 1.1 christos if (!(k->k_flags & IEEE80211_KEY_GROUP)) {
1119 1.1 christos addr = ni->ni_macaddr;
1120 1.1 christos lo = LE_READ_4(&addr[0]);
1121 1.1 christos hi = LE_READ_2(&addr[4]);
1122 1.1 christos lo = lo >> 1 | hi << 31;
1123 1.1 christos hi = hi >> 1;
1124 1.19 msaitoh } else
1125 1.1 christos lo = hi = 0;
1126 1.1 christos AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
1127 1.1 christos AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID);
1128 1.1 christos AR_WRITE_BARRIER(sc);
1129 1.1 christos return 0;
1130 1.1 christos }
1131 1.1 christos
1132 1.1 christos Static void
1133 1.1 christos athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1134 1.1 christos struct ieee80211_key *k)
1135 1.1 christos {
1136 1.1 christos struct athn_softc *sc = ic->ic_ifp->if_softc;
1137 1.1 christos uintptr_t entry;
1138 1.1 christos
1139 1.1 christos switch (k->k_cipher) {
1140 1.1 christos case IEEE80211_CIPHER_WEP40:
1141 1.1 christos case IEEE80211_CIPHER_WEP104:
1142 1.1 christos case IEEE80211_CIPHER_CCMP:
1143 1.1 christos entry = (uintptr_t)k->k_priv;
1144 1.1 christos athn_reset_key(sc, entry);
1145 1.1 christos break;
1146 1.1 christos case IEEE80211_CIPHER_TKIP:
1147 1.1 christos entry = (uintptr_t)k->k_priv;
1148 1.1 christos athn_reset_key(sc, entry);
1149 1.1 christos athn_reset_key(sc, entry + 64);
1150 1.1 christos break;
1151 1.1 christos default:
1152 1.1 christos /* Fallback to software crypto for other ciphers. */
1153 1.1 christos ieee80211_delete_key(ic, ni, k);
1154 1.1 christos }
1155 1.1 christos }
1156 1.1 christos #endif /* notyet */
1157 1.1 christos
1158 1.1 christos PUBLIC void
1159 1.1 christos athn_led_init(struct athn_softc *sc)
1160 1.1 christos {
1161 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1162 1.1 christos
1163 1.1 christos ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1164 1.1 christos /* LED off, active low. */
1165 1.1 christos athn_set_led(sc, 0);
1166 1.1 christos }
1167 1.1 christos
1168 1.1 christos PUBLIC void
1169 1.1 christos athn_set_led(struct athn_softc *sc, int on)
1170 1.1 christos {
1171 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1172 1.1 christos
1173 1.1 christos sc->sc_led_state = on;
1174 1.1 christos ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state);
1175 1.1 christos }
1176 1.1 christos
1177 1.1 christos #ifdef ATHN_BT_COEXISTENCE
1178 1.1 christos Static void
1179 1.1 christos athn_btcoex_init(struct athn_softc *sc)
1180 1.1 christos {
1181 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1182 1.1 christos uint32_t reg;
1183 1.1 christos
1184 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) {
1185 1.1 christos /* Connect bt_active to baseband. */
1186 1.1 christos AR_CLRBITS(sc, sc->sc_gpio_input_en_off,
1187 1.1 christos AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
1188 1.1 christos AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF);
1189 1.1 christos AR_SETBITS(sc, sc->sc_gpio_input_en_off,
1190 1.1 christos AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1191 1.1 christos
1192 1.1 christos reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
1193 1.1 christos reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
1194 1.1 christos AR_GPIO_BTACTIVE_PIN);
1195 1.1 christos AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1196 1.1 christos AR_WRITE_BARRIER(sc);
1197 1.1 christos
1198 1.1 christos ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
1199 1.19 msaitoh } else { /* 3-wire. */
1200 1.1 christos AR_SETBITS(sc, sc->sc_gpio_input_en_off,
1201 1.1 christos AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
1202 1.1 christos AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1203 1.1 christos
1204 1.1 christos reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
1205 1.1 christos reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
1206 1.1 christos AR_GPIO_BTACTIVE_PIN);
1207 1.1 christos reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
1208 1.1 christos AR_GPIO_BTPRIORITY_PIN);
1209 1.1 christos AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1210 1.1 christos AR_WRITE_BARRIER(sc);
1211 1.1 christos
1212 1.1 christos ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
1213 1.1 christos ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
1214 1.1 christos }
1215 1.1 christos }
1216 1.1 christos
1217 1.1 christos Static void
1218 1.1 christos athn_btcoex_enable(struct athn_softc *sc)
1219 1.1 christos {
1220 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1221 1.1 christos uint32_t reg;
1222 1.1 christos
1223 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) {
1224 1.1 christos AR_WRITE(sc, AR_BT_COEX_MODE,
1225 1.1 christos SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |
1226 1.1 christos SM(AR_BT_PRIORITY_TIME, 2) |
1227 1.1 christos SM(AR_BT_FIRST_SLOT_TIME, 5) |
1228 1.1 christos SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |
1229 1.1 christos AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND |
1230 1.1 christos AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY);
1231 1.1 christos AR_WRITE(sc, AR_BT_COEX_WEIGHT,
1232 1.1 christos SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |
1233 1.1 christos SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT));
1234 1.1 christos AR_WRITE(sc, AR_BT_COEX_MODE2,
1235 1.1 christos SM(AR_BT_BCN_MISS_THRESH, 50) |
1236 1.1 christos AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT);
1237 1.1 christos
1238 1.1 christos AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
1239 1.1 christos AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX);
1240 1.1 christos AR_WRITE_BARRIER(sc);
1241 1.1 christos
1242 1.1 christos ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1243 1.1 christos AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
1244 1.1 christos
1245 1.19 msaitoh } else { /* 2-wire. */
1246 1.1 christos ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1247 1.1 christos AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
1248 1.1 christos }
1249 1.1 christos reg = AR_READ(sc, AR_GPIO_PDPU);
1250 1.1 christos reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));
1251 1.1 christos reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);
1252 1.1 christos AR_WRITE(sc, AR_GPIO_PDPU, reg);
1253 1.1 christos AR_WRITE_BARRIER(sc);
1254 1.1 christos
1255 1.1 christos /* Disable PCIe Active State Power Management (ASPM). */
1256 1.1 christos if (sc->sc_disable_aspm != NULL)
1257 1.1 christos sc->sc_disable_aspm(sc);
1258 1.1 christos
1259 1.1 christos /* XXX Start periodic timer. */
1260 1.1 christos }
1261 1.1 christos
1262 1.1 christos Static void
1263 1.1 christos athn_btcoex_disable(struct athn_softc *sc)
1264 1.1 christos {
1265 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1266 1.1 christos
1267 1.1 christos ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0);
1268 1.1 christos
1269 1.1 christos ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1270 1.1 christos AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1271 1.1 christos
1272 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) {
1273 1.1 christos AR_WRITE(sc, AR_BT_COEX_MODE,
1274 1.1 christos SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET);
1275 1.1 christos AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0);
1276 1.1 christos AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
1277 1.1 christos /* XXX Stop periodic timer. */
1278 1.1 christos }
1279 1.1 christos AR_WRITE_BARRIER(sc);
1280 1.1 christos /* XXX Restore ASPM setting? */
1281 1.1 christos }
1282 1.1 christos #endif
1283 1.1 christos
1284 1.1 christos Static void
1285 1.1 christos athn_iter_func(void *arg, struct ieee80211_node *ni)
1286 1.1 christos {
1287 1.1 christos struct athn_softc *sc = arg;
1288 1.1 christos struct athn_node *an = (struct athn_node *)ni;
1289 1.1 christos
1290 1.1 christos ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn);
1291 1.1 christos }
1292 1.1 christos
1293 1.1 christos Static void
1294 1.1 christos athn_calib_to(void *arg)
1295 1.1 christos {
1296 1.1 christos struct athn_softc *sc = arg;
1297 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1298 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
1299 1.1 christos int s;
1300 1.1 christos
1301 1.1 christos s = splnet();
1302 1.1 christos
1303 1.1 christos /* Do periodic (every 4 minutes) PA calibration. */
1304 1.1 christos if (AR_SREV_9285_11_OR_LATER(sc) &&
1305 1.1 christos !AR_SREV_9380_10_OR_LATER(sc) &&
1306 1.10 riz (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) {
1307 1.1 christos sc->sc_pa_calib_ticks = ticks;
1308 1.1 christos if (AR_SREV_9271(sc))
1309 1.1 christos ar9271_pa_calib(sc);
1310 1.1 christos else
1311 1.1 christos ar9285_pa_calib(sc);
1312 1.1 christos }
1313 1.1 christos
1314 1.1 christos /* Do periodic (every 30 seconds) temperature compensation. */
1315 1.1 christos if ((sc->sc_flags & ATHN_FLAG_OLPC) &&
1316 1.1 christos ticks >= sc->sc_olpc_ticks + 30 * hz) {
1317 1.1 christos sc->sc_olpc_ticks = ticks;
1318 1.1 christos ops->olpc_temp_compensation(sc);
1319 1.1 christos }
1320 1.1 christos
1321 1.1 christos #ifdef notyet
1322 1.1 christos /* XXX ANI. */
1323 1.1 christos athn_ani_monitor(sc);
1324 1.1 christos
1325 1.1 christos ops->next_calib(sc);
1326 1.1 christos #endif
1327 1.1 christos if (ic->ic_fixed_rate == -1) {
1328 1.1 christos if (ic->ic_opmode == IEEE80211_M_STA)
1329 1.1 christos athn_iter_func(sc, ic->ic_bss);
1330 1.1 christos else
1331 1.1 christos ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc);
1332 1.1 christos }
1333 1.1 christos callout_schedule(&sc->sc_calib_to, hz / 2);
1334 1.1 christos splx(s);
1335 1.1 christos }
1336 1.1 christos
1337 1.1 christos Static int
1338 1.1 christos athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan,
1339 1.1 christos struct ieee80211_channel *extchan)
1340 1.1 christos {
1341 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1342 1.1 christos int error;
1343 1.1 christos
1344 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc))
1345 1.1 christos error = ar9003_init_calib(sc);
1346 1.1 christos else if (AR_SREV_9285_10_OR_LATER(sc))
1347 1.1 christos error = ar9285_init_calib(sc, curchan, extchan);
1348 1.1 christos else
1349 1.1 christos error = ar5416_init_calib(sc, curchan, extchan);
1350 1.1 christos if (error != 0)
1351 1.1 christos return error;
1352 1.1 christos
1353 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc)) {
1354 1.1 christos /* Do PA calibration. */
1355 1.1 christos if (AR_SREV_9285_11_OR_LATER(sc)) {
1356 1.1 christos sc->sc_pa_calib_ticks = ticks;
1357 1.1 christos if (AR_SREV_9271(sc))
1358 1.1 christos ar9271_pa_calib(sc);
1359 1.1 christos else
1360 1.1 christos ar9285_pa_calib(sc);
1361 1.1 christos }
1362 1.1 christos /* Do noisefloor calibration. */
1363 1.1 christos ops->noisefloor_calib(sc);
1364 1.1 christos }
1365 1.1 christos if (AR_SREV_9160_10_OR_LATER(sc)) {
1366 1.1 christos /* Support IQ calibration. */
1367 1.1 christos sc->sc_sup_calib_mask = ATHN_CAL_IQ;
1368 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc)) {
1369 1.1 christos /* Support temperature compensation calibration. */
1370 1.1 christos sc->sc_sup_calib_mask |= ATHN_CAL_TEMP;
1371 1.19 msaitoh } else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) {
1372 1.1 christos /*
1373 1.1 christos * ADC gain calibration causes uplink throughput
1374 1.1 christos * drops in HT40 mode on AR9287.
1375 1.1 christos */
1376 1.1 christos if (!AR_SREV_9287(sc)) {
1377 1.1 christos /* Support ADC gain calibration. */
1378 1.1 christos sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN;
1379 1.1 christos }
1380 1.1 christos /* Support ADC DC offset calibration. */
1381 1.1 christos sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC;
1382 1.1 christos }
1383 1.1 christos }
1384 1.1 christos return 0;
1385 1.1 christos }
1386 1.1 christos
1387 1.1 christos /*
1388 1.1 christos * Adaptive noise immunity.
1389 1.1 christos */
1390 1.1 christos #ifdef notyet
1391 1.1 christos Static int32_t
1392 1.1 christos athn_ani_get_rssi(struct athn_softc *sc)
1393 1.1 christos {
1394 1.1 christos
1395 1.1 christos return 0; /* XXX */
1396 1.1 christos }
1397 1.1 christos #endif /* notyet */
1398 1.1 christos
1399 1.1 christos #ifdef notyet
1400 1.1 christos Static void
1401 1.1 christos athn_ani_ofdm_err_trigger(struct athn_softc *sc)
1402 1.1 christos {
1403 1.1 christos struct athn_ani *ani = &sc->sc_ani;
1404 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1405 1.1 christos int32_t rssi;
1406 1.1 christos
1407 1.1 christos /* First, raise noise immunity level, up to max. */
1408 1.1 christos if (ani->noise_immunity_level < 4) {
1409 1.1 christos ani->noise_immunity_level++;
1410 1.1 christos ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1411 1.1 christos return;
1412 1.1 christos }
1413 1.1 christos
1414 1.1 christos /* Then, raise our spur immunity level, up to max. */
1415 1.1 christos if (ani->spur_immunity_level < 7) {
1416 1.1 christos ani->spur_immunity_level++;
1417 1.1 christos ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
1418 1.1 christos return;
1419 1.1 christos }
1420 1.1 christos
1421 1.1 christos #ifndef IEEE80211_STA_ONLY
1422 1.1 christos if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1423 1.1 christos if (ani->firstep_level < 2) {
1424 1.1 christos ani->firstep_level++;
1425 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1426 1.1 christos }
1427 1.1 christos return;
1428 1.1 christos }
1429 1.1 christos #endif
1430 1.1 christos rssi = athn_ani_get_rssi(sc);
1431 1.1 christos if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
1432 1.1 christos /*
1433 1.1 christos * Beacon RSSI is high, turn off OFDM weak signal detection
1434 1.1 christos * or raise first step level as last resort.
1435 1.1 christos */
1436 1.1 christos if (ani->ofdm_weak_signal) {
1437 1.1 christos ani->ofdm_weak_signal = 0;
1438 1.1 christos ops->disable_ofdm_weak_signal(sc);
1439 1.1 christos ani->spur_immunity_level = 0;
1440 1.1 christos ops->set_spur_immunity_level(sc, 0);
1441 1.19 msaitoh } else if (ani->firstep_level < 2) {
1442 1.1 christos ani->firstep_level++;
1443 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1444 1.1 christos }
1445 1.19 msaitoh } else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1446 1.1 christos /*
1447 1.1 christos * Beacon RSSI is in mid range, we need OFDM weak signal
1448 1.1 christos * detection but we can raise first step level.
1449 1.1 christos */
1450 1.1 christos if (!ani->ofdm_weak_signal) {
1451 1.1 christos ani->ofdm_weak_signal = 1;
1452 1.1 christos ops->enable_ofdm_weak_signal(sc);
1453 1.1 christos }
1454 1.1 christos if (ani->firstep_level < 2) {
1455 1.1 christos ani->firstep_level++;
1456 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1457 1.1 christos }
1458 1.19 msaitoh } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
1459 1.1 christos /*
1460 1.1 christos * Beacon RSSI is low, if in b/g mode, turn off OFDM weak
1461 1.1 christos * signal detection and zero first step level to maximize
1462 1.1 christos * CCK sensitivity.
1463 1.1 christos */
1464 1.1 christos if (ani->ofdm_weak_signal) {
1465 1.1 christos ani->ofdm_weak_signal = 0;
1466 1.1 christos ops->disable_ofdm_weak_signal(sc);
1467 1.1 christos }
1468 1.1 christos if (ani->firstep_level > 0) {
1469 1.1 christos ani->firstep_level = 0;
1470 1.1 christos ops->set_firstep_level(sc, 0);
1471 1.1 christos }
1472 1.1 christos }
1473 1.1 christos }
1474 1.1 christos #endif /* notyet */
1475 1.1 christos
1476 1.1 christos #ifdef notyet
1477 1.1 christos Static void
1478 1.1 christos athn_ani_cck_err_trigger(struct athn_softc *sc)
1479 1.1 christos {
1480 1.1 christos struct athn_ani *ani = &sc->sc_ani;
1481 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1482 1.1 christos int32_t rssi;
1483 1.1 christos
1484 1.1 christos /* Raise noise immunity level, up to max. */
1485 1.1 christos if (ani->noise_immunity_level < 4) {
1486 1.1 christos ani->noise_immunity_level++;
1487 1.1 christos ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1488 1.1 christos return;
1489 1.1 christos }
1490 1.1 christos
1491 1.1 christos #ifndef IEEE80211_STA_ONLY
1492 1.1 christos if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1493 1.1 christos if (ani->firstep_level < 2) {
1494 1.1 christos ani->firstep_level++;
1495 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1496 1.1 christos }
1497 1.1 christos return;
1498 1.1 christos }
1499 1.1 christos #endif
1500 1.1 christos rssi = athn_ani_get_rssi(sc);
1501 1.1 christos if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1502 1.1 christos /*
1503 1.1 christos * Beacon RSSI is in mid or high range, raise first step
1504 1.1 christos * level.
1505 1.1 christos */
1506 1.1 christos if (ani->firstep_level < 2) {
1507 1.1 christos ani->firstep_level++;
1508 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1509 1.1 christos }
1510 1.19 msaitoh } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
1511 1.1 christos /*
1512 1.1 christos * Beacon RSSI is low, zero first step level to maximize
1513 1.1 christos * CCK sensitivity.
1514 1.1 christos */
1515 1.1 christos if (ani->firstep_level > 0) {
1516 1.1 christos ani->firstep_level = 0;
1517 1.1 christos ops->set_firstep_level(sc, 0);
1518 1.1 christos }
1519 1.1 christos }
1520 1.1 christos }
1521 1.1 christos #endif /* notyet */
1522 1.1 christos
1523 1.1 christos #ifdef notyet
1524 1.1 christos Static void
1525 1.1 christos athn_ani_lower_immunity(struct athn_softc *sc)
1526 1.1 christos {
1527 1.1 christos struct athn_ani *ani = &sc->sc_ani;
1528 1.1 christos struct athn_ops *ops = &sc->sc_ops;
1529 1.1 christos int32_t rssi;
1530 1.1 christos
1531 1.1 christos #ifndef IEEE80211_STA_ONLY
1532 1.1 christos if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1533 1.1 christos if (ani->firstep_level > 0) {
1534 1.1 christos ani->firstep_level--;
1535 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1536 1.1 christos }
1537 1.1 christos return;
1538 1.1 christos }
1539 1.1 christos #endif
1540 1.1 christos rssi = athn_ani_get_rssi(sc);
1541 1.1 christos if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
1542 1.1 christos /*
1543 1.1 christos * Beacon RSSI is high, leave OFDM weak signal detection
1544 1.1 christos * off or it may oscillate.
1545 1.1 christos */
1546 1.19 msaitoh } else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1547 1.1 christos /*
1548 1.1 christos * Beacon RSSI is in mid range, turn on OFDM weak signal
1549 1.1 christos * detection or lower first step level.
1550 1.1 christos */
1551 1.1 christos if (!ani->ofdm_weak_signal) {
1552 1.1 christos ani->ofdm_weak_signal = 1;
1553 1.1 christos ops->enable_ofdm_weak_signal(sc);
1554 1.1 christos return;
1555 1.1 christos }
1556 1.1 christos if (ani->firstep_level > 0) {
1557 1.1 christos ani->firstep_level--;
1558 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1559 1.1 christos return;
1560 1.1 christos }
1561 1.19 msaitoh } else {
1562 1.1 christos /* Beacon RSSI is low, lower first step level. */
1563 1.1 christos if (ani->firstep_level > 0) {
1564 1.1 christos ani->firstep_level--;
1565 1.1 christos ops->set_firstep_level(sc, ani->firstep_level);
1566 1.1 christos return;
1567 1.1 christos }
1568 1.1 christos }
1569 1.1 christos /*
1570 1.1 christos * Lower spur immunity level down to zero, or if all else fails,
1571 1.1 christos * lower noise immunity level down to zero.
1572 1.1 christos */
1573 1.1 christos if (ani->spur_immunity_level > 0) {
1574 1.1 christos ani->spur_immunity_level--;
1575 1.1 christos ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
1576 1.19 msaitoh } else if (ani->noise_immunity_level > 0) {
1577 1.1 christos ani->noise_immunity_level--;
1578 1.1 christos ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1579 1.1 christos }
1580 1.1 christos }
1581 1.1 christos #endif /* notyet */
1582 1.1 christos
1583 1.1 christos #ifdef notyet
1584 1.1 christos Static void
1585 1.1 christos athn_ani_restart(struct athn_softc *sc)
1586 1.1 christos {
1587 1.1 christos struct athn_ani *ani = &sc->sc_ani;
1588 1.1 christos
1589 1.1 christos AR_WRITE(sc, AR_PHY_ERR_1, 0);
1590 1.1 christos AR_WRITE(sc, AR_PHY_ERR_2, 0);
1591 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1592 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1593 1.1 christos AR_WRITE_BARRIER(sc);
1594 1.1 christos
1595 1.1 christos ani->listen_time = 0;
1596 1.1 christos ani->ofdm_phy_err_count = 0;
1597 1.1 christos ani->cck_phy_err_count = 0;
1598 1.1 christos }
1599 1.1 christos #endif /* notyet */
1600 1.1 christos
1601 1.1 christos #ifdef notyet
1602 1.1 christos Static void
1603 1.1 christos athn_ani_monitor(struct athn_softc *sc)
1604 1.1 christos {
1605 1.1 christos struct athn_ani *ani = &sc->sc_ani;
1606 1.1 christos uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2;
1607 1.1 christos int32_t cycdelta, txfdelta, rxfdelta;
1608 1.1 christos int32_t listen_time;
1609 1.1 christos
1610 1.1 christos txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */
1611 1.1 christos rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */
1612 1.1 christos cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */
1613 1.1 christos
1614 1.1 christos if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) {
1615 1.1 christos cycdelta = cyccnt - ani->cyccnt;
1616 1.1 christos txfdelta = txfcnt - ani->txfcnt;
1617 1.1 christos rxfdelta = rxfcnt - ani->rxfcnt;
1618 1.1 christos
1619 1.1 christos listen_time = (cycdelta - txfdelta - rxfdelta) /
1620 1.1 christos (athn_clock_rate(sc) * 1000);
1621 1.19 msaitoh } else
1622 1.1 christos listen_time = 0;
1623 1.1 christos
1624 1.1 christos ani->cyccnt = cyccnt;
1625 1.1 christos ani->txfcnt = txfcnt;
1626 1.1 christos ani->rxfcnt = rxfcnt;
1627 1.1 christos
1628 1.1 christos if (listen_time < 0) {
1629 1.1 christos athn_ani_restart(sc);
1630 1.1 christos return;
1631 1.1 christos }
1632 1.1 christos ani->listen_time += listen_time;
1633 1.1 christos
1634 1.1 christos phy1 = AR_READ(sc, AR_PHY_ERR_1);
1635 1.1 christos phy2 = AR_READ(sc, AR_PHY_ERR_2);
1636 1.1 christos
1637 1.1 christos if (phy1 < ani->ofdm_phy_err_base) {
1638 1.1 christos AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base);
1639 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1640 1.1 christos }
1641 1.1 christos if (phy2 < ani->cck_phy_err_base) {
1642 1.1 christos AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
1643 1.1 christos AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1644 1.1 christos }
1645 1.1 christos if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) {
1646 1.1 christos AR_WRITE_BARRIER(sc);
1647 1.1 christos return;
1648 1.1 christos }
1649 1.1 christos ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base;
1650 1.1 christos ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base;
1651 1.1 christos
1652 1.1 christos if (ani->listen_time > 5 * ATHN_ANI_PERIOD) {
1653 1.1 christos /* Check to see if we need to lower immunity. */
1654 1.1 christos if (ani->ofdm_phy_err_count <=
1655 1.1 christos ani->listen_time * ani->ofdm_trig_low / 1000 &&
1656 1.1 christos ani->cck_phy_err_count <=
1657 1.1 christos ani->listen_time * ani->cck_trig_low / 1000)
1658 1.1 christos athn_ani_lower_immunity(sc);
1659 1.1 christos athn_ani_restart(sc);
1660 1.1 christos
1661 1.19 msaitoh } else if (ani->listen_time > ATHN_ANI_PERIOD) {
1662 1.1 christos /* Check to see if we need to raise immunity. */
1663 1.1 christos if (ani->ofdm_phy_err_count >
1664 1.1 christos ani->listen_time * ani->ofdm_trig_high / 1000) {
1665 1.1 christos athn_ani_ofdm_err_trigger(sc);
1666 1.1 christos athn_ani_restart(sc);
1667 1.19 msaitoh } else if (ani->cck_phy_err_count >
1668 1.1 christos ani->listen_time * ani->cck_trig_high / 1000) {
1669 1.1 christos athn_ani_cck_err_trigger(sc);
1670 1.1 christos athn_ani_restart(sc);
1671 1.1 christos }
1672 1.1 christos }
1673 1.1 christos }
1674 1.1 christos #endif /* notyet */
1675 1.1 christos
1676 1.1 christos PUBLIC uint8_t
1677 1.1 christos athn_chan2fbin(struct ieee80211_channel *c)
1678 1.1 christos {
1679 1.1 christos
1680 1.1 christos if (IEEE80211_IS_CHAN_2GHZ(c))
1681 1.1 christos return c->ic_freq - 2300;
1682 1.1 christos else
1683 1.1 christos return (c->ic_freq - 4800) / 5;
1684 1.1 christos }
1685 1.1 christos
1686 1.1 christos PUBLIC int
1687 1.1 christos athn_interpolate(int x, int x1, int y1, int x2, int y2)
1688 1.1 christos {
1689 1.1 christos
1690 1.1 christos if (x1 == x2) /* Prevents division by zero. */
1691 1.1 christos return y1;
1692 1.1 christos /* Linear interpolation. */
1693 1.1 christos return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1);
1694 1.1 christos }
1695 1.1 christos
1696 1.1 christos PUBLIC void
1697 1.1 christos athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers,
1698 1.1 christos int *lo, int *hi)
1699 1.1 christos {
1700 1.1 christos int i;
1701 1.1 christos
1702 1.1 christos for (i = 0; i < npiers; i++)
1703 1.1 christos if (pierfreq[i] == AR_BCHAN_UNUSED ||
1704 1.1 christos pierfreq[i] > fbin)
1705 1.1 christos break;
1706 1.1 christos *hi = i;
1707 1.1 christos *lo = *hi - 1;
1708 1.1 christos if (*lo == -1)
1709 1.1 christos *lo = *hi;
1710 1.1 christos else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED)
1711 1.1 christos *hi = *lo;
1712 1.1 christos }
1713 1.1 christos
1714 1.1 christos Static void
1715 1.1 christos athn_init_dma(struct athn_softc *sc)
1716 1.1 christos {
1717 1.1 christos uint32_t reg;
1718 1.1 christos
1719 1.1 christos if (!AR_SREV_9380_10_OR_LATER(sc)) {
1720 1.1 christos /* Set AHB not to do cacheline prefetches. */
1721 1.1 christos AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1722 1.1 christos }
1723 1.1 christos reg = AR_READ(sc, AR_TXCFG);
1724 1.1 christos /* Let MAC DMA reads be in 128-byte chunks. */
1725 1.1 christos reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
1726 1.1 christos
1727 1.1 christos /* Set initial Tx trigger level. */
1728 1.1 christos if (AR_SREV_9285(sc) || AR_SREV_9271(sc))
1729 1.1 christos reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
1730 1.1 christos else if (!AR_SREV_9380_10_OR_LATER(sc))
1731 1.1 christos reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
1732 1.1 christos AR_WRITE(sc, AR_TXCFG, reg);
1733 1.1 christos
1734 1.1 christos /* Let MAC DMA writes be in 128-byte chunks. */
1735 1.1 christos reg = AR_READ(sc, AR_RXCFG);
1736 1.1 christos reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);
1737 1.1 christos AR_WRITE(sc, AR_RXCFG, reg);
1738 1.1 christos
1739 1.1 christos /* Setup Rx FIFO threshold to hold off Tx activities. */
1740 1.1 christos AR_WRITE(sc, AR_RXFIFO_CFG, 512);
1741 1.1 christos
1742 1.1 christos /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */
1743 1.1 christos if (AR_SREV_9285(sc)) {
1744 1.1 christos AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1745 1.1 christos AR9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1746 1.19 msaitoh } else if (!AR_SREV_9271(sc)) {
1747 1.1 christos AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1748 1.1 christos AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1749 1.1 christos }
1750 1.1 christos AR_WRITE_BARRIER(sc);
1751 1.1 christos
1752 1.1 christos /* Reset Tx status ring. */
1753 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc))
1754 1.1 christos ar9003_reset_txsring(sc);
1755 1.1 christos }
1756 1.1 christos
1757 1.1 christos PUBLIC void
1758 1.1 christos athn_inc_tx_trigger_level(struct athn_softc *sc)
1759 1.1 christos {
1760 1.1 christos uint32_t reg, ftrig;
1761 1.1 christos
1762 1.1 christos reg = AR_READ(sc, AR_TXCFG);
1763 1.1 christos ftrig = MS(reg, AR_TXCFG_FTRIG);
1764 1.1 christos /*
1765 1.1 christos * NB: The AR9285 and all single-stream parts have an issue that
1766 1.1 christos * limits the size of the PCU Tx FIFO to 2KB instead of 4KB.
1767 1.1 christos */
1768 1.1 christos if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f))
1769 1.1 christos return; /* Already at max. */
1770 1.1 christos reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
1771 1.1 christos AR_WRITE(sc, AR_TXCFG, reg);
1772 1.1 christos AR_WRITE_BARRIER(sc);
1773 1.1 christos }
1774 1.1 christos
1775 1.1 christos PUBLIC int
1776 1.1 christos athn_stop_rx_dma(struct athn_softc *sc)
1777 1.1 christos {
1778 1.1 christos int ntries;
1779 1.1 christos
1780 1.1 christos AR_WRITE(sc, AR_CR, AR_CR_RXD);
1781 1.1 christos /* Wait for Rx enable bit to go low. */
1782 1.1 christos for (ntries = 0; ntries < 100; ntries++) {
1783 1.1 christos if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
1784 1.1 christos return 0;
1785 1.1 christos DELAY(100);
1786 1.1 christos }
1787 1.1 christos DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n");
1788 1.1 christos return ETIMEDOUT;
1789 1.1 christos }
1790 1.1 christos
1791 1.1 christos #ifdef unused
1792 1.1 christos Static int
1793 1.1 christos athn_rx_abort(struct athn_softc *sc)
1794 1.1 christos {
1795 1.1 christos int ntries;
1796 1.1 christos
1797 1.1 christos AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
1798 1.1 christos for (ntries = 0; ntries < 1000; ntries++) {
1799 1.1 christos if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0)
1800 1.1 christos return 0;
1801 1.1 christos DELAY(10);
1802 1.1 christos }
1803 1.1 christos DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n");
1804 1.1 christos AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
1805 1.1 christos AR_WRITE_BARRIER(sc);
1806 1.1 christos return ETIMEDOUT;
1807 1.1 christos }
1808 1.1 christos #endif /* unused */
1809 1.1 christos
1810 1.1 christos Static void
1811 1.1 christos athn_tx_reclaim(struct athn_softc *sc, int qid)
1812 1.1 christos {
1813 1.1 christos struct athn_txq *txq = &sc->sc_txq[qid];
1814 1.1 christos struct athn_tx_buf *bf;
1815 1.1 christos
1816 1.1 christos /* Reclaim all buffers queued in the specified Tx queue. */
1817 1.1 christos /* NB: Tx DMA must be stopped. */
1818 1.1 christos while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) {
1819 1.1 christos SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
1820 1.1 christos
1821 1.1 christos bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
1822 1.1 christos bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1823 1.1 christos bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
1824 1.1 christos m_freem(bf->bf_m);
1825 1.1 christos bf->bf_m = NULL;
1826 1.1 christos bf->bf_ni = NULL; /* Nodes already freed! */
1827 1.1 christos
1828 1.1 christos /* Link Tx buffer back to global free list. */
1829 1.1 christos SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
1830 1.1 christos }
1831 1.1 christos }
1832 1.1 christos
1833 1.1 christos PUBLIC int
1834 1.1 christos athn_tx_pending(struct athn_softc *sc, int qid)
1835 1.1 christos {
1836 1.1 christos
1837 1.1 christos return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 ||
1838 1.1 christos (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0;
1839 1.1 christos }
1840 1.1 christos
1841 1.1 christos PUBLIC void
1842 1.1 christos athn_stop_tx_dma(struct athn_softc *sc, int qid)
1843 1.1 christos {
1844 1.1 christos uint32_t tsflo;
1845 1.1 christos int ntries, i;
1846 1.1 christos
1847 1.1 christos AR_WRITE(sc, AR_Q_TXD, 1 << qid);
1848 1.1 christos for (ntries = 0; ntries < 40; ntries++) {
1849 1.1 christos if (!athn_tx_pending(sc, qid))
1850 1.1 christos break;
1851 1.1 christos DELAY(100);
1852 1.1 christos }
1853 1.1 christos if (ntries == 40) {
1854 1.1 christos for (i = 0; i < 2; i++) {
1855 1.1 christos tsflo = AR_READ(sc, AR_TSF_L32) / 1024;
1856 1.1 christos AR_WRITE(sc, AR_QUIET2,
1857 1.1 christos SM(AR_QUIET2_QUIET_DUR, 10));
1858 1.1 christos AR_WRITE(sc, AR_QUIET_PERIOD, 100);
1859 1.1 christos AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo);
1860 1.1 christos AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
1861 1.1 christos if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo)
1862 1.1 christos break;
1863 1.1 christos }
1864 1.1 christos AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
1865 1.1 christos AR_WRITE_BARRIER(sc);
1866 1.1 christos DELAY(200);
1867 1.1 christos AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
1868 1.1 christos AR_WRITE_BARRIER(sc);
1869 1.1 christos
1870 1.1 christos for (ntries = 0; ntries < 40; ntries++) {
1871 1.1 christos if (!athn_tx_pending(sc, qid))
1872 1.1 christos break;
1873 1.1 christos DELAY(100);
1874 1.1 christos }
1875 1.1 christos
1876 1.1 christos AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
1877 1.1 christos }
1878 1.1 christos AR_WRITE(sc, AR_Q_TXD, 0);
1879 1.1 christos AR_WRITE_BARRIER(sc);
1880 1.1 christos }
1881 1.1 christos
1882 1.1 christos PUBLIC int
1883 1.1 christos athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
1884 1.1 christos {
1885 1.1 christos #define divround(a, b) (((a) + (b) - 1) / (b))
1886 1.1 christos int txtime;
1887 1.1 christos
1888 1.1 christos /* XXX HT. */
1889 1.1 christos if (athn_rates[ridx].phy == IEEE80211_T_OFDM) {
1890 1.1 christos txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate);
1891 1.1 christos /* SIFS is 10us for 11g but Signal Extension adds 6us. */
1892 1.1 christos txtime = 16 + 4 + 4 * txtime + 16;
1893 1.19 msaitoh } else {
1894 1.1 christos txtime = divround(16 * len, athn_rates[ridx].rate);
1895 1.1 christos if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE))
1896 1.1 christos txtime += 72 + 24;
1897 1.1 christos else
1898 1.1 christos txtime += 144 + 48;
1899 1.1 christos txtime += 10; /* 10us SIFS. */
1900 1.1 christos }
1901 1.1 christos return txtime;
1902 1.1 christos #undef divround
1903 1.1 christos }
1904 1.1 christos
1905 1.1 christos PUBLIC void
1906 1.1 christos athn_init_tx_queues(struct athn_softc *sc)
1907 1.1 christos {
1908 1.1 christos int qid;
1909 1.1 christos
1910 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++) {
1911 1.1 christos SIMPLEQ_INIT(&sc->sc_txq[qid].head);
1912 1.1 christos sc->sc_txq[qid].lastds = NULL;
1913 1.1 christos sc->sc_txq[qid].wait = NULL;
1914 1.1 christos sc->sc_txq[qid].queued = 0;
1915 1.1 christos
1916 1.1 christos AR_WRITE(sc, AR_DRETRY_LIMIT(qid),
1917 1.1 christos SM(AR_D_RETRY_LIMIT_STA_SH, 32) |
1918 1.1 christos SM(AR_D_RETRY_LIMIT_STA_LG, 32) |
1919 1.1 christos SM(AR_D_RETRY_LIMIT_FR_SH, 10));
1920 1.1 christos AR_WRITE(sc, AR_QMISC(qid),
1921 1.1 christos AR_Q_MISC_DCU_EARLY_TERM_REQ);
1922 1.1 christos AR_WRITE(sc, AR_DMISC(qid),
1923 1.1 christos SM(AR_D_MISC_BKOFF_THRESH, 2) |
1924 1.1 christos AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN);
1925 1.1 christos }
1926 1.1 christos
1927 1.1 christos /* Init beacon queue. */
1928 1.1 christos AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),
1929 1.1 christos AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE |
1930 1.1 christos AR_Q_MISC_CBR_INCR_DIS1);
1931 1.1 christos AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),
1932 1.1 christos SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
1933 1.1 christos AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |
1934 1.1 christos AR_D_MISC_BEACON_USE |
1935 1.1 christos AR_D_MISC_POST_FR_BKOFF_DIS);
1936 1.1 christos AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),
1937 1.1 christos SM(AR_D_LCL_IFS_CWMIN, 0) |
1938 1.1 christos SM(AR_D_LCL_IFS_CWMAX, 0) |
1939 1.1 christos SM(AR_D_LCL_IFS_AIFS, 1));
1940 1.1 christos
1941 1.1 christos /* Init CAB (Content After Beacon) queue. */
1942 1.1 christos AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),
1943 1.1 christos AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |
1944 1.1 christos AR_Q_MISC_CBR_INCR_DIS0);
1945 1.1 christos AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),
1946 1.1 christos SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
1947 1.1 christos AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL));
1948 1.1 christos
1949 1.1 christos /* Init PS-Poll queue. */
1950 1.1 christos AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),
1951 1.1 christos AR_Q_MISC_CBR_INCR_DIS1);
1952 1.1 christos
1953 1.1 christos /* Init UAPSD queue. */
1954 1.1 christos AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
1955 1.1 christos AR_D_MISC_POST_FR_BKOFF_DIS);
1956 1.1 christos
1957 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc)) {
1958 1.1 christos /* Enable MAC descriptor CRC check. */
1959 1.1 christos AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
1960 1.1 christos }
1961 1.1 christos /* Enable DESC interrupts for all Tx queues. */
1962 1.1 christos AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
1963 1.1 christos /* Enable EOL interrupts for all Tx queues except UAPSD. */
1964 1.1 christos AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
1965 1.1 christos AR_WRITE_BARRIER(sc);
1966 1.1 christos }
1967 1.1 christos
1968 1.1 christos PUBLIC void
1969 1.1 christos athn_set_sta_timers(struct athn_softc *sc)
1970 1.1 christos {
1971 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
1972 1.1 christos uint32_t tsfhi, tsflo, tsftu, reg;
1973 1.1 christos uint32_t intval, next_tbtt, next_dtim;
1974 1.7 christos int dtim_period, rem_dtim_count;
1975 1.1 christos
1976 1.1 christos tsfhi = AR_READ(sc, AR_TSF_U32);
1977 1.1 christos tsflo = AR_READ(sc, AR_TSF_L32);
1978 1.1 christos tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE;
1979 1.1 christos
1980 1.1 christos /* Beacon interval in TU. */
1981 1.1 christos intval = ic->ic_bss->ni_intval;
1982 1.1 christos
1983 1.1 christos next_tbtt = roundup(tsftu, intval);
1984 1.1 christos #ifdef notyet
1985 1.1 christos dtim_period = ic->ic_dtim_period;
1986 1.1 christos if (dtim_period <= 0)
1987 1.1 christos #endif
1988 1.1 christos dtim_period = 1; /* Assume all TIMs are DTIMs. */
1989 1.1 christos
1990 1.1 christos #ifdef notyet
1991 1.7 christos int dtim_count = ic->ic_dtim_count;
1992 1.1 christos if (dtim_count >= dtim_period) /* Should not happen. */
1993 1.7 christos dtim_count = 0; /* Assume last TIM was a DTIM. */
1994 1.1 christos #endif
1995 1.1 christos
1996 1.1 christos /* Compute number of remaining TIMs until next DTIM. */
1997 1.1 christos rem_dtim_count = 0; /* XXX */
1998 1.1 christos next_dtim = next_tbtt + rem_dtim_count * intval;
1999 1.1 christos
2000 1.1 christos AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
2001 1.1 christos AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2002 1.1 christos AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2003 1.1 christos
2004 1.1 christos /*
2005 1.1 christos * Set the number of consecutive beacons to miss before raising
2006 1.1 christos * a BMISS interrupt to 10.
2007 1.1 christos */
2008 1.1 christos reg = AR_READ(sc, AR_RSSI_THR);
2009 1.1 christos reg = RW(reg, AR_RSSI_THR_BM_THR, 10);
2010 1.1 christos AR_WRITE(sc, AR_RSSI_THR, reg);
2011 1.1 christos
2012 1.1 christos AR_WRITE(sc, AR_NEXT_DTIM,
2013 1.1 christos (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
2014 1.1 christos AR_WRITE(sc, AR_NEXT_TIM,
2015 1.1 christos (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
2016 1.1 christos
2017 1.1 christos /* CAB timeout is in 1/8 TU. */
2018 1.1 christos AR_WRITE(sc, AR_SLEEP1,
2019 1.1 christos SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |
2020 1.1 christos AR_SLEEP1_ASSUME_DTIM);
2021 1.1 christos AR_WRITE(sc, AR_SLEEP2,
2022 1.1 christos SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL));
2023 1.1 christos
2024 1.1 christos AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU);
2025 1.1 christos AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU);
2026 1.1 christos
2027 1.1 christos AR_SETBITS(sc, AR_TIMER_MODE,
2028 1.1 christos AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN);
2029 1.1 christos
2030 1.1 christos /* Set TSF out-of-range threshold (fixed at 16k us). */
2031 1.1 christos AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
2032 1.1 christos
2033 1.1 christos AR_WRITE_BARRIER(sc);
2034 1.1 christos }
2035 1.1 christos
2036 1.1 christos #ifndef IEEE80211_STA_ONLY
2037 1.1 christos PUBLIC void
2038 1.1 christos athn_set_hostap_timers(struct athn_softc *sc)
2039 1.1 christos {
2040 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2041 1.1 christos uint32_t intval, next_tbtt;
2042 1.1 christos
2043 1.1 christos /* Beacon interval in TU. */
2044 1.1 christos intval = ic->ic_bss->ni_intval;
2045 1.1 christos next_tbtt = intval;
2046 1.1 christos
2047 1.1 christos AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
2048 1.1 christos AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,
2049 1.1 christos (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU);
2050 1.1 christos AR_WRITE(sc, AR_NEXT_CFP,
2051 1.1 christos (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU);
2052 1.1 christos
2053 1.1 christos AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2054 1.1 christos AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2055 1.1 christos AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU);
2056 1.1 christos AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU);
2057 1.1 christos
2058 1.1 christos AR_WRITE(sc, AR_TIMER_MODE,
2059 1.1 christos AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN);
2060 1.1 christos
2061 1.1 christos AR_WRITE_BARRIER(sc);
2062 1.1 christos }
2063 1.1 christos #endif
2064 1.1 christos
2065 1.1 christos PUBLIC void
2066 1.1 christos athn_set_opmode(struct athn_softc *sc)
2067 1.1 christos {
2068 1.1 christos uint32_t reg;
2069 1.1 christos
2070 1.1 christos switch (sc->sc_ic.ic_opmode) {
2071 1.1 christos #ifndef IEEE80211_STA_ONLY
2072 1.1 christos case IEEE80211_M_HOSTAP:
2073 1.1 christos reg = AR_READ(sc, AR_STA_ID1);
2074 1.1 christos reg &= ~AR_STA_ID1_ADHOC;
2075 1.1 christos reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE;
2076 1.1 christos AR_WRITE(sc, AR_STA_ID1, reg);
2077 1.1 christos
2078 1.1 christos AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
2079 1.1 christos break;
2080 1.1 christos case IEEE80211_M_IBSS:
2081 1.1 christos case IEEE80211_M_AHDEMO:
2082 1.1 christos reg = AR_READ(sc, AR_STA_ID1);
2083 1.1 christos reg &= ~AR_STA_ID1_STA_AP;
2084 1.1 christos reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE;
2085 1.1 christos AR_WRITE(sc, AR_STA_ID1, reg);
2086 1.1 christos
2087 1.1 christos AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
2088 1.1 christos break;
2089 1.1 christos #endif
2090 1.1 christos default:
2091 1.1 christos reg = AR_READ(sc, AR_STA_ID1);
2092 1.1 christos reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP);
2093 1.1 christos reg |= AR_STA_ID1_KSRCH_MODE;
2094 1.1 christos AR_WRITE(sc, AR_STA_ID1, reg);
2095 1.1 christos break;
2096 1.1 christos }
2097 1.1 christos AR_WRITE_BARRIER(sc);
2098 1.1 christos }
2099 1.1 christos
2100 1.1 christos PUBLIC void
2101 1.1 christos athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni)
2102 1.1 christos {
2103 1.1 christos const uint8_t *bssid = ni->ni_bssid;
2104 1.1 christos
2105 1.1 christos AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
2106 1.1 christos AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
2107 1.1 christos SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)));
2108 1.1 christos AR_WRITE_BARRIER(sc);
2109 1.1 christos }
2110 1.1 christos
2111 1.1 christos Static void
2112 1.1 christos athn_enable_interrupts(struct athn_softc *sc)
2113 1.1 christos {
2114 1.1 christos uint32_t mask2;
2115 1.1 christos
2116 1.1 christos athn_disable_interrupts(sc); /* XXX */
2117 1.1 christos
2118 1.1 christos AR_WRITE(sc, AR_IMR, sc->sc_imask);
2119 1.1 christos
2120 1.1 christos mask2 = AR_READ(sc, AR_IMR_S2);
2121 1.1 christos mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2122 1.1 christos AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR);
2123 1.1 christos mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST;
2124 1.1 christos AR_WRITE(sc, AR_IMR_S2, mask2);
2125 1.1 christos
2126 1.1 christos AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2127 1.1 christos
2128 1.1 christos AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
2129 1.1 christos
2130 1.1 christos AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
2131 1.1 christos AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2132 1.1 christos
2133 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
2134 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
2135 1.1 christos AR_WRITE_BARRIER(sc);
2136 1.1 christos }
2137 1.1 christos
2138 1.1 christos Static void
2139 1.1 christos athn_disable_interrupts(struct athn_softc *sc)
2140 1.1 christos {
2141 1.1 christos
2142 1.1 christos AR_WRITE(sc, AR_IER, 0);
2143 1.1 christos (void)AR_READ(sc, AR_IER);
2144 1.1 christos
2145 1.1 christos AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
2146 1.1 christos (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
2147 1.1 christos
2148 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
2149 1.1 christos (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
2150 1.1 christos
2151 1.1 christos AR_WRITE(sc, AR_IMR, 0);
2152 1.1 christos
2153 1.1 christos AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
2154 1.1 christos AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2155 1.1 christos AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2156 1.1 christos
2157 1.1 christos AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2158 1.1 christos AR_WRITE_BARRIER(sc);
2159 1.1 christos }
2160 1.1 christos
2161 1.1 christos Static void
2162 1.1 christos athn_init_qos(struct athn_softc *sc)
2163 1.1 christos {
2164 1.1 christos
2165 1.1 christos /* Initialize QoS settings. */
2166 1.1 christos AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa);
2167 1.1 christos AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210);
2168 1.1 christos AR_WRITE(sc, AR_QOS_NO_ACK,
2169 1.1 christos SM(AR_QOS_NO_ACK_TWO_BIT, 2) |
2170 1.1 christos SM(AR_QOS_NO_ACK_BIT_OFF, 5) |
2171 1.1 christos SM(AR_QOS_NO_ACK_BYTE_OFF, 0));
2172 1.1 christos AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL);
2173 1.1 christos /* Initialize TXOP for all TIDs. */
2174 1.1 christos AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff);
2175 1.1 christos AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
2176 1.1 christos AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
2177 1.1 christos AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
2178 1.1 christos AR_WRITE_BARRIER(sc);
2179 1.1 christos }
2180 1.1 christos
2181 1.1 christos PUBLIC int
2182 1.1 christos athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
2183 1.1 christos struct ieee80211_channel *extchan, int init)
2184 1.1 christos {
2185 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2186 1.1 christos struct athn_ops *ops = &sc->sc_ops;
2187 1.1 christos uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;
2188 1.1 christos int i, error;
2189 1.1 christos
2190 1.1 christos /* XXX not if already awake */
2191 1.1 christos if ((error = athn_set_power_awake(sc)) != 0) {
2192 1.1 christos aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
2193 1.1 christos return error;
2194 1.1 christos }
2195 1.1 christos
2196 1.1 christos /* Preserve the antenna on a channel switch. */
2197 1.1 christos if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0)
2198 1.1 christos def_ant = 1;
2199 1.1 christos /* Preserve other registers. */
2200 1.1 christos sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2201 1.1 christos cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M |
2202 1.1 christos AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M |
2203 1.1 christos AR_CFG_LED_BLINK_SLOW);
2204 1.1 christos
2205 1.1 christos /* Mark PHY as inactive. */
2206 1.1 christos ops->disable_phy(sc);
2207 1.1 christos
2208 1.1 christos if (init && AR_SREV_9271(sc)) {
2209 1.1 christos AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2210 1.1 christos AR9271_RADIO_RF_RST);
2211 1.1 christos DELAY(50);
2212 1.1 christos }
2213 1.1 christos if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) {
2214 1.1 christos /* Save TSF before it gets cleared. */
2215 1.1 christos tsfhi = AR_READ(sc, AR_TSF_U32);
2216 1.1 christos tsflo = AR_READ(sc, AR_TSF_L32);
2217 1.1 christos
2218 1.1 christos /* NB: RTC reset clears TSF. */
2219 1.1 christos error = athn_reset_power_on(sc);
2220 1.19 msaitoh } else {
2221 1.1 christos tsfhi = tsflo = 0; /* XXX: gcc */
2222 1.1 christos error = athn_reset(sc, 0);
2223 1.1 christos }
2224 1.1 christos if (error != 0) {
2225 1.1 christos aprint_error_dev(sc->sc_dev,
2226 1.1 christos "could not reset chip (error=%d)\n", error);
2227 1.1 christos return error;
2228 1.1 christos }
2229 1.1 christos
2230 1.1 christos /* XXX not if already awake */
2231 1.1 christos if ((error = athn_set_power_awake(sc)) != 0) {
2232 1.1 christos aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
2233 1.1 christos return error;
2234 1.1 christos }
2235 1.1 christos
2236 1.1 christos athn_init_pll(sc, curchan);
2237 1.1 christos ops->set_rf_mode(sc, curchan);
2238 1.1 christos
2239 1.1 christos if (sc->sc_flags & ATHN_FLAG_RFSILENT) {
2240 1.1 christos /* Check that the radio is not disabled by hardware switch. */
2241 1.1 christos reg = ops->gpio_read(sc, sc->sc_rfsilent_pin);
2242 1.1 christos if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)
2243 1.1 christos reg = !reg;
2244 1.1 christos if (!reg) {
2245 1.1 christos aprint_error_dev(sc->sc_dev,
2246 1.1 christos "radio is disabled by hardware switch\n");
2247 1.1 christos return EPERM;
2248 1.1 christos }
2249 1.1 christos }
2250 1.1 christos if (init && AR_SREV_9271(sc)) {
2251 1.1 christos AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2252 1.1 christos AR9271_GATE_MAC_CTL);
2253 1.1 christos DELAY(50);
2254 1.1 christos }
2255 1.1 christos if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) {
2256 1.1 christos /* Restore TSF if it got cleared. */
2257 1.1 christos AR_WRITE(sc, AR_TSF_L32, tsflo);
2258 1.1 christos AR_WRITE(sc, AR_TSF_U32, tsfhi);
2259 1.1 christos }
2260 1.1 christos
2261 1.1 christos if (AR_SREV_9280_10_OR_LATER(sc))
2262 1.1 christos AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
2263 1.1 christos
2264 1.1 christos if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
2265 1.1 christos ar9287_1_3_enable_async_fifo(sc);
2266 1.1 christos
2267 1.1 christos /* Write init values to hardware. */
2268 1.1 christos ops->hw_init(sc, curchan, extchan);
2269 1.1 christos
2270 1.1 christos /*
2271 1.1 christos * Only >=AR9280 2.0 parts are capable of encrypting unicast
2272 1.1 christos * management frames using CCMP.
2273 1.1 christos */
2274 1.1 christos if (AR_SREV_9280_20_OR_LATER(sc)) {
2275 1.1 christos reg = AR_READ(sc, AR_AES_MUTE_MASK1);
2276 1.1 christos /* Do not mask the subtype field in management frames. */
2277 1.1 christos reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);
2278 1.1 christos reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,
2279 1.11 joerg (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT |
2280 1.1 christos IEEE80211_FC1_MORE_DATA));
2281 1.1 christos AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
2282 1.19 msaitoh } else if (AR_SREV_9160_10_OR_LATER(sc)) {
2283 1.1 christos /* Disable hardware crypto for management frames. */
2284 1.1 christos AR_CLRBITS(sc, AR_PCU_MISC_MODE2,
2285 1.1 christos AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2286 1.1 christos AR_SETBITS(sc, AR_PCU_MISC_MODE2,
2287 1.1 christos AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2288 1.1 christos }
2289 1.1 christos
2290 1.1 christos if (ic->ic_curmode != IEEE80211_MODE_11B)
2291 1.1 christos ops->set_delta_slope(sc, curchan, extchan);
2292 1.1 christos
2293 1.1 christos ops->spur_mitigate(sc, curchan, extchan);
2294 1.1 christos ops->init_from_rom(sc, curchan, extchan);
2295 1.1 christos
2296 1.1 christos /* XXX */
2297 1.1 christos AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]));
2298 1.1 christos AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |
2299 1.1 christos sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE);
2300 1.1 christos
2301 1.1 christos athn_set_opmode(sc);
2302 1.1 christos
2303 1.1 christos AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
2304 1.1 christos AR_WRITE(sc, AR_BSSMSKU, 0xffff);
2305 1.1 christos
2306 1.1 christos /* Restore previous antenna. */
2307 1.1 christos AR_WRITE(sc, AR_DEF_ANTENNA, def_ant);
2308 1.1 christos
2309 1.1 christos AR_WRITE(sc, AR_BSS_ID0, 0);
2310 1.1 christos AR_WRITE(sc, AR_BSS_ID1, 0);
2311 1.1 christos
2312 1.1 christos AR_WRITE(sc, AR_ISR, 0xffffffff);
2313 1.1 christos
2314 1.1 christos AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
2315 1.1 christos
2316 1.1 christos if ((error = ops->set_synth(sc, curchan, extchan)) != 0) {
2317 1.1 christos aprint_error_dev(sc->sc_dev, "could not set channel\n");
2318 1.1 christos return error;
2319 1.1 christos }
2320 1.1 christos sc->sc_curchan = curchan;
2321 1.1 christos sc->sc_curchanext = extchan;
2322 1.1 christos
2323 1.1 christos for (i = 0; i < AR_NUM_DCU; i++)
2324 1.1 christos AR_WRITE(sc, AR_DQCUMASK(i), 1 << i);
2325 1.1 christos
2326 1.1 christos athn_init_tx_queues(sc);
2327 1.1 christos
2328 1.1 christos /* Initialize interrupt mask. */
2329 1.1 christos sc->sc_imask =
2330 1.1 christos AR_IMR_TXDESC | AR_IMR_TXEOL |
2331 1.1 christos AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
2332 1.1 christos AR_IMR_RXMINTR | AR_IMR_RXINTM |
2333 1.1 christos AR_IMR_GENTMR | AR_IMR_BCNMISC;
2334 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc))
2335 1.1 christos sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
2336 1.1 christos #ifndef IEEE80211_STA_ONLY
2337 1.1 christos if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP)
2338 1.1 christos sc->sc_imask |= AR_IMR_MIB;
2339 1.1 christos #endif
2340 1.1 christos AR_WRITE(sc, AR_IMR, sc->sc_imask);
2341 1.1 christos AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
2342 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2343 1.1 christos sc->sc_isync = AR_INTR_SYNC_DEFAULT;
2344 1.1 christos if (sc->sc_flags & ATHN_FLAG_RFSILENT)
2345 1.1 christos sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin);
2346 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
2347 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2348 1.1 christos if (AR_SREV_9380_10_OR_LATER(sc)) {
2349 1.1 christos AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
2350 1.1 christos AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
2351 1.1 christos AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
2352 1.1 christos AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
2353 1.1 christos }
2354 1.1 christos
2355 1.1 christos athn_init_qos(sc);
2356 1.1 christos
2357 1.1 christos AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA);
2358 1.1 christos
2359 1.1 christos if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
2360 1.1 christos ar9287_1_3_setup_async_fifo(sc);
2361 1.1 christos
2362 1.1 christos /* Disable sequence number generation in hardware. */
2363 1.1 christos AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2364 1.1 christos
2365 1.1 christos athn_init_dma(sc);
2366 1.1 christos
2367 1.1 christos /* Program observation bus to see MAC interrupts. */
2368 1.1 christos AR_WRITE(sc, sc->sc_obs_off, 8);
2369 1.1 christos
2370 1.1 christos /* Setup Rx interrupt mitigation. */
2371 1.1 christos AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
2372 1.1 christos
2373 1.1 christos ops->init_baseband(sc);
2374 1.1 christos
2375 1.1 christos if ((error = athn_init_calib(sc, curchan, extchan)) != 0) {
2376 1.1 christos aprint_error_dev(sc->sc_dev,
2377 1.1 christos "could not initialize calibration\n");
2378 1.1 christos return error;
2379 1.1 christos }
2380 1.1 christos
2381 1.1 christos ops->set_rxchains(sc);
2382 1.1 christos
2383 1.1 christos AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
2384 1.1 christos
2385 1.1 christos if (sc->sc_flags & ATHN_FLAG_USB) {
2386 1.1 christos if (AR_SREV_9271(sc))
2387 1.1 christos AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2388 1.1 christos else
2389 1.1 christos AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2390 1.1 christos }
2391 1.1 christos #if BYTE_ORDER == BIG_ENDIAN
2392 1.1 christos else {
2393 1.1 christos /* Default is LE, turn on swapping for BE. */
2394 1.1 christos AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2395 1.1 christos }
2396 1.1 christos #endif
2397 1.1 christos AR_WRITE_BARRIER(sc);
2398 1.1 christos
2399 1.1 christos return 0;
2400 1.1 christos }
2401 1.1 christos
2402 1.1 christos Static struct ieee80211_node *
2403 1.1 christos athn_node_alloc(struct ieee80211_node_table *ntp)
2404 1.1 christos {
2405 1.1 christos
2406 1.1 christos return malloc(sizeof(struct athn_node), M_DEVBUF,
2407 1.1 christos M_NOWAIT | M_ZERO);
2408 1.1 christos }
2409 1.1 christos
2410 1.1 christos Static void
2411 1.1 christos athn_newassoc(struct ieee80211_node *ni, int isnew)
2412 1.1 christos {
2413 1.1 christos struct ieee80211com *ic = ni->ni_ic;
2414 1.1 christos struct athn_softc *sc = ic->ic_ifp->if_softc;
2415 1.1 christos struct athn_node *an = (void *)ni;
2416 1.1 christos struct ieee80211_rateset *rs = &ni->ni_rates;
2417 1.1 christos uint8_t rate;
2418 1.1 christos int ridx, i, j;
2419 1.1 christos
2420 1.1 christos ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn);
2421 1.1 christos /* Start at lowest available bit-rate, AMRR will raise. */
2422 1.1 christos ni->ni_txrate = 0;
2423 1.1 christos
2424 1.1 christos for (i = 0; i < rs->rs_nrates; i++) {
2425 1.1 christos rate = rs->rs_rates[i] & IEEE80211_RATE_VAL;
2426 1.1 christos
2427 1.1 christos /* Map 802.11 rate to HW rate index. */
2428 1.1 christos for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
2429 1.1 christos if (athn_rates[ridx].rate == rate)
2430 1.1 christos break;
2431 1.1 christos an->ridx[i] = ridx;
2432 1.1 christos DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx);
2433 1.1 christos
2434 1.1 christos /* Compute fallback rate for retries. */
2435 1.1 christos an->fallback[i] = i;
2436 1.1 christos for (j = i - 1; j >= 0; j--) {
2437 1.1 christos if (athn_rates[an->ridx[j]].phy ==
2438 1.1 christos athn_rates[an->ridx[i]].phy) {
2439 1.1 christos an->fallback[i] = j;
2440 1.1 christos break;
2441 1.1 christos }
2442 1.1 christos }
2443 1.1 christos DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n",
2444 1.1 christos i, an->fallback[i]);
2445 1.1 christos }
2446 1.1 christos }
2447 1.1 christos
2448 1.1 christos Static int
2449 1.1 christos athn_media_change(struct ifnet *ifp)
2450 1.1 christos {
2451 1.1 christos struct athn_softc *sc = ifp->if_softc;
2452 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2453 1.1 christos uint8_t rate, ridx;
2454 1.1 christos int error;
2455 1.1 christos
2456 1.1 christos error = ieee80211_media_change(ifp);
2457 1.1 christos if (error != ENETRESET)
2458 1.1 christos return error;
2459 1.1 christos
2460 1.1 christos if (ic->ic_fixed_rate != -1) {
2461 1.1 christos rate = ic->ic_sup_rates[ic->ic_curmode].
2462 1.1 christos rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL;
2463 1.1 christos /* Map 802.11 rate to HW rate index. */
2464 1.1 christos for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
2465 1.1 christos if (athn_rates[ridx].rate == rate)
2466 1.1 christos break;
2467 1.1 christos sc->sc_fixed_ridx = ridx;
2468 1.1 christos }
2469 1.1 christos if (IS_UP_AND_RUNNING(ifp)) {
2470 1.1 christos athn_stop(ifp, 0);
2471 1.1 christos error = athn_init(ifp);
2472 1.1 christos }
2473 1.1 christos return error;
2474 1.1 christos }
2475 1.1 christos
2476 1.1 christos Static void
2477 1.1 christos athn_next_scan(void *arg)
2478 1.1 christos {
2479 1.1 christos struct athn_softc *sc = arg;
2480 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2481 1.1 christos int s;
2482 1.1 christos
2483 1.1 christos s = splnet();
2484 1.1 christos if (ic->ic_state == IEEE80211_S_SCAN)
2485 1.1 christos ieee80211_next_scan(ic);
2486 1.1 christos splx(s);
2487 1.1 christos }
2488 1.1 christos
2489 1.1 christos Static int
2490 1.1 christos athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2491 1.1 christos {
2492 1.1 christos struct ifnet *ifp = ic->ic_ifp;
2493 1.1 christos struct athn_softc *sc = ifp->if_softc;
2494 1.1 christos uint32_t reg;
2495 1.1 christos int error;
2496 1.1 christos
2497 1.1 christos callout_stop(&sc->sc_calib_to);
2498 1.1 christos
2499 1.1 christos switch (nstate) {
2500 1.1 christos case IEEE80211_S_INIT:
2501 1.1 christos athn_set_led(sc, 0);
2502 1.1 christos break;
2503 1.1 christos case IEEE80211_S_SCAN:
2504 1.1 christos /* Make the LED blink while scanning. */
2505 1.1 christos athn_set_led(sc, !sc->sc_led_state);
2506 1.1 christos error = athn_switch_chan(sc, ic->ic_curchan, NULL);
2507 1.1 christos if (error != 0)
2508 1.1 christos return error;
2509 1.1 christos callout_schedule(&sc->sc_scan_to, hz / 5);
2510 1.1 christos break;
2511 1.1 christos case IEEE80211_S_AUTH:
2512 1.1 christos athn_set_led(sc, 0);
2513 1.1 christos error = athn_switch_chan(sc, ic->ic_curchan, NULL);
2514 1.1 christos if (error != 0)
2515 1.1 christos return error;
2516 1.1 christos break;
2517 1.1 christos case IEEE80211_S_ASSOC:
2518 1.1 christos break;
2519 1.1 christos case IEEE80211_S_RUN:
2520 1.1 christos athn_set_led(sc, 1);
2521 1.1 christos
2522 1.1 christos if (ic->ic_opmode == IEEE80211_M_MONITOR)
2523 1.1 christos break;
2524 1.1 christos
2525 1.1 christos /* Fake a join to initialize the Tx rate. */
2526 1.1 christos athn_newassoc(ic->ic_bss, 1);
2527 1.1 christos
2528 1.1 christos athn_set_bss(sc, ic->ic_bss);
2529 1.1 christos athn_disable_interrupts(sc);
2530 1.1 christos #ifndef IEEE80211_STA_ONLY
2531 1.1 christos if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2532 1.1 christos athn_set_hostap_timers(sc);
2533 1.1 christos /* Enable software beacon alert interrupts. */
2534 1.1 christos sc->sc_imask |= AR_IMR_SWBA;
2535 1.19 msaitoh } else
2536 1.1 christos #endif
2537 1.1 christos {
2538 1.1 christos athn_set_sta_timers(sc);
2539 1.1 christos /* Enable beacon miss interrupts. */
2540 1.1 christos sc->sc_imask |= AR_IMR_BMISS;
2541 1.1 christos
2542 1.1 christos /* Stop receiving beacons from other BSS. */
2543 1.1 christos reg = AR_READ(sc, AR_RX_FILTER);
2544 1.1 christos reg = (reg & ~AR_RX_FILTER_BEACON) |
2545 1.1 christos AR_RX_FILTER_MYBEACON;
2546 1.1 christos AR_WRITE(sc, AR_RX_FILTER, reg);
2547 1.1 christos AR_WRITE_BARRIER(sc);
2548 1.1 christos }
2549 1.1 christos athn_enable_interrupts(sc);
2550 1.1 christos
2551 1.1 christos if (sc->sc_sup_calib_mask != 0) {
2552 1.1 christos memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
2553 1.1 christos sc->sc_cur_calib_mask = sc->sc_sup_calib_mask;
2554 1.1 christos /* ops->do_calib(sc); */
2555 1.1 christos }
2556 1.1 christos /* XXX Start ANI. */
2557 1.1 christos
2558 1.1 christos callout_schedule(&sc->sc_calib_to, hz / 2);
2559 1.1 christos break;
2560 1.1 christos }
2561 1.1 christos
2562 1.1 christos return sc->sc_newstate(ic, nstate, arg);
2563 1.1 christos }
2564 1.1 christos
2565 1.1 christos #ifdef notyet_edca
2566 1.1 christos PUBLIC void
2567 1.1 christos athn_updateedca(struct ieee80211com *ic)
2568 1.1 christos {
2569 1.1 christos #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
2570 1.1 christos struct athn_softc *sc = ic->ic_ifp->if_softc;
2571 1.1 christos const struct ieee80211_edca_ac_params *ac;
2572 1.1 christos int aci, qid;
2573 1.1 christos
2574 1.1 christos for (aci = 0; aci < EDCA_NUM_AC; aci++) {
2575 1.1 christos ac = &ic->ic_edca_ac[aci];
2576 1.1 christos qid = athn_ac2qid[aci];
2577 1.1 christos
2578 1.1 christos AR_WRITE(sc, AR_DLCL_IFS(qid),
2579 1.1 christos SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |
2580 1.1 christos SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |
2581 1.1 christos SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn));
2582 1.1 christos if (ac->ac_txoplimit != 0) {
2583 1.1 christos AR_WRITE(sc, AR_DCHNTIME(qid),
2584 1.1 christos SM(AR_D_CHNTIME_DUR,
2585 1.1 christos IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) |
2586 1.1 christos AR_D_CHNTIME_EN);
2587 1.19 msaitoh } else
2588 1.1 christos AR_WRITE(sc, AR_DCHNTIME(qid), 0);
2589 1.1 christos }
2590 1.1 christos AR_WRITE_BARRIER(sc);
2591 1.1 christos #undef ATHN_EXP2
2592 1.1 christos }
2593 1.1 christos #endif /* notyet_edca */
2594 1.1 christos
2595 1.1 christos Static int
2596 1.1 christos athn_clock_rate(struct athn_softc *sc)
2597 1.1 christos {
2598 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2599 1.1 christos int clockrate; /* MHz. */
2600 1.1 christos
2601 1.1 christos if (ic->ic_curmode == IEEE80211_MODE_11A) {
2602 1.1 christos if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)
2603 1.1 christos clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM;
2604 1.1 christos else
2605 1.1 christos clockrate = AR_CLOCK_RATE_5GHZ_OFDM;
2606 1.19 msaitoh } else if (ic->ic_curmode == IEEE80211_MODE_11B) {
2607 1.1 christos clockrate = AR_CLOCK_RATE_CCK;
2608 1.19 msaitoh } else
2609 1.1 christos clockrate = AR_CLOCK_RATE_2GHZ_OFDM;
2610 1.1 christos #ifndef IEEE80211_NO_HT
2611 1.1 christos if (sc->sc_curchanext != NULL)
2612 1.1 christos clockrate *= 2;
2613 1.1 christos #endif
2614 1.1 christos return clockrate;
2615 1.1 christos }
2616 1.1 christos
2617 1.1 christos PUBLIC void
2618 1.1 christos athn_updateslot(struct ifnet *ifp)
2619 1.1 christos {
2620 1.1 christos struct athn_softc *sc = ifp->if_softc;
2621 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2622 1.1 christos int slot;
2623 1.1 christos
2624 1.1 christos slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2625 1.1 christos AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
2626 1.1 christos AR_WRITE_BARRIER(sc);
2627 1.1 christos }
2628 1.1 christos
2629 1.1 christos Static void
2630 1.1 christos athn_start(struct ifnet *ifp)
2631 1.1 christos {
2632 1.1 christos struct athn_softc *sc = ifp->if_softc;
2633 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2634 1.1 christos struct ether_header *eh;
2635 1.1 christos struct ieee80211_node *ni;
2636 1.1 christos struct mbuf *m;
2637 1.1 christos
2638 1.4 martin if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING
2639 1.4 martin || !device_is_active(sc->sc_dev))
2640 1.1 christos return;
2641 1.1 christos
2642 1.1 christos for (;;) {
2643 1.1 christos if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) {
2644 1.1 christos ifp->if_flags |= IFF_OACTIVE;
2645 1.1 christos break;
2646 1.1 christos }
2647 1.1 christos /* Send pending management frames first. */
2648 1.1 christos IF_DEQUEUE(&ic->ic_mgtq, m);
2649 1.1 christos if (m != NULL) {
2650 1.13 ozaki ni = M_GETCTX(m, struct ieee80211_node *);
2651 1.1 christos goto sendit;
2652 1.1 christos }
2653 1.1 christos if (ic->ic_state != IEEE80211_S_RUN)
2654 1.1 christos break;
2655 1.1 christos
2656 1.1 christos /* Encapsulate and send data frames. */
2657 1.1 christos IFQ_DEQUEUE(&ifp->if_snd, m);
2658 1.1 christos if (m == NULL)
2659 1.1 christos break;
2660 1.1 christos
2661 1.1 christos if (m->m_len < (int)sizeof(*eh) &&
2662 1.1 christos (m = m_pullup(m, sizeof(*eh))) == NULL) {
2663 1.23 thorpej if_statinc(ifp, if_oerrors);
2664 1.1 christos continue;
2665 1.1 christos }
2666 1.1 christos eh = mtod(m, struct ether_header *);
2667 1.1 christos ni = ieee80211_find_txnode(ic, eh->ether_dhost);
2668 1.1 christos if (ni == NULL) {
2669 1.1 christos m_freem(m);
2670 1.23 thorpej if_statinc(ifp, if_oerrors);
2671 1.1 christos continue;
2672 1.1 christos }
2673 1.1 christos
2674 1.18 msaitoh bpf_mtap(ifp, m, BPF_D_OUT);
2675 1.1 christos
2676 1.1 christos if ((m = ieee80211_encap(ic, m, ni)) == NULL)
2677 1.1 christos continue;
2678 1.1 christos sendit:
2679 1.18 msaitoh bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT);
2680 1.1 christos
2681 1.1 christos if (sc->sc_ops.tx(sc, m, ni, 0) != 0) {
2682 1.1 christos ieee80211_free_node(ni);
2683 1.23 thorpej if_statinc(ifp, if_oerrors);
2684 1.1 christos continue;
2685 1.1 christos }
2686 1.1 christos
2687 1.1 christos sc->sc_tx_timer = 5;
2688 1.1 christos ifp->if_timer = 1;
2689 1.1 christos }
2690 1.1 christos }
2691 1.1 christos
2692 1.1 christos Static void
2693 1.1 christos athn_watchdog(struct ifnet *ifp)
2694 1.1 christos {
2695 1.1 christos struct athn_softc *sc = ifp->if_softc;
2696 1.1 christos
2697 1.1 christos ifp->if_timer = 0;
2698 1.1 christos
2699 1.1 christos if (sc->sc_tx_timer > 0) {
2700 1.1 christos if (--sc->sc_tx_timer == 0) {
2701 1.1 christos aprint_error_dev(sc->sc_dev, "device timeout\n");
2702 1.6 martin /* see athn_init, no need to call athn_stop here */
2703 1.6 martin /* athn_stop(ifp, 0); */
2704 1.1 christos (void)athn_init(ifp);
2705 1.23 thorpej if_statinc(ifp, if_oerrors);
2706 1.1 christos return;
2707 1.1 christos }
2708 1.1 christos ifp->if_timer = 1;
2709 1.1 christos }
2710 1.1 christos ieee80211_watchdog(&sc->sc_ic);
2711 1.1 christos }
2712 1.1 christos
2713 1.1 christos Static void
2714 1.1 christos athn_set_multi(struct athn_softc *sc)
2715 1.1 christos {
2716 1.20 msaitoh struct ethercom *ec = &sc->sc_ec;
2717 1.20 msaitoh struct ifnet *ifp = &ec->ec_if;
2718 1.1 christos struct ether_multi *enm;
2719 1.1 christos struct ether_multistep step;
2720 1.1 christos const uint8_t *addr;
2721 1.1 christos uint32_t val, lo, hi;
2722 1.1 christos uint8_t bit;
2723 1.1 christos
2724 1.1 christos if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2725 1.1 christos lo = hi = 0xffffffff;
2726 1.24 mlelstv goto done2;
2727 1.1 christos }
2728 1.1 christos lo = hi = 0;
2729 1.21 msaitoh ETHER_LOCK(ec);
2730 1.20 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
2731 1.1 christos while (enm != NULL) {
2732 1.1 christos if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) {
2733 1.1 christos ifp->if_flags |= IFF_ALLMULTI;
2734 1.1 christos lo = hi = 0xffffffff;
2735 1.1 christos goto done;
2736 1.1 christos }
2737 1.1 christos addr = enm->enm_addrlo;
2738 1.1 christos /* Calculate the XOR value of all eight 6-bit words. */
2739 1.1 christos val = addr[0] | addr[1] << 8 | addr[2] << 16;
2740 1.1 christos bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2741 1.1 christos val = addr[3] | addr[4] << 8 | addr[5] << 16;
2742 1.1 christos bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2743 1.1 christos bit &= 0x3f;
2744 1.1 christos if (bit < 32)
2745 1.1 christos lo |= 1 << bit;
2746 1.1 christos else
2747 1.1 christos hi |= 1 << (bit - 32);
2748 1.1 christos ETHER_NEXT_MULTI(step, enm);
2749 1.1 christos }
2750 1.1 christos done:
2751 1.21 msaitoh ETHER_UNLOCK(ec);
2752 1.24 mlelstv done2:
2753 1.1 christos AR_WRITE(sc, AR_MCAST_FIL0, lo);
2754 1.1 christos AR_WRITE(sc, AR_MCAST_FIL1, hi);
2755 1.1 christos AR_WRITE_BARRIER(sc);
2756 1.1 christos }
2757 1.1 christos
2758 1.1 christos Static int
2759 1.1 christos athn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2760 1.1 christos {
2761 1.1 christos struct athn_softc *sc = ifp->if_softc;
2762 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2763 1.1 christos int s, error = 0;
2764 1.1 christos
2765 1.1 christos s = splnet();
2766 1.1 christos
2767 1.1 christos switch (cmd) {
2768 1.1 christos case SIOCSIFFLAGS:
2769 1.1 christos if ((error = ifioctl_common(ifp, cmd, data)) != 0)
2770 1.1 christos break;
2771 1.1 christos
2772 1.1 christos switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
2773 1.1 christos case IFF_UP | IFF_RUNNING:
2774 1.1 christos #ifdef notyet
2775 1.1 christos if (((ifp->if_flags ^ sc->sc_if_flags) &
2776 1.1 christos (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2777 1.1 christos /* XXX: setup multi */
2778 1.1 christos #endif
2779 1.1 christos break;
2780 1.1 christos case IFF_UP:
2781 1.1 christos athn_init(ifp);
2782 1.1 christos break;
2783 1.1 christos
2784 1.1 christos case IFF_RUNNING:
2785 1.1 christos athn_stop(ifp, 1);
2786 1.1 christos break;
2787 1.1 christos case 0:
2788 1.1 christos default:
2789 1.1 christos break;
2790 1.1 christos }
2791 1.1 christos sc->sc_if_flags = ifp->if_flags;
2792 1.1 christos break;
2793 1.1 christos
2794 1.1 christos case SIOCADDMULTI:
2795 1.1 christos case SIOCDELMULTI:
2796 1.1 christos if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
2797 1.1 christos /* setup multicast filter, etc */
2798 1.1 christos athn_set_multi(sc);
2799 1.1 christos error = 0;
2800 1.1 christos }
2801 1.1 christos break;
2802 1.1 christos
2803 1.1 christos case SIOCS80211CHANNEL:
2804 1.1 christos error = ieee80211_ioctl(ic, cmd, data);
2805 1.1 christos if (error == ENETRESET &&
2806 1.1 christos ic->ic_opmode == IEEE80211_M_MONITOR) {
2807 1.1 christos if (IS_UP_AND_RUNNING(ifp))
2808 1.1 christos athn_switch_chan(sc, ic->ic_curchan, NULL);
2809 1.1 christos error = 0;
2810 1.1 christos }
2811 1.1 christos break;
2812 1.1 christos
2813 1.1 christos default:
2814 1.1 christos error = ieee80211_ioctl(ic, cmd, data);
2815 1.1 christos }
2816 1.1 christos
2817 1.1 christos if (error == ENETRESET) {
2818 1.1 christos error = 0;
2819 1.1 christos if (IS_UP_AND_RUNNING(ifp) &&
2820 1.1 christos ic->ic_roaming != IEEE80211_ROAMING_MANUAL) {
2821 1.1 christos athn_stop(ifp, 0);
2822 1.1 christos error = athn_init(ifp);
2823 1.1 christos }
2824 1.1 christos }
2825 1.1 christos
2826 1.1 christos splx(s);
2827 1.1 christos return error;
2828 1.1 christos }
2829 1.1 christos
2830 1.1 christos Static int
2831 1.1 christos athn_init(struct ifnet *ifp)
2832 1.1 christos {
2833 1.1 christos struct athn_softc *sc = ifp->if_softc;
2834 1.1 christos struct athn_ops *ops = &sc->sc_ops;
2835 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2836 1.1 christos struct ieee80211_channel *curchan, *extchan;
2837 1.1 christos size_t i;
2838 1.1 christos int error;
2839 1.1 christos
2840 1.4 martin KASSERT(!cpu_intr_p());
2841 1.4 martin
2842 1.4 martin if (device_is_active(sc->sc_dev)) {
2843 1.6 martin athn_stop(ifp, 0); /* see athn_watchdog() */
2844 1.4 martin } else {
2845 1.4 martin short flags = ifp->if_flags;
2846 1.4 martin ifp->if_flags &= ~IFF_UP;
2847 1.4 martin /* avoid recursion in athn_resume */
2848 1.4 martin if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) ||
2849 1.4 martin !device_is_active(sc->sc_dev)) {
2850 1.12 jakllsch printf("%s: failed to power up device\n",
2851 1.12 jakllsch device_xname(sc->sc_dev));
2852 1.4 martin return 0;
2853 1.4 martin }
2854 1.4 martin ifp->if_flags = flags;
2855 1.4 martin }
2856 1.1 christos
2857 1.1 christos curchan = ic->ic_curchan;
2858 1.1 christos extchan = NULL;
2859 1.1 christos
2860 1.1 christos /* In case a new MAC address has been configured. */
2861 1.1 christos IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
2862 1.1 christos
2863 1.1 christos #ifdef openbsd_power_management
2864 1.1 christos /* For CardBus, power on the socket. */
2865 1.1 christos if (sc->sc_enable != NULL) {
2866 1.1 christos if ((error = sc->sc_enable(sc)) != 0) {
2867 1.1 christos aprint_error_dev(sc->sc_dev,
2868 1.1 christos "could not enable device\n");
2869 1.1 christos goto fail;
2870 1.1 christos }
2871 1.1 christos if ((error = athn_reset_power_on(sc)) != 0) {
2872 1.1 christos aprint_error_dev(sc->sc_dev,
2873 1.1 christos "could not power on device\n");
2874 1.1 christos goto fail;
2875 1.1 christos }
2876 1.1 christos }
2877 1.1 christos #endif
2878 1.1 christos if (!(sc->sc_flags & ATHN_FLAG_PCIE))
2879 1.1 christos athn_config_nonpcie(sc);
2880 1.1 christos else
2881 1.1 christos athn_config_pcie(sc);
2882 1.1 christos
2883 1.1 christos /* Reset HW key cache entries. */
2884 1.1 christos for (i = 0; i < sc->sc_kc_entries; i++)
2885 1.1 christos athn_reset_key(sc, i);
2886 1.1 christos
2887 1.1 christos ops->enable_antenna_diversity(sc);
2888 1.1 christos
2889 1.1 christos #ifdef ATHN_BT_COEXISTENCE
2890 1.1 christos /* Configure bluetooth coexistence for combo chips. */
2891 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX)
2892 1.1 christos athn_btcoex_init(sc);
2893 1.1 christos #endif
2894 1.1 christos
2895 1.1 christos /* Configure LED. */
2896 1.1 christos athn_led_init(sc);
2897 1.1 christos
2898 1.1 christos /* Configure hardware radio switch. */
2899 1.1 christos if (sc->sc_flags & ATHN_FLAG_RFSILENT)
2900 1.1 christos ops->rfsilent_init(sc);
2901 1.1 christos
2902 1.1 christos if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) {
2903 1.1 christos aprint_error_dev(sc->sc_dev,
2904 1.1 christos "unable to reset hardware; reset status %d\n", error);
2905 1.1 christos goto fail;
2906 1.1 christos }
2907 1.1 christos
2908 1.1 christos /* Enable Rx. */
2909 1.1 christos athn_rx_start(sc);
2910 1.1 christos
2911 1.1 christos /* Enable interrupts. */
2912 1.1 christos athn_enable_interrupts(sc);
2913 1.1 christos
2914 1.1 christos #ifdef ATHN_BT_COEXISTENCE
2915 1.1 christos /* Enable bluetooth coexistence for combo chips. */
2916 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX)
2917 1.1 christos athn_btcoex_enable(sc);
2918 1.1 christos #endif
2919 1.1 christos
2920 1.1 christos ifp->if_flags &= ~IFF_OACTIVE;
2921 1.1 christos ifp->if_flags |= IFF_RUNNING;
2922 1.1 christos
2923 1.1 christos #ifdef notyet
2924 1.1 christos if (ic->ic_flags & IEEE80211_F_WEPON) {
2925 1.1 christos /* Configure WEP keys. */
2926 1.1 christos for (i = 0; i < IEEE80211_WEP_NKID; i++)
2927 1.1 christos athn_set_key(ic, NULL, &ic->ic_nw_keys[i]);
2928 1.1 christos }
2929 1.1 christos #endif
2930 1.1 christos if (ic->ic_opmode == IEEE80211_M_MONITOR)
2931 1.1 christos ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2932 1.1 christos else
2933 1.1 christos ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2934 1.1 christos
2935 1.1 christos return 0;
2936 1.1 christos fail:
2937 1.1 christos athn_stop(ifp, 1);
2938 1.1 christos return error;
2939 1.1 christos }
2940 1.1 christos
2941 1.1 christos PUBLIC void
2942 1.1 christos athn_stop(struct ifnet *ifp, int disable)
2943 1.1 christos {
2944 1.1 christos struct athn_softc *sc = ifp->if_softc;
2945 1.1 christos struct ieee80211com *ic = &sc->sc_ic;
2946 1.1 christos int qid;
2947 1.1 christos
2948 1.1 christos ifp->if_timer = sc->sc_tx_timer = 0;
2949 1.1 christos ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2950 1.1 christos
2951 1.1 christos callout_stop(&sc->sc_scan_to);
2952 1.1 christos /* In case we were scanning, release the scan "lock". */
2953 1.1 christos // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */
2954 1.1 christos
2955 1.1 christos ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2956 1.1 christos
2957 1.1 christos #ifdef ATHN_BT_COEXISTENCE
2958 1.1 christos /* Disable bluetooth coexistence for combo chips. */
2959 1.1 christos if (sc->sc_flags & ATHN_FLAG_BTCOEX)
2960 1.1 christos athn_btcoex_disable(sc);
2961 1.1 christos #endif
2962 1.1 christos
2963 1.1 christos /* Disable interrupts. */
2964 1.1 christos athn_disable_interrupts(sc);
2965 1.1 christos /* Acknowledge interrupts (avoids interrupt storms). */
2966 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2967 1.1 christos AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2968 1.1 christos
2969 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
2970 1.1 christos athn_stop_tx_dma(sc, qid);
2971 1.1 christos /* XXX call athn_hw_reset if Tx still pending? */
2972 1.1 christos for (qid = 0; qid < ATHN_QID_COUNT; qid++)
2973 1.1 christos athn_tx_reclaim(sc, qid);
2974 1.1 christos
2975 1.1 christos /* Stop Rx. */
2976 1.1 christos AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
2977 1.1 christos AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
2978 1.1 christos AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
2979 1.1 christos AR_WRITE(sc, AR_FILT_OFDM, 0);
2980 1.1 christos AR_WRITE(sc, AR_FILT_CCK, 0);
2981 1.1 christos AR_WRITE_BARRIER(sc);
2982 1.1 christos athn_set_rxfilter(sc, 0);
2983 1.1 christos athn_stop_rx_dma(sc);
2984 1.1 christos
2985 1.1 christos athn_reset(sc, 0);
2986 1.1 christos athn_init_pll(sc, NULL);
2987 1.1 christos athn_set_power_awake(sc);
2988 1.1 christos athn_reset(sc, 1);
2989 1.1 christos athn_init_pll(sc, NULL);
2990 1.1 christos
2991 1.1 christos athn_set_power_sleep(sc);
2992 1.1 christos
2993 1.1 christos #if 0 /* XXX: shouldn't the pmf stuff take care of this? */
2994 1.1 christos /* For CardBus, power down the socket. */
2995 1.1 christos if (disable && sc->sc_disable != NULL)
2996 1.1 christos sc->sc_disable(sc);
2997 1.1 christos #endif
2998 1.1 christos if (disable)
2999 1.1 christos pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual);
3000 1.1 christos }
3001 1.1 christos
3002 1.3 martin Static void
3003 1.3 martin athn_pmf_wlan_off(device_t self)
3004 1.3 martin {
3005 1.3 martin struct athn_softc *sc = device_private(self);
3006 1.3 martin struct ifnet *ifp = &sc->sc_if;
3007 1.3 martin
3008 1.3 martin /* Turn the interface down. */
3009 1.3 martin ifp->if_flags &= ~IFF_UP;
3010 1.3 martin athn_stop(ifp, 1);
3011 1.3 martin }
3012 1.3 martin
3013 1.1 christos PUBLIC void
3014 1.1 christos athn_suspend(struct athn_softc *sc)
3015 1.1 christos {
3016 1.1 christos struct ifnet *ifp = &sc->sc_if;
3017 1.1 christos
3018 1.1 christos if (ifp->if_flags & IFF_RUNNING)
3019 1.1 christos athn_stop(ifp, 1);
3020 1.1 christos }
3021 1.1 christos
3022 1.4 martin PUBLIC bool
3023 1.1 christos athn_resume(struct athn_softc *sc)
3024 1.1 christos {
3025 1.1 christos struct ifnet *ifp = &sc->sc_if;
3026 1.1 christos
3027 1.1 christos if (ifp->if_flags & IFF_UP)
3028 1.4 martin athn_init(ifp);
3029 1.4 martin
3030 1.4 martin return true;
3031 1.1 christos }
3032