athn.c revision 1.5.4.3
1 1.5.4.2 tls /* $NetBSD: athn.c,v 1.5.4.3 2014/08/20 00:03:37 tls Exp $ */ 2 1.5.4.3 tls /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 1.5.4.2 tls 4 1.5.4.2 tls /*- 5 1.5.4.2 tls * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.5.4.2 tls * Copyright (c) 2008-2010 Atheros Communications Inc. 7 1.5.4.2 tls * 8 1.5.4.2 tls * Permission to use, copy, modify, and/or distribute this software for any 9 1.5.4.2 tls * purpose with or without fee is hereby granted, provided that the above 10 1.5.4.2 tls * copyright notice and this permission notice appear in all copies. 11 1.5.4.2 tls * 12 1.5.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.5.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.5.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.5.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.5.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.5.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.5.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.5.4.2 tls */ 20 1.5.4.2 tls 21 1.5.4.2 tls /* 22 1.5.4.2 tls * Driver for Atheros 802.11a/g/n chipsets. 23 1.5.4.2 tls */ 24 1.5.4.2 tls 25 1.5.4.2 tls #include <sys/cdefs.h> 26 1.5.4.2 tls __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.5.4.3 2014/08/20 00:03:37 tls Exp $"); 27 1.5.4.2 tls 28 1.5.4.2 tls #ifndef _MODULE 29 1.5.4.2 tls #include "athn_usb.h" /* for NATHN_USB */ 30 1.5.4.2 tls #endif 31 1.5.4.2 tls 32 1.5.4.2 tls #include <sys/param.h> 33 1.5.4.2 tls #include <sys/sockio.h> 34 1.5.4.2 tls #include <sys/mbuf.h> 35 1.5.4.2 tls #include <sys/kernel.h> 36 1.5.4.2 tls #include <sys/socket.h> 37 1.5.4.2 tls #include <sys/systm.h> 38 1.5.4.2 tls #include <sys/malloc.h> 39 1.5.4.2 tls #include <sys/queue.h> 40 1.5.4.2 tls #include <sys/callout.h> 41 1.5.4.2 tls #include <sys/conf.h> 42 1.5.4.2 tls #include <sys/cpu.h> 43 1.5.4.2 tls #include <sys/device.h> 44 1.5.4.2 tls 45 1.5.4.2 tls #include <sys/bus.h> 46 1.5.4.2 tls #include <sys/endian.h> 47 1.5.4.2 tls #include <sys/intr.h> 48 1.5.4.2 tls 49 1.5.4.2 tls #include <net/bpf.h> 50 1.5.4.2 tls #include <net/if.h> 51 1.5.4.2 tls #include <net/if_arp.h> 52 1.5.4.2 tls #include <net/if_dl.h> 53 1.5.4.2 tls #include <net/if_ether.h> 54 1.5.4.2 tls #include <net/if_media.h> 55 1.5.4.2 tls #include <net/if_types.h> 56 1.5.4.2 tls 57 1.5.4.2 tls #include <netinet/in.h> 58 1.5.4.2 tls #include <netinet/in_systm.h> 59 1.5.4.2 tls #include <netinet/in_var.h> 60 1.5.4.2 tls #include <netinet/ip.h> 61 1.5.4.2 tls 62 1.5.4.2 tls #include <net80211/ieee80211_var.h> 63 1.5.4.2 tls #include <net80211/ieee80211_amrr.h> 64 1.5.4.2 tls #include <net80211/ieee80211_radiotap.h> 65 1.5.4.2 tls 66 1.5.4.2 tls #include <dev/ic/athnreg.h> 67 1.5.4.2 tls #include <dev/ic/athnvar.h> 68 1.5.4.2 tls #include <dev/ic/arn5008.h> 69 1.5.4.2 tls #include <dev/ic/arn5416.h> 70 1.5.4.2 tls #include <dev/ic/arn9003.h> 71 1.5.4.2 tls #include <dev/ic/arn9280.h> 72 1.5.4.2 tls #include <dev/ic/arn9285.h> 73 1.5.4.2 tls #include <dev/ic/arn9287.h> 74 1.5.4.2 tls #include <dev/ic/arn9380.h> 75 1.5.4.2 tls 76 1.5.4.2 tls #define Static static 77 1.5.4.2 tls 78 1.5.4.2 tls #define IS_UP_AND_RUNNING(ifp) \ 79 1.5.4.2 tls (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 1.5.4.2 tls 81 1.5.4.2 tls #ifdef ATHN_DEBUG 82 1.5.4.2 tls int athn_debug = 0; 83 1.5.4.2 tls #endif 84 1.5.4.2 tls 85 1.5.4.2 tls Static int athn_clock_rate(struct athn_softc *); 86 1.5.4.2 tls Static const char * 87 1.5.4.2 tls athn_get_mac_name(struct athn_softc *); 88 1.5.4.2 tls Static const char * 89 1.5.4.2 tls athn_get_rf_name(struct athn_softc *); 90 1.5.4.2 tls Static int athn_init(struct ifnet *); 91 1.5.4.2 tls Static int athn_init_calib(struct athn_softc *, 92 1.5.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 93 1.5.4.2 tls Static int athn_ioctl(struct ifnet *, u_long, void *); 94 1.5.4.2 tls Static int athn_media_change(struct ifnet *); 95 1.5.4.2 tls Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 1.5.4.2 tls int); 97 1.5.4.2 tls Static struct ieee80211_node * 98 1.5.4.2 tls athn_node_alloc(struct ieee80211_node_table *); 99 1.5.4.2 tls Static int athn_reset_power_on(struct athn_softc *); 100 1.5.4.2 tls Static int athn_stop_rx_dma(struct athn_softc *); 101 1.5.4.2 tls Static int athn_switch_chan(struct athn_softc *, 102 1.5.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 103 1.5.4.2 tls Static void athn_calib_to(void *); 104 1.5.4.2 tls Static void athn_disable_interrupts(struct athn_softc *); 105 1.5.4.2 tls Static void athn_enable_interrupts(struct athn_softc *); 106 1.5.4.2 tls Static void athn_get_chanlist(struct athn_softc *); 107 1.5.4.2 tls Static void athn_get_chipid(struct athn_softc *); 108 1.5.4.2 tls Static void athn_init_dma(struct athn_softc *); 109 1.5.4.2 tls Static void athn_init_qos(struct athn_softc *); 110 1.5.4.2 tls Static void athn_init_tx_queues(struct athn_softc *); 111 1.5.4.2 tls Static void athn_iter_func(void *, struct ieee80211_node *); 112 1.5.4.2 tls Static void athn_newassoc(struct ieee80211_node *, int); 113 1.5.4.2 tls Static void athn_next_scan(void *); 114 1.5.4.2 tls Static void athn_pmf_wlan_off(device_t self); 115 1.5.4.2 tls Static void athn_radiotap_attach(struct athn_softc *); 116 1.5.4.2 tls Static void athn_start(struct ifnet *); 117 1.5.4.2 tls Static void athn_tx_reclaim(struct athn_softc *, int); 118 1.5.4.2 tls Static void athn_watchdog(struct ifnet *); 119 1.5.4.2 tls Static void athn_write_serdes(struct athn_softc *, 120 1.5.4.2 tls const struct athn_serdes *); 121 1.5.4.2 tls 122 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 123 1.5.4.2 tls Static void athn_btcoex_disable(struct athn_softc *); 124 1.5.4.2 tls Static void athn_btcoex_enable(struct athn_softc *); 125 1.5.4.2 tls #endif 126 1.5.4.2 tls 127 1.5.4.2 tls #ifdef unused 128 1.5.4.2 tls Static int32_t athn_ani_get_rssi(struct athn_softc *); 129 1.5.4.2 tls Static int athn_rx_abort(struct athn_softc *); 130 1.5.4.2 tls #endif 131 1.5.4.2 tls 132 1.5.4.2 tls #ifdef notyet 133 1.5.4.2 tls Static void athn_ani_cck_err_trigger(struct athn_softc *); 134 1.5.4.2 tls Static void athn_ani_lower_immunity(struct athn_softc *); 135 1.5.4.2 tls Static void athn_ani_monitor(struct athn_softc *); 136 1.5.4.2 tls Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 137 1.5.4.2 tls Static void athn_ani_restart(struct athn_softc *); 138 1.5.4.2 tls Static void athn_set_multi(struct athn_softc *); 139 1.5.4.2 tls #endif /* notyet */ 140 1.5.4.2 tls 141 1.5.4.2 tls PUBLIC int 142 1.5.4.2 tls athn_attach(struct athn_softc *sc) 143 1.5.4.2 tls { 144 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 145 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 146 1.5.4.2 tls size_t max_nnodes; 147 1.5.4.2 tls int error; 148 1.5.4.2 tls 149 1.5.4.2 tls /* Read hardware revision. */ 150 1.5.4.2 tls athn_get_chipid(sc); 151 1.5.4.2 tls 152 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) { 153 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 154 1.5.4.2 tls return error; 155 1.5.4.2 tls } 156 1.5.4.2 tls 157 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 158 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 159 1.5.4.2 tls return error; 160 1.5.4.2 tls } 161 1.5.4.2 tls 162 1.5.4.2 tls if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 163 1.5.4.2 tls error = ar5416_attach(sc); 164 1.5.4.2 tls else if (AR_SREV_9280(sc)) 165 1.5.4.2 tls error = ar9280_attach(sc); 166 1.5.4.2 tls else if (AR_SREV_9285(sc)) 167 1.5.4.2 tls error = ar9285_attach(sc); 168 1.5.4.2 tls #if NATHN_USB > 0 169 1.5.4.2 tls else if (AR_SREV_9271(sc)) 170 1.5.4.2 tls error = ar9285_attach(sc); 171 1.5.4.2 tls #endif 172 1.5.4.2 tls else if (AR_SREV_9287(sc)) 173 1.5.4.2 tls error = ar9287_attach(sc); 174 1.5.4.2 tls else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 175 1.5.4.2 tls error = ar9380_attach(sc); 176 1.5.4.2 tls else 177 1.5.4.2 tls error = ENOTSUP; 178 1.5.4.2 tls if (error != 0) { 179 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 180 1.5.4.2 tls return error; 181 1.5.4.2 tls } 182 1.5.4.2 tls 183 1.5.4.2 tls pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 184 1.5.4.2 tls pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 185 1.5.4.2 tls false); 186 1.5.4.2 tls 187 1.5.4.2 tls /* We can put the chip in sleep state now. */ 188 1.5.4.2 tls athn_set_power_sleep(sc); 189 1.5.4.2 tls 190 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_USB)) { 191 1.5.4.2 tls error = sc->sc_ops.dma_alloc(sc); 192 1.5.4.2 tls if (error != 0) { 193 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 194 1.5.4.2 tls "could not allocate DMA resources\n"); 195 1.5.4.2 tls return error; 196 1.5.4.2 tls } 197 1.5.4.2 tls /* Steal one Tx buffer for beacons. */ 198 1.5.4.2 tls sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 199 1.5.4.2 tls SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 200 1.5.4.2 tls } 201 1.5.4.2 tls 202 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 203 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, 204 1.5.4.2 tls "found RF switch connected to GPIO pin %d\n", 205 1.5.4.2 tls sc->sc_rfsilent_pin); 206 1.5.4.2 tls } 207 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 208 1.5.4.2 tls 209 1.5.4.2 tls /* 210 1.5.4.2 tls * In HostAP mode, the number of STAs that we can handle is 211 1.5.4.2 tls * limited by the number of entries in the HW key cache. 212 1.5.4.2 tls * TKIP keys consume 2 entries in the cache. 213 1.5.4.2 tls */ 214 1.5.4.2 tls KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 215 1.5.4.2 tls max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 216 1.5.4.2 tls if (sc->sc_max_aid != 0) /* we have an override */ 217 1.5.4.2 tls ic->ic_max_aid = sc->sc_max_aid; 218 1.5.4.2 tls if (ic->ic_max_aid > max_nnodes) 219 1.5.4.2 tls ic->ic_max_aid = max_nnodes; 220 1.5.4.2 tls 221 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 222 1.5.4.2 tls (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 223 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 224 1.5.4.2 tls sc->sc_txchainmask, sc->sc_rxchainmask); 225 1.5.4.2 tls 226 1.5.4.2 tls /* Count the number of bits set (in lowest 3 bits). */ 227 1.5.4.2 tls sc->sc_ntxchains = 228 1.5.4.2 tls ((sc->sc_txchainmask >> 2) & 1) + 229 1.5.4.2 tls ((sc->sc_txchainmask >> 1) & 1) + 230 1.5.4.2 tls ((sc->sc_txchainmask >> 0) & 1); 231 1.5.4.2 tls sc->sc_nrxchains = 232 1.5.4.2 tls ((sc->sc_rxchainmask >> 2) & 1) + 233 1.5.4.2 tls ((sc->sc_rxchainmask >> 1) & 1) + 234 1.5.4.2 tls ((sc->sc_rxchainmask >> 0) & 1); 235 1.5.4.2 tls 236 1.5.4.2 tls if (AR_SINGLE_CHIP(sc)) { 237 1.5.4.3 tls aprint_normal_dev(sc->sc_dev, 238 1.5.4.3 tls "Atheros %s\n", athn_get_mac_name(sc)); 239 1.5.4.2 tls aprint_verbose_dev(sc->sc_dev, 240 1.5.4.2 tls "rev %d (%dT%dR), ROM rev %d, address %s\n", 241 1.5.4.2 tls sc->sc_mac_rev, 242 1.5.4.2 tls sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 243 1.5.4.2 tls ether_sprintf(ic->ic_myaddr)); 244 1.5.4.3 tls } else { 245 1.5.4.3 tls aprint_normal_dev(sc->sc_dev, 246 1.5.4.3 tls "Atheros %s, RF %s\n", athn_get_mac_name(sc), 247 1.5.4.2 tls athn_get_rf_name(sc)); 248 1.5.4.2 tls aprint_verbose_dev(sc->sc_dev, 249 1.5.4.2 tls "rev %d (%dT%dR), ROM rev %d, address %s\n", 250 1.5.4.2 tls sc->sc_mac_rev, 251 1.5.4.2 tls sc->sc_ntxchains, sc->sc_nrxchains, 252 1.5.4.2 tls sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 253 1.5.4.2 tls } 254 1.5.4.2 tls 255 1.5.4.2 tls callout_init(&sc->sc_scan_to, 0); 256 1.5.4.2 tls callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 257 1.5.4.2 tls callout_init(&sc->sc_calib_to, 0); 258 1.5.4.2 tls callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 259 1.5.4.2 tls 260 1.5.4.2 tls sc->sc_amrr.amrr_min_success_threshold = 1; 261 1.5.4.2 tls sc->sc_amrr.amrr_max_success_threshold = 15; 262 1.5.4.2 tls 263 1.5.4.2 tls ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 264 1.5.4.2 tls ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 265 1.5.4.2 tls ic->ic_state = IEEE80211_S_INIT; 266 1.5.4.2 tls 267 1.5.4.2 tls /* Set device capabilities. */ 268 1.5.4.2 tls ic->ic_caps = 269 1.5.4.2 tls IEEE80211_C_WPA | /* 802.11i */ 270 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 271 1.5.4.2 tls IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 272 1.5.4.2 tls // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 273 1.5.4.2 tls #endif 274 1.5.4.2 tls IEEE80211_C_MONITOR | /* Monitor mode supported. */ 275 1.5.4.2 tls IEEE80211_C_SHSLOT | /* Short slot time supported. */ 276 1.5.4.2 tls IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 277 1.5.4.2 tls IEEE80211_C_PMGT; /* Power saving supported. */ 278 1.5.4.2 tls 279 1.5.4.2 tls #ifndef IEEE80211_NO_HT 280 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11N) { 281 1.5.4.2 tls int i, ntxstreams, nrxstreams; 282 1.5.4.2 tls 283 1.5.4.2 tls /* Set HT capabilities. */ 284 1.5.4.2 tls ic->ic_htcaps = 285 1.5.4.2 tls IEEE80211_HTCAP_SMPS_DIS | 286 1.5.4.2 tls IEEE80211_HTCAP_CBW20_40 | 287 1.5.4.2 tls IEEE80211_HTCAP_SGI40 | 288 1.5.4.2 tls IEEE80211_HTCAP_DSSSCCK40; 289 1.5.4.2 tls if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 290 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 291 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 292 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 293 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc)) { 294 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 295 1.5.4.2 tls ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 296 1.5.4.2 tls } 297 1.5.4.2 tls ntxstreams = sc->sc_ntxchains; 298 1.5.4.2 tls nrxstreams = sc->sc_nrxchains; 299 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 300 1.5.4.2 tls ntxstreams = MIN(ntxstreams, 2); 301 1.5.4.2 tls nrxstreams = MIN(nrxstreams, 2); 302 1.5.4.2 tls } 303 1.5.4.2 tls /* Set supported HT rates. */ 304 1.5.4.2 tls for (i = 0; i < nrxstreams; i++) 305 1.5.4.2 tls ic->ic_sup_mcs[i] = 0xff; 306 1.5.4.2 tls /* Set the "Tx MCS Set Defined" bit. */ 307 1.5.4.2 tls ic->ic_sup_mcs[12] |= 0x01; 308 1.5.4.2 tls if (ntxstreams != nrxstreams) { 309 1.5.4.2 tls /* Set "Tx Rx MCS Set Not Equal" bit. */ 310 1.5.4.2 tls ic->ic_sup_mcs[12] |= 0x02; 311 1.5.4.2 tls ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 312 1.5.4.2 tls } 313 1.5.4.2 tls } 314 1.5.4.2 tls #endif 315 1.5.4.2 tls 316 1.5.4.2 tls /* Set supported rates. */ 317 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11G) { 318 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11B] = 319 1.5.4.2 tls ieee80211_std_rateset_11b; 320 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11G] = 321 1.5.4.2 tls ieee80211_std_rateset_11g; 322 1.5.4.2 tls } 323 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11A) { 324 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11A] = 325 1.5.4.2 tls ieee80211_std_rateset_11a; 326 1.5.4.2 tls } 327 1.5.4.2 tls 328 1.5.4.2 tls /* Get the list of authorized/supported channels. */ 329 1.5.4.2 tls athn_get_chanlist(sc); 330 1.5.4.2 tls 331 1.5.4.2 tls ifp->if_softc = sc; 332 1.5.4.2 tls ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 1.5.4.2 tls ifp->if_init = athn_init; 334 1.5.4.2 tls ifp->if_ioctl = athn_ioctl; 335 1.5.4.2 tls ifp->if_start = athn_start; 336 1.5.4.2 tls ifp->if_watchdog = athn_watchdog; 337 1.5.4.2 tls IFQ_SET_READY(&ifp->if_snd); 338 1.5.4.2 tls memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 339 1.5.4.2 tls 340 1.5.4.2 tls if_attach(ifp); 341 1.5.4.2 tls ieee80211_ifattach(ic); 342 1.5.4.2 tls 343 1.5.4.2 tls ic->ic_node_alloc = athn_node_alloc; 344 1.5.4.2 tls ic->ic_newassoc = athn_newassoc; 345 1.5.4.2 tls if (ic->ic_updateslot == NULL) 346 1.5.4.2 tls ic->ic_updateslot = athn_updateslot; 347 1.5.4.2 tls #ifdef notyet_edca 348 1.5.4.2 tls ic->ic_updateedca = athn_updateedca; 349 1.5.4.2 tls #endif 350 1.5.4.2 tls #ifdef notyet 351 1.5.4.2 tls ic->ic_set_key = athn_set_key; 352 1.5.4.2 tls ic->ic_delete_key = athn_delete_key; 353 1.5.4.2 tls #endif 354 1.5.4.2 tls 355 1.5.4.2 tls /* Override 802.11 state transition machine. */ 356 1.5.4.2 tls sc->sc_newstate = ic->ic_newstate; 357 1.5.4.2 tls ic->ic_newstate = athn_newstate; 358 1.5.4.2 tls 359 1.5.4.2 tls if (sc->sc_media_change == NULL) 360 1.5.4.2 tls sc->sc_media_change = athn_media_change; 361 1.5.4.2 tls ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 362 1.5.4.2 tls 363 1.5.4.2 tls athn_radiotap_attach(sc); 364 1.5.4.2 tls return 0; 365 1.5.4.2 tls } 366 1.5.4.2 tls 367 1.5.4.2 tls PUBLIC void 368 1.5.4.2 tls athn_detach(struct athn_softc *sc) 369 1.5.4.2 tls { 370 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 371 1.5.4.2 tls int qid; 372 1.5.4.2 tls 373 1.5.4.2 tls callout_halt(&sc->sc_scan_to, NULL); 374 1.5.4.2 tls callout_halt(&sc->sc_calib_to, NULL); 375 1.5.4.2 tls 376 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_USB)) { 377 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 378 1.5.4.2 tls athn_tx_reclaim(sc, qid); 379 1.5.4.2 tls 380 1.5.4.2 tls /* Free Tx/Rx DMA resources. */ 381 1.5.4.2 tls sc->sc_ops.dma_free(sc); 382 1.5.4.2 tls } 383 1.5.4.2 tls /* Free ROM copy. */ 384 1.5.4.2 tls if (sc->sc_eep != NULL) { 385 1.5.4.2 tls free(sc->sc_eep, M_DEVBUF); 386 1.5.4.2 tls sc->sc_eep = NULL; 387 1.5.4.2 tls } 388 1.5.4.2 tls 389 1.5.4.2 tls bpf_detach(ifp); 390 1.5.4.2 tls ieee80211_ifdetach(&sc->sc_ic); 391 1.5.4.2 tls if_detach(ifp); 392 1.5.4.2 tls 393 1.5.4.2 tls callout_destroy(&sc->sc_scan_to); 394 1.5.4.2 tls callout_destroy(&sc->sc_calib_to); 395 1.5.4.2 tls } 396 1.5.4.2 tls 397 1.5.4.2 tls /* 398 1.5.4.2 tls * Attach the interface to 802.11 radiotap. 399 1.5.4.2 tls */ 400 1.5.4.2 tls Static void 401 1.5.4.2 tls athn_radiotap_attach(struct athn_softc *sc) 402 1.5.4.2 tls { 403 1.5.4.2 tls 404 1.5.4.2 tls bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 405 1.5.4.2 tls sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 406 1.5.4.2 tls &sc->sc_drvbpf); 407 1.5.4.2 tls 408 1.5.4.2 tls sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 409 1.5.4.2 tls sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 410 1.5.4.2 tls sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 411 1.5.4.2 tls 412 1.5.4.2 tls sc->sc_txtap_len = sizeof(sc->sc_txtapu); 413 1.5.4.2 tls sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 414 1.5.4.2 tls sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 415 1.5.4.2 tls } 416 1.5.4.2 tls 417 1.5.4.2 tls Static void 418 1.5.4.2 tls athn_get_chanlist(struct athn_softc *sc) 419 1.5.4.2 tls { 420 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 421 1.5.4.2 tls uint8_t chan; 422 1.5.4.2 tls size_t i; 423 1.5.4.2 tls 424 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11G) { 425 1.5.4.2 tls for (i = 1; i <= 14; i++) { 426 1.5.4.2 tls chan = i; 427 1.5.4.2 tls ic->ic_channels[chan].ic_freq = 428 1.5.4.2 tls ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 429 1.5.4.2 tls ic->ic_channels[chan].ic_flags = 430 1.5.4.2 tls IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 431 1.5.4.2 tls IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 432 1.5.4.2 tls } 433 1.5.4.2 tls } 434 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11A) { 435 1.5.4.2 tls for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 436 1.5.4.2 tls chan = athn_5ghz_chans[i]; 437 1.5.4.2 tls ic->ic_channels[chan].ic_freq = 438 1.5.4.2 tls ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 439 1.5.4.2 tls ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 440 1.5.4.2 tls } 441 1.5.4.2 tls } 442 1.5.4.2 tls } 443 1.5.4.2 tls 444 1.5.4.2 tls PUBLIC void 445 1.5.4.2 tls athn_rx_start(struct athn_softc *sc) 446 1.5.4.2 tls { 447 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 448 1.5.4.2 tls uint32_t rfilt; 449 1.5.4.2 tls 450 1.5.4.2 tls /* Setup Rx DMA descriptors. */ 451 1.5.4.2 tls sc->sc_ops.rx_enable(sc); 452 1.5.4.2 tls 453 1.5.4.2 tls /* Set Rx filter. */ 454 1.5.4.2 tls rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 455 1.5.4.2 tls #ifndef IEEE80211_NO_HT 456 1.5.4.2 tls /* Want Compressed Block Ack Requests. */ 457 1.5.4.2 tls rfilt |= AR_RX_FILTER_COMPR_BAR; 458 1.5.4.2 tls #endif 459 1.5.4.2 tls rfilt |= AR_RX_FILTER_BEACON; 460 1.5.4.2 tls if (ic->ic_opmode != IEEE80211_M_STA) { 461 1.5.4.2 tls rfilt |= AR_RX_FILTER_PROBEREQ; 462 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 463 1.5.4.2 tls rfilt |= AR_RX_FILTER_PROM; 464 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 465 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc) && 466 1.5.4.2 tls ic->ic_opmode == IEEE80211_M_HOSTAP) 467 1.5.4.2 tls rfilt |= AR_RX_FILTER_PSPOLL; 468 1.5.4.2 tls #endif 469 1.5.4.2 tls } 470 1.5.4.2 tls athn_set_rxfilter(sc, rfilt); 471 1.5.4.2 tls 472 1.5.4.2 tls /* Set BSSID mask. */ 473 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 474 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKU, 0xffff); 475 1.5.4.2 tls 476 1.5.4.2 tls athn_set_opmode(sc); 477 1.5.4.2 tls 478 1.5.4.2 tls /* Set multicast filter. */ 479 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 480 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 481 1.5.4.2 tls 482 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 483 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 484 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, 0); 485 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 486 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 487 1.5.4.2 tls 488 1.5.4.2 tls /* XXX ANI. */ 489 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, 0); 490 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, 0); 491 1.5.4.2 tls 492 1.5.4.2 tls /* Disable HW crypto for now. */ 493 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 494 1.5.4.2 tls 495 1.5.4.2 tls /* Start PCU Rx. */ 496 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 497 1.5.4.2 tls AR_WRITE_BARRIER(sc); 498 1.5.4.2 tls } 499 1.5.4.2 tls 500 1.5.4.2 tls PUBLIC void 501 1.5.4.2 tls athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 502 1.5.4.2 tls { 503 1.5.4.2 tls 504 1.5.4.2 tls AR_WRITE(sc, AR_RX_FILTER, rfilt); 505 1.5.4.2 tls #ifdef notyet 506 1.5.4.2 tls reg = AR_READ(sc, AR_PHY_ERR); 507 1.5.4.2 tls reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 508 1.5.4.2 tls AR_PHY_ERR_CCK_TIMING); 509 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR, reg); 510 1.5.4.2 tls if (reg != 0) 511 1.5.4.2 tls AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 512 1.5.4.2 tls else 513 1.5.4.2 tls AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 514 1.5.4.2 tls #else 515 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR, 0); 516 1.5.4.2 tls AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 517 1.5.4.2 tls #endif 518 1.5.4.2 tls AR_WRITE_BARRIER(sc); 519 1.5.4.2 tls } 520 1.5.4.2 tls 521 1.5.4.2 tls PUBLIC int 522 1.5.4.2 tls athn_intr(void *xsc) 523 1.5.4.2 tls { 524 1.5.4.2 tls struct athn_softc *sc = xsc; 525 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 526 1.5.4.2 tls 527 1.5.4.2 tls if (!IS_UP_AND_RUNNING(ifp)) 528 1.5.4.2 tls return 0; 529 1.5.4.2 tls 530 1.5.4.2 tls if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 531 1.5.4.2 tls /* 532 1.5.4.2 tls * The hardware is not ready/present, don't touch anything. 533 1.5.4.2 tls * Note this can happen early on if the IRQ is shared. 534 1.5.4.2 tls */ 535 1.5.4.2 tls return 0; 536 1.5.4.2 tls 537 1.5.4.2 tls return sc->sc_ops.intr(sc); 538 1.5.4.2 tls } 539 1.5.4.2 tls 540 1.5.4.2 tls Static void 541 1.5.4.2 tls athn_get_chipid(struct athn_softc *sc) 542 1.5.4.2 tls { 543 1.5.4.2 tls uint32_t reg; 544 1.5.4.2 tls 545 1.5.4.2 tls reg = AR_READ(sc, AR_SREV); 546 1.5.4.2 tls if (MS(reg, AR_SREV_ID) == 0xff) { 547 1.5.4.2 tls sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 548 1.5.4.2 tls sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 549 1.5.4.2 tls if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 550 1.5.4.2 tls sc->sc_flags |= ATHN_FLAG_PCIE; 551 1.5.4.2 tls } 552 1.5.4.2 tls else { 553 1.5.4.2 tls sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 554 1.5.4.2 tls sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 555 1.5.4.2 tls if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 556 1.5.4.2 tls sc->sc_flags |= ATHN_FLAG_PCIE; 557 1.5.4.2 tls } 558 1.5.4.2 tls } 559 1.5.4.2 tls 560 1.5.4.2 tls Static const char * 561 1.5.4.2 tls athn_get_mac_name(struct athn_softc *sc) 562 1.5.4.2 tls { 563 1.5.4.2 tls 564 1.5.4.2 tls switch (sc->sc_mac_ver) { 565 1.5.4.2 tls case AR_SREV_VERSION_5416_PCI: 566 1.5.4.2 tls return "AR5416"; 567 1.5.4.2 tls case AR_SREV_VERSION_5416_PCIE: 568 1.5.4.2 tls return "AR5418"; 569 1.5.4.2 tls case AR_SREV_VERSION_9160: 570 1.5.4.2 tls return "AR9160"; 571 1.5.4.2 tls case AR_SREV_VERSION_9280: 572 1.5.4.2 tls return "AR9280"; 573 1.5.4.2 tls case AR_SREV_VERSION_9285: 574 1.5.4.2 tls return "AR9285"; 575 1.5.4.2 tls case AR_SREV_VERSION_9271: 576 1.5.4.2 tls return "AR9271"; 577 1.5.4.2 tls case AR_SREV_VERSION_9287: 578 1.5.4.2 tls return "AR9287"; 579 1.5.4.2 tls case AR_SREV_VERSION_9380: 580 1.5.4.2 tls return "AR9380"; 581 1.5.4.2 tls case AR_SREV_VERSION_9485: 582 1.5.4.2 tls return "AR9485"; 583 1.5.4.2 tls default: 584 1.5.4.2 tls return "unknown"; 585 1.5.4.2 tls } 586 1.5.4.2 tls } 587 1.5.4.2 tls 588 1.5.4.2 tls /* 589 1.5.4.2 tls * Return RF chip name (not for single-chip solutions). 590 1.5.4.2 tls */ 591 1.5.4.2 tls Static const char * 592 1.5.4.2 tls athn_get_rf_name(struct athn_softc *sc) 593 1.5.4.2 tls { 594 1.5.4.2 tls 595 1.5.4.2 tls KASSERT(!AR_SINGLE_CHIP(sc)); 596 1.5.4.2 tls 597 1.5.4.2 tls switch (sc->sc_rf_rev) { 598 1.5.4.2 tls case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 599 1.5.4.2 tls return "AR5133"; 600 1.5.4.2 tls case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 601 1.5.4.2 tls return "AR2133"; 602 1.5.4.2 tls case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 603 1.5.4.2 tls return "AR5122"; 604 1.5.4.2 tls case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 605 1.5.4.2 tls return "AR2122"; 606 1.5.4.2 tls default: 607 1.5.4.2 tls return "unknown"; 608 1.5.4.2 tls } 609 1.5.4.2 tls } 610 1.5.4.2 tls 611 1.5.4.2 tls PUBLIC int 612 1.5.4.2 tls athn_reset_power_on(struct athn_softc *sc) 613 1.5.4.2 tls { 614 1.5.4.2 tls int ntries; 615 1.5.4.2 tls 616 1.5.4.2 tls /* Set force wake. */ 617 1.5.4.2 tls AR_WRITE(sc, AR_RTC_FORCE_WAKE, 618 1.5.4.2 tls AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 619 1.5.4.2 tls 620 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 621 1.5.4.2 tls /* Make sure no DMA is active by doing an AHB reset. */ 622 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB); 623 1.5.4.2 tls } 624 1.5.4.2 tls /* RTC reset and clear. */ 625 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RESET, 0); 626 1.5.4.2 tls AR_WRITE_BARRIER(sc); 627 1.5.4.2 tls DELAY(2); 628 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 629 1.5.4.2 tls AR_WRITE(sc, AR_RC, 0); 630 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RESET, 1); 631 1.5.4.2 tls 632 1.5.4.2 tls /* Poll until RTC is ON. */ 633 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 634 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 635 1.5.4.2 tls AR_RTC_STATUS_ON) 636 1.5.4.2 tls break; 637 1.5.4.2 tls DELAY(10); 638 1.5.4.2 tls } 639 1.5.4.2 tls if (ntries == 1000) { 640 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 641 1.5.4.2 tls return ETIMEDOUT; 642 1.5.4.2 tls } 643 1.5.4.2 tls return athn_reset(sc, 0); 644 1.5.4.2 tls } 645 1.5.4.2 tls 646 1.5.4.2 tls PUBLIC int 647 1.5.4.2 tls athn_reset(struct athn_softc *sc, int cold_reset) 648 1.5.4.2 tls { 649 1.5.4.2 tls int ntries; 650 1.5.4.2 tls 651 1.5.4.2 tls /* Set force wake. */ 652 1.5.4.2 tls AR_WRITE(sc, AR_RTC_FORCE_WAKE, 653 1.5.4.2 tls AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 654 1.5.4.2 tls 655 1.5.4.2 tls if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 656 1.5.4.2 tls (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 657 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 658 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 659 1.5.4.2 tls (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 660 1.5.4.2 tls } 661 1.5.4.2 tls else if (!AR_SREV_9380_10_OR_LATER(sc)) 662 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB); 663 1.5.4.2 tls 664 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 665 1.5.4.2 tls (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 666 1.5.4.2 tls AR_WRITE_BARRIER(sc); 667 1.5.4.2 tls DELAY(50); 668 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RC, 0); 669 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 670 1.5.4.2 tls if (!(AR_READ(sc, AR_RTC_RC) & 671 1.5.4.2 tls (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 672 1.5.4.2 tls break; 673 1.5.4.2 tls DELAY(10); 674 1.5.4.2 tls } 675 1.5.4.2 tls if (ntries == 1000) { 676 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 677 1.5.4.2 tls return ETIMEDOUT; 678 1.5.4.2 tls } 679 1.5.4.2 tls AR_WRITE(sc, AR_RC, 0); 680 1.5.4.2 tls AR_WRITE_BARRIER(sc); 681 1.5.4.2 tls return 0; 682 1.5.4.2 tls } 683 1.5.4.2 tls 684 1.5.4.2 tls PUBLIC int 685 1.5.4.2 tls athn_set_power_awake(struct athn_softc *sc) 686 1.5.4.2 tls { 687 1.5.4.2 tls int ntries, error; 688 1.5.4.2 tls 689 1.5.4.2 tls /* Do a Power-On-Reset if shutdown. */ 690 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 691 1.5.4.2 tls AR_RTC_STATUS_SHUTDOWN) { 692 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) 693 1.5.4.2 tls return error; 694 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 695 1.5.4.2 tls athn_init_pll(sc, NULL); 696 1.5.4.2 tls } 697 1.5.4.2 tls AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 698 1.5.4.2 tls AR_WRITE_BARRIER(sc); 699 1.5.4.2 tls DELAY(50); /* Give chip the chance to awake. */ 700 1.5.4.2 tls 701 1.5.4.2 tls /* Poll until RTC is ON. */ 702 1.5.4.2 tls for (ntries = 0; ntries < 4000; ntries++) { 703 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 704 1.5.4.2 tls AR_RTC_STATUS_ON) 705 1.5.4.2 tls break; 706 1.5.4.2 tls DELAY(50); 707 1.5.4.2 tls AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 708 1.5.4.2 tls } 709 1.5.4.2 tls if (ntries == 4000) { 710 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 711 1.5.4.2 tls return ETIMEDOUT; 712 1.5.4.2 tls } 713 1.5.4.2 tls 714 1.5.4.2 tls AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 715 1.5.4.2 tls AR_WRITE_BARRIER(sc); 716 1.5.4.2 tls return 0; 717 1.5.4.2 tls } 718 1.5.4.2 tls 719 1.5.4.2 tls PUBLIC void 720 1.5.4.2 tls athn_set_power_sleep(struct athn_softc *sc) 721 1.5.4.2 tls { 722 1.5.4.2 tls 723 1.5.4.2 tls AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 724 1.5.4.2 tls /* Allow the MAC to go to sleep. */ 725 1.5.4.2 tls AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 726 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 727 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 728 1.5.4.2 tls /* 729 1.5.4.2 tls * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 730 1.5.4.2 tls * results in high power consumption on AR5416 chipsets. 731 1.5.4.2 tls */ 732 1.5.4.2 tls if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 733 1.5.4.2 tls AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 734 1.5.4.2 tls AR_WRITE_BARRIER(sc); 735 1.5.4.2 tls } 736 1.5.4.2 tls 737 1.5.4.2 tls PUBLIC void 738 1.5.4.2 tls athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 739 1.5.4.2 tls { 740 1.5.4.2 tls uint32_t pll; 741 1.5.4.2 tls 742 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 743 1.5.4.2 tls if (AR_SREV_9485(sc)) 744 1.5.4.2 tls AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 745 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 746 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 747 1.5.4.2 tls } 748 1.5.4.2 tls else if (AR_SREV_9280_10_OR_LATER(sc)) { 749 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 750 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 751 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 752 1.5.4.2 tls pll = 0x142c; 753 1.5.4.2 tls else if (AR_SREV_9280_20(sc)) 754 1.5.4.2 tls pll = 0x2850; 755 1.5.4.2 tls else 756 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 757 1.5.4.2 tls } 758 1.5.4.2 tls else 759 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 760 1.5.4.2 tls } 761 1.5.4.2 tls else if (AR_SREV_9160_10_OR_LATER(sc)) { 762 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 763 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 764 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 765 1.5.4.2 tls else 766 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 767 1.5.4.2 tls } 768 1.5.4.2 tls else { 769 1.5.4.2 tls pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 770 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 771 1.5.4.2 tls pll |= SM(AR_RTC_PLL_DIV, 0x0a); 772 1.5.4.2 tls else 773 1.5.4.2 tls pll |= SM(AR_RTC_PLL_DIV, 0x0b); 774 1.5.4.2 tls } 775 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 776 1.5.4.2 tls AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 777 1.5.4.2 tls if (AR_SREV_9271(sc)) { 778 1.5.4.2 tls /* Switch core clock to 117MHz. */ 779 1.5.4.2 tls AR_WRITE_BARRIER(sc); 780 1.5.4.2 tls DELAY(500); 781 1.5.4.2 tls AR_WRITE(sc, 0x50050, 0x304); 782 1.5.4.2 tls } 783 1.5.4.2 tls AR_WRITE_BARRIER(sc); 784 1.5.4.2 tls DELAY(100); 785 1.5.4.2 tls AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 786 1.5.4.2 tls AR_WRITE_BARRIER(sc); 787 1.5.4.2 tls } 788 1.5.4.2 tls 789 1.5.4.2 tls Static void 790 1.5.4.2 tls athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 791 1.5.4.2 tls { 792 1.5.4.2 tls int i; 793 1.5.4.2 tls 794 1.5.4.2 tls /* Write sequence to Serializer/Deserializer. */ 795 1.5.4.2 tls for (i = 0; i < serdes->nvals; i++) 796 1.5.4.2 tls AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 797 1.5.4.2 tls AR_WRITE_BARRIER(sc); 798 1.5.4.2 tls } 799 1.5.4.2 tls 800 1.5.4.2 tls PUBLIC void 801 1.5.4.2 tls athn_config_pcie(struct athn_softc *sc) 802 1.5.4.2 tls { 803 1.5.4.2 tls 804 1.5.4.2 tls /* Disable PLL when in L0s as well as receiver clock when in L1. */ 805 1.5.4.2 tls athn_write_serdes(sc, sc->sc_serdes); 806 1.5.4.2 tls 807 1.5.4.2 tls DELAY(1000); 808 1.5.4.2 tls /* Allow forcing of PCIe core into L1 state. */ 809 1.5.4.2 tls AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 810 1.5.4.2 tls 811 1.5.4.2 tls #ifndef ATHN_PCIE_WAEN 812 1.5.4.2 tls AR_WRITE(sc, AR_WA, sc->sc_workaround); 813 1.5.4.2 tls #else 814 1.5.4.2 tls AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 815 1.5.4.2 tls #endif 816 1.5.4.2 tls AR_WRITE_BARRIER(sc); 817 1.5.4.2 tls } 818 1.5.4.2 tls 819 1.5.4.2 tls /* 820 1.5.4.2 tls * Serializer/Deserializer programming for non-PCIe devices. 821 1.5.4.2 tls */ 822 1.5.4.2 tls static const uint32_t ar_nonpcie_serdes_regs[] = { 823 1.5.4.2 tls AR_PCIE_SERDES, 824 1.5.4.2 tls AR_PCIE_SERDES, 825 1.5.4.2 tls AR_PCIE_SERDES, 826 1.5.4.2 tls AR_PCIE_SERDES, 827 1.5.4.2 tls AR_PCIE_SERDES, 828 1.5.4.2 tls AR_PCIE_SERDES, 829 1.5.4.2 tls AR_PCIE_SERDES, 830 1.5.4.2 tls AR_PCIE_SERDES, 831 1.5.4.2 tls AR_PCIE_SERDES, 832 1.5.4.2 tls AR_PCIE_SERDES2, 833 1.5.4.2 tls }; 834 1.5.4.2 tls 835 1.5.4.2 tls static const uint32_t ar_nonpcie_serdes_vals[] = { 836 1.5.4.2 tls 0x9248fc00, 837 1.5.4.2 tls 0x24924924, 838 1.5.4.2 tls 0x28000029, 839 1.5.4.2 tls 0x57160824, 840 1.5.4.2 tls 0x25980579, 841 1.5.4.2 tls 0x00000000, 842 1.5.4.2 tls 0x1aaabe40, 843 1.5.4.2 tls 0xbe105554, 844 1.5.4.2 tls 0x000e1007, 845 1.5.4.2 tls 0x00000000 846 1.5.4.2 tls }; 847 1.5.4.2 tls 848 1.5.4.2 tls static const struct athn_serdes ar_nonpcie_serdes = { 849 1.5.4.2 tls __arraycount(ar_nonpcie_serdes_vals), 850 1.5.4.2 tls ar_nonpcie_serdes_regs, 851 1.5.4.2 tls ar_nonpcie_serdes_vals 852 1.5.4.2 tls }; 853 1.5.4.2 tls 854 1.5.4.2 tls PUBLIC void 855 1.5.4.2 tls athn_config_nonpcie(struct athn_softc *sc) 856 1.5.4.2 tls { 857 1.5.4.2 tls 858 1.5.4.2 tls athn_write_serdes(sc, &ar_nonpcie_serdes); 859 1.5.4.2 tls } 860 1.5.4.2 tls 861 1.5.4.2 tls PUBLIC int 862 1.5.4.2 tls athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 863 1.5.4.2 tls struct ieee80211_channel *extchan) 864 1.5.4.2 tls { 865 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 866 1.5.4.2 tls int error, qid; 867 1.5.4.2 tls 868 1.5.4.2 tls /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 869 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 870 1.5.4.2 tls if (athn_tx_pending(sc, qid)) 871 1.5.4.2 tls return EBUSY; 872 1.5.4.2 tls 873 1.5.4.2 tls /* Request RF Bus grant. */ 874 1.5.4.2 tls if ((error = ops->rf_bus_request(sc)) != 0) 875 1.5.4.2 tls return error; 876 1.5.4.2 tls 877 1.5.4.2 tls ops->set_phy(sc, curchan, extchan); 878 1.5.4.2 tls 879 1.5.4.2 tls /* Change the synthesizer. */ 880 1.5.4.2 tls if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 881 1.5.4.2 tls return error; 882 1.5.4.2 tls 883 1.5.4.2 tls sc->sc_curchan = curchan; 884 1.5.4.2 tls sc->sc_curchanext = extchan; 885 1.5.4.2 tls 886 1.5.4.2 tls /* Set transmit power values for new channel. */ 887 1.5.4.2 tls ops->set_txpower(sc, curchan, extchan); 888 1.5.4.2 tls 889 1.5.4.2 tls /* Release the RF Bus grant. */ 890 1.5.4.2 tls ops->rf_bus_release(sc); 891 1.5.4.2 tls 892 1.5.4.2 tls /* Write delta slope coeffs for modes where OFDM may be used. */ 893 1.5.4.2 tls if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 894 1.5.4.2 tls ops->set_delta_slope(sc, curchan, extchan); 895 1.5.4.2 tls 896 1.5.4.2 tls ops->spur_mitigate(sc, curchan, extchan); 897 1.5.4.2 tls /* XXX Load noisefloor values and start calibration. */ 898 1.5.4.2 tls 899 1.5.4.2 tls return 0; 900 1.5.4.2 tls } 901 1.5.4.2 tls 902 1.5.4.2 tls Static int 903 1.5.4.2 tls athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 904 1.5.4.2 tls struct ieee80211_channel *extchan) 905 1.5.4.2 tls { 906 1.5.4.2 tls int error, qid; 907 1.5.4.2 tls 908 1.5.4.2 tls /* Disable interrupts. */ 909 1.5.4.2 tls athn_disable_interrupts(sc); 910 1.5.4.2 tls 911 1.5.4.2 tls /* Stop all Tx queues. */ 912 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 913 1.5.4.2 tls athn_stop_tx_dma(sc, qid); 914 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 915 1.5.4.2 tls athn_tx_reclaim(sc, qid); 916 1.5.4.2 tls 917 1.5.4.2 tls /* Stop Rx. */ 918 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 919 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 920 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 921 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 922 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 923 1.5.4.2 tls athn_set_rxfilter(sc, 0); 924 1.5.4.2 tls error = athn_stop_rx_dma(sc); 925 1.5.4.2 tls if (error != 0) 926 1.5.4.2 tls goto reset; 927 1.5.4.2 tls 928 1.5.4.2 tls #ifdef notyet 929 1.5.4.2 tls /* AR9280 needs a full reset. */ 930 1.5.4.2 tls if (AR_SREV_9280(sc)) 931 1.5.4.2 tls #endif 932 1.5.4.2 tls goto reset; 933 1.5.4.2 tls 934 1.5.4.2 tls /* If band or bandwidth changes, we need to do a full reset. */ 935 1.5.4.2 tls if (curchan->ic_flags != sc->sc_curchan->ic_flags || 936 1.5.4.2 tls ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 937 1.5.4.2 tls DPRINTFN(DBG_RF, sc, "channel band switch\n"); 938 1.5.4.2 tls goto reset; 939 1.5.4.2 tls } 940 1.5.4.2 tls error = athn_set_power_awake(sc); 941 1.5.4.2 tls if (error != 0) 942 1.5.4.2 tls goto reset; 943 1.5.4.2 tls 944 1.5.4.2 tls error = athn_set_chan(sc, curchan, extchan); 945 1.5.4.2 tls if (error != 0) { 946 1.5.4.2 tls reset: /* Error found, try a full reset. */ 947 1.5.4.2 tls DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 948 1.5.4.2 tls error = athn_hw_reset(sc, curchan, extchan, 0); 949 1.5.4.2 tls if (error != 0) /* Hopeless case. */ 950 1.5.4.2 tls return error; 951 1.5.4.2 tls } 952 1.5.4.2 tls athn_rx_start(sc); 953 1.5.4.2 tls 954 1.5.4.2 tls /* Re-enable interrupts. */ 955 1.5.4.2 tls athn_enable_interrupts(sc); 956 1.5.4.2 tls return 0; 957 1.5.4.2 tls } 958 1.5.4.2 tls 959 1.5.4.2 tls PUBLIC void 960 1.5.4.2 tls athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 961 1.5.4.2 tls { 962 1.5.4.2 tls #define COEFF_SCALE_SHIFT 24 963 1.5.4.2 tls uint32_t exp, man; 964 1.5.4.2 tls 965 1.5.4.2 tls /* exponent = 14 - floor(log2(coeff)) */ 966 1.5.4.2 tls for (exp = 31; exp > 0; exp--) 967 1.5.4.2 tls if (coeff & (1 << exp)) 968 1.5.4.2 tls break; 969 1.5.4.2 tls exp = 14 - (exp - COEFF_SCALE_SHIFT); 970 1.5.4.2 tls 971 1.5.4.2 tls /* mantissa = floor(coeff * 2^exponent + 0.5) */ 972 1.5.4.2 tls man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 973 1.5.4.2 tls 974 1.5.4.2 tls *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 975 1.5.4.2 tls *exponent = exp - 16; 976 1.5.4.2 tls #undef COEFF_SCALE_SHIFT 977 1.5.4.2 tls } 978 1.5.4.2 tls 979 1.5.4.2 tls PUBLIC void 980 1.5.4.2 tls athn_reset_key(struct athn_softc *sc, int entry) 981 1.5.4.2 tls { 982 1.5.4.2 tls 983 1.5.4.2 tls /* 984 1.5.4.2 tls * NB: Key cache registers access special memory area that requires 985 1.5.4.2 tls * two 32-bit writes to actually update the values in the internal 986 1.5.4.2 tls * memory. Consequently, writes must be grouped by pair. 987 1.5.4.2 tls */ 988 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 989 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 990 1.5.4.2 tls 991 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 992 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 993 1.5.4.2 tls 994 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 995 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 996 1.5.4.2 tls 997 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 998 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 999 1.5.4.2 tls 1000 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1001 1.5.4.2 tls } 1002 1.5.4.2 tls 1003 1.5.4.2 tls #ifdef notyet 1004 1.5.4.2 tls Static int 1005 1.5.4.2 tls athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1006 1.5.4.2 tls struct ieee80211_key *k) 1007 1.5.4.2 tls { 1008 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 1009 1.5.4.2 tls const uint8_t *txmic, *rxmic, *key, *addr; 1010 1.5.4.2 tls uintptr_t entry, micentry; 1011 1.5.4.2 tls uint32_t type, lo, hi; 1012 1.5.4.2 tls 1013 1.5.4.2 tls switch (k->k_cipher) { 1014 1.5.4.2 tls case IEEE80211_CIPHER_WEP40: 1015 1.5.4.2 tls type = AR_KEYTABLE_TYPE_40; 1016 1.5.4.2 tls break; 1017 1.5.4.2 tls case IEEE80211_CIPHER_WEP104: 1018 1.5.4.2 tls type = AR_KEYTABLE_TYPE_104; 1019 1.5.4.2 tls break; 1020 1.5.4.2 tls case IEEE80211_CIPHER_TKIP: 1021 1.5.4.2 tls type = AR_KEYTABLE_TYPE_TKIP; 1022 1.5.4.2 tls break; 1023 1.5.4.2 tls case IEEE80211_CIPHER_CCMP: 1024 1.5.4.2 tls type = AR_KEYTABLE_TYPE_CCM; 1025 1.5.4.2 tls break; 1026 1.5.4.2 tls default: 1027 1.5.4.2 tls /* Fallback to software crypto for other ciphers. */ 1028 1.5.4.2 tls return ieee80211_set_key(ic, ni, k); 1029 1.5.4.2 tls } 1030 1.5.4.2 tls 1031 1.5.4.2 tls if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1032 1.5.4.2 tls entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1033 1.5.4.2 tls else 1034 1.5.4.2 tls entry = k->k_id; 1035 1.5.4.2 tls k->k_priv = (void *)entry; 1036 1.5.4.2 tls 1037 1.5.4.2 tls /* NB: See note about key cache registers access above. */ 1038 1.5.4.2 tls key = k->k_key; 1039 1.5.4.2 tls if (type == AR_KEYTABLE_TYPE_TKIP) { 1040 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1041 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1042 1.5.4.2 tls txmic = &key[16]; 1043 1.5.4.2 tls rxmic = &key[24]; 1044 1.5.4.2 tls } 1045 1.5.4.2 tls else 1046 1.5.4.2 tls #endif 1047 1.5.4.2 tls { 1048 1.5.4.2 tls rxmic = &key[16]; 1049 1.5.4.2 tls txmic = &key[24]; 1050 1.5.4.2 tls } 1051 1.5.4.2 tls /* Tx+Rx MIC key is at entry + 64. */ 1052 1.5.4.2 tls micentry = entry + 64; 1053 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1054 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1055 1.5.4.2 tls 1056 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1057 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1058 1.5.4.2 tls 1059 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1060 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1061 1.5.4.2 tls } 1062 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1063 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1064 1.5.4.2 tls 1065 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1066 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1067 1.5.4.2 tls 1068 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1069 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1070 1.5.4.2 tls 1071 1.5.4.2 tls if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1072 1.5.4.2 tls addr = ni->ni_macaddr; 1073 1.5.4.2 tls lo = LE_READ_4(&addr[0]); 1074 1.5.4.2 tls hi = LE_READ_2(&addr[4]); 1075 1.5.4.2 tls lo = lo >> 1 | hi << 31; 1076 1.5.4.2 tls hi = hi >> 1; 1077 1.5.4.2 tls } 1078 1.5.4.2 tls else 1079 1.5.4.2 tls lo = hi = 0; 1080 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1081 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1082 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1083 1.5.4.2 tls return 0; 1084 1.5.4.2 tls } 1085 1.5.4.2 tls 1086 1.5.4.2 tls Static void 1087 1.5.4.2 tls athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1088 1.5.4.2 tls struct ieee80211_key *k) 1089 1.5.4.2 tls { 1090 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 1091 1.5.4.2 tls uintptr_t entry; 1092 1.5.4.2 tls 1093 1.5.4.2 tls switch (k->k_cipher) { 1094 1.5.4.2 tls case IEEE80211_CIPHER_WEP40: 1095 1.5.4.2 tls case IEEE80211_CIPHER_WEP104: 1096 1.5.4.2 tls case IEEE80211_CIPHER_CCMP: 1097 1.5.4.2 tls entry = (uintptr_t)k->k_priv; 1098 1.5.4.2 tls athn_reset_key(sc, entry); 1099 1.5.4.2 tls break; 1100 1.5.4.2 tls case IEEE80211_CIPHER_TKIP: 1101 1.5.4.2 tls entry = (uintptr_t)k->k_priv; 1102 1.5.4.2 tls athn_reset_key(sc, entry); 1103 1.5.4.2 tls athn_reset_key(sc, entry + 64); 1104 1.5.4.2 tls break; 1105 1.5.4.2 tls default: 1106 1.5.4.2 tls /* Fallback to software crypto for other ciphers. */ 1107 1.5.4.2 tls ieee80211_delete_key(ic, ni, k); 1108 1.5.4.2 tls } 1109 1.5.4.2 tls } 1110 1.5.4.2 tls #endif /* notyet */ 1111 1.5.4.2 tls 1112 1.5.4.2 tls PUBLIC void 1113 1.5.4.2 tls athn_led_init(struct athn_softc *sc) 1114 1.5.4.2 tls { 1115 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1116 1.5.4.2 tls 1117 1.5.4.2 tls ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1118 1.5.4.2 tls /* LED off, active low. */ 1119 1.5.4.2 tls athn_set_led(sc, 0); 1120 1.5.4.2 tls } 1121 1.5.4.2 tls 1122 1.5.4.2 tls PUBLIC void 1123 1.5.4.2 tls athn_set_led(struct athn_softc *sc, int on) 1124 1.5.4.2 tls { 1125 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1126 1.5.4.2 tls 1127 1.5.4.2 tls sc->sc_led_state = on; 1128 1.5.4.2 tls ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1129 1.5.4.2 tls } 1130 1.5.4.2 tls 1131 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 1132 1.5.4.2 tls Static void 1133 1.5.4.2 tls athn_btcoex_init(struct athn_softc *sc) 1134 1.5.4.2 tls { 1135 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1136 1.5.4.2 tls uint32_t reg; 1137 1.5.4.2 tls 1138 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1139 1.5.4.2 tls /* Connect bt_active to baseband. */ 1140 1.5.4.2 tls AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1141 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1142 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1143 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1144 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1145 1.5.4.2 tls 1146 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1147 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1148 1.5.4.2 tls AR_GPIO_BTACTIVE_PIN); 1149 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1150 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1151 1.5.4.2 tls 1152 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1153 1.5.4.2 tls } 1154 1.5.4.2 tls else { /* 3-wire. */ 1155 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1156 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1157 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1158 1.5.4.2 tls 1159 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1160 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1161 1.5.4.2 tls AR_GPIO_BTACTIVE_PIN); 1162 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1163 1.5.4.2 tls AR_GPIO_BTPRIORITY_PIN); 1164 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1165 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1166 1.5.4.2 tls 1167 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1168 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1169 1.5.4.2 tls } 1170 1.5.4.2 tls } 1171 1.5.4.2 tls 1172 1.5.4.2 tls Static void 1173 1.5.4.2 tls athn_btcoex_enable(struct athn_softc *sc) 1174 1.5.4.2 tls { 1175 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1176 1.5.4.2 tls uint32_t reg; 1177 1.5.4.2 tls 1178 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1179 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE, 1180 1.5.4.2 tls SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1181 1.5.4.2 tls SM(AR_BT_PRIORITY_TIME, 2) | 1182 1.5.4.2 tls SM(AR_BT_FIRST_SLOT_TIME, 5) | 1183 1.5.4.2 tls SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1184 1.5.4.2 tls AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1185 1.5.4.2 tls AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1186 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1187 1.5.4.2 tls SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1188 1.5.4.2 tls SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1189 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE2, 1190 1.5.4.2 tls SM(AR_BT_BCN_MISS_THRESH, 50) | 1191 1.5.4.2 tls AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1192 1.5.4.2 tls 1193 1.5.4.2 tls AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1194 1.5.4.2 tls AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1195 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1196 1.5.4.2 tls 1197 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1198 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1199 1.5.4.2 tls 1200 1.5.4.2 tls } 1201 1.5.4.2 tls else { /* 2-wire. */ 1202 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1203 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1204 1.5.4.2 tls } 1205 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_PDPU); 1206 1.5.4.2 tls reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1207 1.5.4.2 tls reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1208 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_PDPU, reg); 1209 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1210 1.5.4.2 tls 1211 1.5.4.2 tls /* Disable PCIe Active State Power Management (ASPM). */ 1212 1.5.4.2 tls if (sc->sc_disable_aspm != NULL) 1213 1.5.4.2 tls sc->sc_disable_aspm(sc); 1214 1.5.4.2 tls 1215 1.5.4.2 tls /* XXX Start periodic timer. */ 1216 1.5.4.2 tls } 1217 1.5.4.2 tls 1218 1.5.4.2 tls Static void 1219 1.5.4.2 tls athn_btcoex_disable(struct athn_softc *sc) 1220 1.5.4.2 tls { 1221 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1222 1.5.4.2 tls 1223 1.5.4.2 tls ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1224 1.5.4.2 tls 1225 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1226 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1227 1.5.4.2 tls 1228 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1229 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE, 1230 1.5.4.2 tls SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1231 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1232 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1233 1.5.4.2 tls /* XXX Stop periodic timer. */ 1234 1.5.4.2 tls } 1235 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1236 1.5.4.2 tls /* XXX Restore ASPM setting? */ 1237 1.5.4.2 tls } 1238 1.5.4.2 tls #endif 1239 1.5.4.2 tls 1240 1.5.4.2 tls Static void 1241 1.5.4.2 tls athn_iter_func(void *arg, struct ieee80211_node *ni) 1242 1.5.4.2 tls { 1243 1.5.4.2 tls struct athn_softc *sc = arg; 1244 1.5.4.2 tls struct athn_node *an = (struct athn_node *)ni; 1245 1.5.4.2 tls 1246 1.5.4.2 tls ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1247 1.5.4.2 tls } 1248 1.5.4.2 tls 1249 1.5.4.2 tls Static void 1250 1.5.4.2 tls athn_calib_to(void *arg) 1251 1.5.4.2 tls { 1252 1.5.4.2 tls extern int ticks; 1253 1.5.4.2 tls struct athn_softc *sc = arg; 1254 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1255 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 1256 1.5.4.2 tls int s; 1257 1.5.4.2 tls 1258 1.5.4.2 tls s = splnet(); 1259 1.5.4.2 tls 1260 1.5.4.2 tls /* Do periodic (every 4 minutes) PA calibration. */ 1261 1.5.4.2 tls if (AR_SREV_9285_11_OR_LATER(sc) && 1262 1.5.4.2 tls !AR_SREV_9380_10_OR_LATER(sc) && 1263 1.5.4.3 tls (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1264 1.5.4.2 tls sc->sc_pa_calib_ticks = ticks; 1265 1.5.4.2 tls if (AR_SREV_9271(sc)) 1266 1.5.4.2 tls ar9271_pa_calib(sc); 1267 1.5.4.2 tls else 1268 1.5.4.2 tls ar9285_pa_calib(sc); 1269 1.5.4.2 tls } 1270 1.5.4.2 tls 1271 1.5.4.2 tls /* Do periodic (every 30 seconds) temperature compensation. */ 1272 1.5.4.2 tls if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1273 1.5.4.2 tls ticks >= sc->sc_olpc_ticks + 30 * hz) { 1274 1.5.4.2 tls sc->sc_olpc_ticks = ticks; 1275 1.5.4.2 tls ops->olpc_temp_compensation(sc); 1276 1.5.4.2 tls } 1277 1.5.4.2 tls 1278 1.5.4.2 tls #ifdef notyet 1279 1.5.4.2 tls /* XXX ANI. */ 1280 1.5.4.2 tls athn_ani_monitor(sc); 1281 1.5.4.2 tls 1282 1.5.4.2 tls ops->next_calib(sc); 1283 1.5.4.2 tls #endif 1284 1.5.4.2 tls if (ic->ic_fixed_rate == -1) { 1285 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_STA) 1286 1.5.4.2 tls athn_iter_func(sc, ic->ic_bss); 1287 1.5.4.2 tls else 1288 1.5.4.2 tls ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1289 1.5.4.2 tls } 1290 1.5.4.2 tls callout_schedule(&sc->sc_calib_to, hz / 2); 1291 1.5.4.2 tls splx(s); 1292 1.5.4.2 tls } 1293 1.5.4.2 tls 1294 1.5.4.2 tls Static int 1295 1.5.4.2 tls athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1296 1.5.4.2 tls struct ieee80211_channel *extchan) 1297 1.5.4.2 tls { 1298 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1299 1.5.4.2 tls int error; 1300 1.5.4.2 tls 1301 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 1302 1.5.4.2 tls error = ar9003_init_calib(sc); 1303 1.5.4.2 tls else if (AR_SREV_9285_10_OR_LATER(sc)) 1304 1.5.4.2 tls error = ar9285_init_calib(sc, curchan, extchan); 1305 1.5.4.2 tls else 1306 1.5.4.2 tls error = ar5416_init_calib(sc, curchan, extchan); 1307 1.5.4.2 tls if (error != 0) 1308 1.5.4.2 tls return error; 1309 1.5.4.2 tls 1310 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 1311 1.5.4.2 tls /* Do PA calibration. */ 1312 1.5.4.2 tls if (AR_SREV_9285_11_OR_LATER(sc)) { 1313 1.5.4.2 tls extern int ticks; 1314 1.5.4.2 tls sc->sc_pa_calib_ticks = ticks; 1315 1.5.4.2 tls if (AR_SREV_9271(sc)) 1316 1.5.4.2 tls ar9271_pa_calib(sc); 1317 1.5.4.2 tls else 1318 1.5.4.2 tls ar9285_pa_calib(sc); 1319 1.5.4.2 tls } 1320 1.5.4.2 tls /* Do noisefloor calibration. */ 1321 1.5.4.2 tls ops->noisefloor_calib(sc); 1322 1.5.4.2 tls } 1323 1.5.4.2 tls if (AR_SREV_9160_10_OR_LATER(sc)) { 1324 1.5.4.2 tls /* Support IQ calibration. */ 1325 1.5.4.2 tls sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1326 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 1327 1.5.4.2 tls /* Support temperature compensation calibration. */ 1328 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1329 1.5.4.2 tls } 1330 1.5.4.2 tls else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1331 1.5.4.2 tls /* 1332 1.5.4.2 tls * ADC gain calibration causes uplink throughput 1333 1.5.4.2 tls * drops in HT40 mode on AR9287. 1334 1.5.4.2 tls */ 1335 1.5.4.2 tls if (!AR_SREV_9287(sc)) { 1336 1.5.4.2 tls /* Support ADC gain calibration. */ 1337 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1338 1.5.4.2 tls } 1339 1.5.4.2 tls /* Support ADC DC offset calibration. */ 1340 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1341 1.5.4.2 tls } 1342 1.5.4.2 tls } 1343 1.5.4.2 tls return 0; 1344 1.5.4.2 tls } 1345 1.5.4.2 tls 1346 1.5.4.2 tls /* 1347 1.5.4.2 tls * Adaptive noise immunity. 1348 1.5.4.2 tls */ 1349 1.5.4.2 tls #ifdef notyet 1350 1.5.4.2 tls Static int32_t 1351 1.5.4.2 tls athn_ani_get_rssi(struct athn_softc *sc) 1352 1.5.4.2 tls { 1353 1.5.4.2 tls 1354 1.5.4.2 tls return 0; /* XXX */ 1355 1.5.4.2 tls } 1356 1.5.4.2 tls #endif /* notyet */ 1357 1.5.4.2 tls 1358 1.5.4.2 tls #ifdef notyet 1359 1.5.4.2 tls Static void 1360 1.5.4.2 tls athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1361 1.5.4.2 tls { 1362 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1363 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1364 1.5.4.2 tls int32_t rssi; 1365 1.5.4.2 tls 1366 1.5.4.2 tls /* First, raise noise immunity level, up to max. */ 1367 1.5.4.2 tls if (ani->noise_immunity_level < 4) { 1368 1.5.4.2 tls ani->noise_immunity_level++; 1369 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1370 1.5.4.2 tls return; 1371 1.5.4.2 tls } 1372 1.5.4.2 tls 1373 1.5.4.2 tls /* Then, raise our spur immunity level, up to max. */ 1374 1.5.4.2 tls if (ani->spur_immunity_level < 7) { 1375 1.5.4.2 tls ani->spur_immunity_level++; 1376 1.5.4.2 tls ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1377 1.5.4.2 tls return; 1378 1.5.4.2 tls } 1379 1.5.4.2 tls 1380 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1381 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1382 1.5.4.2 tls if (ani->firstep_level < 2) { 1383 1.5.4.2 tls ani->firstep_level++; 1384 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1385 1.5.4.2 tls } 1386 1.5.4.2 tls return; 1387 1.5.4.2 tls } 1388 1.5.4.2 tls #endif 1389 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1390 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1391 1.5.4.2 tls /* 1392 1.5.4.2 tls * Beacon RSSI is high, turn off OFDM weak signal detection 1393 1.5.4.2 tls * or raise first step level as last resort. 1394 1.5.4.2 tls */ 1395 1.5.4.2 tls if (ani->ofdm_weak_signal) { 1396 1.5.4.2 tls ani->ofdm_weak_signal = 0; 1397 1.5.4.2 tls ops->disable_ofdm_weak_signal(sc); 1398 1.5.4.2 tls ani->spur_immunity_level = 0; 1399 1.5.4.2 tls ops->set_spur_immunity_level(sc, 0); 1400 1.5.4.2 tls } 1401 1.5.4.2 tls else if (ani->firstep_level < 2) { 1402 1.5.4.2 tls ani->firstep_level++; 1403 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1404 1.5.4.2 tls } 1405 1.5.4.2 tls } 1406 1.5.4.2 tls else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1407 1.5.4.2 tls /* 1408 1.5.4.2 tls * Beacon RSSI is in mid range, we need OFDM weak signal 1409 1.5.4.2 tls * detection but we can raise first step level. 1410 1.5.4.2 tls */ 1411 1.5.4.2 tls if (!ani->ofdm_weak_signal) { 1412 1.5.4.2 tls ani->ofdm_weak_signal = 1; 1413 1.5.4.2 tls ops->enable_ofdm_weak_signal(sc); 1414 1.5.4.2 tls } 1415 1.5.4.2 tls if (ani->firstep_level < 2) { 1416 1.5.4.2 tls ani->firstep_level++; 1417 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1418 1.5.4.2 tls } 1419 1.5.4.2 tls } 1420 1.5.4.2 tls else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1421 1.5.4.2 tls /* 1422 1.5.4.2 tls * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1423 1.5.4.2 tls * signal detection and zero first step level to maximize 1424 1.5.4.2 tls * CCK sensitivity. 1425 1.5.4.2 tls */ 1426 1.5.4.2 tls if (ani->ofdm_weak_signal) { 1427 1.5.4.2 tls ani->ofdm_weak_signal = 0; 1428 1.5.4.2 tls ops->disable_ofdm_weak_signal(sc); 1429 1.5.4.2 tls } 1430 1.5.4.2 tls if (ani->firstep_level > 0) { 1431 1.5.4.2 tls ani->firstep_level = 0; 1432 1.5.4.2 tls ops->set_firstep_level(sc, 0); 1433 1.5.4.2 tls } 1434 1.5.4.2 tls } 1435 1.5.4.2 tls } 1436 1.5.4.2 tls #endif /* notyet */ 1437 1.5.4.2 tls 1438 1.5.4.2 tls #ifdef notyet 1439 1.5.4.2 tls Static void 1440 1.5.4.2 tls athn_ani_cck_err_trigger(struct athn_softc *sc) 1441 1.5.4.2 tls { 1442 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1443 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1444 1.5.4.2 tls int32_t rssi; 1445 1.5.4.2 tls 1446 1.5.4.2 tls /* Raise noise immunity level, up to max. */ 1447 1.5.4.2 tls if (ani->noise_immunity_level < 4) { 1448 1.5.4.2 tls ani->noise_immunity_level++; 1449 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1450 1.5.4.2 tls return; 1451 1.5.4.2 tls } 1452 1.5.4.2 tls 1453 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1454 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1455 1.5.4.2 tls if (ani->firstep_level < 2) { 1456 1.5.4.2 tls ani->firstep_level++; 1457 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1458 1.5.4.2 tls } 1459 1.5.4.2 tls return; 1460 1.5.4.2 tls } 1461 1.5.4.2 tls #endif 1462 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1463 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1464 1.5.4.2 tls /* 1465 1.5.4.2 tls * Beacon RSSI is in mid or high range, raise first step 1466 1.5.4.2 tls * level. 1467 1.5.4.2 tls */ 1468 1.5.4.2 tls if (ani->firstep_level < 2) { 1469 1.5.4.2 tls ani->firstep_level++; 1470 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1471 1.5.4.2 tls } 1472 1.5.4.2 tls } 1473 1.5.4.2 tls else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1474 1.5.4.2 tls /* 1475 1.5.4.2 tls * Beacon RSSI is low, zero first step level to maximize 1476 1.5.4.2 tls * CCK sensitivity. 1477 1.5.4.2 tls */ 1478 1.5.4.2 tls if (ani->firstep_level > 0) { 1479 1.5.4.2 tls ani->firstep_level = 0; 1480 1.5.4.2 tls ops->set_firstep_level(sc, 0); 1481 1.5.4.2 tls } 1482 1.5.4.2 tls } 1483 1.5.4.2 tls } 1484 1.5.4.2 tls #endif /* notyet */ 1485 1.5.4.2 tls 1486 1.5.4.2 tls #ifdef notyet 1487 1.5.4.2 tls Static void 1488 1.5.4.2 tls athn_ani_lower_immunity(struct athn_softc *sc) 1489 1.5.4.2 tls { 1490 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1491 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1492 1.5.4.2 tls int32_t rssi; 1493 1.5.4.2 tls 1494 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1495 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1496 1.5.4.2 tls if (ani->firstep_level > 0) { 1497 1.5.4.2 tls ani->firstep_level--; 1498 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1499 1.5.4.2 tls } 1500 1.5.4.2 tls return; 1501 1.5.4.2 tls } 1502 1.5.4.2 tls #endif 1503 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1504 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1505 1.5.4.2 tls /* 1506 1.5.4.2 tls * Beacon RSSI is high, leave OFDM weak signal detection 1507 1.5.4.2 tls * off or it may oscillate. 1508 1.5.4.2 tls */ 1509 1.5.4.2 tls } 1510 1.5.4.2 tls else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1511 1.5.4.2 tls /* 1512 1.5.4.2 tls * Beacon RSSI is in mid range, turn on OFDM weak signal 1513 1.5.4.2 tls * detection or lower first step level. 1514 1.5.4.2 tls */ 1515 1.5.4.2 tls if (!ani->ofdm_weak_signal) { 1516 1.5.4.2 tls ani->ofdm_weak_signal = 1; 1517 1.5.4.2 tls ops->enable_ofdm_weak_signal(sc); 1518 1.5.4.2 tls return; 1519 1.5.4.2 tls } 1520 1.5.4.2 tls if (ani->firstep_level > 0) { 1521 1.5.4.2 tls ani->firstep_level--; 1522 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1523 1.5.4.2 tls return; 1524 1.5.4.2 tls } 1525 1.5.4.2 tls } 1526 1.5.4.2 tls else { 1527 1.5.4.2 tls /* Beacon RSSI is low, lower first step level. */ 1528 1.5.4.2 tls if (ani->firstep_level > 0) { 1529 1.5.4.2 tls ani->firstep_level--; 1530 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1531 1.5.4.2 tls return; 1532 1.5.4.2 tls } 1533 1.5.4.2 tls } 1534 1.5.4.2 tls /* 1535 1.5.4.2 tls * Lower spur immunity level down to zero, or if all else fails, 1536 1.5.4.2 tls * lower noise immunity level down to zero. 1537 1.5.4.2 tls */ 1538 1.5.4.2 tls if (ani->spur_immunity_level > 0) { 1539 1.5.4.2 tls ani->spur_immunity_level--; 1540 1.5.4.2 tls ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1541 1.5.4.2 tls } 1542 1.5.4.2 tls else if (ani->noise_immunity_level > 0) { 1543 1.5.4.2 tls ani->noise_immunity_level--; 1544 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1545 1.5.4.2 tls } 1546 1.5.4.2 tls } 1547 1.5.4.2 tls #endif /* notyet */ 1548 1.5.4.2 tls 1549 1.5.4.2 tls #ifdef notyet 1550 1.5.4.2 tls Static void 1551 1.5.4.2 tls athn_ani_restart(struct athn_softc *sc) 1552 1.5.4.2 tls { 1553 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1554 1.5.4.2 tls 1555 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, 0); 1556 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, 0); 1557 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1558 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1559 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1560 1.5.4.2 tls 1561 1.5.4.2 tls ani->listen_time = 0; 1562 1.5.4.2 tls ani->ofdm_phy_err_count = 0; 1563 1.5.4.2 tls ani->cck_phy_err_count = 0; 1564 1.5.4.2 tls } 1565 1.5.4.2 tls #endif /* notyet */ 1566 1.5.4.2 tls 1567 1.5.4.2 tls #ifdef notyet 1568 1.5.4.2 tls Static void 1569 1.5.4.2 tls athn_ani_monitor(struct athn_softc *sc) 1570 1.5.4.2 tls { 1571 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1572 1.5.4.2 tls uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1573 1.5.4.2 tls int32_t cycdelta, txfdelta, rxfdelta; 1574 1.5.4.2 tls int32_t listen_time; 1575 1.5.4.2 tls 1576 1.5.4.2 tls txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1577 1.5.4.2 tls rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1578 1.5.4.2 tls cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1579 1.5.4.2 tls 1580 1.5.4.2 tls if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1581 1.5.4.2 tls cycdelta = cyccnt - ani->cyccnt; 1582 1.5.4.2 tls txfdelta = txfcnt - ani->txfcnt; 1583 1.5.4.2 tls rxfdelta = rxfcnt - ani->rxfcnt; 1584 1.5.4.2 tls 1585 1.5.4.2 tls listen_time = (cycdelta - txfdelta - rxfdelta) / 1586 1.5.4.2 tls (athn_clock_rate(sc) * 1000); 1587 1.5.4.2 tls } 1588 1.5.4.2 tls else 1589 1.5.4.2 tls listen_time = 0; 1590 1.5.4.2 tls 1591 1.5.4.2 tls ani->cyccnt = cyccnt; 1592 1.5.4.2 tls ani->txfcnt = txfcnt; 1593 1.5.4.2 tls ani->rxfcnt = rxfcnt; 1594 1.5.4.2 tls 1595 1.5.4.2 tls if (listen_time < 0) { 1596 1.5.4.2 tls athn_ani_restart(sc); 1597 1.5.4.2 tls return; 1598 1.5.4.2 tls } 1599 1.5.4.2 tls ani->listen_time += listen_time; 1600 1.5.4.2 tls 1601 1.5.4.2 tls phy1 = AR_READ(sc, AR_PHY_ERR_1); 1602 1.5.4.2 tls phy2 = AR_READ(sc, AR_PHY_ERR_2); 1603 1.5.4.2 tls 1604 1.5.4.2 tls if (phy1 < ani->ofdm_phy_err_base) { 1605 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1606 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1607 1.5.4.2 tls } 1608 1.5.4.2 tls if (phy2 < ani->cck_phy_err_base) { 1609 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1610 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1611 1.5.4.2 tls } 1612 1.5.4.2 tls if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1613 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1614 1.5.4.2 tls return; 1615 1.5.4.2 tls } 1616 1.5.4.2 tls ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1617 1.5.4.2 tls ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1618 1.5.4.2 tls 1619 1.5.4.2 tls if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1620 1.5.4.2 tls /* Check to see if we need to lower immunity. */ 1621 1.5.4.2 tls if (ani->ofdm_phy_err_count <= 1622 1.5.4.2 tls ani->listen_time * ani->ofdm_trig_low / 1000 && 1623 1.5.4.2 tls ani->cck_phy_err_count <= 1624 1.5.4.2 tls ani->listen_time * ani->cck_trig_low / 1000) 1625 1.5.4.2 tls athn_ani_lower_immunity(sc); 1626 1.5.4.2 tls athn_ani_restart(sc); 1627 1.5.4.2 tls 1628 1.5.4.2 tls } 1629 1.5.4.2 tls else if (ani->listen_time > ATHN_ANI_PERIOD) { 1630 1.5.4.2 tls /* Check to see if we need to raise immunity. */ 1631 1.5.4.2 tls if (ani->ofdm_phy_err_count > 1632 1.5.4.2 tls ani->listen_time * ani->ofdm_trig_high / 1000) { 1633 1.5.4.2 tls athn_ani_ofdm_err_trigger(sc); 1634 1.5.4.2 tls athn_ani_restart(sc); 1635 1.5.4.2 tls } 1636 1.5.4.2 tls else if (ani->cck_phy_err_count > 1637 1.5.4.2 tls ani->listen_time * ani->cck_trig_high / 1000) { 1638 1.5.4.2 tls athn_ani_cck_err_trigger(sc); 1639 1.5.4.2 tls athn_ani_restart(sc); 1640 1.5.4.2 tls } 1641 1.5.4.2 tls } 1642 1.5.4.2 tls } 1643 1.5.4.2 tls #endif /* notyet */ 1644 1.5.4.2 tls 1645 1.5.4.2 tls PUBLIC uint8_t 1646 1.5.4.2 tls athn_chan2fbin(struct ieee80211_channel *c) 1647 1.5.4.2 tls { 1648 1.5.4.2 tls 1649 1.5.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 1650 1.5.4.2 tls return c->ic_freq - 2300; 1651 1.5.4.2 tls else 1652 1.5.4.2 tls return (c->ic_freq - 4800) / 5; 1653 1.5.4.2 tls } 1654 1.5.4.2 tls 1655 1.5.4.2 tls PUBLIC int 1656 1.5.4.2 tls athn_interpolate(int x, int x1, int y1, int x2, int y2) 1657 1.5.4.2 tls { 1658 1.5.4.2 tls 1659 1.5.4.2 tls if (x1 == x2) /* Prevents division by zero. */ 1660 1.5.4.2 tls return y1; 1661 1.5.4.2 tls /* Linear interpolation. */ 1662 1.5.4.2 tls return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1663 1.5.4.2 tls } 1664 1.5.4.2 tls 1665 1.5.4.2 tls PUBLIC void 1666 1.5.4.2 tls athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1667 1.5.4.2 tls int *lo, int *hi) 1668 1.5.4.2 tls { 1669 1.5.4.2 tls int i; 1670 1.5.4.2 tls 1671 1.5.4.2 tls for (i = 0; i < npiers; i++) 1672 1.5.4.2 tls if (pierfreq[i] == AR_BCHAN_UNUSED || 1673 1.5.4.2 tls pierfreq[i] > fbin) 1674 1.5.4.2 tls break; 1675 1.5.4.2 tls *hi = i; 1676 1.5.4.2 tls *lo = *hi - 1; 1677 1.5.4.2 tls if (*lo == -1) 1678 1.5.4.2 tls *lo = *hi; 1679 1.5.4.2 tls else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1680 1.5.4.2 tls *hi = *lo; 1681 1.5.4.2 tls } 1682 1.5.4.2 tls 1683 1.5.4.2 tls Static void 1684 1.5.4.2 tls athn_init_dma(struct athn_softc *sc) 1685 1.5.4.2 tls { 1686 1.5.4.2 tls uint32_t reg; 1687 1.5.4.2 tls 1688 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 1689 1.5.4.2 tls /* Set AHB not to do cacheline prefetches. */ 1690 1.5.4.2 tls AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1691 1.5.4.2 tls } 1692 1.5.4.2 tls reg = AR_READ(sc, AR_TXCFG); 1693 1.5.4.2 tls /* Let MAC DMA reads be in 128-byte chunks. */ 1694 1.5.4.2 tls reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1695 1.5.4.2 tls 1696 1.5.4.2 tls /* Set initial Tx trigger level. */ 1697 1.5.4.2 tls if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1698 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1699 1.5.4.2 tls else if (!AR_SREV_9380_10_OR_LATER(sc)) 1700 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1701 1.5.4.2 tls AR_WRITE(sc, AR_TXCFG, reg); 1702 1.5.4.2 tls 1703 1.5.4.2 tls /* Let MAC DMA writes be in 128-byte chunks. */ 1704 1.5.4.2 tls reg = AR_READ(sc, AR_RXCFG); 1705 1.5.4.2 tls reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1706 1.5.4.2 tls AR_WRITE(sc, AR_RXCFG, reg); 1707 1.5.4.2 tls 1708 1.5.4.2 tls /* Setup Rx FIFO threshold to hold off Tx activities. */ 1709 1.5.4.2 tls AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1710 1.5.4.2 tls 1711 1.5.4.2 tls /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1712 1.5.4.2 tls if (AR_SREV_9285(sc)) { 1713 1.5.4.2 tls AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1714 1.5.4.2 tls AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1715 1.5.4.2 tls } 1716 1.5.4.2 tls else if (!AR_SREV_9271(sc)) { 1717 1.5.4.2 tls AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1718 1.5.4.2 tls AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1719 1.5.4.2 tls } 1720 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1721 1.5.4.2 tls 1722 1.5.4.2 tls /* Reset Tx status ring. */ 1723 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 1724 1.5.4.2 tls ar9003_reset_txsring(sc); 1725 1.5.4.2 tls } 1726 1.5.4.2 tls 1727 1.5.4.2 tls PUBLIC void 1728 1.5.4.2 tls athn_inc_tx_trigger_level(struct athn_softc *sc) 1729 1.5.4.2 tls { 1730 1.5.4.2 tls uint32_t reg, ftrig; 1731 1.5.4.2 tls 1732 1.5.4.2 tls reg = AR_READ(sc, AR_TXCFG); 1733 1.5.4.2 tls ftrig = MS(reg, AR_TXCFG_FTRIG); 1734 1.5.4.2 tls /* 1735 1.5.4.2 tls * NB: The AR9285 and all single-stream parts have an issue that 1736 1.5.4.2 tls * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1737 1.5.4.2 tls */ 1738 1.5.4.2 tls if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1739 1.5.4.2 tls return; /* Already at max. */ 1740 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1741 1.5.4.2 tls AR_WRITE(sc, AR_TXCFG, reg); 1742 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1743 1.5.4.2 tls } 1744 1.5.4.2 tls 1745 1.5.4.2 tls PUBLIC int 1746 1.5.4.2 tls athn_stop_rx_dma(struct athn_softc *sc) 1747 1.5.4.2 tls { 1748 1.5.4.2 tls int ntries; 1749 1.5.4.2 tls 1750 1.5.4.2 tls AR_WRITE(sc, AR_CR, AR_CR_RXD); 1751 1.5.4.2 tls /* Wait for Rx enable bit to go low. */ 1752 1.5.4.2 tls for (ntries = 0; ntries < 100; ntries++) { 1753 1.5.4.2 tls if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1754 1.5.4.2 tls return 0; 1755 1.5.4.2 tls DELAY(100); 1756 1.5.4.2 tls } 1757 1.5.4.2 tls DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1758 1.5.4.2 tls return ETIMEDOUT; 1759 1.5.4.2 tls } 1760 1.5.4.2 tls 1761 1.5.4.2 tls #ifdef unused 1762 1.5.4.2 tls Static int 1763 1.5.4.2 tls athn_rx_abort(struct athn_softc *sc) 1764 1.5.4.2 tls { 1765 1.5.4.2 tls int ntries; 1766 1.5.4.2 tls 1767 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1768 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 1769 1.5.4.2 tls if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1770 1.5.4.2 tls return 0; 1771 1.5.4.2 tls DELAY(10); 1772 1.5.4.2 tls } 1773 1.5.4.2 tls DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1774 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1775 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1776 1.5.4.2 tls return ETIMEDOUT; 1777 1.5.4.2 tls } 1778 1.5.4.2 tls #endif /* unused */ 1779 1.5.4.2 tls 1780 1.5.4.2 tls Static void 1781 1.5.4.2 tls athn_tx_reclaim(struct athn_softc *sc, int qid) 1782 1.5.4.2 tls { 1783 1.5.4.2 tls struct athn_txq *txq = &sc->sc_txq[qid]; 1784 1.5.4.2 tls struct athn_tx_buf *bf; 1785 1.5.4.2 tls 1786 1.5.4.2 tls /* Reclaim all buffers queued in the specified Tx queue. */ 1787 1.5.4.2 tls /* NB: Tx DMA must be stopped. */ 1788 1.5.4.2 tls while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1789 1.5.4.2 tls SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1790 1.5.4.2 tls 1791 1.5.4.2 tls bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1792 1.5.4.2 tls bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1793 1.5.4.2 tls bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1794 1.5.4.2 tls m_freem(bf->bf_m); 1795 1.5.4.2 tls bf->bf_m = NULL; 1796 1.5.4.2 tls bf->bf_ni = NULL; /* Nodes already freed! */ 1797 1.5.4.2 tls 1798 1.5.4.2 tls /* Link Tx buffer back to global free list. */ 1799 1.5.4.2 tls SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1800 1.5.4.2 tls } 1801 1.5.4.2 tls } 1802 1.5.4.2 tls 1803 1.5.4.2 tls PUBLIC int 1804 1.5.4.2 tls athn_tx_pending(struct athn_softc *sc, int qid) 1805 1.5.4.2 tls { 1806 1.5.4.2 tls 1807 1.5.4.2 tls return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1808 1.5.4.2 tls (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1809 1.5.4.2 tls } 1810 1.5.4.2 tls 1811 1.5.4.2 tls PUBLIC void 1812 1.5.4.2 tls athn_stop_tx_dma(struct athn_softc *sc, int qid) 1813 1.5.4.2 tls { 1814 1.5.4.2 tls uint32_t tsflo; 1815 1.5.4.2 tls int ntries, i; 1816 1.5.4.2 tls 1817 1.5.4.2 tls AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1818 1.5.4.2 tls for (ntries = 0; ntries < 40; ntries++) { 1819 1.5.4.2 tls if (!athn_tx_pending(sc, qid)) 1820 1.5.4.2 tls break; 1821 1.5.4.2 tls DELAY(100); 1822 1.5.4.2 tls } 1823 1.5.4.2 tls if (ntries == 40) { 1824 1.5.4.2 tls for (i = 0; i < 2; i++) { 1825 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1826 1.5.4.2 tls AR_WRITE(sc, AR_QUIET2, 1827 1.5.4.2 tls SM(AR_QUIET2_QUIET_DUR, 10)); 1828 1.5.4.2 tls AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1829 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1830 1.5.4.2 tls AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1831 1.5.4.2 tls if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1832 1.5.4.2 tls break; 1833 1.5.4.2 tls } 1834 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1835 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1836 1.5.4.2 tls DELAY(200); 1837 1.5.4.2 tls AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1838 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1839 1.5.4.2 tls 1840 1.5.4.2 tls for (ntries = 0; ntries < 40; ntries++) { 1841 1.5.4.2 tls if (!athn_tx_pending(sc, qid)) 1842 1.5.4.2 tls break; 1843 1.5.4.2 tls DELAY(100); 1844 1.5.4.2 tls } 1845 1.5.4.2 tls 1846 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1847 1.5.4.2 tls } 1848 1.5.4.2 tls AR_WRITE(sc, AR_Q_TXD, 0); 1849 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1850 1.5.4.2 tls } 1851 1.5.4.2 tls 1852 1.5.4.2 tls PUBLIC int 1853 1.5.4.2 tls athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1854 1.5.4.2 tls { 1855 1.5.4.2 tls #define divround(a, b) (((a) + (b) - 1) / (b)) 1856 1.5.4.2 tls int txtime; 1857 1.5.4.2 tls 1858 1.5.4.2 tls /* XXX HT. */ 1859 1.5.4.2 tls if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1860 1.5.4.2 tls txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1861 1.5.4.2 tls /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1862 1.5.4.2 tls txtime = 16 + 4 + 4 * txtime + 16; 1863 1.5.4.2 tls } 1864 1.5.4.2 tls else { 1865 1.5.4.2 tls txtime = divround(16 * len, athn_rates[ridx].rate); 1866 1.5.4.2 tls if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1867 1.5.4.2 tls txtime += 72 + 24; 1868 1.5.4.2 tls else 1869 1.5.4.2 tls txtime += 144 + 48; 1870 1.5.4.2 tls txtime += 10; /* 10us SIFS. */ 1871 1.5.4.2 tls } 1872 1.5.4.2 tls return txtime; 1873 1.5.4.2 tls #undef divround 1874 1.5.4.2 tls } 1875 1.5.4.2 tls 1876 1.5.4.2 tls PUBLIC void 1877 1.5.4.2 tls athn_init_tx_queues(struct athn_softc *sc) 1878 1.5.4.2 tls { 1879 1.5.4.2 tls int qid; 1880 1.5.4.2 tls 1881 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1882 1.5.4.2 tls SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1883 1.5.4.2 tls sc->sc_txq[qid].lastds = NULL; 1884 1.5.4.2 tls sc->sc_txq[qid].wait = NULL; 1885 1.5.4.2 tls sc->sc_txq[qid].queued = 0; 1886 1.5.4.2 tls 1887 1.5.4.2 tls AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1888 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1889 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1890 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1891 1.5.4.2 tls AR_WRITE(sc, AR_QMISC(qid), 1892 1.5.4.2 tls AR_Q_MISC_DCU_EARLY_TERM_REQ); 1893 1.5.4.2 tls AR_WRITE(sc, AR_DMISC(qid), 1894 1.5.4.2 tls SM(AR_D_MISC_BKOFF_THRESH, 2) | 1895 1.5.4.2 tls AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1896 1.5.4.2 tls } 1897 1.5.4.2 tls 1898 1.5.4.2 tls /* Init beacon queue. */ 1899 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1900 1.5.4.2 tls AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1901 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS1); 1902 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1903 1.5.4.2 tls SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1904 1.5.4.2 tls AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1905 1.5.4.2 tls AR_D_MISC_BEACON_USE | 1906 1.5.4.2 tls AR_D_MISC_POST_FR_BKOFF_DIS); 1907 1.5.4.2 tls AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1908 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMIN, 0) | 1909 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMAX, 0) | 1910 1.5.4.2 tls SM(AR_D_LCL_IFS_AIFS, 1)); 1911 1.5.4.2 tls 1912 1.5.4.2 tls /* Init CAB (Content After Beacon) queue. */ 1913 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1914 1.5.4.2 tls AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1915 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS0); 1916 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1917 1.5.4.2 tls SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1918 1.5.4.2 tls AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1919 1.5.4.2 tls 1920 1.5.4.2 tls /* Init PS-Poll queue. */ 1921 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1922 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS1); 1923 1.5.4.2 tls 1924 1.5.4.2 tls /* Init UAPSD queue. */ 1925 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1926 1.5.4.2 tls AR_D_MISC_POST_FR_BKOFF_DIS); 1927 1.5.4.2 tls 1928 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 1929 1.5.4.2 tls /* Enable MAC descriptor CRC check. */ 1930 1.5.4.2 tls AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1931 1.5.4.2 tls } 1932 1.5.4.2 tls /* Enable DESC interrupts for all Tx queues. */ 1933 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1934 1.5.4.2 tls /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1935 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1936 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1937 1.5.4.2 tls } 1938 1.5.4.2 tls 1939 1.5.4.2 tls PUBLIC void 1940 1.5.4.2 tls athn_set_sta_timers(struct athn_softc *sc) 1941 1.5.4.2 tls { 1942 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 1943 1.5.4.2 tls uint32_t tsfhi, tsflo, tsftu, reg; 1944 1.5.4.2 tls uint32_t intval, next_tbtt, next_dtim; 1945 1.5.4.3 tls int dtim_period, rem_dtim_count; 1946 1.5.4.2 tls 1947 1.5.4.2 tls tsfhi = AR_READ(sc, AR_TSF_U32); 1948 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32); 1949 1.5.4.2 tls tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1950 1.5.4.2 tls 1951 1.5.4.2 tls /* Beacon interval in TU. */ 1952 1.5.4.2 tls intval = ic->ic_bss->ni_intval; 1953 1.5.4.2 tls 1954 1.5.4.2 tls next_tbtt = roundup(tsftu, intval); 1955 1.5.4.2 tls #ifdef notyet 1956 1.5.4.2 tls dtim_period = ic->ic_dtim_period; 1957 1.5.4.2 tls if (dtim_period <= 0) 1958 1.5.4.2 tls #endif 1959 1.5.4.2 tls dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1960 1.5.4.2 tls 1961 1.5.4.2 tls #ifdef notyet 1962 1.5.4.3 tls int dtim_count = ic->ic_dtim_count; 1963 1.5.4.2 tls if (dtim_count >= dtim_period) /* Should not happen. */ 1964 1.5.4.2 tls dtim_count = 0; /* Assume last TIM was a DTIM. */ 1965 1.5.4.3 tls #endif 1966 1.5.4.2 tls 1967 1.5.4.2 tls /* Compute number of remaining TIMs until next DTIM. */ 1968 1.5.4.2 tls rem_dtim_count = 0; /* XXX */ 1969 1.5.4.2 tls next_dtim = next_tbtt + rem_dtim_count * intval; 1970 1.5.4.2 tls 1971 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1972 1.5.4.2 tls AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1973 1.5.4.2 tls AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1974 1.5.4.2 tls 1975 1.5.4.2 tls /* 1976 1.5.4.2 tls * Set the number of consecutive beacons to miss before raising 1977 1.5.4.2 tls * a BMISS interrupt to 10. 1978 1.5.4.2 tls */ 1979 1.5.4.2 tls reg = AR_READ(sc, AR_RSSI_THR); 1980 1.5.4.2 tls reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 1981 1.5.4.2 tls AR_WRITE(sc, AR_RSSI_THR, reg); 1982 1.5.4.2 tls 1983 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_DTIM, 1984 1.5.4.2 tls (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1985 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TIM, 1986 1.5.4.2 tls (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1987 1.5.4.2 tls 1988 1.5.4.2 tls /* CAB timeout is in 1/8 TU. */ 1989 1.5.4.2 tls AR_WRITE(sc, AR_SLEEP1, 1990 1.5.4.2 tls SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 1991 1.5.4.2 tls AR_SLEEP1_ASSUME_DTIM); 1992 1.5.4.2 tls AR_WRITE(sc, AR_SLEEP2, 1993 1.5.4.2 tls SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 1994 1.5.4.2 tls 1995 1.5.4.2 tls AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 1996 1.5.4.2 tls AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 1997 1.5.4.2 tls 1998 1.5.4.2 tls AR_SETBITS(sc, AR_TIMER_MODE, 1999 1.5.4.2 tls AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2000 1.5.4.2 tls 2001 1.5.4.2 tls /* Set TSF out-of-range threshold (fixed at 16k us). */ 2002 1.5.4.2 tls AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2003 1.5.4.2 tls 2004 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2005 1.5.4.2 tls } 2006 1.5.4.2 tls 2007 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2008 1.5.4.2 tls PUBLIC void 2009 1.5.4.2 tls athn_set_hostap_timers(struct athn_softc *sc) 2010 1.5.4.2 tls { 2011 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2012 1.5.4.2 tls uint32_t intval, next_tbtt; 2013 1.5.4.2 tls 2014 1.5.4.2 tls /* Beacon interval in TU. */ 2015 1.5.4.2 tls intval = ic->ic_bss->ni_intval; 2016 1.5.4.2 tls next_tbtt = intval; 2017 1.5.4.2 tls 2018 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2019 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2020 1.5.4.2 tls (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2021 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_CFP, 2022 1.5.4.2 tls (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2023 1.5.4.2 tls 2024 1.5.4.2 tls AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2025 1.5.4.2 tls AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2026 1.5.4.2 tls AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2027 1.5.4.2 tls AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2028 1.5.4.2 tls 2029 1.5.4.2 tls AR_WRITE(sc, AR_TIMER_MODE, 2030 1.5.4.2 tls AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2031 1.5.4.2 tls 2032 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2033 1.5.4.2 tls } 2034 1.5.4.2 tls #endif 2035 1.5.4.2 tls 2036 1.5.4.2 tls PUBLIC void 2037 1.5.4.2 tls athn_set_opmode(struct athn_softc *sc) 2038 1.5.4.2 tls { 2039 1.5.4.2 tls uint32_t reg; 2040 1.5.4.2 tls 2041 1.5.4.2 tls switch (sc->sc_ic.ic_opmode) { 2042 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2043 1.5.4.2 tls case IEEE80211_M_HOSTAP: 2044 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2045 1.5.4.2 tls reg &= ~AR_STA_ID1_ADHOC; 2046 1.5.4.2 tls reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2047 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2048 1.5.4.2 tls 2049 1.5.4.2 tls AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2050 1.5.4.2 tls break; 2051 1.5.4.2 tls case IEEE80211_M_IBSS: 2052 1.5.4.2 tls case IEEE80211_M_AHDEMO: 2053 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2054 1.5.4.2 tls reg &= ~AR_STA_ID1_STA_AP; 2055 1.5.4.2 tls reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2056 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2057 1.5.4.2 tls 2058 1.5.4.2 tls AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2059 1.5.4.2 tls break; 2060 1.5.4.2 tls #endif 2061 1.5.4.2 tls default: 2062 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2063 1.5.4.2 tls reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2064 1.5.4.2 tls reg |= AR_STA_ID1_KSRCH_MODE; 2065 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2066 1.5.4.2 tls break; 2067 1.5.4.2 tls } 2068 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2069 1.5.4.2 tls } 2070 1.5.4.2 tls 2071 1.5.4.2 tls PUBLIC void 2072 1.5.4.2 tls athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2073 1.5.4.2 tls { 2074 1.5.4.2 tls const uint8_t *bssid = ni->ni_bssid; 2075 1.5.4.2 tls 2076 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2077 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2078 1.5.4.2 tls SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2079 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2080 1.5.4.2 tls } 2081 1.5.4.2 tls 2082 1.5.4.2 tls Static void 2083 1.5.4.2 tls athn_enable_interrupts(struct athn_softc *sc) 2084 1.5.4.2 tls { 2085 1.5.4.2 tls uint32_t mask2; 2086 1.5.4.2 tls 2087 1.5.4.2 tls athn_disable_interrupts(sc); /* XXX */ 2088 1.5.4.2 tls 2089 1.5.4.2 tls AR_WRITE(sc, AR_IMR, sc->sc_imask); 2090 1.5.4.2 tls 2091 1.5.4.2 tls mask2 = AR_READ(sc, AR_IMR_S2); 2092 1.5.4.2 tls mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2093 1.5.4.2 tls AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2094 1.5.4.2 tls mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2095 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S2, mask2); 2096 1.5.4.2 tls 2097 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2098 1.5.4.2 tls 2099 1.5.4.2 tls AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2100 1.5.4.2 tls 2101 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2102 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2103 1.5.4.2 tls 2104 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2105 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2106 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2107 1.5.4.2 tls } 2108 1.5.4.2 tls 2109 1.5.4.2 tls Static void 2110 1.5.4.2 tls athn_disable_interrupts(struct athn_softc *sc) 2111 1.5.4.2 tls { 2112 1.5.4.2 tls 2113 1.5.4.2 tls AR_WRITE(sc, AR_IER, 0); 2114 1.5.4.2 tls (void)AR_READ(sc, AR_IER); 2115 1.5.4.2 tls 2116 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2117 1.5.4.2 tls (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2118 1.5.4.2 tls 2119 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2120 1.5.4.2 tls (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2121 1.5.4.2 tls 2122 1.5.4.2 tls AR_WRITE(sc, AR_IMR, 0); 2123 1.5.4.2 tls 2124 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2125 1.5.4.2 tls AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2126 1.5.4.2 tls AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2127 1.5.4.2 tls 2128 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2129 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2130 1.5.4.2 tls } 2131 1.5.4.2 tls 2132 1.5.4.2 tls Static void 2133 1.5.4.2 tls athn_init_qos(struct athn_softc *sc) 2134 1.5.4.2 tls { 2135 1.5.4.2 tls 2136 1.5.4.2 tls /* Initialize QoS settings. */ 2137 1.5.4.2 tls AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2138 1.5.4.2 tls AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2139 1.5.4.2 tls AR_WRITE(sc, AR_QOS_NO_ACK, 2140 1.5.4.2 tls SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2141 1.5.4.2 tls SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2142 1.5.4.2 tls SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2143 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2144 1.5.4.2 tls /* Initialize TXOP for all TIDs. */ 2145 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2146 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2147 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2148 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2149 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2150 1.5.4.2 tls } 2151 1.5.4.2 tls 2152 1.5.4.2 tls PUBLIC int 2153 1.5.4.2 tls athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2154 1.5.4.2 tls struct ieee80211_channel *extchan, int init) 2155 1.5.4.2 tls { 2156 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2157 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 2158 1.5.4.2 tls uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2159 1.5.4.2 tls int i, error; 2160 1.5.4.2 tls 2161 1.5.4.2 tls /* XXX not if already awake */ 2162 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 2163 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2164 1.5.4.2 tls return error; 2165 1.5.4.2 tls } 2166 1.5.4.2 tls 2167 1.5.4.2 tls /* Preserve the antenna on a channel switch. */ 2168 1.5.4.2 tls if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2169 1.5.4.2 tls def_ant = 1; 2170 1.5.4.2 tls /* Preserve other registers. */ 2171 1.5.4.2 tls sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2172 1.5.4.2 tls cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2173 1.5.4.2 tls AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2174 1.5.4.2 tls AR_CFG_LED_BLINK_SLOW); 2175 1.5.4.2 tls 2176 1.5.4.2 tls /* Mark PHY as inactive. */ 2177 1.5.4.2 tls ops->disable_phy(sc); 2178 1.5.4.2 tls 2179 1.5.4.2 tls if (init && AR_SREV_9271(sc)) { 2180 1.5.4.2 tls AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2181 1.5.4.2 tls AR9271_RADIO_RF_RST); 2182 1.5.4.2 tls DELAY(50); 2183 1.5.4.2 tls } 2184 1.5.4.2 tls if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2185 1.5.4.2 tls /* Save TSF before it gets cleared. */ 2186 1.5.4.2 tls tsfhi = AR_READ(sc, AR_TSF_U32); 2187 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32); 2188 1.5.4.2 tls 2189 1.5.4.2 tls /* NB: RTC reset clears TSF. */ 2190 1.5.4.2 tls error = athn_reset_power_on(sc); 2191 1.5.4.2 tls } 2192 1.5.4.2 tls else { 2193 1.5.4.2 tls tsfhi = tsflo = 0; /* XXX: gcc */ 2194 1.5.4.2 tls error = athn_reset(sc, 0); 2195 1.5.4.2 tls } 2196 1.5.4.2 tls if (error != 0) { 2197 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2198 1.5.4.2 tls "could not reset chip (error=%d)\n", error); 2199 1.5.4.2 tls return error; 2200 1.5.4.2 tls } 2201 1.5.4.2 tls 2202 1.5.4.2 tls /* XXX not if already awake */ 2203 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 2204 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2205 1.5.4.2 tls return error; 2206 1.5.4.2 tls } 2207 1.5.4.2 tls 2208 1.5.4.2 tls athn_init_pll(sc, curchan); 2209 1.5.4.2 tls ops->set_rf_mode(sc, curchan); 2210 1.5.4.2 tls 2211 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2212 1.5.4.2 tls /* Check that the radio is not disabled by hardware switch. */ 2213 1.5.4.2 tls reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2214 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2215 1.5.4.2 tls reg = !reg; 2216 1.5.4.2 tls if (!reg) { 2217 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2218 1.5.4.2 tls "radio is disabled by hardware switch\n"); 2219 1.5.4.2 tls return EPERM; 2220 1.5.4.2 tls } 2221 1.5.4.2 tls } 2222 1.5.4.2 tls if (init && AR_SREV_9271(sc)) { 2223 1.5.4.2 tls AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2224 1.5.4.2 tls AR9271_GATE_MAC_CTL); 2225 1.5.4.2 tls DELAY(50); 2226 1.5.4.2 tls } 2227 1.5.4.2 tls if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2228 1.5.4.2 tls /* Restore TSF if it got cleared. */ 2229 1.5.4.2 tls AR_WRITE(sc, AR_TSF_L32, tsflo); 2230 1.5.4.2 tls AR_WRITE(sc, AR_TSF_U32, tsfhi); 2231 1.5.4.2 tls } 2232 1.5.4.2 tls 2233 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc)) 2234 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2235 1.5.4.2 tls 2236 1.5.4.2 tls if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2237 1.5.4.2 tls ar9287_1_3_enable_async_fifo(sc); 2238 1.5.4.2 tls 2239 1.5.4.2 tls /* Write init values to hardware. */ 2240 1.5.4.2 tls ops->hw_init(sc, curchan, extchan); 2241 1.5.4.2 tls 2242 1.5.4.2 tls /* 2243 1.5.4.2 tls * Only >=AR9280 2.0 parts are capable of encrypting unicast 2244 1.5.4.2 tls * management frames using CCMP. 2245 1.5.4.2 tls */ 2246 1.5.4.2 tls if (AR_SREV_9280_20_OR_LATER(sc)) { 2247 1.5.4.2 tls reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2248 1.5.4.2 tls /* Do not mask the subtype field in management frames. */ 2249 1.5.4.2 tls reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2250 1.5.4.2 tls reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2251 1.5.4.2 tls ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2252 1.5.4.2 tls IEEE80211_FC1_MORE_DATA)); 2253 1.5.4.2 tls AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2254 1.5.4.2 tls } 2255 1.5.4.2 tls else if (AR_SREV_9160_10_OR_LATER(sc)) { 2256 1.5.4.2 tls /* Disable hardware crypto for management frames. */ 2257 1.5.4.2 tls AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2258 1.5.4.2 tls AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2259 1.5.4.2 tls AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2260 1.5.4.2 tls AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2261 1.5.4.2 tls } 2262 1.5.4.2 tls 2263 1.5.4.2 tls if (ic->ic_curmode != IEEE80211_MODE_11B) 2264 1.5.4.2 tls ops->set_delta_slope(sc, curchan, extchan); 2265 1.5.4.2 tls 2266 1.5.4.2 tls ops->spur_mitigate(sc, curchan, extchan); 2267 1.5.4.2 tls ops->init_from_rom(sc, curchan, extchan); 2268 1.5.4.2 tls 2269 1.5.4.2 tls /* XXX */ 2270 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2271 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2272 1.5.4.2 tls sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2273 1.5.4.2 tls 2274 1.5.4.2 tls athn_set_opmode(sc); 2275 1.5.4.2 tls 2276 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2277 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2278 1.5.4.2 tls 2279 1.5.4.2 tls /* Restore previous antenna. */ 2280 1.5.4.2 tls AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2281 1.5.4.2 tls 2282 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID0, 0); 2283 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID1, 0); 2284 1.5.4.2 tls 2285 1.5.4.2 tls AR_WRITE(sc, AR_ISR, 0xffffffff); 2286 1.5.4.2 tls 2287 1.5.4.2 tls AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2288 1.5.4.2 tls 2289 1.5.4.2 tls if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2290 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2291 1.5.4.2 tls return error; 2292 1.5.4.2 tls } 2293 1.5.4.2 tls sc->sc_curchan = curchan; 2294 1.5.4.2 tls sc->sc_curchanext = extchan; 2295 1.5.4.2 tls 2296 1.5.4.2 tls for (i = 0; i < AR_NUM_DCU; i++) 2297 1.5.4.2 tls AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2298 1.5.4.2 tls 2299 1.5.4.2 tls athn_init_tx_queues(sc); 2300 1.5.4.2 tls 2301 1.5.4.2 tls /* Initialize interrupt mask. */ 2302 1.5.4.2 tls sc->sc_imask = 2303 1.5.4.2 tls AR_IMR_TXDESC | AR_IMR_TXEOL | 2304 1.5.4.2 tls AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2305 1.5.4.2 tls AR_IMR_RXMINTR | AR_IMR_RXINTM | 2306 1.5.4.2 tls AR_IMR_GENTMR | AR_IMR_BCNMISC; 2307 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 2308 1.5.4.2 tls sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2309 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2310 1.5.4.2 tls if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2311 1.5.4.2 tls sc->sc_imask |= AR_IMR_MIB; 2312 1.5.4.2 tls #endif 2313 1.5.4.2 tls AR_WRITE(sc, AR_IMR, sc->sc_imask); 2314 1.5.4.2 tls AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2315 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2316 1.5.4.2 tls sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2317 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2318 1.5.4.2 tls sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2319 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2320 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2321 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 2322 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2323 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2324 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2325 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2326 1.5.4.2 tls } 2327 1.5.4.2 tls 2328 1.5.4.2 tls athn_init_qos(sc); 2329 1.5.4.2 tls 2330 1.5.4.2 tls AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2331 1.5.4.2 tls 2332 1.5.4.2 tls if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2333 1.5.4.2 tls ar9287_1_3_setup_async_fifo(sc); 2334 1.5.4.2 tls 2335 1.5.4.2 tls /* Disable sequence number generation in hardware. */ 2336 1.5.4.2 tls AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2337 1.5.4.2 tls 2338 1.5.4.2 tls athn_init_dma(sc); 2339 1.5.4.2 tls 2340 1.5.4.2 tls /* Program observation bus to see MAC interrupts. */ 2341 1.5.4.2 tls AR_WRITE(sc, sc->sc_obs_off, 8); 2342 1.5.4.2 tls 2343 1.5.4.2 tls /* Setup Rx interrupt mitigation. */ 2344 1.5.4.2 tls AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2345 1.5.4.2 tls 2346 1.5.4.2 tls ops->init_baseband(sc); 2347 1.5.4.2 tls 2348 1.5.4.2 tls if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2349 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2350 1.5.4.2 tls "could not initialize calibration\n"); 2351 1.5.4.2 tls return error; 2352 1.5.4.2 tls } 2353 1.5.4.2 tls 2354 1.5.4.2 tls ops->set_rxchains(sc); 2355 1.5.4.2 tls 2356 1.5.4.2 tls AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2357 1.5.4.2 tls 2358 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_USB) { 2359 1.5.4.2 tls if (AR_SREV_9271(sc)) 2360 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2361 1.5.4.2 tls else 2362 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2363 1.5.4.2 tls } 2364 1.5.4.2 tls #if BYTE_ORDER == BIG_ENDIAN 2365 1.5.4.2 tls else { 2366 1.5.4.2 tls /* Default is LE, turn on swapping for BE. */ 2367 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2368 1.5.4.2 tls } 2369 1.5.4.2 tls #endif 2370 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2371 1.5.4.2 tls 2372 1.5.4.2 tls return 0; 2373 1.5.4.2 tls } 2374 1.5.4.2 tls 2375 1.5.4.2 tls Static struct ieee80211_node * 2376 1.5.4.2 tls athn_node_alloc(struct ieee80211_node_table *ntp) 2377 1.5.4.2 tls { 2378 1.5.4.2 tls 2379 1.5.4.2 tls return malloc(sizeof(struct athn_node), M_DEVBUF, 2380 1.5.4.2 tls M_NOWAIT | M_ZERO); 2381 1.5.4.2 tls } 2382 1.5.4.2 tls 2383 1.5.4.2 tls Static void 2384 1.5.4.2 tls athn_newassoc(struct ieee80211_node *ni, int isnew) 2385 1.5.4.2 tls { 2386 1.5.4.2 tls struct ieee80211com *ic = ni->ni_ic; 2387 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 2388 1.5.4.2 tls struct athn_node *an = (void *)ni; 2389 1.5.4.2 tls struct ieee80211_rateset *rs = &ni->ni_rates; 2390 1.5.4.2 tls uint8_t rate; 2391 1.5.4.2 tls int ridx, i, j; 2392 1.5.4.2 tls 2393 1.5.4.2 tls ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2394 1.5.4.2 tls /* Start at lowest available bit-rate, AMRR will raise. */ 2395 1.5.4.2 tls ni->ni_txrate = 0; 2396 1.5.4.2 tls 2397 1.5.4.2 tls for (i = 0; i < rs->rs_nrates; i++) { 2398 1.5.4.2 tls rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2399 1.5.4.2 tls 2400 1.5.4.2 tls /* Map 802.11 rate to HW rate index. */ 2401 1.5.4.2 tls for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2402 1.5.4.2 tls if (athn_rates[ridx].rate == rate) 2403 1.5.4.2 tls break; 2404 1.5.4.2 tls an->ridx[i] = ridx; 2405 1.5.4.2 tls DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2406 1.5.4.2 tls 2407 1.5.4.2 tls /* Compute fallback rate for retries. */ 2408 1.5.4.2 tls an->fallback[i] = i; 2409 1.5.4.2 tls for (j = i - 1; j >= 0; j--) { 2410 1.5.4.2 tls if (athn_rates[an->ridx[j]].phy == 2411 1.5.4.2 tls athn_rates[an->ridx[i]].phy) { 2412 1.5.4.2 tls an->fallback[i] = j; 2413 1.5.4.2 tls break; 2414 1.5.4.2 tls } 2415 1.5.4.2 tls } 2416 1.5.4.2 tls DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2417 1.5.4.2 tls i, an->fallback[i]); 2418 1.5.4.2 tls } 2419 1.5.4.2 tls } 2420 1.5.4.2 tls 2421 1.5.4.2 tls Static int 2422 1.5.4.2 tls athn_media_change(struct ifnet *ifp) 2423 1.5.4.2 tls { 2424 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2425 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2426 1.5.4.2 tls uint8_t rate, ridx; 2427 1.5.4.2 tls int error; 2428 1.5.4.2 tls 2429 1.5.4.2 tls error = ieee80211_media_change(ifp); 2430 1.5.4.2 tls if (error != ENETRESET) 2431 1.5.4.2 tls return error; 2432 1.5.4.2 tls 2433 1.5.4.2 tls if (ic->ic_fixed_rate != -1) { 2434 1.5.4.2 tls rate = ic->ic_sup_rates[ic->ic_curmode]. 2435 1.5.4.2 tls rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2436 1.5.4.2 tls /* Map 802.11 rate to HW rate index. */ 2437 1.5.4.2 tls for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2438 1.5.4.2 tls if (athn_rates[ridx].rate == rate) 2439 1.5.4.2 tls break; 2440 1.5.4.2 tls sc->sc_fixed_ridx = ridx; 2441 1.5.4.2 tls } 2442 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp)) { 2443 1.5.4.2 tls athn_stop(ifp, 0); 2444 1.5.4.2 tls error = athn_init(ifp); 2445 1.5.4.2 tls } 2446 1.5.4.2 tls return error; 2447 1.5.4.2 tls } 2448 1.5.4.2 tls 2449 1.5.4.2 tls Static void 2450 1.5.4.2 tls athn_next_scan(void *arg) 2451 1.5.4.2 tls { 2452 1.5.4.2 tls struct athn_softc *sc = arg; 2453 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2454 1.5.4.2 tls int s; 2455 1.5.4.2 tls 2456 1.5.4.2 tls s = splnet(); 2457 1.5.4.2 tls if (ic->ic_state == IEEE80211_S_SCAN) 2458 1.5.4.2 tls ieee80211_next_scan(ic); 2459 1.5.4.2 tls splx(s); 2460 1.5.4.2 tls } 2461 1.5.4.2 tls 2462 1.5.4.2 tls Static int 2463 1.5.4.2 tls athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2464 1.5.4.2 tls { 2465 1.5.4.2 tls struct ifnet *ifp = ic->ic_ifp; 2466 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2467 1.5.4.2 tls uint32_t reg; 2468 1.5.4.2 tls int error; 2469 1.5.4.2 tls 2470 1.5.4.2 tls callout_stop(&sc->sc_calib_to); 2471 1.5.4.2 tls 2472 1.5.4.2 tls switch (nstate) { 2473 1.5.4.2 tls case IEEE80211_S_INIT: 2474 1.5.4.2 tls athn_set_led(sc, 0); 2475 1.5.4.2 tls break; 2476 1.5.4.2 tls case IEEE80211_S_SCAN: 2477 1.5.4.2 tls /* Make the LED blink while scanning. */ 2478 1.5.4.2 tls athn_set_led(sc, !sc->sc_led_state); 2479 1.5.4.2 tls error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2480 1.5.4.2 tls if (error != 0) 2481 1.5.4.2 tls return error; 2482 1.5.4.2 tls callout_schedule(&sc->sc_scan_to, hz / 5); 2483 1.5.4.2 tls break; 2484 1.5.4.2 tls case IEEE80211_S_AUTH: 2485 1.5.4.2 tls athn_set_led(sc, 0); 2486 1.5.4.2 tls error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2487 1.5.4.2 tls if (error != 0) 2488 1.5.4.2 tls return error; 2489 1.5.4.2 tls break; 2490 1.5.4.2 tls case IEEE80211_S_ASSOC: 2491 1.5.4.2 tls break; 2492 1.5.4.2 tls case IEEE80211_S_RUN: 2493 1.5.4.2 tls athn_set_led(sc, 1); 2494 1.5.4.2 tls 2495 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 2496 1.5.4.2 tls break; 2497 1.5.4.2 tls 2498 1.5.4.2 tls /* Fake a join to initialize the Tx rate. */ 2499 1.5.4.2 tls athn_newassoc(ic->ic_bss, 1); 2500 1.5.4.2 tls 2501 1.5.4.2 tls athn_set_bss(sc, ic->ic_bss); 2502 1.5.4.2 tls athn_disable_interrupts(sc); 2503 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2504 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2505 1.5.4.2 tls athn_set_hostap_timers(sc); 2506 1.5.4.2 tls /* Enable software beacon alert interrupts. */ 2507 1.5.4.2 tls sc->sc_imask |= AR_IMR_SWBA; 2508 1.5.4.2 tls } 2509 1.5.4.2 tls else 2510 1.5.4.2 tls #endif 2511 1.5.4.2 tls { 2512 1.5.4.2 tls athn_set_sta_timers(sc); 2513 1.5.4.2 tls /* Enable beacon miss interrupts. */ 2514 1.5.4.2 tls sc->sc_imask |= AR_IMR_BMISS; 2515 1.5.4.2 tls 2516 1.5.4.2 tls /* Stop receiving beacons from other BSS. */ 2517 1.5.4.2 tls reg = AR_READ(sc, AR_RX_FILTER); 2518 1.5.4.2 tls reg = (reg & ~AR_RX_FILTER_BEACON) | 2519 1.5.4.2 tls AR_RX_FILTER_MYBEACON; 2520 1.5.4.2 tls AR_WRITE(sc, AR_RX_FILTER, reg); 2521 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2522 1.5.4.2 tls } 2523 1.5.4.2 tls athn_enable_interrupts(sc); 2524 1.5.4.2 tls 2525 1.5.4.2 tls if (sc->sc_sup_calib_mask != 0) { 2526 1.5.4.2 tls memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2527 1.5.4.2 tls sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2528 1.5.4.2 tls /* ops->do_calib(sc); */ 2529 1.5.4.2 tls } 2530 1.5.4.2 tls /* XXX Start ANI. */ 2531 1.5.4.2 tls 2532 1.5.4.2 tls callout_schedule(&sc->sc_calib_to, hz / 2); 2533 1.5.4.2 tls break; 2534 1.5.4.2 tls } 2535 1.5.4.2 tls 2536 1.5.4.2 tls return sc->sc_newstate(ic, nstate, arg); 2537 1.5.4.2 tls } 2538 1.5.4.2 tls 2539 1.5.4.2 tls #ifdef notyet_edca 2540 1.5.4.2 tls PUBLIC void 2541 1.5.4.2 tls athn_updateedca(struct ieee80211com *ic) 2542 1.5.4.2 tls { 2543 1.5.4.2 tls #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2544 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 2545 1.5.4.2 tls const struct ieee80211_edca_ac_params *ac; 2546 1.5.4.2 tls int aci, qid; 2547 1.5.4.2 tls 2548 1.5.4.2 tls for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2549 1.5.4.2 tls ac = &ic->ic_edca_ac[aci]; 2550 1.5.4.2 tls qid = athn_ac2qid[aci]; 2551 1.5.4.2 tls 2552 1.5.4.2 tls AR_WRITE(sc, AR_DLCL_IFS(qid), 2553 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2554 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2555 1.5.4.2 tls SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2556 1.5.4.2 tls if (ac->ac_txoplimit != 0) { 2557 1.5.4.2 tls AR_WRITE(sc, AR_DCHNTIME(qid), 2558 1.5.4.2 tls SM(AR_D_CHNTIME_DUR, 2559 1.5.4.2 tls IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2560 1.5.4.2 tls AR_D_CHNTIME_EN); 2561 1.5.4.2 tls } 2562 1.5.4.2 tls else 2563 1.5.4.2 tls AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2564 1.5.4.2 tls } 2565 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2566 1.5.4.2 tls #undef ATHN_EXP2 2567 1.5.4.2 tls } 2568 1.5.4.2 tls #endif /* notyet_edca */ 2569 1.5.4.2 tls 2570 1.5.4.2 tls Static int 2571 1.5.4.2 tls athn_clock_rate(struct athn_softc *sc) 2572 1.5.4.2 tls { 2573 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2574 1.5.4.2 tls int clockrate; /* MHz. */ 2575 1.5.4.2 tls 2576 1.5.4.2 tls if (ic->ic_curmode == IEEE80211_MODE_11A) { 2577 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2578 1.5.4.2 tls clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2579 1.5.4.2 tls else 2580 1.5.4.2 tls clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2581 1.5.4.2 tls } 2582 1.5.4.2 tls else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2583 1.5.4.2 tls clockrate = AR_CLOCK_RATE_CCK; 2584 1.5.4.2 tls } 2585 1.5.4.2 tls else 2586 1.5.4.2 tls clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2587 1.5.4.2 tls #ifndef IEEE80211_NO_HT 2588 1.5.4.2 tls if (sc->sc_curchanext != NULL) 2589 1.5.4.2 tls clockrate *= 2; 2590 1.5.4.2 tls #endif 2591 1.5.4.2 tls return clockrate; 2592 1.5.4.2 tls } 2593 1.5.4.2 tls 2594 1.5.4.2 tls PUBLIC void 2595 1.5.4.2 tls athn_updateslot(struct ifnet *ifp) 2596 1.5.4.2 tls { 2597 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2598 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2599 1.5.4.2 tls int slot; 2600 1.5.4.2 tls 2601 1.5.4.2 tls slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2602 1.5.4.2 tls AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2603 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2604 1.5.4.2 tls } 2605 1.5.4.2 tls 2606 1.5.4.2 tls Static void 2607 1.5.4.2 tls athn_start(struct ifnet *ifp) 2608 1.5.4.2 tls { 2609 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2610 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2611 1.5.4.2 tls struct ether_header *eh; 2612 1.5.4.2 tls struct ieee80211_node *ni; 2613 1.5.4.2 tls struct mbuf *m; 2614 1.5.4.2 tls 2615 1.5.4.2 tls if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2616 1.5.4.2 tls || !device_is_active(sc->sc_dev)) 2617 1.5.4.2 tls return; 2618 1.5.4.2 tls 2619 1.5.4.2 tls for (;;) { 2620 1.5.4.2 tls if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2621 1.5.4.2 tls ifp->if_flags |= IFF_OACTIVE; 2622 1.5.4.2 tls break; 2623 1.5.4.2 tls } 2624 1.5.4.2 tls /* Send pending management frames first. */ 2625 1.5.4.2 tls IF_DEQUEUE(&ic->ic_mgtq, m); 2626 1.5.4.2 tls if (m != NULL) { 2627 1.5.4.2 tls ni = (void *)m->m_pkthdr.rcvif; 2628 1.5.4.2 tls goto sendit; 2629 1.5.4.2 tls } 2630 1.5.4.2 tls if (ic->ic_state != IEEE80211_S_RUN) 2631 1.5.4.2 tls break; 2632 1.5.4.2 tls 2633 1.5.4.2 tls /* Encapsulate and send data frames. */ 2634 1.5.4.2 tls IFQ_DEQUEUE(&ifp->if_snd, m); 2635 1.5.4.2 tls if (m == NULL) 2636 1.5.4.2 tls break; 2637 1.5.4.2 tls 2638 1.5.4.2 tls if (m->m_len < (int)sizeof(*eh) && 2639 1.5.4.2 tls (m = m_pullup(m, sizeof(*eh))) == NULL) { 2640 1.5.4.2 tls ifp->if_oerrors++; 2641 1.5.4.2 tls continue; 2642 1.5.4.2 tls } 2643 1.5.4.2 tls eh = mtod(m, struct ether_header *); 2644 1.5.4.2 tls ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2645 1.5.4.2 tls if (ni == NULL) { 2646 1.5.4.2 tls m_freem(m); 2647 1.5.4.2 tls ifp->if_oerrors++; 2648 1.5.4.2 tls continue; 2649 1.5.4.2 tls } 2650 1.5.4.2 tls 2651 1.5.4.2 tls bpf_mtap(ifp, m); 2652 1.5.4.2 tls 2653 1.5.4.2 tls if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2654 1.5.4.2 tls continue; 2655 1.5.4.2 tls sendit: 2656 1.5.4.2 tls bpf_mtap3(ic->ic_rawbpf, m); 2657 1.5.4.2 tls 2658 1.5.4.2 tls if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2659 1.5.4.2 tls ieee80211_free_node(ni); 2660 1.5.4.2 tls ifp->if_oerrors++; 2661 1.5.4.2 tls continue; 2662 1.5.4.2 tls } 2663 1.5.4.2 tls 2664 1.5.4.2 tls sc->sc_tx_timer = 5; 2665 1.5.4.2 tls ifp->if_timer = 1; 2666 1.5.4.2 tls } 2667 1.5.4.2 tls } 2668 1.5.4.2 tls 2669 1.5.4.2 tls Static void 2670 1.5.4.2 tls athn_watchdog(struct ifnet *ifp) 2671 1.5.4.2 tls { 2672 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2673 1.5.4.2 tls 2674 1.5.4.2 tls ifp->if_timer = 0; 2675 1.5.4.2 tls 2676 1.5.4.2 tls if (sc->sc_tx_timer > 0) { 2677 1.5.4.2 tls if (--sc->sc_tx_timer == 0) { 2678 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "device timeout\n"); 2679 1.5.4.3 tls /* see athn_init, no need to call athn_stop here */ 2680 1.5.4.3 tls /* athn_stop(ifp, 0); */ 2681 1.5.4.2 tls (void)athn_init(ifp); 2682 1.5.4.2 tls ifp->if_oerrors++; 2683 1.5.4.2 tls return; 2684 1.5.4.2 tls } 2685 1.5.4.2 tls ifp->if_timer = 1; 2686 1.5.4.2 tls } 2687 1.5.4.2 tls ieee80211_watchdog(&sc->sc_ic); 2688 1.5.4.2 tls } 2689 1.5.4.2 tls 2690 1.5.4.2 tls #ifdef notyet 2691 1.5.4.2 tls Static void 2692 1.5.4.2 tls athn_set_multi(struct athn_softc *sc) 2693 1.5.4.2 tls { 2694 1.5.4.2 tls struct arpcom *ac = &sc->sc_ic.ic_ac; 2695 1.5.4.2 tls struct ifnet *ifp = &ac->ac_if; 2696 1.5.4.2 tls struct ether_multi *enm; 2697 1.5.4.2 tls struct ether_multistep step; 2698 1.5.4.2 tls const uint8_t *addr; 2699 1.5.4.2 tls uint32_t val, lo, hi; 2700 1.5.4.2 tls uint8_t bit; 2701 1.5.4.2 tls 2702 1.5.4.2 tls if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2703 1.5.4.2 tls lo = hi = 0xffffffff; 2704 1.5.4.2 tls goto done; 2705 1.5.4.2 tls } 2706 1.5.4.2 tls lo = hi = 0; 2707 1.5.4.2 tls ETHER_FIRST_MULTI(step, ac, enm); 2708 1.5.4.2 tls while (enm != NULL) { 2709 1.5.4.2 tls if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2710 1.5.4.2 tls ifp->if_flags |= IFF_ALLMULTI; 2711 1.5.4.2 tls lo = hi = 0xffffffff; 2712 1.5.4.2 tls goto done; 2713 1.5.4.2 tls } 2714 1.5.4.2 tls addr = enm->enm_addrlo; 2715 1.5.4.2 tls /* Calculate the XOR value of all eight 6-bit words. */ 2716 1.5.4.2 tls val = addr[0] | addr[1] << 8 | addr[2] << 16; 2717 1.5.4.2 tls bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2718 1.5.4.2 tls val = addr[3] | addr[4] << 8 | addr[5] << 16; 2719 1.5.4.2 tls bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2720 1.5.4.2 tls bit &= 0x3f; 2721 1.5.4.2 tls if (bit < 32) 2722 1.5.4.2 tls lo |= 1 << bit; 2723 1.5.4.2 tls else 2724 1.5.4.2 tls hi |= 1 << (bit - 32); 2725 1.5.4.2 tls ETHER_NEXT_MULTI(step, enm); 2726 1.5.4.2 tls } 2727 1.5.4.2 tls done: 2728 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL0, lo); 2729 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL1, hi); 2730 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2731 1.5.4.2 tls } 2732 1.5.4.2 tls #endif /* notyet */ 2733 1.5.4.2 tls 2734 1.5.4.2 tls Static int 2735 1.5.4.2 tls athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2736 1.5.4.2 tls { 2737 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2738 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2739 1.5.4.2 tls int s, error = 0; 2740 1.5.4.2 tls 2741 1.5.4.2 tls s = splnet(); 2742 1.5.4.2 tls 2743 1.5.4.2 tls switch (cmd) { 2744 1.5.4.2 tls case SIOCSIFFLAGS: 2745 1.5.4.2 tls if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2746 1.5.4.2 tls break; 2747 1.5.4.2 tls 2748 1.5.4.2 tls switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2749 1.5.4.2 tls case IFF_UP | IFF_RUNNING: 2750 1.5.4.2 tls #ifdef notyet 2751 1.5.4.2 tls if (((ifp->if_flags ^ sc->sc_if_flags) & 2752 1.5.4.2 tls (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2753 1.5.4.2 tls /* XXX: setup multi */ 2754 1.5.4.2 tls #endif 2755 1.5.4.2 tls break; 2756 1.5.4.2 tls case IFF_UP: 2757 1.5.4.2 tls athn_init(ifp); 2758 1.5.4.2 tls break; 2759 1.5.4.2 tls 2760 1.5.4.2 tls case IFF_RUNNING: 2761 1.5.4.2 tls athn_stop(ifp, 1); 2762 1.5.4.2 tls break; 2763 1.5.4.2 tls case 0: 2764 1.5.4.2 tls default: 2765 1.5.4.2 tls break; 2766 1.5.4.2 tls } 2767 1.5.4.2 tls sc->sc_if_flags = ifp->if_flags; 2768 1.5.4.2 tls break; 2769 1.5.4.2 tls 2770 1.5.4.2 tls case SIOCADDMULTI: 2771 1.5.4.2 tls case SIOCDELMULTI: 2772 1.5.4.2 tls if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2773 1.5.4.2 tls /* setup multicast filter, etc */ 2774 1.5.4.2 tls #ifdef notyet 2775 1.5.4.2 tls athn_set_multi(sc); 2776 1.5.4.2 tls #endif 2777 1.5.4.2 tls error = 0; 2778 1.5.4.2 tls } 2779 1.5.4.2 tls break; 2780 1.5.4.2 tls 2781 1.5.4.2 tls case SIOCS80211CHANNEL: 2782 1.5.4.2 tls error = ieee80211_ioctl(ic, cmd, data); 2783 1.5.4.2 tls if (error == ENETRESET && 2784 1.5.4.2 tls ic->ic_opmode == IEEE80211_M_MONITOR) { 2785 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp)) 2786 1.5.4.2 tls athn_switch_chan(sc, ic->ic_curchan, NULL); 2787 1.5.4.2 tls error = 0; 2788 1.5.4.2 tls } 2789 1.5.4.2 tls break; 2790 1.5.4.2 tls 2791 1.5.4.2 tls default: 2792 1.5.4.2 tls error = ieee80211_ioctl(ic, cmd, data); 2793 1.5.4.2 tls } 2794 1.5.4.2 tls 2795 1.5.4.2 tls if (error == ENETRESET) { 2796 1.5.4.2 tls error = 0; 2797 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp) && 2798 1.5.4.2 tls ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2799 1.5.4.2 tls athn_stop(ifp, 0); 2800 1.5.4.2 tls error = athn_init(ifp); 2801 1.5.4.2 tls } 2802 1.5.4.2 tls } 2803 1.5.4.2 tls 2804 1.5.4.2 tls splx(s); 2805 1.5.4.2 tls return error; 2806 1.5.4.2 tls } 2807 1.5.4.2 tls 2808 1.5.4.2 tls Static int 2809 1.5.4.2 tls athn_init(struct ifnet *ifp) 2810 1.5.4.2 tls { 2811 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2812 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 2813 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2814 1.5.4.2 tls struct ieee80211_channel *curchan, *extchan; 2815 1.5.4.2 tls size_t i; 2816 1.5.4.2 tls int error; 2817 1.5.4.2 tls 2818 1.5.4.2 tls KASSERT(!cpu_intr_p()); 2819 1.5.4.2 tls 2820 1.5.4.2 tls if (device_is_active(sc->sc_dev)) { 2821 1.5.4.3 tls athn_stop(ifp, 0); /* see athn_watchdog() */ 2822 1.5.4.2 tls } else { 2823 1.5.4.2 tls short flags = ifp->if_flags; 2824 1.5.4.2 tls ifp->if_flags &= ~IFF_UP; 2825 1.5.4.2 tls /* avoid recursion in athn_resume */ 2826 1.5.4.2 tls if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2827 1.5.4.2 tls !device_is_active(sc->sc_dev)) { 2828 1.5.4.3 tls aprint_error_dev(sc->sc_dev, 2829 1.5.4.3 tls "failed to power up device\n"); 2830 1.5.4.2 tls return 0; 2831 1.5.4.2 tls } 2832 1.5.4.2 tls ifp->if_flags = flags; 2833 1.5.4.2 tls } 2834 1.5.4.2 tls 2835 1.5.4.2 tls curchan = ic->ic_curchan; 2836 1.5.4.2 tls extchan = NULL; 2837 1.5.4.2 tls 2838 1.5.4.2 tls /* In case a new MAC address has been configured. */ 2839 1.5.4.2 tls IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2840 1.5.4.2 tls 2841 1.5.4.2 tls #ifdef openbsd_power_management 2842 1.5.4.2 tls /* For CardBus, power on the socket. */ 2843 1.5.4.2 tls if (sc->sc_enable != NULL) { 2844 1.5.4.2 tls if ((error = sc->sc_enable(sc)) != 0) { 2845 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2846 1.5.4.2 tls "could not enable device\n"); 2847 1.5.4.2 tls goto fail; 2848 1.5.4.2 tls } 2849 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) { 2850 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2851 1.5.4.2 tls "could not power on device\n"); 2852 1.5.4.2 tls goto fail; 2853 1.5.4.2 tls } 2854 1.5.4.2 tls } 2855 1.5.4.2 tls #endif 2856 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2857 1.5.4.2 tls athn_config_nonpcie(sc); 2858 1.5.4.2 tls else 2859 1.5.4.2 tls athn_config_pcie(sc); 2860 1.5.4.2 tls 2861 1.5.4.2 tls /* Reset HW key cache entries. */ 2862 1.5.4.2 tls for (i = 0; i < sc->sc_kc_entries; i++) 2863 1.5.4.2 tls athn_reset_key(sc, i); 2864 1.5.4.2 tls 2865 1.5.4.2 tls ops->enable_antenna_diversity(sc); 2866 1.5.4.2 tls 2867 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 2868 1.5.4.2 tls /* Configure bluetooth coexistence for combo chips. */ 2869 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2870 1.5.4.2 tls athn_btcoex_init(sc); 2871 1.5.4.2 tls #endif 2872 1.5.4.2 tls 2873 1.5.4.2 tls /* Configure LED. */ 2874 1.5.4.2 tls athn_led_init(sc); 2875 1.5.4.2 tls 2876 1.5.4.2 tls /* Configure hardware radio switch. */ 2877 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2878 1.5.4.2 tls ops->rfsilent_init(sc); 2879 1.5.4.2 tls 2880 1.5.4.2 tls if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2881 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2882 1.5.4.2 tls "unable to reset hardware; reset status %d\n", error); 2883 1.5.4.2 tls goto fail; 2884 1.5.4.2 tls } 2885 1.5.4.2 tls 2886 1.5.4.2 tls /* Enable Rx. */ 2887 1.5.4.2 tls athn_rx_start(sc); 2888 1.5.4.2 tls 2889 1.5.4.2 tls /* Enable interrupts. */ 2890 1.5.4.2 tls athn_enable_interrupts(sc); 2891 1.5.4.2 tls 2892 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 2893 1.5.4.2 tls /* Enable bluetooth coexistence for combo chips. */ 2894 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2895 1.5.4.2 tls athn_btcoex_enable(sc); 2896 1.5.4.2 tls #endif 2897 1.5.4.2 tls 2898 1.5.4.2 tls ifp->if_flags &= ~IFF_OACTIVE; 2899 1.5.4.2 tls ifp->if_flags |= IFF_RUNNING; 2900 1.5.4.2 tls 2901 1.5.4.2 tls #ifdef notyet 2902 1.5.4.2 tls if (ic->ic_flags & IEEE80211_F_WEPON) { 2903 1.5.4.2 tls /* Configure WEP keys. */ 2904 1.5.4.2 tls for (i = 0; i < IEEE80211_WEP_NKID; i++) 2905 1.5.4.2 tls athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2906 1.5.4.2 tls } 2907 1.5.4.2 tls #endif 2908 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 2909 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2910 1.5.4.2 tls else 2911 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2912 1.5.4.2 tls 2913 1.5.4.2 tls return 0; 2914 1.5.4.2 tls fail: 2915 1.5.4.2 tls athn_stop(ifp, 1); 2916 1.5.4.2 tls return error; 2917 1.5.4.2 tls } 2918 1.5.4.2 tls 2919 1.5.4.2 tls PUBLIC void 2920 1.5.4.2 tls athn_stop(struct ifnet *ifp, int disable) 2921 1.5.4.2 tls { 2922 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2923 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2924 1.5.4.2 tls int qid; 2925 1.5.4.2 tls 2926 1.5.4.2 tls ifp->if_timer = sc->sc_tx_timer = 0; 2927 1.5.4.2 tls ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2928 1.5.4.2 tls 2929 1.5.4.2 tls callout_stop(&sc->sc_scan_to); 2930 1.5.4.2 tls /* In case we were scanning, release the scan "lock". */ 2931 1.5.4.2 tls // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2932 1.5.4.2 tls 2933 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2934 1.5.4.2 tls 2935 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 2936 1.5.4.2 tls /* Disable bluetooth coexistence for combo chips. */ 2937 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2938 1.5.4.2 tls athn_btcoex_disable(sc); 2939 1.5.4.2 tls #endif 2940 1.5.4.2 tls 2941 1.5.4.2 tls /* Disable interrupts. */ 2942 1.5.4.2 tls athn_disable_interrupts(sc); 2943 1.5.4.2 tls /* Acknowledge interrupts (avoids interrupt storms). */ 2944 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2945 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2946 1.5.4.2 tls 2947 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2948 1.5.4.2 tls athn_stop_tx_dma(sc, qid); 2949 1.5.4.2 tls /* XXX call athn_hw_reset if Tx still pending? */ 2950 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2951 1.5.4.2 tls athn_tx_reclaim(sc, qid); 2952 1.5.4.2 tls 2953 1.5.4.2 tls /* Stop Rx. */ 2954 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2955 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2956 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2957 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 2958 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 2959 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2960 1.5.4.2 tls athn_set_rxfilter(sc, 0); 2961 1.5.4.2 tls athn_stop_rx_dma(sc); 2962 1.5.4.2 tls 2963 1.5.4.2 tls athn_reset(sc, 0); 2964 1.5.4.2 tls athn_init_pll(sc, NULL); 2965 1.5.4.2 tls athn_set_power_awake(sc); 2966 1.5.4.2 tls athn_reset(sc, 1); 2967 1.5.4.2 tls athn_init_pll(sc, NULL); 2968 1.5.4.2 tls 2969 1.5.4.2 tls athn_set_power_sleep(sc); 2970 1.5.4.2 tls 2971 1.5.4.2 tls #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 2972 1.5.4.2 tls /* For CardBus, power down the socket. */ 2973 1.5.4.2 tls if (disable && sc->sc_disable != NULL) 2974 1.5.4.2 tls sc->sc_disable(sc); 2975 1.5.4.2 tls #endif 2976 1.5.4.2 tls if (disable) 2977 1.5.4.2 tls pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2978 1.5.4.2 tls } 2979 1.5.4.2 tls 2980 1.5.4.2 tls Static void 2981 1.5.4.2 tls athn_pmf_wlan_off(device_t self) 2982 1.5.4.2 tls { 2983 1.5.4.2 tls struct athn_softc *sc = device_private(self); 2984 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 2985 1.5.4.2 tls 2986 1.5.4.2 tls /* Turn the interface down. */ 2987 1.5.4.2 tls ifp->if_flags &= ~IFF_UP; 2988 1.5.4.2 tls athn_stop(ifp, 1); 2989 1.5.4.2 tls } 2990 1.5.4.2 tls 2991 1.5.4.2 tls PUBLIC void 2992 1.5.4.2 tls athn_suspend(struct athn_softc *sc) 2993 1.5.4.2 tls { 2994 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 2995 1.5.4.2 tls 2996 1.5.4.2 tls if (ifp->if_flags & IFF_RUNNING) 2997 1.5.4.2 tls athn_stop(ifp, 1); 2998 1.5.4.2 tls } 2999 1.5.4.2 tls 3000 1.5.4.2 tls PUBLIC bool 3001 1.5.4.2 tls athn_resume(struct athn_softc *sc) 3002 1.5.4.2 tls { 3003 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 3004 1.5.4.2 tls 3005 1.5.4.2 tls if (ifp->if_flags & IFF_UP) 3006 1.5.4.2 tls athn_init(ifp); 3007 1.5.4.2 tls 3008 1.5.4.2 tls return true; 3009 1.5.4.2 tls } 3010
Indexes created Wed Oct 15 16:09:53 GMT 2025