athn.c revision 1.5.4.4
1 1.5.4.2 tls /* $NetBSD: athn.c,v 1.5.4.4 2017/12/03 11:37:03 jdolecek Exp $ */ 2 1.5.4.3 tls /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 1.5.4.2 tls 4 1.5.4.2 tls /*- 5 1.5.4.2 tls * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.5.4.2 tls * Copyright (c) 2008-2010 Atheros Communications Inc. 7 1.5.4.2 tls * 8 1.5.4.2 tls * Permission to use, copy, modify, and/or distribute this software for any 9 1.5.4.2 tls * purpose with or without fee is hereby granted, provided that the above 10 1.5.4.2 tls * copyright notice and this permission notice appear in all copies. 11 1.5.4.2 tls * 12 1.5.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.5.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.5.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.5.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.5.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.5.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.5.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.5.4.2 tls */ 20 1.5.4.2 tls 21 1.5.4.2 tls /* 22 1.5.4.2 tls * Driver for Atheros 802.11a/g/n chipsets. 23 1.5.4.2 tls */ 24 1.5.4.2 tls 25 1.5.4.2 tls #include <sys/cdefs.h> 26 1.5.4.2 tls __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.5.4.4 2017/12/03 11:37:03 jdolecek Exp $"); 27 1.5.4.2 tls 28 1.5.4.2 tls #ifndef _MODULE 29 1.5.4.2 tls #include "athn_usb.h" /* for NATHN_USB */ 30 1.5.4.2 tls #endif 31 1.5.4.2 tls 32 1.5.4.2 tls #include <sys/param.h> 33 1.5.4.2 tls #include <sys/sockio.h> 34 1.5.4.2 tls #include <sys/mbuf.h> 35 1.5.4.2 tls #include <sys/kernel.h> 36 1.5.4.2 tls #include <sys/socket.h> 37 1.5.4.2 tls #include <sys/systm.h> 38 1.5.4.2 tls #include <sys/malloc.h> 39 1.5.4.2 tls #include <sys/queue.h> 40 1.5.4.2 tls #include <sys/callout.h> 41 1.5.4.2 tls #include <sys/conf.h> 42 1.5.4.2 tls #include <sys/cpu.h> 43 1.5.4.2 tls #include <sys/device.h> 44 1.5.4.2 tls 45 1.5.4.2 tls #include <sys/bus.h> 46 1.5.4.2 tls #include <sys/endian.h> 47 1.5.4.2 tls #include <sys/intr.h> 48 1.5.4.2 tls 49 1.5.4.2 tls #include <net/bpf.h> 50 1.5.4.2 tls #include <net/if.h> 51 1.5.4.2 tls #include <net/if_arp.h> 52 1.5.4.2 tls #include <net/if_dl.h> 53 1.5.4.2 tls #include <net/if_ether.h> 54 1.5.4.2 tls #include <net/if_media.h> 55 1.5.4.2 tls #include <net/if_types.h> 56 1.5.4.2 tls 57 1.5.4.2 tls #include <netinet/in.h> 58 1.5.4.2 tls #include <netinet/in_systm.h> 59 1.5.4.2 tls #include <netinet/in_var.h> 60 1.5.4.2 tls #include <netinet/ip.h> 61 1.5.4.2 tls 62 1.5.4.2 tls #include <net80211/ieee80211_var.h> 63 1.5.4.2 tls #include <net80211/ieee80211_amrr.h> 64 1.5.4.2 tls #include <net80211/ieee80211_radiotap.h> 65 1.5.4.2 tls 66 1.5.4.2 tls #include <dev/ic/athnreg.h> 67 1.5.4.2 tls #include <dev/ic/athnvar.h> 68 1.5.4.2 tls #include <dev/ic/arn5008.h> 69 1.5.4.2 tls #include <dev/ic/arn5416.h> 70 1.5.4.2 tls #include <dev/ic/arn9003.h> 71 1.5.4.2 tls #include <dev/ic/arn9280.h> 72 1.5.4.2 tls #include <dev/ic/arn9285.h> 73 1.5.4.2 tls #include <dev/ic/arn9287.h> 74 1.5.4.2 tls #include <dev/ic/arn9380.h> 75 1.5.4.2 tls 76 1.5.4.2 tls #define Static static 77 1.5.4.2 tls 78 1.5.4.2 tls #define IS_UP_AND_RUNNING(ifp) \ 79 1.5.4.2 tls (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 1.5.4.2 tls 81 1.5.4.2 tls #ifdef ATHN_DEBUG 82 1.5.4.2 tls int athn_debug = 0; 83 1.5.4.2 tls #endif 84 1.5.4.2 tls 85 1.5.4.2 tls Static int athn_clock_rate(struct athn_softc *); 86 1.5.4.2 tls Static const char * 87 1.5.4.2 tls athn_get_mac_name(struct athn_softc *); 88 1.5.4.2 tls Static const char * 89 1.5.4.2 tls athn_get_rf_name(struct athn_softc *); 90 1.5.4.2 tls Static int athn_init(struct ifnet *); 91 1.5.4.2 tls Static int athn_init_calib(struct athn_softc *, 92 1.5.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 93 1.5.4.2 tls Static int athn_ioctl(struct ifnet *, u_long, void *); 94 1.5.4.2 tls Static int athn_media_change(struct ifnet *); 95 1.5.4.2 tls Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 1.5.4.2 tls int); 97 1.5.4.2 tls Static struct ieee80211_node * 98 1.5.4.2 tls athn_node_alloc(struct ieee80211_node_table *); 99 1.5.4.2 tls Static int athn_reset_power_on(struct athn_softc *); 100 1.5.4.2 tls Static int athn_stop_rx_dma(struct athn_softc *); 101 1.5.4.2 tls Static int athn_switch_chan(struct athn_softc *, 102 1.5.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 103 1.5.4.2 tls Static void athn_calib_to(void *); 104 1.5.4.2 tls Static void athn_disable_interrupts(struct athn_softc *); 105 1.5.4.2 tls Static void athn_enable_interrupts(struct athn_softc *); 106 1.5.4.2 tls Static void athn_get_chanlist(struct athn_softc *); 107 1.5.4.2 tls Static void athn_get_chipid(struct athn_softc *); 108 1.5.4.2 tls Static void athn_init_dma(struct athn_softc *); 109 1.5.4.2 tls Static void athn_init_qos(struct athn_softc *); 110 1.5.4.2 tls Static void athn_init_tx_queues(struct athn_softc *); 111 1.5.4.2 tls Static void athn_iter_func(void *, struct ieee80211_node *); 112 1.5.4.2 tls Static void athn_newassoc(struct ieee80211_node *, int); 113 1.5.4.2 tls Static void athn_next_scan(void *); 114 1.5.4.2 tls Static void athn_pmf_wlan_off(device_t self); 115 1.5.4.2 tls Static void athn_radiotap_attach(struct athn_softc *); 116 1.5.4.2 tls Static void athn_start(struct ifnet *); 117 1.5.4.2 tls Static void athn_tx_reclaim(struct athn_softc *, int); 118 1.5.4.2 tls Static void athn_watchdog(struct ifnet *); 119 1.5.4.2 tls Static void athn_write_serdes(struct athn_softc *, 120 1.5.4.2 tls const struct athn_serdes *); 121 1.5.4.4 jdolecek Static void athn_softintr(void *); 122 1.5.4.2 tls 123 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 124 1.5.4.2 tls Static void athn_btcoex_disable(struct athn_softc *); 125 1.5.4.2 tls Static void athn_btcoex_enable(struct athn_softc *); 126 1.5.4.2 tls #endif 127 1.5.4.2 tls 128 1.5.4.2 tls #ifdef unused 129 1.5.4.2 tls Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 1.5.4.2 tls Static int athn_rx_abort(struct athn_softc *); 131 1.5.4.2 tls #endif 132 1.5.4.2 tls 133 1.5.4.2 tls #ifdef notyet 134 1.5.4.2 tls Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 1.5.4.2 tls Static void athn_ani_lower_immunity(struct athn_softc *); 136 1.5.4.2 tls Static void athn_ani_monitor(struct athn_softc *); 137 1.5.4.2 tls Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 1.5.4.2 tls Static void athn_ani_restart(struct athn_softc *); 139 1.5.4.2 tls Static void athn_set_multi(struct athn_softc *); 140 1.5.4.2 tls #endif /* notyet */ 141 1.5.4.2 tls 142 1.5.4.2 tls PUBLIC int 143 1.5.4.2 tls athn_attach(struct athn_softc *sc) 144 1.5.4.2 tls { 145 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 146 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 147 1.5.4.2 tls size_t max_nnodes; 148 1.5.4.2 tls int error; 149 1.5.4.2 tls 150 1.5.4.2 tls /* Read hardware revision. */ 151 1.5.4.2 tls athn_get_chipid(sc); 152 1.5.4.2 tls 153 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) { 154 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 1.5.4.2 tls return error; 156 1.5.4.2 tls } 157 1.5.4.2 tls 158 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 159 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 1.5.4.2 tls return error; 161 1.5.4.2 tls } 162 1.5.4.2 tls 163 1.5.4.2 tls if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 1.5.4.2 tls error = ar5416_attach(sc); 165 1.5.4.2 tls else if (AR_SREV_9280(sc)) 166 1.5.4.2 tls error = ar9280_attach(sc); 167 1.5.4.2 tls else if (AR_SREV_9285(sc)) 168 1.5.4.2 tls error = ar9285_attach(sc); 169 1.5.4.2 tls #if NATHN_USB > 0 170 1.5.4.2 tls else if (AR_SREV_9271(sc)) 171 1.5.4.2 tls error = ar9285_attach(sc); 172 1.5.4.2 tls #endif 173 1.5.4.2 tls else if (AR_SREV_9287(sc)) 174 1.5.4.2 tls error = ar9287_attach(sc); 175 1.5.4.2 tls else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 1.5.4.2 tls error = ar9380_attach(sc); 177 1.5.4.2 tls else 178 1.5.4.2 tls error = ENOTSUP; 179 1.5.4.2 tls if (error != 0) { 180 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 1.5.4.2 tls return error; 182 1.5.4.2 tls } 183 1.5.4.2 tls 184 1.5.4.2 tls pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 1.5.4.2 tls pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 1.5.4.2 tls false); 187 1.5.4.2 tls 188 1.5.4.2 tls /* We can put the chip in sleep state now. */ 189 1.5.4.2 tls athn_set_power_sleep(sc); 190 1.5.4.2 tls 191 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 1.5.4.4 jdolecek sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 1.5.4.4 jdolecek sc); 194 1.5.4.4 jdolecek if (sc->sc_soft_ih == NULL) { 195 1.5.4.4 jdolecek aprint_error_dev(sc->sc_dev, 196 1.5.4.4 jdolecek "could not establish softint\n"); 197 1.5.4.4 jdolecek return EINVAL; 198 1.5.4.4 jdolecek } 199 1.5.4.4 jdolecek 200 1.5.4.2 tls error = sc->sc_ops.dma_alloc(sc); 201 1.5.4.2 tls if (error != 0) { 202 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 203 1.5.4.2 tls "could not allocate DMA resources\n"); 204 1.5.4.2 tls return error; 205 1.5.4.2 tls } 206 1.5.4.2 tls /* Steal one Tx buffer for beacons. */ 207 1.5.4.2 tls sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 1.5.4.2 tls SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 1.5.4.2 tls } 210 1.5.4.2 tls 211 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, 213 1.5.4.2 tls "found RF switch connected to GPIO pin %d\n", 214 1.5.4.2 tls sc->sc_rfsilent_pin); 215 1.5.4.2 tls } 216 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 1.5.4.2 tls 218 1.5.4.2 tls /* 219 1.5.4.2 tls * In HostAP mode, the number of STAs that we can handle is 220 1.5.4.2 tls * limited by the number of entries in the HW key cache. 221 1.5.4.2 tls * TKIP keys consume 2 entries in the cache. 222 1.5.4.2 tls */ 223 1.5.4.2 tls KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 1.5.4.2 tls max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 1.5.4.2 tls if (sc->sc_max_aid != 0) /* we have an override */ 226 1.5.4.2 tls ic->ic_max_aid = sc->sc_max_aid; 227 1.5.4.2 tls if (ic->ic_max_aid > max_nnodes) 228 1.5.4.2 tls ic->ic_max_aid = max_nnodes; 229 1.5.4.2 tls 230 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 1.5.4.2 tls (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 1.5.4.2 tls sc->sc_txchainmask, sc->sc_rxchainmask); 234 1.5.4.2 tls 235 1.5.4.2 tls /* Count the number of bits set (in lowest 3 bits). */ 236 1.5.4.2 tls sc->sc_ntxchains = 237 1.5.4.2 tls ((sc->sc_txchainmask >> 2) & 1) + 238 1.5.4.2 tls ((sc->sc_txchainmask >> 1) & 1) + 239 1.5.4.2 tls ((sc->sc_txchainmask >> 0) & 1); 240 1.5.4.2 tls sc->sc_nrxchains = 241 1.5.4.2 tls ((sc->sc_rxchainmask >> 2) & 1) + 242 1.5.4.2 tls ((sc->sc_rxchainmask >> 1) & 1) + 243 1.5.4.2 tls ((sc->sc_rxchainmask >> 0) & 1); 244 1.5.4.2 tls 245 1.5.4.2 tls if (AR_SINGLE_CHIP(sc)) { 246 1.5.4.4 jdolecek aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 1.5.4.2 tls aprint_verbose_dev(sc->sc_dev, 248 1.5.4.2 tls "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 1.5.4.2 tls sc->sc_mac_rev, 250 1.5.4.2 tls sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 1.5.4.2 tls ether_sprintf(ic->ic_myaddr)); 252 1.5.4.4 jdolecek } 253 1.5.4.4 jdolecek else { 254 1.5.4.4 jdolecek aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 255 1.5.4.2 tls athn_get_rf_name(sc)); 256 1.5.4.2 tls aprint_verbose_dev(sc->sc_dev, 257 1.5.4.2 tls "rev %d (%dT%dR), ROM rev %d, address %s\n", 258 1.5.4.2 tls sc->sc_mac_rev, 259 1.5.4.2 tls sc->sc_ntxchains, sc->sc_nrxchains, 260 1.5.4.2 tls sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 261 1.5.4.2 tls } 262 1.5.4.2 tls 263 1.5.4.2 tls callout_init(&sc->sc_scan_to, 0); 264 1.5.4.2 tls callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 265 1.5.4.2 tls callout_init(&sc->sc_calib_to, 0); 266 1.5.4.2 tls callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 267 1.5.4.2 tls 268 1.5.4.2 tls sc->sc_amrr.amrr_min_success_threshold = 1; 269 1.5.4.2 tls sc->sc_amrr.amrr_max_success_threshold = 15; 270 1.5.4.2 tls 271 1.5.4.2 tls ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 272 1.5.4.2 tls ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 273 1.5.4.2 tls ic->ic_state = IEEE80211_S_INIT; 274 1.5.4.2 tls 275 1.5.4.2 tls /* Set device capabilities. */ 276 1.5.4.2 tls ic->ic_caps = 277 1.5.4.2 tls IEEE80211_C_WPA | /* 802.11i */ 278 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 279 1.5.4.2 tls IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 280 1.5.4.2 tls // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 281 1.5.4.2 tls #endif 282 1.5.4.2 tls IEEE80211_C_MONITOR | /* Monitor mode supported. */ 283 1.5.4.2 tls IEEE80211_C_SHSLOT | /* Short slot time supported. */ 284 1.5.4.2 tls IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 285 1.5.4.2 tls IEEE80211_C_PMGT; /* Power saving supported. */ 286 1.5.4.2 tls 287 1.5.4.2 tls #ifndef IEEE80211_NO_HT 288 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11N) { 289 1.5.4.2 tls int i, ntxstreams, nrxstreams; 290 1.5.4.2 tls 291 1.5.4.2 tls /* Set HT capabilities. */ 292 1.5.4.2 tls ic->ic_htcaps = 293 1.5.4.2 tls IEEE80211_HTCAP_SMPS_DIS | 294 1.5.4.2 tls IEEE80211_HTCAP_CBW20_40 | 295 1.5.4.2 tls IEEE80211_HTCAP_SGI40 | 296 1.5.4.2 tls IEEE80211_HTCAP_DSSSCCK40; 297 1.5.4.2 tls if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 298 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 299 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 300 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 301 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc)) { 302 1.5.4.2 tls ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 303 1.5.4.2 tls ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 304 1.5.4.2 tls } 305 1.5.4.2 tls ntxstreams = sc->sc_ntxchains; 306 1.5.4.2 tls nrxstreams = sc->sc_nrxchains; 307 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 308 1.5.4.2 tls ntxstreams = MIN(ntxstreams, 2); 309 1.5.4.2 tls nrxstreams = MIN(nrxstreams, 2); 310 1.5.4.2 tls } 311 1.5.4.2 tls /* Set supported HT rates. */ 312 1.5.4.2 tls for (i = 0; i < nrxstreams; i++) 313 1.5.4.2 tls ic->ic_sup_mcs[i] = 0xff; 314 1.5.4.2 tls /* Set the "Tx MCS Set Defined" bit. */ 315 1.5.4.2 tls ic->ic_sup_mcs[12] |= 0x01; 316 1.5.4.2 tls if (ntxstreams != nrxstreams) { 317 1.5.4.2 tls /* Set "Tx Rx MCS Set Not Equal" bit. */ 318 1.5.4.2 tls ic->ic_sup_mcs[12] |= 0x02; 319 1.5.4.2 tls ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 320 1.5.4.2 tls } 321 1.5.4.2 tls } 322 1.5.4.2 tls #endif 323 1.5.4.2 tls 324 1.5.4.2 tls /* Set supported rates. */ 325 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11G) { 326 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11B] = 327 1.5.4.2 tls ieee80211_std_rateset_11b; 328 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11G] = 329 1.5.4.2 tls ieee80211_std_rateset_11g; 330 1.5.4.2 tls } 331 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11A) { 332 1.5.4.2 tls ic->ic_sup_rates[IEEE80211_MODE_11A] = 333 1.5.4.2 tls ieee80211_std_rateset_11a; 334 1.5.4.2 tls } 335 1.5.4.2 tls 336 1.5.4.2 tls /* Get the list of authorized/supported channels. */ 337 1.5.4.2 tls athn_get_chanlist(sc); 338 1.5.4.2 tls 339 1.5.4.2 tls ifp->if_softc = sc; 340 1.5.4.2 tls ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 341 1.5.4.4 jdolecek if (!ifp->if_init) 342 1.5.4.4 jdolecek ifp->if_init = athn_init; 343 1.5.4.4 jdolecek if (!ifp->if_ioctl) 344 1.5.4.4 jdolecek ifp->if_ioctl = athn_ioctl; 345 1.5.4.4 jdolecek if (!ifp->if_start) 346 1.5.4.4 jdolecek ifp->if_start = athn_start; 347 1.5.4.4 jdolecek if (!ifp->if_watchdog) 348 1.5.4.4 jdolecek ifp->if_watchdog = athn_watchdog; 349 1.5.4.2 tls IFQ_SET_READY(&ifp->if_snd); 350 1.5.4.2 tls memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 351 1.5.4.2 tls 352 1.5.4.4 jdolecek error = if_initialize(ifp); 353 1.5.4.4 jdolecek if (error != 0) { 354 1.5.4.4 jdolecek aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 355 1.5.4.4 jdolecek error); 356 1.5.4.4 jdolecek pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, 357 1.5.4.4 jdolecek athn_pmf_wlan_off, false); 358 1.5.4.4 jdolecek callout_destroy(&sc->sc_scan_to); 359 1.5.4.4 jdolecek callout_destroy(&sc->sc_calib_to); 360 1.5.4.4 jdolecek return error; 361 1.5.4.4 jdolecek } 362 1.5.4.2 tls ieee80211_ifattach(ic); 363 1.5.4.4 jdolecek /* Use common softint-based if_input */ 364 1.5.4.4 jdolecek ifp->if_percpuq = if_percpuq_create(ifp); 365 1.5.4.4 jdolecek if_register(ifp); 366 1.5.4.2 tls 367 1.5.4.2 tls ic->ic_node_alloc = athn_node_alloc; 368 1.5.4.2 tls ic->ic_newassoc = athn_newassoc; 369 1.5.4.2 tls if (ic->ic_updateslot == NULL) 370 1.5.4.2 tls ic->ic_updateslot = athn_updateslot; 371 1.5.4.2 tls #ifdef notyet_edca 372 1.5.4.2 tls ic->ic_updateedca = athn_updateedca; 373 1.5.4.2 tls #endif 374 1.5.4.2 tls #ifdef notyet 375 1.5.4.2 tls ic->ic_set_key = athn_set_key; 376 1.5.4.2 tls ic->ic_delete_key = athn_delete_key; 377 1.5.4.2 tls #endif 378 1.5.4.2 tls 379 1.5.4.2 tls /* Override 802.11 state transition machine. */ 380 1.5.4.2 tls sc->sc_newstate = ic->ic_newstate; 381 1.5.4.2 tls ic->ic_newstate = athn_newstate; 382 1.5.4.2 tls 383 1.5.4.2 tls if (sc->sc_media_change == NULL) 384 1.5.4.2 tls sc->sc_media_change = athn_media_change; 385 1.5.4.2 tls ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 386 1.5.4.2 tls 387 1.5.4.2 tls athn_radiotap_attach(sc); 388 1.5.4.2 tls return 0; 389 1.5.4.2 tls } 390 1.5.4.2 tls 391 1.5.4.2 tls PUBLIC void 392 1.5.4.2 tls athn_detach(struct athn_softc *sc) 393 1.5.4.2 tls { 394 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 395 1.5.4.2 tls int qid; 396 1.5.4.2 tls 397 1.5.4.2 tls callout_halt(&sc->sc_scan_to, NULL); 398 1.5.4.2 tls callout_halt(&sc->sc_calib_to, NULL); 399 1.5.4.2 tls 400 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_USB)) { 401 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 402 1.5.4.2 tls athn_tx_reclaim(sc, qid); 403 1.5.4.2 tls 404 1.5.4.2 tls /* Free Tx/Rx DMA resources. */ 405 1.5.4.2 tls sc->sc_ops.dma_free(sc); 406 1.5.4.4 jdolecek 407 1.5.4.4 jdolecek if (sc->sc_soft_ih != NULL) { 408 1.5.4.4 jdolecek softint_disestablish(sc->sc_soft_ih); 409 1.5.4.4 jdolecek sc->sc_soft_ih = NULL; 410 1.5.4.4 jdolecek } 411 1.5.4.2 tls } 412 1.5.4.2 tls /* Free ROM copy. */ 413 1.5.4.2 tls if (sc->sc_eep != NULL) { 414 1.5.4.2 tls free(sc->sc_eep, M_DEVBUF); 415 1.5.4.2 tls sc->sc_eep = NULL; 416 1.5.4.2 tls } 417 1.5.4.2 tls 418 1.5.4.2 tls bpf_detach(ifp); 419 1.5.4.2 tls ieee80211_ifdetach(&sc->sc_ic); 420 1.5.4.2 tls if_detach(ifp); 421 1.5.4.2 tls 422 1.5.4.2 tls callout_destroy(&sc->sc_scan_to); 423 1.5.4.2 tls callout_destroy(&sc->sc_calib_to); 424 1.5.4.4 jdolecek 425 1.5.4.4 jdolecek pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 426 1.5.4.4 jdolecek false); 427 1.5.4.2 tls } 428 1.5.4.2 tls 429 1.5.4.2 tls /* 430 1.5.4.2 tls * Attach the interface to 802.11 radiotap. 431 1.5.4.2 tls */ 432 1.5.4.2 tls Static void 433 1.5.4.2 tls athn_radiotap_attach(struct athn_softc *sc) 434 1.5.4.2 tls { 435 1.5.4.2 tls 436 1.5.4.2 tls bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 437 1.5.4.2 tls sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 438 1.5.4.2 tls &sc->sc_drvbpf); 439 1.5.4.2 tls 440 1.5.4.2 tls sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 441 1.5.4.2 tls sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 442 1.5.4.2 tls sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 443 1.5.4.2 tls 444 1.5.4.2 tls sc->sc_txtap_len = sizeof(sc->sc_txtapu); 445 1.5.4.2 tls sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 446 1.5.4.2 tls sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 447 1.5.4.2 tls } 448 1.5.4.2 tls 449 1.5.4.2 tls Static void 450 1.5.4.2 tls athn_get_chanlist(struct athn_softc *sc) 451 1.5.4.2 tls { 452 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 453 1.5.4.2 tls uint8_t chan; 454 1.5.4.2 tls size_t i; 455 1.5.4.2 tls 456 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11G) { 457 1.5.4.2 tls for (i = 1; i <= 14; i++) { 458 1.5.4.2 tls chan = i; 459 1.5.4.2 tls ic->ic_channels[chan].ic_freq = 460 1.5.4.2 tls ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 461 1.5.4.2 tls ic->ic_channels[chan].ic_flags = 462 1.5.4.2 tls IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 463 1.5.4.2 tls IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 464 1.5.4.2 tls } 465 1.5.4.2 tls } 466 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_11A) { 467 1.5.4.2 tls for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 468 1.5.4.2 tls chan = athn_5ghz_chans[i]; 469 1.5.4.2 tls ic->ic_channels[chan].ic_freq = 470 1.5.4.2 tls ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 471 1.5.4.2 tls ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 472 1.5.4.2 tls } 473 1.5.4.2 tls } 474 1.5.4.2 tls } 475 1.5.4.2 tls 476 1.5.4.2 tls PUBLIC void 477 1.5.4.2 tls athn_rx_start(struct athn_softc *sc) 478 1.5.4.2 tls { 479 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 480 1.5.4.2 tls uint32_t rfilt; 481 1.5.4.2 tls 482 1.5.4.2 tls /* Setup Rx DMA descriptors. */ 483 1.5.4.2 tls sc->sc_ops.rx_enable(sc); 484 1.5.4.2 tls 485 1.5.4.2 tls /* Set Rx filter. */ 486 1.5.4.2 tls rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 487 1.5.4.2 tls #ifndef IEEE80211_NO_HT 488 1.5.4.2 tls /* Want Compressed Block Ack Requests. */ 489 1.5.4.2 tls rfilt |= AR_RX_FILTER_COMPR_BAR; 490 1.5.4.2 tls #endif 491 1.5.4.2 tls rfilt |= AR_RX_FILTER_BEACON; 492 1.5.4.2 tls if (ic->ic_opmode != IEEE80211_M_STA) { 493 1.5.4.2 tls rfilt |= AR_RX_FILTER_PROBEREQ; 494 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 495 1.5.4.2 tls rfilt |= AR_RX_FILTER_PROM; 496 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 497 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc) && 498 1.5.4.2 tls ic->ic_opmode == IEEE80211_M_HOSTAP) 499 1.5.4.2 tls rfilt |= AR_RX_FILTER_PSPOLL; 500 1.5.4.2 tls #endif 501 1.5.4.2 tls } 502 1.5.4.2 tls athn_set_rxfilter(sc, rfilt); 503 1.5.4.2 tls 504 1.5.4.2 tls /* Set BSSID mask. */ 505 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 506 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKU, 0xffff); 507 1.5.4.2 tls 508 1.5.4.2 tls athn_set_opmode(sc); 509 1.5.4.2 tls 510 1.5.4.2 tls /* Set multicast filter. */ 511 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 512 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 513 1.5.4.2 tls 514 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 515 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 516 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, 0); 517 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 518 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 519 1.5.4.2 tls 520 1.5.4.2 tls /* XXX ANI. */ 521 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, 0); 522 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, 0); 523 1.5.4.2 tls 524 1.5.4.2 tls /* Disable HW crypto for now. */ 525 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 526 1.5.4.2 tls 527 1.5.4.2 tls /* Start PCU Rx. */ 528 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 529 1.5.4.2 tls AR_WRITE_BARRIER(sc); 530 1.5.4.2 tls } 531 1.5.4.2 tls 532 1.5.4.2 tls PUBLIC void 533 1.5.4.2 tls athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 534 1.5.4.2 tls { 535 1.5.4.2 tls 536 1.5.4.2 tls AR_WRITE(sc, AR_RX_FILTER, rfilt); 537 1.5.4.2 tls #ifdef notyet 538 1.5.4.2 tls reg = AR_READ(sc, AR_PHY_ERR); 539 1.5.4.2 tls reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 540 1.5.4.2 tls AR_PHY_ERR_CCK_TIMING); 541 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR, reg); 542 1.5.4.2 tls if (reg != 0) 543 1.5.4.2 tls AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 544 1.5.4.2 tls else 545 1.5.4.2 tls AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 546 1.5.4.2 tls #else 547 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR, 0); 548 1.5.4.2 tls AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 549 1.5.4.2 tls #endif 550 1.5.4.2 tls AR_WRITE_BARRIER(sc); 551 1.5.4.2 tls } 552 1.5.4.2 tls 553 1.5.4.2 tls PUBLIC int 554 1.5.4.2 tls athn_intr(void *xsc) 555 1.5.4.2 tls { 556 1.5.4.2 tls struct athn_softc *sc = xsc; 557 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 558 1.5.4.2 tls 559 1.5.4.2 tls if (!IS_UP_AND_RUNNING(ifp)) 560 1.5.4.2 tls return 0; 561 1.5.4.2 tls 562 1.5.4.2 tls if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 563 1.5.4.2 tls /* 564 1.5.4.2 tls * The hardware is not ready/present, don't touch anything. 565 1.5.4.2 tls * Note this can happen early on if the IRQ is shared. 566 1.5.4.2 tls */ 567 1.5.4.2 tls return 0; 568 1.5.4.2 tls 569 1.5.4.4 jdolecek if (!sc->sc_ops.intr_status(sc)) 570 1.5.4.4 jdolecek return 0; 571 1.5.4.4 jdolecek 572 1.5.4.4 jdolecek AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 573 1.5.4.4 jdolecek AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 574 1.5.4.4 jdolecek AR_WRITE_BARRIER(sc); 575 1.5.4.4 jdolecek 576 1.5.4.4 jdolecek softint_schedule(sc->sc_soft_ih); 577 1.5.4.4 jdolecek 578 1.5.4.4 jdolecek return 1; 579 1.5.4.4 jdolecek } 580 1.5.4.4 jdolecek 581 1.5.4.4 jdolecek Static void 582 1.5.4.4 jdolecek athn_softintr(void *xsc) 583 1.5.4.4 jdolecek { 584 1.5.4.4 jdolecek struct athn_softc *sc = xsc; 585 1.5.4.4 jdolecek struct ifnet *ifp = &sc->sc_if; 586 1.5.4.4 jdolecek 587 1.5.4.4 jdolecek if (!IS_UP_AND_RUNNING(ifp)) 588 1.5.4.4 jdolecek return; 589 1.5.4.4 jdolecek 590 1.5.4.4 jdolecek if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 591 1.5.4.4 jdolecek /* 592 1.5.4.4 jdolecek * The hardware is not ready/present, don't touch anything. 593 1.5.4.4 jdolecek * Note this can happen early on if the IRQ is shared. 594 1.5.4.4 jdolecek */ 595 1.5.4.4 jdolecek return; 596 1.5.4.4 jdolecek 597 1.5.4.4 jdolecek sc->sc_ops.intr(sc); 598 1.5.4.4 jdolecek 599 1.5.4.4 jdolecek AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 600 1.5.4.4 jdolecek AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 601 1.5.4.4 jdolecek AR_WRITE_BARRIER(sc); 602 1.5.4.2 tls } 603 1.5.4.2 tls 604 1.5.4.2 tls Static void 605 1.5.4.2 tls athn_get_chipid(struct athn_softc *sc) 606 1.5.4.2 tls { 607 1.5.4.2 tls uint32_t reg; 608 1.5.4.2 tls 609 1.5.4.2 tls reg = AR_READ(sc, AR_SREV); 610 1.5.4.2 tls if (MS(reg, AR_SREV_ID) == 0xff) { 611 1.5.4.2 tls sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 612 1.5.4.2 tls sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 613 1.5.4.2 tls if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 614 1.5.4.2 tls sc->sc_flags |= ATHN_FLAG_PCIE; 615 1.5.4.2 tls } 616 1.5.4.2 tls else { 617 1.5.4.2 tls sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 618 1.5.4.2 tls sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 619 1.5.4.2 tls if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 620 1.5.4.2 tls sc->sc_flags |= ATHN_FLAG_PCIE; 621 1.5.4.2 tls } 622 1.5.4.2 tls } 623 1.5.4.2 tls 624 1.5.4.2 tls Static const char * 625 1.5.4.2 tls athn_get_mac_name(struct athn_softc *sc) 626 1.5.4.2 tls { 627 1.5.4.2 tls 628 1.5.4.2 tls switch (sc->sc_mac_ver) { 629 1.5.4.2 tls case AR_SREV_VERSION_5416_PCI: 630 1.5.4.2 tls return "AR5416"; 631 1.5.4.2 tls case AR_SREV_VERSION_5416_PCIE: 632 1.5.4.2 tls return "AR5418"; 633 1.5.4.2 tls case AR_SREV_VERSION_9160: 634 1.5.4.2 tls return "AR9160"; 635 1.5.4.2 tls case AR_SREV_VERSION_9280: 636 1.5.4.2 tls return "AR9280"; 637 1.5.4.2 tls case AR_SREV_VERSION_9285: 638 1.5.4.2 tls return "AR9285"; 639 1.5.4.2 tls case AR_SREV_VERSION_9271: 640 1.5.4.2 tls return "AR9271"; 641 1.5.4.2 tls case AR_SREV_VERSION_9287: 642 1.5.4.2 tls return "AR9287"; 643 1.5.4.2 tls case AR_SREV_VERSION_9380: 644 1.5.4.2 tls return "AR9380"; 645 1.5.4.2 tls case AR_SREV_VERSION_9485: 646 1.5.4.2 tls return "AR9485"; 647 1.5.4.2 tls default: 648 1.5.4.2 tls return "unknown"; 649 1.5.4.2 tls } 650 1.5.4.2 tls } 651 1.5.4.2 tls 652 1.5.4.2 tls /* 653 1.5.4.2 tls * Return RF chip name (not for single-chip solutions). 654 1.5.4.2 tls */ 655 1.5.4.2 tls Static const char * 656 1.5.4.2 tls athn_get_rf_name(struct athn_softc *sc) 657 1.5.4.2 tls { 658 1.5.4.2 tls 659 1.5.4.2 tls KASSERT(!AR_SINGLE_CHIP(sc)); 660 1.5.4.2 tls 661 1.5.4.2 tls switch (sc->sc_rf_rev) { 662 1.5.4.2 tls case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 663 1.5.4.2 tls return "AR5133"; 664 1.5.4.2 tls case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 665 1.5.4.2 tls return "AR2133"; 666 1.5.4.2 tls case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 667 1.5.4.2 tls return "AR5122"; 668 1.5.4.2 tls case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 669 1.5.4.2 tls return "AR2122"; 670 1.5.4.2 tls default: 671 1.5.4.2 tls return "unknown"; 672 1.5.4.2 tls } 673 1.5.4.2 tls } 674 1.5.4.2 tls 675 1.5.4.2 tls PUBLIC int 676 1.5.4.2 tls athn_reset_power_on(struct athn_softc *sc) 677 1.5.4.2 tls { 678 1.5.4.2 tls int ntries; 679 1.5.4.2 tls 680 1.5.4.2 tls /* Set force wake. */ 681 1.5.4.2 tls AR_WRITE(sc, AR_RTC_FORCE_WAKE, 682 1.5.4.2 tls AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 683 1.5.4.2 tls 684 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 685 1.5.4.2 tls /* Make sure no DMA is active by doing an AHB reset. */ 686 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB); 687 1.5.4.2 tls } 688 1.5.4.2 tls /* RTC reset and clear. */ 689 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RESET, 0); 690 1.5.4.2 tls AR_WRITE_BARRIER(sc); 691 1.5.4.2 tls DELAY(2); 692 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 693 1.5.4.2 tls AR_WRITE(sc, AR_RC, 0); 694 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RESET, 1); 695 1.5.4.2 tls 696 1.5.4.2 tls /* Poll until RTC is ON. */ 697 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 698 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 699 1.5.4.2 tls AR_RTC_STATUS_ON) 700 1.5.4.2 tls break; 701 1.5.4.2 tls DELAY(10); 702 1.5.4.2 tls } 703 1.5.4.2 tls if (ntries == 1000) { 704 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 705 1.5.4.2 tls return ETIMEDOUT; 706 1.5.4.2 tls } 707 1.5.4.2 tls return athn_reset(sc, 0); 708 1.5.4.2 tls } 709 1.5.4.2 tls 710 1.5.4.2 tls PUBLIC int 711 1.5.4.2 tls athn_reset(struct athn_softc *sc, int cold_reset) 712 1.5.4.2 tls { 713 1.5.4.2 tls int ntries; 714 1.5.4.2 tls 715 1.5.4.2 tls /* Set force wake. */ 716 1.5.4.2 tls AR_WRITE(sc, AR_RTC_FORCE_WAKE, 717 1.5.4.2 tls AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 718 1.5.4.2 tls 719 1.5.4.2 tls if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 720 1.5.4.2 tls (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 721 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 722 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 723 1.5.4.2 tls (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 724 1.5.4.2 tls } 725 1.5.4.2 tls else if (!AR_SREV_9380_10_OR_LATER(sc)) 726 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB); 727 1.5.4.2 tls 728 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 729 1.5.4.2 tls (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 730 1.5.4.2 tls AR_WRITE_BARRIER(sc); 731 1.5.4.2 tls DELAY(50); 732 1.5.4.2 tls AR_WRITE(sc, AR_RTC_RC, 0); 733 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 734 1.5.4.2 tls if (!(AR_READ(sc, AR_RTC_RC) & 735 1.5.4.2 tls (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 736 1.5.4.2 tls break; 737 1.5.4.2 tls DELAY(10); 738 1.5.4.2 tls } 739 1.5.4.2 tls if (ntries == 1000) { 740 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 741 1.5.4.2 tls return ETIMEDOUT; 742 1.5.4.2 tls } 743 1.5.4.2 tls AR_WRITE(sc, AR_RC, 0); 744 1.5.4.2 tls AR_WRITE_BARRIER(sc); 745 1.5.4.2 tls return 0; 746 1.5.4.2 tls } 747 1.5.4.2 tls 748 1.5.4.2 tls PUBLIC int 749 1.5.4.2 tls athn_set_power_awake(struct athn_softc *sc) 750 1.5.4.2 tls { 751 1.5.4.2 tls int ntries, error; 752 1.5.4.2 tls 753 1.5.4.2 tls /* Do a Power-On-Reset if shutdown. */ 754 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 755 1.5.4.2 tls AR_RTC_STATUS_SHUTDOWN) { 756 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) 757 1.5.4.2 tls return error; 758 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 759 1.5.4.2 tls athn_init_pll(sc, NULL); 760 1.5.4.2 tls } 761 1.5.4.2 tls AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 762 1.5.4.2 tls AR_WRITE_BARRIER(sc); 763 1.5.4.2 tls DELAY(50); /* Give chip the chance to awake. */ 764 1.5.4.2 tls 765 1.5.4.2 tls /* Poll until RTC is ON. */ 766 1.5.4.2 tls for (ntries = 0; ntries < 4000; ntries++) { 767 1.5.4.2 tls if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 768 1.5.4.2 tls AR_RTC_STATUS_ON) 769 1.5.4.2 tls break; 770 1.5.4.2 tls DELAY(50); 771 1.5.4.2 tls AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 772 1.5.4.2 tls } 773 1.5.4.2 tls if (ntries == 4000) { 774 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 775 1.5.4.2 tls return ETIMEDOUT; 776 1.5.4.2 tls } 777 1.5.4.2 tls 778 1.5.4.2 tls AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 779 1.5.4.2 tls AR_WRITE_BARRIER(sc); 780 1.5.4.2 tls return 0; 781 1.5.4.2 tls } 782 1.5.4.2 tls 783 1.5.4.2 tls PUBLIC void 784 1.5.4.2 tls athn_set_power_sleep(struct athn_softc *sc) 785 1.5.4.2 tls { 786 1.5.4.2 tls 787 1.5.4.2 tls AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 788 1.5.4.2 tls /* Allow the MAC to go to sleep. */ 789 1.5.4.2 tls AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 790 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) 791 1.5.4.2 tls AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 792 1.5.4.2 tls /* 793 1.5.4.2 tls * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 794 1.5.4.2 tls * results in high power consumption on AR5416 chipsets. 795 1.5.4.2 tls */ 796 1.5.4.2 tls if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 797 1.5.4.2 tls AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 798 1.5.4.2 tls AR_WRITE_BARRIER(sc); 799 1.5.4.2 tls } 800 1.5.4.2 tls 801 1.5.4.2 tls PUBLIC void 802 1.5.4.2 tls athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 803 1.5.4.2 tls { 804 1.5.4.2 tls uint32_t pll; 805 1.5.4.2 tls 806 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 807 1.5.4.2 tls if (AR_SREV_9485(sc)) 808 1.5.4.2 tls AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 809 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 810 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 811 1.5.4.2 tls } 812 1.5.4.2 tls else if (AR_SREV_9280_10_OR_LATER(sc)) { 813 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 814 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 815 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 816 1.5.4.2 tls pll = 0x142c; 817 1.5.4.2 tls else if (AR_SREV_9280_20(sc)) 818 1.5.4.2 tls pll = 0x2850; 819 1.5.4.2 tls else 820 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 821 1.5.4.2 tls } 822 1.5.4.2 tls else 823 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 824 1.5.4.2 tls } 825 1.5.4.2 tls else if (AR_SREV_9160_10_OR_LATER(sc)) { 826 1.5.4.2 tls pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 827 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 828 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 829 1.5.4.2 tls else 830 1.5.4.2 tls pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 831 1.5.4.2 tls } 832 1.5.4.2 tls else { 833 1.5.4.2 tls pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 834 1.5.4.2 tls if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 835 1.5.4.2 tls pll |= SM(AR_RTC_PLL_DIV, 0x0a); 836 1.5.4.2 tls else 837 1.5.4.2 tls pll |= SM(AR_RTC_PLL_DIV, 0x0b); 838 1.5.4.2 tls } 839 1.5.4.2 tls DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 840 1.5.4.2 tls AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 841 1.5.4.2 tls if (AR_SREV_9271(sc)) { 842 1.5.4.2 tls /* Switch core clock to 117MHz. */ 843 1.5.4.2 tls AR_WRITE_BARRIER(sc); 844 1.5.4.2 tls DELAY(500); 845 1.5.4.2 tls AR_WRITE(sc, 0x50050, 0x304); 846 1.5.4.2 tls } 847 1.5.4.2 tls AR_WRITE_BARRIER(sc); 848 1.5.4.2 tls DELAY(100); 849 1.5.4.2 tls AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 850 1.5.4.2 tls AR_WRITE_BARRIER(sc); 851 1.5.4.2 tls } 852 1.5.4.2 tls 853 1.5.4.2 tls Static void 854 1.5.4.2 tls athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 855 1.5.4.2 tls { 856 1.5.4.2 tls int i; 857 1.5.4.2 tls 858 1.5.4.2 tls /* Write sequence to Serializer/Deserializer. */ 859 1.5.4.2 tls for (i = 0; i < serdes->nvals; i++) 860 1.5.4.2 tls AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 861 1.5.4.2 tls AR_WRITE_BARRIER(sc); 862 1.5.4.2 tls } 863 1.5.4.2 tls 864 1.5.4.2 tls PUBLIC void 865 1.5.4.2 tls athn_config_pcie(struct athn_softc *sc) 866 1.5.4.2 tls { 867 1.5.4.2 tls 868 1.5.4.2 tls /* Disable PLL when in L0s as well as receiver clock when in L1. */ 869 1.5.4.2 tls athn_write_serdes(sc, sc->sc_serdes); 870 1.5.4.2 tls 871 1.5.4.2 tls DELAY(1000); 872 1.5.4.2 tls /* Allow forcing of PCIe core into L1 state. */ 873 1.5.4.2 tls AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 874 1.5.4.2 tls 875 1.5.4.2 tls #ifndef ATHN_PCIE_WAEN 876 1.5.4.2 tls AR_WRITE(sc, AR_WA, sc->sc_workaround); 877 1.5.4.2 tls #else 878 1.5.4.2 tls AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 879 1.5.4.2 tls #endif 880 1.5.4.2 tls AR_WRITE_BARRIER(sc); 881 1.5.4.2 tls } 882 1.5.4.2 tls 883 1.5.4.2 tls /* 884 1.5.4.2 tls * Serializer/Deserializer programming for non-PCIe devices. 885 1.5.4.2 tls */ 886 1.5.4.2 tls static const uint32_t ar_nonpcie_serdes_regs[] = { 887 1.5.4.2 tls AR_PCIE_SERDES, 888 1.5.4.2 tls AR_PCIE_SERDES, 889 1.5.4.2 tls AR_PCIE_SERDES, 890 1.5.4.2 tls AR_PCIE_SERDES, 891 1.5.4.2 tls AR_PCIE_SERDES, 892 1.5.4.2 tls AR_PCIE_SERDES, 893 1.5.4.2 tls AR_PCIE_SERDES, 894 1.5.4.2 tls AR_PCIE_SERDES, 895 1.5.4.2 tls AR_PCIE_SERDES, 896 1.5.4.2 tls AR_PCIE_SERDES2, 897 1.5.4.2 tls }; 898 1.5.4.2 tls 899 1.5.4.2 tls static const uint32_t ar_nonpcie_serdes_vals[] = { 900 1.5.4.2 tls 0x9248fc00, 901 1.5.4.2 tls 0x24924924, 902 1.5.4.2 tls 0x28000029, 903 1.5.4.2 tls 0x57160824, 904 1.5.4.2 tls 0x25980579, 905 1.5.4.2 tls 0x00000000, 906 1.5.4.2 tls 0x1aaabe40, 907 1.5.4.2 tls 0xbe105554, 908 1.5.4.2 tls 0x000e1007, 909 1.5.4.2 tls 0x00000000 910 1.5.4.2 tls }; 911 1.5.4.2 tls 912 1.5.4.2 tls static const struct athn_serdes ar_nonpcie_serdes = { 913 1.5.4.2 tls __arraycount(ar_nonpcie_serdes_vals), 914 1.5.4.2 tls ar_nonpcie_serdes_regs, 915 1.5.4.2 tls ar_nonpcie_serdes_vals 916 1.5.4.2 tls }; 917 1.5.4.2 tls 918 1.5.4.2 tls PUBLIC void 919 1.5.4.2 tls athn_config_nonpcie(struct athn_softc *sc) 920 1.5.4.2 tls { 921 1.5.4.2 tls 922 1.5.4.2 tls athn_write_serdes(sc, &ar_nonpcie_serdes); 923 1.5.4.2 tls } 924 1.5.4.2 tls 925 1.5.4.2 tls PUBLIC int 926 1.5.4.2 tls athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 927 1.5.4.2 tls struct ieee80211_channel *extchan) 928 1.5.4.2 tls { 929 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 930 1.5.4.2 tls int error, qid; 931 1.5.4.2 tls 932 1.5.4.2 tls /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 933 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 934 1.5.4.2 tls if (athn_tx_pending(sc, qid)) 935 1.5.4.2 tls return EBUSY; 936 1.5.4.2 tls 937 1.5.4.2 tls /* Request RF Bus grant. */ 938 1.5.4.2 tls if ((error = ops->rf_bus_request(sc)) != 0) 939 1.5.4.2 tls return error; 940 1.5.4.2 tls 941 1.5.4.2 tls ops->set_phy(sc, curchan, extchan); 942 1.5.4.2 tls 943 1.5.4.2 tls /* Change the synthesizer. */ 944 1.5.4.2 tls if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 945 1.5.4.2 tls return error; 946 1.5.4.2 tls 947 1.5.4.2 tls sc->sc_curchan = curchan; 948 1.5.4.2 tls sc->sc_curchanext = extchan; 949 1.5.4.2 tls 950 1.5.4.2 tls /* Set transmit power values for new channel. */ 951 1.5.4.2 tls ops->set_txpower(sc, curchan, extchan); 952 1.5.4.2 tls 953 1.5.4.2 tls /* Release the RF Bus grant. */ 954 1.5.4.2 tls ops->rf_bus_release(sc); 955 1.5.4.2 tls 956 1.5.4.2 tls /* Write delta slope coeffs for modes where OFDM may be used. */ 957 1.5.4.2 tls if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 958 1.5.4.2 tls ops->set_delta_slope(sc, curchan, extchan); 959 1.5.4.2 tls 960 1.5.4.2 tls ops->spur_mitigate(sc, curchan, extchan); 961 1.5.4.2 tls /* XXX Load noisefloor values and start calibration. */ 962 1.5.4.2 tls 963 1.5.4.2 tls return 0; 964 1.5.4.2 tls } 965 1.5.4.2 tls 966 1.5.4.2 tls Static int 967 1.5.4.2 tls athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 968 1.5.4.2 tls struct ieee80211_channel *extchan) 969 1.5.4.2 tls { 970 1.5.4.2 tls int error, qid; 971 1.5.4.2 tls 972 1.5.4.2 tls /* Disable interrupts. */ 973 1.5.4.2 tls athn_disable_interrupts(sc); 974 1.5.4.2 tls 975 1.5.4.2 tls /* Stop all Tx queues. */ 976 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 977 1.5.4.2 tls athn_stop_tx_dma(sc, qid); 978 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 979 1.5.4.2 tls athn_tx_reclaim(sc, qid); 980 1.5.4.2 tls 981 1.5.4.2 tls /* Stop Rx. */ 982 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 983 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 984 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 985 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 986 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 987 1.5.4.2 tls athn_set_rxfilter(sc, 0); 988 1.5.4.2 tls error = athn_stop_rx_dma(sc); 989 1.5.4.2 tls if (error != 0) 990 1.5.4.2 tls goto reset; 991 1.5.4.2 tls 992 1.5.4.2 tls #ifdef notyet 993 1.5.4.2 tls /* AR9280 needs a full reset. */ 994 1.5.4.2 tls if (AR_SREV_9280(sc)) 995 1.5.4.2 tls #endif 996 1.5.4.2 tls goto reset; 997 1.5.4.2 tls 998 1.5.4.2 tls /* If band or bandwidth changes, we need to do a full reset. */ 999 1.5.4.2 tls if (curchan->ic_flags != sc->sc_curchan->ic_flags || 1000 1.5.4.2 tls ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 1001 1.5.4.2 tls DPRINTFN(DBG_RF, sc, "channel band switch\n"); 1002 1.5.4.2 tls goto reset; 1003 1.5.4.2 tls } 1004 1.5.4.2 tls error = athn_set_power_awake(sc); 1005 1.5.4.2 tls if (error != 0) 1006 1.5.4.2 tls goto reset; 1007 1.5.4.2 tls 1008 1.5.4.2 tls error = athn_set_chan(sc, curchan, extchan); 1009 1.5.4.2 tls if (error != 0) { 1010 1.5.4.2 tls reset: /* Error found, try a full reset. */ 1011 1.5.4.2 tls DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 1012 1.5.4.2 tls error = athn_hw_reset(sc, curchan, extchan, 0); 1013 1.5.4.2 tls if (error != 0) /* Hopeless case. */ 1014 1.5.4.2 tls return error; 1015 1.5.4.2 tls } 1016 1.5.4.2 tls athn_rx_start(sc); 1017 1.5.4.2 tls 1018 1.5.4.2 tls /* Re-enable interrupts. */ 1019 1.5.4.2 tls athn_enable_interrupts(sc); 1020 1.5.4.2 tls return 0; 1021 1.5.4.2 tls } 1022 1.5.4.2 tls 1023 1.5.4.2 tls PUBLIC void 1024 1.5.4.2 tls athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1025 1.5.4.2 tls { 1026 1.5.4.2 tls #define COEFF_SCALE_SHIFT 24 1027 1.5.4.2 tls uint32_t exp, man; 1028 1.5.4.2 tls 1029 1.5.4.2 tls /* exponent = 14 - floor(log2(coeff)) */ 1030 1.5.4.2 tls for (exp = 31; exp > 0; exp--) 1031 1.5.4.2 tls if (coeff & (1 << exp)) 1032 1.5.4.2 tls break; 1033 1.5.4.2 tls exp = 14 - (exp - COEFF_SCALE_SHIFT); 1034 1.5.4.2 tls 1035 1.5.4.2 tls /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1036 1.5.4.2 tls man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1037 1.5.4.2 tls 1038 1.5.4.2 tls *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1039 1.5.4.2 tls *exponent = exp - 16; 1040 1.5.4.2 tls #undef COEFF_SCALE_SHIFT 1041 1.5.4.2 tls } 1042 1.5.4.2 tls 1043 1.5.4.2 tls PUBLIC void 1044 1.5.4.2 tls athn_reset_key(struct athn_softc *sc, int entry) 1045 1.5.4.2 tls { 1046 1.5.4.2 tls 1047 1.5.4.2 tls /* 1048 1.5.4.2 tls * NB: Key cache registers access special memory area that requires 1049 1.5.4.2 tls * two 32-bit writes to actually update the values in the internal 1050 1.5.4.2 tls * memory. Consequently, writes must be grouped by pair. 1051 1.5.4.2 tls */ 1052 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1053 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1054 1.5.4.2 tls 1055 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1056 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1057 1.5.4.2 tls 1058 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1059 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1060 1.5.4.2 tls 1061 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1062 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1063 1.5.4.2 tls 1064 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1065 1.5.4.2 tls } 1066 1.5.4.2 tls 1067 1.5.4.2 tls #ifdef notyet 1068 1.5.4.2 tls Static int 1069 1.5.4.2 tls athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1070 1.5.4.2 tls struct ieee80211_key *k) 1071 1.5.4.2 tls { 1072 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 1073 1.5.4.2 tls const uint8_t *txmic, *rxmic, *key, *addr; 1074 1.5.4.2 tls uintptr_t entry, micentry; 1075 1.5.4.2 tls uint32_t type, lo, hi; 1076 1.5.4.2 tls 1077 1.5.4.2 tls switch (k->k_cipher) { 1078 1.5.4.2 tls case IEEE80211_CIPHER_WEP40: 1079 1.5.4.2 tls type = AR_KEYTABLE_TYPE_40; 1080 1.5.4.2 tls break; 1081 1.5.4.2 tls case IEEE80211_CIPHER_WEP104: 1082 1.5.4.2 tls type = AR_KEYTABLE_TYPE_104; 1083 1.5.4.2 tls break; 1084 1.5.4.2 tls case IEEE80211_CIPHER_TKIP: 1085 1.5.4.2 tls type = AR_KEYTABLE_TYPE_TKIP; 1086 1.5.4.2 tls break; 1087 1.5.4.2 tls case IEEE80211_CIPHER_CCMP: 1088 1.5.4.2 tls type = AR_KEYTABLE_TYPE_CCM; 1089 1.5.4.2 tls break; 1090 1.5.4.2 tls default: 1091 1.5.4.2 tls /* Fallback to software crypto for other ciphers. */ 1092 1.5.4.2 tls return ieee80211_set_key(ic, ni, k); 1093 1.5.4.2 tls } 1094 1.5.4.2 tls 1095 1.5.4.2 tls if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1096 1.5.4.2 tls entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1097 1.5.4.2 tls else 1098 1.5.4.2 tls entry = k->k_id; 1099 1.5.4.2 tls k->k_priv = (void *)entry; 1100 1.5.4.2 tls 1101 1.5.4.2 tls /* NB: See note about key cache registers access above. */ 1102 1.5.4.2 tls key = k->k_key; 1103 1.5.4.2 tls if (type == AR_KEYTABLE_TYPE_TKIP) { 1104 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1105 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1106 1.5.4.2 tls txmic = &key[16]; 1107 1.5.4.2 tls rxmic = &key[24]; 1108 1.5.4.2 tls } 1109 1.5.4.2 tls else 1110 1.5.4.2 tls #endif 1111 1.5.4.2 tls { 1112 1.5.4.2 tls rxmic = &key[16]; 1113 1.5.4.2 tls txmic = &key[24]; 1114 1.5.4.2 tls } 1115 1.5.4.2 tls /* Tx+Rx MIC key is at entry + 64. */ 1116 1.5.4.2 tls micentry = entry + 64; 1117 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1118 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1119 1.5.4.2 tls 1120 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1121 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1122 1.5.4.2 tls 1123 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1124 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1125 1.5.4.2 tls } 1126 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1127 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1128 1.5.4.2 tls 1129 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1130 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1131 1.5.4.2 tls 1132 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1133 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1134 1.5.4.2 tls 1135 1.5.4.2 tls if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1136 1.5.4.2 tls addr = ni->ni_macaddr; 1137 1.5.4.2 tls lo = LE_READ_4(&addr[0]); 1138 1.5.4.2 tls hi = LE_READ_2(&addr[4]); 1139 1.5.4.2 tls lo = lo >> 1 | hi << 31; 1140 1.5.4.2 tls hi = hi >> 1; 1141 1.5.4.2 tls } 1142 1.5.4.2 tls else 1143 1.5.4.2 tls lo = hi = 0; 1144 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1145 1.5.4.2 tls AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1146 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1147 1.5.4.2 tls return 0; 1148 1.5.4.2 tls } 1149 1.5.4.2 tls 1150 1.5.4.2 tls Static void 1151 1.5.4.2 tls athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1152 1.5.4.2 tls struct ieee80211_key *k) 1153 1.5.4.2 tls { 1154 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 1155 1.5.4.2 tls uintptr_t entry; 1156 1.5.4.2 tls 1157 1.5.4.2 tls switch (k->k_cipher) { 1158 1.5.4.2 tls case IEEE80211_CIPHER_WEP40: 1159 1.5.4.2 tls case IEEE80211_CIPHER_WEP104: 1160 1.5.4.2 tls case IEEE80211_CIPHER_CCMP: 1161 1.5.4.2 tls entry = (uintptr_t)k->k_priv; 1162 1.5.4.2 tls athn_reset_key(sc, entry); 1163 1.5.4.2 tls break; 1164 1.5.4.2 tls case IEEE80211_CIPHER_TKIP: 1165 1.5.4.2 tls entry = (uintptr_t)k->k_priv; 1166 1.5.4.2 tls athn_reset_key(sc, entry); 1167 1.5.4.2 tls athn_reset_key(sc, entry + 64); 1168 1.5.4.2 tls break; 1169 1.5.4.2 tls default: 1170 1.5.4.2 tls /* Fallback to software crypto for other ciphers. */ 1171 1.5.4.2 tls ieee80211_delete_key(ic, ni, k); 1172 1.5.4.2 tls } 1173 1.5.4.2 tls } 1174 1.5.4.2 tls #endif /* notyet */ 1175 1.5.4.2 tls 1176 1.5.4.2 tls PUBLIC void 1177 1.5.4.2 tls athn_led_init(struct athn_softc *sc) 1178 1.5.4.2 tls { 1179 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1180 1.5.4.2 tls 1181 1.5.4.2 tls ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1182 1.5.4.2 tls /* LED off, active low. */ 1183 1.5.4.2 tls athn_set_led(sc, 0); 1184 1.5.4.2 tls } 1185 1.5.4.2 tls 1186 1.5.4.2 tls PUBLIC void 1187 1.5.4.2 tls athn_set_led(struct athn_softc *sc, int on) 1188 1.5.4.2 tls { 1189 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1190 1.5.4.2 tls 1191 1.5.4.2 tls sc->sc_led_state = on; 1192 1.5.4.2 tls ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1193 1.5.4.2 tls } 1194 1.5.4.2 tls 1195 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 1196 1.5.4.2 tls Static void 1197 1.5.4.2 tls athn_btcoex_init(struct athn_softc *sc) 1198 1.5.4.2 tls { 1199 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1200 1.5.4.2 tls uint32_t reg; 1201 1.5.4.2 tls 1202 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1203 1.5.4.2 tls /* Connect bt_active to baseband. */ 1204 1.5.4.2 tls AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1205 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1206 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1207 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1208 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1209 1.5.4.2 tls 1210 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1211 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1212 1.5.4.2 tls AR_GPIO_BTACTIVE_PIN); 1213 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1214 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1215 1.5.4.2 tls 1216 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1217 1.5.4.2 tls } 1218 1.5.4.2 tls else { /* 3-wire. */ 1219 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1220 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1221 1.5.4.2 tls AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1222 1.5.4.2 tls 1223 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1224 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1225 1.5.4.2 tls AR_GPIO_BTACTIVE_PIN); 1226 1.5.4.2 tls reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1227 1.5.4.2 tls AR_GPIO_BTPRIORITY_PIN); 1228 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1229 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1230 1.5.4.2 tls 1231 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1232 1.5.4.2 tls ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1233 1.5.4.2 tls } 1234 1.5.4.2 tls } 1235 1.5.4.2 tls 1236 1.5.4.2 tls Static void 1237 1.5.4.2 tls athn_btcoex_enable(struct athn_softc *sc) 1238 1.5.4.2 tls { 1239 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1240 1.5.4.2 tls uint32_t reg; 1241 1.5.4.2 tls 1242 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1243 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE, 1244 1.5.4.2 tls SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1245 1.5.4.2 tls SM(AR_BT_PRIORITY_TIME, 2) | 1246 1.5.4.2 tls SM(AR_BT_FIRST_SLOT_TIME, 5) | 1247 1.5.4.2 tls SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1248 1.5.4.2 tls AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1249 1.5.4.2 tls AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1250 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1251 1.5.4.2 tls SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1252 1.5.4.2 tls SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1253 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE2, 1254 1.5.4.2 tls SM(AR_BT_BCN_MISS_THRESH, 50) | 1255 1.5.4.2 tls AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1256 1.5.4.2 tls 1257 1.5.4.2 tls AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1258 1.5.4.2 tls AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1259 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1260 1.5.4.2 tls 1261 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1262 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1263 1.5.4.2 tls 1264 1.5.4.2 tls } 1265 1.5.4.2 tls else { /* 2-wire. */ 1266 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1267 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1268 1.5.4.2 tls } 1269 1.5.4.2 tls reg = AR_READ(sc, AR_GPIO_PDPU); 1270 1.5.4.2 tls reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1271 1.5.4.2 tls reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1272 1.5.4.2 tls AR_WRITE(sc, AR_GPIO_PDPU, reg); 1273 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1274 1.5.4.2 tls 1275 1.5.4.2 tls /* Disable PCIe Active State Power Management (ASPM). */ 1276 1.5.4.2 tls if (sc->sc_disable_aspm != NULL) 1277 1.5.4.2 tls sc->sc_disable_aspm(sc); 1278 1.5.4.2 tls 1279 1.5.4.2 tls /* XXX Start periodic timer. */ 1280 1.5.4.2 tls } 1281 1.5.4.2 tls 1282 1.5.4.2 tls Static void 1283 1.5.4.2 tls athn_btcoex_disable(struct athn_softc *sc) 1284 1.5.4.2 tls { 1285 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1286 1.5.4.2 tls 1287 1.5.4.2 tls ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1288 1.5.4.2 tls 1289 1.5.4.2 tls ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1290 1.5.4.2 tls AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1291 1.5.4.2 tls 1292 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1293 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE, 1294 1.5.4.2 tls SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1295 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1296 1.5.4.2 tls AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1297 1.5.4.2 tls /* XXX Stop periodic timer. */ 1298 1.5.4.2 tls } 1299 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1300 1.5.4.2 tls /* XXX Restore ASPM setting? */ 1301 1.5.4.2 tls } 1302 1.5.4.2 tls #endif 1303 1.5.4.2 tls 1304 1.5.4.2 tls Static void 1305 1.5.4.2 tls athn_iter_func(void *arg, struct ieee80211_node *ni) 1306 1.5.4.2 tls { 1307 1.5.4.2 tls struct athn_softc *sc = arg; 1308 1.5.4.2 tls struct athn_node *an = (struct athn_node *)ni; 1309 1.5.4.2 tls 1310 1.5.4.2 tls ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1311 1.5.4.2 tls } 1312 1.5.4.2 tls 1313 1.5.4.2 tls Static void 1314 1.5.4.2 tls athn_calib_to(void *arg) 1315 1.5.4.2 tls { 1316 1.5.4.2 tls extern int ticks; 1317 1.5.4.2 tls struct athn_softc *sc = arg; 1318 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1319 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 1320 1.5.4.2 tls int s; 1321 1.5.4.2 tls 1322 1.5.4.2 tls s = splnet(); 1323 1.5.4.2 tls 1324 1.5.4.2 tls /* Do periodic (every 4 minutes) PA calibration. */ 1325 1.5.4.2 tls if (AR_SREV_9285_11_OR_LATER(sc) && 1326 1.5.4.2 tls !AR_SREV_9380_10_OR_LATER(sc) && 1327 1.5.4.3 tls (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1328 1.5.4.2 tls sc->sc_pa_calib_ticks = ticks; 1329 1.5.4.2 tls if (AR_SREV_9271(sc)) 1330 1.5.4.2 tls ar9271_pa_calib(sc); 1331 1.5.4.2 tls else 1332 1.5.4.2 tls ar9285_pa_calib(sc); 1333 1.5.4.2 tls } 1334 1.5.4.2 tls 1335 1.5.4.2 tls /* Do periodic (every 30 seconds) temperature compensation. */ 1336 1.5.4.2 tls if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1337 1.5.4.2 tls ticks >= sc->sc_olpc_ticks + 30 * hz) { 1338 1.5.4.2 tls sc->sc_olpc_ticks = ticks; 1339 1.5.4.2 tls ops->olpc_temp_compensation(sc); 1340 1.5.4.2 tls } 1341 1.5.4.2 tls 1342 1.5.4.2 tls #ifdef notyet 1343 1.5.4.2 tls /* XXX ANI. */ 1344 1.5.4.2 tls athn_ani_monitor(sc); 1345 1.5.4.2 tls 1346 1.5.4.2 tls ops->next_calib(sc); 1347 1.5.4.2 tls #endif 1348 1.5.4.2 tls if (ic->ic_fixed_rate == -1) { 1349 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_STA) 1350 1.5.4.2 tls athn_iter_func(sc, ic->ic_bss); 1351 1.5.4.2 tls else 1352 1.5.4.2 tls ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1353 1.5.4.2 tls } 1354 1.5.4.2 tls callout_schedule(&sc->sc_calib_to, hz / 2); 1355 1.5.4.2 tls splx(s); 1356 1.5.4.2 tls } 1357 1.5.4.2 tls 1358 1.5.4.2 tls Static int 1359 1.5.4.2 tls athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1360 1.5.4.2 tls struct ieee80211_channel *extchan) 1361 1.5.4.2 tls { 1362 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1363 1.5.4.2 tls int error; 1364 1.5.4.2 tls 1365 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 1366 1.5.4.2 tls error = ar9003_init_calib(sc); 1367 1.5.4.2 tls else if (AR_SREV_9285_10_OR_LATER(sc)) 1368 1.5.4.2 tls error = ar9285_init_calib(sc, curchan, extchan); 1369 1.5.4.2 tls else 1370 1.5.4.2 tls error = ar5416_init_calib(sc, curchan, extchan); 1371 1.5.4.2 tls if (error != 0) 1372 1.5.4.2 tls return error; 1373 1.5.4.2 tls 1374 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 1375 1.5.4.2 tls /* Do PA calibration. */ 1376 1.5.4.2 tls if (AR_SREV_9285_11_OR_LATER(sc)) { 1377 1.5.4.2 tls extern int ticks; 1378 1.5.4.2 tls sc->sc_pa_calib_ticks = ticks; 1379 1.5.4.2 tls if (AR_SREV_9271(sc)) 1380 1.5.4.2 tls ar9271_pa_calib(sc); 1381 1.5.4.2 tls else 1382 1.5.4.2 tls ar9285_pa_calib(sc); 1383 1.5.4.2 tls } 1384 1.5.4.2 tls /* Do noisefloor calibration. */ 1385 1.5.4.2 tls ops->noisefloor_calib(sc); 1386 1.5.4.2 tls } 1387 1.5.4.2 tls if (AR_SREV_9160_10_OR_LATER(sc)) { 1388 1.5.4.2 tls /* Support IQ calibration. */ 1389 1.5.4.2 tls sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1390 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 1391 1.5.4.2 tls /* Support temperature compensation calibration. */ 1392 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1393 1.5.4.2 tls } 1394 1.5.4.2 tls else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1395 1.5.4.2 tls /* 1396 1.5.4.2 tls * ADC gain calibration causes uplink throughput 1397 1.5.4.2 tls * drops in HT40 mode on AR9287. 1398 1.5.4.2 tls */ 1399 1.5.4.2 tls if (!AR_SREV_9287(sc)) { 1400 1.5.4.2 tls /* Support ADC gain calibration. */ 1401 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1402 1.5.4.2 tls } 1403 1.5.4.2 tls /* Support ADC DC offset calibration. */ 1404 1.5.4.2 tls sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1405 1.5.4.2 tls } 1406 1.5.4.2 tls } 1407 1.5.4.2 tls return 0; 1408 1.5.4.2 tls } 1409 1.5.4.2 tls 1410 1.5.4.2 tls /* 1411 1.5.4.2 tls * Adaptive noise immunity. 1412 1.5.4.2 tls */ 1413 1.5.4.2 tls #ifdef notyet 1414 1.5.4.2 tls Static int32_t 1415 1.5.4.2 tls athn_ani_get_rssi(struct athn_softc *sc) 1416 1.5.4.2 tls { 1417 1.5.4.2 tls 1418 1.5.4.2 tls return 0; /* XXX */ 1419 1.5.4.2 tls } 1420 1.5.4.2 tls #endif /* notyet */ 1421 1.5.4.2 tls 1422 1.5.4.2 tls #ifdef notyet 1423 1.5.4.2 tls Static void 1424 1.5.4.2 tls athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1425 1.5.4.2 tls { 1426 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1427 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1428 1.5.4.2 tls int32_t rssi; 1429 1.5.4.2 tls 1430 1.5.4.2 tls /* First, raise noise immunity level, up to max. */ 1431 1.5.4.2 tls if (ani->noise_immunity_level < 4) { 1432 1.5.4.2 tls ani->noise_immunity_level++; 1433 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1434 1.5.4.2 tls return; 1435 1.5.4.2 tls } 1436 1.5.4.2 tls 1437 1.5.4.2 tls /* Then, raise our spur immunity level, up to max. */ 1438 1.5.4.2 tls if (ani->spur_immunity_level < 7) { 1439 1.5.4.2 tls ani->spur_immunity_level++; 1440 1.5.4.2 tls ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1441 1.5.4.2 tls return; 1442 1.5.4.2 tls } 1443 1.5.4.2 tls 1444 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1445 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1446 1.5.4.2 tls if (ani->firstep_level < 2) { 1447 1.5.4.2 tls ani->firstep_level++; 1448 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1449 1.5.4.2 tls } 1450 1.5.4.2 tls return; 1451 1.5.4.2 tls } 1452 1.5.4.2 tls #endif 1453 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1454 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1455 1.5.4.2 tls /* 1456 1.5.4.2 tls * Beacon RSSI is high, turn off OFDM weak signal detection 1457 1.5.4.2 tls * or raise first step level as last resort. 1458 1.5.4.2 tls */ 1459 1.5.4.2 tls if (ani->ofdm_weak_signal) { 1460 1.5.4.2 tls ani->ofdm_weak_signal = 0; 1461 1.5.4.2 tls ops->disable_ofdm_weak_signal(sc); 1462 1.5.4.2 tls ani->spur_immunity_level = 0; 1463 1.5.4.2 tls ops->set_spur_immunity_level(sc, 0); 1464 1.5.4.2 tls } 1465 1.5.4.2 tls else if (ani->firstep_level < 2) { 1466 1.5.4.2 tls ani->firstep_level++; 1467 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1468 1.5.4.2 tls } 1469 1.5.4.2 tls } 1470 1.5.4.2 tls else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1471 1.5.4.2 tls /* 1472 1.5.4.2 tls * Beacon RSSI is in mid range, we need OFDM weak signal 1473 1.5.4.2 tls * detection but we can raise first step level. 1474 1.5.4.2 tls */ 1475 1.5.4.2 tls if (!ani->ofdm_weak_signal) { 1476 1.5.4.2 tls ani->ofdm_weak_signal = 1; 1477 1.5.4.2 tls ops->enable_ofdm_weak_signal(sc); 1478 1.5.4.2 tls } 1479 1.5.4.2 tls if (ani->firstep_level < 2) { 1480 1.5.4.2 tls ani->firstep_level++; 1481 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1482 1.5.4.2 tls } 1483 1.5.4.2 tls } 1484 1.5.4.2 tls else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1485 1.5.4.2 tls /* 1486 1.5.4.2 tls * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1487 1.5.4.2 tls * signal detection and zero first step level to maximize 1488 1.5.4.2 tls * CCK sensitivity. 1489 1.5.4.2 tls */ 1490 1.5.4.2 tls if (ani->ofdm_weak_signal) { 1491 1.5.4.2 tls ani->ofdm_weak_signal = 0; 1492 1.5.4.2 tls ops->disable_ofdm_weak_signal(sc); 1493 1.5.4.2 tls } 1494 1.5.4.2 tls if (ani->firstep_level > 0) { 1495 1.5.4.2 tls ani->firstep_level = 0; 1496 1.5.4.2 tls ops->set_firstep_level(sc, 0); 1497 1.5.4.2 tls } 1498 1.5.4.2 tls } 1499 1.5.4.2 tls } 1500 1.5.4.2 tls #endif /* notyet */ 1501 1.5.4.2 tls 1502 1.5.4.2 tls #ifdef notyet 1503 1.5.4.2 tls Static void 1504 1.5.4.2 tls athn_ani_cck_err_trigger(struct athn_softc *sc) 1505 1.5.4.2 tls { 1506 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1507 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1508 1.5.4.2 tls int32_t rssi; 1509 1.5.4.2 tls 1510 1.5.4.2 tls /* Raise noise immunity level, up to max. */ 1511 1.5.4.2 tls if (ani->noise_immunity_level < 4) { 1512 1.5.4.2 tls ani->noise_immunity_level++; 1513 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1514 1.5.4.2 tls return; 1515 1.5.4.2 tls } 1516 1.5.4.2 tls 1517 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1518 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1519 1.5.4.2 tls if (ani->firstep_level < 2) { 1520 1.5.4.2 tls ani->firstep_level++; 1521 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1522 1.5.4.2 tls } 1523 1.5.4.2 tls return; 1524 1.5.4.2 tls } 1525 1.5.4.2 tls #endif 1526 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1527 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1528 1.5.4.2 tls /* 1529 1.5.4.2 tls * Beacon RSSI is in mid or high range, raise first step 1530 1.5.4.2 tls * level. 1531 1.5.4.2 tls */ 1532 1.5.4.2 tls if (ani->firstep_level < 2) { 1533 1.5.4.2 tls ani->firstep_level++; 1534 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1535 1.5.4.2 tls } 1536 1.5.4.2 tls } 1537 1.5.4.2 tls else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1538 1.5.4.2 tls /* 1539 1.5.4.2 tls * Beacon RSSI is low, zero first step level to maximize 1540 1.5.4.2 tls * CCK sensitivity. 1541 1.5.4.2 tls */ 1542 1.5.4.2 tls if (ani->firstep_level > 0) { 1543 1.5.4.2 tls ani->firstep_level = 0; 1544 1.5.4.2 tls ops->set_firstep_level(sc, 0); 1545 1.5.4.2 tls } 1546 1.5.4.2 tls } 1547 1.5.4.2 tls } 1548 1.5.4.2 tls #endif /* notyet */ 1549 1.5.4.2 tls 1550 1.5.4.2 tls #ifdef notyet 1551 1.5.4.2 tls Static void 1552 1.5.4.2 tls athn_ani_lower_immunity(struct athn_softc *sc) 1553 1.5.4.2 tls { 1554 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1555 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 1556 1.5.4.2 tls int32_t rssi; 1557 1.5.4.2 tls 1558 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 1559 1.5.4.2 tls if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1560 1.5.4.2 tls if (ani->firstep_level > 0) { 1561 1.5.4.2 tls ani->firstep_level--; 1562 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1563 1.5.4.2 tls } 1564 1.5.4.2 tls return; 1565 1.5.4.2 tls } 1566 1.5.4.2 tls #endif 1567 1.5.4.2 tls rssi = athn_ani_get_rssi(sc); 1568 1.5.4.2 tls if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1569 1.5.4.2 tls /* 1570 1.5.4.2 tls * Beacon RSSI is high, leave OFDM weak signal detection 1571 1.5.4.2 tls * off or it may oscillate. 1572 1.5.4.2 tls */ 1573 1.5.4.2 tls } 1574 1.5.4.2 tls else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1575 1.5.4.2 tls /* 1576 1.5.4.2 tls * Beacon RSSI is in mid range, turn on OFDM weak signal 1577 1.5.4.2 tls * detection or lower first step level. 1578 1.5.4.2 tls */ 1579 1.5.4.2 tls if (!ani->ofdm_weak_signal) { 1580 1.5.4.2 tls ani->ofdm_weak_signal = 1; 1581 1.5.4.2 tls ops->enable_ofdm_weak_signal(sc); 1582 1.5.4.2 tls return; 1583 1.5.4.2 tls } 1584 1.5.4.2 tls if (ani->firstep_level > 0) { 1585 1.5.4.2 tls ani->firstep_level--; 1586 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1587 1.5.4.2 tls return; 1588 1.5.4.2 tls } 1589 1.5.4.2 tls } 1590 1.5.4.2 tls else { 1591 1.5.4.2 tls /* Beacon RSSI is low, lower first step level. */ 1592 1.5.4.2 tls if (ani->firstep_level > 0) { 1593 1.5.4.2 tls ani->firstep_level--; 1594 1.5.4.2 tls ops->set_firstep_level(sc, ani->firstep_level); 1595 1.5.4.2 tls return; 1596 1.5.4.2 tls } 1597 1.5.4.2 tls } 1598 1.5.4.2 tls /* 1599 1.5.4.2 tls * Lower spur immunity level down to zero, or if all else fails, 1600 1.5.4.2 tls * lower noise immunity level down to zero. 1601 1.5.4.2 tls */ 1602 1.5.4.2 tls if (ani->spur_immunity_level > 0) { 1603 1.5.4.2 tls ani->spur_immunity_level--; 1604 1.5.4.2 tls ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1605 1.5.4.2 tls } 1606 1.5.4.2 tls else if (ani->noise_immunity_level > 0) { 1607 1.5.4.2 tls ani->noise_immunity_level--; 1608 1.5.4.2 tls ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1609 1.5.4.2 tls } 1610 1.5.4.2 tls } 1611 1.5.4.2 tls #endif /* notyet */ 1612 1.5.4.2 tls 1613 1.5.4.2 tls #ifdef notyet 1614 1.5.4.2 tls Static void 1615 1.5.4.2 tls athn_ani_restart(struct athn_softc *sc) 1616 1.5.4.2 tls { 1617 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1618 1.5.4.2 tls 1619 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, 0); 1620 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, 0); 1621 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1622 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1623 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1624 1.5.4.2 tls 1625 1.5.4.2 tls ani->listen_time = 0; 1626 1.5.4.2 tls ani->ofdm_phy_err_count = 0; 1627 1.5.4.2 tls ani->cck_phy_err_count = 0; 1628 1.5.4.2 tls } 1629 1.5.4.2 tls #endif /* notyet */ 1630 1.5.4.2 tls 1631 1.5.4.2 tls #ifdef notyet 1632 1.5.4.2 tls Static void 1633 1.5.4.2 tls athn_ani_monitor(struct athn_softc *sc) 1634 1.5.4.2 tls { 1635 1.5.4.2 tls struct athn_ani *ani = &sc->sc_ani; 1636 1.5.4.2 tls uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1637 1.5.4.2 tls int32_t cycdelta, txfdelta, rxfdelta; 1638 1.5.4.2 tls int32_t listen_time; 1639 1.5.4.2 tls 1640 1.5.4.2 tls txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1641 1.5.4.2 tls rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1642 1.5.4.2 tls cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1643 1.5.4.2 tls 1644 1.5.4.2 tls if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1645 1.5.4.2 tls cycdelta = cyccnt - ani->cyccnt; 1646 1.5.4.2 tls txfdelta = txfcnt - ani->txfcnt; 1647 1.5.4.2 tls rxfdelta = rxfcnt - ani->rxfcnt; 1648 1.5.4.2 tls 1649 1.5.4.2 tls listen_time = (cycdelta - txfdelta - rxfdelta) / 1650 1.5.4.2 tls (athn_clock_rate(sc) * 1000); 1651 1.5.4.2 tls } 1652 1.5.4.2 tls else 1653 1.5.4.2 tls listen_time = 0; 1654 1.5.4.2 tls 1655 1.5.4.2 tls ani->cyccnt = cyccnt; 1656 1.5.4.2 tls ani->txfcnt = txfcnt; 1657 1.5.4.2 tls ani->rxfcnt = rxfcnt; 1658 1.5.4.2 tls 1659 1.5.4.2 tls if (listen_time < 0) { 1660 1.5.4.2 tls athn_ani_restart(sc); 1661 1.5.4.2 tls return; 1662 1.5.4.2 tls } 1663 1.5.4.2 tls ani->listen_time += listen_time; 1664 1.5.4.2 tls 1665 1.5.4.2 tls phy1 = AR_READ(sc, AR_PHY_ERR_1); 1666 1.5.4.2 tls phy2 = AR_READ(sc, AR_PHY_ERR_2); 1667 1.5.4.2 tls 1668 1.5.4.2 tls if (phy1 < ani->ofdm_phy_err_base) { 1669 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1670 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1671 1.5.4.2 tls } 1672 1.5.4.2 tls if (phy2 < ani->cck_phy_err_base) { 1673 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1674 1.5.4.2 tls AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1675 1.5.4.2 tls } 1676 1.5.4.2 tls if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1677 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1678 1.5.4.2 tls return; 1679 1.5.4.2 tls } 1680 1.5.4.2 tls ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1681 1.5.4.2 tls ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1682 1.5.4.2 tls 1683 1.5.4.2 tls if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1684 1.5.4.2 tls /* Check to see if we need to lower immunity. */ 1685 1.5.4.2 tls if (ani->ofdm_phy_err_count <= 1686 1.5.4.2 tls ani->listen_time * ani->ofdm_trig_low / 1000 && 1687 1.5.4.2 tls ani->cck_phy_err_count <= 1688 1.5.4.2 tls ani->listen_time * ani->cck_trig_low / 1000) 1689 1.5.4.2 tls athn_ani_lower_immunity(sc); 1690 1.5.4.2 tls athn_ani_restart(sc); 1691 1.5.4.2 tls 1692 1.5.4.2 tls } 1693 1.5.4.2 tls else if (ani->listen_time > ATHN_ANI_PERIOD) { 1694 1.5.4.2 tls /* Check to see if we need to raise immunity. */ 1695 1.5.4.2 tls if (ani->ofdm_phy_err_count > 1696 1.5.4.2 tls ani->listen_time * ani->ofdm_trig_high / 1000) { 1697 1.5.4.2 tls athn_ani_ofdm_err_trigger(sc); 1698 1.5.4.2 tls athn_ani_restart(sc); 1699 1.5.4.2 tls } 1700 1.5.4.2 tls else if (ani->cck_phy_err_count > 1701 1.5.4.2 tls ani->listen_time * ani->cck_trig_high / 1000) { 1702 1.5.4.2 tls athn_ani_cck_err_trigger(sc); 1703 1.5.4.2 tls athn_ani_restart(sc); 1704 1.5.4.2 tls } 1705 1.5.4.2 tls } 1706 1.5.4.2 tls } 1707 1.5.4.2 tls #endif /* notyet */ 1708 1.5.4.2 tls 1709 1.5.4.2 tls PUBLIC uint8_t 1710 1.5.4.2 tls athn_chan2fbin(struct ieee80211_channel *c) 1711 1.5.4.2 tls { 1712 1.5.4.2 tls 1713 1.5.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 1714 1.5.4.2 tls return c->ic_freq - 2300; 1715 1.5.4.2 tls else 1716 1.5.4.2 tls return (c->ic_freq - 4800) / 5; 1717 1.5.4.2 tls } 1718 1.5.4.2 tls 1719 1.5.4.2 tls PUBLIC int 1720 1.5.4.2 tls athn_interpolate(int x, int x1, int y1, int x2, int y2) 1721 1.5.4.2 tls { 1722 1.5.4.2 tls 1723 1.5.4.2 tls if (x1 == x2) /* Prevents division by zero. */ 1724 1.5.4.2 tls return y1; 1725 1.5.4.2 tls /* Linear interpolation. */ 1726 1.5.4.2 tls return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1727 1.5.4.2 tls } 1728 1.5.4.2 tls 1729 1.5.4.2 tls PUBLIC void 1730 1.5.4.2 tls athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1731 1.5.4.2 tls int *lo, int *hi) 1732 1.5.4.2 tls { 1733 1.5.4.2 tls int i; 1734 1.5.4.2 tls 1735 1.5.4.2 tls for (i = 0; i < npiers; i++) 1736 1.5.4.2 tls if (pierfreq[i] == AR_BCHAN_UNUSED || 1737 1.5.4.2 tls pierfreq[i] > fbin) 1738 1.5.4.2 tls break; 1739 1.5.4.2 tls *hi = i; 1740 1.5.4.2 tls *lo = *hi - 1; 1741 1.5.4.2 tls if (*lo == -1) 1742 1.5.4.2 tls *lo = *hi; 1743 1.5.4.2 tls else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1744 1.5.4.2 tls *hi = *lo; 1745 1.5.4.2 tls } 1746 1.5.4.2 tls 1747 1.5.4.2 tls Static void 1748 1.5.4.2 tls athn_init_dma(struct athn_softc *sc) 1749 1.5.4.2 tls { 1750 1.5.4.2 tls uint32_t reg; 1751 1.5.4.2 tls 1752 1.5.4.2 tls if (!AR_SREV_9380_10_OR_LATER(sc)) { 1753 1.5.4.2 tls /* Set AHB not to do cacheline prefetches. */ 1754 1.5.4.2 tls AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1755 1.5.4.2 tls } 1756 1.5.4.2 tls reg = AR_READ(sc, AR_TXCFG); 1757 1.5.4.2 tls /* Let MAC DMA reads be in 128-byte chunks. */ 1758 1.5.4.2 tls reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1759 1.5.4.2 tls 1760 1.5.4.2 tls /* Set initial Tx trigger level. */ 1761 1.5.4.2 tls if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1762 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1763 1.5.4.2 tls else if (!AR_SREV_9380_10_OR_LATER(sc)) 1764 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1765 1.5.4.2 tls AR_WRITE(sc, AR_TXCFG, reg); 1766 1.5.4.2 tls 1767 1.5.4.2 tls /* Let MAC DMA writes be in 128-byte chunks. */ 1768 1.5.4.2 tls reg = AR_READ(sc, AR_RXCFG); 1769 1.5.4.2 tls reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1770 1.5.4.2 tls AR_WRITE(sc, AR_RXCFG, reg); 1771 1.5.4.2 tls 1772 1.5.4.2 tls /* Setup Rx FIFO threshold to hold off Tx activities. */ 1773 1.5.4.2 tls AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1774 1.5.4.2 tls 1775 1.5.4.2 tls /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1776 1.5.4.2 tls if (AR_SREV_9285(sc)) { 1777 1.5.4.2 tls AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1778 1.5.4.2 tls AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1779 1.5.4.2 tls } 1780 1.5.4.2 tls else if (!AR_SREV_9271(sc)) { 1781 1.5.4.2 tls AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1782 1.5.4.2 tls AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1783 1.5.4.2 tls } 1784 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1785 1.5.4.2 tls 1786 1.5.4.2 tls /* Reset Tx status ring. */ 1787 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 1788 1.5.4.2 tls ar9003_reset_txsring(sc); 1789 1.5.4.2 tls } 1790 1.5.4.2 tls 1791 1.5.4.2 tls PUBLIC void 1792 1.5.4.2 tls athn_inc_tx_trigger_level(struct athn_softc *sc) 1793 1.5.4.2 tls { 1794 1.5.4.2 tls uint32_t reg, ftrig; 1795 1.5.4.2 tls 1796 1.5.4.2 tls reg = AR_READ(sc, AR_TXCFG); 1797 1.5.4.2 tls ftrig = MS(reg, AR_TXCFG_FTRIG); 1798 1.5.4.2 tls /* 1799 1.5.4.2 tls * NB: The AR9285 and all single-stream parts have an issue that 1800 1.5.4.2 tls * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1801 1.5.4.2 tls */ 1802 1.5.4.2 tls if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1803 1.5.4.2 tls return; /* Already at max. */ 1804 1.5.4.2 tls reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1805 1.5.4.2 tls AR_WRITE(sc, AR_TXCFG, reg); 1806 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1807 1.5.4.2 tls } 1808 1.5.4.2 tls 1809 1.5.4.2 tls PUBLIC int 1810 1.5.4.2 tls athn_stop_rx_dma(struct athn_softc *sc) 1811 1.5.4.2 tls { 1812 1.5.4.2 tls int ntries; 1813 1.5.4.2 tls 1814 1.5.4.2 tls AR_WRITE(sc, AR_CR, AR_CR_RXD); 1815 1.5.4.2 tls /* Wait for Rx enable bit to go low. */ 1816 1.5.4.2 tls for (ntries = 0; ntries < 100; ntries++) { 1817 1.5.4.2 tls if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1818 1.5.4.2 tls return 0; 1819 1.5.4.2 tls DELAY(100); 1820 1.5.4.2 tls } 1821 1.5.4.2 tls DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1822 1.5.4.2 tls return ETIMEDOUT; 1823 1.5.4.2 tls } 1824 1.5.4.2 tls 1825 1.5.4.2 tls #ifdef unused 1826 1.5.4.2 tls Static int 1827 1.5.4.2 tls athn_rx_abort(struct athn_softc *sc) 1828 1.5.4.2 tls { 1829 1.5.4.2 tls int ntries; 1830 1.5.4.2 tls 1831 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1832 1.5.4.2 tls for (ntries = 0; ntries < 1000; ntries++) { 1833 1.5.4.2 tls if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1834 1.5.4.2 tls return 0; 1835 1.5.4.2 tls DELAY(10); 1836 1.5.4.2 tls } 1837 1.5.4.2 tls DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1838 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1839 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1840 1.5.4.2 tls return ETIMEDOUT; 1841 1.5.4.2 tls } 1842 1.5.4.2 tls #endif /* unused */ 1843 1.5.4.2 tls 1844 1.5.4.2 tls Static void 1845 1.5.4.2 tls athn_tx_reclaim(struct athn_softc *sc, int qid) 1846 1.5.4.2 tls { 1847 1.5.4.2 tls struct athn_txq *txq = &sc->sc_txq[qid]; 1848 1.5.4.2 tls struct athn_tx_buf *bf; 1849 1.5.4.2 tls 1850 1.5.4.2 tls /* Reclaim all buffers queued in the specified Tx queue. */ 1851 1.5.4.2 tls /* NB: Tx DMA must be stopped. */ 1852 1.5.4.2 tls while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1853 1.5.4.2 tls SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1854 1.5.4.2 tls 1855 1.5.4.2 tls bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1856 1.5.4.2 tls bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1857 1.5.4.2 tls bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1858 1.5.4.2 tls m_freem(bf->bf_m); 1859 1.5.4.2 tls bf->bf_m = NULL; 1860 1.5.4.2 tls bf->bf_ni = NULL; /* Nodes already freed! */ 1861 1.5.4.2 tls 1862 1.5.4.2 tls /* Link Tx buffer back to global free list. */ 1863 1.5.4.2 tls SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1864 1.5.4.2 tls } 1865 1.5.4.2 tls } 1866 1.5.4.2 tls 1867 1.5.4.2 tls PUBLIC int 1868 1.5.4.2 tls athn_tx_pending(struct athn_softc *sc, int qid) 1869 1.5.4.2 tls { 1870 1.5.4.2 tls 1871 1.5.4.2 tls return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1872 1.5.4.2 tls (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1873 1.5.4.2 tls } 1874 1.5.4.2 tls 1875 1.5.4.2 tls PUBLIC void 1876 1.5.4.2 tls athn_stop_tx_dma(struct athn_softc *sc, int qid) 1877 1.5.4.2 tls { 1878 1.5.4.2 tls uint32_t tsflo; 1879 1.5.4.2 tls int ntries, i; 1880 1.5.4.2 tls 1881 1.5.4.2 tls AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1882 1.5.4.2 tls for (ntries = 0; ntries < 40; ntries++) { 1883 1.5.4.2 tls if (!athn_tx_pending(sc, qid)) 1884 1.5.4.2 tls break; 1885 1.5.4.2 tls DELAY(100); 1886 1.5.4.2 tls } 1887 1.5.4.2 tls if (ntries == 40) { 1888 1.5.4.2 tls for (i = 0; i < 2; i++) { 1889 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1890 1.5.4.2 tls AR_WRITE(sc, AR_QUIET2, 1891 1.5.4.2 tls SM(AR_QUIET2_QUIET_DUR, 10)); 1892 1.5.4.2 tls AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1893 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1894 1.5.4.2 tls AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1895 1.5.4.2 tls if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1896 1.5.4.2 tls break; 1897 1.5.4.2 tls } 1898 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1899 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1900 1.5.4.2 tls DELAY(200); 1901 1.5.4.2 tls AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1902 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1903 1.5.4.2 tls 1904 1.5.4.2 tls for (ntries = 0; ntries < 40; ntries++) { 1905 1.5.4.2 tls if (!athn_tx_pending(sc, qid)) 1906 1.5.4.2 tls break; 1907 1.5.4.2 tls DELAY(100); 1908 1.5.4.2 tls } 1909 1.5.4.2 tls 1910 1.5.4.2 tls AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1911 1.5.4.2 tls } 1912 1.5.4.2 tls AR_WRITE(sc, AR_Q_TXD, 0); 1913 1.5.4.2 tls AR_WRITE_BARRIER(sc); 1914 1.5.4.2 tls } 1915 1.5.4.2 tls 1916 1.5.4.2 tls PUBLIC int 1917 1.5.4.2 tls athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1918 1.5.4.2 tls { 1919 1.5.4.2 tls #define divround(a, b) (((a) + (b) - 1) / (b)) 1920 1.5.4.2 tls int txtime; 1921 1.5.4.2 tls 1922 1.5.4.2 tls /* XXX HT. */ 1923 1.5.4.2 tls if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1924 1.5.4.2 tls txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1925 1.5.4.2 tls /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1926 1.5.4.2 tls txtime = 16 + 4 + 4 * txtime + 16; 1927 1.5.4.2 tls } 1928 1.5.4.2 tls else { 1929 1.5.4.2 tls txtime = divround(16 * len, athn_rates[ridx].rate); 1930 1.5.4.2 tls if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1931 1.5.4.2 tls txtime += 72 + 24; 1932 1.5.4.2 tls else 1933 1.5.4.2 tls txtime += 144 + 48; 1934 1.5.4.2 tls txtime += 10; /* 10us SIFS. */ 1935 1.5.4.2 tls } 1936 1.5.4.2 tls return txtime; 1937 1.5.4.2 tls #undef divround 1938 1.5.4.2 tls } 1939 1.5.4.2 tls 1940 1.5.4.2 tls PUBLIC void 1941 1.5.4.2 tls athn_init_tx_queues(struct athn_softc *sc) 1942 1.5.4.2 tls { 1943 1.5.4.2 tls int qid; 1944 1.5.4.2 tls 1945 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1946 1.5.4.2 tls SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1947 1.5.4.2 tls sc->sc_txq[qid].lastds = NULL; 1948 1.5.4.2 tls sc->sc_txq[qid].wait = NULL; 1949 1.5.4.2 tls sc->sc_txq[qid].queued = 0; 1950 1.5.4.2 tls 1951 1.5.4.2 tls AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1952 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1953 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1954 1.5.4.2 tls SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1955 1.5.4.2 tls AR_WRITE(sc, AR_QMISC(qid), 1956 1.5.4.2 tls AR_Q_MISC_DCU_EARLY_TERM_REQ); 1957 1.5.4.2 tls AR_WRITE(sc, AR_DMISC(qid), 1958 1.5.4.2 tls SM(AR_D_MISC_BKOFF_THRESH, 2) | 1959 1.5.4.2 tls AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1960 1.5.4.2 tls } 1961 1.5.4.2 tls 1962 1.5.4.2 tls /* Init beacon queue. */ 1963 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1964 1.5.4.2 tls AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1965 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS1); 1966 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1967 1.5.4.2 tls SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1968 1.5.4.2 tls AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1969 1.5.4.2 tls AR_D_MISC_BEACON_USE | 1970 1.5.4.2 tls AR_D_MISC_POST_FR_BKOFF_DIS); 1971 1.5.4.2 tls AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1972 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMIN, 0) | 1973 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMAX, 0) | 1974 1.5.4.2 tls SM(AR_D_LCL_IFS_AIFS, 1)); 1975 1.5.4.2 tls 1976 1.5.4.2 tls /* Init CAB (Content After Beacon) queue. */ 1977 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1978 1.5.4.2 tls AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1979 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS0); 1980 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1981 1.5.4.2 tls SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1982 1.5.4.2 tls AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1983 1.5.4.2 tls 1984 1.5.4.2 tls /* Init PS-Poll queue. */ 1985 1.5.4.2 tls AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1986 1.5.4.2 tls AR_Q_MISC_CBR_INCR_DIS1); 1987 1.5.4.2 tls 1988 1.5.4.2 tls /* Init UAPSD queue. */ 1989 1.5.4.2 tls AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1990 1.5.4.2 tls AR_D_MISC_POST_FR_BKOFF_DIS); 1991 1.5.4.2 tls 1992 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 1993 1.5.4.2 tls /* Enable MAC descriptor CRC check. */ 1994 1.5.4.2 tls AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1995 1.5.4.2 tls } 1996 1.5.4.2 tls /* Enable DESC interrupts for all Tx queues. */ 1997 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1998 1.5.4.2 tls /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1999 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 2000 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2001 1.5.4.2 tls } 2002 1.5.4.2 tls 2003 1.5.4.2 tls PUBLIC void 2004 1.5.4.2 tls athn_set_sta_timers(struct athn_softc *sc) 2005 1.5.4.2 tls { 2006 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2007 1.5.4.2 tls uint32_t tsfhi, tsflo, tsftu, reg; 2008 1.5.4.2 tls uint32_t intval, next_tbtt, next_dtim; 2009 1.5.4.3 tls int dtim_period, rem_dtim_count; 2010 1.5.4.2 tls 2011 1.5.4.2 tls tsfhi = AR_READ(sc, AR_TSF_U32); 2012 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32); 2013 1.5.4.2 tls tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 2014 1.5.4.2 tls 2015 1.5.4.2 tls /* Beacon interval in TU. */ 2016 1.5.4.2 tls intval = ic->ic_bss->ni_intval; 2017 1.5.4.2 tls 2018 1.5.4.2 tls next_tbtt = roundup(tsftu, intval); 2019 1.5.4.2 tls #ifdef notyet 2020 1.5.4.2 tls dtim_period = ic->ic_dtim_period; 2021 1.5.4.2 tls if (dtim_period <= 0) 2022 1.5.4.2 tls #endif 2023 1.5.4.2 tls dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2024 1.5.4.2 tls 2025 1.5.4.2 tls #ifdef notyet 2026 1.5.4.3 tls int dtim_count = ic->ic_dtim_count; 2027 1.5.4.2 tls if (dtim_count >= dtim_period) /* Should not happen. */ 2028 1.5.4.2 tls dtim_count = 0; /* Assume last TIM was a DTIM. */ 2029 1.5.4.3 tls #endif 2030 1.5.4.2 tls 2031 1.5.4.2 tls /* Compute number of remaining TIMs until next DTIM. */ 2032 1.5.4.2 tls rem_dtim_count = 0; /* XXX */ 2033 1.5.4.2 tls next_dtim = next_tbtt + rem_dtim_count * intval; 2034 1.5.4.2 tls 2035 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2036 1.5.4.2 tls AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2037 1.5.4.2 tls AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2038 1.5.4.2 tls 2039 1.5.4.2 tls /* 2040 1.5.4.2 tls * Set the number of consecutive beacons to miss before raising 2041 1.5.4.2 tls * a BMISS interrupt to 10. 2042 1.5.4.2 tls */ 2043 1.5.4.2 tls reg = AR_READ(sc, AR_RSSI_THR); 2044 1.5.4.2 tls reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2045 1.5.4.2 tls AR_WRITE(sc, AR_RSSI_THR, reg); 2046 1.5.4.2 tls 2047 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_DTIM, 2048 1.5.4.2 tls (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2049 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TIM, 2050 1.5.4.2 tls (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2051 1.5.4.2 tls 2052 1.5.4.2 tls /* CAB timeout is in 1/8 TU. */ 2053 1.5.4.2 tls AR_WRITE(sc, AR_SLEEP1, 2054 1.5.4.2 tls SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2055 1.5.4.2 tls AR_SLEEP1_ASSUME_DTIM); 2056 1.5.4.2 tls AR_WRITE(sc, AR_SLEEP2, 2057 1.5.4.2 tls SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2058 1.5.4.2 tls 2059 1.5.4.2 tls AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2060 1.5.4.2 tls AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2061 1.5.4.2 tls 2062 1.5.4.2 tls AR_SETBITS(sc, AR_TIMER_MODE, 2063 1.5.4.2 tls AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2064 1.5.4.2 tls 2065 1.5.4.2 tls /* Set TSF out-of-range threshold (fixed at 16k us). */ 2066 1.5.4.2 tls AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2067 1.5.4.2 tls 2068 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2069 1.5.4.2 tls } 2070 1.5.4.2 tls 2071 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2072 1.5.4.2 tls PUBLIC void 2073 1.5.4.2 tls athn_set_hostap_timers(struct athn_softc *sc) 2074 1.5.4.2 tls { 2075 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2076 1.5.4.2 tls uint32_t intval, next_tbtt; 2077 1.5.4.2 tls 2078 1.5.4.2 tls /* Beacon interval in TU. */ 2079 1.5.4.2 tls intval = ic->ic_bss->ni_intval; 2080 1.5.4.2 tls next_tbtt = intval; 2081 1.5.4.2 tls 2082 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2083 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2084 1.5.4.2 tls (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2085 1.5.4.2 tls AR_WRITE(sc, AR_NEXT_CFP, 2086 1.5.4.2 tls (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2087 1.5.4.2 tls 2088 1.5.4.2 tls AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2089 1.5.4.2 tls AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2090 1.5.4.2 tls AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2091 1.5.4.2 tls AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2092 1.5.4.2 tls 2093 1.5.4.2 tls AR_WRITE(sc, AR_TIMER_MODE, 2094 1.5.4.2 tls AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2095 1.5.4.2 tls 2096 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2097 1.5.4.2 tls } 2098 1.5.4.2 tls #endif 2099 1.5.4.2 tls 2100 1.5.4.2 tls PUBLIC void 2101 1.5.4.2 tls athn_set_opmode(struct athn_softc *sc) 2102 1.5.4.2 tls { 2103 1.5.4.2 tls uint32_t reg; 2104 1.5.4.2 tls 2105 1.5.4.2 tls switch (sc->sc_ic.ic_opmode) { 2106 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2107 1.5.4.2 tls case IEEE80211_M_HOSTAP: 2108 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2109 1.5.4.2 tls reg &= ~AR_STA_ID1_ADHOC; 2110 1.5.4.2 tls reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2111 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2112 1.5.4.2 tls 2113 1.5.4.2 tls AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2114 1.5.4.2 tls break; 2115 1.5.4.2 tls case IEEE80211_M_IBSS: 2116 1.5.4.2 tls case IEEE80211_M_AHDEMO: 2117 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2118 1.5.4.2 tls reg &= ~AR_STA_ID1_STA_AP; 2119 1.5.4.2 tls reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2120 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2121 1.5.4.2 tls 2122 1.5.4.2 tls AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2123 1.5.4.2 tls break; 2124 1.5.4.2 tls #endif 2125 1.5.4.2 tls default: 2126 1.5.4.2 tls reg = AR_READ(sc, AR_STA_ID1); 2127 1.5.4.2 tls reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2128 1.5.4.2 tls reg |= AR_STA_ID1_KSRCH_MODE; 2129 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, reg); 2130 1.5.4.2 tls break; 2131 1.5.4.2 tls } 2132 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2133 1.5.4.2 tls } 2134 1.5.4.2 tls 2135 1.5.4.2 tls PUBLIC void 2136 1.5.4.2 tls athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2137 1.5.4.2 tls { 2138 1.5.4.2 tls const uint8_t *bssid = ni->ni_bssid; 2139 1.5.4.2 tls 2140 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2141 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2142 1.5.4.2 tls SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2143 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2144 1.5.4.2 tls } 2145 1.5.4.2 tls 2146 1.5.4.2 tls Static void 2147 1.5.4.2 tls athn_enable_interrupts(struct athn_softc *sc) 2148 1.5.4.2 tls { 2149 1.5.4.2 tls uint32_t mask2; 2150 1.5.4.2 tls 2151 1.5.4.2 tls athn_disable_interrupts(sc); /* XXX */ 2152 1.5.4.2 tls 2153 1.5.4.2 tls AR_WRITE(sc, AR_IMR, sc->sc_imask); 2154 1.5.4.2 tls 2155 1.5.4.2 tls mask2 = AR_READ(sc, AR_IMR_S2); 2156 1.5.4.2 tls mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2157 1.5.4.2 tls AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2158 1.5.4.2 tls mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2159 1.5.4.2 tls AR_WRITE(sc, AR_IMR_S2, mask2); 2160 1.5.4.2 tls 2161 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2162 1.5.4.2 tls 2163 1.5.4.2 tls AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2164 1.5.4.2 tls 2165 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2166 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2167 1.5.4.2 tls 2168 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2169 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2170 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2171 1.5.4.2 tls } 2172 1.5.4.2 tls 2173 1.5.4.2 tls Static void 2174 1.5.4.2 tls athn_disable_interrupts(struct athn_softc *sc) 2175 1.5.4.2 tls { 2176 1.5.4.2 tls 2177 1.5.4.2 tls AR_WRITE(sc, AR_IER, 0); 2178 1.5.4.2 tls (void)AR_READ(sc, AR_IER); 2179 1.5.4.2 tls 2180 1.5.4.2 tls AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2181 1.5.4.2 tls (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2182 1.5.4.2 tls 2183 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2184 1.5.4.2 tls (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2185 1.5.4.2 tls 2186 1.5.4.2 tls AR_WRITE(sc, AR_IMR, 0); 2187 1.5.4.2 tls 2188 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2189 1.5.4.2 tls AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2190 1.5.4.2 tls AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2191 1.5.4.2 tls 2192 1.5.4.2 tls AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2193 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2194 1.5.4.2 tls } 2195 1.5.4.2 tls 2196 1.5.4.2 tls Static void 2197 1.5.4.2 tls athn_init_qos(struct athn_softc *sc) 2198 1.5.4.2 tls { 2199 1.5.4.2 tls 2200 1.5.4.2 tls /* Initialize QoS settings. */ 2201 1.5.4.2 tls AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2202 1.5.4.2 tls AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2203 1.5.4.2 tls AR_WRITE(sc, AR_QOS_NO_ACK, 2204 1.5.4.2 tls SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2205 1.5.4.2 tls SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2206 1.5.4.2 tls SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2207 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2208 1.5.4.2 tls /* Initialize TXOP for all TIDs. */ 2209 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2210 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2211 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2212 1.5.4.2 tls AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2213 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2214 1.5.4.2 tls } 2215 1.5.4.2 tls 2216 1.5.4.2 tls PUBLIC int 2217 1.5.4.2 tls athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2218 1.5.4.2 tls struct ieee80211_channel *extchan, int init) 2219 1.5.4.2 tls { 2220 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2221 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 2222 1.5.4.2 tls uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2223 1.5.4.2 tls int i, error; 2224 1.5.4.2 tls 2225 1.5.4.2 tls /* XXX not if already awake */ 2226 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 2227 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2228 1.5.4.2 tls return error; 2229 1.5.4.2 tls } 2230 1.5.4.2 tls 2231 1.5.4.2 tls /* Preserve the antenna on a channel switch. */ 2232 1.5.4.2 tls if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2233 1.5.4.2 tls def_ant = 1; 2234 1.5.4.2 tls /* Preserve other registers. */ 2235 1.5.4.2 tls sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2236 1.5.4.2 tls cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2237 1.5.4.2 tls AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2238 1.5.4.2 tls AR_CFG_LED_BLINK_SLOW); 2239 1.5.4.2 tls 2240 1.5.4.2 tls /* Mark PHY as inactive. */ 2241 1.5.4.2 tls ops->disable_phy(sc); 2242 1.5.4.2 tls 2243 1.5.4.2 tls if (init && AR_SREV_9271(sc)) { 2244 1.5.4.2 tls AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2245 1.5.4.2 tls AR9271_RADIO_RF_RST); 2246 1.5.4.2 tls DELAY(50); 2247 1.5.4.2 tls } 2248 1.5.4.2 tls if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2249 1.5.4.2 tls /* Save TSF before it gets cleared. */ 2250 1.5.4.2 tls tsfhi = AR_READ(sc, AR_TSF_U32); 2251 1.5.4.2 tls tsflo = AR_READ(sc, AR_TSF_L32); 2252 1.5.4.2 tls 2253 1.5.4.2 tls /* NB: RTC reset clears TSF. */ 2254 1.5.4.2 tls error = athn_reset_power_on(sc); 2255 1.5.4.2 tls } 2256 1.5.4.2 tls else { 2257 1.5.4.2 tls tsfhi = tsflo = 0; /* XXX: gcc */ 2258 1.5.4.2 tls error = athn_reset(sc, 0); 2259 1.5.4.2 tls } 2260 1.5.4.2 tls if (error != 0) { 2261 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2262 1.5.4.2 tls "could not reset chip (error=%d)\n", error); 2263 1.5.4.2 tls return error; 2264 1.5.4.2 tls } 2265 1.5.4.2 tls 2266 1.5.4.2 tls /* XXX not if already awake */ 2267 1.5.4.2 tls if ((error = athn_set_power_awake(sc)) != 0) { 2268 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2269 1.5.4.2 tls return error; 2270 1.5.4.2 tls } 2271 1.5.4.2 tls 2272 1.5.4.2 tls athn_init_pll(sc, curchan); 2273 1.5.4.2 tls ops->set_rf_mode(sc, curchan); 2274 1.5.4.2 tls 2275 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2276 1.5.4.2 tls /* Check that the radio is not disabled by hardware switch. */ 2277 1.5.4.2 tls reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2278 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2279 1.5.4.2 tls reg = !reg; 2280 1.5.4.2 tls if (!reg) { 2281 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2282 1.5.4.2 tls "radio is disabled by hardware switch\n"); 2283 1.5.4.2 tls return EPERM; 2284 1.5.4.2 tls } 2285 1.5.4.2 tls } 2286 1.5.4.2 tls if (init && AR_SREV_9271(sc)) { 2287 1.5.4.2 tls AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2288 1.5.4.2 tls AR9271_GATE_MAC_CTL); 2289 1.5.4.2 tls DELAY(50); 2290 1.5.4.2 tls } 2291 1.5.4.2 tls if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2292 1.5.4.2 tls /* Restore TSF if it got cleared. */ 2293 1.5.4.2 tls AR_WRITE(sc, AR_TSF_L32, tsflo); 2294 1.5.4.2 tls AR_WRITE(sc, AR_TSF_U32, tsfhi); 2295 1.5.4.2 tls } 2296 1.5.4.2 tls 2297 1.5.4.2 tls if (AR_SREV_9280_10_OR_LATER(sc)) 2298 1.5.4.2 tls AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2299 1.5.4.2 tls 2300 1.5.4.2 tls if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2301 1.5.4.2 tls ar9287_1_3_enable_async_fifo(sc); 2302 1.5.4.2 tls 2303 1.5.4.2 tls /* Write init values to hardware. */ 2304 1.5.4.2 tls ops->hw_init(sc, curchan, extchan); 2305 1.5.4.2 tls 2306 1.5.4.2 tls /* 2307 1.5.4.2 tls * Only >=AR9280 2.0 parts are capable of encrypting unicast 2308 1.5.4.2 tls * management frames using CCMP. 2309 1.5.4.2 tls */ 2310 1.5.4.2 tls if (AR_SREV_9280_20_OR_LATER(sc)) { 2311 1.5.4.2 tls reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2312 1.5.4.2 tls /* Do not mask the subtype field in management frames. */ 2313 1.5.4.2 tls reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2314 1.5.4.2 tls reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2315 1.5.4.4 jdolecek (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2316 1.5.4.2 tls IEEE80211_FC1_MORE_DATA)); 2317 1.5.4.2 tls AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2318 1.5.4.2 tls } 2319 1.5.4.2 tls else if (AR_SREV_9160_10_OR_LATER(sc)) { 2320 1.5.4.2 tls /* Disable hardware crypto for management frames. */ 2321 1.5.4.2 tls AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2322 1.5.4.2 tls AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2323 1.5.4.2 tls AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2324 1.5.4.2 tls AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2325 1.5.4.2 tls } 2326 1.5.4.2 tls 2327 1.5.4.2 tls if (ic->ic_curmode != IEEE80211_MODE_11B) 2328 1.5.4.2 tls ops->set_delta_slope(sc, curchan, extchan); 2329 1.5.4.2 tls 2330 1.5.4.2 tls ops->spur_mitigate(sc, curchan, extchan); 2331 1.5.4.2 tls ops->init_from_rom(sc, curchan, extchan); 2332 1.5.4.2 tls 2333 1.5.4.2 tls /* XXX */ 2334 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2335 1.5.4.2 tls AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2336 1.5.4.2 tls sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2337 1.5.4.2 tls 2338 1.5.4.2 tls athn_set_opmode(sc); 2339 1.5.4.2 tls 2340 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2341 1.5.4.2 tls AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2342 1.5.4.2 tls 2343 1.5.4.2 tls /* Restore previous antenna. */ 2344 1.5.4.2 tls AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2345 1.5.4.2 tls 2346 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID0, 0); 2347 1.5.4.2 tls AR_WRITE(sc, AR_BSS_ID1, 0); 2348 1.5.4.2 tls 2349 1.5.4.2 tls AR_WRITE(sc, AR_ISR, 0xffffffff); 2350 1.5.4.2 tls 2351 1.5.4.2 tls AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2352 1.5.4.2 tls 2353 1.5.4.2 tls if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2354 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2355 1.5.4.2 tls return error; 2356 1.5.4.2 tls } 2357 1.5.4.2 tls sc->sc_curchan = curchan; 2358 1.5.4.2 tls sc->sc_curchanext = extchan; 2359 1.5.4.2 tls 2360 1.5.4.2 tls for (i = 0; i < AR_NUM_DCU; i++) 2361 1.5.4.2 tls AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2362 1.5.4.2 tls 2363 1.5.4.2 tls athn_init_tx_queues(sc); 2364 1.5.4.2 tls 2365 1.5.4.2 tls /* Initialize interrupt mask. */ 2366 1.5.4.2 tls sc->sc_imask = 2367 1.5.4.2 tls AR_IMR_TXDESC | AR_IMR_TXEOL | 2368 1.5.4.2 tls AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2369 1.5.4.2 tls AR_IMR_RXMINTR | AR_IMR_RXINTM | 2370 1.5.4.2 tls AR_IMR_GENTMR | AR_IMR_BCNMISC; 2371 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) 2372 1.5.4.2 tls sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2373 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2374 1.5.4.2 tls if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2375 1.5.4.2 tls sc->sc_imask |= AR_IMR_MIB; 2376 1.5.4.2 tls #endif 2377 1.5.4.2 tls AR_WRITE(sc, AR_IMR, sc->sc_imask); 2378 1.5.4.2 tls AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2379 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2380 1.5.4.2 tls sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2381 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2382 1.5.4.2 tls sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2383 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2384 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2385 1.5.4.2 tls if (AR_SREV_9380_10_OR_LATER(sc)) { 2386 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2387 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2388 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2389 1.5.4.2 tls AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2390 1.5.4.2 tls } 2391 1.5.4.2 tls 2392 1.5.4.2 tls athn_init_qos(sc); 2393 1.5.4.2 tls 2394 1.5.4.2 tls AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2395 1.5.4.2 tls 2396 1.5.4.2 tls if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2397 1.5.4.2 tls ar9287_1_3_setup_async_fifo(sc); 2398 1.5.4.2 tls 2399 1.5.4.2 tls /* Disable sequence number generation in hardware. */ 2400 1.5.4.2 tls AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2401 1.5.4.2 tls 2402 1.5.4.2 tls athn_init_dma(sc); 2403 1.5.4.2 tls 2404 1.5.4.2 tls /* Program observation bus to see MAC interrupts. */ 2405 1.5.4.2 tls AR_WRITE(sc, sc->sc_obs_off, 8); 2406 1.5.4.2 tls 2407 1.5.4.2 tls /* Setup Rx interrupt mitigation. */ 2408 1.5.4.2 tls AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2409 1.5.4.2 tls 2410 1.5.4.2 tls ops->init_baseband(sc); 2411 1.5.4.2 tls 2412 1.5.4.2 tls if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2413 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2414 1.5.4.2 tls "could not initialize calibration\n"); 2415 1.5.4.2 tls return error; 2416 1.5.4.2 tls } 2417 1.5.4.2 tls 2418 1.5.4.2 tls ops->set_rxchains(sc); 2419 1.5.4.2 tls 2420 1.5.4.2 tls AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2421 1.5.4.2 tls 2422 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_USB) { 2423 1.5.4.2 tls if (AR_SREV_9271(sc)) 2424 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2425 1.5.4.2 tls else 2426 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2427 1.5.4.2 tls } 2428 1.5.4.2 tls #if BYTE_ORDER == BIG_ENDIAN 2429 1.5.4.2 tls else { 2430 1.5.4.2 tls /* Default is LE, turn on swapping for BE. */ 2431 1.5.4.2 tls AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2432 1.5.4.2 tls } 2433 1.5.4.2 tls #endif 2434 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2435 1.5.4.2 tls 2436 1.5.4.2 tls return 0; 2437 1.5.4.2 tls } 2438 1.5.4.2 tls 2439 1.5.4.2 tls Static struct ieee80211_node * 2440 1.5.4.2 tls athn_node_alloc(struct ieee80211_node_table *ntp) 2441 1.5.4.2 tls { 2442 1.5.4.2 tls 2443 1.5.4.2 tls return malloc(sizeof(struct athn_node), M_DEVBUF, 2444 1.5.4.2 tls M_NOWAIT | M_ZERO); 2445 1.5.4.2 tls } 2446 1.5.4.2 tls 2447 1.5.4.2 tls Static void 2448 1.5.4.2 tls athn_newassoc(struct ieee80211_node *ni, int isnew) 2449 1.5.4.2 tls { 2450 1.5.4.2 tls struct ieee80211com *ic = ni->ni_ic; 2451 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 2452 1.5.4.2 tls struct athn_node *an = (void *)ni; 2453 1.5.4.2 tls struct ieee80211_rateset *rs = &ni->ni_rates; 2454 1.5.4.2 tls uint8_t rate; 2455 1.5.4.2 tls int ridx, i, j; 2456 1.5.4.2 tls 2457 1.5.4.2 tls ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2458 1.5.4.2 tls /* Start at lowest available bit-rate, AMRR will raise. */ 2459 1.5.4.2 tls ni->ni_txrate = 0; 2460 1.5.4.2 tls 2461 1.5.4.2 tls for (i = 0; i < rs->rs_nrates; i++) { 2462 1.5.4.2 tls rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2463 1.5.4.2 tls 2464 1.5.4.2 tls /* Map 802.11 rate to HW rate index. */ 2465 1.5.4.2 tls for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2466 1.5.4.2 tls if (athn_rates[ridx].rate == rate) 2467 1.5.4.2 tls break; 2468 1.5.4.2 tls an->ridx[i] = ridx; 2469 1.5.4.2 tls DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2470 1.5.4.2 tls 2471 1.5.4.2 tls /* Compute fallback rate for retries. */ 2472 1.5.4.2 tls an->fallback[i] = i; 2473 1.5.4.2 tls for (j = i - 1; j >= 0; j--) { 2474 1.5.4.2 tls if (athn_rates[an->ridx[j]].phy == 2475 1.5.4.2 tls athn_rates[an->ridx[i]].phy) { 2476 1.5.4.2 tls an->fallback[i] = j; 2477 1.5.4.2 tls break; 2478 1.5.4.2 tls } 2479 1.5.4.2 tls } 2480 1.5.4.2 tls DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2481 1.5.4.2 tls i, an->fallback[i]); 2482 1.5.4.2 tls } 2483 1.5.4.2 tls } 2484 1.5.4.2 tls 2485 1.5.4.2 tls Static int 2486 1.5.4.2 tls athn_media_change(struct ifnet *ifp) 2487 1.5.4.2 tls { 2488 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2489 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2490 1.5.4.2 tls uint8_t rate, ridx; 2491 1.5.4.2 tls int error; 2492 1.5.4.2 tls 2493 1.5.4.2 tls error = ieee80211_media_change(ifp); 2494 1.5.4.2 tls if (error != ENETRESET) 2495 1.5.4.2 tls return error; 2496 1.5.4.2 tls 2497 1.5.4.2 tls if (ic->ic_fixed_rate != -1) { 2498 1.5.4.2 tls rate = ic->ic_sup_rates[ic->ic_curmode]. 2499 1.5.4.2 tls rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2500 1.5.4.2 tls /* Map 802.11 rate to HW rate index. */ 2501 1.5.4.2 tls for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2502 1.5.4.2 tls if (athn_rates[ridx].rate == rate) 2503 1.5.4.2 tls break; 2504 1.5.4.2 tls sc->sc_fixed_ridx = ridx; 2505 1.5.4.2 tls } 2506 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp)) { 2507 1.5.4.2 tls athn_stop(ifp, 0); 2508 1.5.4.2 tls error = athn_init(ifp); 2509 1.5.4.2 tls } 2510 1.5.4.2 tls return error; 2511 1.5.4.2 tls } 2512 1.5.4.2 tls 2513 1.5.4.2 tls Static void 2514 1.5.4.2 tls athn_next_scan(void *arg) 2515 1.5.4.2 tls { 2516 1.5.4.2 tls struct athn_softc *sc = arg; 2517 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2518 1.5.4.2 tls int s; 2519 1.5.4.2 tls 2520 1.5.4.2 tls s = splnet(); 2521 1.5.4.2 tls if (ic->ic_state == IEEE80211_S_SCAN) 2522 1.5.4.2 tls ieee80211_next_scan(ic); 2523 1.5.4.2 tls splx(s); 2524 1.5.4.2 tls } 2525 1.5.4.2 tls 2526 1.5.4.2 tls Static int 2527 1.5.4.2 tls athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2528 1.5.4.2 tls { 2529 1.5.4.2 tls struct ifnet *ifp = ic->ic_ifp; 2530 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2531 1.5.4.2 tls uint32_t reg; 2532 1.5.4.2 tls int error; 2533 1.5.4.2 tls 2534 1.5.4.2 tls callout_stop(&sc->sc_calib_to); 2535 1.5.4.2 tls 2536 1.5.4.2 tls switch (nstate) { 2537 1.5.4.2 tls case IEEE80211_S_INIT: 2538 1.5.4.2 tls athn_set_led(sc, 0); 2539 1.5.4.2 tls break; 2540 1.5.4.2 tls case IEEE80211_S_SCAN: 2541 1.5.4.2 tls /* Make the LED blink while scanning. */ 2542 1.5.4.2 tls athn_set_led(sc, !sc->sc_led_state); 2543 1.5.4.2 tls error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2544 1.5.4.2 tls if (error != 0) 2545 1.5.4.2 tls return error; 2546 1.5.4.2 tls callout_schedule(&sc->sc_scan_to, hz / 5); 2547 1.5.4.2 tls break; 2548 1.5.4.2 tls case IEEE80211_S_AUTH: 2549 1.5.4.2 tls athn_set_led(sc, 0); 2550 1.5.4.2 tls error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2551 1.5.4.2 tls if (error != 0) 2552 1.5.4.2 tls return error; 2553 1.5.4.2 tls break; 2554 1.5.4.2 tls case IEEE80211_S_ASSOC: 2555 1.5.4.2 tls break; 2556 1.5.4.2 tls case IEEE80211_S_RUN: 2557 1.5.4.2 tls athn_set_led(sc, 1); 2558 1.5.4.2 tls 2559 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 2560 1.5.4.2 tls break; 2561 1.5.4.2 tls 2562 1.5.4.2 tls /* Fake a join to initialize the Tx rate. */ 2563 1.5.4.2 tls athn_newassoc(ic->ic_bss, 1); 2564 1.5.4.2 tls 2565 1.5.4.2 tls athn_set_bss(sc, ic->ic_bss); 2566 1.5.4.2 tls athn_disable_interrupts(sc); 2567 1.5.4.2 tls #ifndef IEEE80211_STA_ONLY 2568 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2569 1.5.4.2 tls athn_set_hostap_timers(sc); 2570 1.5.4.2 tls /* Enable software beacon alert interrupts. */ 2571 1.5.4.2 tls sc->sc_imask |= AR_IMR_SWBA; 2572 1.5.4.2 tls } 2573 1.5.4.2 tls else 2574 1.5.4.2 tls #endif 2575 1.5.4.2 tls { 2576 1.5.4.2 tls athn_set_sta_timers(sc); 2577 1.5.4.2 tls /* Enable beacon miss interrupts. */ 2578 1.5.4.2 tls sc->sc_imask |= AR_IMR_BMISS; 2579 1.5.4.2 tls 2580 1.5.4.2 tls /* Stop receiving beacons from other BSS. */ 2581 1.5.4.2 tls reg = AR_READ(sc, AR_RX_FILTER); 2582 1.5.4.2 tls reg = (reg & ~AR_RX_FILTER_BEACON) | 2583 1.5.4.2 tls AR_RX_FILTER_MYBEACON; 2584 1.5.4.2 tls AR_WRITE(sc, AR_RX_FILTER, reg); 2585 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2586 1.5.4.2 tls } 2587 1.5.4.2 tls athn_enable_interrupts(sc); 2588 1.5.4.2 tls 2589 1.5.4.2 tls if (sc->sc_sup_calib_mask != 0) { 2590 1.5.4.2 tls memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2591 1.5.4.2 tls sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2592 1.5.4.2 tls /* ops->do_calib(sc); */ 2593 1.5.4.2 tls } 2594 1.5.4.2 tls /* XXX Start ANI. */ 2595 1.5.4.2 tls 2596 1.5.4.2 tls callout_schedule(&sc->sc_calib_to, hz / 2); 2597 1.5.4.2 tls break; 2598 1.5.4.2 tls } 2599 1.5.4.2 tls 2600 1.5.4.2 tls return sc->sc_newstate(ic, nstate, arg); 2601 1.5.4.2 tls } 2602 1.5.4.2 tls 2603 1.5.4.2 tls #ifdef notyet_edca 2604 1.5.4.2 tls PUBLIC void 2605 1.5.4.2 tls athn_updateedca(struct ieee80211com *ic) 2606 1.5.4.2 tls { 2607 1.5.4.2 tls #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2608 1.5.4.2 tls struct athn_softc *sc = ic->ic_ifp->if_softc; 2609 1.5.4.2 tls const struct ieee80211_edca_ac_params *ac; 2610 1.5.4.2 tls int aci, qid; 2611 1.5.4.2 tls 2612 1.5.4.2 tls for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2613 1.5.4.2 tls ac = &ic->ic_edca_ac[aci]; 2614 1.5.4.2 tls qid = athn_ac2qid[aci]; 2615 1.5.4.2 tls 2616 1.5.4.2 tls AR_WRITE(sc, AR_DLCL_IFS(qid), 2617 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2618 1.5.4.2 tls SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2619 1.5.4.2 tls SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2620 1.5.4.2 tls if (ac->ac_txoplimit != 0) { 2621 1.5.4.2 tls AR_WRITE(sc, AR_DCHNTIME(qid), 2622 1.5.4.2 tls SM(AR_D_CHNTIME_DUR, 2623 1.5.4.2 tls IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2624 1.5.4.2 tls AR_D_CHNTIME_EN); 2625 1.5.4.2 tls } 2626 1.5.4.2 tls else 2627 1.5.4.2 tls AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2628 1.5.4.2 tls } 2629 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2630 1.5.4.2 tls #undef ATHN_EXP2 2631 1.5.4.2 tls } 2632 1.5.4.2 tls #endif /* notyet_edca */ 2633 1.5.4.2 tls 2634 1.5.4.2 tls Static int 2635 1.5.4.2 tls athn_clock_rate(struct athn_softc *sc) 2636 1.5.4.2 tls { 2637 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2638 1.5.4.2 tls int clockrate; /* MHz. */ 2639 1.5.4.2 tls 2640 1.5.4.2 tls if (ic->ic_curmode == IEEE80211_MODE_11A) { 2641 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2642 1.5.4.2 tls clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2643 1.5.4.2 tls else 2644 1.5.4.2 tls clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2645 1.5.4.2 tls } 2646 1.5.4.2 tls else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2647 1.5.4.2 tls clockrate = AR_CLOCK_RATE_CCK; 2648 1.5.4.2 tls } 2649 1.5.4.2 tls else 2650 1.5.4.2 tls clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2651 1.5.4.2 tls #ifndef IEEE80211_NO_HT 2652 1.5.4.2 tls if (sc->sc_curchanext != NULL) 2653 1.5.4.2 tls clockrate *= 2; 2654 1.5.4.2 tls #endif 2655 1.5.4.2 tls return clockrate; 2656 1.5.4.2 tls } 2657 1.5.4.2 tls 2658 1.5.4.2 tls PUBLIC void 2659 1.5.4.2 tls athn_updateslot(struct ifnet *ifp) 2660 1.5.4.2 tls { 2661 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2662 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2663 1.5.4.2 tls int slot; 2664 1.5.4.2 tls 2665 1.5.4.2 tls slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2666 1.5.4.2 tls AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2667 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2668 1.5.4.2 tls } 2669 1.5.4.2 tls 2670 1.5.4.2 tls Static void 2671 1.5.4.2 tls athn_start(struct ifnet *ifp) 2672 1.5.4.2 tls { 2673 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2674 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2675 1.5.4.2 tls struct ether_header *eh; 2676 1.5.4.2 tls struct ieee80211_node *ni; 2677 1.5.4.2 tls struct mbuf *m; 2678 1.5.4.2 tls 2679 1.5.4.2 tls if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2680 1.5.4.2 tls || !device_is_active(sc->sc_dev)) 2681 1.5.4.2 tls return; 2682 1.5.4.2 tls 2683 1.5.4.2 tls for (;;) { 2684 1.5.4.2 tls if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2685 1.5.4.2 tls ifp->if_flags |= IFF_OACTIVE; 2686 1.5.4.2 tls break; 2687 1.5.4.2 tls } 2688 1.5.4.2 tls /* Send pending management frames first. */ 2689 1.5.4.2 tls IF_DEQUEUE(&ic->ic_mgtq, m); 2690 1.5.4.2 tls if (m != NULL) { 2691 1.5.4.4 jdolecek ni = M_GETCTX(m, struct ieee80211_node *); 2692 1.5.4.2 tls goto sendit; 2693 1.5.4.2 tls } 2694 1.5.4.2 tls if (ic->ic_state != IEEE80211_S_RUN) 2695 1.5.4.2 tls break; 2696 1.5.4.2 tls 2697 1.5.4.2 tls /* Encapsulate and send data frames. */ 2698 1.5.4.2 tls IFQ_DEQUEUE(&ifp->if_snd, m); 2699 1.5.4.2 tls if (m == NULL) 2700 1.5.4.2 tls break; 2701 1.5.4.2 tls 2702 1.5.4.2 tls if (m->m_len < (int)sizeof(*eh) && 2703 1.5.4.2 tls (m = m_pullup(m, sizeof(*eh))) == NULL) { 2704 1.5.4.2 tls ifp->if_oerrors++; 2705 1.5.4.2 tls continue; 2706 1.5.4.2 tls } 2707 1.5.4.2 tls eh = mtod(m, struct ether_header *); 2708 1.5.4.2 tls ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2709 1.5.4.2 tls if (ni == NULL) { 2710 1.5.4.2 tls m_freem(m); 2711 1.5.4.2 tls ifp->if_oerrors++; 2712 1.5.4.2 tls continue; 2713 1.5.4.2 tls } 2714 1.5.4.2 tls 2715 1.5.4.2 tls bpf_mtap(ifp, m); 2716 1.5.4.2 tls 2717 1.5.4.2 tls if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2718 1.5.4.2 tls continue; 2719 1.5.4.2 tls sendit: 2720 1.5.4.2 tls bpf_mtap3(ic->ic_rawbpf, m); 2721 1.5.4.2 tls 2722 1.5.4.2 tls if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2723 1.5.4.2 tls ieee80211_free_node(ni); 2724 1.5.4.2 tls ifp->if_oerrors++; 2725 1.5.4.2 tls continue; 2726 1.5.4.2 tls } 2727 1.5.4.2 tls 2728 1.5.4.2 tls sc->sc_tx_timer = 5; 2729 1.5.4.2 tls ifp->if_timer = 1; 2730 1.5.4.2 tls } 2731 1.5.4.2 tls } 2732 1.5.4.2 tls 2733 1.5.4.2 tls Static void 2734 1.5.4.2 tls athn_watchdog(struct ifnet *ifp) 2735 1.5.4.2 tls { 2736 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2737 1.5.4.2 tls 2738 1.5.4.2 tls ifp->if_timer = 0; 2739 1.5.4.2 tls 2740 1.5.4.2 tls if (sc->sc_tx_timer > 0) { 2741 1.5.4.2 tls if (--sc->sc_tx_timer == 0) { 2742 1.5.4.2 tls aprint_error_dev(sc->sc_dev, "device timeout\n"); 2743 1.5.4.3 tls /* see athn_init, no need to call athn_stop here */ 2744 1.5.4.3 tls /* athn_stop(ifp, 0); */ 2745 1.5.4.2 tls (void)athn_init(ifp); 2746 1.5.4.2 tls ifp->if_oerrors++; 2747 1.5.4.2 tls return; 2748 1.5.4.2 tls } 2749 1.5.4.2 tls ifp->if_timer = 1; 2750 1.5.4.2 tls } 2751 1.5.4.2 tls ieee80211_watchdog(&sc->sc_ic); 2752 1.5.4.2 tls } 2753 1.5.4.2 tls 2754 1.5.4.2 tls #ifdef notyet 2755 1.5.4.2 tls Static void 2756 1.5.4.2 tls athn_set_multi(struct athn_softc *sc) 2757 1.5.4.2 tls { 2758 1.5.4.2 tls struct arpcom *ac = &sc->sc_ic.ic_ac; 2759 1.5.4.2 tls struct ifnet *ifp = &ac->ac_if; 2760 1.5.4.2 tls struct ether_multi *enm; 2761 1.5.4.2 tls struct ether_multistep step; 2762 1.5.4.2 tls const uint8_t *addr; 2763 1.5.4.2 tls uint32_t val, lo, hi; 2764 1.5.4.2 tls uint8_t bit; 2765 1.5.4.2 tls 2766 1.5.4.2 tls if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2767 1.5.4.2 tls lo = hi = 0xffffffff; 2768 1.5.4.2 tls goto done; 2769 1.5.4.2 tls } 2770 1.5.4.2 tls lo = hi = 0; 2771 1.5.4.2 tls ETHER_FIRST_MULTI(step, ac, enm); 2772 1.5.4.2 tls while (enm != NULL) { 2773 1.5.4.2 tls if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2774 1.5.4.2 tls ifp->if_flags |= IFF_ALLMULTI; 2775 1.5.4.2 tls lo = hi = 0xffffffff; 2776 1.5.4.2 tls goto done; 2777 1.5.4.2 tls } 2778 1.5.4.2 tls addr = enm->enm_addrlo; 2779 1.5.4.2 tls /* Calculate the XOR value of all eight 6-bit words. */ 2780 1.5.4.2 tls val = addr[0] | addr[1] << 8 | addr[2] << 16; 2781 1.5.4.2 tls bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2782 1.5.4.2 tls val = addr[3] | addr[4] << 8 | addr[5] << 16; 2783 1.5.4.2 tls bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2784 1.5.4.2 tls bit &= 0x3f; 2785 1.5.4.2 tls if (bit < 32) 2786 1.5.4.2 tls lo |= 1 << bit; 2787 1.5.4.2 tls else 2788 1.5.4.2 tls hi |= 1 << (bit - 32); 2789 1.5.4.2 tls ETHER_NEXT_MULTI(step, enm); 2790 1.5.4.2 tls } 2791 1.5.4.2 tls done: 2792 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL0, lo); 2793 1.5.4.2 tls AR_WRITE(sc, AR_MCAST_FIL1, hi); 2794 1.5.4.2 tls AR_WRITE_BARRIER(sc); 2795 1.5.4.2 tls } 2796 1.5.4.2 tls #endif /* notyet */ 2797 1.5.4.2 tls 2798 1.5.4.2 tls Static int 2799 1.5.4.2 tls athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2800 1.5.4.2 tls { 2801 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2802 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2803 1.5.4.2 tls int s, error = 0; 2804 1.5.4.2 tls 2805 1.5.4.2 tls s = splnet(); 2806 1.5.4.2 tls 2807 1.5.4.2 tls switch (cmd) { 2808 1.5.4.2 tls case SIOCSIFFLAGS: 2809 1.5.4.2 tls if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2810 1.5.4.2 tls break; 2811 1.5.4.2 tls 2812 1.5.4.2 tls switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2813 1.5.4.2 tls case IFF_UP | IFF_RUNNING: 2814 1.5.4.2 tls #ifdef notyet 2815 1.5.4.2 tls if (((ifp->if_flags ^ sc->sc_if_flags) & 2816 1.5.4.2 tls (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2817 1.5.4.2 tls /* XXX: setup multi */ 2818 1.5.4.2 tls #endif 2819 1.5.4.2 tls break; 2820 1.5.4.2 tls case IFF_UP: 2821 1.5.4.2 tls athn_init(ifp); 2822 1.5.4.2 tls break; 2823 1.5.4.2 tls 2824 1.5.4.2 tls case IFF_RUNNING: 2825 1.5.4.2 tls athn_stop(ifp, 1); 2826 1.5.4.2 tls break; 2827 1.5.4.2 tls case 0: 2828 1.5.4.2 tls default: 2829 1.5.4.2 tls break; 2830 1.5.4.2 tls } 2831 1.5.4.2 tls sc->sc_if_flags = ifp->if_flags; 2832 1.5.4.2 tls break; 2833 1.5.4.2 tls 2834 1.5.4.2 tls case SIOCADDMULTI: 2835 1.5.4.2 tls case SIOCDELMULTI: 2836 1.5.4.2 tls if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2837 1.5.4.2 tls /* setup multicast filter, etc */ 2838 1.5.4.2 tls #ifdef notyet 2839 1.5.4.2 tls athn_set_multi(sc); 2840 1.5.4.2 tls #endif 2841 1.5.4.2 tls error = 0; 2842 1.5.4.2 tls } 2843 1.5.4.2 tls break; 2844 1.5.4.2 tls 2845 1.5.4.2 tls case SIOCS80211CHANNEL: 2846 1.5.4.2 tls error = ieee80211_ioctl(ic, cmd, data); 2847 1.5.4.2 tls if (error == ENETRESET && 2848 1.5.4.2 tls ic->ic_opmode == IEEE80211_M_MONITOR) { 2849 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp)) 2850 1.5.4.2 tls athn_switch_chan(sc, ic->ic_curchan, NULL); 2851 1.5.4.2 tls error = 0; 2852 1.5.4.2 tls } 2853 1.5.4.2 tls break; 2854 1.5.4.2 tls 2855 1.5.4.2 tls default: 2856 1.5.4.2 tls error = ieee80211_ioctl(ic, cmd, data); 2857 1.5.4.2 tls } 2858 1.5.4.2 tls 2859 1.5.4.2 tls if (error == ENETRESET) { 2860 1.5.4.2 tls error = 0; 2861 1.5.4.2 tls if (IS_UP_AND_RUNNING(ifp) && 2862 1.5.4.2 tls ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2863 1.5.4.2 tls athn_stop(ifp, 0); 2864 1.5.4.2 tls error = athn_init(ifp); 2865 1.5.4.2 tls } 2866 1.5.4.2 tls } 2867 1.5.4.2 tls 2868 1.5.4.2 tls splx(s); 2869 1.5.4.2 tls return error; 2870 1.5.4.2 tls } 2871 1.5.4.2 tls 2872 1.5.4.2 tls Static int 2873 1.5.4.2 tls athn_init(struct ifnet *ifp) 2874 1.5.4.2 tls { 2875 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2876 1.5.4.2 tls struct athn_ops *ops = &sc->sc_ops; 2877 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2878 1.5.4.2 tls struct ieee80211_channel *curchan, *extchan; 2879 1.5.4.2 tls size_t i; 2880 1.5.4.2 tls int error; 2881 1.5.4.2 tls 2882 1.5.4.2 tls KASSERT(!cpu_intr_p()); 2883 1.5.4.2 tls 2884 1.5.4.2 tls if (device_is_active(sc->sc_dev)) { 2885 1.5.4.3 tls athn_stop(ifp, 0); /* see athn_watchdog() */ 2886 1.5.4.2 tls } else { 2887 1.5.4.2 tls short flags = ifp->if_flags; 2888 1.5.4.2 tls ifp->if_flags &= ~IFF_UP; 2889 1.5.4.2 tls /* avoid recursion in athn_resume */ 2890 1.5.4.2 tls if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2891 1.5.4.2 tls !device_is_active(sc->sc_dev)) { 2892 1.5.4.4 jdolecek printf("%s: failed to power up device\n", 2893 1.5.4.4 jdolecek device_xname(sc->sc_dev)); 2894 1.5.4.2 tls return 0; 2895 1.5.4.2 tls } 2896 1.5.4.2 tls ifp->if_flags = flags; 2897 1.5.4.2 tls } 2898 1.5.4.2 tls 2899 1.5.4.2 tls curchan = ic->ic_curchan; 2900 1.5.4.2 tls extchan = NULL; 2901 1.5.4.2 tls 2902 1.5.4.2 tls /* In case a new MAC address has been configured. */ 2903 1.5.4.2 tls IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2904 1.5.4.2 tls 2905 1.5.4.2 tls #ifdef openbsd_power_management 2906 1.5.4.2 tls /* For CardBus, power on the socket. */ 2907 1.5.4.2 tls if (sc->sc_enable != NULL) { 2908 1.5.4.2 tls if ((error = sc->sc_enable(sc)) != 0) { 2909 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2910 1.5.4.2 tls "could not enable device\n"); 2911 1.5.4.2 tls goto fail; 2912 1.5.4.2 tls } 2913 1.5.4.2 tls if ((error = athn_reset_power_on(sc)) != 0) { 2914 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2915 1.5.4.2 tls "could not power on device\n"); 2916 1.5.4.2 tls goto fail; 2917 1.5.4.2 tls } 2918 1.5.4.2 tls } 2919 1.5.4.2 tls #endif 2920 1.5.4.2 tls if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2921 1.5.4.2 tls athn_config_nonpcie(sc); 2922 1.5.4.2 tls else 2923 1.5.4.2 tls athn_config_pcie(sc); 2924 1.5.4.2 tls 2925 1.5.4.2 tls /* Reset HW key cache entries. */ 2926 1.5.4.2 tls for (i = 0; i < sc->sc_kc_entries; i++) 2927 1.5.4.2 tls athn_reset_key(sc, i); 2928 1.5.4.2 tls 2929 1.5.4.2 tls ops->enable_antenna_diversity(sc); 2930 1.5.4.2 tls 2931 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 2932 1.5.4.2 tls /* Configure bluetooth coexistence for combo chips. */ 2933 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2934 1.5.4.2 tls athn_btcoex_init(sc); 2935 1.5.4.2 tls #endif 2936 1.5.4.2 tls 2937 1.5.4.2 tls /* Configure LED. */ 2938 1.5.4.2 tls athn_led_init(sc); 2939 1.5.4.2 tls 2940 1.5.4.2 tls /* Configure hardware radio switch. */ 2941 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2942 1.5.4.2 tls ops->rfsilent_init(sc); 2943 1.5.4.2 tls 2944 1.5.4.2 tls if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2945 1.5.4.2 tls aprint_error_dev(sc->sc_dev, 2946 1.5.4.2 tls "unable to reset hardware; reset status %d\n", error); 2947 1.5.4.2 tls goto fail; 2948 1.5.4.2 tls } 2949 1.5.4.2 tls 2950 1.5.4.2 tls /* Enable Rx. */ 2951 1.5.4.2 tls athn_rx_start(sc); 2952 1.5.4.2 tls 2953 1.5.4.2 tls /* Enable interrupts. */ 2954 1.5.4.2 tls athn_enable_interrupts(sc); 2955 1.5.4.2 tls 2956 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 2957 1.5.4.2 tls /* Enable bluetooth coexistence for combo chips. */ 2958 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2959 1.5.4.2 tls athn_btcoex_enable(sc); 2960 1.5.4.2 tls #endif 2961 1.5.4.2 tls 2962 1.5.4.2 tls ifp->if_flags &= ~IFF_OACTIVE; 2963 1.5.4.2 tls ifp->if_flags |= IFF_RUNNING; 2964 1.5.4.2 tls 2965 1.5.4.2 tls #ifdef notyet 2966 1.5.4.2 tls if (ic->ic_flags & IEEE80211_F_WEPON) { 2967 1.5.4.2 tls /* Configure WEP keys. */ 2968 1.5.4.2 tls for (i = 0; i < IEEE80211_WEP_NKID; i++) 2969 1.5.4.2 tls athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2970 1.5.4.2 tls } 2971 1.5.4.2 tls #endif 2972 1.5.4.2 tls if (ic->ic_opmode == IEEE80211_M_MONITOR) 2973 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2974 1.5.4.2 tls else 2975 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2976 1.5.4.2 tls 2977 1.5.4.2 tls return 0; 2978 1.5.4.2 tls fail: 2979 1.5.4.2 tls athn_stop(ifp, 1); 2980 1.5.4.2 tls return error; 2981 1.5.4.2 tls } 2982 1.5.4.2 tls 2983 1.5.4.2 tls PUBLIC void 2984 1.5.4.2 tls athn_stop(struct ifnet *ifp, int disable) 2985 1.5.4.2 tls { 2986 1.5.4.2 tls struct athn_softc *sc = ifp->if_softc; 2987 1.5.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 2988 1.5.4.2 tls int qid; 2989 1.5.4.2 tls 2990 1.5.4.2 tls ifp->if_timer = sc->sc_tx_timer = 0; 2991 1.5.4.2 tls ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2992 1.5.4.2 tls 2993 1.5.4.2 tls callout_stop(&sc->sc_scan_to); 2994 1.5.4.2 tls /* In case we were scanning, release the scan "lock". */ 2995 1.5.4.2 tls // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2996 1.5.4.2 tls 2997 1.5.4.2 tls ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2998 1.5.4.2 tls 2999 1.5.4.2 tls #ifdef ATHN_BT_COEXISTENCE 3000 1.5.4.2 tls /* Disable bluetooth coexistence for combo chips. */ 3001 1.5.4.2 tls if (sc->sc_flags & ATHN_FLAG_BTCOEX) 3002 1.5.4.2 tls athn_btcoex_disable(sc); 3003 1.5.4.2 tls #endif 3004 1.5.4.2 tls 3005 1.5.4.2 tls /* Disable interrupts. */ 3006 1.5.4.2 tls athn_disable_interrupts(sc); 3007 1.5.4.2 tls /* Acknowledge interrupts (avoids interrupt storms). */ 3008 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 3009 1.5.4.2 tls AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 3010 1.5.4.2 tls 3011 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3012 1.5.4.2 tls athn_stop_tx_dma(sc, qid); 3013 1.5.4.2 tls /* XXX call athn_hw_reset if Tx still pending? */ 3014 1.5.4.2 tls for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3015 1.5.4.2 tls athn_tx_reclaim(sc, qid); 3016 1.5.4.2 tls 3017 1.5.4.2 tls /* Stop Rx. */ 3018 1.5.4.2 tls AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3019 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 3020 1.5.4.2 tls AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 3021 1.5.4.2 tls AR_WRITE(sc, AR_FILT_OFDM, 0); 3022 1.5.4.2 tls AR_WRITE(sc, AR_FILT_CCK, 0); 3023 1.5.4.2 tls AR_WRITE_BARRIER(sc); 3024 1.5.4.2 tls athn_set_rxfilter(sc, 0); 3025 1.5.4.2 tls athn_stop_rx_dma(sc); 3026 1.5.4.2 tls 3027 1.5.4.2 tls athn_reset(sc, 0); 3028 1.5.4.2 tls athn_init_pll(sc, NULL); 3029 1.5.4.2 tls athn_set_power_awake(sc); 3030 1.5.4.2 tls athn_reset(sc, 1); 3031 1.5.4.2 tls athn_init_pll(sc, NULL); 3032 1.5.4.2 tls 3033 1.5.4.2 tls athn_set_power_sleep(sc); 3034 1.5.4.2 tls 3035 1.5.4.2 tls #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3036 1.5.4.2 tls /* For CardBus, power down the socket. */ 3037 1.5.4.2 tls if (disable && sc->sc_disable != NULL) 3038 1.5.4.2 tls sc->sc_disable(sc); 3039 1.5.4.2 tls #endif 3040 1.5.4.2 tls if (disable) 3041 1.5.4.2 tls pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3042 1.5.4.2 tls } 3043 1.5.4.2 tls 3044 1.5.4.2 tls Static void 3045 1.5.4.2 tls athn_pmf_wlan_off(device_t self) 3046 1.5.4.2 tls { 3047 1.5.4.2 tls struct athn_softc *sc = device_private(self); 3048 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 3049 1.5.4.2 tls 3050 1.5.4.2 tls /* Turn the interface down. */ 3051 1.5.4.2 tls ifp->if_flags &= ~IFF_UP; 3052 1.5.4.2 tls athn_stop(ifp, 1); 3053 1.5.4.2 tls } 3054 1.5.4.2 tls 3055 1.5.4.2 tls PUBLIC void 3056 1.5.4.2 tls athn_suspend(struct athn_softc *sc) 3057 1.5.4.2 tls { 3058 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 3059 1.5.4.2 tls 3060 1.5.4.2 tls if (ifp->if_flags & IFF_RUNNING) 3061 1.5.4.2 tls athn_stop(ifp, 1); 3062 1.5.4.2 tls } 3063 1.5.4.2 tls 3064 1.5.4.2 tls PUBLIC bool 3065 1.5.4.2 tls athn_resume(struct athn_softc *sc) 3066 1.5.4.2 tls { 3067 1.5.4.2 tls struct ifnet *ifp = &sc->sc_if; 3068 1.5.4.2 tls 3069 1.5.4.2 tls if (ifp->if_flags & IFF_UP) 3070 1.5.4.2 tls athn_init(ifp); 3071 1.5.4.2 tls 3072 1.5.4.2 tls return true; 3073 1.5.4.2 tls } 3074
Indexes created Thu Oct 23 22:10:10 GMT 2025