athn.c revision 1.13.4.1
1 /* $NetBSD: athn.c,v 1.13.4.1 2017/04/21 16:53:46 bouyer Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.13.4.1 2017/04/21 16:53:46 bouyer Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 Static void athn_set_multi(struct athn_softc *); 140 #endif /* notyet */ 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } 253 else { 254 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 255 athn_get_rf_name(sc)); 256 aprint_verbose_dev(sc->sc_dev, 257 "rev %d (%dT%dR), ROM rev %d, address %s\n", 258 sc->sc_mac_rev, 259 sc->sc_ntxchains, sc->sc_nrxchains, 260 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 261 } 262 263 callout_init(&sc->sc_scan_to, 0); 264 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 265 callout_init(&sc->sc_calib_to, 0); 266 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 267 268 sc->sc_amrr.amrr_min_success_threshold = 1; 269 sc->sc_amrr.amrr_max_success_threshold = 15; 270 271 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 272 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 273 ic->ic_state = IEEE80211_S_INIT; 274 275 /* Set device capabilities. */ 276 ic->ic_caps = 277 IEEE80211_C_WPA | /* 802.11i */ 278 #ifndef IEEE80211_STA_ONLY 279 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 280 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 281 #endif 282 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 283 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 284 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 285 IEEE80211_C_PMGT; /* Power saving supported. */ 286 287 #ifndef IEEE80211_NO_HT 288 if (sc->sc_flags & ATHN_FLAG_11N) { 289 int i, ntxstreams, nrxstreams; 290 291 /* Set HT capabilities. */ 292 ic->ic_htcaps = 293 IEEE80211_HTCAP_SMPS_DIS | 294 IEEE80211_HTCAP_CBW20_40 | 295 IEEE80211_HTCAP_SGI40 | 296 IEEE80211_HTCAP_DSSSCCK40; 297 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 298 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 299 if (AR_SREV_9380_10_OR_LATER(sc)) 300 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 301 if (AR_SREV_9280_10_OR_LATER(sc)) { 302 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 303 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 304 } 305 ntxstreams = sc->sc_ntxchains; 306 nrxstreams = sc->sc_nrxchains; 307 if (!AR_SREV_9380_10_OR_LATER(sc)) { 308 ntxstreams = MIN(ntxstreams, 2); 309 nrxstreams = MIN(nrxstreams, 2); 310 } 311 /* Set supported HT rates. */ 312 for (i = 0; i < nrxstreams; i++) 313 ic->ic_sup_mcs[i] = 0xff; 314 /* Set the "Tx MCS Set Defined" bit. */ 315 ic->ic_sup_mcs[12] |= 0x01; 316 if (ntxstreams != nrxstreams) { 317 /* Set "Tx Rx MCS Set Not Equal" bit. */ 318 ic->ic_sup_mcs[12] |= 0x02; 319 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 320 } 321 } 322 #endif 323 324 /* Set supported rates. */ 325 if (sc->sc_flags & ATHN_FLAG_11G) { 326 ic->ic_sup_rates[IEEE80211_MODE_11B] = 327 ieee80211_std_rateset_11b; 328 ic->ic_sup_rates[IEEE80211_MODE_11G] = 329 ieee80211_std_rateset_11g; 330 } 331 if (sc->sc_flags & ATHN_FLAG_11A) { 332 ic->ic_sup_rates[IEEE80211_MODE_11A] = 333 ieee80211_std_rateset_11a; 334 } 335 336 /* Get the list of authorized/supported channels. */ 337 athn_get_chanlist(sc); 338 339 ifp->if_softc = sc; 340 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 341 if (!ifp->if_init) 342 ifp->if_init = athn_init; 343 if (!ifp->if_ioctl) 344 ifp->if_ioctl = athn_ioctl; 345 if (!ifp->if_start) 346 ifp->if_start = athn_start; 347 if (!ifp->if_watchdog) 348 ifp->if_watchdog = athn_watchdog; 349 IFQ_SET_READY(&ifp->if_snd); 350 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 351 352 if_initialize(ifp); 353 ieee80211_ifattach(ic); 354 /* Use common softint-based if_input */ 355 ifp->if_percpuq = if_percpuq_create(ifp); 356 if_register(ifp); 357 358 ic->ic_node_alloc = athn_node_alloc; 359 ic->ic_newassoc = athn_newassoc; 360 if (ic->ic_updateslot == NULL) 361 ic->ic_updateslot = athn_updateslot; 362 #ifdef notyet_edca 363 ic->ic_updateedca = athn_updateedca; 364 #endif 365 #ifdef notyet 366 ic->ic_set_key = athn_set_key; 367 ic->ic_delete_key = athn_delete_key; 368 #endif 369 370 /* Override 802.11 state transition machine. */ 371 sc->sc_newstate = ic->ic_newstate; 372 ic->ic_newstate = athn_newstate; 373 374 if (sc->sc_media_change == NULL) 375 sc->sc_media_change = athn_media_change; 376 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 377 378 athn_radiotap_attach(sc); 379 return 0; 380 } 381 382 PUBLIC void 383 athn_detach(struct athn_softc *sc) 384 { 385 struct ifnet *ifp = &sc->sc_if; 386 int qid; 387 388 callout_halt(&sc->sc_scan_to, NULL); 389 callout_halt(&sc->sc_calib_to, NULL); 390 391 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 392 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 393 athn_tx_reclaim(sc, qid); 394 395 /* Free Tx/Rx DMA resources. */ 396 sc->sc_ops.dma_free(sc); 397 398 if (sc->sc_soft_ih != NULL) { 399 softint_disestablish(sc->sc_soft_ih); 400 sc->sc_soft_ih = NULL; 401 } 402 } 403 /* Free ROM copy. */ 404 if (sc->sc_eep != NULL) { 405 free(sc->sc_eep, M_DEVBUF); 406 sc->sc_eep = NULL; 407 } 408 409 bpf_detach(ifp); 410 ieee80211_ifdetach(&sc->sc_ic); 411 if_detach(ifp); 412 413 callout_destroy(&sc->sc_scan_to); 414 callout_destroy(&sc->sc_calib_to); 415 } 416 417 /* 418 * Attach the interface to 802.11 radiotap. 419 */ 420 Static void 421 athn_radiotap_attach(struct athn_softc *sc) 422 { 423 424 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 425 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 426 &sc->sc_drvbpf); 427 428 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 429 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 430 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 431 432 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 433 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 434 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 435 } 436 437 Static void 438 athn_get_chanlist(struct athn_softc *sc) 439 { 440 struct ieee80211com *ic = &sc->sc_ic; 441 uint8_t chan; 442 size_t i; 443 444 if (sc->sc_flags & ATHN_FLAG_11G) { 445 for (i = 1; i <= 14; i++) { 446 chan = i; 447 ic->ic_channels[chan].ic_freq = 448 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 449 ic->ic_channels[chan].ic_flags = 450 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 451 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 452 } 453 } 454 if (sc->sc_flags & ATHN_FLAG_11A) { 455 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 456 chan = athn_5ghz_chans[i]; 457 ic->ic_channels[chan].ic_freq = 458 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 459 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 460 } 461 } 462 } 463 464 PUBLIC void 465 athn_rx_start(struct athn_softc *sc) 466 { 467 struct ieee80211com *ic = &sc->sc_ic; 468 uint32_t rfilt; 469 470 /* Setup Rx DMA descriptors. */ 471 sc->sc_ops.rx_enable(sc); 472 473 /* Set Rx filter. */ 474 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 475 #ifndef IEEE80211_NO_HT 476 /* Want Compressed Block Ack Requests. */ 477 rfilt |= AR_RX_FILTER_COMPR_BAR; 478 #endif 479 rfilt |= AR_RX_FILTER_BEACON; 480 if (ic->ic_opmode != IEEE80211_M_STA) { 481 rfilt |= AR_RX_FILTER_PROBEREQ; 482 if (ic->ic_opmode == IEEE80211_M_MONITOR) 483 rfilt |= AR_RX_FILTER_PROM; 484 #ifndef IEEE80211_STA_ONLY 485 if (AR_SREV_9280_10_OR_LATER(sc) && 486 ic->ic_opmode == IEEE80211_M_HOSTAP) 487 rfilt |= AR_RX_FILTER_PSPOLL; 488 #endif 489 } 490 athn_set_rxfilter(sc, rfilt); 491 492 /* Set BSSID mask. */ 493 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 494 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 495 496 athn_set_opmode(sc); 497 498 /* Set multicast filter. */ 499 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 500 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 501 502 AR_WRITE(sc, AR_FILT_OFDM, 0); 503 AR_WRITE(sc, AR_FILT_CCK, 0); 504 AR_WRITE(sc, AR_MIBC, 0); 505 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 506 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 507 508 /* XXX ANI. */ 509 AR_WRITE(sc, AR_PHY_ERR_1, 0); 510 AR_WRITE(sc, AR_PHY_ERR_2, 0); 511 512 /* Disable HW crypto for now. */ 513 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 514 515 /* Start PCU Rx. */ 516 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 517 AR_WRITE_BARRIER(sc); 518 } 519 520 PUBLIC void 521 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 522 { 523 524 AR_WRITE(sc, AR_RX_FILTER, rfilt); 525 #ifdef notyet 526 reg = AR_READ(sc, AR_PHY_ERR); 527 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 528 AR_PHY_ERR_CCK_TIMING); 529 AR_WRITE(sc, AR_PHY_ERR, reg); 530 if (reg != 0) 531 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 532 else 533 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 534 #else 535 AR_WRITE(sc, AR_PHY_ERR, 0); 536 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 537 #endif 538 AR_WRITE_BARRIER(sc); 539 } 540 541 PUBLIC int 542 athn_intr(void *xsc) 543 { 544 struct athn_softc *sc = xsc; 545 struct ifnet *ifp = &sc->sc_if; 546 547 if (!IS_UP_AND_RUNNING(ifp)) 548 return 0; 549 550 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 551 /* 552 * The hardware is not ready/present, don't touch anything. 553 * Note this can happen early on if the IRQ is shared. 554 */ 555 return 0; 556 557 if (!sc->sc_ops.intr_status(sc)) 558 return 0; 559 560 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 561 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 562 AR_WRITE_BARRIER(sc); 563 564 softint_schedule(sc->sc_soft_ih); 565 566 return 1; 567 } 568 569 Static void 570 athn_softintr(void *xsc) 571 { 572 struct athn_softc *sc = xsc; 573 struct ifnet *ifp = &sc->sc_if; 574 575 if (!IS_UP_AND_RUNNING(ifp)) 576 return; 577 578 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 579 /* 580 * The hardware is not ready/present, don't touch anything. 581 * Note this can happen early on if the IRQ is shared. 582 */ 583 return; 584 585 sc->sc_ops.intr(sc); 586 587 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 588 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 589 AR_WRITE_BARRIER(sc); 590 } 591 592 Static void 593 athn_get_chipid(struct athn_softc *sc) 594 { 595 uint32_t reg; 596 597 reg = AR_READ(sc, AR_SREV); 598 if (MS(reg, AR_SREV_ID) == 0xff) { 599 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 600 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 601 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 602 sc->sc_flags |= ATHN_FLAG_PCIE; 603 } 604 else { 605 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 606 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 607 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 608 sc->sc_flags |= ATHN_FLAG_PCIE; 609 } 610 } 611 612 Static const char * 613 athn_get_mac_name(struct athn_softc *sc) 614 { 615 616 switch (sc->sc_mac_ver) { 617 case AR_SREV_VERSION_5416_PCI: 618 return "AR5416"; 619 case AR_SREV_VERSION_5416_PCIE: 620 return "AR5418"; 621 case AR_SREV_VERSION_9160: 622 return "AR9160"; 623 case AR_SREV_VERSION_9280: 624 return "AR9280"; 625 case AR_SREV_VERSION_9285: 626 return "AR9285"; 627 case AR_SREV_VERSION_9271: 628 return "AR9271"; 629 case AR_SREV_VERSION_9287: 630 return "AR9287"; 631 case AR_SREV_VERSION_9380: 632 return "AR9380"; 633 case AR_SREV_VERSION_9485: 634 return "AR9485"; 635 default: 636 return "unknown"; 637 } 638 } 639 640 /* 641 * Return RF chip name (not for single-chip solutions). 642 */ 643 Static const char * 644 athn_get_rf_name(struct athn_softc *sc) 645 { 646 647 KASSERT(!AR_SINGLE_CHIP(sc)); 648 649 switch (sc->sc_rf_rev) { 650 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 651 return "AR5133"; 652 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 653 return "AR2133"; 654 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 655 return "AR5122"; 656 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 657 return "AR2122"; 658 default: 659 return "unknown"; 660 } 661 } 662 663 PUBLIC int 664 athn_reset_power_on(struct athn_softc *sc) 665 { 666 int ntries; 667 668 /* Set force wake. */ 669 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 670 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 671 672 if (!AR_SREV_9380_10_OR_LATER(sc)) { 673 /* Make sure no DMA is active by doing an AHB reset. */ 674 AR_WRITE(sc, AR_RC, AR_RC_AHB); 675 } 676 /* RTC reset and clear. */ 677 AR_WRITE(sc, AR_RTC_RESET, 0); 678 AR_WRITE_BARRIER(sc); 679 DELAY(2); 680 if (!AR_SREV_9380_10_OR_LATER(sc)) 681 AR_WRITE(sc, AR_RC, 0); 682 AR_WRITE(sc, AR_RTC_RESET, 1); 683 684 /* Poll until RTC is ON. */ 685 for (ntries = 0; ntries < 1000; ntries++) { 686 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 687 AR_RTC_STATUS_ON) 688 break; 689 DELAY(10); 690 } 691 if (ntries == 1000) { 692 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 693 return ETIMEDOUT; 694 } 695 return athn_reset(sc, 0); 696 } 697 698 PUBLIC int 699 athn_reset(struct athn_softc *sc, int cold_reset) 700 { 701 int ntries; 702 703 /* Set force wake. */ 704 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 705 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 706 707 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 708 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 709 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 710 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 711 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 712 } 713 else if (!AR_SREV_9380_10_OR_LATER(sc)) 714 AR_WRITE(sc, AR_RC, AR_RC_AHB); 715 716 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 717 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 718 AR_WRITE_BARRIER(sc); 719 DELAY(50); 720 AR_WRITE(sc, AR_RTC_RC, 0); 721 for (ntries = 0; ntries < 1000; ntries++) { 722 if (!(AR_READ(sc, AR_RTC_RC) & 723 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 724 break; 725 DELAY(10); 726 } 727 if (ntries == 1000) { 728 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 729 return ETIMEDOUT; 730 } 731 AR_WRITE(sc, AR_RC, 0); 732 AR_WRITE_BARRIER(sc); 733 return 0; 734 } 735 736 PUBLIC int 737 athn_set_power_awake(struct athn_softc *sc) 738 { 739 int ntries, error; 740 741 /* Do a Power-On-Reset if shutdown. */ 742 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 743 AR_RTC_STATUS_SHUTDOWN) { 744 if ((error = athn_reset_power_on(sc)) != 0) 745 return error; 746 if (!AR_SREV_9380_10_OR_LATER(sc)) 747 athn_init_pll(sc, NULL); 748 } 749 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 750 AR_WRITE_BARRIER(sc); 751 DELAY(50); /* Give chip the chance to awake. */ 752 753 /* Poll until RTC is ON. */ 754 for (ntries = 0; ntries < 4000; ntries++) { 755 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 756 AR_RTC_STATUS_ON) 757 break; 758 DELAY(50); 759 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 760 } 761 if (ntries == 4000) { 762 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 763 return ETIMEDOUT; 764 } 765 766 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 767 AR_WRITE_BARRIER(sc); 768 return 0; 769 } 770 771 PUBLIC void 772 athn_set_power_sleep(struct athn_softc *sc) 773 { 774 775 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 776 /* Allow the MAC to go to sleep. */ 777 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 778 if (!AR_SREV_9380_10_OR_LATER(sc)) 779 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 780 /* 781 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 782 * results in high power consumption on AR5416 chipsets. 783 */ 784 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 785 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 786 AR_WRITE_BARRIER(sc); 787 } 788 789 PUBLIC void 790 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 791 { 792 uint32_t pll; 793 794 if (AR_SREV_9380_10_OR_LATER(sc)) { 795 if (AR_SREV_9485(sc)) 796 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 797 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 798 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 799 } 800 else if (AR_SREV_9280_10_OR_LATER(sc)) { 801 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 802 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 803 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 804 pll = 0x142c; 805 else if (AR_SREV_9280_20(sc)) 806 pll = 0x2850; 807 else 808 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 809 } 810 else 811 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 812 } 813 else if (AR_SREV_9160_10_OR_LATER(sc)) { 814 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 815 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 816 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 817 else 818 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 819 } 820 else { 821 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 822 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 823 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 824 else 825 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 826 } 827 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 828 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 829 if (AR_SREV_9271(sc)) { 830 /* Switch core clock to 117MHz. */ 831 AR_WRITE_BARRIER(sc); 832 DELAY(500); 833 AR_WRITE(sc, 0x50050, 0x304); 834 } 835 AR_WRITE_BARRIER(sc); 836 DELAY(100); 837 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 838 AR_WRITE_BARRIER(sc); 839 } 840 841 Static void 842 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 843 { 844 int i; 845 846 /* Write sequence to Serializer/Deserializer. */ 847 for (i = 0; i < serdes->nvals; i++) 848 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 849 AR_WRITE_BARRIER(sc); 850 } 851 852 PUBLIC void 853 athn_config_pcie(struct athn_softc *sc) 854 { 855 856 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 857 athn_write_serdes(sc, sc->sc_serdes); 858 859 DELAY(1000); 860 /* Allow forcing of PCIe core into L1 state. */ 861 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 862 863 #ifndef ATHN_PCIE_WAEN 864 AR_WRITE(sc, AR_WA, sc->sc_workaround); 865 #else 866 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 867 #endif 868 AR_WRITE_BARRIER(sc); 869 } 870 871 /* 872 * Serializer/Deserializer programming for non-PCIe devices. 873 */ 874 static const uint32_t ar_nonpcie_serdes_regs[] = { 875 AR_PCIE_SERDES, 876 AR_PCIE_SERDES, 877 AR_PCIE_SERDES, 878 AR_PCIE_SERDES, 879 AR_PCIE_SERDES, 880 AR_PCIE_SERDES, 881 AR_PCIE_SERDES, 882 AR_PCIE_SERDES, 883 AR_PCIE_SERDES, 884 AR_PCIE_SERDES2, 885 }; 886 887 static const uint32_t ar_nonpcie_serdes_vals[] = { 888 0x9248fc00, 889 0x24924924, 890 0x28000029, 891 0x57160824, 892 0x25980579, 893 0x00000000, 894 0x1aaabe40, 895 0xbe105554, 896 0x000e1007, 897 0x00000000 898 }; 899 900 static const struct athn_serdes ar_nonpcie_serdes = { 901 __arraycount(ar_nonpcie_serdes_vals), 902 ar_nonpcie_serdes_regs, 903 ar_nonpcie_serdes_vals 904 }; 905 906 PUBLIC void 907 athn_config_nonpcie(struct athn_softc *sc) 908 { 909 910 athn_write_serdes(sc, &ar_nonpcie_serdes); 911 } 912 913 PUBLIC int 914 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 915 struct ieee80211_channel *extchan) 916 { 917 struct athn_ops *ops = &sc->sc_ops; 918 int error, qid; 919 920 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 921 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 922 if (athn_tx_pending(sc, qid)) 923 return EBUSY; 924 925 /* Request RF Bus grant. */ 926 if ((error = ops->rf_bus_request(sc)) != 0) 927 return error; 928 929 ops->set_phy(sc, curchan, extchan); 930 931 /* Change the synthesizer. */ 932 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 933 return error; 934 935 sc->sc_curchan = curchan; 936 sc->sc_curchanext = extchan; 937 938 /* Set transmit power values for new channel. */ 939 ops->set_txpower(sc, curchan, extchan); 940 941 /* Release the RF Bus grant. */ 942 ops->rf_bus_release(sc); 943 944 /* Write delta slope coeffs for modes where OFDM may be used. */ 945 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 946 ops->set_delta_slope(sc, curchan, extchan); 947 948 ops->spur_mitigate(sc, curchan, extchan); 949 /* XXX Load noisefloor values and start calibration. */ 950 951 return 0; 952 } 953 954 Static int 955 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 956 struct ieee80211_channel *extchan) 957 { 958 int error, qid; 959 960 /* Disable interrupts. */ 961 athn_disable_interrupts(sc); 962 963 /* Stop all Tx queues. */ 964 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 965 athn_stop_tx_dma(sc, qid); 966 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 967 athn_tx_reclaim(sc, qid); 968 969 /* Stop Rx. */ 970 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 971 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 972 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 973 AR_WRITE(sc, AR_FILT_OFDM, 0); 974 AR_WRITE(sc, AR_FILT_CCK, 0); 975 athn_set_rxfilter(sc, 0); 976 error = athn_stop_rx_dma(sc); 977 if (error != 0) 978 goto reset; 979 980 #ifdef notyet 981 /* AR9280 needs a full reset. */ 982 if (AR_SREV_9280(sc)) 983 #endif 984 goto reset; 985 986 /* If band or bandwidth changes, we need to do a full reset. */ 987 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 988 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 989 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 990 goto reset; 991 } 992 error = athn_set_power_awake(sc); 993 if (error != 0) 994 goto reset; 995 996 error = athn_set_chan(sc, curchan, extchan); 997 if (error != 0) { 998 reset: /* Error found, try a full reset. */ 999 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 1000 error = athn_hw_reset(sc, curchan, extchan, 0); 1001 if (error != 0) /* Hopeless case. */ 1002 return error; 1003 } 1004 athn_rx_start(sc); 1005 1006 /* Re-enable interrupts. */ 1007 athn_enable_interrupts(sc); 1008 return 0; 1009 } 1010 1011 PUBLIC void 1012 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1013 { 1014 #define COEFF_SCALE_SHIFT 24 1015 uint32_t exp, man; 1016 1017 /* exponent = 14 - floor(log2(coeff)) */ 1018 for (exp = 31; exp > 0; exp--) 1019 if (coeff & (1 << exp)) 1020 break; 1021 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1022 1023 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1024 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1025 1026 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1027 *exponent = exp - 16; 1028 #undef COEFF_SCALE_SHIFT 1029 } 1030 1031 PUBLIC void 1032 athn_reset_key(struct athn_softc *sc, int entry) 1033 { 1034 1035 /* 1036 * NB: Key cache registers access special memory area that requires 1037 * two 32-bit writes to actually update the values in the internal 1038 * memory. Consequently, writes must be grouped by pair. 1039 */ 1040 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1041 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1042 1043 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1044 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1045 1046 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1047 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1048 1049 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1050 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1051 1052 AR_WRITE_BARRIER(sc); 1053 } 1054 1055 #ifdef notyet 1056 Static int 1057 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1058 struct ieee80211_key *k) 1059 { 1060 struct athn_softc *sc = ic->ic_ifp->if_softc; 1061 const uint8_t *txmic, *rxmic, *key, *addr; 1062 uintptr_t entry, micentry; 1063 uint32_t type, lo, hi; 1064 1065 switch (k->k_cipher) { 1066 case IEEE80211_CIPHER_WEP40: 1067 type = AR_KEYTABLE_TYPE_40; 1068 break; 1069 case IEEE80211_CIPHER_WEP104: 1070 type = AR_KEYTABLE_TYPE_104; 1071 break; 1072 case IEEE80211_CIPHER_TKIP: 1073 type = AR_KEYTABLE_TYPE_TKIP; 1074 break; 1075 case IEEE80211_CIPHER_CCMP: 1076 type = AR_KEYTABLE_TYPE_CCM; 1077 break; 1078 default: 1079 /* Fallback to software crypto for other ciphers. */ 1080 return ieee80211_set_key(ic, ni, k); 1081 } 1082 1083 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1084 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1085 else 1086 entry = k->k_id; 1087 k->k_priv = (void *)entry; 1088 1089 /* NB: See note about key cache registers access above. */ 1090 key = k->k_key; 1091 if (type == AR_KEYTABLE_TYPE_TKIP) { 1092 #ifndef IEEE80211_STA_ONLY 1093 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1094 txmic = &key[16]; 1095 rxmic = &key[24]; 1096 } 1097 else 1098 #endif 1099 { 1100 rxmic = &key[16]; 1101 txmic = &key[24]; 1102 } 1103 /* Tx+Rx MIC key is at entry + 64. */ 1104 micentry = entry + 64; 1105 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1106 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1107 1108 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1109 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1110 1111 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1112 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1113 } 1114 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1115 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1116 1117 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1118 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1119 1120 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1121 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1122 1123 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1124 addr = ni->ni_macaddr; 1125 lo = LE_READ_4(&addr[0]); 1126 hi = LE_READ_2(&addr[4]); 1127 lo = lo >> 1 | hi << 31; 1128 hi = hi >> 1; 1129 } 1130 else 1131 lo = hi = 0; 1132 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1133 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1134 AR_WRITE_BARRIER(sc); 1135 return 0; 1136 } 1137 1138 Static void 1139 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1140 struct ieee80211_key *k) 1141 { 1142 struct athn_softc *sc = ic->ic_ifp->if_softc; 1143 uintptr_t entry; 1144 1145 switch (k->k_cipher) { 1146 case IEEE80211_CIPHER_WEP40: 1147 case IEEE80211_CIPHER_WEP104: 1148 case IEEE80211_CIPHER_CCMP: 1149 entry = (uintptr_t)k->k_priv; 1150 athn_reset_key(sc, entry); 1151 break; 1152 case IEEE80211_CIPHER_TKIP: 1153 entry = (uintptr_t)k->k_priv; 1154 athn_reset_key(sc, entry); 1155 athn_reset_key(sc, entry + 64); 1156 break; 1157 default: 1158 /* Fallback to software crypto for other ciphers. */ 1159 ieee80211_delete_key(ic, ni, k); 1160 } 1161 } 1162 #endif /* notyet */ 1163 1164 PUBLIC void 1165 athn_led_init(struct athn_softc *sc) 1166 { 1167 struct athn_ops *ops = &sc->sc_ops; 1168 1169 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1170 /* LED off, active low. */ 1171 athn_set_led(sc, 0); 1172 } 1173 1174 PUBLIC void 1175 athn_set_led(struct athn_softc *sc, int on) 1176 { 1177 struct athn_ops *ops = &sc->sc_ops; 1178 1179 sc->sc_led_state = on; 1180 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1181 } 1182 1183 #ifdef ATHN_BT_COEXISTENCE 1184 Static void 1185 athn_btcoex_init(struct athn_softc *sc) 1186 { 1187 struct athn_ops *ops = &sc->sc_ops; 1188 uint32_t reg; 1189 1190 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1191 /* Connect bt_active to baseband. */ 1192 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1193 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1194 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1195 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1196 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1197 1198 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1199 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1200 AR_GPIO_BTACTIVE_PIN); 1201 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1202 AR_WRITE_BARRIER(sc); 1203 1204 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1205 } 1206 else { /* 3-wire. */ 1207 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1208 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1209 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1210 1211 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1212 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1213 AR_GPIO_BTACTIVE_PIN); 1214 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1215 AR_GPIO_BTPRIORITY_PIN); 1216 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1217 AR_WRITE_BARRIER(sc); 1218 1219 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1220 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1221 } 1222 } 1223 1224 Static void 1225 athn_btcoex_enable(struct athn_softc *sc) 1226 { 1227 struct athn_ops *ops = &sc->sc_ops; 1228 uint32_t reg; 1229 1230 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1231 AR_WRITE(sc, AR_BT_COEX_MODE, 1232 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1233 SM(AR_BT_PRIORITY_TIME, 2) | 1234 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1235 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1236 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1237 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1238 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1239 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1240 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1241 AR_WRITE(sc, AR_BT_COEX_MODE2, 1242 SM(AR_BT_BCN_MISS_THRESH, 50) | 1243 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1244 1245 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1246 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1247 AR_WRITE_BARRIER(sc); 1248 1249 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1250 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1251 1252 } 1253 else { /* 2-wire. */ 1254 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1255 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1256 } 1257 reg = AR_READ(sc, AR_GPIO_PDPU); 1258 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1259 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1260 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1261 AR_WRITE_BARRIER(sc); 1262 1263 /* Disable PCIe Active State Power Management (ASPM). */ 1264 if (sc->sc_disable_aspm != NULL) 1265 sc->sc_disable_aspm(sc); 1266 1267 /* XXX Start periodic timer. */ 1268 } 1269 1270 Static void 1271 athn_btcoex_disable(struct athn_softc *sc) 1272 { 1273 struct athn_ops *ops = &sc->sc_ops; 1274 1275 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1276 1277 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1278 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1279 1280 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1281 AR_WRITE(sc, AR_BT_COEX_MODE, 1282 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1283 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1284 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1285 /* XXX Stop periodic timer. */ 1286 } 1287 AR_WRITE_BARRIER(sc); 1288 /* XXX Restore ASPM setting? */ 1289 } 1290 #endif 1291 1292 Static void 1293 athn_iter_func(void *arg, struct ieee80211_node *ni) 1294 { 1295 struct athn_softc *sc = arg; 1296 struct athn_node *an = (struct athn_node *)ni; 1297 1298 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1299 } 1300 1301 Static void 1302 athn_calib_to(void *arg) 1303 { 1304 extern int ticks; 1305 struct athn_softc *sc = arg; 1306 struct athn_ops *ops = &sc->sc_ops; 1307 struct ieee80211com *ic = &sc->sc_ic; 1308 int s; 1309 1310 s = splnet(); 1311 1312 /* Do periodic (every 4 minutes) PA calibration. */ 1313 if (AR_SREV_9285_11_OR_LATER(sc) && 1314 !AR_SREV_9380_10_OR_LATER(sc) && 1315 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1316 sc->sc_pa_calib_ticks = ticks; 1317 if (AR_SREV_9271(sc)) 1318 ar9271_pa_calib(sc); 1319 else 1320 ar9285_pa_calib(sc); 1321 } 1322 1323 /* Do periodic (every 30 seconds) temperature compensation. */ 1324 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1325 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1326 sc->sc_olpc_ticks = ticks; 1327 ops->olpc_temp_compensation(sc); 1328 } 1329 1330 #ifdef notyet 1331 /* XXX ANI. */ 1332 athn_ani_monitor(sc); 1333 1334 ops->next_calib(sc); 1335 #endif 1336 if (ic->ic_fixed_rate == -1) { 1337 if (ic->ic_opmode == IEEE80211_M_STA) 1338 athn_iter_func(sc, ic->ic_bss); 1339 else 1340 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1341 } 1342 callout_schedule(&sc->sc_calib_to, hz / 2); 1343 splx(s); 1344 } 1345 1346 Static int 1347 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1348 struct ieee80211_channel *extchan) 1349 { 1350 struct athn_ops *ops = &sc->sc_ops; 1351 int error; 1352 1353 if (AR_SREV_9380_10_OR_LATER(sc)) 1354 error = ar9003_init_calib(sc); 1355 else if (AR_SREV_9285_10_OR_LATER(sc)) 1356 error = ar9285_init_calib(sc, curchan, extchan); 1357 else 1358 error = ar5416_init_calib(sc, curchan, extchan); 1359 if (error != 0) 1360 return error; 1361 1362 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1363 /* Do PA calibration. */ 1364 if (AR_SREV_9285_11_OR_LATER(sc)) { 1365 extern int ticks; 1366 sc->sc_pa_calib_ticks = ticks; 1367 if (AR_SREV_9271(sc)) 1368 ar9271_pa_calib(sc); 1369 else 1370 ar9285_pa_calib(sc); 1371 } 1372 /* Do noisefloor calibration. */ 1373 ops->noisefloor_calib(sc); 1374 } 1375 if (AR_SREV_9160_10_OR_LATER(sc)) { 1376 /* Support IQ calibration. */ 1377 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1378 if (AR_SREV_9380_10_OR_LATER(sc)) { 1379 /* Support temperature compensation calibration. */ 1380 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1381 } 1382 else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1383 /* 1384 * ADC gain calibration causes uplink throughput 1385 * drops in HT40 mode on AR9287. 1386 */ 1387 if (!AR_SREV_9287(sc)) { 1388 /* Support ADC gain calibration. */ 1389 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1390 } 1391 /* Support ADC DC offset calibration. */ 1392 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1393 } 1394 } 1395 return 0; 1396 } 1397 1398 /* 1399 * Adaptive noise immunity. 1400 */ 1401 #ifdef notyet 1402 Static int32_t 1403 athn_ani_get_rssi(struct athn_softc *sc) 1404 { 1405 1406 return 0; /* XXX */ 1407 } 1408 #endif /* notyet */ 1409 1410 #ifdef notyet 1411 Static void 1412 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1413 { 1414 struct athn_ani *ani = &sc->sc_ani; 1415 struct athn_ops *ops = &sc->sc_ops; 1416 int32_t rssi; 1417 1418 /* First, raise noise immunity level, up to max. */ 1419 if (ani->noise_immunity_level < 4) { 1420 ani->noise_immunity_level++; 1421 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1422 return; 1423 } 1424 1425 /* Then, raise our spur immunity level, up to max. */ 1426 if (ani->spur_immunity_level < 7) { 1427 ani->spur_immunity_level++; 1428 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1429 return; 1430 } 1431 1432 #ifndef IEEE80211_STA_ONLY 1433 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1434 if (ani->firstep_level < 2) { 1435 ani->firstep_level++; 1436 ops->set_firstep_level(sc, ani->firstep_level); 1437 } 1438 return; 1439 } 1440 #endif 1441 rssi = athn_ani_get_rssi(sc); 1442 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1443 /* 1444 * Beacon RSSI is high, turn off OFDM weak signal detection 1445 * or raise first step level as last resort. 1446 */ 1447 if (ani->ofdm_weak_signal) { 1448 ani->ofdm_weak_signal = 0; 1449 ops->disable_ofdm_weak_signal(sc); 1450 ani->spur_immunity_level = 0; 1451 ops->set_spur_immunity_level(sc, 0); 1452 } 1453 else if (ani->firstep_level < 2) { 1454 ani->firstep_level++; 1455 ops->set_firstep_level(sc, ani->firstep_level); 1456 } 1457 } 1458 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1459 /* 1460 * Beacon RSSI is in mid range, we need OFDM weak signal 1461 * detection but we can raise first step level. 1462 */ 1463 if (!ani->ofdm_weak_signal) { 1464 ani->ofdm_weak_signal = 1; 1465 ops->enable_ofdm_weak_signal(sc); 1466 } 1467 if (ani->firstep_level < 2) { 1468 ani->firstep_level++; 1469 ops->set_firstep_level(sc, ani->firstep_level); 1470 } 1471 } 1472 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1473 /* 1474 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1475 * signal detection and zero first step level to maximize 1476 * CCK sensitivity. 1477 */ 1478 if (ani->ofdm_weak_signal) { 1479 ani->ofdm_weak_signal = 0; 1480 ops->disable_ofdm_weak_signal(sc); 1481 } 1482 if (ani->firstep_level > 0) { 1483 ani->firstep_level = 0; 1484 ops->set_firstep_level(sc, 0); 1485 } 1486 } 1487 } 1488 #endif /* notyet */ 1489 1490 #ifdef notyet 1491 Static void 1492 athn_ani_cck_err_trigger(struct athn_softc *sc) 1493 { 1494 struct athn_ani *ani = &sc->sc_ani; 1495 struct athn_ops *ops = &sc->sc_ops; 1496 int32_t rssi; 1497 1498 /* Raise noise immunity level, up to max. */ 1499 if (ani->noise_immunity_level < 4) { 1500 ani->noise_immunity_level++; 1501 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1502 return; 1503 } 1504 1505 #ifndef IEEE80211_STA_ONLY 1506 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1507 if (ani->firstep_level < 2) { 1508 ani->firstep_level++; 1509 ops->set_firstep_level(sc, ani->firstep_level); 1510 } 1511 return; 1512 } 1513 #endif 1514 rssi = athn_ani_get_rssi(sc); 1515 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1516 /* 1517 * Beacon RSSI is in mid or high range, raise first step 1518 * level. 1519 */ 1520 if (ani->firstep_level < 2) { 1521 ani->firstep_level++; 1522 ops->set_firstep_level(sc, ani->firstep_level); 1523 } 1524 } 1525 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1526 /* 1527 * Beacon RSSI is low, zero first step level to maximize 1528 * CCK sensitivity. 1529 */ 1530 if (ani->firstep_level > 0) { 1531 ani->firstep_level = 0; 1532 ops->set_firstep_level(sc, 0); 1533 } 1534 } 1535 } 1536 #endif /* notyet */ 1537 1538 #ifdef notyet 1539 Static void 1540 athn_ani_lower_immunity(struct athn_softc *sc) 1541 { 1542 struct athn_ani *ani = &sc->sc_ani; 1543 struct athn_ops *ops = &sc->sc_ops; 1544 int32_t rssi; 1545 1546 #ifndef IEEE80211_STA_ONLY 1547 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1548 if (ani->firstep_level > 0) { 1549 ani->firstep_level--; 1550 ops->set_firstep_level(sc, ani->firstep_level); 1551 } 1552 return; 1553 } 1554 #endif 1555 rssi = athn_ani_get_rssi(sc); 1556 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1557 /* 1558 * Beacon RSSI is high, leave OFDM weak signal detection 1559 * off or it may oscillate. 1560 */ 1561 } 1562 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1563 /* 1564 * Beacon RSSI is in mid range, turn on OFDM weak signal 1565 * detection or lower first step level. 1566 */ 1567 if (!ani->ofdm_weak_signal) { 1568 ani->ofdm_weak_signal = 1; 1569 ops->enable_ofdm_weak_signal(sc); 1570 return; 1571 } 1572 if (ani->firstep_level > 0) { 1573 ani->firstep_level--; 1574 ops->set_firstep_level(sc, ani->firstep_level); 1575 return; 1576 } 1577 } 1578 else { 1579 /* Beacon RSSI is low, lower first step level. */ 1580 if (ani->firstep_level > 0) { 1581 ani->firstep_level--; 1582 ops->set_firstep_level(sc, ani->firstep_level); 1583 return; 1584 } 1585 } 1586 /* 1587 * Lower spur immunity level down to zero, or if all else fails, 1588 * lower noise immunity level down to zero. 1589 */ 1590 if (ani->spur_immunity_level > 0) { 1591 ani->spur_immunity_level--; 1592 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1593 } 1594 else if (ani->noise_immunity_level > 0) { 1595 ani->noise_immunity_level--; 1596 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1597 } 1598 } 1599 #endif /* notyet */ 1600 1601 #ifdef notyet 1602 Static void 1603 athn_ani_restart(struct athn_softc *sc) 1604 { 1605 struct athn_ani *ani = &sc->sc_ani; 1606 1607 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1608 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1609 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1610 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1611 AR_WRITE_BARRIER(sc); 1612 1613 ani->listen_time = 0; 1614 ani->ofdm_phy_err_count = 0; 1615 ani->cck_phy_err_count = 0; 1616 } 1617 #endif /* notyet */ 1618 1619 #ifdef notyet 1620 Static void 1621 athn_ani_monitor(struct athn_softc *sc) 1622 { 1623 struct athn_ani *ani = &sc->sc_ani; 1624 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1625 int32_t cycdelta, txfdelta, rxfdelta; 1626 int32_t listen_time; 1627 1628 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1629 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1630 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1631 1632 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1633 cycdelta = cyccnt - ani->cyccnt; 1634 txfdelta = txfcnt - ani->txfcnt; 1635 rxfdelta = rxfcnt - ani->rxfcnt; 1636 1637 listen_time = (cycdelta - txfdelta - rxfdelta) / 1638 (athn_clock_rate(sc) * 1000); 1639 } 1640 else 1641 listen_time = 0; 1642 1643 ani->cyccnt = cyccnt; 1644 ani->txfcnt = txfcnt; 1645 ani->rxfcnt = rxfcnt; 1646 1647 if (listen_time < 0) { 1648 athn_ani_restart(sc); 1649 return; 1650 } 1651 ani->listen_time += listen_time; 1652 1653 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1654 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1655 1656 if (phy1 < ani->ofdm_phy_err_base) { 1657 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1658 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1659 } 1660 if (phy2 < ani->cck_phy_err_base) { 1661 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1662 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1663 } 1664 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1665 AR_WRITE_BARRIER(sc); 1666 return; 1667 } 1668 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1669 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1670 1671 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1672 /* Check to see if we need to lower immunity. */ 1673 if (ani->ofdm_phy_err_count <= 1674 ani->listen_time * ani->ofdm_trig_low / 1000 && 1675 ani->cck_phy_err_count <= 1676 ani->listen_time * ani->cck_trig_low / 1000) 1677 athn_ani_lower_immunity(sc); 1678 athn_ani_restart(sc); 1679 1680 } 1681 else if (ani->listen_time > ATHN_ANI_PERIOD) { 1682 /* Check to see if we need to raise immunity. */ 1683 if (ani->ofdm_phy_err_count > 1684 ani->listen_time * ani->ofdm_trig_high / 1000) { 1685 athn_ani_ofdm_err_trigger(sc); 1686 athn_ani_restart(sc); 1687 } 1688 else if (ani->cck_phy_err_count > 1689 ani->listen_time * ani->cck_trig_high / 1000) { 1690 athn_ani_cck_err_trigger(sc); 1691 athn_ani_restart(sc); 1692 } 1693 } 1694 } 1695 #endif /* notyet */ 1696 1697 PUBLIC uint8_t 1698 athn_chan2fbin(struct ieee80211_channel *c) 1699 { 1700 1701 if (IEEE80211_IS_CHAN_2GHZ(c)) 1702 return c->ic_freq - 2300; 1703 else 1704 return (c->ic_freq - 4800) / 5; 1705 } 1706 1707 PUBLIC int 1708 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1709 { 1710 1711 if (x1 == x2) /* Prevents division by zero. */ 1712 return y1; 1713 /* Linear interpolation. */ 1714 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1715 } 1716 1717 PUBLIC void 1718 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1719 int *lo, int *hi) 1720 { 1721 int i; 1722 1723 for (i = 0; i < npiers; i++) 1724 if (pierfreq[i] == AR_BCHAN_UNUSED || 1725 pierfreq[i] > fbin) 1726 break; 1727 *hi = i; 1728 *lo = *hi - 1; 1729 if (*lo == -1) 1730 *lo = *hi; 1731 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1732 *hi = *lo; 1733 } 1734 1735 Static void 1736 athn_init_dma(struct athn_softc *sc) 1737 { 1738 uint32_t reg; 1739 1740 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1741 /* Set AHB not to do cacheline prefetches. */ 1742 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1743 } 1744 reg = AR_READ(sc, AR_TXCFG); 1745 /* Let MAC DMA reads be in 128-byte chunks. */ 1746 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1747 1748 /* Set initial Tx trigger level. */ 1749 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1750 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1751 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1752 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1753 AR_WRITE(sc, AR_TXCFG, reg); 1754 1755 /* Let MAC DMA writes be in 128-byte chunks. */ 1756 reg = AR_READ(sc, AR_RXCFG); 1757 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1758 AR_WRITE(sc, AR_RXCFG, reg); 1759 1760 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1761 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1762 1763 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1764 if (AR_SREV_9285(sc)) { 1765 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1766 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1767 } 1768 else if (!AR_SREV_9271(sc)) { 1769 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1770 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1771 } 1772 AR_WRITE_BARRIER(sc); 1773 1774 /* Reset Tx status ring. */ 1775 if (AR_SREV_9380_10_OR_LATER(sc)) 1776 ar9003_reset_txsring(sc); 1777 } 1778 1779 PUBLIC void 1780 athn_inc_tx_trigger_level(struct athn_softc *sc) 1781 { 1782 uint32_t reg, ftrig; 1783 1784 reg = AR_READ(sc, AR_TXCFG); 1785 ftrig = MS(reg, AR_TXCFG_FTRIG); 1786 /* 1787 * NB: The AR9285 and all single-stream parts have an issue that 1788 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1789 */ 1790 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1791 return; /* Already at max. */ 1792 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1793 AR_WRITE(sc, AR_TXCFG, reg); 1794 AR_WRITE_BARRIER(sc); 1795 } 1796 1797 PUBLIC int 1798 athn_stop_rx_dma(struct athn_softc *sc) 1799 { 1800 int ntries; 1801 1802 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1803 /* Wait for Rx enable bit to go low. */ 1804 for (ntries = 0; ntries < 100; ntries++) { 1805 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1806 return 0; 1807 DELAY(100); 1808 } 1809 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1810 return ETIMEDOUT; 1811 } 1812 1813 #ifdef unused 1814 Static int 1815 athn_rx_abort(struct athn_softc *sc) 1816 { 1817 int ntries; 1818 1819 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1820 for (ntries = 0; ntries < 1000; ntries++) { 1821 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1822 return 0; 1823 DELAY(10); 1824 } 1825 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1826 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1827 AR_WRITE_BARRIER(sc); 1828 return ETIMEDOUT; 1829 } 1830 #endif /* unused */ 1831 1832 Static void 1833 athn_tx_reclaim(struct athn_softc *sc, int qid) 1834 { 1835 struct athn_txq *txq = &sc->sc_txq[qid]; 1836 struct athn_tx_buf *bf; 1837 1838 /* Reclaim all buffers queued in the specified Tx queue. */ 1839 /* NB: Tx DMA must be stopped. */ 1840 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1841 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1842 1843 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1844 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1845 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1846 m_freem(bf->bf_m); 1847 bf->bf_m = NULL; 1848 bf->bf_ni = NULL; /* Nodes already freed! */ 1849 1850 /* Link Tx buffer back to global free list. */ 1851 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1852 } 1853 } 1854 1855 PUBLIC int 1856 athn_tx_pending(struct athn_softc *sc, int qid) 1857 { 1858 1859 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1860 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1861 } 1862 1863 PUBLIC void 1864 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1865 { 1866 uint32_t tsflo; 1867 int ntries, i; 1868 1869 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1870 for (ntries = 0; ntries < 40; ntries++) { 1871 if (!athn_tx_pending(sc, qid)) 1872 break; 1873 DELAY(100); 1874 } 1875 if (ntries == 40) { 1876 for (i = 0; i < 2; i++) { 1877 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1878 AR_WRITE(sc, AR_QUIET2, 1879 SM(AR_QUIET2_QUIET_DUR, 10)); 1880 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1881 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1882 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1883 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1884 break; 1885 } 1886 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1887 AR_WRITE_BARRIER(sc); 1888 DELAY(200); 1889 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1890 AR_WRITE_BARRIER(sc); 1891 1892 for (ntries = 0; ntries < 40; ntries++) { 1893 if (!athn_tx_pending(sc, qid)) 1894 break; 1895 DELAY(100); 1896 } 1897 1898 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1899 } 1900 AR_WRITE(sc, AR_Q_TXD, 0); 1901 AR_WRITE_BARRIER(sc); 1902 } 1903 1904 PUBLIC int 1905 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1906 { 1907 #define divround(a, b) (((a) + (b) - 1) / (b)) 1908 int txtime; 1909 1910 /* XXX HT. */ 1911 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1912 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1913 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1914 txtime = 16 + 4 + 4 * txtime + 16; 1915 } 1916 else { 1917 txtime = divround(16 * len, athn_rates[ridx].rate); 1918 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1919 txtime += 72 + 24; 1920 else 1921 txtime += 144 + 48; 1922 txtime += 10; /* 10us SIFS. */ 1923 } 1924 return txtime; 1925 #undef divround 1926 } 1927 1928 PUBLIC void 1929 athn_init_tx_queues(struct athn_softc *sc) 1930 { 1931 int qid; 1932 1933 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1934 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1935 sc->sc_txq[qid].lastds = NULL; 1936 sc->sc_txq[qid].wait = NULL; 1937 sc->sc_txq[qid].queued = 0; 1938 1939 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1940 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1941 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1942 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1943 AR_WRITE(sc, AR_QMISC(qid), 1944 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1945 AR_WRITE(sc, AR_DMISC(qid), 1946 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1947 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1948 } 1949 1950 /* Init beacon queue. */ 1951 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1952 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1953 AR_Q_MISC_CBR_INCR_DIS1); 1954 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1955 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1956 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1957 AR_D_MISC_BEACON_USE | 1958 AR_D_MISC_POST_FR_BKOFF_DIS); 1959 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1960 SM(AR_D_LCL_IFS_CWMIN, 0) | 1961 SM(AR_D_LCL_IFS_CWMAX, 0) | 1962 SM(AR_D_LCL_IFS_AIFS, 1)); 1963 1964 /* Init CAB (Content After Beacon) queue. */ 1965 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1966 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1967 AR_Q_MISC_CBR_INCR_DIS0); 1968 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1969 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1970 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1971 1972 /* Init PS-Poll queue. */ 1973 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1974 AR_Q_MISC_CBR_INCR_DIS1); 1975 1976 /* Init UAPSD queue. */ 1977 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1978 AR_D_MISC_POST_FR_BKOFF_DIS); 1979 1980 if (AR_SREV_9380_10_OR_LATER(sc)) { 1981 /* Enable MAC descriptor CRC check. */ 1982 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1983 } 1984 /* Enable DESC interrupts for all Tx queues. */ 1985 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1986 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1987 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1988 AR_WRITE_BARRIER(sc); 1989 } 1990 1991 PUBLIC void 1992 athn_set_sta_timers(struct athn_softc *sc) 1993 { 1994 struct ieee80211com *ic = &sc->sc_ic; 1995 uint32_t tsfhi, tsflo, tsftu, reg; 1996 uint32_t intval, next_tbtt, next_dtim; 1997 int dtim_period, rem_dtim_count; 1998 1999 tsfhi = AR_READ(sc, AR_TSF_U32); 2000 tsflo = AR_READ(sc, AR_TSF_L32); 2001 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 2002 2003 /* Beacon interval in TU. */ 2004 intval = ic->ic_bss->ni_intval; 2005 2006 next_tbtt = roundup(tsftu, intval); 2007 #ifdef notyet 2008 dtim_period = ic->ic_dtim_period; 2009 if (dtim_period <= 0) 2010 #endif 2011 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2012 2013 #ifdef notyet 2014 int dtim_count = ic->ic_dtim_count; 2015 if (dtim_count >= dtim_period) /* Should not happen. */ 2016 dtim_count = 0; /* Assume last TIM was a DTIM. */ 2017 #endif 2018 2019 /* Compute number of remaining TIMs until next DTIM. */ 2020 rem_dtim_count = 0; /* XXX */ 2021 next_dtim = next_tbtt + rem_dtim_count * intval; 2022 2023 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2024 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2025 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2026 2027 /* 2028 * Set the number of consecutive beacons to miss before raising 2029 * a BMISS interrupt to 10. 2030 */ 2031 reg = AR_READ(sc, AR_RSSI_THR); 2032 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2033 AR_WRITE(sc, AR_RSSI_THR, reg); 2034 2035 AR_WRITE(sc, AR_NEXT_DTIM, 2036 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2037 AR_WRITE(sc, AR_NEXT_TIM, 2038 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2039 2040 /* CAB timeout is in 1/8 TU. */ 2041 AR_WRITE(sc, AR_SLEEP1, 2042 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2043 AR_SLEEP1_ASSUME_DTIM); 2044 AR_WRITE(sc, AR_SLEEP2, 2045 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2046 2047 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2048 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2049 2050 AR_SETBITS(sc, AR_TIMER_MODE, 2051 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2052 2053 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2054 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2055 2056 AR_WRITE_BARRIER(sc); 2057 } 2058 2059 #ifndef IEEE80211_STA_ONLY 2060 PUBLIC void 2061 athn_set_hostap_timers(struct athn_softc *sc) 2062 { 2063 struct ieee80211com *ic = &sc->sc_ic; 2064 uint32_t intval, next_tbtt; 2065 2066 /* Beacon interval in TU. */ 2067 intval = ic->ic_bss->ni_intval; 2068 next_tbtt = intval; 2069 2070 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2071 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2072 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2073 AR_WRITE(sc, AR_NEXT_CFP, 2074 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2075 2076 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2077 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2078 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2079 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2080 2081 AR_WRITE(sc, AR_TIMER_MODE, 2082 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2083 2084 AR_WRITE_BARRIER(sc); 2085 } 2086 #endif 2087 2088 PUBLIC void 2089 athn_set_opmode(struct athn_softc *sc) 2090 { 2091 uint32_t reg; 2092 2093 switch (sc->sc_ic.ic_opmode) { 2094 #ifndef IEEE80211_STA_ONLY 2095 case IEEE80211_M_HOSTAP: 2096 reg = AR_READ(sc, AR_STA_ID1); 2097 reg &= ~AR_STA_ID1_ADHOC; 2098 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2099 AR_WRITE(sc, AR_STA_ID1, reg); 2100 2101 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2102 break; 2103 case IEEE80211_M_IBSS: 2104 case IEEE80211_M_AHDEMO: 2105 reg = AR_READ(sc, AR_STA_ID1); 2106 reg &= ~AR_STA_ID1_STA_AP; 2107 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2108 AR_WRITE(sc, AR_STA_ID1, reg); 2109 2110 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2111 break; 2112 #endif 2113 default: 2114 reg = AR_READ(sc, AR_STA_ID1); 2115 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2116 reg |= AR_STA_ID1_KSRCH_MODE; 2117 AR_WRITE(sc, AR_STA_ID1, reg); 2118 break; 2119 } 2120 AR_WRITE_BARRIER(sc); 2121 } 2122 2123 PUBLIC void 2124 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2125 { 2126 const uint8_t *bssid = ni->ni_bssid; 2127 2128 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2129 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2130 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2131 AR_WRITE_BARRIER(sc); 2132 } 2133 2134 Static void 2135 athn_enable_interrupts(struct athn_softc *sc) 2136 { 2137 uint32_t mask2; 2138 2139 athn_disable_interrupts(sc); /* XXX */ 2140 2141 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2142 2143 mask2 = AR_READ(sc, AR_IMR_S2); 2144 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2145 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2146 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2147 AR_WRITE(sc, AR_IMR_S2, mask2); 2148 2149 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2150 2151 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2152 2153 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2154 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2155 2156 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2157 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2158 AR_WRITE_BARRIER(sc); 2159 } 2160 2161 Static void 2162 athn_disable_interrupts(struct athn_softc *sc) 2163 { 2164 2165 AR_WRITE(sc, AR_IER, 0); 2166 (void)AR_READ(sc, AR_IER); 2167 2168 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2169 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2170 2171 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2172 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2173 2174 AR_WRITE(sc, AR_IMR, 0); 2175 2176 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2177 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2178 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2179 2180 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2181 AR_WRITE_BARRIER(sc); 2182 } 2183 2184 Static void 2185 athn_init_qos(struct athn_softc *sc) 2186 { 2187 2188 /* Initialize QoS settings. */ 2189 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2190 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2191 AR_WRITE(sc, AR_QOS_NO_ACK, 2192 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2193 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2194 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2195 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2196 /* Initialize TXOP for all TIDs. */ 2197 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2198 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2199 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2200 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2201 AR_WRITE_BARRIER(sc); 2202 } 2203 2204 PUBLIC int 2205 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2206 struct ieee80211_channel *extchan, int init) 2207 { 2208 struct ieee80211com *ic = &sc->sc_ic; 2209 struct athn_ops *ops = &sc->sc_ops; 2210 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2211 int i, error; 2212 2213 /* XXX not if already awake */ 2214 if ((error = athn_set_power_awake(sc)) != 0) { 2215 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2216 return error; 2217 } 2218 2219 /* Preserve the antenna on a channel switch. */ 2220 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2221 def_ant = 1; 2222 /* Preserve other registers. */ 2223 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2224 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2225 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2226 AR_CFG_LED_BLINK_SLOW); 2227 2228 /* Mark PHY as inactive. */ 2229 ops->disable_phy(sc); 2230 2231 if (init && AR_SREV_9271(sc)) { 2232 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2233 AR9271_RADIO_RF_RST); 2234 DELAY(50); 2235 } 2236 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2237 /* Save TSF before it gets cleared. */ 2238 tsfhi = AR_READ(sc, AR_TSF_U32); 2239 tsflo = AR_READ(sc, AR_TSF_L32); 2240 2241 /* NB: RTC reset clears TSF. */ 2242 error = athn_reset_power_on(sc); 2243 } 2244 else { 2245 tsfhi = tsflo = 0; /* XXX: gcc */ 2246 error = athn_reset(sc, 0); 2247 } 2248 if (error != 0) { 2249 aprint_error_dev(sc->sc_dev, 2250 "could not reset chip (error=%d)\n", error); 2251 return error; 2252 } 2253 2254 /* XXX not if already awake */ 2255 if ((error = athn_set_power_awake(sc)) != 0) { 2256 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2257 return error; 2258 } 2259 2260 athn_init_pll(sc, curchan); 2261 ops->set_rf_mode(sc, curchan); 2262 2263 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2264 /* Check that the radio is not disabled by hardware switch. */ 2265 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2266 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2267 reg = !reg; 2268 if (!reg) { 2269 aprint_error_dev(sc->sc_dev, 2270 "radio is disabled by hardware switch\n"); 2271 return EPERM; 2272 } 2273 } 2274 if (init && AR_SREV_9271(sc)) { 2275 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2276 AR9271_GATE_MAC_CTL); 2277 DELAY(50); 2278 } 2279 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2280 /* Restore TSF if it got cleared. */ 2281 AR_WRITE(sc, AR_TSF_L32, tsflo); 2282 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2283 } 2284 2285 if (AR_SREV_9280_10_OR_LATER(sc)) 2286 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2287 2288 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2289 ar9287_1_3_enable_async_fifo(sc); 2290 2291 /* Write init values to hardware. */ 2292 ops->hw_init(sc, curchan, extchan); 2293 2294 /* 2295 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2296 * management frames using CCMP. 2297 */ 2298 if (AR_SREV_9280_20_OR_LATER(sc)) { 2299 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2300 /* Do not mask the subtype field in management frames. */ 2301 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2302 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2303 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2304 IEEE80211_FC1_MORE_DATA)); 2305 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2306 } 2307 else if (AR_SREV_9160_10_OR_LATER(sc)) { 2308 /* Disable hardware crypto for management frames. */ 2309 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2310 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2311 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2312 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2313 } 2314 2315 if (ic->ic_curmode != IEEE80211_MODE_11B) 2316 ops->set_delta_slope(sc, curchan, extchan); 2317 2318 ops->spur_mitigate(sc, curchan, extchan); 2319 ops->init_from_rom(sc, curchan, extchan); 2320 2321 /* XXX */ 2322 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2323 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2324 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2325 2326 athn_set_opmode(sc); 2327 2328 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2329 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2330 2331 /* Restore previous antenna. */ 2332 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2333 2334 AR_WRITE(sc, AR_BSS_ID0, 0); 2335 AR_WRITE(sc, AR_BSS_ID1, 0); 2336 2337 AR_WRITE(sc, AR_ISR, 0xffffffff); 2338 2339 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2340 2341 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2342 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2343 return error; 2344 } 2345 sc->sc_curchan = curchan; 2346 sc->sc_curchanext = extchan; 2347 2348 for (i = 0; i < AR_NUM_DCU; i++) 2349 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2350 2351 athn_init_tx_queues(sc); 2352 2353 /* Initialize interrupt mask. */ 2354 sc->sc_imask = 2355 AR_IMR_TXDESC | AR_IMR_TXEOL | 2356 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2357 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2358 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2359 if (AR_SREV_9380_10_OR_LATER(sc)) 2360 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2361 #ifndef IEEE80211_STA_ONLY 2362 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2363 sc->sc_imask |= AR_IMR_MIB; 2364 #endif 2365 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2366 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2367 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2368 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2369 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2370 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2371 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2372 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2373 if (AR_SREV_9380_10_OR_LATER(sc)) { 2374 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2375 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2376 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2377 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2378 } 2379 2380 athn_init_qos(sc); 2381 2382 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2383 2384 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2385 ar9287_1_3_setup_async_fifo(sc); 2386 2387 /* Disable sequence number generation in hardware. */ 2388 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2389 2390 athn_init_dma(sc); 2391 2392 /* Program observation bus to see MAC interrupts. */ 2393 AR_WRITE(sc, sc->sc_obs_off, 8); 2394 2395 /* Setup Rx interrupt mitigation. */ 2396 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2397 2398 ops->init_baseband(sc); 2399 2400 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2401 aprint_error_dev(sc->sc_dev, 2402 "could not initialize calibration\n"); 2403 return error; 2404 } 2405 2406 ops->set_rxchains(sc); 2407 2408 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2409 2410 if (sc->sc_flags & ATHN_FLAG_USB) { 2411 if (AR_SREV_9271(sc)) 2412 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2413 else 2414 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2415 } 2416 #if BYTE_ORDER == BIG_ENDIAN 2417 else { 2418 /* Default is LE, turn on swapping for BE. */ 2419 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2420 } 2421 #endif 2422 AR_WRITE_BARRIER(sc); 2423 2424 return 0; 2425 } 2426 2427 Static struct ieee80211_node * 2428 athn_node_alloc(struct ieee80211_node_table *ntp) 2429 { 2430 2431 return malloc(sizeof(struct athn_node), M_DEVBUF, 2432 M_NOWAIT | M_ZERO); 2433 } 2434 2435 Static void 2436 athn_newassoc(struct ieee80211_node *ni, int isnew) 2437 { 2438 struct ieee80211com *ic = ni->ni_ic; 2439 struct athn_softc *sc = ic->ic_ifp->if_softc; 2440 struct athn_node *an = (void *)ni; 2441 struct ieee80211_rateset *rs = &ni->ni_rates; 2442 uint8_t rate; 2443 int ridx, i, j; 2444 2445 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2446 /* Start at lowest available bit-rate, AMRR will raise. */ 2447 ni->ni_txrate = 0; 2448 2449 for (i = 0; i < rs->rs_nrates; i++) { 2450 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2451 2452 /* Map 802.11 rate to HW rate index. */ 2453 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2454 if (athn_rates[ridx].rate == rate) 2455 break; 2456 an->ridx[i] = ridx; 2457 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2458 2459 /* Compute fallback rate for retries. */ 2460 an->fallback[i] = i; 2461 for (j = i - 1; j >= 0; j--) { 2462 if (athn_rates[an->ridx[j]].phy == 2463 athn_rates[an->ridx[i]].phy) { 2464 an->fallback[i] = j; 2465 break; 2466 } 2467 } 2468 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2469 i, an->fallback[i]); 2470 } 2471 } 2472 2473 Static int 2474 athn_media_change(struct ifnet *ifp) 2475 { 2476 struct athn_softc *sc = ifp->if_softc; 2477 struct ieee80211com *ic = &sc->sc_ic; 2478 uint8_t rate, ridx; 2479 int error; 2480 2481 error = ieee80211_media_change(ifp); 2482 if (error != ENETRESET) 2483 return error; 2484 2485 if (ic->ic_fixed_rate != -1) { 2486 rate = ic->ic_sup_rates[ic->ic_curmode]. 2487 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2488 /* Map 802.11 rate to HW rate index. */ 2489 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2490 if (athn_rates[ridx].rate == rate) 2491 break; 2492 sc->sc_fixed_ridx = ridx; 2493 } 2494 if (IS_UP_AND_RUNNING(ifp)) { 2495 athn_stop(ifp, 0); 2496 error = athn_init(ifp); 2497 } 2498 return error; 2499 } 2500 2501 Static void 2502 athn_next_scan(void *arg) 2503 { 2504 struct athn_softc *sc = arg; 2505 struct ieee80211com *ic = &sc->sc_ic; 2506 int s; 2507 2508 s = splnet(); 2509 if (ic->ic_state == IEEE80211_S_SCAN) 2510 ieee80211_next_scan(ic); 2511 splx(s); 2512 } 2513 2514 Static int 2515 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2516 { 2517 struct ifnet *ifp = ic->ic_ifp; 2518 struct athn_softc *sc = ifp->if_softc; 2519 uint32_t reg; 2520 int error; 2521 2522 callout_stop(&sc->sc_calib_to); 2523 2524 switch (nstate) { 2525 case IEEE80211_S_INIT: 2526 athn_set_led(sc, 0); 2527 break; 2528 case IEEE80211_S_SCAN: 2529 /* Make the LED blink while scanning. */ 2530 athn_set_led(sc, !sc->sc_led_state); 2531 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2532 if (error != 0) 2533 return error; 2534 callout_schedule(&sc->sc_scan_to, hz / 5); 2535 break; 2536 case IEEE80211_S_AUTH: 2537 athn_set_led(sc, 0); 2538 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2539 if (error != 0) 2540 return error; 2541 break; 2542 case IEEE80211_S_ASSOC: 2543 break; 2544 case IEEE80211_S_RUN: 2545 athn_set_led(sc, 1); 2546 2547 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2548 break; 2549 2550 /* Fake a join to initialize the Tx rate. */ 2551 athn_newassoc(ic->ic_bss, 1); 2552 2553 athn_set_bss(sc, ic->ic_bss); 2554 athn_disable_interrupts(sc); 2555 #ifndef IEEE80211_STA_ONLY 2556 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2557 athn_set_hostap_timers(sc); 2558 /* Enable software beacon alert interrupts. */ 2559 sc->sc_imask |= AR_IMR_SWBA; 2560 } 2561 else 2562 #endif 2563 { 2564 athn_set_sta_timers(sc); 2565 /* Enable beacon miss interrupts. */ 2566 sc->sc_imask |= AR_IMR_BMISS; 2567 2568 /* Stop receiving beacons from other BSS. */ 2569 reg = AR_READ(sc, AR_RX_FILTER); 2570 reg = (reg & ~AR_RX_FILTER_BEACON) | 2571 AR_RX_FILTER_MYBEACON; 2572 AR_WRITE(sc, AR_RX_FILTER, reg); 2573 AR_WRITE_BARRIER(sc); 2574 } 2575 athn_enable_interrupts(sc); 2576 2577 if (sc->sc_sup_calib_mask != 0) { 2578 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2579 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2580 /* ops->do_calib(sc); */ 2581 } 2582 /* XXX Start ANI. */ 2583 2584 callout_schedule(&sc->sc_calib_to, hz / 2); 2585 break; 2586 } 2587 2588 return sc->sc_newstate(ic, nstate, arg); 2589 } 2590 2591 #ifdef notyet_edca 2592 PUBLIC void 2593 athn_updateedca(struct ieee80211com *ic) 2594 { 2595 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2596 struct athn_softc *sc = ic->ic_ifp->if_softc; 2597 const struct ieee80211_edca_ac_params *ac; 2598 int aci, qid; 2599 2600 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2601 ac = &ic->ic_edca_ac[aci]; 2602 qid = athn_ac2qid[aci]; 2603 2604 AR_WRITE(sc, AR_DLCL_IFS(qid), 2605 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2606 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2607 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2608 if (ac->ac_txoplimit != 0) { 2609 AR_WRITE(sc, AR_DCHNTIME(qid), 2610 SM(AR_D_CHNTIME_DUR, 2611 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2612 AR_D_CHNTIME_EN); 2613 } 2614 else 2615 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2616 } 2617 AR_WRITE_BARRIER(sc); 2618 #undef ATHN_EXP2 2619 } 2620 #endif /* notyet_edca */ 2621 2622 Static int 2623 athn_clock_rate(struct athn_softc *sc) 2624 { 2625 struct ieee80211com *ic = &sc->sc_ic; 2626 int clockrate; /* MHz. */ 2627 2628 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2629 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2630 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2631 else 2632 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2633 } 2634 else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2635 clockrate = AR_CLOCK_RATE_CCK; 2636 } 2637 else 2638 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2639 #ifndef IEEE80211_NO_HT 2640 if (sc->sc_curchanext != NULL) 2641 clockrate *= 2; 2642 #endif 2643 return clockrate; 2644 } 2645 2646 PUBLIC void 2647 athn_updateslot(struct ifnet *ifp) 2648 { 2649 struct athn_softc *sc = ifp->if_softc; 2650 struct ieee80211com *ic = &sc->sc_ic; 2651 int slot; 2652 2653 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2654 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2655 AR_WRITE_BARRIER(sc); 2656 } 2657 2658 Static void 2659 athn_start(struct ifnet *ifp) 2660 { 2661 struct athn_softc *sc = ifp->if_softc; 2662 struct ieee80211com *ic = &sc->sc_ic; 2663 struct ether_header *eh; 2664 struct ieee80211_node *ni; 2665 struct mbuf *m; 2666 2667 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2668 || !device_is_active(sc->sc_dev)) 2669 return; 2670 2671 for (;;) { 2672 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2673 ifp->if_flags |= IFF_OACTIVE; 2674 break; 2675 } 2676 /* Send pending management frames first. */ 2677 IF_DEQUEUE(&ic->ic_mgtq, m); 2678 if (m != NULL) { 2679 ni = M_GETCTX(m, struct ieee80211_node *); 2680 goto sendit; 2681 } 2682 if (ic->ic_state != IEEE80211_S_RUN) 2683 break; 2684 2685 /* Encapsulate and send data frames. */ 2686 IFQ_DEQUEUE(&ifp->if_snd, m); 2687 if (m == NULL) 2688 break; 2689 2690 if (m->m_len < (int)sizeof(*eh) && 2691 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2692 ifp->if_oerrors++; 2693 continue; 2694 } 2695 eh = mtod(m, struct ether_header *); 2696 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2697 if (ni == NULL) { 2698 m_freem(m); 2699 ifp->if_oerrors++; 2700 continue; 2701 } 2702 2703 bpf_mtap(ifp, m); 2704 2705 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2706 continue; 2707 sendit: 2708 bpf_mtap3(ic->ic_rawbpf, m); 2709 2710 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2711 ieee80211_free_node(ni); 2712 ifp->if_oerrors++; 2713 continue; 2714 } 2715 2716 sc->sc_tx_timer = 5; 2717 ifp->if_timer = 1; 2718 } 2719 } 2720 2721 Static void 2722 athn_watchdog(struct ifnet *ifp) 2723 { 2724 struct athn_softc *sc = ifp->if_softc; 2725 2726 ifp->if_timer = 0; 2727 2728 if (sc->sc_tx_timer > 0) { 2729 if (--sc->sc_tx_timer == 0) { 2730 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2731 /* see athn_init, no need to call athn_stop here */ 2732 /* athn_stop(ifp, 0); */ 2733 (void)athn_init(ifp); 2734 ifp->if_oerrors++; 2735 return; 2736 } 2737 ifp->if_timer = 1; 2738 } 2739 ieee80211_watchdog(&sc->sc_ic); 2740 } 2741 2742 #ifdef notyet 2743 Static void 2744 athn_set_multi(struct athn_softc *sc) 2745 { 2746 struct arpcom *ac = &sc->sc_ic.ic_ac; 2747 struct ifnet *ifp = &ac->ac_if; 2748 struct ether_multi *enm; 2749 struct ether_multistep step; 2750 const uint8_t *addr; 2751 uint32_t val, lo, hi; 2752 uint8_t bit; 2753 2754 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2755 lo = hi = 0xffffffff; 2756 goto done; 2757 } 2758 lo = hi = 0; 2759 ETHER_FIRST_MULTI(step, ac, enm); 2760 while (enm != NULL) { 2761 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2762 ifp->if_flags |= IFF_ALLMULTI; 2763 lo = hi = 0xffffffff; 2764 goto done; 2765 } 2766 addr = enm->enm_addrlo; 2767 /* Calculate the XOR value of all eight 6-bit words. */ 2768 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2769 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2770 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2771 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2772 bit &= 0x3f; 2773 if (bit < 32) 2774 lo |= 1 << bit; 2775 else 2776 hi |= 1 << (bit - 32); 2777 ETHER_NEXT_MULTI(step, enm); 2778 } 2779 done: 2780 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2781 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2782 AR_WRITE_BARRIER(sc); 2783 } 2784 #endif /* notyet */ 2785 2786 Static int 2787 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2788 { 2789 struct athn_softc *sc = ifp->if_softc; 2790 struct ieee80211com *ic = &sc->sc_ic; 2791 int s, error = 0; 2792 2793 s = splnet(); 2794 2795 switch (cmd) { 2796 case SIOCSIFFLAGS: 2797 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2798 break; 2799 2800 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2801 case IFF_UP | IFF_RUNNING: 2802 #ifdef notyet 2803 if (((ifp->if_flags ^ sc->sc_if_flags) & 2804 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2805 /* XXX: setup multi */ 2806 #endif 2807 break; 2808 case IFF_UP: 2809 athn_init(ifp); 2810 break; 2811 2812 case IFF_RUNNING: 2813 athn_stop(ifp, 1); 2814 break; 2815 case 0: 2816 default: 2817 break; 2818 } 2819 sc->sc_if_flags = ifp->if_flags; 2820 break; 2821 2822 case SIOCADDMULTI: 2823 case SIOCDELMULTI: 2824 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2825 /* setup multicast filter, etc */ 2826 #ifdef notyet 2827 athn_set_multi(sc); 2828 #endif 2829 error = 0; 2830 } 2831 break; 2832 2833 case SIOCS80211CHANNEL: 2834 error = ieee80211_ioctl(ic, cmd, data); 2835 if (error == ENETRESET && 2836 ic->ic_opmode == IEEE80211_M_MONITOR) { 2837 if (IS_UP_AND_RUNNING(ifp)) 2838 athn_switch_chan(sc, ic->ic_curchan, NULL); 2839 error = 0; 2840 } 2841 break; 2842 2843 default: 2844 error = ieee80211_ioctl(ic, cmd, data); 2845 } 2846 2847 if (error == ENETRESET) { 2848 error = 0; 2849 if (IS_UP_AND_RUNNING(ifp) && 2850 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2851 athn_stop(ifp, 0); 2852 error = athn_init(ifp); 2853 } 2854 } 2855 2856 splx(s); 2857 return error; 2858 } 2859 2860 Static int 2861 athn_init(struct ifnet *ifp) 2862 { 2863 struct athn_softc *sc = ifp->if_softc; 2864 struct athn_ops *ops = &sc->sc_ops; 2865 struct ieee80211com *ic = &sc->sc_ic; 2866 struct ieee80211_channel *curchan, *extchan; 2867 size_t i; 2868 int error; 2869 2870 KASSERT(!cpu_intr_p()); 2871 2872 if (device_is_active(sc->sc_dev)) { 2873 athn_stop(ifp, 0); /* see athn_watchdog() */ 2874 } else { 2875 short flags = ifp->if_flags; 2876 ifp->if_flags &= ~IFF_UP; 2877 /* avoid recursion in athn_resume */ 2878 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2879 !device_is_active(sc->sc_dev)) { 2880 printf("%s: failed to power up device\n", 2881 device_xname(sc->sc_dev)); 2882 return 0; 2883 } 2884 ifp->if_flags = flags; 2885 } 2886 2887 curchan = ic->ic_curchan; 2888 extchan = NULL; 2889 2890 /* In case a new MAC address has been configured. */ 2891 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2892 2893 #ifdef openbsd_power_management 2894 /* For CardBus, power on the socket. */ 2895 if (sc->sc_enable != NULL) { 2896 if ((error = sc->sc_enable(sc)) != 0) { 2897 aprint_error_dev(sc->sc_dev, 2898 "could not enable device\n"); 2899 goto fail; 2900 } 2901 if ((error = athn_reset_power_on(sc)) != 0) { 2902 aprint_error_dev(sc->sc_dev, 2903 "could not power on device\n"); 2904 goto fail; 2905 } 2906 } 2907 #endif 2908 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2909 athn_config_nonpcie(sc); 2910 else 2911 athn_config_pcie(sc); 2912 2913 /* Reset HW key cache entries. */ 2914 for (i = 0; i < sc->sc_kc_entries; i++) 2915 athn_reset_key(sc, i); 2916 2917 ops->enable_antenna_diversity(sc); 2918 2919 #ifdef ATHN_BT_COEXISTENCE 2920 /* Configure bluetooth coexistence for combo chips. */ 2921 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2922 athn_btcoex_init(sc); 2923 #endif 2924 2925 /* Configure LED. */ 2926 athn_led_init(sc); 2927 2928 /* Configure hardware radio switch. */ 2929 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2930 ops->rfsilent_init(sc); 2931 2932 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2933 aprint_error_dev(sc->sc_dev, 2934 "unable to reset hardware; reset status %d\n", error); 2935 goto fail; 2936 } 2937 2938 /* Enable Rx. */ 2939 athn_rx_start(sc); 2940 2941 /* Enable interrupts. */ 2942 athn_enable_interrupts(sc); 2943 2944 #ifdef ATHN_BT_COEXISTENCE 2945 /* Enable bluetooth coexistence for combo chips. */ 2946 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2947 athn_btcoex_enable(sc); 2948 #endif 2949 2950 ifp->if_flags &= ~IFF_OACTIVE; 2951 ifp->if_flags |= IFF_RUNNING; 2952 2953 #ifdef notyet 2954 if (ic->ic_flags & IEEE80211_F_WEPON) { 2955 /* Configure WEP keys. */ 2956 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2957 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2958 } 2959 #endif 2960 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2961 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2962 else 2963 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2964 2965 return 0; 2966 fail: 2967 athn_stop(ifp, 1); 2968 return error; 2969 } 2970 2971 PUBLIC void 2972 athn_stop(struct ifnet *ifp, int disable) 2973 { 2974 struct athn_softc *sc = ifp->if_softc; 2975 struct ieee80211com *ic = &sc->sc_ic; 2976 int qid; 2977 2978 ifp->if_timer = sc->sc_tx_timer = 0; 2979 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2980 2981 callout_stop(&sc->sc_scan_to); 2982 /* In case we were scanning, release the scan "lock". */ 2983 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2984 2985 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2986 2987 #ifdef ATHN_BT_COEXISTENCE 2988 /* Disable bluetooth coexistence for combo chips. */ 2989 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2990 athn_btcoex_disable(sc); 2991 #endif 2992 2993 /* Disable interrupts. */ 2994 athn_disable_interrupts(sc); 2995 /* Acknowledge interrupts (avoids interrupt storms). */ 2996 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2997 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2998 2999 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3000 athn_stop_tx_dma(sc, qid); 3001 /* XXX call athn_hw_reset if Tx still pending? */ 3002 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3003 athn_tx_reclaim(sc, qid); 3004 3005 /* Stop Rx. */ 3006 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3007 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 3008 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 3009 AR_WRITE(sc, AR_FILT_OFDM, 0); 3010 AR_WRITE(sc, AR_FILT_CCK, 0); 3011 AR_WRITE_BARRIER(sc); 3012 athn_set_rxfilter(sc, 0); 3013 athn_stop_rx_dma(sc); 3014 3015 athn_reset(sc, 0); 3016 athn_init_pll(sc, NULL); 3017 athn_set_power_awake(sc); 3018 athn_reset(sc, 1); 3019 athn_init_pll(sc, NULL); 3020 3021 athn_set_power_sleep(sc); 3022 3023 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3024 /* For CardBus, power down the socket. */ 3025 if (disable && sc->sc_disable != NULL) 3026 sc->sc_disable(sc); 3027 #endif 3028 if (disable) 3029 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3030 } 3031 3032 Static void 3033 athn_pmf_wlan_off(device_t self) 3034 { 3035 struct athn_softc *sc = device_private(self); 3036 struct ifnet *ifp = &sc->sc_if; 3037 3038 /* Turn the interface down. */ 3039 ifp->if_flags &= ~IFF_UP; 3040 athn_stop(ifp, 1); 3041 } 3042 3043 PUBLIC void 3044 athn_suspend(struct athn_softc *sc) 3045 { 3046 struct ifnet *ifp = &sc->sc_if; 3047 3048 if (ifp->if_flags & IFF_RUNNING) 3049 athn_stop(ifp, 1); 3050 } 3051 3052 PUBLIC bool 3053 athn_resume(struct athn_softc *sc) 3054 { 3055 struct ifnet *ifp = &sc->sc_if; 3056 3057 if (ifp->if_flags & IFF_UP) 3058 athn_init(ifp); 3059 3060 return true; 3061 } 3062
Indexes created Tue Oct 14 08:09:56 GMT 2025