athn.c revision 1.18.2.2
1 /* $NetBSD: athn.c,v 1.18.2.2 2019/06/10 22:07:10 christos Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.18.2.2 2019/06/10 22:07:10 christos Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 #endif /* notyet */ 140 Static void athn_set_multi(struct athn_softc *); 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } else { 253 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 254 athn_get_rf_name(sc)); 255 aprint_verbose_dev(sc->sc_dev, 256 "rev %d (%dT%dR), ROM rev %d, address %s\n", 257 sc->sc_mac_rev, 258 sc->sc_ntxchains, sc->sc_nrxchains, 259 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 260 } 261 262 callout_init(&sc->sc_scan_to, 0); 263 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 264 callout_init(&sc->sc_calib_to, 0); 265 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 266 267 sc->sc_amrr.amrr_min_success_threshold = 1; 268 sc->sc_amrr.amrr_max_success_threshold = 15; 269 270 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 271 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* Set device capabilities. */ 275 ic->ic_caps = 276 IEEE80211_C_WPA | /* 802.11i */ 277 #ifndef IEEE80211_STA_ONLY 278 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 279 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 280 #endif 281 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 282 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 283 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 284 IEEE80211_C_PMGT; /* Power saving supported. */ 285 286 #ifndef IEEE80211_NO_HT 287 if (sc->sc_flags & ATHN_FLAG_11N) { 288 int i, ntxstreams, nrxstreams; 289 290 /* Set HT capabilities. */ 291 ic->ic_htcaps = 292 IEEE80211_HTCAP_SMPS_DIS | 293 IEEE80211_HTCAP_CBW20_40 | 294 IEEE80211_HTCAP_SGI40 | 295 IEEE80211_HTCAP_DSSSCCK40; 296 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 297 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 298 if (AR_SREV_9380_10_OR_LATER(sc)) 299 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 300 if (AR_SREV_9280_10_OR_LATER(sc)) { 301 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 302 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 303 } 304 ntxstreams = sc->sc_ntxchains; 305 nrxstreams = sc->sc_nrxchains; 306 if (!AR_SREV_9380_10_OR_LATER(sc)) { 307 ntxstreams = MIN(ntxstreams, 2); 308 nrxstreams = MIN(nrxstreams, 2); 309 } 310 /* Set supported HT rates. */ 311 for (i = 0; i < nrxstreams; i++) 312 ic->ic_sup_mcs[i] = 0xff; 313 /* Set the "Tx MCS Set Defined" bit. */ 314 ic->ic_sup_mcs[12] |= 0x01; 315 if (ntxstreams != nrxstreams) { 316 /* Set "Tx Rx MCS Set Not Equal" bit. */ 317 ic->ic_sup_mcs[12] |= 0x02; 318 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 319 } 320 } 321 #endif 322 323 /* Set supported rates. */ 324 if (sc->sc_flags & ATHN_FLAG_11G) { 325 ic->ic_sup_rates[IEEE80211_MODE_11B] = 326 ieee80211_std_rateset_11b; 327 ic->ic_sup_rates[IEEE80211_MODE_11G] = 328 ieee80211_std_rateset_11g; 329 } 330 if (sc->sc_flags & ATHN_FLAG_11A) { 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 } 334 335 /* Get the list of authorized/supported channels. */ 336 athn_get_chanlist(sc); 337 338 ifp->if_softc = sc; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 if (!ifp->if_init) 341 ifp->if_init = athn_init; 342 if (!ifp->if_ioctl) 343 ifp->if_ioctl = athn_ioctl; 344 if (!ifp->if_start) 345 ifp->if_start = athn_start; 346 if (!ifp->if_watchdog) 347 ifp->if_watchdog = athn_watchdog; 348 IFQ_SET_READY(&ifp->if_snd); 349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 350 351 error = if_initialize(ifp); 352 if (error != 0) { 353 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 354 error); 355 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, 356 athn_pmf_wlan_off, false); 357 callout_destroy(&sc->sc_scan_to); 358 callout_destroy(&sc->sc_calib_to); 359 return error; 360 } 361 ieee80211_ifattach(ic); 362 /* Use common softint-based if_input */ 363 ifp->if_percpuq = if_percpuq_create(ifp); 364 if_register(ifp); 365 366 ic->ic_node_alloc = athn_node_alloc; 367 ic->ic_newassoc = athn_newassoc; 368 if (ic->ic_updateslot == NULL) 369 ic->ic_updateslot = athn_updateslot; 370 #ifdef notyet_edca 371 ic->ic_updateedca = athn_updateedca; 372 #endif 373 #ifdef notyet 374 ic->ic_set_key = athn_set_key; 375 ic->ic_delete_key = athn_delete_key; 376 #endif 377 378 /* Override 802.11 state transition machine. */ 379 sc->sc_newstate = ic->ic_newstate; 380 ic->ic_newstate = athn_newstate; 381 382 /* XXX we should create at least one vap here??? */ 383 384 if (sc->sc_media_change == NULL) 385 sc->sc_media_change = athn_media_change; 386 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 387 388 athn_radiotap_attach(sc); 389 return 0; 390 } 391 392 PUBLIC void 393 athn_detach(struct athn_softc *sc) 394 { 395 struct ifnet *ifp = &sc->sc_if; 396 int qid; 397 398 callout_halt(&sc->sc_scan_to, NULL); 399 callout_halt(&sc->sc_calib_to, NULL); 400 401 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 402 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 403 athn_tx_reclaim(sc, qid); 404 405 /* Free Tx/Rx DMA resources. */ 406 sc->sc_ops.dma_free(sc); 407 408 if (sc->sc_soft_ih != NULL) { 409 softint_disestablish(sc->sc_soft_ih); 410 sc->sc_soft_ih = NULL; 411 } 412 } 413 /* Free ROM copy. */ 414 if (sc->sc_eep != NULL) { 415 free(sc->sc_eep, M_DEVBUF); 416 sc->sc_eep = NULL; 417 } 418 419 bpf_detach(ifp); 420 ieee80211_ifdetach(&sc->sc_ic); 421 if_detach(ifp); 422 423 callout_destroy(&sc->sc_scan_to); 424 callout_destroy(&sc->sc_calib_to); 425 426 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 427 false); 428 } 429 430 /* 431 * Attach the interface to 802.11 radiotap. 432 */ 433 Static void 434 athn_radiotap_attach(struct athn_softc *sc) 435 { 436 437 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 438 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 439 &sc->sc_drvbpf); 440 441 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 442 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 443 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 444 445 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 446 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 447 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 448 } 449 450 Static void 451 athn_get_chanlist(struct athn_softc *sc) 452 { 453 struct ieee80211com *ic = &sc->sc_ic; 454 uint8_t chan; 455 size_t i; 456 457 if (sc->sc_flags & ATHN_FLAG_11G) { 458 for (i = 1; i <= 14; i++) { 459 chan = i; 460 ic->ic_channels[chan].ic_freq = 461 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 462 ic->ic_channels[chan].ic_flags = 463 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 464 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 465 } 466 } 467 if (sc->sc_flags & ATHN_FLAG_11A) { 468 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 469 chan = athn_5ghz_chans[i]; 470 ic->ic_channels[chan].ic_freq = 471 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 472 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 473 } 474 } 475 } 476 477 PUBLIC void 478 athn_rx_start(struct athn_softc *sc) 479 { 480 struct ieee80211com *ic = &sc->sc_ic; 481 uint32_t rfilt; 482 483 /* Setup Rx DMA descriptors. */ 484 sc->sc_ops.rx_enable(sc); 485 486 /* Set Rx filter. */ 487 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 488 #ifndef IEEE80211_NO_HT 489 /* Want Compressed Block Ack Requests. */ 490 rfilt |= AR_RX_FILTER_COMPR_BAR; 491 #endif 492 rfilt |= AR_RX_FILTER_BEACON; 493 if (ic->ic_opmode != IEEE80211_M_STA) { 494 rfilt |= AR_RX_FILTER_PROBEREQ; 495 if (ic->ic_opmode == IEEE80211_M_MONITOR) 496 rfilt |= AR_RX_FILTER_PROM; 497 #ifndef IEEE80211_STA_ONLY 498 if (AR_SREV_9280_10_OR_LATER(sc) && 499 ic->ic_opmode == IEEE80211_M_HOSTAP) 500 rfilt |= AR_RX_FILTER_PSPOLL; 501 #endif 502 } 503 athn_set_rxfilter(sc, rfilt); 504 505 /* Set BSSID mask. */ 506 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 507 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 508 509 athn_set_opmode(sc); 510 511 /* Set multicast filter. */ 512 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 513 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 514 515 AR_WRITE(sc, AR_FILT_OFDM, 0); 516 AR_WRITE(sc, AR_FILT_CCK, 0); 517 AR_WRITE(sc, AR_MIBC, 0); 518 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 519 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 520 521 /* XXX ANI. */ 522 AR_WRITE(sc, AR_PHY_ERR_1, 0); 523 AR_WRITE(sc, AR_PHY_ERR_2, 0); 524 525 /* Disable HW crypto for now. */ 526 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 527 528 /* Start PCU Rx. */ 529 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 530 AR_WRITE_BARRIER(sc); 531 } 532 533 PUBLIC void 534 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 535 { 536 537 AR_WRITE(sc, AR_RX_FILTER, rfilt); 538 #ifdef notyet 539 reg = AR_READ(sc, AR_PHY_ERR); 540 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 541 AR_PHY_ERR_CCK_TIMING); 542 AR_WRITE(sc, AR_PHY_ERR, reg); 543 if (reg != 0) 544 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 545 else 546 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 547 #else 548 AR_WRITE(sc, AR_PHY_ERR, 0); 549 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 550 #endif 551 AR_WRITE_BARRIER(sc); 552 } 553 554 PUBLIC int 555 athn_intr(void *xsc) 556 { 557 struct athn_softc *sc = xsc; 558 struct ifnet *ifp = &sc->sc_if; 559 560 if (!IS_UP_AND_RUNNING(ifp)) 561 return 0; 562 563 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 564 /* 565 * The hardware is not ready/present, don't touch anything. 566 * Note this can happen early on if the IRQ is shared. 567 */ 568 return 0; 569 570 if (!sc->sc_ops.intr_status(sc)) 571 return 0; 572 573 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 574 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 575 AR_WRITE_BARRIER(sc); 576 577 softint_schedule(sc->sc_soft_ih); 578 579 return 1; 580 } 581 582 Static void 583 athn_softintr(void *xsc) 584 { 585 struct athn_softc *sc = xsc; 586 struct ifnet *ifp = &sc->sc_if; 587 588 if (!IS_UP_AND_RUNNING(ifp)) 589 return; 590 591 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 592 /* 593 * The hardware is not ready/present, don't touch anything. 594 * Note this can happen early on if the IRQ is shared. 595 */ 596 return; 597 598 sc->sc_ops.intr(sc); 599 600 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 601 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 602 AR_WRITE_BARRIER(sc); 603 } 604 605 Static void 606 athn_get_chipid(struct athn_softc *sc) 607 { 608 uint32_t reg; 609 610 reg = AR_READ(sc, AR_SREV); 611 if (MS(reg, AR_SREV_ID) == 0xff) { 612 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 613 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 614 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 615 sc->sc_flags |= ATHN_FLAG_PCIE; 616 } else { 617 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 618 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 619 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 620 sc->sc_flags |= ATHN_FLAG_PCIE; 621 } 622 } 623 624 Static const char * 625 athn_get_mac_name(struct athn_softc *sc) 626 { 627 628 switch (sc->sc_mac_ver) { 629 case AR_SREV_VERSION_5416_PCI: 630 return "AR5416"; 631 case AR_SREV_VERSION_5416_PCIE: 632 return "AR5418"; 633 case AR_SREV_VERSION_9160: 634 return "AR9160"; 635 case AR_SREV_VERSION_9280: 636 return "AR9280"; 637 case AR_SREV_VERSION_9285: 638 return "AR9285"; 639 case AR_SREV_VERSION_9271: 640 return "AR9271"; 641 case AR_SREV_VERSION_9287: 642 return "AR9287"; 643 case AR_SREV_VERSION_9380: 644 return "AR9380"; 645 case AR_SREV_VERSION_9485: 646 return "AR9485"; 647 default: 648 return "unknown"; 649 } 650 } 651 652 /* 653 * Return RF chip name (not for single-chip solutions). 654 */ 655 Static const char * 656 athn_get_rf_name(struct athn_softc *sc) 657 { 658 659 KASSERT(!AR_SINGLE_CHIP(sc)); 660 661 switch (sc->sc_rf_rev) { 662 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 663 return "AR5133"; 664 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 665 return "AR2133"; 666 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 667 return "AR5122"; 668 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 669 return "AR2122"; 670 default: 671 return "unknown"; 672 } 673 } 674 675 PUBLIC int 676 athn_reset_power_on(struct athn_softc *sc) 677 { 678 int ntries; 679 680 /* Set force wake. */ 681 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 682 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 683 684 if (!AR_SREV_9380_10_OR_LATER(sc)) { 685 /* Make sure no DMA is active by doing an AHB reset. */ 686 AR_WRITE(sc, AR_RC, AR_RC_AHB); 687 } 688 /* RTC reset and clear. */ 689 AR_WRITE(sc, AR_RTC_RESET, 0); 690 AR_WRITE_BARRIER(sc); 691 DELAY(2); 692 if (!AR_SREV_9380_10_OR_LATER(sc)) 693 AR_WRITE(sc, AR_RC, 0); 694 AR_WRITE(sc, AR_RTC_RESET, 1); 695 696 /* Poll until RTC is ON. */ 697 for (ntries = 0; ntries < 1000; ntries++) { 698 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 699 AR_RTC_STATUS_ON) 700 break; 701 DELAY(10); 702 } 703 if (ntries == 1000) { 704 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 705 return ETIMEDOUT; 706 } 707 return athn_reset(sc, 0); 708 } 709 710 PUBLIC int 711 athn_reset(struct athn_softc *sc, int cold_reset) 712 { 713 int ntries; 714 715 /* Set force wake. */ 716 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 717 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 718 719 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 720 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 721 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 722 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 723 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 724 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 725 AR_WRITE(sc, AR_RC, AR_RC_AHB); 726 727 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 728 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 729 AR_WRITE_BARRIER(sc); 730 DELAY(50); 731 AR_WRITE(sc, AR_RTC_RC, 0); 732 for (ntries = 0; ntries < 1000; ntries++) { 733 if (!(AR_READ(sc, AR_RTC_RC) & 734 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 735 break; 736 DELAY(10); 737 } 738 if (ntries == 1000) { 739 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 740 return ETIMEDOUT; 741 } 742 AR_WRITE(sc, AR_RC, 0); 743 AR_WRITE_BARRIER(sc); 744 return 0; 745 } 746 747 PUBLIC int 748 athn_set_power_awake(struct athn_softc *sc) 749 { 750 int ntries, error; 751 752 /* Do a Power-On-Reset if shutdown. */ 753 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 754 AR_RTC_STATUS_SHUTDOWN) { 755 if ((error = athn_reset_power_on(sc)) != 0) 756 return error; 757 if (!AR_SREV_9380_10_OR_LATER(sc)) 758 athn_init_pll(sc, NULL); 759 } 760 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 761 AR_WRITE_BARRIER(sc); 762 DELAY(50); /* Give chip the chance to awake. */ 763 764 /* Poll until RTC is ON. */ 765 for (ntries = 0; ntries < 4000; ntries++) { 766 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 767 AR_RTC_STATUS_ON) 768 break; 769 DELAY(50); 770 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 771 } 772 if (ntries == 4000) { 773 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 774 return ETIMEDOUT; 775 } 776 777 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 778 AR_WRITE_BARRIER(sc); 779 return 0; 780 } 781 782 PUBLIC void 783 athn_set_power_sleep(struct athn_softc *sc) 784 { 785 786 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 787 /* Allow the MAC to go to sleep. */ 788 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 789 if (!AR_SREV_9380_10_OR_LATER(sc)) 790 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 791 /* 792 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 793 * results in high power consumption on AR5416 chipsets. 794 */ 795 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 796 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 797 AR_WRITE_BARRIER(sc); 798 } 799 800 PUBLIC void 801 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 802 { 803 uint32_t pll; 804 805 if (AR_SREV_9380_10_OR_LATER(sc)) { 806 if (AR_SREV_9485(sc)) 807 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 808 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 809 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 810 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 811 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 812 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 813 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 814 pll = 0x142c; 815 else if (AR_SREV_9280_20(sc)) 816 pll = 0x2850; 817 else 818 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 819 } else 820 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 821 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 822 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 823 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 824 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 825 else 826 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 827 } else { 828 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 829 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 830 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 831 else 832 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 833 } 834 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 835 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 836 if (AR_SREV_9271(sc)) { 837 /* Switch core clock to 117MHz. */ 838 AR_WRITE_BARRIER(sc); 839 DELAY(500); 840 AR_WRITE(sc, 0x50050, 0x304); 841 } 842 AR_WRITE_BARRIER(sc); 843 DELAY(100); 844 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 845 AR_WRITE_BARRIER(sc); 846 } 847 848 Static void 849 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 850 { 851 int i; 852 853 /* Write sequence to Serializer/Deserializer. */ 854 for (i = 0; i < serdes->nvals; i++) 855 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 856 AR_WRITE_BARRIER(sc); 857 } 858 859 PUBLIC void 860 athn_config_pcie(struct athn_softc *sc) 861 { 862 863 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 864 athn_write_serdes(sc, sc->sc_serdes); 865 866 DELAY(1000); 867 /* Allow forcing of PCIe core into L1 state. */ 868 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 869 870 #ifndef ATHN_PCIE_WAEN 871 AR_WRITE(sc, AR_WA, sc->sc_workaround); 872 #else 873 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 874 #endif 875 AR_WRITE_BARRIER(sc); 876 } 877 878 /* 879 * Serializer/Deserializer programming for non-PCIe devices. 880 */ 881 static const uint32_t ar_nonpcie_serdes_regs[] = { 882 AR_PCIE_SERDES, 883 AR_PCIE_SERDES, 884 AR_PCIE_SERDES, 885 AR_PCIE_SERDES, 886 AR_PCIE_SERDES, 887 AR_PCIE_SERDES, 888 AR_PCIE_SERDES, 889 AR_PCIE_SERDES, 890 AR_PCIE_SERDES, 891 AR_PCIE_SERDES2, 892 }; 893 894 static const uint32_t ar_nonpcie_serdes_vals[] = { 895 0x9248fc00, 896 0x24924924, 897 0x28000029, 898 0x57160824, 899 0x25980579, 900 0x00000000, 901 0x1aaabe40, 902 0xbe105554, 903 0x000e1007, 904 0x00000000 905 }; 906 907 static const struct athn_serdes ar_nonpcie_serdes = { 908 __arraycount(ar_nonpcie_serdes_vals), 909 ar_nonpcie_serdes_regs, 910 ar_nonpcie_serdes_vals 911 }; 912 913 PUBLIC void 914 athn_config_nonpcie(struct athn_softc *sc) 915 { 916 917 athn_write_serdes(sc, &ar_nonpcie_serdes); 918 } 919 920 PUBLIC int 921 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 922 struct ieee80211_channel *extchan) 923 { 924 struct athn_ops *ops = &sc->sc_ops; 925 int error, qid; 926 927 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 928 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 929 if (athn_tx_pending(sc, qid)) 930 return EBUSY; 931 932 /* Request RF Bus grant. */ 933 if ((error = ops->rf_bus_request(sc)) != 0) 934 return error; 935 936 ops->set_phy(sc, curchan, extchan); 937 938 /* Change the synthesizer. */ 939 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 940 return error; 941 942 sc->sc_curchan = curchan; 943 sc->sc_curchanext = extchan; 944 945 /* Set transmit power values for new channel. */ 946 ops->set_txpower(sc, curchan, extchan); 947 948 /* Release the RF Bus grant. */ 949 ops->rf_bus_release(sc); 950 951 /* Write delta slope coeffs for modes where OFDM may be used. */ 952 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 953 ops->set_delta_slope(sc, curchan, extchan); 954 955 ops->spur_mitigate(sc, curchan, extchan); 956 /* XXX Load noisefloor values and start calibration. */ 957 958 return 0; 959 } 960 961 Static int 962 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 963 struct ieee80211_channel *extchan) 964 { 965 int error, qid; 966 967 /* Disable interrupts. */ 968 athn_disable_interrupts(sc); 969 970 /* Stop all Tx queues. */ 971 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 972 athn_stop_tx_dma(sc, qid); 973 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 974 athn_tx_reclaim(sc, qid); 975 976 /* Stop Rx. */ 977 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 978 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 979 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 980 AR_WRITE(sc, AR_FILT_OFDM, 0); 981 AR_WRITE(sc, AR_FILT_CCK, 0); 982 athn_set_rxfilter(sc, 0); 983 error = athn_stop_rx_dma(sc); 984 if (error != 0) 985 goto reset; 986 987 #ifdef notyet 988 /* AR9280 needs a full reset. */ 989 if (AR_SREV_9280(sc)) 990 #endif 991 goto reset; 992 993 /* If band or bandwidth changes, we need to do a full reset. */ 994 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 995 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 996 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 997 goto reset; 998 } 999 error = athn_set_power_awake(sc); 1000 if (error != 0) 1001 goto reset; 1002 1003 error = athn_set_chan(sc, curchan, extchan); 1004 if (error != 0) { 1005 reset: /* Error found, try a full reset. */ 1006 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 1007 error = athn_hw_reset(sc, curchan, extchan, 0); 1008 if (error != 0) /* Hopeless case. */ 1009 return error; 1010 } 1011 athn_rx_start(sc); 1012 1013 /* Re-enable interrupts. */ 1014 athn_enable_interrupts(sc); 1015 return 0; 1016 } 1017 1018 PUBLIC void 1019 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1020 { 1021 #define COEFF_SCALE_SHIFT 24 1022 uint32_t exp, man; 1023 1024 /* exponent = 14 - floor(log2(coeff)) */ 1025 for (exp = 31; exp > 0; exp--) 1026 if (coeff & (1 << exp)) 1027 break; 1028 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1029 1030 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1031 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1032 1033 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1034 *exponent = exp - 16; 1035 #undef COEFF_SCALE_SHIFT 1036 } 1037 1038 PUBLIC void 1039 athn_reset_key(struct athn_softc *sc, int entry) 1040 { 1041 1042 /* 1043 * NB: Key cache registers access special memory area that requires 1044 * two 32-bit writes to actually update the values in the internal 1045 * memory. Consequently, writes must be grouped by pair. 1046 */ 1047 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1048 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1049 1050 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1051 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1052 1053 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1054 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1055 1056 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1057 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1058 1059 AR_WRITE_BARRIER(sc); 1060 } 1061 1062 #ifdef notyet 1063 Static int 1064 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1065 struct ieee80211_key *k) 1066 { 1067 struct athn_softc *sc = ic->ic_ifp->if_softc; 1068 const uint8_t *txmic, *rxmic, *key, *addr; 1069 uintptr_t entry, micentry; 1070 uint32_t type, lo, hi; 1071 1072 switch (k->k_cipher) { 1073 case IEEE80211_CIPHER_WEP40: 1074 type = AR_KEYTABLE_TYPE_40; 1075 break; 1076 case IEEE80211_CIPHER_WEP104: 1077 type = AR_KEYTABLE_TYPE_104; 1078 break; 1079 case IEEE80211_CIPHER_TKIP: 1080 type = AR_KEYTABLE_TYPE_TKIP; 1081 break; 1082 case IEEE80211_CIPHER_CCMP: 1083 type = AR_KEYTABLE_TYPE_CCM; 1084 break; 1085 default: 1086 /* Fallback to software crypto for other ciphers. */ 1087 return ieee80211_set_key(ic, ni, k); 1088 } 1089 1090 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1091 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1092 else 1093 entry = k->k_id; 1094 k->k_priv = (void *)entry; 1095 1096 /* NB: See note about key cache registers access above. */ 1097 key = k->k_key; 1098 if (type == AR_KEYTABLE_TYPE_TKIP) { 1099 #ifndef IEEE80211_STA_ONLY 1100 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1101 txmic = &key[16]; 1102 rxmic = &key[24]; 1103 } else 1104 #endif 1105 { 1106 rxmic = &key[16]; 1107 txmic = &key[24]; 1108 } 1109 /* Tx+Rx MIC key is at entry + 64. */ 1110 micentry = entry + 64; 1111 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1112 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1113 1114 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1115 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1116 1117 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1118 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1119 } 1120 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1121 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1122 1123 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1124 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1125 1126 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1127 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1128 1129 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1130 addr = ni->ni_macaddr; 1131 lo = LE_READ_4(&addr[0]); 1132 hi = LE_READ_2(&addr[4]); 1133 lo = lo >> 1 | hi << 31; 1134 hi = hi >> 1; 1135 } else 1136 lo = hi = 0; 1137 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1138 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1139 AR_WRITE_BARRIER(sc); 1140 return 0; 1141 } 1142 1143 Static void 1144 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1145 struct ieee80211_key *k) 1146 { 1147 struct athn_softc *sc = ic->ic_ifp->if_softc; 1148 uintptr_t entry; 1149 1150 switch (k->k_cipher) { 1151 case IEEE80211_CIPHER_WEP40: 1152 case IEEE80211_CIPHER_WEP104: 1153 case IEEE80211_CIPHER_CCMP: 1154 entry = (uintptr_t)k->k_priv; 1155 athn_reset_key(sc, entry); 1156 break; 1157 case IEEE80211_CIPHER_TKIP: 1158 entry = (uintptr_t)k->k_priv; 1159 athn_reset_key(sc, entry); 1160 athn_reset_key(sc, entry + 64); 1161 break; 1162 default: 1163 /* Fallback to software crypto for other ciphers. */ 1164 ieee80211_delete_key(ic, ni, k); 1165 } 1166 } 1167 #endif /* notyet */ 1168 1169 PUBLIC void 1170 athn_led_init(struct athn_softc *sc) 1171 { 1172 struct athn_ops *ops = &sc->sc_ops; 1173 1174 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1175 /* LED off, active low. */ 1176 athn_set_led(sc, 0); 1177 } 1178 1179 PUBLIC void 1180 athn_set_led(struct athn_softc *sc, int on) 1181 { 1182 struct athn_ops *ops = &sc->sc_ops; 1183 1184 sc->sc_led_state = on; 1185 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1186 } 1187 1188 #ifdef ATHN_BT_COEXISTENCE 1189 Static void 1190 athn_btcoex_init(struct athn_softc *sc) 1191 { 1192 struct athn_ops *ops = &sc->sc_ops; 1193 uint32_t reg; 1194 1195 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1196 /* Connect bt_active to baseband. */ 1197 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1198 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1199 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1200 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1201 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1202 1203 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1204 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1205 AR_GPIO_BTACTIVE_PIN); 1206 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1207 AR_WRITE_BARRIER(sc); 1208 1209 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1210 } else { /* 3-wire. */ 1211 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1212 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1213 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1214 1215 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1216 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1217 AR_GPIO_BTACTIVE_PIN); 1218 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1219 AR_GPIO_BTPRIORITY_PIN); 1220 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1221 AR_WRITE_BARRIER(sc); 1222 1223 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1224 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1225 } 1226 } 1227 1228 Static void 1229 athn_btcoex_enable(struct athn_softc *sc) 1230 { 1231 struct athn_ops *ops = &sc->sc_ops; 1232 uint32_t reg; 1233 1234 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1235 AR_WRITE(sc, AR_BT_COEX_MODE, 1236 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1237 SM(AR_BT_PRIORITY_TIME, 2) | 1238 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1239 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1240 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1241 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1242 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1243 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1244 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1245 AR_WRITE(sc, AR_BT_COEX_MODE2, 1246 SM(AR_BT_BCN_MISS_THRESH, 50) | 1247 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1248 1249 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1250 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1251 AR_WRITE_BARRIER(sc); 1252 1253 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1254 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1255 1256 } else { /* 2-wire. */ 1257 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1258 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1259 } 1260 reg = AR_READ(sc, AR_GPIO_PDPU); 1261 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1262 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1263 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1264 AR_WRITE_BARRIER(sc); 1265 1266 /* Disable PCIe Active State Power Management (ASPM). */ 1267 if (sc->sc_disable_aspm != NULL) 1268 sc->sc_disable_aspm(sc); 1269 1270 /* XXX Start periodic timer. */ 1271 } 1272 1273 Static void 1274 athn_btcoex_disable(struct athn_softc *sc) 1275 { 1276 struct athn_ops *ops = &sc->sc_ops; 1277 1278 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1279 1280 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1281 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1282 1283 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1284 AR_WRITE(sc, AR_BT_COEX_MODE, 1285 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1286 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1287 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1288 /* XXX Stop periodic timer. */ 1289 } 1290 AR_WRITE_BARRIER(sc); 1291 /* XXX Restore ASPM setting? */ 1292 } 1293 #endif 1294 1295 Static void 1296 athn_iter_func(void *arg, struct ieee80211_node *ni) 1297 { 1298 struct athn_softc *sc = arg; 1299 struct athn_node *an = (struct athn_node *)ni; 1300 1301 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1302 } 1303 1304 Static void 1305 athn_calib_to(void *arg) 1306 { 1307 extern int ticks; 1308 struct athn_softc *sc = arg; 1309 struct athn_ops *ops = &sc->sc_ops; 1310 struct ieee80211com *ic = &sc->sc_ic; 1311 int s; 1312 1313 s = splnet(); 1314 1315 /* Do periodic (every 4 minutes) PA calibration. */ 1316 if (AR_SREV_9285_11_OR_LATER(sc) && 1317 !AR_SREV_9380_10_OR_LATER(sc) && 1318 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1319 sc->sc_pa_calib_ticks = ticks; 1320 if (AR_SREV_9271(sc)) 1321 ar9271_pa_calib(sc); 1322 else 1323 ar9285_pa_calib(sc); 1324 } 1325 1326 /* Do periodic (every 30 seconds) temperature compensation. */ 1327 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1328 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1329 sc->sc_olpc_ticks = ticks; 1330 ops->olpc_temp_compensation(sc); 1331 } 1332 1333 #ifdef notyet 1334 /* XXX ANI. */ 1335 athn_ani_monitor(sc); 1336 1337 ops->next_calib(sc); 1338 #endif 1339 if (ic->ic_fixed_rate == -1) { 1340 if (ic->ic_opmode == IEEE80211_M_STA) 1341 athn_iter_func(sc, ic->ic_bss); 1342 else 1343 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1344 } 1345 callout_schedule(&sc->sc_calib_to, hz / 2); 1346 splx(s); 1347 } 1348 1349 Static int 1350 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1351 struct ieee80211_channel *extchan) 1352 { 1353 struct athn_ops *ops = &sc->sc_ops; 1354 int error; 1355 1356 if (AR_SREV_9380_10_OR_LATER(sc)) 1357 error = ar9003_init_calib(sc); 1358 else if (AR_SREV_9285_10_OR_LATER(sc)) 1359 error = ar9285_init_calib(sc, curchan, extchan); 1360 else 1361 error = ar5416_init_calib(sc, curchan, extchan); 1362 if (error != 0) 1363 return error; 1364 1365 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1366 /* Do PA calibration. */ 1367 if (AR_SREV_9285_11_OR_LATER(sc)) { 1368 extern int ticks; 1369 sc->sc_pa_calib_ticks = ticks; 1370 if (AR_SREV_9271(sc)) 1371 ar9271_pa_calib(sc); 1372 else 1373 ar9285_pa_calib(sc); 1374 } 1375 /* Do noisefloor calibration. */ 1376 ops->noisefloor_calib(sc); 1377 } 1378 if (AR_SREV_9160_10_OR_LATER(sc)) { 1379 /* Support IQ calibration. */ 1380 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1381 if (AR_SREV_9380_10_OR_LATER(sc)) { 1382 /* Support temperature compensation calibration. */ 1383 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1384 } else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1385 /* 1386 * ADC gain calibration causes uplink throughput 1387 * drops in HT40 mode on AR9287. 1388 */ 1389 if (!AR_SREV_9287(sc)) { 1390 /* Support ADC gain calibration. */ 1391 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1392 } 1393 /* Support ADC DC offset calibration. */ 1394 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1395 } 1396 } 1397 return 0; 1398 } 1399 1400 /* 1401 * Adaptive noise immunity. 1402 */ 1403 #ifdef notyet 1404 Static int32_t 1405 athn_ani_get_rssi(struct athn_softc *sc) 1406 { 1407 1408 return 0; /* XXX */ 1409 } 1410 #endif /* notyet */ 1411 1412 #ifdef notyet 1413 Static void 1414 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1415 { 1416 struct athn_ani *ani = &sc->sc_ani; 1417 struct athn_ops *ops = &sc->sc_ops; 1418 int32_t rssi; 1419 1420 /* First, raise noise immunity level, up to max. */ 1421 if (ani->noise_immunity_level < 4) { 1422 ani->noise_immunity_level++; 1423 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1424 return; 1425 } 1426 1427 /* Then, raise our spur immunity level, up to max. */ 1428 if (ani->spur_immunity_level < 7) { 1429 ani->spur_immunity_level++; 1430 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1431 return; 1432 } 1433 1434 #ifndef IEEE80211_STA_ONLY 1435 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1436 if (ani->firstep_level < 2) { 1437 ani->firstep_level++; 1438 ops->set_firstep_level(sc, ani->firstep_level); 1439 } 1440 return; 1441 } 1442 #endif 1443 rssi = athn_ani_get_rssi(sc); 1444 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1445 /* 1446 * Beacon RSSI is high, turn off OFDM weak signal detection 1447 * or raise first step level as last resort. 1448 */ 1449 if (ani->ofdm_weak_signal) { 1450 ani->ofdm_weak_signal = 0; 1451 ops->disable_ofdm_weak_signal(sc); 1452 ani->spur_immunity_level = 0; 1453 ops->set_spur_immunity_level(sc, 0); 1454 } else if (ani->firstep_level < 2) { 1455 ani->firstep_level++; 1456 ops->set_firstep_level(sc, ani->firstep_level); 1457 } 1458 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1459 /* 1460 * Beacon RSSI is in mid range, we need OFDM weak signal 1461 * detection but we can raise first step level. 1462 */ 1463 if (!ani->ofdm_weak_signal) { 1464 ani->ofdm_weak_signal = 1; 1465 ops->enable_ofdm_weak_signal(sc); 1466 } 1467 if (ani->firstep_level < 2) { 1468 ani->firstep_level++; 1469 ops->set_firstep_level(sc, ani->firstep_level); 1470 } 1471 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1472 /* 1473 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1474 * signal detection and zero first step level to maximize 1475 * CCK sensitivity. 1476 */ 1477 if (ani->ofdm_weak_signal) { 1478 ani->ofdm_weak_signal = 0; 1479 ops->disable_ofdm_weak_signal(sc); 1480 } 1481 if (ani->firstep_level > 0) { 1482 ani->firstep_level = 0; 1483 ops->set_firstep_level(sc, 0); 1484 } 1485 } 1486 } 1487 #endif /* notyet */ 1488 1489 #ifdef notyet 1490 Static void 1491 athn_ani_cck_err_trigger(struct athn_softc *sc) 1492 { 1493 struct athn_ani *ani = &sc->sc_ani; 1494 struct athn_ops *ops = &sc->sc_ops; 1495 int32_t rssi; 1496 1497 /* Raise noise immunity level, up to max. */ 1498 if (ani->noise_immunity_level < 4) { 1499 ani->noise_immunity_level++; 1500 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1501 return; 1502 } 1503 1504 #ifndef IEEE80211_STA_ONLY 1505 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1506 if (ani->firstep_level < 2) { 1507 ani->firstep_level++; 1508 ops->set_firstep_level(sc, ani->firstep_level); 1509 } 1510 return; 1511 } 1512 #endif 1513 rssi = athn_ani_get_rssi(sc); 1514 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1515 /* 1516 * Beacon RSSI is in mid or high range, raise first step 1517 * level. 1518 */ 1519 if (ani->firstep_level < 2) { 1520 ani->firstep_level++; 1521 ops->set_firstep_level(sc, ani->firstep_level); 1522 } 1523 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1524 /* 1525 * Beacon RSSI is low, zero first step level to maximize 1526 * CCK sensitivity. 1527 */ 1528 if (ani->firstep_level > 0) { 1529 ani->firstep_level = 0; 1530 ops->set_firstep_level(sc, 0); 1531 } 1532 } 1533 } 1534 #endif /* notyet */ 1535 1536 #ifdef notyet 1537 Static void 1538 athn_ani_lower_immunity(struct athn_softc *sc) 1539 { 1540 struct athn_ani *ani = &sc->sc_ani; 1541 struct athn_ops *ops = &sc->sc_ops; 1542 int32_t rssi; 1543 1544 #ifndef IEEE80211_STA_ONLY 1545 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1546 if (ani->firstep_level > 0) { 1547 ani->firstep_level--; 1548 ops->set_firstep_level(sc, ani->firstep_level); 1549 } 1550 return; 1551 } 1552 #endif 1553 rssi = athn_ani_get_rssi(sc); 1554 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1555 /* 1556 * Beacon RSSI is high, leave OFDM weak signal detection 1557 * off or it may oscillate. 1558 */ 1559 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1560 /* 1561 * Beacon RSSI is in mid range, turn on OFDM weak signal 1562 * detection or lower first step level. 1563 */ 1564 if (!ani->ofdm_weak_signal) { 1565 ani->ofdm_weak_signal = 1; 1566 ops->enable_ofdm_weak_signal(sc); 1567 return; 1568 } 1569 if (ani->firstep_level > 0) { 1570 ani->firstep_level--; 1571 ops->set_firstep_level(sc, ani->firstep_level); 1572 return; 1573 } 1574 } else { 1575 /* Beacon RSSI is low, lower first step level. */ 1576 if (ani->firstep_level > 0) { 1577 ani->firstep_level--; 1578 ops->set_firstep_level(sc, ani->firstep_level); 1579 return; 1580 } 1581 } 1582 /* 1583 * Lower spur immunity level down to zero, or if all else fails, 1584 * lower noise immunity level down to zero. 1585 */ 1586 if (ani->spur_immunity_level > 0) { 1587 ani->spur_immunity_level--; 1588 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1589 } else if (ani->noise_immunity_level > 0) { 1590 ani->noise_immunity_level--; 1591 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1592 } 1593 } 1594 #endif /* notyet */ 1595 1596 #ifdef notyet 1597 Static void 1598 athn_ani_restart(struct athn_softc *sc) 1599 { 1600 struct athn_ani *ani = &sc->sc_ani; 1601 1602 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1603 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1604 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1605 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1606 AR_WRITE_BARRIER(sc); 1607 1608 ani->listen_time = 0; 1609 ani->ofdm_phy_err_count = 0; 1610 ani->cck_phy_err_count = 0; 1611 } 1612 #endif /* notyet */ 1613 1614 #ifdef notyet 1615 Static void 1616 athn_ani_monitor(struct athn_softc *sc) 1617 { 1618 struct athn_ani *ani = &sc->sc_ani; 1619 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1620 int32_t cycdelta, txfdelta, rxfdelta; 1621 int32_t listen_time; 1622 1623 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1624 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1625 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1626 1627 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1628 cycdelta = cyccnt - ani->cyccnt; 1629 txfdelta = txfcnt - ani->txfcnt; 1630 rxfdelta = rxfcnt - ani->rxfcnt; 1631 1632 listen_time = (cycdelta - txfdelta - rxfdelta) / 1633 (athn_clock_rate(sc) * 1000); 1634 } else 1635 listen_time = 0; 1636 1637 ani->cyccnt = cyccnt; 1638 ani->txfcnt = txfcnt; 1639 ani->rxfcnt = rxfcnt; 1640 1641 if (listen_time < 0) { 1642 athn_ani_restart(sc); 1643 return; 1644 } 1645 ani->listen_time += listen_time; 1646 1647 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1648 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1649 1650 if (phy1 < ani->ofdm_phy_err_base) { 1651 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1652 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1653 } 1654 if (phy2 < ani->cck_phy_err_base) { 1655 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1656 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1657 } 1658 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1659 AR_WRITE_BARRIER(sc); 1660 return; 1661 } 1662 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1663 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1664 1665 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1666 /* Check to see if we need to lower immunity. */ 1667 if (ani->ofdm_phy_err_count <= 1668 ani->listen_time * ani->ofdm_trig_low / 1000 && 1669 ani->cck_phy_err_count <= 1670 ani->listen_time * ani->cck_trig_low / 1000) 1671 athn_ani_lower_immunity(sc); 1672 athn_ani_restart(sc); 1673 1674 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1675 /* Check to see if we need to raise immunity. */ 1676 if (ani->ofdm_phy_err_count > 1677 ani->listen_time * ani->ofdm_trig_high / 1000) { 1678 athn_ani_ofdm_err_trigger(sc); 1679 athn_ani_restart(sc); 1680 } else if (ani->cck_phy_err_count > 1681 ani->listen_time * ani->cck_trig_high / 1000) { 1682 athn_ani_cck_err_trigger(sc); 1683 athn_ani_restart(sc); 1684 } 1685 } 1686 } 1687 #endif /* notyet */ 1688 1689 PUBLIC uint8_t 1690 athn_chan2fbin(struct ieee80211_channel *c) 1691 { 1692 1693 if (IEEE80211_IS_CHAN_2GHZ(c)) 1694 return c->ic_freq - 2300; 1695 else 1696 return (c->ic_freq - 4800) / 5; 1697 } 1698 1699 PUBLIC int 1700 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1701 { 1702 1703 if (x1 == x2) /* Prevents division by zero. */ 1704 return y1; 1705 /* Linear interpolation. */ 1706 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1707 } 1708 1709 PUBLIC void 1710 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1711 int *lo, int *hi) 1712 { 1713 int i; 1714 1715 for (i = 0; i < npiers; i++) 1716 if (pierfreq[i] == AR_BCHAN_UNUSED || 1717 pierfreq[i] > fbin) 1718 break; 1719 *hi = i; 1720 *lo = *hi - 1; 1721 if (*lo == -1) 1722 *lo = *hi; 1723 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1724 *hi = *lo; 1725 } 1726 1727 Static void 1728 athn_init_dma(struct athn_softc *sc) 1729 { 1730 uint32_t reg; 1731 1732 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1733 /* Set AHB not to do cacheline prefetches. */ 1734 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1735 } 1736 reg = AR_READ(sc, AR_TXCFG); 1737 /* Let MAC DMA reads be in 128-byte chunks. */ 1738 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1739 1740 /* Set initial Tx trigger level. */ 1741 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1742 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1743 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1744 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1745 AR_WRITE(sc, AR_TXCFG, reg); 1746 1747 /* Let MAC DMA writes be in 128-byte chunks. */ 1748 reg = AR_READ(sc, AR_RXCFG); 1749 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1750 AR_WRITE(sc, AR_RXCFG, reg); 1751 1752 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1753 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1754 1755 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1756 if (AR_SREV_9285(sc)) { 1757 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1758 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1759 } else if (!AR_SREV_9271(sc)) { 1760 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1761 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1762 } 1763 AR_WRITE_BARRIER(sc); 1764 1765 /* Reset Tx status ring. */ 1766 if (AR_SREV_9380_10_OR_LATER(sc)) 1767 ar9003_reset_txsring(sc); 1768 } 1769 1770 PUBLIC void 1771 athn_inc_tx_trigger_level(struct athn_softc *sc) 1772 { 1773 uint32_t reg, ftrig; 1774 1775 reg = AR_READ(sc, AR_TXCFG); 1776 ftrig = MS(reg, AR_TXCFG_FTRIG); 1777 /* 1778 * NB: The AR9285 and all single-stream parts have an issue that 1779 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1780 */ 1781 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1782 return; /* Already at max. */ 1783 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1784 AR_WRITE(sc, AR_TXCFG, reg); 1785 AR_WRITE_BARRIER(sc); 1786 } 1787 1788 PUBLIC int 1789 athn_stop_rx_dma(struct athn_softc *sc) 1790 { 1791 int ntries; 1792 1793 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1794 /* Wait for Rx enable bit to go low. */ 1795 for (ntries = 0; ntries < 100; ntries++) { 1796 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1797 return 0; 1798 DELAY(100); 1799 } 1800 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1801 return ETIMEDOUT; 1802 } 1803 1804 #ifdef unused 1805 Static int 1806 athn_rx_abort(struct athn_softc *sc) 1807 { 1808 int ntries; 1809 1810 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1811 for (ntries = 0; ntries < 1000; ntries++) { 1812 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1813 return 0; 1814 DELAY(10); 1815 } 1816 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1817 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1818 AR_WRITE_BARRIER(sc); 1819 return ETIMEDOUT; 1820 } 1821 #endif /* unused */ 1822 1823 Static void 1824 athn_tx_reclaim(struct athn_softc *sc, int qid) 1825 { 1826 struct athn_txq *txq = &sc->sc_txq[qid]; 1827 struct athn_tx_buf *bf; 1828 1829 /* Reclaim all buffers queued in the specified Tx queue. */ 1830 /* NB: Tx DMA must be stopped. */ 1831 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1832 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1833 1834 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1835 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1836 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1837 m_freem(bf->bf_m); 1838 bf->bf_m = NULL; 1839 bf->bf_ni = NULL; /* Nodes already freed! */ 1840 1841 /* Link Tx buffer back to global free list. */ 1842 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1843 } 1844 } 1845 1846 PUBLIC int 1847 athn_tx_pending(struct athn_softc *sc, int qid) 1848 { 1849 1850 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1851 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1852 } 1853 1854 PUBLIC void 1855 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1856 { 1857 uint32_t tsflo; 1858 int ntries, i; 1859 1860 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1861 for (ntries = 0; ntries < 40; ntries++) { 1862 if (!athn_tx_pending(sc, qid)) 1863 break; 1864 DELAY(100); 1865 } 1866 if (ntries == 40) { 1867 for (i = 0; i < 2; i++) { 1868 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1869 AR_WRITE(sc, AR_QUIET2, 1870 SM(AR_QUIET2_QUIET_DUR, 10)); 1871 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1872 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1873 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1874 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1875 break; 1876 } 1877 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1878 AR_WRITE_BARRIER(sc); 1879 DELAY(200); 1880 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1881 AR_WRITE_BARRIER(sc); 1882 1883 for (ntries = 0; ntries < 40; ntries++) { 1884 if (!athn_tx_pending(sc, qid)) 1885 break; 1886 DELAY(100); 1887 } 1888 1889 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1890 } 1891 AR_WRITE(sc, AR_Q_TXD, 0); 1892 AR_WRITE_BARRIER(sc); 1893 } 1894 1895 PUBLIC int 1896 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1897 { 1898 #define divround(a, b) (((a) + (b) - 1) / (b)) 1899 int txtime; 1900 1901 /* XXX HT. */ 1902 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1903 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1904 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1905 txtime = 16 + 4 + 4 * txtime + 16; 1906 } else { 1907 txtime = divround(16 * len, athn_rates[ridx].rate); 1908 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1909 txtime += 72 + 24; 1910 else 1911 txtime += 144 + 48; 1912 txtime += 10; /* 10us SIFS. */ 1913 } 1914 return txtime; 1915 #undef divround 1916 } 1917 1918 PUBLIC void 1919 athn_init_tx_queues(struct athn_softc *sc) 1920 { 1921 int qid; 1922 1923 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1924 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1925 sc->sc_txq[qid].lastds = NULL; 1926 sc->sc_txq[qid].wait = NULL; 1927 sc->sc_txq[qid].queued = 0; 1928 1929 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1930 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1931 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1932 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1933 AR_WRITE(sc, AR_QMISC(qid), 1934 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1935 AR_WRITE(sc, AR_DMISC(qid), 1936 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1937 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1938 } 1939 1940 /* Init beacon queue. */ 1941 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1942 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1943 AR_Q_MISC_CBR_INCR_DIS1); 1944 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1945 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1946 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1947 AR_D_MISC_BEACON_USE | 1948 AR_D_MISC_POST_FR_BKOFF_DIS); 1949 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1950 SM(AR_D_LCL_IFS_CWMIN, 0) | 1951 SM(AR_D_LCL_IFS_CWMAX, 0) | 1952 SM(AR_D_LCL_IFS_AIFS, 1)); 1953 1954 /* Init CAB (Content After Beacon) queue. */ 1955 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1956 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1957 AR_Q_MISC_CBR_INCR_DIS0); 1958 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1959 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1960 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1961 1962 /* Init PS-Poll queue. */ 1963 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1964 AR_Q_MISC_CBR_INCR_DIS1); 1965 1966 /* Init UAPSD queue. */ 1967 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1968 AR_D_MISC_POST_FR_BKOFF_DIS); 1969 1970 if (AR_SREV_9380_10_OR_LATER(sc)) { 1971 /* Enable MAC descriptor CRC check. */ 1972 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1973 } 1974 /* Enable DESC interrupts for all Tx queues. */ 1975 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1976 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1977 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1978 AR_WRITE_BARRIER(sc); 1979 } 1980 1981 PUBLIC void 1982 athn_set_sta_timers(struct athn_softc *sc) 1983 { 1984 struct ieee80211com *ic = &sc->sc_ic; 1985 uint32_t tsfhi, tsflo, tsftu, reg; 1986 uint32_t intval, next_tbtt, next_dtim; 1987 int dtim_period, rem_dtim_count; 1988 1989 tsfhi = AR_READ(sc, AR_TSF_U32); 1990 tsflo = AR_READ(sc, AR_TSF_L32); 1991 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1992 1993 /* Beacon interval in TU. */ 1994 intval = ic->ic_bss->ni_intval; 1995 1996 next_tbtt = roundup(tsftu, intval); 1997 #ifdef notyet 1998 dtim_period = ic->ic_dtim_period; 1999 if (dtim_period <= 0) 2000 #endif 2001 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2002 2003 #ifdef notyet 2004 int dtim_count = ic->ic_dtim_count; 2005 if (dtim_count >= dtim_period) /* Should not happen. */ 2006 dtim_count = 0; /* Assume last TIM was a DTIM. */ 2007 #endif 2008 2009 /* Compute number of remaining TIMs until next DTIM. */ 2010 rem_dtim_count = 0; /* XXX */ 2011 next_dtim = next_tbtt + rem_dtim_count * intval; 2012 2013 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2014 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2015 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2016 2017 /* 2018 * Set the number of consecutive beacons to miss before raising 2019 * a BMISS interrupt to 10. 2020 */ 2021 reg = AR_READ(sc, AR_RSSI_THR); 2022 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2023 AR_WRITE(sc, AR_RSSI_THR, reg); 2024 2025 AR_WRITE(sc, AR_NEXT_DTIM, 2026 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2027 AR_WRITE(sc, AR_NEXT_TIM, 2028 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2029 2030 /* CAB timeout is in 1/8 TU. */ 2031 AR_WRITE(sc, AR_SLEEP1, 2032 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2033 AR_SLEEP1_ASSUME_DTIM); 2034 AR_WRITE(sc, AR_SLEEP2, 2035 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2036 2037 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2038 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2039 2040 AR_SETBITS(sc, AR_TIMER_MODE, 2041 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2042 2043 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2044 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2045 2046 AR_WRITE_BARRIER(sc); 2047 } 2048 2049 #ifndef IEEE80211_STA_ONLY 2050 PUBLIC void 2051 athn_set_hostap_timers(struct athn_softc *sc) 2052 { 2053 struct ieee80211com *ic = &sc->sc_ic; 2054 uint32_t intval, next_tbtt; 2055 2056 /* Beacon interval in TU. */ 2057 intval = ic->ic_bss->ni_intval; 2058 next_tbtt = intval; 2059 2060 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2061 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2062 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2063 AR_WRITE(sc, AR_NEXT_CFP, 2064 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2065 2066 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2067 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2068 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2069 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2070 2071 AR_WRITE(sc, AR_TIMER_MODE, 2072 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2073 2074 AR_WRITE_BARRIER(sc); 2075 } 2076 #endif 2077 2078 PUBLIC void 2079 athn_set_opmode(struct athn_softc *sc) 2080 { 2081 uint32_t reg; 2082 2083 switch (sc->sc_ic.ic_opmode) { 2084 #ifndef IEEE80211_STA_ONLY 2085 case IEEE80211_M_HOSTAP: 2086 reg = AR_READ(sc, AR_STA_ID1); 2087 reg &= ~AR_STA_ID1_ADHOC; 2088 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2089 AR_WRITE(sc, AR_STA_ID1, reg); 2090 2091 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2092 break; 2093 case IEEE80211_M_IBSS: 2094 case IEEE80211_M_AHDEMO: 2095 reg = AR_READ(sc, AR_STA_ID1); 2096 reg &= ~AR_STA_ID1_STA_AP; 2097 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2098 AR_WRITE(sc, AR_STA_ID1, reg); 2099 2100 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2101 break; 2102 #endif 2103 default: 2104 reg = AR_READ(sc, AR_STA_ID1); 2105 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2106 reg |= AR_STA_ID1_KSRCH_MODE; 2107 AR_WRITE(sc, AR_STA_ID1, reg); 2108 break; 2109 } 2110 AR_WRITE_BARRIER(sc); 2111 } 2112 2113 PUBLIC void 2114 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2115 { 2116 const uint8_t *bssid = ni->ni_bssid; 2117 2118 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2119 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2120 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2121 AR_WRITE_BARRIER(sc); 2122 } 2123 2124 Static void 2125 athn_enable_interrupts(struct athn_softc *sc) 2126 { 2127 uint32_t mask2; 2128 2129 athn_disable_interrupts(sc); /* XXX */ 2130 2131 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2132 2133 mask2 = AR_READ(sc, AR_IMR_S2); 2134 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2135 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2136 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2137 AR_WRITE(sc, AR_IMR_S2, mask2); 2138 2139 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2140 2141 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2142 2143 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2144 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2145 2146 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2147 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2148 AR_WRITE_BARRIER(sc); 2149 } 2150 2151 Static void 2152 athn_disable_interrupts(struct athn_softc *sc) 2153 { 2154 2155 AR_WRITE(sc, AR_IER, 0); 2156 (void)AR_READ(sc, AR_IER); 2157 2158 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2159 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2160 2161 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2162 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2163 2164 AR_WRITE(sc, AR_IMR, 0); 2165 2166 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2167 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2168 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2169 2170 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2171 AR_WRITE_BARRIER(sc); 2172 } 2173 2174 Static void 2175 athn_init_qos(struct athn_softc *sc) 2176 { 2177 2178 /* Initialize QoS settings. */ 2179 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2180 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2181 AR_WRITE(sc, AR_QOS_NO_ACK, 2182 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2183 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2184 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2185 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2186 /* Initialize TXOP for all TIDs. */ 2187 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2188 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2189 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2190 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2191 AR_WRITE_BARRIER(sc); 2192 } 2193 2194 PUBLIC int 2195 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2196 struct ieee80211_channel *extchan, int init) 2197 { 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 struct athn_ops *ops = &sc->sc_ops; 2200 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2201 int i, error; 2202 2203 /* XXX not if already awake */ 2204 if ((error = athn_set_power_awake(sc)) != 0) { 2205 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2206 return error; 2207 } 2208 2209 /* Preserve the antenna on a channel switch. */ 2210 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2211 def_ant = 1; 2212 /* Preserve other registers. */ 2213 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2214 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2215 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2216 AR_CFG_LED_BLINK_SLOW); 2217 2218 /* Mark PHY as inactive. */ 2219 ops->disable_phy(sc); 2220 2221 if (init && AR_SREV_9271(sc)) { 2222 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2223 AR9271_RADIO_RF_RST); 2224 DELAY(50); 2225 } 2226 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2227 /* Save TSF before it gets cleared. */ 2228 tsfhi = AR_READ(sc, AR_TSF_U32); 2229 tsflo = AR_READ(sc, AR_TSF_L32); 2230 2231 /* NB: RTC reset clears TSF. */ 2232 error = athn_reset_power_on(sc); 2233 } else { 2234 tsfhi = tsflo = 0; /* XXX: gcc */ 2235 error = athn_reset(sc, 0); 2236 } 2237 if (error != 0) { 2238 aprint_error_dev(sc->sc_dev, 2239 "could not reset chip (error=%d)\n", error); 2240 return error; 2241 } 2242 2243 /* XXX not if already awake */ 2244 if ((error = athn_set_power_awake(sc)) != 0) { 2245 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2246 return error; 2247 } 2248 2249 athn_init_pll(sc, curchan); 2250 ops->set_rf_mode(sc, curchan); 2251 2252 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2253 /* Check that the radio is not disabled by hardware switch. */ 2254 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2255 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2256 reg = !reg; 2257 if (!reg) { 2258 aprint_error_dev(sc->sc_dev, 2259 "radio is disabled by hardware switch\n"); 2260 return EPERM; 2261 } 2262 } 2263 if (init && AR_SREV_9271(sc)) { 2264 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2265 AR9271_GATE_MAC_CTL); 2266 DELAY(50); 2267 } 2268 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2269 /* Restore TSF if it got cleared. */ 2270 AR_WRITE(sc, AR_TSF_L32, tsflo); 2271 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2272 } 2273 2274 if (AR_SREV_9280_10_OR_LATER(sc)) 2275 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2276 2277 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2278 ar9287_1_3_enable_async_fifo(sc); 2279 2280 /* Write init values to hardware. */ 2281 ops->hw_init(sc, curchan, extchan); 2282 2283 /* 2284 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2285 * management frames using CCMP. 2286 */ 2287 if (AR_SREV_9280_20_OR_LATER(sc)) { 2288 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2289 /* Do not mask the subtype field in management frames. */ 2290 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2291 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2292 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2293 IEEE80211_FC1_MORE_DATA)); 2294 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2295 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2296 /* Disable hardware crypto for management frames. */ 2297 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2298 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2299 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2300 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2301 } 2302 2303 if (ic->ic_curmode != IEEE80211_MODE_11B) 2304 ops->set_delta_slope(sc, curchan, extchan); 2305 2306 ops->spur_mitigate(sc, curchan, extchan); 2307 ops->init_from_rom(sc, curchan, extchan); 2308 2309 /* XXX */ 2310 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2311 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2312 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2313 2314 athn_set_opmode(sc); 2315 2316 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2317 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2318 2319 /* Restore previous antenna. */ 2320 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2321 2322 AR_WRITE(sc, AR_BSS_ID0, 0); 2323 AR_WRITE(sc, AR_BSS_ID1, 0); 2324 2325 AR_WRITE(sc, AR_ISR, 0xffffffff); 2326 2327 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2328 2329 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2330 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2331 return error; 2332 } 2333 sc->sc_curchan = curchan; 2334 sc->sc_curchanext = extchan; 2335 2336 for (i = 0; i < AR_NUM_DCU; i++) 2337 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2338 2339 athn_init_tx_queues(sc); 2340 2341 /* Initialize interrupt mask. */ 2342 sc->sc_imask = 2343 AR_IMR_TXDESC | AR_IMR_TXEOL | 2344 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2345 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2346 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2347 if (AR_SREV_9380_10_OR_LATER(sc)) 2348 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2349 #ifndef IEEE80211_STA_ONLY 2350 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2351 sc->sc_imask |= AR_IMR_MIB; 2352 #endif 2353 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2354 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2355 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2356 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2357 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2358 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2359 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2360 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2361 if (AR_SREV_9380_10_OR_LATER(sc)) { 2362 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2363 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2364 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2365 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2366 } 2367 2368 athn_init_qos(sc); 2369 2370 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2371 2372 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2373 ar9287_1_3_setup_async_fifo(sc); 2374 2375 /* Disable sequence number generation in hardware. */ 2376 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2377 2378 athn_init_dma(sc); 2379 2380 /* Program observation bus to see MAC interrupts. */ 2381 AR_WRITE(sc, sc->sc_obs_off, 8); 2382 2383 /* Setup Rx interrupt mitigation. */ 2384 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2385 2386 ops->init_baseband(sc); 2387 2388 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2389 aprint_error_dev(sc->sc_dev, 2390 "could not initialize calibration\n"); 2391 return error; 2392 } 2393 2394 ops->set_rxchains(sc); 2395 2396 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2397 2398 if (sc->sc_flags & ATHN_FLAG_USB) { 2399 if (AR_SREV_9271(sc)) 2400 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2401 else 2402 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2403 } 2404 #if BYTE_ORDER == BIG_ENDIAN 2405 else { 2406 /* Default is LE, turn on swapping for BE. */ 2407 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2408 } 2409 #endif 2410 AR_WRITE_BARRIER(sc); 2411 2412 return 0; 2413 } 2414 2415 Static struct ieee80211_node * 2416 athn_node_alloc(struct ieee80211_node_table *ntp) 2417 { 2418 2419 return malloc(sizeof(struct athn_node), M_DEVBUF, 2420 M_NOWAIT | M_ZERO); 2421 } 2422 2423 Static void 2424 athn_newassoc(struct ieee80211_node *ni, int isnew) 2425 { 2426 struct ieee80211com *ic = ni->ni_ic; 2427 struct athn_softc *sc = ic->ic_ifp->if_softc; 2428 struct athn_node *an = (void *)ni; 2429 struct ieee80211_rateset *rs = &ni->ni_rates; 2430 uint8_t rate; 2431 int ridx, i, j; 2432 2433 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2434 /* Start at lowest available bit-rate, AMRR will raise. */ 2435 ni->ni_txrate = 0; 2436 2437 for (i = 0; i < rs->rs_nrates; i++) { 2438 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2439 2440 /* Map 802.11 rate to HW rate index. */ 2441 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2442 if (athn_rates[ridx].rate == rate) 2443 break; 2444 an->ridx[i] = ridx; 2445 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2446 2447 /* Compute fallback rate for retries. */ 2448 an->fallback[i] = i; 2449 for (j = i - 1; j >= 0; j--) { 2450 if (athn_rates[an->ridx[j]].phy == 2451 athn_rates[an->ridx[i]].phy) { 2452 an->fallback[i] = j; 2453 break; 2454 } 2455 } 2456 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2457 i, an->fallback[i]); 2458 } 2459 } 2460 2461 Static int 2462 athn_media_change(struct ifnet *ifp) 2463 { 2464 struct athn_softc *sc = ifp->if_softc; 2465 struct ieee80211com *ic = &sc->sc_ic; 2466 uint8_t rate, ridx; 2467 int error; 2468 2469 error = ieee80211_media_change(ifp); 2470 if (error != ENETRESET) 2471 return error; 2472 2473 if (ic->ic_fixed_rate != -1) { 2474 rate = ic->ic_sup_rates[ic->ic_curmode]. 2475 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2476 /* Map 802.11 rate to HW rate index. */ 2477 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2478 if (athn_rates[ridx].rate == rate) 2479 break; 2480 sc->sc_fixed_ridx = ridx; 2481 } 2482 if (IS_UP_AND_RUNNING(ifp)) { 2483 athn_stop(ifp, 0); 2484 error = athn_init(ifp); 2485 } 2486 return error; 2487 } 2488 2489 Static void 2490 athn_next_scan(void *arg) 2491 { 2492 struct athn_softc *sc = arg; 2493 struct ieee80211com *ic = &sc->sc_ic; 2494 int s; 2495 2496 s = splnet(); 2497 if (ic->ic_state == IEEE80211_S_SCAN) 2498 ieee80211_next_scan(ic); 2499 splx(s); 2500 } 2501 2502 Static int 2503 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2504 { 2505 struct ifnet *ifp = ic->ic_ifp; 2506 struct athn_softc *sc = ifp->if_softc; 2507 uint32_t reg; 2508 int error; 2509 2510 callout_stop(&sc->sc_calib_to); 2511 2512 switch (nstate) { 2513 case IEEE80211_S_INIT: 2514 athn_set_led(sc, 0); 2515 break; 2516 case IEEE80211_S_SCAN: 2517 /* Make the LED blink while scanning. */ 2518 athn_set_led(sc, !sc->sc_led_state); 2519 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2520 if (error != 0) 2521 return error; 2522 callout_schedule(&sc->sc_scan_to, hz / 5); 2523 break; 2524 case IEEE80211_S_AUTH: 2525 athn_set_led(sc, 0); 2526 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2527 if (error != 0) 2528 return error; 2529 break; 2530 case IEEE80211_S_ASSOC: 2531 break; 2532 case IEEE80211_S_RUN: 2533 athn_set_led(sc, 1); 2534 2535 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2536 break; 2537 2538 /* Fake a join to initialize the Tx rate. */ 2539 athn_newassoc(ic->ic_bss, 1); 2540 2541 athn_set_bss(sc, ic->ic_bss); 2542 athn_disable_interrupts(sc); 2543 #ifndef IEEE80211_STA_ONLY 2544 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2545 athn_set_hostap_timers(sc); 2546 /* Enable software beacon alert interrupts. */ 2547 sc->sc_imask |= AR_IMR_SWBA; 2548 } else 2549 #endif 2550 { 2551 athn_set_sta_timers(sc); 2552 /* Enable beacon miss interrupts. */ 2553 sc->sc_imask |= AR_IMR_BMISS; 2554 2555 /* Stop receiving beacons from other BSS. */ 2556 reg = AR_READ(sc, AR_RX_FILTER); 2557 reg = (reg & ~AR_RX_FILTER_BEACON) | 2558 AR_RX_FILTER_MYBEACON; 2559 AR_WRITE(sc, AR_RX_FILTER, reg); 2560 AR_WRITE_BARRIER(sc); 2561 } 2562 athn_enable_interrupts(sc); 2563 2564 if (sc->sc_sup_calib_mask != 0) { 2565 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2566 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2567 /* ops->do_calib(sc); */ 2568 } 2569 /* XXX Start ANI. */ 2570 2571 callout_schedule(&sc->sc_calib_to, hz / 2); 2572 break; 2573 } 2574 2575 return sc->sc_newstate(ic, nstate, arg); 2576 } 2577 2578 #ifdef notyet_edca 2579 PUBLIC void 2580 athn_updateedca(struct ieee80211com *ic) 2581 { 2582 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2583 struct athn_softc *sc = ic->ic_ifp->if_softc; 2584 const struct ieee80211_edca_ac_params *ac; 2585 int aci, qid; 2586 2587 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2588 ac = &ic->ic_edca_ac[aci]; 2589 qid = athn_ac2qid[aci]; 2590 2591 AR_WRITE(sc, AR_DLCL_IFS(qid), 2592 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2593 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2594 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2595 if (ac->ac_txoplimit != 0) { 2596 AR_WRITE(sc, AR_DCHNTIME(qid), 2597 SM(AR_D_CHNTIME_DUR, 2598 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2599 AR_D_CHNTIME_EN); 2600 } else 2601 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2602 } 2603 AR_WRITE_BARRIER(sc); 2604 #undef ATHN_EXP2 2605 } 2606 #endif /* notyet_edca */ 2607 2608 Static int 2609 athn_clock_rate(struct athn_softc *sc) 2610 { 2611 struct ieee80211com *ic = &sc->sc_ic; 2612 int clockrate; /* MHz. */ 2613 2614 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2615 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2616 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2617 else 2618 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2619 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2620 clockrate = AR_CLOCK_RATE_CCK; 2621 } else 2622 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2623 #ifndef IEEE80211_NO_HT 2624 if (sc->sc_curchanext != NULL) 2625 clockrate *= 2; 2626 #endif 2627 return clockrate; 2628 } 2629 2630 PUBLIC void 2631 athn_updateslot(struct ifnet *ifp) 2632 { 2633 struct athn_softc *sc = ifp->if_softc; 2634 struct ieee80211com *ic = &sc->sc_ic; 2635 int slot; 2636 2637 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2638 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2639 AR_WRITE_BARRIER(sc); 2640 } 2641 2642 Static void 2643 athn_start(struct ifnet *ifp) 2644 { 2645 struct athn_softc *sc = ifp->if_softc; 2646 struct ieee80211com *ic = &sc->sc_ic; 2647 struct ether_header *eh; 2648 struct ieee80211_node *ni; 2649 struct mbuf *m; 2650 2651 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2652 || !device_is_active(sc->sc_dev)) 2653 return; 2654 2655 for (;;) { 2656 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2657 ifp->if_flags |= IFF_OACTIVE; 2658 break; 2659 } 2660 /* Send pending management frames first. */ 2661 IF_DEQUEUE(&ic->ic_mgtq, m); 2662 if (m != NULL) { 2663 ni = M_GETCTX(m, struct ieee80211_node *); 2664 goto sendit; 2665 } 2666 if (ic->ic_state != IEEE80211_S_RUN) 2667 break; 2668 2669 /* Encapsulate and send data frames. */ 2670 IFQ_DEQUEUE(&ifp->if_snd, m); 2671 if (m == NULL) 2672 break; 2673 2674 if (m->m_len < (int)sizeof(*eh) && 2675 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2676 ifp->if_oerrors++; 2677 continue; 2678 } 2679 eh = mtod(m, struct ether_header *); 2680 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2681 if (ni == NULL) { 2682 m_freem(m); 2683 ifp->if_oerrors++; 2684 continue; 2685 } 2686 2687 bpf_mtap(ifp, m, BPF_D_OUT); 2688 2689 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2690 continue; 2691 sendit: 2692 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2693 2694 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2695 ieee80211_free_node(ni); 2696 ifp->if_oerrors++; 2697 continue; 2698 } 2699 2700 sc->sc_tx_timer = 5; 2701 ifp->if_timer = 1; 2702 } 2703 } 2704 2705 Static void 2706 athn_watchdog(struct ifnet *ifp) 2707 { 2708 struct athn_softc *sc = ifp->if_softc; 2709 2710 ifp->if_timer = 0; 2711 2712 if (sc->sc_tx_timer > 0) { 2713 if (--sc->sc_tx_timer == 0) { 2714 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2715 /* see athn_init, no need to call athn_stop here */ 2716 /* athn_stop(ifp, 0); */ 2717 (void)athn_init(ifp); 2718 ifp->if_oerrors++; 2719 return; 2720 } 2721 ifp->if_timer = 1; 2722 } 2723 ieee80211_watchdog(&sc->sc_ic); 2724 } 2725 2726 Static void 2727 athn_set_multi(struct athn_softc *sc) 2728 { 2729 struct ethercom *ec = &sc->sc_ec; 2730 struct ifnet *ifp = &ec->ec_if; 2731 struct ether_multi *enm; 2732 struct ether_multistep step; 2733 const uint8_t *addr; 2734 uint32_t val, lo, hi; 2735 uint8_t bit; 2736 2737 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2738 lo = hi = 0xffffffff; 2739 goto done; 2740 } 2741 lo = hi = 0; 2742 ETHER_LOCK(ec); 2743 ETHER_FIRST_MULTI(step, ec, enm); 2744 while (enm != NULL) { 2745 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2746 ifp->if_flags |= IFF_ALLMULTI; 2747 lo = hi = 0xffffffff; 2748 goto done; 2749 } 2750 addr = enm->enm_addrlo; 2751 /* Calculate the XOR value of all eight 6-bit words. */ 2752 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2753 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2754 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2755 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2756 bit &= 0x3f; 2757 if (bit < 32) 2758 lo |= 1 << bit; 2759 else 2760 hi |= 1 << (bit - 32); 2761 ETHER_NEXT_MULTI(step, enm); 2762 } 2763 done: 2764 ETHER_UNLOCK(ec); 2765 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2766 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2767 AR_WRITE_BARRIER(sc); 2768 } 2769 2770 Static int 2771 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2772 { 2773 struct athn_softc *sc = ifp->if_softc; 2774 struct ieee80211com *ic = &sc->sc_ic; 2775 int s, error = 0; 2776 2777 s = splnet(); 2778 2779 switch (cmd) { 2780 case SIOCSIFFLAGS: 2781 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2782 break; 2783 2784 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2785 case IFF_UP | IFF_RUNNING: 2786 #ifdef notyet 2787 if (((ifp->if_flags ^ sc->sc_if_flags) & 2788 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2789 /* XXX: setup multi */ 2790 #endif 2791 break; 2792 case IFF_UP: 2793 athn_init(ifp); 2794 break; 2795 2796 case IFF_RUNNING: 2797 athn_stop(ifp, 1); 2798 break; 2799 case 0: 2800 default: 2801 break; 2802 } 2803 sc->sc_if_flags = ifp->if_flags; 2804 break; 2805 2806 case SIOCADDMULTI: 2807 case SIOCDELMULTI: 2808 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2809 /* setup multicast filter, etc */ 2810 athn_set_multi(sc); 2811 error = 0; 2812 } 2813 break; 2814 2815 case SIOCS80211CHANNEL: 2816 error = ieee80211_ioctl(ic, cmd, data); 2817 if (error == ENETRESET && 2818 ic->ic_opmode == IEEE80211_M_MONITOR) { 2819 if (IS_UP_AND_RUNNING(ifp)) 2820 athn_switch_chan(sc, ic->ic_curchan, NULL); 2821 error = 0; 2822 } 2823 break; 2824 2825 default: 2826 error = ieee80211_ioctl(ic, cmd, data); 2827 } 2828 2829 if (error == ENETRESET) { 2830 error = 0; 2831 if (IS_UP_AND_RUNNING(ifp) && 2832 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2833 athn_stop(ifp, 0); 2834 error = athn_init(ifp); 2835 } 2836 } 2837 2838 splx(s); 2839 return error; 2840 } 2841 2842 Static int 2843 athn_init(struct ifnet *ifp) 2844 { 2845 struct athn_softc *sc = ifp->if_softc; 2846 struct athn_ops *ops = &sc->sc_ops; 2847 struct ieee80211com *ic = &sc->sc_ic; 2848 struct ieee80211_channel *curchan, *extchan; 2849 size_t i; 2850 int error; 2851 2852 KASSERT(!cpu_intr_p()); 2853 2854 if (device_is_active(sc->sc_dev)) { 2855 athn_stop(ifp, 0); /* see athn_watchdog() */ 2856 } else { 2857 short flags = ifp->if_flags; 2858 ifp->if_flags &= ~IFF_UP; 2859 /* avoid recursion in athn_resume */ 2860 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2861 !device_is_active(sc->sc_dev)) { 2862 printf("%s: failed to power up device\n", 2863 device_xname(sc->sc_dev)); 2864 return 0; 2865 } 2866 ifp->if_flags = flags; 2867 } 2868 2869 curchan = ic->ic_curchan; 2870 extchan = NULL; 2871 2872 /* In case a new MAC address has been configured. */ 2873 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2874 2875 #ifdef openbsd_power_management 2876 /* For CardBus, power on the socket. */ 2877 if (sc->sc_enable != NULL) { 2878 if ((error = sc->sc_enable(sc)) != 0) { 2879 aprint_error_dev(sc->sc_dev, 2880 "could not enable device\n"); 2881 goto fail; 2882 } 2883 if ((error = athn_reset_power_on(sc)) != 0) { 2884 aprint_error_dev(sc->sc_dev, 2885 "could not power on device\n"); 2886 goto fail; 2887 } 2888 } 2889 #endif 2890 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2891 athn_config_nonpcie(sc); 2892 else 2893 athn_config_pcie(sc); 2894 2895 /* Reset HW key cache entries. */ 2896 for (i = 0; i < sc->sc_kc_entries; i++) 2897 athn_reset_key(sc, i); 2898 2899 ops->enable_antenna_diversity(sc); 2900 2901 #ifdef ATHN_BT_COEXISTENCE 2902 /* Configure bluetooth coexistence for combo chips. */ 2903 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2904 athn_btcoex_init(sc); 2905 #endif 2906 2907 /* Configure LED. */ 2908 athn_led_init(sc); 2909 2910 /* Configure hardware radio switch. */ 2911 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2912 ops->rfsilent_init(sc); 2913 2914 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2915 aprint_error_dev(sc->sc_dev, 2916 "unable to reset hardware; reset status %d\n", error); 2917 goto fail; 2918 } 2919 2920 /* Enable Rx. */ 2921 athn_rx_start(sc); 2922 2923 /* Enable interrupts. */ 2924 athn_enable_interrupts(sc); 2925 2926 #ifdef ATHN_BT_COEXISTENCE 2927 /* Enable bluetooth coexistence for combo chips. */ 2928 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2929 athn_btcoex_enable(sc); 2930 #endif 2931 2932 ifp->if_flags &= ~IFF_OACTIVE; 2933 ifp->if_flags |= IFF_RUNNING; 2934 2935 #ifdef notyet 2936 if (ic->ic_flags & IEEE80211_F_WEPON) { 2937 /* Configure WEP keys. */ 2938 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2939 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2940 } 2941 #endif 2942 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2943 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2944 else 2945 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2946 2947 return 0; 2948 fail: 2949 athn_stop(ifp, 1); 2950 return error; 2951 } 2952 2953 PUBLIC void 2954 athn_stop(struct ifnet *ifp, int disable) 2955 { 2956 struct athn_softc *sc = ifp->if_softc; 2957 struct ieee80211com *ic = &sc->sc_ic; 2958 int qid; 2959 2960 ifp->if_timer = sc->sc_tx_timer = 0; 2961 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2962 2963 callout_stop(&sc->sc_scan_to); 2964 /* In case we were scanning, release the scan "lock". */ 2965 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2966 2967 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2968 2969 #ifdef ATHN_BT_COEXISTENCE 2970 /* Disable bluetooth coexistence for combo chips. */ 2971 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2972 athn_btcoex_disable(sc); 2973 #endif 2974 2975 /* Disable interrupts. */ 2976 athn_disable_interrupts(sc); 2977 /* Acknowledge interrupts (avoids interrupt storms). */ 2978 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2979 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2980 2981 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2982 athn_stop_tx_dma(sc, qid); 2983 /* XXX call athn_hw_reset if Tx still pending? */ 2984 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2985 athn_tx_reclaim(sc, qid); 2986 2987 /* Stop Rx. */ 2988 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2989 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2990 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2991 AR_WRITE(sc, AR_FILT_OFDM, 0); 2992 AR_WRITE(sc, AR_FILT_CCK, 0); 2993 AR_WRITE_BARRIER(sc); 2994 athn_set_rxfilter(sc, 0); 2995 athn_stop_rx_dma(sc); 2996 2997 athn_reset(sc, 0); 2998 athn_init_pll(sc, NULL); 2999 athn_set_power_awake(sc); 3000 athn_reset(sc, 1); 3001 athn_init_pll(sc, NULL); 3002 3003 athn_set_power_sleep(sc); 3004 3005 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3006 /* For CardBus, power down the socket. */ 3007 if (disable && sc->sc_disable != NULL) 3008 sc->sc_disable(sc); 3009 #endif 3010 if (disable) 3011 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3012 } 3013 3014 Static void 3015 athn_pmf_wlan_off(device_t self) 3016 { 3017 struct athn_softc *sc = device_private(self); 3018 struct ifnet *ifp = &sc->sc_if; 3019 3020 /* Turn the interface down. */ 3021 ifp->if_flags &= ~IFF_UP; 3022 athn_stop(ifp, 1); 3023 } 3024 3025 PUBLIC void 3026 athn_suspend(struct athn_softc *sc) 3027 { 3028 struct ifnet *ifp = &sc->sc_if; 3029 3030 if (ifp->if_flags & IFF_RUNNING) 3031 athn_stop(ifp, 1); 3032 } 3033 3034 PUBLIC bool 3035 athn_resume(struct athn_softc *sc) 3036 { 3037 struct ifnet *ifp = &sc->sc_if; 3038 3039 if (ifp->if_flags & IFF_UP) 3040 athn_init(ifp); 3041 3042 return true; 3043 } 3044
Indexes created Tue Oct 14 08:09:56 GMT 2025