athn.c revision 1.24
1 /* $NetBSD: athn.c,v 1.24 2020/11/15 12:33:53 mlelstv Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.24 2020/11/15 12:33:53 mlelstv Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 #endif /* notyet */ 140 Static void athn_set_multi(struct athn_softc *); 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } else { 253 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 254 athn_get_rf_name(sc)); 255 aprint_verbose_dev(sc->sc_dev, 256 "rev %d (%dT%dR), ROM rev %d, address %s\n", 257 sc->sc_mac_rev, 258 sc->sc_ntxchains, sc->sc_nrxchains, 259 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 260 } 261 262 callout_init(&sc->sc_scan_to, 0); 263 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 264 callout_init(&sc->sc_calib_to, 0); 265 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 266 267 sc->sc_amrr.amrr_min_success_threshold = 1; 268 sc->sc_amrr.amrr_max_success_threshold = 15; 269 270 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 271 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* Set device capabilities. */ 275 ic->ic_caps = 276 IEEE80211_C_WPA | /* 802.11i */ 277 #ifndef IEEE80211_STA_ONLY 278 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 279 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 280 #endif 281 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 282 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 283 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 284 IEEE80211_C_PMGT; /* Power saving supported. */ 285 286 #ifndef IEEE80211_NO_HT 287 if (sc->sc_flags & ATHN_FLAG_11N) { 288 int i, ntxstreams, nrxstreams; 289 290 /* Set HT capabilities. */ 291 ic->ic_htcaps = 292 IEEE80211_HTCAP_SMPS_DIS | 293 IEEE80211_HTCAP_CBW20_40 | 294 IEEE80211_HTCAP_SGI40 | 295 IEEE80211_HTCAP_DSSSCCK40; 296 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 297 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 298 if (AR_SREV_9380_10_OR_LATER(sc)) 299 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 300 if (AR_SREV_9280_10_OR_LATER(sc)) { 301 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 302 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 303 } 304 ntxstreams = sc->sc_ntxchains; 305 nrxstreams = sc->sc_nrxchains; 306 if (!AR_SREV_9380_10_OR_LATER(sc)) { 307 ntxstreams = MIN(ntxstreams, 2); 308 nrxstreams = MIN(nrxstreams, 2); 309 } 310 /* Set supported HT rates. */ 311 for (i = 0; i < nrxstreams; i++) 312 ic->ic_sup_mcs[i] = 0xff; 313 /* Set the "Tx MCS Set Defined" bit. */ 314 ic->ic_sup_mcs[12] |= 0x01; 315 if (ntxstreams != nrxstreams) { 316 /* Set "Tx Rx MCS Set Not Equal" bit. */ 317 ic->ic_sup_mcs[12] |= 0x02; 318 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 319 } 320 } 321 #endif 322 323 /* Set supported rates. */ 324 if (sc->sc_flags & ATHN_FLAG_11G) { 325 ic->ic_sup_rates[IEEE80211_MODE_11B] = 326 ieee80211_std_rateset_11b; 327 ic->ic_sup_rates[IEEE80211_MODE_11G] = 328 ieee80211_std_rateset_11g; 329 } 330 if (sc->sc_flags & ATHN_FLAG_11A) { 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 } 334 335 /* Get the list of authorized/supported channels. */ 336 athn_get_chanlist(sc); 337 338 ifp->if_softc = sc; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 if (!ifp->if_init) 341 ifp->if_init = athn_init; 342 if (!ifp->if_ioctl) 343 ifp->if_ioctl = athn_ioctl; 344 if (!ifp->if_start) 345 ifp->if_start = athn_start; 346 if (!ifp->if_watchdog) 347 ifp->if_watchdog = athn_watchdog; 348 IFQ_SET_READY(&ifp->if_snd); 349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 350 351 error = if_initialize(ifp); 352 if (error != 0) { 353 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 354 error); 355 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, 356 athn_pmf_wlan_off, false); 357 callout_destroy(&sc->sc_scan_to); 358 callout_destroy(&sc->sc_calib_to); 359 return error; 360 } 361 ieee80211_ifattach(ic); 362 /* Use common softint-based if_input */ 363 ifp->if_percpuq = if_percpuq_create(ifp); 364 if_register(ifp); 365 366 ic->ic_node_alloc = athn_node_alloc; 367 ic->ic_newassoc = athn_newassoc; 368 if (ic->ic_updateslot == NULL) 369 ic->ic_updateslot = athn_updateslot; 370 #ifdef notyet_edca 371 ic->ic_updateedca = athn_updateedca; 372 #endif 373 #ifdef notyet 374 ic->ic_set_key = athn_set_key; 375 ic->ic_delete_key = athn_delete_key; 376 #endif 377 378 /* Override 802.11 state transition machine. */ 379 sc->sc_newstate = ic->ic_newstate; 380 ic->ic_newstate = athn_newstate; 381 382 if (sc->sc_media_change == NULL) 383 sc->sc_media_change = athn_media_change; 384 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 385 386 athn_radiotap_attach(sc); 387 return 0; 388 } 389 390 PUBLIC void 391 athn_detach(struct athn_softc *sc) 392 { 393 struct ifnet *ifp = &sc->sc_if; 394 int qid; 395 396 callout_halt(&sc->sc_scan_to, NULL); 397 callout_halt(&sc->sc_calib_to, NULL); 398 399 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 400 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 401 athn_tx_reclaim(sc, qid); 402 403 /* Free Tx/Rx DMA resources. */ 404 sc->sc_ops.dma_free(sc); 405 406 if (sc->sc_soft_ih != NULL) { 407 softint_disestablish(sc->sc_soft_ih); 408 sc->sc_soft_ih = NULL; 409 } 410 } 411 /* Free ROM copy. */ 412 if (sc->sc_eep != NULL) { 413 free(sc->sc_eep, M_DEVBUF); 414 sc->sc_eep = NULL; 415 } 416 417 bpf_detach(ifp); 418 ieee80211_ifdetach(&sc->sc_ic); 419 if_detach(ifp); 420 421 callout_destroy(&sc->sc_scan_to); 422 callout_destroy(&sc->sc_calib_to); 423 424 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 425 false); 426 } 427 428 /* 429 * Attach the interface to 802.11 radiotap. 430 */ 431 Static void 432 athn_radiotap_attach(struct athn_softc *sc) 433 { 434 435 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 436 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 437 &sc->sc_drvbpf); 438 439 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 440 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 441 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 442 443 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 444 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 445 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 446 } 447 448 Static void 449 athn_get_chanlist(struct athn_softc *sc) 450 { 451 struct ieee80211com *ic = &sc->sc_ic; 452 uint8_t chan; 453 size_t i; 454 455 if (sc->sc_flags & ATHN_FLAG_11G) { 456 for (i = 1; i <= 14; i++) { 457 chan = i; 458 ic->ic_channels[chan].ic_freq = 459 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 460 ic->ic_channels[chan].ic_flags = 461 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 462 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 463 } 464 } 465 if (sc->sc_flags & ATHN_FLAG_11A) { 466 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 467 chan = athn_5ghz_chans[i]; 468 ic->ic_channels[chan].ic_freq = 469 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 470 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 471 } 472 } 473 } 474 475 PUBLIC void 476 athn_rx_start(struct athn_softc *sc) 477 { 478 struct ieee80211com *ic = &sc->sc_ic; 479 uint32_t rfilt; 480 481 /* Setup Rx DMA descriptors. */ 482 sc->sc_ops.rx_enable(sc); 483 484 /* Set Rx filter. */ 485 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 486 #ifndef IEEE80211_NO_HT 487 /* Want Compressed Block Ack Requests. */ 488 rfilt |= AR_RX_FILTER_COMPR_BAR; 489 #endif 490 rfilt |= AR_RX_FILTER_BEACON; 491 if (ic->ic_opmode != IEEE80211_M_STA) { 492 rfilt |= AR_RX_FILTER_PROBEREQ; 493 if (ic->ic_opmode == IEEE80211_M_MONITOR) 494 rfilt |= AR_RX_FILTER_PROM; 495 #ifndef IEEE80211_STA_ONLY 496 if (AR_SREV_9280_10_OR_LATER(sc) && 497 ic->ic_opmode == IEEE80211_M_HOSTAP) 498 rfilt |= AR_RX_FILTER_PSPOLL; 499 #endif 500 } 501 athn_set_rxfilter(sc, rfilt); 502 503 /* Set BSSID mask. */ 504 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 505 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 506 507 athn_set_opmode(sc); 508 509 /* Set multicast filter. */ 510 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 511 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 512 513 AR_WRITE(sc, AR_FILT_OFDM, 0); 514 AR_WRITE(sc, AR_FILT_CCK, 0); 515 AR_WRITE(sc, AR_MIBC, 0); 516 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 517 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 518 519 /* XXX ANI. */ 520 AR_WRITE(sc, AR_PHY_ERR_1, 0); 521 AR_WRITE(sc, AR_PHY_ERR_2, 0); 522 523 /* Disable HW crypto for now. */ 524 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 525 526 /* Start PCU Rx. */ 527 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 528 AR_WRITE_BARRIER(sc); 529 } 530 531 PUBLIC void 532 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 533 { 534 535 AR_WRITE(sc, AR_RX_FILTER, rfilt); 536 #ifdef notyet 537 reg = AR_READ(sc, AR_PHY_ERR); 538 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 539 AR_PHY_ERR_CCK_TIMING); 540 AR_WRITE(sc, AR_PHY_ERR, reg); 541 if (reg != 0) 542 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 543 else 544 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 545 #else 546 AR_WRITE(sc, AR_PHY_ERR, 0); 547 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 548 #endif 549 AR_WRITE_BARRIER(sc); 550 } 551 552 PUBLIC int 553 athn_intr(void *xsc) 554 { 555 struct athn_softc *sc = xsc; 556 struct ifnet *ifp = &sc->sc_if; 557 558 if (!IS_UP_AND_RUNNING(ifp)) 559 return 0; 560 561 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 562 /* 563 * The hardware is not ready/present, don't touch anything. 564 * Note this can happen early on if the IRQ is shared. 565 */ 566 return 0; 567 568 if (!sc->sc_ops.intr_status(sc)) 569 return 0; 570 571 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 572 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 573 AR_WRITE_BARRIER(sc); 574 575 softint_schedule(sc->sc_soft_ih); 576 577 return 1; 578 } 579 580 Static void 581 athn_softintr(void *xsc) 582 { 583 struct athn_softc *sc = xsc; 584 struct ifnet *ifp = &sc->sc_if; 585 586 if (!IS_UP_AND_RUNNING(ifp)) 587 return; 588 589 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 590 /* 591 * The hardware is not ready/present, don't touch anything. 592 * Note this can happen early on if the IRQ is shared. 593 */ 594 return; 595 596 sc->sc_ops.intr(sc); 597 598 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 599 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 600 AR_WRITE_BARRIER(sc); 601 } 602 603 Static void 604 athn_get_chipid(struct athn_softc *sc) 605 { 606 uint32_t reg; 607 608 reg = AR_READ(sc, AR_SREV); 609 if (MS(reg, AR_SREV_ID) == 0xff) { 610 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 611 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 612 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 613 sc->sc_flags |= ATHN_FLAG_PCIE; 614 } else { 615 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 616 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 617 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 618 sc->sc_flags |= ATHN_FLAG_PCIE; 619 } 620 } 621 622 Static const char * 623 athn_get_mac_name(struct athn_softc *sc) 624 { 625 626 switch (sc->sc_mac_ver) { 627 case AR_SREV_VERSION_5416_PCI: 628 return "AR5416"; 629 case AR_SREV_VERSION_5416_PCIE: 630 return "AR5418"; 631 case AR_SREV_VERSION_9160: 632 return "AR9160"; 633 case AR_SREV_VERSION_9280: 634 return "AR9280"; 635 case AR_SREV_VERSION_9285: 636 return "AR9285"; 637 case AR_SREV_VERSION_9271: 638 return "AR9271"; 639 case AR_SREV_VERSION_9287: 640 return "AR9287"; 641 case AR_SREV_VERSION_9380: 642 return "AR9380"; 643 case AR_SREV_VERSION_9485: 644 return "AR9485"; 645 default: 646 return "unknown"; 647 } 648 } 649 650 /* 651 * Return RF chip name (not for single-chip solutions). 652 */ 653 Static const char * 654 athn_get_rf_name(struct athn_softc *sc) 655 { 656 657 KASSERT(!AR_SINGLE_CHIP(sc)); 658 659 switch (sc->sc_rf_rev) { 660 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 661 return "AR5133"; 662 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 663 return "AR2133"; 664 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 665 return "AR5122"; 666 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 667 return "AR2122"; 668 default: 669 return "unknown"; 670 } 671 } 672 673 PUBLIC int 674 athn_reset_power_on(struct athn_softc *sc) 675 { 676 int ntries; 677 678 /* Set force wake. */ 679 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 680 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 681 682 if (!AR_SREV_9380_10_OR_LATER(sc)) { 683 /* Make sure no DMA is active by doing an AHB reset. */ 684 AR_WRITE(sc, AR_RC, AR_RC_AHB); 685 } 686 /* RTC reset and clear. */ 687 AR_WRITE(sc, AR_RTC_RESET, 0); 688 AR_WRITE_BARRIER(sc); 689 DELAY(2); 690 if (!AR_SREV_9380_10_OR_LATER(sc)) 691 AR_WRITE(sc, AR_RC, 0); 692 AR_WRITE(sc, AR_RTC_RESET, 1); 693 694 /* Poll until RTC is ON. */ 695 for (ntries = 0; ntries < 1000; ntries++) { 696 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 697 AR_RTC_STATUS_ON) 698 break; 699 DELAY(10); 700 } 701 if (ntries == 1000) { 702 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 703 return ETIMEDOUT; 704 } 705 return athn_reset(sc, 0); 706 } 707 708 PUBLIC int 709 athn_reset(struct athn_softc *sc, int cold_reset) 710 { 711 int ntries; 712 713 /* Set force wake. */ 714 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 715 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 716 717 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 718 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 719 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 720 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 721 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 722 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 723 AR_WRITE(sc, AR_RC, AR_RC_AHB); 724 725 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 726 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 727 AR_WRITE_BARRIER(sc); 728 DELAY(50); 729 AR_WRITE(sc, AR_RTC_RC, 0); 730 for (ntries = 0; ntries < 1000; ntries++) { 731 if (!(AR_READ(sc, AR_RTC_RC) & 732 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 733 break; 734 DELAY(10); 735 } 736 if (ntries == 1000) { 737 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 738 return ETIMEDOUT; 739 } 740 AR_WRITE(sc, AR_RC, 0); 741 AR_WRITE_BARRIER(sc); 742 return 0; 743 } 744 745 PUBLIC int 746 athn_set_power_awake(struct athn_softc *sc) 747 { 748 int ntries, error; 749 750 /* Do a Power-On-Reset if shutdown. */ 751 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 752 AR_RTC_STATUS_SHUTDOWN) { 753 if ((error = athn_reset_power_on(sc)) != 0) 754 return error; 755 if (!AR_SREV_9380_10_OR_LATER(sc)) 756 athn_init_pll(sc, NULL); 757 } 758 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 759 AR_WRITE_BARRIER(sc); 760 DELAY(50); /* Give chip the chance to awake. */ 761 762 /* Poll until RTC is ON. */ 763 for (ntries = 0; ntries < 4000; ntries++) { 764 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 765 AR_RTC_STATUS_ON) 766 break; 767 DELAY(50); 768 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 769 } 770 if (ntries == 4000) { 771 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 772 return ETIMEDOUT; 773 } 774 775 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 776 AR_WRITE_BARRIER(sc); 777 return 0; 778 } 779 780 PUBLIC void 781 athn_set_power_sleep(struct athn_softc *sc) 782 { 783 784 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 785 /* Allow the MAC to go to sleep. */ 786 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 787 if (!AR_SREV_9380_10_OR_LATER(sc)) 788 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 789 /* 790 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 791 * results in high power consumption on AR5416 chipsets. 792 */ 793 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 794 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 795 AR_WRITE_BARRIER(sc); 796 } 797 798 PUBLIC void 799 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 800 { 801 uint32_t pll; 802 803 if (AR_SREV_9380_10_OR_LATER(sc)) { 804 if (AR_SREV_9485(sc)) 805 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 806 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 807 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 808 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 809 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 810 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 811 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 812 pll = 0x142c; 813 else if (AR_SREV_9280_20(sc)) 814 pll = 0x2850; 815 else 816 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 817 } else 818 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 819 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 820 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 821 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 822 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 823 else 824 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 825 } else { 826 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 827 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 828 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 829 else 830 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 831 } 832 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 833 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 834 if (AR_SREV_9271(sc)) { 835 /* Switch core clock to 117MHz. */ 836 AR_WRITE_BARRIER(sc); 837 DELAY(500); 838 AR_WRITE(sc, 0x50050, 0x304); 839 } 840 AR_WRITE_BARRIER(sc); 841 DELAY(100); 842 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 843 AR_WRITE_BARRIER(sc); 844 } 845 846 Static void 847 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 848 { 849 int i; 850 851 /* Write sequence to Serializer/Deserializer. */ 852 for (i = 0; i < serdes->nvals; i++) 853 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 854 AR_WRITE_BARRIER(sc); 855 } 856 857 PUBLIC void 858 athn_config_pcie(struct athn_softc *sc) 859 { 860 861 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 862 athn_write_serdes(sc, sc->sc_serdes); 863 864 DELAY(1000); 865 /* Allow forcing of PCIe core into L1 state. */ 866 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 867 868 #ifndef ATHN_PCIE_WAEN 869 AR_WRITE(sc, AR_WA, sc->sc_workaround); 870 #else 871 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 872 #endif 873 AR_WRITE_BARRIER(sc); 874 } 875 876 /* 877 * Serializer/Deserializer programming for non-PCIe devices. 878 */ 879 static const uint32_t ar_nonpcie_serdes_regs[] = { 880 AR_PCIE_SERDES, 881 AR_PCIE_SERDES, 882 AR_PCIE_SERDES, 883 AR_PCIE_SERDES, 884 AR_PCIE_SERDES, 885 AR_PCIE_SERDES, 886 AR_PCIE_SERDES, 887 AR_PCIE_SERDES, 888 AR_PCIE_SERDES, 889 AR_PCIE_SERDES2, 890 }; 891 892 static const uint32_t ar_nonpcie_serdes_vals[] = { 893 0x9248fc00, 894 0x24924924, 895 0x28000029, 896 0x57160824, 897 0x25980579, 898 0x00000000, 899 0x1aaabe40, 900 0xbe105554, 901 0x000e1007, 902 0x00000000 903 }; 904 905 static const struct athn_serdes ar_nonpcie_serdes = { 906 __arraycount(ar_nonpcie_serdes_vals), 907 ar_nonpcie_serdes_regs, 908 ar_nonpcie_serdes_vals 909 }; 910 911 PUBLIC void 912 athn_config_nonpcie(struct athn_softc *sc) 913 { 914 915 athn_write_serdes(sc, &ar_nonpcie_serdes); 916 } 917 918 PUBLIC int 919 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 920 struct ieee80211_channel *extchan) 921 { 922 struct athn_ops *ops = &sc->sc_ops; 923 int error, qid; 924 925 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 926 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 927 if (athn_tx_pending(sc, qid)) 928 return EBUSY; 929 930 /* Request RF Bus grant. */ 931 if ((error = ops->rf_bus_request(sc)) != 0) 932 return error; 933 934 ops->set_phy(sc, curchan, extchan); 935 936 /* Change the synthesizer. */ 937 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 938 return error; 939 940 sc->sc_curchan = curchan; 941 sc->sc_curchanext = extchan; 942 943 /* Set transmit power values for new channel. */ 944 ops->set_txpower(sc, curchan, extchan); 945 946 /* Release the RF Bus grant. */ 947 ops->rf_bus_release(sc); 948 949 /* Write delta slope coeffs for modes where OFDM may be used. */ 950 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 951 ops->set_delta_slope(sc, curchan, extchan); 952 953 ops->spur_mitigate(sc, curchan, extchan); 954 /* XXX Load noisefloor values and start calibration. */ 955 956 return 0; 957 } 958 959 Static int 960 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 961 struct ieee80211_channel *extchan) 962 { 963 int error, qid; 964 965 /* Disable interrupts. */ 966 athn_disable_interrupts(sc); 967 968 /* Stop all Tx queues. */ 969 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 970 athn_stop_tx_dma(sc, qid); 971 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 972 athn_tx_reclaim(sc, qid); 973 974 /* Stop Rx. */ 975 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 976 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 977 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 978 AR_WRITE(sc, AR_FILT_OFDM, 0); 979 AR_WRITE(sc, AR_FILT_CCK, 0); 980 athn_set_rxfilter(sc, 0); 981 error = athn_stop_rx_dma(sc); 982 if (error != 0) 983 goto reset; 984 985 #ifdef notyet 986 /* AR9280 needs a full reset. */ 987 if (AR_SREV_9280(sc)) 988 #endif 989 goto reset; 990 991 /* If band or bandwidth changes, we need to do a full reset. */ 992 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 993 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 994 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 995 goto reset; 996 } 997 error = athn_set_power_awake(sc); 998 if (error != 0) 999 goto reset; 1000 1001 error = athn_set_chan(sc, curchan, extchan); 1002 if (error != 0) { 1003 reset: /* Error found, try a full reset. */ 1004 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 1005 error = athn_hw_reset(sc, curchan, extchan, 0); 1006 if (error != 0) /* Hopeless case. */ 1007 return error; 1008 } 1009 athn_rx_start(sc); 1010 1011 /* Re-enable interrupts. */ 1012 athn_enable_interrupts(sc); 1013 return 0; 1014 } 1015 1016 PUBLIC void 1017 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1018 { 1019 #define COEFF_SCALE_SHIFT 24 1020 uint32_t exp, man; 1021 1022 /* exponent = 14 - floor(log2(coeff)) */ 1023 for (exp = 31; exp > 0; exp--) 1024 if (coeff & (1U << exp)) 1025 break; 1026 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1027 1028 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1029 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1030 1031 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1032 *exponent = exp - 16; 1033 #undef COEFF_SCALE_SHIFT 1034 } 1035 1036 PUBLIC void 1037 athn_reset_key(struct athn_softc *sc, int entry) 1038 { 1039 1040 /* 1041 * NB: Key cache registers access special memory area that requires 1042 * two 32-bit writes to actually update the values in the internal 1043 * memory. Consequently, writes must be grouped by pair. 1044 */ 1045 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1046 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1047 1048 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1049 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1050 1051 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1052 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1053 1054 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1055 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1056 1057 AR_WRITE_BARRIER(sc); 1058 } 1059 1060 #ifdef notyet 1061 Static int 1062 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1063 struct ieee80211_key *k) 1064 { 1065 struct athn_softc *sc = ic->ic_ifp->if_softc; 1066 const uint8_t *txmic, *rxmic, *key, *addr; 1067 uintptr_t entry, micentry; 1068 uint32_t type, lo, hi; 1069 1070 switch (k->k_cipher) { 1071 case IEEE80211_CIPHER_WEP40: 1072 type = AR_KEYTABLE_TYPE_40; 1073 break; 1074 case IEEE80211_CIPHER_WEP104: 1075 type = AR_KEYTABLE_TYPE_104; 1076 break; 1077 case IEEE80211_CIPHER_TKIP: 1078 type = AR_KEYTABLE_TYPE_TKIP; 1079 break; 1080 case IEEE80211_CIPHER_CCMP: 1081 type = AR_KEYTABLE_TYPE_CCM; 1082 break; 1083 default: 1084 /* Fallback to software crypto for other ciphers. */ 1085 return ieee80211_set_key(ic, ni, k); 1086 } 1087 1088 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1089 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1090 else 1091 entry = k->k_id; 1092 k->k_priv = (void *)entry; 1093 1094 /* NB: See note about key cache registers access above. */ 1095 key = k->k_key; 1096 if (type == AR_KEYTABLE_TYPE_TKIP) { 1097 #ifndef IEEE80211_STA_ONLY 1098 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1099 txmic = &key[16]; 1100 rxmic = &key[24]; 1101 } else 1102 #endif 1103 { 1104 rxmic = &key[16]; 1105 txmic = &key[24]; 1106 } 1107 /* Tx+Rx MIC key is at entry + 64. */ 1108 micentry = entry + 64; 1109 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1110 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1111 1112 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1113 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1114 1115 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1116 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1117 } 1118 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1119 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1120 1121 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1122 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1123 1124 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1125 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1126 1127 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1128 addr = ni->ni_macaddr; 1129 lo = LE_READ_4(&addr[0]); 1130 hi = LE_READ_2(&addr[4]); 1131 lo = lo >> 1 | hi << 31; 1132 hi = hi >> 1; 1133 } else 1134 lo = hi = 0; 1135 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1136 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1137 AR_WRITE_BARRIER(sc); 1138 return 0; 1139 } 1140 1141 Static void 1142 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1143 struct ieee80211_key *k) 1144 { 1145 struct athn_softc *sc = ic->ic_ifp->if_softc; 1146 uintptr_t entry; 1147 1148 switch (k->k_cipher) { 1149 case IEEE80211_CIPHER_WEP40: 1150 case IEEE80211_CIPHER_WEP104: 1151 case IEEE80211_CIPHER_CCMP: 1152 entry = (uintptr_t)k->k_priv; 1153 athn_reset_key(sc, entry); 1154 break; 1155 case IEEE80211_CIPHER_TKIP: 1156 entry = (uintptr_t)k->k_priv; 1157 athn_reset_key(sc, entry); 1158 athn_reset_key(sc, entry + 64); 1159 break; 1160 default: 1161 /* Fallback to software crypto for other ciphers. */ 1162 ieee80211_delete_key(ic, ni, k); 1163 } 1164 } 1165 #endif /* notyet */ 1166 1167 PUBLIC void 1168 athn_led_init(struct athn_softc *sc) 1169 { 1170 struct athn_ops *ops = &sc->sc_ops; 1171 1172 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1173 /* LED off, active low. */ 1174 athn_set_led(sc, 0); 1175 } 1176 1177 PUBLIC void 1178 athn_set_led(struct athn_softc *sc, int on) 1179 { 1180 struct athn_ops *ops = &sc->sc_ops; 1181 1182 sc->sc_led_state = on; 1183 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1184 } 1185 1186 #ifdef ATHN_BT_COEXISTENCE 1187 Static void 1188 athn_btcoex_init(struct athn_softc *sc) 1189 { 1190 struct athn_ops *ops = &sc->sc_ops; 1191 uint32_t reg; 1192 1193 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1194 /* Connect bt_active to baseband. */ 1195 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1196 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1197 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1198 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1199 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1200 1201 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1202 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1203 AR_GPIO_BTACTIVE_PIN); 1204 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1205 AR_WRITE_BARRIER(sc); 1206 1207 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1208 } else { /* 3-wire. */ 1209 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1210 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1211 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1212 1213 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1214 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1215 AR_GPIO_BTACTIVE_PIN); 1216 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1217 AR_GPIO_BTPRIORITY_PIN); 1218 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1219 AR_WRITE_BARRIER(sc); 1220 1221 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1222 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1223 } 1224 } 1225 1226 Static void 1227 athn_btcoex_enable(struct athn_softc *sc) 1228 { 1229 struct athn_ops *ops = &sc->sc_ops; 1230 uint32_t reg; 1231 1232 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1233 AR_WRITE(sc, AR_BT_COEX_MODE, 1234 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1235 SM(AR_BT_PRIORITY_TIME, 2) | 1236 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1237 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1238 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1239 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1240 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1241 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1242 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1243 AR_WRITE(sc, AR_BT_COEX_MODE2, 1244 SM(AR_BT_BCN_MISS_THRESH, 50) | 1245 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1246 1247 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1248 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1249 AR_WRITE_BARRIER(sc); 1250 1251 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1252 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1253 1254 } else { /* 2-wire. */ 1255 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1256 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1257 } 1258 reg = AR_READ(sc, AR_GPIO_PDPU); 1259 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1260 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1261 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1262 AR_WRITE_BARRIER(sc); 1263 1264 /* Disable PCIe Active State Power Management (ASPM). */ 1265 if (sc->sc_disable_aspm != NULL) 1266 sc->sc_disable_aspm(sc); 1267 1268 /* XXX Start periodic timer. */ 1269 } 1270 1271 Static void 1272 athn_btcoex_disable(struct athn_softc *sc) 1273 { 1274 struct athn_ops *ops = &sc->sc_ops; 1275 1276 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1277 1278 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1279 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1280 1281 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1282 AR_WRITE(sc, AR_BT_COEX_MODE, 1283 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1284 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1285 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1286 /* XXX Stop periodic timer. */ 1287 } 1288 AR_WRITE_BARRIER(sc); 1289 /* XXX Restore ASPM setting? */ 1290 } 1291 #endif 1292 1293 Static void 1294 athn_iter_func(void *arg, struct ieee80211_node *ni) 1295 { 1296 struct athn_softc *sc = arg; 1297 struct athn_node *an = (struct athn_node *)ni; 1298 1299 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1300 } 1301 1302 Static void 1303 athn_calib_to(void *arg) 1304 { 1305 extern int ticks; 1306 struct athn_softc *sc = arg; 1307 struct athn_ops *ops = &sc->sc_ops; 1308 struct ieee80211com *ic = &sc->sc_ic; 1309 int s; 1310 1311 s = splnet(); 1312 1313 /* Do periodic (every 4 minutes) PA calibration. */ 1314 if (AR_SREV_9285_11_OR_LATER(sc) && 1315 !AR_SREV_9380_10_OR_LATER(sc) && 1316 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1317 sc->sc_pa_calib_ticks = ticks; 1318 if (AR_SREV_9271(sc)) 1319 ar9271_pa_calib(sc); 1320 else 1321 ar9285_pa_calib(sc); 1322 } 1323 1324 /* Do periodic (every 30 seconds) temperature compensation. */ 1325 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1326 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1327 sc->sc_olpc_ticks = ticks; 1328 ops->olpc_temp_compensation(sc); 1329 } 1330 1331 #ifdef notyet 1332 /* XXX ANI. */ 1333 athn_ani_monitor(sc); 1334 1335 ops->next_calib(sc); 1336 #endif 1337 if (ic->ic_fixed_rate == -1) { 1338 if (ic->ic_opmode == IEEE80211_M_STA) 1339 athn_iter_func(sc, ic->ic_bss); 1340 else 1341 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1342 } 1343 callout_schedule(&sc->sc_calib_to, hz / 2); 1344 splx(s); 1345 } 1346 1347 Static int 1348 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1349 struct ieee80211_channel *extchan) 1350 { 1351 struct athn_ops *ops = &sc->sc_ops; 1352 int error; 1353 1354 if (AR_SREV_9380_10_OR_LATER(sc)) 1355 error = ar9003_init_calib(sc); 1356 else if (AR_SREV_9285_10_OR_LATER(sc)) 1357 error = ar9285_init_calib(sc, curchan, extchan); 1358 else 1359 error = ar5416_init_calib(sc, curchan, extchan); 1360 if (error != 0) 1361 return error; 1362 1363 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1364 /* Do PA calibration. */ 1365 if (AR_SREV_9285_11_OR_LATER(sc)) { 1366 extern int ticks; 1367 sc->sc_pa_calib_ticks = ticks; 1368 if (AR_SREV_9271(sc)) 1369 ar9271_pa_calib(sc); 1370 else 1371 ar9285_pa_calib(sc); 1372 } 1373 /* Do noisefloor calibration. */ 1374 ops->noisefloor_calib(sc); 1375 } 1376 if (AR_SREV_9160_10_OR_LATER(sc)) { 1377 /* Support IQ calibration. */ 1378 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1379 if (AR_SREV_9380_10_OR_LATER(sc)) { 1380 /* Support temperature compensation calibration. */ 1381 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1382 } else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1383 /* 1384 * ADC gain calibration causes uplink throughput 1385 * drops in HT40 mode on AR9287. 1386 */ 1387 if (!AR_SREV_9287(sc)) { 1388 /* Support ADC gain calibration. */ 1389 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1390 } 1391 /* Support ADC DC offset calibration. */ 1392 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1393 } 1394 } 1395 return 0; 1396 } 1397 1398 /* 1399 * Adaptive noise immunity. 1400 */ 1401 #ifdef notyet 1402 Static int32_t 1403 athn_ani_get_rssi(struct athn_softc *sc) 1404 { 1405 1406 return 0; /* XXX */ 1407 } 1408 #endif /* notyet */ 1409 1410 #ifdef notyet 1411 Static void 1412 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1413 { 1414 struct athn_ani *ani = &sc->sc_ani; 1415 struct athn_ops *ops = &sc->sc_ops; 1416 int32_t rssi; 1417 1418 /* First, raise noise immunity level, up to max. */ 1419 if (ani->noise_immunity_level < 4) { 1420 ani->noise_immunity_level++; 1421 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1422 return; 1423 } 1424 1425 /* Then, raise our spur immunity level, up to max. */ 1426 if (ani->spur_immunity_level < 7) { 1427 ani->spur_immunity_level++; 1428 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1429 return; 1430 } 1431 1432 #ifndef IEEE80211_STA_ONLY 1433 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1434 if (ani->firstep_level < 2) { 1435 ani->firstep_level++; 1436 ops->set_firstep_level(sc, ani->firstep_level); 1437 } 1438 return; 1439 } 1440 #endif 1441 rssi = athn_ani_get_rssi(sc); 1442 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1443 /* 1444 * Beacon RSSI is high, turn off OFDM weak signal detection 1445 * or raise first step level as last resort. 1446 */ 1447 if (ani->ofdm_weak_signal) { 1448 ani->ofdm_weak_signal = 0; 1449 ops->disable_ofdm_weak_signal(sc); 1450 ani->spur_immunity_level = 0; 1451 ops->set_spur_immunity_level(sc, 0); 1452 } else if (ani->firstep_level < 2) { 1453 ani->firstep_level++; 1454 ops->set_firstep_level(sc, ani->firstep_level); 1455 } 1456 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1457 /* 1458 * Beacon RSSI is in mid range, we need OFDM weak signal 1459 * detection but we can raise first step level. 1460 */ 1461 if (!ani->ofdm_weak_signal) { 1462 ani->ofdm_weak_signal = 1; 1463 ops->enable_ofdm_weak_signal(sc); 1464 } 1465 if (ani->firstep_level < 2) { 1466 ani->firstep_level++; 1467 ops->set_firstep_level(sc, ani->firstep_level); 1468 } 1469 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1470 /* 1471 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1472 * signal detection and zero first step level to maximize 1473 * CCK sensitivity. 1474 */ 1475 if (ani->ofdm_weak_signal) { 1476 ani->ofdm_weak_signal = 0; 1477 ops->disable_ofdm_weak_signal(sc); 1478 } 1479 if (ani->firstep_level > 0) { 1480 ani->firstep_level = 0; 1481 ops->set_firstep_level(sc, 0); 1482 } 1483 } 1484 } 1485 #endif /* notyet */ 1486 1487 #ifdef notyet 1488 Static void 1489 athn_ani_cck_err_trigger(struct athn_softc *sc) 1490 { 1491 struct athn_ani *ani = &sc->sc_ani; 1492 struct athn_ops *ops = &sc->sc_ops; 1493 int32_t rssi; 1494 1495 /* Raise noise immunity level, up to max. */ 1496 if (ani->noise_immunity_level < 4) { 1497 ani->noise_immunity_level++; 1498 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1499 return; 1500 } 1501 1502 #ifndef IEEE80211_STA_ONLY 1503 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1504 if (ani->firstep_level < 2) { 1505 ani->firstep_level++; 1506 ops->set_firstep_level(sc, ani->firstep_level); 1507 } 1508 return; 1509 } 1510 #endif 1511 rssi = athn_ani_get_rssi(sc); 1512 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1513 /* 1514 * Beacon RSSI is in mid or high range, raise first step 1515 * level. 1516 */ 1517 if (ani->firstep_level < 2) { 1518 ani->firstep_level++; 1519 ops->set_firstep_level(sc, ani->firstep_level); 1520 } 1521 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1522 /* 1523 * Beacon RSSI is low, zero first step level to maximize 1524 * CCK sensitivity. 1525 */ 1526 if (ani->firstep_level > 0) { 1527 ani->firstep_level = 0; 1528 ops->set_firstep_level(sc, 0); 1529 } 1530 } 1531 } 1532 #endif /* notyet */ 1533 1534 #ifdef notyet 1535 Static void 1536 athn_ani_lower_immunity(struct athn_softc *sc) 1537 { 1538 struct athn_ani *ani = &sc->sc_ani; 1539 struct athn_ops *ops = &sc->sc_ops; 1540 int32_t rssi; 1541 1542 #ifndef IEEE80211_STA_ONLY 1543 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1544 if (ani->firstep_level > 0) { 1545 ani->firstep_level--; 1546 ops->set_firstep_level(sc, ani->firstep_level); 1547 } 1548 return; 1549 } 1550 #endif 1551 rssi = athn_ani_get_rssi(sc); 1552 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1553 /* 1554 * Beacon RSSI is high, leave OFDM weak signal detection 1555 * off or it may oscillate. 1556 */ 1557 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1558 /* 1559 * Beacon RSSI is in mid range, turn on OFDM weak signal 1560 * detection or lower first step level. 1561 */ 1562 if (!ani->ofdm_weak_signal) { 1563 ani->ofdm_weak_signal = 1; 1564 ops->enable_ofdm_weak_signal(sc); 1565 return; 1566 } 1567 if (ani->firstep_level > 0) { 1568 ani->firstep_level--; 1569 ops->set_firstep_level(sc, ani->firstep_level); 1570 return; 1571 } 1572 } else { 1573 /* Beacon RSSI is low, lower first step level. */ 1574 if (ani->firstep_level > 0) { 1575 ani->firstep_level--; 1576 ops->set_firstep_level(sc, ani->firstep_level); 1577 return; 1578 } 1579 } 1580 /* 1581 * Lower spur immunity level down to zero, or if all else fails, 1582 * lower noise immunity level down to zero. 1583 */ 1584 if (ani->spur_immunity_level > 0) { 1585 ani->spur_immunity_level--; 1586 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1587 } else if (ani->noise_immunity_level > 0) { 1588 ani->noise_immunity_level--; 1589 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1590 } 1591 } 1592 #endif /* notyet */ 1593 1594 #ifdef notyet 1595 Static void 1596 athn_ani_restart(struct athn_softc *sc) 1597 { 1598 struct athn_ani *ani = &sc->sc_ani; 1599 1600 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1601 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1602 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1603 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1604 AR_WRITE_BARRIER(sc); 1605 1606 ani->listen_time = 0; 1607 ani->ofdm_phy_err_count = 0; 1608 ani->cck_phy_err_count = 0; 1609 } 1610 #endif /* notyet */ 1611 1612 #ifdef notyet 1613 Static void 1614 athn_ani_monitor(struct athn_softc *sc) 1615 { 1616 struct athn_ani *ani = &sc->sc_ani; 1617 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1618 int32_t cycdelta, txfdelta, rxfdelta; 1619 int32_t listen_time; 1620 1621 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1622 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1623 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1624 1625 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1626 cycdelta = cyccnt - ani->cyccnt; 1627 txfdelta = txfcnt - ani->txfcnt; 1628 rxfdelta = rxfcnt - ani->rxfcnt; 1629 1630 listen_time = (cycdelta - txfdelta - rxfdelta) / 1631 (athn_clock_rate(sc) * 1000); 1632 } else 1633 listen_time = 0; 1634 1635 ani->cyccnt = cyccnt; 1636 ani->txfcnt = txfcnt; 1637 ani->rxfcnt = rxfcnt; 1638 1639 if (listen_time < 0) { 1640 athn_ani_restart(sc); 1641 return; 1642 } 1643 ani->listen_time += listen_time; 1644 1645 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1646 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1647 1648 if (phy1 < ani->ofdm_phy_err_base) { 1649 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1650 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1651 } 1652 if (phy2 < ani->cck_phy_err_base) { 1653 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1654 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1655 } 1656 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1657 AR_WRITE_BARRIER(sc); 1658 return; 1659 } 1660 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1661 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1662 1663 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1664 /* Check to see if we need to lower immunity. */ 1665 if (ani->ofdm_phy_err_count <= 1666 ani->listen_time * ani->ofdm_trig_low / 1000 && 1667 ani->cck_phy_err_count <= 1668 ani->listen_time * ani->cck_trig_low / 1000) 1669 athn_ani_lower_immunity(sc); 1670 athn_ani_restart(sc); 1671 1672 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1673 /* Check to see if we need to raise immunity. */ 1674 if (ani->ofdm_phy_err_count > 1675 ani->listen_time * ani->ofdm_trig_high / 1000) { 1676 athn_ani_ofdm_err_trigger(sc); 1677 athn_ani_restart(sc); 1678 } else if (ani->cck_phy_err_count > 1679 ani->listen_time * ani->cck_trig_high / 1000) { 1680 athn_ani_cck_err_trigger(sc); 1681 athn_ani_restart(sc); 1682 } 1683 } 1684 } 1685 #endif /* notyet */ 1686 1687 PUBLIC uint8_t 1688 athn_chan2fbin(struct ieee80211_channel *c) 1689 { 1690 1691 if (IEEE80211_IS_CHAN_2GHZ(c)) 1692 return c->ic_freq - 2300; 1693 else 1694 return (c->ic_freq - 4800) / 5; 1695 } 1696 1697 PUBLIC int 1698 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1699 { 1700 1701 if (x1 == x2) /* Prevents division by zero. */ 1702 return y1; 1703 /* Linear interpolation. */ 1704 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1705 } 1706 1707 PUBLIC void 1708 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1709 int *lo, int *hi) 1710 { 1711 int i; 1712 1713 for (i = 0; i < npiers; i++) 1714 if (pierfreq[i] == AR_BCHAN_UNUSED || 1715 pierfreq[i] > fbin) 1716 break; 1717 *hi = i; 1718 *lo = *hi - 1; 1719 if (*lo == -1) 1720 *lo = *hi; 1721 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1722 *hi = *lo; 1723 } 1724 1725 Static void 1726 athn_init_dma(struct athn_softc *sc) 1727 { 1728 uint32_t reg; 1729 1730 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1731 /* Set AHB not to do cacheline prefetches. */ 1732 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1733 } 1734 reg = AR_READ(sc, AR_TXCFG); 1735 /* Let MAC DMA reads be in 128-byte chunks. */ 1736 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1737 1738 /* Set initial Tx trigger level. */ 1739 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1740 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1741 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1742 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1743 AR_WRITE(sc, AR_TXCFG, reg); 1744 1745 /* Let MAC DMA writes be in 128-byte chunks. */ 1746 reg = AR_READ(sc, AR_RXCFG); 1747 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1748 AR_WRITE(sc, AR_RXCFG, reg); 1749 1750 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1751 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1752 1753 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1754 if (AR_SREV_9285(sc)) { 1755 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1756 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1757 } else if (!AR_SREV_9271(sc)) { 1758 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1759 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1760 } 1761 AR_WRITE_BARRIER(sc); 1762 1763 /* Reset Tx status ring. */ 1764 if (AR_SREV_9380_10_OR_LATER(sc)) 1765 ar9003_reset_txsring(sc); 1766 } 1767 1768 PUBLIC void 1769 athn_inc_tx_trigger_level(struct athn_softc *sc) 1770 { 1771 uint32_t reg, ftrig; 1772 1773 reg = AR_READ(sc, AR_TXCFG); 1774 ftrig = MS(reg, AR_TXCFG_FTRIG); 1775 /* 1776 * NB: The AR9285 and all single-stream parts have an issue that 1777 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1778 */ 1779 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1780 return; /* Already at max. */ 1781 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1782 AR_WRITE(sc, AR_TXCFG, reg); 1783 AR_WRITE_BARRIER(sc); 1784 } 1785 1786 PUBLIC int 1787 athn_stop_rx_dma(struct athn_softc *sc) 1788 { 1789 int ntries; 1790 1791 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1792 /* Wait for Rx enable bit to go low. */ 1793 for (ntries = 0; ntries < 100; ntries++) { 1794 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1795 return 0; 1796 DELAY(100); 1797 } 1798 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1799 return ETIMEDOUT; 1800 } 1801 1802 #ifdef unused 1803 Static int 1804 athn_rx_abort(struct athn_softc *sc) 1805 { 1806 int ntries; 1807 1808 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1809 for (ntries = 0; ntries < 1000; ntries++) { 1810 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1811 return 0; 1812 DELAY(10); 1813 } 1814 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1815 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1816 AR_WRITE_BARRIER(sc); 1817 return ETIMEDOUT; 1818 } 1819 #endif /* unused */ 1820 1821 Static void 1822 athn_tx_reclaim(struct athn_softc *sc, int qid) 1823 { 1824 struct athn_txq *txq = &sc->sc_txq[qid]; 1825 struct athn_tx_buf *bf; 1826 1827 /* Reclaim all buffers queued in the specified Tx queue. */ 1828 /* NB: Tx DMA must be stopped. */ 1829 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1830 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1831 1832 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1833 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1834 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1835 m_freem(bf->bf_m); 1836 bf->bf_m = NULL; 1837 bf->bf_ni = NULL; /* Nodes already freed! */ 1838 1839 /* Link Tx buffer back to global free list. */ 1840 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1841 } 1842 } 1843 1844 PUBLIC int 1845 athn_tx_pending(struct athn_softc *sc, int qid) 1846 { 1847 1848 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1849 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1850 } 1851 1852 PUBLIC void 1853 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1854 { 1855 uint32_t tsflo; 1856 int ntries, i; 1857 1858 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1859 for (ntries = 0; ntries < 40; ntries++) { 1860 if (!athn_tx_pending(sc, qid)) 1861 break; 1862 DELAY(100); 1863 } 1864 if (ntries == 40) { 1865 for (i = 0; i < 2; i++) { 1866 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1867 AR_WRITE(sc, AR_QUIET2, 1868 SM(AR_QUIET2_QUIET_DUR, 10)); 1869 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1870 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1871 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1872 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1873 break; 1874 } 1875 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1876 AR_WRITE_BARRIER(sc); 1877 DELAY(200); 1878 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1879 AR_WRITE_BARRIER(sc); 1880 1881 for (ntries = 0; ntries < 40; ntries++) { 1882 if (!athn_tx_pending(sc, qid)) 1883 break; 1884 DELAY(100); 1885 } 1886 1887 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1888 } 1889 AR_WRITE(sc, AR_Q_TXD, 0); 1890 AR_WRITE_BARRIER(sc); 1891 } 1892 1893 PUBLIC int 1894 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1895 { 1896 #define divround(a, b) (((a) + (b) - 1) / (b)) 1897 int txtime; 1898 1899 /* XXX HT. */ 1900 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1901 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1902 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1903 txtime = 16 + 4 + 4 * txtime + 16; 1904 } else { 1905 txtime = divround(16 * len, athn_rates[ridx].rate); 1906 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1907 txtime += 72 + 24; 1908 else 1909 txtime += 144 + 48; 1910 txtime += 10; /* 10us SIFS. */ 1911 } 1912 return txtime; 1913 #undef divround 1914 } 1915 1916 PUBLIC void 1917 athn_init_tx_queues(struct athn_softc *sc) 1918 { 1919 int qid; 1920 1921 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1922 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1923 sc->sc_txq[qid].lastds = NULL; 1924 sc->sc_txq[qid].wait = NULL; 1925 sc->sc_txq[qid].queued = 0; 1926 1927 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1928 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1929 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1930 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1931 AR_WRITE(sc, AR_QMISC(qid), 1932 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1933 AR_WRITE(sc, AR_DMISC(qid), 1934 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1935 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1936 } 1937 1938 /* Init beacon queue. */ 1939 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1940 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1941 AR_Q_MISC_CBR_INCR_DIS1); 1942 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1943 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1944 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1945 AR_D_MISC_BEACON_USE | 1946 AR_D_MISC_POST_FR_BKOFF_DIS); 1947 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1948 SM(AR_D_LCL_IFS_CWMIN, 0) | 1949 SM(AR_D_LCL_IFS_CWMAX, 0) | 1950 SM(AR_D_LCL_IFS_AIFS, 1)); 1951 1952 /* Init CAB (Content After Beacon) queue. */ 1953 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1954 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1955 AR_Q_MISC_CBR_INCR_DIS0); 1956 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1957 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1958 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1959 1960 /* Init PS-Poll queue. */ 1961 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1962 AR_Q_MISC_CBR_INCR_DIS1); 1963 1964 /* Init UAPSD queue. */ 1965 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1966 AR_D_MISC_POST_FR_BKOFF_DIS); 1967 1968 if (AR_SREV_9380_10_OR_LATER(sc)) { 1969 /* Enable MAC descriptor CRC check. */ 1970 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1971 } 1972 /* Enable DESC interrupts for all Tx queues. */ 1973 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1974 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1975 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1976 AR_WRITE_BARRIER(sc); 1977 } 1978 1979 PUBLIC void 1980 athn_set_sta_timers(struct athn_softc *sc) 1981 { 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 uint32_t tsfhi, tsflo, tsftu, reg; 1984 uint32_t intval, next_tbtt, next_dtim; 1985 int dtim_period, rem_dtim_count; 1986 1987 tsfhi = AR_READ(sc, AR_TSF_U32); 1988 tsflo = AR_READ(sc, AR_TSF_L32); 1989 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1990 1991 /* Beacon interval in TU. */ 1992 intval = ic->ic_bss->ni_intval; 1993 1994 next_tbtt = roundup(tsftu, intval); 1995 #ifdef notyet 1996 dtim_period = ic->ic_dtim_period; 1997 if (dtim_period <= 0) 1998 #endif 1999 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2000 2001 #ifdef notyet 2002 int dtim_count = ic->ic_dtim_count; 2003 if (dtim_count >= dtim_period) /* Should not happen. */ 2004 dtim_count = 0; /* Assume last TIM was a DTIM. */ 2005 #endif 2006 2007 /* Compute number of remaining TIMs until next DTIM. */ 2008 rem_dtim_count = 0; /* XXX */ 2009 next_dtim = next_tbtt + rem_dtim_count * intval; 2010 2011 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2012 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2013 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2014 2015 /* 2016 * Set the number of consecutive beacons to miss before raising 2017 * a BMISS interrupt to 10. 2018 */ 2019 reg = AR_READ(sc, AR_RSSI_THR); 2020 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2021 AR_WRITE(sc, AR_RSSI_THR, reg); 2022 2023 AR_WRITE(sc, AR_NEXT_DTIM, 2024 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2025 AR_WRITE(sc, AR_NEXT_TIM, 2026 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2027 2028 /* CAB timeout is in 1/8 TU. */ 2029 AR_WRITE(sc, AR_SLEEP1, 2030 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2031 AR_SLEEP1_ASSUME_DTIM); 2032 AR_WRITE(sc, AR_SLEEP2, 2033 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2034 2035 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2036 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2037 2038 AR_SETBITS(sc, AR_TIMER_MODE, 2039 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2040 2041 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2042 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2043 2044 AR_WRITE_BARRIER(sc); 2045 } 2046 2047 #ifndef IEEE80211_STA_ONLY 2048 PUBLIC void 2049 athn_set_hostap_timers(struct athn_softc *sc) 2050 { 2051 struct ieee80211com *ic = &sc->sc_ic; 2052 uint32_t intval, next_tbtt; 2053 2054 /* Beacon interval in TU. */ 2055 intval = ic->ic_bss->ni_intval; 2056 next_tbtt = intval; 2057 2058 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2059 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2060 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2061 AR_WRITE(sc, AR_NEXT_CFP, 2062 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2063 2064 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2065 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2066 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2067 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2068 2069 AR_WRITE(sc, AR_TIMER_MODE, 2070 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2071 2072 AR_WRITE_BARRIER(sc); 2073 } 2074 #endif 2075 2076 PUBLIC void 2077 athn_set_opmode(struct athn_softc *sc) 2078 { 2079 uint32_t reg; 2080 2081 switch (sc->sc_ic.ic_opmode) { 2082 #ifndef IEEE80211_STA_ONLY 2083 case IEEE80211_M_HOSTAP: 2084 reg = AR_READ(sc, AR_STA_ID1); 2085 reg &= ~AR_STA_ID1_ADHOC; 2086 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2087 AR_WRITE(sc, AR_STA_ID1, reg); 2088 2089 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2090 break; 2091 case IEEE80211_M_IBSS: 2092 case IEEE80211_M_AHDEMO: 2093 reg = AR_READ(sc, AR_STA_ID1); 2094 reg &= ~AR_STA_ID1_STA_AP; 2095 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2096 AR_WRITE(sc, AR_STA_ID1, reg); 2097 2098 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2099 break; 2100 #endif 2101 default: 2102 reg = AR_READ(sc, AR_STA_ID1); 2103 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2104 reg |= AR_STA_ID1_KSRCH_MODE; 2105 AR_WRITE(sc, AR_STA_ID1, reg); 2106 break; 2107 } 2108 AR_WRITE_BARRIER(sc); 2109 } 2110 2111 PUBLIC void 2112 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2113 { 2114 const uint8_t *bssid = ni->ni_bssid; 2115 2116 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2117 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2118 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2119 AR_WRITE_BARRIER(sc); 2120 } 2121 2122 Static void 2123 athn_enable_interrupts(struct athn_softc *sc) 2124 { 2125 uint32_t mask2; 2126 2127 athn_disable_interrupts(sc); /* XXX */ 2128 2129 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2130 2131 mask2 = AR_READ(sc, AR_IMR_S2); 2132 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2133 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2134 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2135 AR_WRITE(sc, AR_IMR_S2, mask2); 2136 2137 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2138 2139 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2140 2141 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2142 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2143 2144 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2145 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2146 AR_WRITE_BARRIER(sc); 2147 } 2148 2149 Static void 2150 athn_disable_interrupts(struct athn_softc *sc) 2151 { 2152 2153 AR_WRITE(sc, AR_IER, 0); 2154 (void)AR_READ(sc, AR_IER); 2155 2156 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2157 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2158 2159 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2160 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2161 2162 AR_WRITE(sc, AR_IMR, 0); 2163 2164 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2165 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2166 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2167 2168 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2169 AR_WRITE_BARRIER(sc); 2170 } 2171 2172 Static void 2173 athn_init_qos(struct athn_softc *sc) 2174 { 2175 2176 /* Initialize QoS settings. */ 2177 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2178 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2179 AR_WRITE(sc, AR_QOS_NO_ACK, 2180 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2181 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2182 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2183 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2184 /* Initialize TXOP for all TIDs. */ 2185 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2186 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2187 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2188 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2189 AR_WRITE_BARRIER(sc); 2190 } 2191 2192 PUBLIC int 2193 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2194 struct ieee80211_channel *extchan, int init) 2195 { 2196 struct ieee80211com *ic = &sc->sc_ic; 2197 struct athn_ops *ops = &sc->sc_ops; 2198 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2199 int i, error; 2200 2201 /* XXX not if already awake */ 2202 if ((error = athn_set_power_awake(sc)) != 0) { 2203 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2204 return error; 2205 } 2206 2207 /* Preserve the antenna on a channel switch. */ 2208 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2209 def_ant = 1; 2210 /* Preserve other registers. */ 2211 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2212 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2213 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2214 AR_CFG_LED_BLINK_SLOW); 2215 2216 /* Mark PHY as inactive. */ 2217 ops->disable_phy(sc); 2218 2219 if (init && AR_SREV_9271(sc)) { 2220 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2221 AR9271_RADIO_RF_RST); 2222 DELAY(50); 2223 } 2224 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2225 /* Save TSF before it gets cleared. */ 2226 tsfhi = AR_READ(sc, AR_TSF_U32); 2227 tsflo = AR_READ(sc, AR_TSF_L32); 2228 2229 /* NB: RTC reset clears TSF. */ 2230 error = athn_reset_power_on(sc); 2231 } else { 2232 tsfhi = tsflo = 0; /* XXX: gcc */ 2233 error = athn_reset(sc, 0); 2234 } 2235 if (error != 0) { 2236 aprint_error_dev(sc->sc_dev, 2237 "could not reset chip (error=%d)\n", error); 2238 return error; 2239 } 2240 2241 /* XXX not if already awake */ 2242 if ((error = athn_set_power_awake(sc)) != 0) { 2243 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2244 return error; 2245 } 2246 2247 athn_init_pll(sc, curchan); 2248 ops->set_rf_mode(sc, curchan); 2249 2250 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2251 /* Check that the radio is not disabled by hardware switch. */ 2252 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2253 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2254 reg = !reg; 2255 if (!reg) { 2256 aprint_error_dev(sc->sc_dev, 2257 "radio is disabled by hardware switch\n"); 2258 return EPERM; 2259 } 2260 } 2261 if (init && AR_SREV_9271(sc)) { 2262 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2263 AR9271_GATE_MAC_CTL); 2264 DELAY(50); 2265 } 2266 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2267 /* Restore TSF if it got cleared. */ 2268 AR_WRITE(sc, AR_TSF_L32, tsflo); 2269 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2270 } 2271 2272 if (AR_SREV_9280_10_OR_LATER(sc)) 2273 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2274 2275 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2276 ar9287_1_3_enable_async_fifo(sc); 2277 2278 /* Write init values to hardware. */ 2279 ops->hw_init(sc, curchan, extchan); 2280 2281 /* 2282 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2283 * management frames using CCMP. 2284 */ 2285 if (AR_SREV_9280_20_OR_LATER(sc)) { 2286 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2287 /* Do not mask the subtype field in management frames. */ 2288 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2289 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2290 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2291 IEEE80211_FC1_MORE_DATA)); 2292 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2293 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2294 /* Disable hardware crypto for management frames. */ 2295 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2296 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2297 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2298 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2299 } 2300 2301 if (ic->ic_curmode != IEEE80211_MODE_11B) 2302 ops->set_delta_slope(sc, curchan, extchan); 2303 2304 ops->spur_mitigate(sc, curchan, extchan); 2305 ops->init_from_rom(sc, curchan, extchan); 2306 2307 /* XXX */ 2308 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2309 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2310 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2311 2312 athn_set_opmode(sc); 2313 2314 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2315 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2316 2317 /* Restore previous antenna. */ 2318 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2319 2320 AR_WRITE(sc, AR_BSS_ID0, 0); 2321 AR_WRITE(sc, AR_BSS_ID1, 0); 2322 2323 AR_WRITE(sc, AR_ISR, 0xffffffff); 2324 2325 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2326 2327 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2328 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2329 return error; 2330 } 2331 sc->sc_curchan = curchan; 2332 sc->sc_curchanext = extchan; 2333 2334 for (i = 0; i < AR_NUM_DCU; i++) 2335 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2336 2337 athn_init_tx_queues(sc); 2338 2339 /* Initialize interrupt mask. */ 2340 sc->sc_imask = 2341 AR_IMR_TXDESC | AR_IMR_TXEOL | 2342 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2343 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2344 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2345 if (AR_SREV_9380_10_OR_LATER(sc)) 2346 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2347 #ifndef IEEE80211_STA_ONLY 2348 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2349 sc->sc_imask |= AR_IMR_MIB; 2350 #endif 2351 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2352 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2353 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2354 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2355 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2356 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2357 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2358 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2359 if (AR_SREV_9380_10_OR_LATER(sc)) { 2360 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2361 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2362 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2363 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2364 } 2365 2366 athn_init_qos(sc); 2367 2368 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2369 2370 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2371 ar9287_1_3_setup_async_fifo(sc); 2372 2373 /* Disable sequence number generation in hardware. */ 2374 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2375 2376 athn_init_dma(sc); 2377 2378 /* Program observation bus to see MAC interrupts. */ 2379 AR_WRITE(sc, sc->sc_obs_off, 8); 2380 2381 /* Setup Rx interrupt mitigation. */ 2382 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2383 2384 ops->init_baseband(sc); 2385 2386 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2387 aprint_error_dev(sc->sc_dev, 2388 "could not initialize calibration\n"); 2389 return error; 2390 } 2391 2392 ops->set_rxchains(sc); 2393 2394 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2395 2396 if (sc->sc_flags & ATHN_FLAG_USB) { 2397 if (AR_SREV_9271(sc)) 2398 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2399 else 2400 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2401 } 2402 #if BYTE_ORDER == BIG_ENDIAN 2403 else { 2404 /* Default is LE, turn on swapping for BE. */ 2405 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2406 } 2407 #endif 2408 AR_WRITE_BARRIER(sc); 2409 2410 return 0; 2411 } 2412 2413 Static struct ieee80211_node * 2414 athn_node_alloc(struct ieee80211_node_table *ntp) 2415 { 2416 2417 return malloc(sizeof(struct athn_node), M_DEVBUF, 2418 M_NOWAIT | M_ZERO); 2419 } 2420 2421 Static void 2422 athn_newassoc(struct ieee80211_node *ni, int isnew) 2423 { 2424 struct ieee80211com *ic = ni->ni_ic; 2425 struct athn_softc *sc = ic->ic_ifp->if_softc; 2426 struct athn_node *an = (void *)ni; 2427 struct ieee80211_rateset *rs = &ni->ni_rates; 2428 uint8_t rate; 2429 int ridx, i, j; 2430 2431 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2432 /* Start at lowest available bit-rate, AMRR will raise. */ 2433 ni->ni_txrate = 0; 2434 2435 for (i = 0; i < rs->rs_nrates; i++) { 2436 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2437 2438 /* Map 802.11 rate to HW rate index. */ 2439 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2440 if (athn_rates[ridx].rate == rate) 2441 break; 2442 an->ridx[i] = ridx; 2443 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2444 2445 /* Compute fallback rate for retries. */ 2446 an->fallback[i] = i; 2447 for (j = i - 1; j >= 0; j--) { 2448 if (athn_rates[an->ridx[j]].phy == 2449 athn_rates[an->ridx[i]].phy) { 2450 an->fallback[i] = j; 2451 break; 2452 } 2453 } 2454 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2455 i, an->fallback[i]); 2456 } 2457 } 2458 2459 Static int 2460 athn_media_change(struct ifnet *ifp) 2461 { 2462 struct athn_softc *sc = ifp->if_softc; 2463 struct ieee80211com *ic = &sc->sc_ic; 2464 uint8_t rate, ridx; 2465 int error; 2466 2467 error = ieee80211_media_change(ifp); 2468 if (error != ENETRESET) 2469 return error; 2470 2471 if (ic->ic_fixed_rate != -1) { 2472 rate = ic->ic_sup_rates[ic->ic_curmode]. 2473 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2474 /* Map 802.11 rate to HW rate index. */ 2475 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2476 if (athn_rates[ridx].rate == rate) 2477 break; 2478 sc->sc_fixed_ridx = ridx; 2479 } 2480 if (IS_UP_AND_RUNNING(ifp)) { 2481 athn_stop(ifp, 0); 2482 error = athn_init(ifp); 2483 } 2484 return error; 2485 } 2486 2487 Static void 2488 athn_next_scan(void *arg) 2489 { 2490 struct athn_softc *sc = arg; 2491 struct ieee80211com *ic = &sc->sc_ic; 2492 int s; 2493 2494 s = splnet(); 2495 if (ic->ic_state == IEEE80211_S_SCAN) 2496 ieee80211_next_scan(ic); 2497 splx(s); 2498 } 2499 2500 Static int 2501 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2502 { 2503 struct ifnet *ifp = ic->ic_ifp; 2504 struct athn_softc *sc = ifp->if_softc; 2505 uint32_t reg; 2506 int error; 2507 2508 callout_stop(&sc->sc_calib_to); 2509 2510 switch (nstate) { 2511 case IEEE80211_S_INIT: 2512 athn_set_led(sc, 0); 2513 break; 2514 case IEEE80211_S_SCAN: 2515 /* Make the LED blink while scanning. */ 2516 athn_set_led(sc, !sc->sc_led_state); 2517 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2518 if (error != 0) 2519 return error; 2520 callout_schedule(&sc->sc_scan_to, hz / 5); 2521 break; 2522 case IEEE80211_S_AUTH: 2523 athn_set_led(sc, 0); 2524 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2525 if (error != 0) 2526 return error; 2527 break; 2528 case IEEE80211_S_ASSOC: 2529 break; 2530 case IEEE80211_S_RUN: 2531 athn_set_led(sc, 1); 2532 2533 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2534 break; 2535 2536 /* Fake a join to initialize the Tx rate. */ 2537 athn_newassoc(ic->ic_bss, 1); 2538 2539 athn_set_bss(sc, ic->ic_bss); 2540 athn_disable_interrupts(sc); 2541 #ifndef IEEE80211_STA_ONLY 2542 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2543 athn_set_hostap_timers(sc); 2544 /* Enable software beacon alert interrupts. */ 2545 sc->sc_imask |= AR_IMR_SWBA; 2546 } else 2547 #endif 2548 { 2549 athn_set_sta_timers(sc); 2550 /* Enable beacon miss interrupts. */ 2551 sc->sc_imask |= AR_IMR_BMISS; 2552 2553 /* Stop receiving beacons from other BSS. */ 2554 reg = AR_READ(sc, AR_RX_FILTER); 2555 reg = (reg & ~AR_RX_FILTER_BEACON) | 2556 AR_RX_FILTER_MYBEACON; 2557 AR_WRITE(sc, AR_RX_FILTER, reg); 2558 AR_WRITE_BARRIER(sc); 2559 } 2560 athn_enable_interrupts(sc); 2561 2562 if (sc->sc_sup_calib_mask != 0) { 2563 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2564 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2565 /* ops->do_calib(sc); */ 2566 } 2567 /* XXX Start ANI. */ 2568 2569 callout_schedule(&sc->sc_calib_to, hz / 2); 2570 break; 2571 } 2572 2573 return sc->sc_newstate(ic, nstate, arg); 2574 } 2575 2576 #ifdef notyet_edca 2577 PUBLIC void 2578 athn_updateedca(struct ieee80211com *ic) 2579 { 2580 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2581 struct athn_softc *sc = ic->ic_ifp->if_softc; 2582 const struct ieee80211_edca_ac_params *ac; 2583 int aci, qid; 2584 2585 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2586 ac = &ic->ic_edca_ac[aci]; 2587 qid = athn_ac2qid[aci]; 2588 2589 AR_WRITE(sc, AR_DLCL_IFS(qid), 2590 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2591 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2592 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2593 if (ac->ac_txoplimit != 0) { 2594 AR_WRITE(sc, AR_DCHNTIME(qid), 2595 SM(AR_D_CHNTIME_DUR, 2596 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2597 AR_D_CHNTIME_EN); 2598 } else 2599 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2600 } 2601 AR_WRITE_BARRIER(sc); 2602 #undef ATHN_EXP2 2603 } 2604 #endif /* notyet_edca */ 2605 2606 Static int 2607 athn_clock_rate(struct athn_softc *sc) 2608 { 2609 struct ieee80211com *ic = &sc->sc_ic; 2610 int clockrate; /* MHz. */ 2611 2612 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2613 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2614 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2615 else 2616 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2617 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2618 clockrate = AR_CLOCK_RATE_CCK; 2619 } else 2620 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2621 #ifndef IEEE80211_NO_HT 2622 if (sc->sc_curchanext != NULL) 2623 clockrate *= 2; 2624 #endif 2625 return clockrate; 2626 } 2627 2628 PUBLIC void 2629 athn_updateslot(struct ifnet *ifp) 2630 { 2631 struct athn_softc *sc = ifp->if_softc; 2632 struct ieee80211com *ic = &sc->sc_ic; 2633 int slot; 2634 2635 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2636 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2637 AR_WRITE_BARRIER(sc); 2638 } 2639 2640 Static void 2641 athn_start(struct ifnet *ifp) 2642 { 2643 struct athn_softc *sc = ifp->if_softc; 2644 struct ieee80211com *ic = &sc->sc_ic; 2645 struct ether_header *eh; 2646 struct ieee80211_node *ni; 2647 struct mbuf *m; 2648 2649 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2650 || !device_is_active(sc->sc_dev)) 2651 return; 2652 2653 for (;;) { 2654 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2655 ifp->if_flags |= IFF_OACTIVE; 2656 break; 2657 } 2658 /* Send pending management frames first. */ 2659 IF_DEQUEUE(&ic->ic_mgtq, m); 2660 if (m != NULL) { 2661 ni = M_GETCTX(m, struct ieee80211_node *); 2662 goto sendit; 2663 } 2664 if (ic->ic_state != IEEE80211_S_RUN) 2665 break; 2666 2667 /* Encapsulate and send data frames. */ 2668 IFQ_DEQUEUE(&ifp->if_snd, m); 2669 if (m == NULL) 2670 break; 2671 2672 if (m->m_len < (int)sizeof(*eh) && 2673 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2674 if_statinc(ifp, if_oerrors); 2675 continue; 2676 } 2677 eh = mtod(m, struct ether_header *); 2678 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2679 if (ni == NULL) { 2680 m_freem(m); 2681 if_statinc(ifp, if_oerrors); 2682 continue; 2683 } 2684 2685 bpf_mtap(ifp, m, BPF_D_OUT); 2686 2687 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2688 continue; 2689 sendit: 2690 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2691 2692 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2693 ieee80211_free_node(ni); 2694 if_statinc(ifp, if_oerrors); 2695 continue; 2696 } 2697 2698 sc->sc_tx_timer = 5; 2699 ifp->if_timer = 1; 2700 } 2701 } 2702 2703 Static void 2704 athn_watchdog(struct ifnet *ifp) 2705 { 2706 struct athn_softc *sc = ifp->if_softc; 2707 2708 ifp->if_timer = 0; 2709 2710 if (sc->sc_tx_timer > 0) { 2711 if (--sc->sc_tx_timer == 0) { 2712 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2713 /* see athn_init, no need to call athn_stop here */ 2714 /* athn_stop(ifp, 0); */ 2715 (void)athn_init(ifp); 2716 if_statinc(ifp, if_oerrors); 2717 return; 2718 } 2719 ifp->if_timer = 1; 2720 } 2721 ieee80211_watchdog(&sc->sc_ic); 2722 } 2723 2724 Static void 2725 athn_set_multi(struct athn_softc *sc) 2726 { 2727 struct ethercom *ec = &sc->sc_ec; 2728 struct ifnet *ifp = &ec->ec_if; 2729 struct ether_multi *enm; 2730 struct ether_multistep step; 2731 const uint8_t *addr; 2732 uint32_t val, lo, hi; 2733 uint8_t bit; 2734 2735 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2736 lo = hi = 0xffffffff; 2737 goto done2; 2738 } 2739 lo = hi = 0; 2740 ETHER_LOCK(ec); 2741 ETHER_FIRST_MULTI(step, ec, enm); 2742 while (enm != NULL) { 2743 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2744 ifp->if_flags |= IFF_ALLMULTI; 2745 lo = hi = 0xffffffff; 2746 goto done; 2747 } 2748 addr = enm->enm_addrlo; 2749 /* Calculate the XOR value of all eight 6-bit words. */ 2750 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2751 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2752 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2753 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2754 bit &= 0x3f; 2755 if (bit < 32) 2756 lo |= 1 << bit; 2757 else 2758 hi |= 1 << (bit - 32); 2759 ETHER_NEXT_MULTI(step, enm); 2760 } 2761 done: 2762 ETHER_UNLOCK(ec); 2763 done2: 2764 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2765 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2766 AR_WRITE_BARRIER(sc); 2767 } 2768 2769 Static int 2770 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2771 { 2772 struct athn_softc *sc = ifp->if_softc; 2773 struct ieee80211com *ic = &sc->sc_ic; 2774 int s, error = 0; 2775 2776 s = splnet(); 2777 2778 switch (cmd) { 2779 case SIOCSIFFLAGS: 2780 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2781 break; 2782 2783 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2784 case IFF_UP | IFF_RUNNING: 2785 #ifdef notyet 2786 if (((ifp->if_flags ^ sc->sc_if_flags) & 2787 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2788 /* XXX: setup multi */ 2789 #endif 2790 break; 2791 case IFF_UP: 2792 athn_init(ifp); 2793 break; 2794 2795 case IFF_RUNNING: 2796 athn_stop(ifp, 1); 2797 break; 2798 case 0: 2799 default: 2800 break; 2801 } 2802 sc->sc_if_flags = ifp->if_flags; 2803 break; 2804 2805 case SIOCADDMULTI: 2806 case SIOCDELMULTI: 2807 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2808 /* setup multicast filter, etc */ 2809 athn_set_multi(sc); 2810 error = 0; 2811 } 2812 break; 2813 2814 case SIOCS80211CHANNEL: 2815 error = ieee80211_ioctl(ic, cmd, data); 2816 if (error == ENETRESET && 2817 ic->ic_opmode == IEEE80211_M_MONITOR) { 2818 if (IS_UP_AND_RUNNING(ifp)) 2819 athn_switch_chan(sc, ic->ic_curchan, NULL); 2820 error = 0; 2821 } 2822 break; 2823 2824 default: 2825 error = ieee80211_ioctl(ic, cmd, data); 2826 } 2827 2828 if (error == ENETRESET) { 2829 error = 0; 2830 if (IS_UP_AND_RUNNING(ifp) && 2831 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2832 athn_stop(ifp, 0); 2833 error = athn_init(ifp); 2834 } 2835 } 2836 2837 splx(s); 2838 return error; 2839 } 2840 2841 Static int 2842 athn_init(struct ifnet *ifp) 2843 { 2844 struct athn_softc *sc = ifp->if_softc; 2845 struct athn_ops *ops = &sc->sc_ops; 2846 struct ieee80211com *ic = &sc->sc_ic; 2847 struct ieee80211_channel *curchan, *extchan; 2848 size_t i; 2849 int error; 2850 2851 KASSERT(!cpu_intr_p()); 2852 2853 if (device_is_active(sc->sc_dev)) { 2854 athn_stop(ifp, 0); /* see athn_watchdog() */ 2855 } else { 2856 short flags = ifp->if_flags; 2857 ifp->if_flags &= ~IFF_UP; 2858 /* avoid recursion in athn_resume */ 2859 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2860 !device_is_active(sc->sc_dev)) { 2861 printf("%s: failed to power up device\n", 2862 device_xname(sc->sc_dev)); 2863 return 0; 2864 } 2865 ifp->if_flags = flags; 2866 } 2867 2868 curchan = ic->ic_curchan; 2869 extchan = NULL; 2870 2871 /* In case a new MAC address has been configured. */ 2872 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2873 2874 #ifdef openbsd_power_management 2875 /* For CardBus, power on the socket. */ 2876 if (sc->sc_enable != NULL) { 2877 if ((error = sc->sc_enable(sc)) != 0) { 2878 aprint_error_dev(sc->sc_dev, 2879 "could not enable device\n"); 2880 goto fail; 2881 } 2882 if ((error = athn_reset_power_on(sc)) != 0) { 2883 aprint_error_dev(sc->sc_dev, 2884 "could not power on device\n"); 2885 goto fail; 2886 } 2887 } 2888 #endif 2889 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2890 athn_config_nonpcie(sc); 2891 else 2892 athn_config_pcie(sc); 2893 2894 /* Reset HW key cache entries. */ 2895 for (i = 0; i < sc->sc_kc_entries; i++) 2896 athn_reset_key(sc, i); 2897 2898 ops->enable_antenna_diversity(sc); 2899 2900 #ifdef ATHN_BT_COEXISTENCE 2901 /* Configure bluetooth coexistence for combo chips. */ 2902 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2903 athn_btcoex_init(sc); 2904 #endif 2905 2906 /* Configure LED. */ 2907 athn_led_init(sc); 2908 2909 /* Configure hardware radio switch. */ 2910 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2911 ops->rfsilent_init(sc); 2912 2913 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2914 aprint_error_dev(sc->sc_dev, 2915 "unable to reset hardware; reset status %d\n", error); 2916 goto fail; 2917 } 2918 2919 /* Enable Rx. */ 2920 athn_rx_start(sc); 2921 2922 /* Enable interrupts. */ 2923 athn_enable_interrupts(sc); 2924 2925 #ifdef ATHN_BT_COEXISTENCE 2926 /* Enable bluetooth coexistence for combo chips. */ 2927 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2928 athn_btcoex_enable(sc); 2929 #endif 2930 2931 ifp->if_flags &= ~IFF_OACTIVE; 2932 ifp->if_flags |= IFF_RUNNING; 2933 2934 #ifdef notyet 2935 if (ic->ic_flags & IEEE80211_F_WEPON) { 2936 /* Configure WEP keys. */ 2937 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2938 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2939 } 2940 #endif 2941 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2942 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2943 else 2944 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2945 2946 return 0; 2947 fail: 2948 athn_stop(ifp, 1); 2949 return error; 2950 } 2951 2952 PUBLIC void 2953 athn_stop(struct ifnet *ifp, int disable) 2954 { 2955 struct athn_softc *sc = ifp->if_softc; 2956 struct ieee80211com *ic = &sc->sc_ic; 2957 int qid; 2958 2959 ifp->if_timer = sc->sc_tx_timer = 0; 2960 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2961 2962 callout_stop(&sc->sc_scan_to); 2963 /* In case we were scanning, release the scan "lock". */ 2964 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2965 2966 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2967 2968 #ifdef ATHN_BT_COEXISTENCE 2969 /* Disable bluetooth coexistence for combo chips. */ 2970 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2971 athn_btcoex_disable(sc); 2972 #endif 2973 2974 /* Disable interrupts. */ 2975 athn_disable_interrupts(sc); 2976 /* Acknowledge interrupts (avoids interrupt storms). */ 2977 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2978 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2979 2980 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2981 athn_stop_tx_dma(sc, qid); 2982 /* XXX call athn_hw_reset if Tx still pending? */ 2983 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2984 athn_tx_reclaim(sc, qid); 2985 2986 /* Stop Rx. */ 2987 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2988 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2989 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2990 AR_WRITE(sc, AR_FILT_OFDM, 0); 2991 AR_WRITE(sc, AR_FILT_CCK, 0); 2992 AR_WRITE_BARRIER(sc); 2993 athn_set_rxfilter(sc, 0); 2994 athn_stop_rx_dma(sc); 2995 2996 athn_reset(sc, 0); 2997 athn_init_pll(sc, NULL); 2998 athn_set_power_awake(sc); 2999 athn_reset(sc, 1); 3000 athn_init_pll(sc, NULL); 3001 3002 athn_set_power_sleep(sc); 3003 3004 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3005 /* For CardBus, power down the socket. */ 3006 if (disable && sc->sc_disable != NULL) 3007 sc->sc_disable(sc); 3008 #endif 3009 if (disable) 3010 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3011 } 3012 3013 Static void 3014 athn_pmf_wlan_off(device_t self) 3015 { 3016 struct athn_softc *sc = device_private(self); 3017 struct ifnet *ifp = &sc->sc_if; 3018 3019 /* Turn the interface down. */ 3020 ifp->if_flags &= ~IFF_UP; 3021 athn_stop(ifp, 1); 3022 } 3023 3024 PUBLIC void 3025 athn_suspend(struct athn_softc *sc) 3026 { 3027 struct ifnet *ifp = &sc->sc_if; 3028 3029 if (ifp->if_flags & IFF_RUNNING) 3030 athn_stop(ifp, 1); 3031 } 3032 3033 PUBLIC bool 3034 athn_resume(struct athn_softc *sc) 3035 { 3036 struct ifnet *ifp = &sc->sc_if; 3037 3038 if (ifp->if_flags & IFF_UP) 3039 athn_init(ifp); 3040 3041 return true; 3042 } 3043
Indexes created Mon Sep 22 10:09:38 GMT 2025