athn.c revision 1.25
1 /* $NetBSD: athn.c,v 1.25 2021/06/16 00:21:18 riastradh Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.25 2021/06/16 00:21:18 riastradh Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 #endif /* notyet */ 140 Static void athn_set_multi(struct athn_softc *); 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } else { 253 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 254 athn_get_rf_name(sc)); 255 aprint_verbose_dev(sc->sc_dev, 256 "rev %d (%dT%dR), ROM rev %d, address %s\n", 257 sc->sc_mac_rev, 258 sc->sc_ntxchains, sc->sc_nrxchains, 259 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 260 } 261 262 callout_init(&sc->sc_scan_to, 0); 263 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 264 callout_init(&sc->sc_calib_to, 0); 265 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 266 267 sc->sc_amrr.amrr_min_success_threshold = 1; 268 sc->sc_amrr.amrr_max_success_threshold = 15; 269 270 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 271 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* Set device capabilities. */ 275 ic->ic_caps = 276 IEEE80211_C_WPA | /* 802.11i */ 277 #ifndef IEEE80211_STA_ONLY 278 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 279 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 280 #endif 281 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 282 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 283 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 284 IEEE80211_C_PMGT; /* Power saving supported. */ 285 286 #ifndef IEEE80211_NO_HT 287 if (sc->sc_flags & ATHN_FLAG_11N) { 288 int i, ntxstreams, nrxstreams; 289 290 /* Set HT capabilities. */ 291 ic->ic_htcaps = 292 IEEE80211_HTCAP_SMPS_DIS | 293 IEEE80211_HTCAP_CBW20_40 | 294 IEEE80211_HTCAP_SGI40 | 295 IEEE80211_HTCAP_DSSSCCK40; 296 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 297 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 298 if (AR_SREV_9380_10_OR_LATER(sc)) 299 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 300 if (AR_SREV_9280_10_OR_LATER(sc)) { 301 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 302 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 303 } 304 ntxstreams = sc->sc_ntxchains; 305 nrxstreams = sc->sc_nrxchains; 306 if (!AR_SREV_9380_10_OR_LATER(sc)) { 307 ntxstreams = MIN(ntxstreams, 2); 308 nrxstreams = MIN(nrxstreams, 2); 309 } 310 /* Set supported HT rates. */ 311 for (i = 0; i < nrxstreams; i++) 312 ic->ic_sup_mcs[i] = 0xff; 313 /* Set the "Tx MCS Set Defined" bit. */ 314 ic->ic_sup_mcs[12] |= 0x01; 315 if (ntxstreams != nrxstreams) { 316 /* Set "Tx Rx MCS Set Not Equal" bit. */ 317 ic->ic_sup_mcs[12] |= 0x02; 318 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 319 } 320 } 321 #endif 322 323 /* Set supported rates. */ 324 if (sc->sc_flags & ATHN_FLAG_11G) { 325 ic->ic_sup_rates[IEEE80211_MODE_11B] = 326 ieee80211_std_rateset_11b; 327 ic->ic_sup_rates[IEEE80211_MODE_11G] = 328 ieee80211_std_rateset_11g; 329 } 330 if (sc->sc_flags & ATHN_FLAG_11A) { 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 } 334 335 /* Get the list of authorized/supported channels. */ 336 athn_get_chanlist(sc); 337 338 ifp->if_softc = sc; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 if (!ifp->if_init) 341 ifp->if_init = athn_init; 342 if (!ifp->if_ioctl) 343 ifp->if_ioctl = athn_ioctl; 344 if (!ifp->if_start) 345 ifp->if_start = athn_start; 346 if (!ifp->if_watchdog) 347 ifp->if_watchdog = athn_watchdog; 348 IFQ_SET_READY(&ifp->if_snd); 349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 350 351 if_initialize(ifp); 352 ieee80211_ifattach(ic); 353 /* Use common softint-based if_input */ 354 ifp->if_percpuq = if_percpuq_create(ifp); 355 if_register(ifp); 356 357 ic->ic_node_alloc = athn_node_alloc; 358 ic->ic_newassoc = athn_newassoc; 359 if (ic->ic_updateslot == NULL) 360 ic->ic_updateslot = athn_updateslot; 361 #ifdef notyet_edca 362 ic->ic_updateedca = athn_updateedca; 363 #endif 364 #ifdef notyet 365 ic->ic_set_key = athn_set_key; 366 ic->ic_delete_key = athn_delete_key; 367 #endif 368 369 /* Override 802.11 state transition machine. */ 370 sc->sc_newstate = ic->ic_newstate; 371 ic->ic_newstate = athn_newstate; 372 373 if (sc->sc_media_change == NULL) 374 sc->sc_media_change = athn_media_change; 375 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 376 377 athn_radiotap_attach(sc); 378 return 0; 379 } 380 381 PUBLIC void 382 athn_detach(struct athn_softc *sc) 383 { 384 struct ifnet *ifp = &sc->sc_if; 385 int qid; 386 387 callout_halt(&sc->sc_scan_to, NULL); 388 callout_halt(&sc->sc_calib_to, NULL); 389 390 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 391 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 392 athn_tx_reclaim(sc, qid); 393 394 /* Free Tx/Rx DMA resources. */ 395 sc->sc_ops.dma_free(sc); 396 397 if (sc->sc_soft_ih != NULL) { 398 softint_disestablish(sc->sc_soft_ih); 399 sc->sc_soft_ih = NULL; 400 } 401 } 402 /* Free ROM copy. */ 403 if (sc->sc_eep != NULL) { 404 free(sc->sc_eep, M_DEVBUF); 405 sc->sc_eep = NULL; 406 } 407 408 bpf_detach(ifp); 409 ieee80211_ifdetach(&sc->sc_ic); 410 if_detach(ifp); 411 412 callout_destroy(&sc->sc_scan_to); 413 callout_destroy(&sc->sc_calib_to); 414 415 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 416 false); 417 } 418 419 /* 420 * Attach the interface to 802.11 radiotap. 421 */ 422 Static void 423 athn_radiotap_attach(struct athn_softc *sc) 424 { 425 426 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 427 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 428 &sc->sc_drvbpf); 429 430 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 431 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 432 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 433 434 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 435 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 436 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 437 } 438 439 Static void 440 athn_get_chanlist(struct athn_softc *sc) 441 { 442 struct ieee80211com *ic = &sc->sc_ic; 443 uint8_t chan; 444 size_t i; 445 446 if (sc->sc_flags & ATHN_FLAG_11G) { 447 for (i = 1; i <= 14; i++) { 448 chan = i; 449 ic->ic_channels[chan].ic_freq = 450 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 451 ic->ic_channels[chan].ic_flags = 452 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 453 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 454 } 455 } 456 if (sc->sc_flags & ATHN_FLAG_11A) { 457 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 458 chan = athn_5ghz_chans[i]; 459 ic->ic_channels[chan].ic_freq = 460 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 461 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 462 } 463 } 464 } 465 466 PUBLIC void 467 athn_rx_start(struct athn_softc *sc) 468 { 469 struct ieee80211com *ic = &sc->sc_ic; 470 uint32_t rfilt; 471 472 /* Setup Rx DMA descriptors. */ 473 sc->sc_ops.rx_enable(sc); 474 475 /* Set Rx filter. */ 476 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 477 #ifndef IEEE80211_NO_HT 478 /* Want Compressed Block Ack Requests. */ 479 rfilt |= AR_RX_FILTER_COMPR_BAR; 480 #endif 481 rfilt |= AR_RX_FILTER_BEACON; 482 if (ic->ic_opmode != IEEE80211_M_STA) { 483 rfilt |= AR_RX_FILTER_PROBEREQ; 484 if (ic->ic_opmode == IEEE80211_M_MONITOR) 485 rfilt |= AR_RX_FILTER_PROM; 486 #ifndef IEEE80211_STA_ONLY 487 if (AR_SREV_9280_10_OR_LATER(sc) && 488 ic->ic_opmode == IEEE80211_M_HOSTAP) 489 rfilt |= AR_RX_FILTER_PSPOLL; 490 #endif 491 } 492 athn_set_rxfilter(sc, rfilt); 493 494 /* Set BSSID mask. */ 495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 496 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 497 498 athn_set_opmode(sc); 499 500 /* Set multicast filter. */ 501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 503 504 AR_WRITE(sc, AR_FILT_OFDM, 0); 505 AR_WRITE(sc, AR_FILT_CCK, 0); 506 AR_WRITE(sc, AR_MIBC, 0); 507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 509 510 /* XXX ANI. */ 511 AR_WRITE(sc, AR_PHY_ERR_1, 0); 512 AR_WRITE(sc, AR_PHY_ERR_2, 0); 513 514 /* Disable HW crypto for now. */ 515 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 516 517 /* Start PCU Rx. */ 518 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 519 AR_WRITE_BARRIER(sc); 520 } 521 522 PUBLIC void 523 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 524 { 525 526 AR_WRITE(sc, AR_RX_FILTER, rfilt); 527 #ifdef notyet 528 reg = AR_READ(sc, AR_PHY_ERR); 529 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 530 AR_PHY_ERR_CCK_TIMING); 531 AR_WRITE(sc, AR_PHY_ERR, reg); 532 if (reg != 0) 533 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 534 else 535 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 536 #else 537 AR_WRITE(sc, AR_PHY_ERR, 0); 538 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 539 #endif 540 AR_WRITE_BARRIER(sc); 541 } 542 543 PUBLIC int 544 athn_intr(void *xsc) 545 { 546 struct athn_softc *sc = xsc; 547 struct ifnet *ifp = &sc->sc_if; 548 549 if (!IS_UP_AND_RUNNING(ifp)) 550 return 0; 551 552 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 553 /* 554 * The hardware is not ready/present, don't touch anything. 555 * Note this can happen early on if the IRQ is shared. 556 */ 557 return 0; 558 559 if (!sc->sc_ops.intr_status(sc)) 560 return 0; 561 562 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 563 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 564 AR_WRITE_BARRIER(sc); 565 566 softint_schedule(sc->sc_soft_ih); 567 568 return 1; 569 } 570 571 Static void 572 athn_softintr(void *xsc) 573 { 574 struct athn_softc *sc = xsc; 575 struct ifnet *ifp = &sc->sc_if; 576 577 if (!IS_UP_AND_RUNNING(ifp)) 578 return; 579 580 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 581 /* 582 * The hardware is not ready/present, don't touch anything. 583 * Note this can happen early on if the IRQ is shared. 584 */ 585 return; 586 587 sc->sc_ops.intr(sc); 588 589 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 590 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 591 AR_WRITE_BARRIER(sc); 592 } 593 594 Static void 595 athn_get_chipid(struct athn_softc *sc) 596 { 597 uint32_t reg; 598 599 reg = AR_READ(sc, AR_SREV); 600 if (MS(reg, AR_SREV_ID) == 0xff) { 601 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 602 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 603 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 604 sc->sc_flags |= ATHN_FLAG_PCIE; 605 } else { 606 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 607 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 608 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 609 sc->sc_flags |= ATHN_FLAG_PCIE; 610 } 611 } 612 613 Static const char * 614 athn_get_mac_name(struct athn_softc *sc) 615 { 616 617 switch (sc->sc_mac_ver) { 618 case AR_SREV_VERSION_5416_PCI: 619 return "AR5416"; 620 case AR_SREV_VERSION_5416_PCIE: 621 return "AR5418"; 622 case AR_SREV_VERSION_9160: 623 return "AR9160"; 624 case AR_SREV_VERSION_9280: 625 return "AR9280"; 626 case AR_SREV_VERSION_9285: 627 return "AR9285"; 628 case AR_SREV_VERSION_9271: 629 return "AR9271"; 630 case AR_SREV_VERSION_9287: 631 return "AR9287"; 632 case AR_SREV_VERSION_9380: 633 return "AR9380"; 634 case AR_SREV_VERSION_9485: 635 return "AR9485"; 636 default: 637 return "unknown"; 638 } 639 } 640 641 /* 642 * Return RF chip name (not for single-chip solutions). 643 */ 644 Static const char * 645 athn_get_rf_name(struct athn_softc *sc) 646 { 647 648 KASSERT(!AR_SINGLE_CHIP(sc)); 649 650 switch (sc->sc_rf_rev) { 651 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 652 return "AR5133"; 653 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 654 return "AR2133"; 655 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 656 return "AR5122"; 657 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 658 return "AR2122"; 659 default: 660 return "unknown"; 661 } 662 } 663 664 PUBLIC int 665 athn_reset_power_on(struct athn_softc *sc) 666 { 667 int ntries; 668 669 /* Set force wake. */ 670 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 671 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 672 673 if (!AR_SREV_9380_10_OR_LATER(sc)) { 674 /* Make sure no DMA is active by doing an AHB reset. */ 675 AR_WRITE(sc, AR_RC, AR_RC_AHB); 676 } 677 /* RTC reset and clear. */ 678 AR_WRITE(sc, AR_RTC_RESET, 0); 679 AR_WRITE_BARRIER(sc); 680 DELAY(2); 681 if (!AR_SREV_9380_10_OR_LATER(sc)) 682 AR_WRITE(sc, AR_RC, 0); 683 AR_WRITE(sc, AR_RTC_RESET, 1); 684 685 /* Poll until RTC is ON. */ 686 for (ntries = 0; ntries < 1000; ntries++) { 687 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 688 AR_RTC_STATUS_ON) 689 break; 690 DELAY(10); 691 } 692 if (ntries == 1000) { 693 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 694 return ETIMEDOUT; 695 } 696 return athn_reset(sc, 0); 697 } 698 699 PUBLIC int 700 athn_reset(struct athn_softc *sc, int cold_reset) 701 { 702 int ntries; 703 704 /* Set force wake. */ 705 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 706 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 707 708 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 709 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 710 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 711 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 712 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 713 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 714 AR_WRITE(sc, AR_RC, AR_RC_AHB); 715 716 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 717 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 718 AR_WRITE_BARRIER(sc); 719 DELAY(50); 720 AR_WRITE(sc, AR_RTC_RC, 0); 721 for (ntries = 0; ntries < 1000; ntries++) { 722 if (!(AR_READ(sc, AR_RTC_RC) & 723 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 724 break; 725 DELAY(10); 726 } 727 if (ntries == 1000) { 728 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 729 return ETIMEDOUT; 730 } 731 AR_WRITE(sc, AR_RC, 0); 732 AR_WRITE_BARRIER(sc); 733 return 0; 734 } 735 736 PUBLIC int 737 athn_set_power_awake(struct athn_softc *sc) 738 { 739 int ntries, error; 740 741 /* Do a Power-On-Reset if shutdown. */ 742 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 743 AR_RTC_STATUS_SHUTDOWN) { 744 if ((error = athn_reset_power_on(sc)) != 0) 745 return error; 746 if (!AR_SREV_9380_10_OR_LATER(sc)) 747 athn_init_pll(sc, NULL); 748 } 749 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 750 AR_WRITE_BARRIER(sc); 751 DELAY(50); /* Give chip the chance to awake. */ 752 753 /* Poll until RTC is ON. */ 754 for (ntries = 0; ntries < 4000; ntries++) { 755 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 756 AR_RTC_STATUS_ON) 757 break; 758 DELAY(50); 759 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 760 } 761 if (ntries == 4000) { 762 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 763 return ETIMEDOUT; 764 } 765 766 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 767 AR_WRITE_BARRIER(sc); 768 return 0; 769 } 770 771 PUBLIC void 772 athn_set_power_sleep(struct athn_softc *sc) 773 { 774 775 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 776 /* Allow the MAC to go to sleep. */ 777 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 778 if (!AR_SREV_9380_10_OR_LATER(sc)) 779 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 780 /* 781 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 782 * results in high power consumption on AR5416 chipsets. 783 */ 784 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 785 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 786 AR_WRITE_BARRIER(sc); 787 } 788 789 PUBLIC void 790 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 791 { 792 uint32_t pll; 793 794 if (AR_SREV_9380_10_OR_LATER(sc)) { 795 if (AR_SREV_9485(sc)) 796 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 797 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 798 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 799 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 800 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 801 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 802 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 803 pll = 0x142c; 804 else if (AR_SREV_9280_20(sc)) 805 pll = 0x2850; 806 else 807 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 808 } else 809 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 810 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 811 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 812 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 813 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 814 else 815 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 816 } else { 817 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 818 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 819 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 820 else 821 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 822 } 823 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 824 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 825 if (AR_SREV_9271(sc)) { 826 /* Switch core clock to 117MHz. */ 827 AR_WRITE_BARRIER(sc); 828 DELAY(500); 829 AR_WRITE(sc, 0x50050, 0x304); 830 } 831 AR_WRITE_BARRIER(sc); 832 DELAY(100); 833 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 834 AR_WRITE_BARRIER(sc); 835 } 836 837 Static void 838 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 839 { 840 int i; 841 842 /* Write sequence to Serializer/Deserializer. */ 843 for (i = 0; i < serdes->nvals; i++) 844 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 845 AR_WRITE_BARRIER(sc); 846 } 847 848 PUBLIC void 849 athn_config_pcie(struct athn_softc *sc) 850 { 851 852 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 853 athn_write_serdes(sc, sc->sc_serdes); 854 855 DELAY(1000); 856 /* Allow forcing of PCIe core into L1 state. */ 857 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 858 859 #ifndef ATHN_PCIE_WAEN 860 AR_WRITE(sc, AR_WA, sc->sc_workaround); 861 #else 862 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 863 #endif 864 AR_WRITE_BARRIER(sc); 865 } 866 867 /* 868 * Serializer/Deserializer programming for non-PCIe devices. 869 */ 870 static const uint32_t ar_nonpcie_serdes_regs[] = { 871 AR_PCIE_SERDES, 872 AR_PCIE_SERDES, 873 AR_PCIE_SERDES, 874 AR_PCIE_SERDES, 875 AR_PCIE_SERDES, 876 AR_PCIE_SERDES, 877 AR_PCIE_SERDES, 878 AR_PCIE_SERDES, 879 AR_PCIE_SERDES, 880 AR_PCIE_SERDES2, 881 }; 882 883 static const uint32_t ar_nonpcie_serdes_vals[] = { 884 0x9248fc00, 885 0x24924924, 886 0x28000029, 887 0x57160824, 888 0x25980579, 889 0x00000000, 890 0x1aaabe40, 891 0xbe105554, 892 0x000e1007, 893 0x00000000 894 }; 895 896 static const struct athn_serdes ar_nonpcie_serdes = { 897 __arraycount(ar_nonpcie_serdes_vals), 898 ar_nonpcie_serdes_regs, 899 ar_nonpcie_serdes_vals 900 }; 901 902 PUBLIC void 903 athn_config_nonpcie(struct athn_softc *sc) 904 { 905 906 athn_write_serdes(sc, &ar_nonpcie_serdes); 907 } 908 909 PUBLIC int 910 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 911 struct ieee80211_channel *extchan) 912 { 913 struct athn_ops *ops = &sc->sc_ops; 914 int error, qid; 915 916 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 917 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 918 if (athn_tx_pending(sc, qid)) 919 return EBUSY; 920 921 /* Request RF Bus grant. */ 922 if ((error = ops->rf_bus_request(sc)) != 0) 923 return error; 924 925 ops->set_phy(sc, curchan, extchan); 926 927 /* Change the synthesizer. */ 928 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 929 return error; 930 931 sc->sc_curchan = curchan; 932 sc->sc_curchanext = extchan; 933 934 /* Set transmit power values for new channel. */ 935 ops->set_txpower(sc, curchan, extchan); 936 937 /* Release the RF Bus grant. */ 938 ops->rf_bus_release(sc); 939 940 /* Write delta slope coeffs for modes where OFDM may be used. */ 941 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 942 ops->set_delta_slope(sc, curchan, extchan); 943 944 ops->spur_mitigate(sc, curchan, extchan); 945 /* XXX Load noisefloor values and start calibration. */ 946 947 return 0; 948 } 949 950 Static int 951 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 952 struct ieee80211_channel *extchan) 953 { 954 int error, qid; 955 956 /* Disable interrupts. */ 957 athn_disable_interrupts(sc); 958 959 /* Stop all Tx queues. */ 960 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 961 athn_stop_tx_dma(sc, qid); 962 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 963 athn_tx_reclaim(sc, qid); 964 965 /* Stop Rx. */ 966 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 967 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 968 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 969 AR_WRITE(sc, AR_FILT_OFDM, 0); 970 AR_WRITE(sc, AR_FILT_CCK, 0); 971 athn_set_rxfilter(sc, 0); 972 error = athn_stop_rx_dma(sc); 973 if (error != 0) 974 goto reset; 975 976 #ifdef notyet 977 /* AR9280 needs a full reset. */ 978 if (AR_SREV_9280(sc)) 979 #endif 980 goto reset; 981 982 /* If band or bandwidth changes, we need to do a full reset. */ 983 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 984 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 985 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 986 goto reset; 987 } 988 error = athn_set_power_awake(sc); 989 if (error != 0) 990 goto reset; 991 992 error = athn_set_chan(sc, curchan, extchan); 993 if (error != 0) { 994 reset: /* Error found, try a full reset. */ 995 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 996 error = athn_hw_reset(sc, curchan, extchan, 0); 997 if (error != 0) /* Hopeless case. */ 998 return error; 999 } 1000 athn_rx_start(sc); 1001 1002 /* Re-enable interrupts. */ 1003 athn_enable_interrupts(sc); 1004 return 0; 1005 } 1006 1007 PUBLIC void 1008 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1009 { 1010 #define COEFF_SCALE_SHIFT 24 1011 uint32_t exp, man; 1012 1013 /* exponent = 14 - floor(log2(coeff)) */ 1014 for (exp = 31; exp > 0; exp--) 1015 if (coeff & (1U << exp)) 1016 break; 1017 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1018 1019 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1020 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1021 1022 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1023 *exponent = exp - 16; 1024 #undef COEFF_SCALE_SHIFT 1025 } 1026 1027 PUBLIC void 1028 athn_reset_key(struct athn_softc *sc, int entry) 1029 { 1030 1031 /* 1032 * NB: Key cache registers access special memory area that requires 1033 * two 32-bit writes to actually update the values in the internal 1034 * memory. Consequently, writes must be grouped by pair. 1035 */ 1036 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1037 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1038 1039 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1040 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1041 1042 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1043 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1044 1045 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1046 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1047 1048 AR_WRITE_BARRIER(sc); 1049 } 1050 1051 #ifdef notyet 1052 Static int 1053 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1054 struct ieee80211_key *k) 1055 { 1056 struct athn_softc *sc = ic->ic_ifp->if_softc; 1057 const uint8_t *txmic, *rxmic, *key, *addr; 1058 uintptr_t entry, micentry; 1059 uint32_t type, lo, hi; 1060 1061 switch (k->k_cipher) { 1062 case IEEE80211_CIPHER_WEP40: 1063 type = AR_KEYTABLE_TYPE_40; 1064 break; 1065 case IEEE80211_CIPHER_WEP104: 1066 type = AR_KEYTABLE_TYPE_104; 1067 break; 1068 case IEEE80211_CIPHER_TKIP: 1069 type = AR_KEYTABLE_TYPE_TKIP; 1070 break; 1071 case IEEE80211_CIPHER_CCMP: 1072 type = AR_KEYTABLE_TYPE_CCM; 1073 break; 1074 default: 1075 /* Fallback to software crypto for other ciphers. */ 1076 return ieee80211_set_key(ic, ni, k); 1077 } 1078 1079 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1080 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1081 else 1082 entry = k->k_id; 1083 k->k_priv = (void *)entry; 1084 1085 /* NB: See note about key cache registers access above. */ 1086 key = k->k_key; 1087 if (type == AR_KEYTABLE_TYPE_TKIP) { 1088 #ifndef IEEE80211_STA_ONLY 1089 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1090 txmic = &key[16]; 1091 rxmic = &key[24]; 1092 } else 1093 #endif 1094 { 1095 rxmic = &key[16]; 1096 txmic = &key[24]; 1097 } 1098 /* Tx+Rx MIC key is at entry + 64. */ 1099 micentry = entry + 64; 1100 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1101 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1102 1103 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1104 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1105 1106 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1107 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1108 } 1109 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1110 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1111 1112 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1113 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1114 1115 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1116 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1117 1118 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1119 addr = ni->ni_macaddr; 1120 lo = LE_READ_4(&addr[0]); 1121 hi = LE_READ_2(&addr[4]); 1122 lo = lo >> 1 | hi << 31; 1123 hi = hi >> 1; 1124 } else 1125 lo = hi = 0; 1126 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1127 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1128 AR_WRITE_BARRIER(sc); 1129 return 0; 1130 } 1131 1132 Static void 1133 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1134 struct ieee80211_key *k) 1135 { 1136 struct athn_softc *sc = ic->ic_ifp->if_softc; 1137 uintptr_t entry; 1138 1139 switch (k->k_cipher) { 1140 case IEEE80211_CIPHER_WEP40: 1141 case IEEE80211_CIPHER_WEP104: 1142 case IEEE80211_CIPHER_CCMP: 1143 entry = (uintptr_t)k->k_priv; 1144 athn_reset_key(sc, entry); 1145 break; 1146 case IEEE80211_CIPHER_TKIP: 1147 entry = (uintptr_t)k->k_priv; 1148 athn_reset_key(sc, entry); 1149 athn_reset_key(sc, entry + 64); 1150 break; 1151 default: 1152 /* Fallback to software crypto for other ciphers. */ 1153 ieee80211_delete_key(ic, ni, k); 1154 } 1155 } 1156 #endif /* notyet */ 1157 1158 PUBLIC void 1159 athn_led_init(struct athn_softc *sc) 1160 { 1161 struct athn_ops *ops = &sc->sc_ops; 1162 1163 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1164 /* LED off, active low. */ 1165 athn_set_led(sc, 0); 1166 } 1167 1168 PUBLIC void 1169 athn_set_led(struct athn_softc *sc, int on) 1170 { 1171 struct athn_ops *ops = &sc->sc_ops; 1172 1173 sc->sc_led_state = on; 1174 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1175 } 1176 1177 #ifdef ATHN_BT_COEXISTENCE 1178 Static void 1179 athn_btcoex_init(struct athn_softc *sc) 1180 { 1181 struct athn_ops *ops = &sc->sc_ops; 1182 uint32_t reg; 1183 1184 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1185 /* Connect bt_active to baseband. */ 1186 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1187 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1188 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1189 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1190 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1191 1192 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1193 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1194 AR_GPIO_BTACTIVE_PIN); 1195 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1196 AR_WRITE_BARRIER(sc); 1197 1198 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1199 } else { /* 3-wire. */ 1200 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1201 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1202 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1203 1204 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1205 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1206 AR_GPIO_BTACTIVE_PIN); 1207 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1208 AR_GPIO_BTPRIORITY_PIN); 1209 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1210 AR_WRITE_BARRIER(sc); 1211 1212 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1213 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1214 } 1215 } 1216 1217 Static void 1218 athn_btcoex_enable(struct athn_softc *sc) 1219 { 1220 struct athn_ops *ops = &sc->sc_ops; 1221 uint32_t reg; 1222 1223 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1224 AR_WRITE(sc, AR_BT_COEX_MODE, 1225 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1226 SM(AR_BT_PRIORITY_TIME, 2) | 1227 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1228 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1229 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1230 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1231 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1232 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1233 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1234 AR_WRITE(sc, AR_BT_COEX_MODE2, 1235 SM(AR_BT_BCN_MISS_THRESH, 50) | 1236 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1237 1238 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1239 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1240 AR_WRITE_BARRIER(sc); 1241 1242 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1243 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1244 1245 } else { /* 2-wire. */ 1246 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1247 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1248 } 1249 reg = AR_READ(sc, AR_GPIO_PDPU); 1250 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1251 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1252 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1253 AR_WRITE_BARRIER(sc); 1254 1255 /* Disable PCIe Active State Power Management (ASPM). */ 1256 if (sc->sc_disable_aspm != NULL) 1257 sc->sc_disable_aspm(sc); 1258 1259 /* XXX Start periodic timer. */ 1260 } 1261 1262 Static void 1263 athn_btcoex_disable(struct athn_softc *sc) 1264 { 1265 struct athn_ops *ops = &sc->sc_ops; 1266 1267 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1268 1269 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1270 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1271 1272 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1273 AR_WRITE(sc, AR_BT_COEX_MODE, 1274 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1275 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1276 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1277 /* XXX Stop periodic timer. */ 1278 } 1279 AR_WRITE_BARRIER(sc); 1280 /* XXX Restore ASPM setting? */ 1281 } 1282 #endif 1283 1284 Static void 1285 athn_iter_func(void *arg, struct ieee80211_node *ni) 1286 { 1287 struct athn_softc *sc = arg; 1288 struct athn_node *an = (struct athn_node *)ni; 1289 1290 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1291 } 1292 1293 Static void 1294 athn_calib_to(void *arg) 1295 { 1296 extern int ticks; 1297 struct athn_softc *sc = arg; 1298 struct athn_ops *ops = &sc->sc_ops; 1299 struct ieee80211com *ic = &sc->sc_ic; 1300 int s; 1301 1302 s = splnet(); 1303 1304 /* Do periodic (every 4 minutes) PA calibration. */ 1305 if (AR_SREV_9285_11_OR_LATER(sc) && 1306 !AR_SREV_9380_10_OR_LATER(sc) && 1307 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1308 sc->sc_pa_calib_ticks = ticks; 1309 if (AR_SREV_9271(sc)) 1310 ar9271_pa_calib(sc); 1311 else 1312 ar9285_pa_calib(sc); 1313 } 1314 1315 /* Do periodic (every 30 seconds) temperature compensation. */ 1316 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1317 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1318 sc->sc_olpc_ticks = ticks; 1319 ops->olpc_temp_compensation(sc); 1320 } 1321 1322 #ifdef notyet 1323 /* XXX ANI. */ 1324 athn_ani_monitor(sc); 1325 1326 ops->next_calib(sc); 1327 #endif 1328 if (ic->ic_fixed_rate == -1) { 1329 if (ic->ic_opmode == IEEE80211_M_STA) 1330 athn_iter_func(sc, ic->ic_bss); 1331 else 1332 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1333 } 1334 callout_schedule(&sc->sc_calib_to, hz / 2); 1335 splx(s); 1336 } 1337 1338 Static int 1339 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1340 struct ieee80211_channel *extchan) 1341 { 1342 struct athn_ops *ops = &sc->sc_ops; 1343 int error; 1344 1345 if (AR_SREV_9380_10_OR_LATER(sc)) 1346 error = ar9003_init_calib(sc); 1347 else if (AR_SREV_9285_10_OR_LATER(sc)) 1348 error = ar9285_init_calib(sc, curchan, extchan); 1349 else 1350 error = ar5416_init_calib(sc, curchan, extchan); 1351 if (error != 0) 1352 return error; 1353 1354 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1355 /* Do PA calibration. */ 1356 if (AR_SREV_9285_11_OR_LATER(sc)) { 1357 extern int ticks; 1358 sc->sc_pa_calib_ticks = ticks; 1359 if (AR_SREV_9271(sc)) 1360 ar9271_pa_calib(sc); 1361 else 1362 ar9285_pa_calib(sc); 1363 } 1364 /* Do noisefloor calibration. */ 1365 ops->noisefloor_calib(sc); 1366 } 1367 if (AR_SREV_9160_10_OR_LATER(sc)) { 1368 /* Support IQ calibration. */ 1369 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1370 if (AR_SREV_9380_10_OR_LATER(sc)) { 1371 /* Support temperature compensation calibration. */ 1372 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1373 } else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1374 /* 1375 * ADC gain calibration causes uplink throughput 1376 * drops in HT40 mode on AR9287. 1377 */ 1378 if (!AR_SREV_9287(sc)) { 1379 /* Support ADC gain calibration. */ 1380 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1381 } 1382 /* Support ADC DC offset calibration. */ 1383 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1384 } 1385 } 1386 return 0; 1387 } 1388 1389 /* 1390 * Adaptive noise immunity. 1391 */ 1392 #ifdef notyet 1393 Static int32_t 1394 athn_ani_get_rssi(struct athn_softc *sc) 1395 { 1396 1397 return 0; /* XXX */ 1398 } 1399 #endif /* notyet */ 1400 1401 #ifdef notyet 1402 Static void 1403 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1404 { 1405 struct athn_ani *ani = &sc->sc_ani; 1406 struct athn_ops *ops = &sc->sc_ops; 1407 int32_t rssi; 1408 1409 /* First, raise noise immunity level, up to max. */ 1410 if (ani->noise_immunity_level < 4) { 1411 ani->noise_immunity_level++; 1412 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1413 return; 1414 } 1415 1416 /* Then, raise our spur immunity level, up to max. */ 1417 if (ani->spur_immunity_level < 7) { 1418 ani->spur_immunity_level++; 1419 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1420 return; 1421 } 1422 1423 #ifndef IEEE80211_STA_ONLY 1424 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1425 if (ani->firstep_level < 2) { 1426 ani->firstep_level++; 1427 ops->set_firstep_level(sc, ani->firstep_level); 1428 } 1429 return; 1430 } 1431 #endif 1432 rssi = athn_ani_get_rssi(sc); 1433 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1434 /* 1435 * Beacon RSSI is high, turn off OFDM weak signal detection 1436 * or raise first step level as last resort. 1437 */ 1438 if (ani->ofdm_weak_signal) { 1439 ani->ofdm_weak_signal = 0; 1440 ops->disable_ofdm_weak_signal(sc); 1441 ani->spur_immunity_level = 0; 1442 ops->set_spur_immunity_level(sc, 0); 1443 } else if (ani->firstep_level < 2) { 1444 ani->firstep_level++; 1445 ops->set_firstep_level(sc, ani->firstep_level); 1446 } 1447 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1448 /* 1449 * Beacon RSSI is in mid range, we need OFDM weak signal 1450 * detection but we can raise first step level. 1451 */ 1452 if (!ani->ofdm_weak_signal) { 1453 ani->ofdm_weak_signal = 1; 1454 ops->enable_ofdm_weak_signal(sc); 1455 } 1456 if (ani->firstep_level < 2) { 1457 ani->firstep_level++; 1458 ops->set_firstep_level(sc, ani->firstep_level); 1459 } 1460 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1461 /* 1462 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1463 * signal detection and zero first step level to maximize 1464 * CCK sensitivity. 1465 */ 1466 if (ani->ofdm_weak_signal) { 1467 ani->ofdm_weak_signal = 0; 1468 ops->disable_ofdm_weak_signal(sc); 1469 } 1470 if (ani->firstep_level > 0) { 1471 ani->firstep_level = 0; 1472 ops->set_firstep_level(sc, 0); 1473 } 1474 } 1475 } 1476 #endif /* notyet */ 1477 1478 #ifdef notyet 1479 Static void 1480 athn_ani_cck_err_trigger(struct athn_softc *sc) 1481 { 1482 struct athn_ani *ani = &sc->sc_ani; 1483 struct athn_ops *ops = &sc->sc_ops; 1484 int32_t rssi; 1485 1486 /* Raise noise immunity level, up to max. */ 1487 if (ani->noise_immunity_level < 4) { 1488 ani->noise_immunity_level++; 1489 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1490 return; 1491 } 1492 1493 #ifndef IEEE80211_STA_ONLY 1494 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1495 if (ani->firstep_level < 2) { 1496 ani->firstep_level++; 1497 ops->set_firstep_level(sc, ani->firstep_level); 1498 } 1499 return; 1500 } 1501 #endif 1502 rssi = athn_ani_get_rssi(sc); 1503 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1504 /* 1505 * Beacon RSSI is in mid or high range, raise first step 1506 * level. 1507 */ 1508 if (ani->firstep_level < 2) { 1509 ani->firstep_level++; 1510 ops->set_firstep_level(sc, ani->firstep_level); 1511 } 1512 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1513 /* 1514 * Beacon RSSI is low, zero first step level to maximize 1515 * CCK sensitivity. 1516 */ 1517 if (ani->firstep_level > 0) { 1518 ani->firstep_level = 0; 1519 ops->set_firstep_level(sc, 0); 1520 } 1521 } 1522 } 1523 #endif /* notyet */ 1524 1525 #ifdef notyet 1526 Static void 1527 athn_ani_lower_immunity(struct athn_softc *sc) 1528 { 1529 struct athn_ani *ani = &sc->sc_ani; 1530 struct athn_ops *ops = &sc->sc_ops; 1531 int32_t rssi; 1532 1533 #ifndef IEEE80211_STA_ONLY 1534 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1535 if (ani->firstep_level > 0) { 1536 ani->firstep_level--; 1537 ops->set_firstep_level(sc, ani->firstep_level); 1538 } 1539 return; 1540 } 1541 #endif 1542 rssi = athn_ani_get_rssi(sc); 1543 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1544 /* 1545 * Beacon RSSI is high, leave OFDM weak signal detection 1546 * off or it may oscillate. 1547 */ 1548 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1549 /* 1550 * Beacon RSSI is in mid range, turn on OFDM weak signal 1551 * detection or lower first step level. 1552 */ 1553 if (!ani->ofdm_weak_signal) { 1554 ani->ofdm_weak_signal = 1; 1555 ops->enable_ofdm_weak_signal(sc); 1556 return; 1557 } 1558 if (ani->firstep_level > 0) { 1559 ani->firstep_level--; 1560 ops->set_firstep_level(sc, ani->firstep_level); 1561 return; 1562 } 1563 } else { 1564 /* Beacon RSSI is low, lower first step level. */ 1565 if (ani->firstep_level > 0) { 1566 ani->firstep_level--; 1567 ops->set_firstep_level(sc, ani->firstep_level); 1568 return; 1569 } 1570 } 1571 /* 1572 * Lower spur immunity level down to zero, or if all else fails, 1573 * lower noise immunity level down to zero. 1574 */ 1575 if (ani->spur_immunity_level > 0) { 1576 ani->spur_immunity_level--; 1577 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1578 } else if (ani->noise_immunity_level > 0) { 1579 ani->noise_immunity_level--; 1580 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1581 } 1582 } 1583 #endif /* notyet */ 1584 1585 #ifdef notyet 1586 Static void 1587 athn_ani_restart(struct athn_softc *sc) 1588 { 1589 struct athn_ani *ani = &sc->sc_ani; 1590 1591 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1592 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1593 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1594 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1595 AR_WRITE_BARRIER(sc); 1596 1597 ani->listen_time = 0; 1598 ani->ofdm_phy_err_count = 0; 1599 ani->cck_phy_err_count = 0; 1600 } 1601 #endif /* notyet */ 1602 1603 #ifdef notyet 1604 Static void 1605 athn_ani_monitor(struct athn_softc *sc) 1606 { 1607 struct athn_ani *ani = &sc->sc_ani; 1608 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1609 int32_t cycdelta, txfdelta, rxfdelta; 1610 int32_t listen_time; 1611 1612 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1613 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1614 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1615 1616 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1617 cycdelta = cyccnt - ani->cyccnt; 1618 txfdelta = txfcnt - ani->txfcnt; 1619 rxfdelta = rxfcnt - ani->rxfcnt; 1620 1621 listen_time = (cycdelta - txfdelta - rxfdelta) / 1622 (athn_clock_rate(sc) * 1000); 1623 } else 1624 listen_time = 0; 1625 1626 ani->cyccnt = cyccnt; 1627 ani->txfcnt = txfcnt; 1628 ani->rxfcnt = rxfcnt; 1629 1630 if (listen_time < 0) { 1631 athn_ani_restart(sc); 1632 return; 1633 } 1634 ani->listen_time += listen_time; 1635 1636 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1637 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1638 1639 if (phy1 < ani->ofdm_phy_err_base) { 1640 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1641 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1642 } 1643 if (phy2 < ani->cck_phy_err_base) { 1644 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1645 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1646 } 1647 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1648 AR_WRITE_BARRIER(sc); 1649 return; 1650 } 1651 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1652 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1653 1654 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1655 /* Check to see if we need to lower immunity. */ 1656 if (ani->ofdm_phy_err_count <= 1657 ani->listen_time * ani->ofdm_trig_low / 1000 && 1658 ani->cck_phy_err_count <= 1659 ani->listen_time * ani->cck_trig_low / 1000) 1660 athn_ani_lower_immunity(sc); 1661 athn_ani_restart(sc); 1662 1663 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1664 /* Check to see if we need to raise immunity. */ 1665 if (ani->ofdm_phy_err_count > 1666 ani->listen_time * ani->ofdm_trig_high / 1000) { 1667 athn_ani_ofdm_err_trigger(sc); 1668 athn_ani_restart(sc); 1669 } else if (ani->cck_phy_err_count > 1670 ani->listen_time * ani->cck_trig_high / 1000) { 1671 athn_ani_cck_err_trigger(sc); 1672 athn_ani_restart(sc); 1673 } 1674 } 1675 } 1676 #endif /* notyet */ 1677 1678 PUBLIC uint8_t 1679 athn_chan2fbin(struct ieee80211_channel *c) 1680 { 1681 1682 if (IEEE80211_IS_CHAN_2GHZ(c)) 1683 return c->ic_freq - 2300; 1684 else 1685 return (c->ic_freq - 4800) / 5; 1686 } 1687 1688 PUBLIC int 1689 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1690 { 1691 1692 if (x1 == x2) /* Prevents division by zero. */ 1693 return y1; 1694 /* Linear interpolation. */ 1695 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1696 } 1697 1698 PUBLIC void 1699 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1700 int *lo, int *hi) 1701 { 1702 int i; 1703 1704 for (i = 0; i < npiers; i++) 1705 if (pierfreq[i] == AR_BCHAN_UNUSED || 1706 pierfreq[i] > fbin) 1707 break; 1708 *hi = i; 1709 *lo = *hi - 1; 1710 if (*lo == -1) 1711 *lo = *hi; 1712 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1713 *hi = *lo; 1714 } 1715 1716 Static void 1717 athn_init_dma(struct athn_softc *sc) 1718 { 1719 uint32_t reg; 1720 1721 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1722 /* Set AHB not to do cacheline prefetches. */ 1723 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1724 } 1725 reg = AR_READ(sc, AR_TXCFG); 1726 /* Let MAC DMA reads be in 128-byte chunks. */ 1727 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1728 1729 /* Set initial Tx trigger level. */ 1730 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1731 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1732 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1733 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1734 AR_WRITE(sc, AR_TXCFG, reg); 1735 1736 /* Let MAC DMA writes be in 128-byte chunks. */ 1737 reg = AR_READ(sc, AR_RXCFG); 1738 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1739 AR_WRITE(sc, AR_RXCFG, reg); 1740 1741 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1742 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1743 1744 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1745 if (AR_SREV_9285(sc)) { 1746 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1747 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1748 } else if (!AR_SREV_9271(sc)) { 1749 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1750 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1751 } 1752 AR_WRITE_BARRIER(sc); 1753 1754 /* Reset Tx status ring. */ 1755 if (AR_SREV_9380_10_OR_LATER(sc)) 1756 ar9003_reset_txsring(sc); 1757 } 1758 1759 PUBLIC void 1760 athn_inc_tx_trigger_level(struct athn_softc *sc) 1761 { 1762 uint32_t reg, ftrig; 1763 1764 reg = AR_READ(sc, AR_TXCFG); 1765 ftrig = MS(reg, AR_TXCFG_FTRIG); 1766 /* 1767 * NB: The AR9285 and all single-stream parts have an issue that 1768 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1769 */ 1770 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1771 return; /* Already at max. */ 1772 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1773 AR_WRITE(sc, AR_TXCFG, reg); 1774 AR_WRITE_BARRIER(sc); 1775 } 1776 1777 PUBLIC int 1778 athn_stop_rx_dma(struct athn_softc *sc) 1779 { 1780 int ntries; 1781 1782 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1783 /* Wait for Rx enable bit to go low. */ 1784 for (ntries = 0; ntries < 100; ntries++) { 1785 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1786 return 0; 1787 DELAY(100); 1788 } 1789 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1790 return ETIMEDOUT; 1791 } 1792 1793 #ifdef unused 1794 Static int 1795 athn_rx_abort(struct athn_softc *sc) 1796 { 1797 int ntries; 1798 1799 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1800 for (ntries = 0; ntries < 1000; ntries++) { 1801 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1802 return 0; 1803 DELAY(10); 1804 } 1805 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1806 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1807 AR_WRITE_BARRIER(sc); 1808 return ETIMEDOUT; 1809 } 1810 #endif /* unused */ 1811 1812 Static void 1813 athn_tx_reclaim(struct athn_softc *sc, int qid) 1814 { 1815 struct athn_txq *txq = &sc->sc_txq[qid]; 1816 struct athn_tx_buf *bf; 1817 1818 /* Reclaim all buffers queued in the specified Tx queue. */ 1819 /* NB: Tx DMA must be stopped. */ 1820 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1821 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1822 1823 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1824 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1825 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1826 m_freem(bf->bf_m); 1827 bf->bf_m = NULL; 1828 bf->bf_ni = NULL; /* Nodes already freed! */ 1829 1830 /* Link Tx buffer back to global free list. */ 1831 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1832 } 1833 } 1834 1835 PUBLIC int 1836 athn_tx_pending(struct athn_softc *sc, int qid) 1837 { 1838 1839 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1840 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1841 } 1842 1843 PUBLIC void 1844 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1845 { 1846 uint32_t tsflo; 1847 int ntries, i; 1848 1849 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1850 for (ntries = 0; ntries < 40; ntries++) { 1851 if (!athn_tx_pending(sc, qid)) 1852 break; 1853 DELAY(100); 1854 } 1855 if (ntries == 40) { 1856 for (i = 0; i < 2; i++) { 1857 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1858 AR_WRITE(sc, AR_QUIET2, 1859 SM(AR_QUIET2_QUIET_DUR, 10)); 1860 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1861 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1862 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1863 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1864 break; 1865 } 1866 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1867 AR_WRITE_BARRIER(sc); 1868 DELAY(200); 1869 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1870 AR_WRITE_BARRIER(sc); 1871 1872 for (ntries = 0; ntries < 40; ntries++) { 1873 if (!athn_tx_pending(sc, qid)) 1874 break; 1875 DELAY(100); 1876 } 1877 1878 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1879 } 1880 AR_WRITE(sc, AR_Q_TXD, 0); 1881 AR_WRITE_BARRIER(sc); 1882 } 1883 1884 PUBLIC int 1885 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1886 { 1887 #define divround(a, b) (((a) + (b) - 1) / (b)) 1888 int txtime; 1889 1890 /* XXX HT. */ 1891 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1892 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1893 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1894 txtime = 16 + 4 + 4 * txtime + 16; 1895 } else { 1896 txtime = divround(16 * len, athn_rates[ridx].rate); 1897 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1898 txtime += 72 + 24; 1899 else 1900 txtime += 144 + 48; 1901 txtime += 10; /* 10us SIFS. */ 1902 } 1903 return txtime; 1904 #undef divround 1905 } 1906 1907 PUBLIC void 1908 athn_init_tx_queues(struct athn_softc *sc) 1909 { 1910 int qid; 1911 1912 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1913 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1914 sc->sc_txq[qid].lastds = NULL; 1915 sc->sc_txq[qid].wait = NULL; 1916 sc->sc_txq[qid].queued = 0; 1917 1918 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1919 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1920 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1921 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1922 AR_WRITE(sc, AR_QMISC(qid), 1923 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1924 AR_WRITE(sc, AR_DMISC(qid), 1925 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1926 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1927 } 1928 1929 /* Init beacon queue. */ 1930 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1931 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1932 AR_Q_MISC_CBR_INCR_DIS1); 1933 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1934 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1935 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1936 AR_D_MISC_BEACON_USE | 1937 AR_D_MISC_POST_FR_BKOFF_DIS); 1938 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1939 SM(AR_D_LCL_IFS_CWMIN, 0) | 1940 SM(AR_D_LCL_IFS_CWMAX, 0) | 1941 SM(AR_D_LCL_IFS_AIFS, 1)); 1942 1943 /* Init CAB (Content After Beacon) queue. */ 1944 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1945 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1946 AR_Q_MISC_CBR_INCR_DIS0); 1947 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1948 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1949 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1950 1951 /* Init PS-Poll queue. */ 1952 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1953 AR_Q_MISC_CBR_INCR_DIS1); 1954 1955 /* Init UAPSD queue. */ 1956 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1957 AR_D_MISC_POST_FR_BKOFF_DIS); 1958 1959 if (AR_SREV_9380_10_OR_LATER(sc)) { 1960 /* Enable MAC descriptor CRC check. */ 1961 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1962 } 1963 /* Enable DESC interrupts for all Tx queues. */ 1964 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1965 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1966 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1967 AR_WRITE_BARRIER(sc); 1968 } 1969 1970 PUBLIC void 1971 athn_set_sta_timers(struct athn_softc *sc) 1972 { 1973 struct ieee80211com *ic = &sc->sc_ic; 1974 uint32_t tsfhi, tsflo, tsftu, reg; 1975 uint32_t intval, next_tbtt, next_dtim; 1976 int dtim_period, rem_dtim_count; 1977 1978 tsfhi = AR_READ(sc, AR_TSF_U32); 1979 tsflo = AR_READ(sc, AR_TSF_L32); 1980 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1981 1982 /* Beacon interval in TU. */ 1983 intval = ic->ic_bss->ni_intval; 1984 1985 next_tbtt = roundup(tsftu, intval); 1986 #ifdef notyet 1987 dtim_period = ic->ic_dtim_period; 1988 if (dtim_period <= 0) 1989 #endif 1990 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1991 1992 #ifdef notyet 1993 int dtim_count = ic->ic_dtim_count; 1994 if (dtim_count >= dtim_period) /* Should not happen. */ 1995 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1996 #endif 1997 1998 /* Compute number of remaining TIMs until next DTIM. */ 1999 rem_dtim_count = 0; /* XXX */ 2000 next_dtim = next_tbtt + rem_dtim_count * intval; 2001 2002 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2003 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2004 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2005 2006 /* 2007 * Set the number of consecutive beacons to miss before raising 2008 * a BMISS interrupt to 10. 2009 */ 2010 reg = AR_READ(sc, AR_RSSI_THR); 2011 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2012 AR_WRITE(sc, AR_RSSI_THR, reg); 2013 2014 AR_WRITE(sc, AR_NEXT_DTIM, 2015 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2016 AR_WRITE(sc, AR_NEXT_TIM, 2017 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2018 2019 /* CAB timeout is in 1/8 TU. */ 2020 AR_WRITE(sc, AR_SLEEP1, 2021 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2022 AR_SLEEP1_ASSUME_DTIM); 2023 AR_WRITE(sc, AR_SLEEP2, 2024 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2025 2026 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2027 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2028 2029 AR_SETBITS(sc, AR_TIMER_MODE, 2030 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2031 2032 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2033 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2034 2035 AR_WRITE_BARRIER(sc); 2036 } 2037 2038 #ifndef IEEE80211_STA_ONLY 2039 PUBLIC void 2040 athn_set_hostap_timers(struct athn_softc *sc) 2041 { 2042 struct ieee80211com *ic = &sc->sc_ic; 2043 uint32_t intval, next_tbtt; 2044 2045 /* Beacon interval in TU. */ 2046 intval = ic->ic_bss->ni_intval; 2047 next_tbtt = intval; 2048 2049 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2050 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2051 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2052 AR_WRITE(sc, AR_NEXT_CFP, 2053 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2054 2055 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2056 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2057 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2058 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2059 2060 AR_WRITE(sc, AR_TIMER_MODE, 2061 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2062 2063 AR_WRITE_BARRIER(sc); 2064 } 2065 #endif 2066 2067 PUBLIC void 2068 athn_set_opmode(struct athn_softc *sc) 2069 { 2070 uint32_t reg; 2071 2072 switch (sc->sc_ic.ic_opmode) { 2073 #ifndef IEEE80211_STA_ONLY 2074 case IEEE80211_M_HOSTAP: 2075 reg = AR_READ(sc, AR_STA_ID1); 2076 reg &= ~AR_STA_ID1_ADHOC; 2077 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2078 AR_WRITE(sc, AR_STA_ID1, reg); 2079 2080 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2081 break; 2082 case IEEE80211_M_IBSS: 2083 case IEEE80211_M_AHDEMO: 2084 reg = AR_READ(sc, AR_STA_ID1); 2085 reg &= ~AR_STA_ID1_STA_AP; 2086 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2087 AR_WRITE(sc, AR_STA_ID1, reg); 2088 2089 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2090 break; 2091 #endif 2092 default: 2093 reg = AR_READ(sc, AR_STA_ID1); 2094 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2095 reg |= AR_STA_ID1_KSRCH_MODE; 2096 AR_WRITE(sc, AR_STA_ID1, reg); 2097 break; 2098 } 2099 AR_WRITE_BARRIER(sc); 2100 } 2101 2102 PUBLIC void 2103 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2104 { 2105 const uint8_t *bssid = ni->ni_bssid; 2106 2107 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2108 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2109 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2110 AR_WRITE_BARRIER(sc); 2111 } 2112 2113 Static void 2114 athn_enable_interrupts(struct athn_softc *sc) 2115 { 2116 uint32_t mask2; 2117 2118 athn_disable_interrupts(sc); /* XXX */ 2119 2120 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2121 2122 mask2 = AR_READ(sc, AR_IMR_S2); 2123 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2124 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2125 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2126 AR_WRITE(sc, AR_IMR_S2, mask2); 2127 2128 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2129 2130 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2131 2132 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2133 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2134 2135 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2136 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2137 AR_WRITE_BARRIER(sc); 2138 } 2139 2140 Static void 2141 athn_disable_interrupts(struct athn_softc *sc) 2142 { 2143 2144 AR_WRITE(sc, AR_IER, 0); 2145 (void)AR_READ(sc, AR_IER); 2146 2147 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2148 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2149 2150 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2151 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2152 2153 AR_WRITE(sc, AR_IMR, 0); 2154 2155 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2156 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2157 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2158 2159 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2160 AR_WRITE_BARRIER(sc); 2161 } 2162 2163 Static void 2164 athn_init_qos(struct athn_softc *sc) 2165 { 2166 2167 /* Initialize QoS settings. */ 2168 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2169 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2170 AR_WRITE(sc, AR_QOS_NO_ACK, 2171 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2172 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2173 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2174 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2175 /* Initialize TXOP for all TIDs. */ 2176 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2177 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2178 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2179 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2180 AR_WRITE_BARRIER(sc); 2181 } 2182 2183 PUBLIC int 2184 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2185 struct ieee80211_channel *extchan, int init) 2186 { 2187 struct ieee80211com *ic = &sc->sc_ic; 2188 struct athn_ops *ops = &sc->sc_ops; 2189 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2190 int i, error; 2191 2192 /* XXX not if already awake */ 2193 if ((error = athn_set_power_awake(sc)) != 0) { 2194 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2195 return error; 2196 } 2197 2198 /* Preserve the antenna on a channel switch. */ 2199 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2200 def_ant = 1; 2201 /* Preserve other registers. */ 2202 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2203 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2204 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2205 AR_CFG_LED_BLINK_SLOW); 2206 2207 /* Mark PHY as inactive. */ 2208 ops->disable_phy(sc); 2209 2210 if (init && AR_SREV_9271(sc)) { 2211 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2212 AR9271_RADIO_RF_RST); 2213 DELAY(50); 2214 } 2215 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2216 /* Save TSF before it gets cleared. */ 2217 tsfhi = AR_READ(sc, AR_TSF_U32); 2218 tsflo = AR_READ(sc, AR_TSF_L32); 2219 2220 /* NB: RTC reset clears TSF. */ 2221 error = athn_reset_power_on(sc); 2222 } else { 2223 tsfhi = tsflo = 0; /* XXX: gcc */ 2224 error = athn_reset(sc, 0); 2225 } 2226 if (error != 0) { 2227 aprint_error_dev(sc->sc_dev, 2228 "could not reset chip (error=%d)\n", error); 2229 return error; 2230 } 2231 2232 /* XXX not if already awake */ 2233 if ((error = athn_set_power_awake(sc)) != 0) { 2234 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2235 return error; 2236 } 2237 2238 athn_init_pll(sc, curchan); 2239 ops->set_rf_mode(sc, curchan); 2240 2241 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2242 /* Check that the radio is not disabled by hardware switch. */ 2243 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2244 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2245 reg = !reg; 2246 if (!reg) { 2247 aprint_error_dev(sc->sc_dev, 2248 "radio is disabled by hardware switch\n"); 2249 return EPERM; 2250 } 2251 } 2252 if (init && AR_SREV_9271(sc)) { 2253 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2254 AR9271_GATE_MAC_CTL); 2255 DELAY(50); 2256 } 2257 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2258 /* Restore TSF if it got cleared. */ 2259 AR_WRITE(sc, AR_TSF_L32, tsflo); 2260 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2261 } 2262 2263 if (AR_SREV_9280_10_OR_LATER(sc)) 2264 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2265 2266 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2267 ar9287_1_3_enable_async_fifo(sc); 2268 2269 /* Write init values to hardware. */ 2270 ops->hw_init(sc, curchan, extchan); 2271 2272 /* 2273 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2274 * management frames using CCMP. 2275 */ 2276 if (AR_SREV_9280_20_OR_LATER(sc)) { 2277 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2278 /* Do not mask the subtype field in management frames. */ 2279 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2280 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2281 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2282 IEEE80211_FC1_MORE_DATA)); 2283 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2284 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2285 /* Disable hardware crypto for management frames. */ 2286 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2287 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2288 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2289 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2290 } 2291 2292 if (ic->ic_curmode != IEEE80211_MODE_11B) 2293 ops->set_delta_slope(sc, curchan, extchan); 2294 2295 ops->spur_mitigate(sc, curchan, extchan); 2296 ops->init_from_rom(sc, curchan, extchan); 2297 2298 /* XXX */ 2299 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2300 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2301 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2302 2303 athn_set_opmode(sc); 2304 2305 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2306 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2307 2308 /* Restore previous antenna. */ 2309 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2310 2311 AR_WRITE(sc, AR_BSS_ID0, 0); 2312 AR_WRITE(sc, AR_BSS_ID1, 0); 2313 2314 AR_WRITE(sc, AR_ISR, 0xffffffff); 2315 2316 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2317 2318 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2319 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2320 return error; 2321 } 2322 sc->sc_curchan = curchan; 2323 sc->sc_curchanext = extchan; 2324 2325 for (i = 0; i < AR_NUM_DCU; i++) 2326 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2327 2328 athn_init_tx_queues(sc); 2329 2330 /* Initialize interrupt mask. */ 2331 sc->sc_imask = 2332 AR_IMR_TXDESC | AR_IMR_TXEOL | 2333 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2334 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2335 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2336 if (AR_SREV_9380_10_OR_LATER(sc)) 2337 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2338 #ifndef IEEE80211_STA_ONLY 2339 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2340 sc->sc_imask |= AR_IMR_MIB; 2341 #endif 2342 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2343 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2344 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2345 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2346 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2347 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2348 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2349 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2350 if (AR_SREV_9380_10_OR_LATER(sc)) { 2351 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2352 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2353 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2354 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2355 } 2356 2357 athn_init_qos(sc); 2358 2359 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2360 2361 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2362 ar9287_1_3_setup_async_fifo(sc); 2363 2364 /* Disable sequence number generation in hardware. */ 2365 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2366 2367 athn_init_dma(sc); 2368 2369 /* Program observation bus to see MAC interrupts. */ 2370 AR_WRITE(sc, sc->sc_obs_off, 8); 2371 2372 /* Setup Rx interrupt mitigation. */ 2373 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2374 2375 ops->init_baseband(sc); 2376 2377 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2378 aprint_error_dev(sc->sc_dev, 2379 "could not initialize calibration\n"); 2380 return error; 2381 } 2382 2383 ops->set_rxchains(sc); 2384 2385 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2386 2387 if (sc->sc_flags & ATHN_FLAG_USB) { 2388 if (AR_SREV_9271(sc)) 2389 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2390 else 2391 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2392 } 2393 #if BYTE_ORDER == BIG_ENDIAN 2394 else { 2395 /* Default is LE, turn on swapping for BE. */ 2396 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2397 } 2398 #endif 2399 AR_WRITE_BARRIER(sc); 2400 2401 return 0; 2402 } 2403 2404 Static struct ieee80211_node * 2405 athn_node_alloc(struct ieee80211_node_table *ntp) 2406 { 2407 2408 return malloc(sizeof(struct athn_node), M_DEVBUF, 2409 M_NOWAIT | M_ZERO); 2410 } 2411 2412 Static void 2413 athn_newassoc(struct ieee80211_node *ni, int isnew) 2414 { 2415 struct ieee80211com *ic = ni->ni_ic; 2416 struct athn_softc *sc = ic->ic_ifp->if_softc; 2417 struct athn_node *an = (void *)ni; 2418 struct ieee80211_rateset *rs = &ni->ni_rates; 2419 uint8_t rate; 2420 int ridx, i, j; 2421 2422 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2423 /* Start at lowest available bit-rate, AMRR will raise. */ 2424 ni->ni_txrate = 0; 2425 2426 for (i = 0; i < rs->rs_nrates; i++) { 2427 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2428 2429 /* Map 802.11 rate to HW rate index. */ 2430 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2431 if (athn_rates[ridx].rate == rate) 2432 break; 2433 an->ridx[i] = ridx; 2434 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2435 2436 /* Compute fallback rate for retries. */ 2437 an->fallback[i] = i; 2438 for (j = i - 1; j >= 0; j--) { 2439 if (athn_rates[an->ridx[j]].phy == 2440 athn_rates[an->ridx[i]].phy) { 2441 an->fallback[i] = j; 2442 break; 2443 } 2444 } 2445 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2446 i, an->fallback[i]); 2447 } 2448 } 2449 2450 Static int 2451 athn_media_change(struct ifnet *ifp) 2452 { 2453 struct athn_softc *sc = ifp->if_softc; 2454 struct ieee80211com *ic = &sc->sc_ic; 2455 uint8_t rate, ridx; 2456 int error; 2457 2458 error = ieee80211_media_change(ifp); 2459 if (error != ENETRESET) 2460 return error; 2461 2462 if (ic->ic_fixed_rate != -1) { 2463 rate = ic->ic_sup_rates[ic->ic_curmode]. 2464 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2465 /* Map 802.11 rate to HW rate index. */ 2466 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2467 if (athn_rates[ridx].rate == rate) 2468 break; 2469 sc->sc_fixed_ridx = ridx; 2470 } 2471 if (IS_UP_AND_RUNNING(ifp)) { 2472 athn_stop(ifp, 0); 2473 error = athn_init(ifp); 2474 } 2475 return error; 2476 } 2477 2478 Static void 2479 athn_next_scan(void *arg) 2480 { 2481 struct athn_softc *sc = arg; 2482 struct ieee80211com *ic = &sc->sc_ic; 2483 int s; 2484 2485 s = splnet(); 2486 if (ic->ic_state == IEEE80211_S_SCAN) 2487 ieee80211_next_scan(ic); 2488 splx(s); 2489 } 2490 2491 Static int 2492 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2493 { 2494 struct ifnet *ifp = ic->ic_ifp; 2495 struct athn_softc *sc = ifp->if_softc; 2496 uint32_t reg; 2497 int error; 2498 2499 callout_stop(&sc->sc_calib_to); 2500 2501 switch (nstate) { 2502 case IEEE80211_S_INIT: 2503 athn_set_led(sc, 0); 2504 break; 2505 case IEEE80211_S_SCAN: 2506 /* Make the LED blink while scanning. */ 2507 athn_set_led(sc, !sc->sc_led_state); 2508 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2509 if (error != 0) 2510 return error; 2511 callout_schedule(&sc->sc_scan_to, hz / 5); 2512 break; 2513 case IEEE80211_S_AUTH: 2514 athn_set_led(sc, 0); 2515 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2516 if (error != 0) 2517 return error; 2518 break; 2519 case IEEE80211_S_ASSOC: 2520 break; 2521 case IEEE80211_S_RUN: 2522 athn_set_led(sc, 1); 2523 2524 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2525 break; 2526 2527 /* Fake a join to initialize the Tx rate. */ 2528 athn_newassoc(ic->ic_bss, 1); 2529 2530 athn_set_bss(sc, ic->ic_bss); 2531 athn_disable_interrupts(sc); 2532 #ifndef IEEE80211_STA_ONLY 2533 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2534 athn_set_hostap_timers(sc); 2535 /* Enable software beacon alert interrupts. */ 2536 sc->sc_imask |= AR_IMR_SWBA; 2537 } else 2538 #endif 2539 { 2540 athn_set_sta_timers(sc); 2541 /* Enable beacon miss interrupts. */ 2542 sc->sc_imask |= AR_IMR_BMISS; 2543 2544 /* Stop receiving beacons from other BSS. */ 2545 reg = AR_READ(sc, AR_RX_FILTER); 2546 reg = (reg & ~AR_RX_FILTER_BEACON) | 2547 AR_RX_FILTER_MYBEACON; 2548 AR_WRITE(sc, AR_RX_FILTER, reg); 2549 AR_WRITE_BARRIER(sc); 2550 } 2551 athn_enable_interrupts(sc); 2552 2553 if (sc->sc_sup_calib_mask != 0) { 2554 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2555 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2556 /* ops->do_calib(sc); */ 2557 } 2558 /* XXX Start ANI. */ 2559 2560 callout_schedule(&sc->sc_calib_to, hz / 2); 2561 break; 2562 } 2563 2564 return sc->sc_newstate(ic, nstate, arg); 2565 } 2566 2567 #ifdef notyet_edca 2568 PUBLIC void 2569 athn_updateedca(struct ieee80211com *ic) 2570 { 2571 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2572 struct athn_softc *sc = ic->ic_ifp->if_softc; 2573 const struct ieee80211_edca_ac_params *ac; 2574 int aci, qid; 2575 2576 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2577 ac = &ic->ic_edca_ac[aci]; 2578 qid = athn_ac2qid[aci]; 2579 2580 AR_WRITE(sc, AR_DLCL_IFS(qid), 2581 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2582 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2583 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2584 if (ac->ac_txoplimit != 0) { 2585 AR_WRITE(sc, AR_DCHNTIME(qid), 2586 SM(AR_D_CHNTIME_DUR, 2587 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2588 AR_D_CHNTIME_EN); 2589 } else 2590 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2591 } 2592 AR_WRITE_BARRIER(sc); 2593 #undef ATHN_EXP2 2594 } 2595 #endif /* notyet_edca */ 2596 2597 Static int 2598 athn_clock_rate(struct athn_softc *sc) 2599 { 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 int clockrate; /* MHz. */ 2602 2603 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2604 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2605 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2606 else 2607 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2608 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2609 clockrate = AR_CLOCK_RATE_CCK; 2610 } else 2611 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2612 #ifndef IEEE80211_NO_HT 2613 if (sc->sc_curchanext != NULL) 2614 clockrate *= 2; 2615 #endif 2616 return clockrate; 2617 } 2618 2619 PUBLIC void 2620 athn_updateslot(struct ifnet *ifp) 2621 { 2622 struct athn_softc *sc = ifp->if_softc; 2623 struct ieee80211com *ic = &sc->sc_ic; 2624 int slot; 2625 2626 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2627 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2628 AR_WRITE_BARRIER(sc); 2629 } 2630 2631 Static void 2632 athn_start(struct ifnet *ifp) 2633 { 2634 struct athn_softc *sc = ifp->if_softc; 2635 struct ieee80211com *ic = &sc->sc_ic; 2636 struct ether_header *eh; 2637 struct ieee80211_node *ni; 2638 struct mbuf *m; 2639 2640 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2641 || !device_is_active(sc->sc_dev)) 2642 return; 2643 2644 for (;;) { 2645 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2646 ifp->if_flags |= IFF_OACTIVE; 2647 break; 2648 } 2649 /* Send pending management frames first. */ 2650 IF_DEQUEUE(&ic->ic_mgtq, m); 2651 if (m != NULL) { 2652 ni = M_GETCTX(m, struct ieee80211_node *); 2653 goto sendit; 2654 } 2655 if (ic->ic_state != IEEE80211_S_RUN) 2656 break; 2657 2658 /* Encapsulate and send data frames. */ 2659 IFQ_DEQUEUE(&ifp->if_snd, m); 2660 if (m == NULL) 2661 break; 2662 2663 if (m->m_len < (int)sizeof(*eh) && 2664 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2665 if_statinc(ifp, if_oerrors); 2666 continue; 2667 } 2668 eh = mtod(m, struct ether_header *); 2669 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2670 if (ni == NULL) { 2671 m_freem(m); 2672 if_statinc(ifp, if_oerrors); 2673 continue; 2674 } 2675 2676 bpf_mtap(ifp, m, BPF_D_OUT); 2677 2678 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2679 continue; 2680 sendit: 2681 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2682 2683 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2684 ieee80211_free_node(ni); 2685 if_statinc(ifp, if_oerrors); 2686 continue; 2687 } 2688 2689 sc->sc_tx_timer = 5; 2690 ifp->if_timer = 1; 2691 } 2692 } 2693 2694 Static void 2695 athn_watchdog(struct ifnet *ifp) 2696 { 2697 struct athn_softc *sc = ifp->if_softc; 2698 2699 ifp->if_timer = 0; 2700 2701 if (sc->sc_tx_timer > 0) { 2702 if (--sc->sc_tx_timer == 0) { 2703 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2704 /* see athn_init, no need to call athn_stop here */ 2705 /* athn_stop(ifp, 0); */ 2706 (void)athn_init(ifp); 2707 if_statinc(ifp, if_oerrors); 2708 return; 2709 } 2710 ifp->if_timer = 1; 2711 } 2712 ieee80211_watchdog(&sc->sc_ic); 2713 } 2714 2715 Static void 2716 athn_set_multi(struct athn_softc *sc) 2717 { 2718 struct ethercom *ec = &sc->sc_ec; 2719 struct ifnet *ifp = &ec->ec_if; 2720 struct ether_multi *enm; 2721 struct ether_multistep step; 2722 const uint8_t *addr; 2723 uint32_t val, lo, hi; 2724 uint8_t bit; 2725 2726 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2727 lo = hi = 0xffffffff; 2728 goto done2; 2729 } 2730 lo = hi = 0; 2731 ETHER_LOCK(ec); 2732 ETHER_FIRST_MULTI(step, ec, enm); 2733 while (enm != NULL) { 2734 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2735 ifp->if_flags |= IFF_ALLMULTI; 2736 lo = hi = 0xffffffff; 2737 goto done; 2738 } 2739 addr = enm->enm_addrlo; 2740 /* Calculate the XOR value of all eight 6-bit words. */ 2741 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2742 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2743 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2744 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2745 bit &= 0x3f; 2746 if (bit < 32) 2747 lo |= 1 << bit; 2748 else 2749 hi |= 1 << (bit - 32); 2750 ETHER_NEXT_MULTI(step, enm); 2751 } 2752 done: 2753 ETHER_UNLOCK(ec); 2754 done2: 2755 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2756 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2757 AR_WRITE_BARRIER(sc); 2758 } 2759 2760 Static int 2761 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2762 { 2763 struct athn_softc *sc = ifp->if_softc; 2764 struct ieee80211com *ic = &sc->sc_ic; 2765 int s, error = 0; 2766 2767 s = splnet(); 2768 2769 switch (cmd) { 2770 case SIOCSIFFLAGS: 2771 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2772 break; 2773 2774 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2775 case IFF_UP | IFF_RUNNING: 2776 #ifdef notyet 2777 if (((ifp->if_flags ^ sc->sc_if_flags) & 2778 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2779 /* XXX: setup multi */ 2780 #endif 2781 break; 2782 case IFF_UP: 2783 athn_init(ifp); 2784 break; 2785 2786 case IFF_RUNNING: 2787 athn_stop(ifp, 1); 2788 break; 2789 case 0: 2790 default: 2791 break; 2792 } 2793 sc->sc_if_flags = ifp->if_flags; 2794 break; 2795 2796 case SIOCADDMULTI: 2797 case SIOCDELMULTI: 2798 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2799 /* setup multicast filter, etc */ 2800 athn_set_multi(sc); 2801 error = 0; 2802 } 2803 break; 2804 2805 case SIOCS80211CHANNEL: 2806 error = ieee80211_ioctl(ic, cmd, data); 2807 if (error == ENETRESET && 2808 ic->ic_opmode == IEEE80211_M_MONITOR) { 2809 if (IS_UP_AND_RUNNING(ifp)) 2810 athn_switch_chan(sc, ic->ic_curchan, NULL); 2811 error = 0; 2812 } 2813 break; 2814 2815 default: 2816 error = ieee80211_ioctl(ic, cmd, data); 2817 } 2818 2819 if (error == ENETRESET) { 2820 error = 0; 2821 if (IS_UP_AND_RUNNING(ifp) && 2822 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2823 athn_stop(ifp, 0); 2824 error = athn_init(ifp); 2825 } 2826 } 2827 2828 splx(s); 2829 return error; 2830 } 2831 2832 Static int 2833 athn_init(struct ifnet *ifp) 2834 { 2835 struct athn_softc *sc = ifp->if_softc; 2836 struct athn_ops *ops = &sc->sc_ops; 2837 struct ieee80211com *ic = &sc->sc_ic; 2838 struct ieee80211_channel *curchan, *extchan; 2839 size_t i; 2840 int error; 2841 2842 KASSERT(!cpu_intr_p()); 2843 2844 if (device_is_active(sc->sc_dev)) { 2845 athn_stop(ifp, 0); /* see athn_watchdog() */ 2846 } else { 2847 short flags = ifp->if_flags; 2848 ifp->if_flags &= ~IFF_UP; 2849 /* avoid recursion in athn_resume */ 2850 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2851 !device_is_active(sc->sc_dev)) { 2852 printf("%s: failed to power up device\n", 2853 device_xname(sc->sc_dev)); 2854 return 0; 2855 } 2856 ifp->if_flags = flags; 2857 } 2858 2859 curchan = ic->ic_curchan; 2860 extchan = NULL; 2861 2862 /* In case a new MAC address has been configured. */ 2863 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2864 2865 #ifdef openbsd_power_management 2866 /* For CardBus, power on the socket. */ 2867 if (sc->sc_enable != NULL) { 2868 if ((error = sc->sc_enable(sc)) != 0) { 2869 aprint_error_dev(sc->sc_dev, 2870 "could not enable device\n"); 2871 goto fail; 2872 } 2873 if ((error = athn_reset_power_on(sc)) != 0) { 2874 aprint_error_dev(sc->sc_dev, 2875 "could not power on device\n"); 2876 goto fail; 2877 } 2878 } 2879 #endif 2880 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2881 athn_config_nonpcie(sc); 2882 else 2883 athn_config_pcie(sc); 2884 2885 /* Reset HW key cache entries. */ 2886 for (i = 0; i < sc->sc_kc_entries; i++) 2887 athn_reset_key(sc, i); 2888 2889 ops->enable_antenna_diversity(sc); 2890 2891 #ifdef ATHN_BT_COEXISTENCE 2892 /* Configure bluetooth coexistence for combo chips. */ 2893 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2894 athn_btcoex_init(sc); 2895 #endif 2896 2897 /* Configure LED. */ 2898 athn_led_init(sc); 2899 2900 /* Configure hardware radio switch. */ 2901 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2902 ops->rfsilent_init(sc); 2903 2904 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2905 aprint_error_dev(sc->sc_dev, 2906 "unable to reset hardware; reset status %d\n", error); 2907 goto fail; 2908 } 2909 2910 /* Enable Rx. */ 2911 athn_rx_start(sc); 2912 2913 /* Enable interrupts. */ 2914 athn_enable_interrupts(sc); 2915 2916 #ifdef ATHN_BT_COEXISTENCE 2917 /* Enable bluetooth coexistence for combo chips. */ 2918 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2919 athn_btcoex_enable(sc); 2920 #endif 2921 2922 ifp->if_flags &= ~IFF_OACTIVE; 2923 ifp->if_flags |= IFF_RUNNING; 2924 2925 #ifdef notyet 2926 if (ic->ic_flags & IEEE80211_F_WEPON) { 2927 /* Configure WEP keys. */ 2928 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2929 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2930 } 2931 #endif 2932 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2933 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2934 else 2935 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2936 2937 return 0; 2938 fail: 2939 athn_stop(ifp, 1); 2940 return error; 2941 } 2942 2943 PUBLIC void 2944 athn_stop(struct ifnet *ifp, int disable) 2945 { 2946 struct athn_softc *sc = ifp->if_softc; 2947 struct ieee80211com *ic = &sc->sc_ic; 2948 int qid; 2949 2950 ifp->if_timer = sc->sc_tx_timer = 0; 2951 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2952 2953 callout_stop(&sc->sc_scan_to); 2954 /* In case we were scanning, release the scan "lock". */ 2955 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2956 2957 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2958 2959 #ifdef ATHN_BT_COEXISTENCE 2960 /* Disable bluetooth coexistence for combo chips. */ 2961 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2962 athn_btcoex_disable(sc); 2963 #endif 2964 2965 /* Disable interrupts. */ 2966 athn_disable_interrupts(sc); 2967 /* Acknowledge interrupts (avoids interrupt storms). */ 2968 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2969 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2970 2971 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2972 athn_stop_tx_dma(sc, qid); 2973 /* XXX call athn_hw_reset if Tx still pending? */ 2974 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2975 athn_tx_reclaim(sc, qid); 2976 2977 /* Stop Rx. */ 2978 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2979 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2980 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2981 AR_WRITE(sc, AR_FILT_OFDM, 0); 2982 AR_WRITE(sc, AR_FILT_CCK, 0); 2983 AR_WRITE_BARRIER(sc); 2984 athn_set_rxfilter(sc, 0); 2985 athn_stop_rx_dma(sc); 2986 2987 athn_reset(sc, 0); 2988 athn_init_pll(sc, NULL); 2989 athn_set_power_awake(sc); 2990 athn_reset(sc, 1); 2991 athn_init_pll(sc, NULL); 2992 2993 athn_set_power_sleep(sc); 2994 2995 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 2996 /* For CardBus, power down the socket. */ 2997 if (disable && sc->sc_disable != NULL) 2998 sc->sc_disable(sc); 2999 #endif 3000 if (disable) 3001 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3002 } 3003 3004 Static void 3005 athn_pmf_wlan_off(device_t self) 3006 { 3007 struct athn_softc *sc = device_private(self); 3008 struct ifnet *ifp = &sc->sc_if; 3009 3010 /* Turn the interface down. */ 3011 ifp->if_flags &= ~IFF_UP; 3012 athn_stop(ifp, 1); 3013 } 3014 3015 PUBLIC void 3016 athn_suspend(struct athn_softc *sc) 3017 { 3018 struct ifnet *ifp = &sc->sc_if; 3019 3020 if (ifp->if_flags & IFF_RUNNING) 3021 athn_stop(ifp, 1); 3022 } 3023 3024 PUBLIC bool 3025 athn_resume(struct athn_softc *sc) 3026 { 3027 struct ifnet *ifp = &sc->sc_if; 3028 3029 if (ifp->if_flags & IFF_UP) 3030 athn_init(ifp); 3031 3032 return true; 3033 } 3034
Indexes created Thu Sep 25 16:09:42 GMT 2025