athnreg.h revision 1.1
1 /* $NetBSD: athnreg.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */ 2 /* $OpenBSD: athnreg.h,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2009 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #ifndef _ATHNREG_H_ 22 #define _ATHNREG_H_ 23 24 /* 25 * MAC registers. 26 */ 27 #define AR_CR 0x0008 28 #define AR_RXDP 0x000c 29 #define AR_CFG 0x0014 30 #define AR_RXBP_THRESH 0x0018 31 #define AR_MIRT 0x0020 32 #define AR_IER 0x0024 33 #define AR_TIMT 0x0028 34 #define AR_RIMT 0x002c 35 #define AR_TXCFG 0x0030 36 #define AR_RXCFG 0x0034 37 #define AR_MIBC 0x0040 38 #define AR_TOPS 0x0044 39 #define AR_RXNPTO 0x0048 40 #define AR_TXNPTO 0x004c 41 #define AR_RPGTO 0x0050 42 #define AR_RPCNT 0x0054 43 #define AR_MACMISC 0x0058 44 #define AR_DATABUF_SIZE 0x0060 45 #define AR_GTXTO 0x0064 46 #define AR_GTTM 0x0068 47 #define AR_CST 0x006c 48 #define AR_HP_RXDP 0x0074 49 #define AR_LP_RXDP 0x0078 50 #define AR_ISR 0x0080 51 #define AR_ISR_S0 0x0084 52 #define AR_ISR_S1 0x0088 53 #define AR_ISR_S2 0x008c 54 #define AR_ISR_S3 0x0090 55 #define AR_ISR_S4 0x0094 56 #define AR_ISR_S5 0x0098 57 #define AR_IMR 0x00a0 58 #define AR_IMR_S0 0x00a4 59 #define AR_IMR_S1 0x00a8 60 #define AR_IMR_S2 0x00ac 61 #define AR_IMR_S3 0x00b0 62 #define AR_IMR_S4 0x00b4 63 #define AR_IMR_S5 0x00b8 64 #define AR_ISR_RAC 0x00c0 65 #define AR_ISR_S0_S 0x00c4 66 #define AR_ISR_S1_S 0x00c8 67 #define AR_DMADBG(i) (0x00e0 + (i) * 4) 68 #define AR_QTXDP(i) (0x0800 + (i) * 4) 69 #define AR_Q_STATUS_RING_START 0x0830 70 #define AR_Q_STATUS_RING_END 0x0834 71 #define AR_Q_TXE 0x0840 72 #define AR_Q_TXD 0x0880 73 #define AR_QCBRCFG(i) (0x08c0 + (i) * 4) 74 #define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4) 75 #define AR_Q_ONESHOTARM_SC 0x0940 76 #define AR_Q_ONESHOTARM_CC 0x0980 77 #define AR_QMISC(i) (0x09c0 + (i) * 4) 78 #define AR_QSTS(i) (0x0a00 + (i) * 4) 79 #define AR_Q_RDYTIMESHDN 0x0a40 80 #define AR_Q_DESC_CRCCHK 0x0a44 81 #define AR_DQCUMASK(i) (0x1000 + (i) * 4) 82 #define AR_D_GBL_IFS_SIFS 0x1030 83 #define AR_D_TXBLK_CMD 0x1038 84 #define AR_DLCL_IFS(i) (0x1040 + (i) * 4) 85 #define AR_D_GBL_IFS_SLOT 0x1070 86 #define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4) 87 #define AR_D_GBL_IFS_EIFS 0x10b0 88 #define AR_DCHNTIME(i) (0x10c0 + (i) * 4) 89 #define AR_D_GBL_IFS_MISC 0x10f0 90 #define AR_DMISC(i) (0x1100 + (i) * 4) 91 #define AR_D_SEQNUM 0x1140 92 #define AR_D_FPCTL 0x1230 93 #define AR_D_TXPSE 0x1270 94 #define AR_D_TXSLOTMASK 0x12f0 95 #define AR_MAC_SLEEP 0x1f00 96 #define AR_CFG_LED 0x1f04 97 #define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4) 98 #define AR_RC 0x4000 99 #define AR_WA 0x4004 100 #define AR_PM_STATE 0x4008 101 #define AR_PCIE_PM_CTRL 0x4014 102 #define AR_HOST_TIMEOUT 0x4018 103 #define AR_EEPROM 0x401c 104 #define AR_SREV 0x4020 105 #define AR_AHB_MODE 0x4024 106 #define AR_INTR_SYNC_CAUSE 0x4028 107 #define AR_INTR_SYNC_ENABLE 0x402c 108 #define AR_INTR_ASYNC_MASK 0x4030 109 #define AR_INTR_SYNC_MASK 0x4034 110 #define AR_INTR_ASYNC_CAUSE 0x4038 111 #define AR_INTR_ASYNC_ENABLE 0x403c 112 #define AR_PCIE_SERDES 0x4040 113 #define AR_PCIE_SERDES2 0x4044 114 #define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 115 #define AR_INTR_PRIO_ASYNC_MASK 0x40c8 116 #define AR_INTR_PRIO_SYNC_MASK 0x40cc 117 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 118 #define AR_RTC_RC 0x7000 119 #define AR_RTC_XTAL_CONTROL 0x7004 120 #define AR_RTC_REG_CONTROL0 0x7008 121 #define AR_RTC_REG_CONTROL1 0x700c 122 #define AR_RTC_PLL_CONTROL 0x7014 123 #define AR_RTC_PLL_CONTROL2 0x703c 124 #define AR_RTC_RESET 0x7040 125 #define AR_RTC_STATUS 0x7044 126 #define AR_RTC_SLEEP_CLK 0x7048 127 #define AR_RTC_FORCE_WAKE 0x704c 128 #define AR_RTC_INTR_CAUSE 0x7050 129 #define AR_RTC_INTR_ENABLE 0x7054 130 #define AR_RTC_INTR_MASK 0x7058 131 #define AR_STA_ID0 0x8000 132 #define AR_STA_ID1 0x8004 133 #define AR_BSS_ID0 0x8008 134 #define AR_BSS_ID1 0x800c 135 #define AR_BCN_RSSI_AVE 0x8010 136 #define AR_TIME_OUT 0x8014 137 #define AR_RSSI_THR 0x8018 138 #define AR_USEC 0x801c 139 #define AR_RESET_TSF 0x8020 140 #define AR_MAX_CFP_DUR 0x8038 141 #define AR_RX_FILTER 0x803c 142 #define AR_MCAST_FIL0 0x8040 143 #define AR_MCAST_FIL1 0x8044 144 #define AR_DIAG_SW 0x8048 145 #define AR_TSF_L32 0x804c 146 #define AR_TSF_U32 0x8050 147 #define AR_TST_ADDAC 0x8054 148 #define AR_DEF_ANTENNA 0x8058 149 #define AR_AES_MUTE_MASK0 0x805c 150 #define AR_AES_MUTE_MASK1 0x8060 151 #define AR_GATED_CLKS 0x8064 152 #define AR_OBS_BUS_CTRL 0x8068 153 #define AR_OBS_BUS_1 0x806c 154 #define AR_LAST_TSTP 0x8080 155 #define AR_NAV 0x8084 156 #define AR_RTS_OK 0x8088 157 #define AR_RTS_FAIL 0x808c 158 #define AR_ACK_FAIL 0x8090 159 #define AR_FCS_FAIL 0x8094 160 #define AR_BEACON_CNT 0x8098 161 #define AR_SLEEP1 0x80d4 162 #define AR_SLEEP2 0x80d8 163 #define AR_BSSMSKL 0x80e0 164 #define AR_BSSMSKU 0x80e4 165 #define AR_TPC 0x80e8 166 #define AR_TFCNT 0x80ec 167 #define AR_RFCNT 0x80f0 168 #define AR_RCCNT 0x80f4 169 #define AR_CCCNT 0x80f8 170 #define AR_QUIET1 0x80fc 171 #define AR_QUIET2 0x8100 172 #define AR_TSF_PARM 0x8104 173 #define AR_QOS_NO_ACK 0x8108 174 #define AR_PHY_ERR 0x810c 175 #define AR_RXFIFO_CFG 0x8114 176 #define AR_MIC_QOS_CONTROL 0x8118 177 #define AR_MIC_QOS_SELECT 0x811c 178 #define AR_PCU_MISC 0x8120 179 #define AR_FILT_OFDM 0x8124 180 #define AR_FILT_CCK 0x8128 181 #define AR_PHY_ERR_1 0x812c 182 #define AR_PHY_ERR_MASK_1 0x8130 183 #define AR_PHY_ERR_2 0x8134 184 #define AR_PHY_ERR_MASK_2 0x8138 185 #define AR_TSFOOR_THRESHOLD 0x813c 186 #define AR_PHY_ERR_EIFS_MASK 0x8144 187 #define AR_PHY_ERR_3 0x8168 188 #define AR_PHY_ERR_MASK_3 0x816c 189 #define AR_BT_COEX_MODE 0x8170 190 #define AR_BT_COEX_WEIGHT 0x8174 191 #define AR_BT_COEX_MODE2 0x817c 192 #define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4) 193 #define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4) 194 #define AR_NDP2_TIMER_MODE 0x81c0 195 #define AR_TXSIFS 0x81d0 196 #define AR_TXOP_X 0x81ec 197 #define AR_TXOP_0_3 0x81f0 198 #define AR_TXOP_4_7 0x81f4 199 #define AR_TXOP_8_11 0x81f8 200 #define AR_TXOP_12_15 0x81fc 201 #define AR_GEN_TIMER(i) (0x8200 + (i) * 4) 202 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMER(0) 203 #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMER(1) 204 #define AR_NEXT_CFP AR_GEN_TIMER(2) 205 #define AR_NEXT_HCF AR_GEN_TIMER(3) 206 #define AR_NEXT_TIM AR_GEN_TIMER(4) 207 #define AR_NEXT_DTIM AR_GEN_TIMER(5) 208 #define AR_NEXT_QUIET_TIMER AR_GEN_TIMER(6) 209 #define AR_NEXT_NDP_TIMER AR_GEN_TIMER(7) 210 #define AR_BEACON_PERIOD AR_GEN_TIMER(8) 211 #define AR_DMA_BEACON_PERIOD AR_GEN_TIMER(9) 212 #define AR_SWBA_PERIOD AR_GEN_TIMER(10) 213 #define AR_HCF_PERIOD AR_GEN_TIMER(11) 214 #define AR_TIM_PERIOD AR_GEN_TIMER(12) 215 #define AR_DTIM_PERIOD AR_GEN_TIMER(13) 216 #define AR_QUIET_PERIOD AR_GEN_TIMER(14) 217 #define AR_NDP_PERIOD AR_GEN_TIMER(15) 218 #define AR_TIMER_MODE 0x8240 219 #define AR_SLP32_MODE 0x8244 220 #define AR_SLP32_WAKE 0x8248 221 #define AR_SLP32_INC 0x824c 222 #define AR_SLP_CNT 0x8250 223 #define AR_SLP_CYCLE_CNT 0x8254 224 #define AR_SLP_MIB_CTRL 0x8258 225 #define AR_WOW_PATTERN_REG 0x825c 226 #define AR_WOW_COUNT_REG 0x8260 227 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 228 #define AR_WOW_BCN_EN_REG 0x8270 229 #define AR_WOW_BCN_TIMO_REG 0x8274 230 #define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278 231 #define AR_WOW_KEEP_ALIVE_REG 0x827c 232 #define AR_WOW_US_SCALAR_REG 0x8284 233 #define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288 234 #define AR_WOW_PATTERN_MATCH_REG 0x828c 235 #define AR_WOW_PATTERN_OFF1_REG 0x8290 236 #define AR_WOW_PATTERN_OFF2_REG 0x8294 237 #define AR_WOW_EXACT_REG 0x829c 238 #define AR_2040_MODE 0x8318 239 #define AR_EXTRCCNT 0x8328 240 #define AR_SELFGEN_MASK 0x832c 241 #define AR_PCU_TXBUF_CTRL 0x8340 242 #define AR_PCU_MISC_MODE2 0x8344 243 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 244 #define AR_WOW_LENGTH1_REG 0x8360 245 #define AR_WOW_LENGTH2_REG 0x8364 246 #define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 247 #define AR_RATE_DURATION(i) (0x8700 + (i) * 4) 248 #define AR_KEYTABLE(i) (0x8800 + (i) * 32) 249 #define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0) 250 #define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4) 251 #define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8) 252 #define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12) 253 #define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16) 254 #define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20) 255 #define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24) 256 #define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28) 257 258 259 /* Bits for AR_CR. */ 260 #define AR_CR_RXE 0x00000004 261 #define AR_CR_RXD 0x00000020 262 #define AR_CR_SWI 0x00000040 263 264 /* Bits for AR_CFG. */ 265 #define AR_CFG_SWTD 0x00000001 266 #define AR_CFG_SWTB 0x00000002 267 #define AR_CFG_SWRD 0x00000004 268 #define AR_CFG_SWRB 0x00000008 269 #define AR_CFG_SWRG 0x00000010 270 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 271 #define AR_CFG_PHOK 0x00000100 272 #define AR_CFG_EEBS 0x00000200 273 #define AR_CFG_CLK_GATE_DIS 0x00000400 274 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 275 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 276 277 /* Bits for AR_RXBP_THRESH. */ 278 #define AR_RXBP_THRESH_HP_M 0x0000000f 279 #define AR_RXBP_THRESH_HP_S 0 280 #define AR_RXBP_THRESH_LP_M 0x00003f00 281 #define AR_RXBP_THRESH_LP_S 8 282 283 /* Bits for AR_IER. */ 284 #define AR_IER_ENABLE 0x00000001 285 286 /* Bits for AR_TIMT. */ 287 #define AR_TIMT_LAST_M 0x0000ffff 288 #define AR_TIMT_LAST_S 0 289 #define AR_TIMT_FIRST_M 0xffff0000 290 #define AR_TIMT_FIRST_S 16 291 292 /* Bits for AR_RIMT. */ 293 #define AR_RIMT_LAST_M 0x0000ffff 294 #define AR_RIMT_LAST_S 0 295 #define AR_RIMT_FIRST_M 0xffff0000 296 #define AR_RIMT_FIRST_S 16 297 298 /* Bits for AR_[TR]XCFG_DMASZ fields. */ 299 #define AR_DMASZ_4B 0 300 #define AR_DMASZ_8B 1 301 #define AR_DMASZ_16B 2 302 #define AR_DMASZ_32B 3 303 #define AR_DMASZ_64B 4 304 #define AR_DMASZ_128B 5 305 #define AR_DMASZ_256B 6 306 #define AR_DMASZ_512B 7 307 308 /* Bits for AR_TXCFG. */ 309 #define AR_TXCFG_DMASZ_M 0x00000007 310 #define AR_TXCFG_DMASZ_S 0 311 #define AR_TXCFG_FTRIG_M 0x000003f0 312 #define AR_TXCFG_FTRIG_S 4 313 #define AR_TXCFG_FTRIG_IMMED ( 0 / 64) 314 #define AR_TXCFG_FTRIG_64B ( 64 / 64) 315 #define AR_TXCFG_FTRIG_128B (128 / 64) 316 #define AR_TXCFG_FTRIG_192B (192 / 64) 317 #define AR_TXCFG_FTRIG_256B (256 / 64) 318 #define AR_TXCFG_FTRIG_512B (512 / 64) 319 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 320 321 /* Bits for AR_RXCFG. */ 322 #define AR_RXCFG_DMASZ_M 0x00000007 323 #define AR_RXCFG_DMASZ_S 0 324 #define AR_RXCFG_CHIRP 0x00000008 325 #define AR_RXCFG_ZLFDMA 0x00000010 326 327 /* Bits for AR_MIBC. */ 328 #define AR_MIBC_COW 0x00000001 329 #define AR_MIBC_FMC 0x00000002 330 #define AR_MIBC_CMC 0x00000004 331 #define AR_MIBC_MCS 0x00000008 332 333 /* Bits for AR_TOPS. */ 334 #define AR_TOPS_MASK 0x0000ffff 335 336 /* Bits for AR_RXNPTO. */ 337 #define AR_RXNPTO_MASK 0x000003ff 338 339 /* Bits for AR_TXNPTO. */ 340 #define AR_TXNPTO_MASK 0x000003ff 341 #define AR_TXNPTO_QCU_MASK 0x000ffc00 342 343 /* Bits for AR_RPGTO. */ 344 #define AR_RPGTO_MASK 0x000003ff 345 346 /* Bits for AR_RPCNT. */ 347 #define AR_RPCNT_MASK 0x0000001f 348 349 /* Bits for AR_MACMISC. */ 350 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 351 #define AR_MACMISC_DMA_OBS_M 0x000001e0 352 #define AR_MACMISC_DMA_OBS_S 5 353 #define AR_MACMISC_MISC_OBS_M 0x00000e00 354 #define AR_MACMISC_MISC_OBS_S 9 355 #define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000 356 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 357 #define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000 358 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 359 360 /* Bits for AR_GTXTO. */ 361 #define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff 362 #define AR_GTXTO_TIMEOUT_COUNTER_S 0 363 #define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000 364 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 365 366 /* Bits for AR_GTTM. */ 367 #define AR_GTTM_USEC 0x00000001 368 #define AR_GTTM_IGNORE_IDLE 0x00000002 369 #define AR_GTTM_RESET_IDLE 0x00000004 370 #define AR_GTTM_CST_USEC 0x00000008 371 372 /* Bits for AR_CST. */ 373 #define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff 374 #define AR_CST_TIMEOUT_COUNTER_S 0 375 #define AR_CST_TIMEOUT_LIMIT_M 0xffff0000 376 #define AR_CST_TIMEOUT_LIMIT_S 16 377 378 /* Bits for AR_ISR. */ 379 #define AR_ISR_RXOK 0x00000001 380 #define AR_ISR_HP_RXOK 0x00000001 381 #define AR_ISR_RXDESC 0x00000002 382 #define AR_ISR_LP_RXOK 0x00000002 383 #define AR_ISR_RXERR 0x00000004 384 #define AR_ISR_RXNOPKT 0x00000008 385 #define AR_ISR_RXEOL 0x00000010 386 #define AR_ISR_RXORN 0x00000020 387 #define AR_ISR_TXOK 0x00000040 388 #define AR_ISR_TXDESC 0x00000080 389 #define AR_ISR_TXERR 0x00000100 390 #define AR_ISR_TXNOPKT 0x00000200 391 #define AR_ISR_TXEOL 0x00000400 392 #define AR_ISR_TXURN 0x00000800 393 #define AR_ISR_MIB 0x00001000 394 #define AR_ISR_SWI 0x00002000 395 #define AR_ISR_RXPHY 0x00004000 396 #define AR_ISR_RXKCM 0x00008000 397 #define AR_ISR_SWBA 0x00010000 398 #define AR_ISR_BRSSI 0x00020000 399 #define AR_ISR_BMISS 0x00040000 400 #define AR_ISR_TXMINTR 0x00080000 401 #define AR_ISR_BNR 0x00100000 402 #define AR_ISR_RXCHIRP 0x00200000 403 #define AR_ISR_BCNMISC 0x00800000 404 #define AR_ISR_TIM 0x00800000 405 #define AR_ISR_RXMINTR 0x01000000 406 #define AR_ISR_QCBROVF 0x02000000 407 #define AR_ISR_QCBRURN 0x04000000 408 #define AR_ISR_QTRIG 0x08000000 409 #define AR_ISR_GENTMR 0x10000000 410 #define AR_ISR_TXINTM 0x40000000 411 #define AR_ISR_RXINTM 0x80000000 412 413 /* Bits for AR_ISR_S0. */ 414 #define AR_ISR_S0_QCU_TXOK_M 0x000003ff 415 #define AR_ISR_S0_QCU_TXOK_S 0 416 #define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000 417 #define AR_ISR_S0_QCU_TXDESC_S 16 418 419 /* Bits for AR_ISR_S1. */ 420 #define AR_ISR_S1_QCU_TXERR_M 0x000003ff 421 #define AR_ISR_S1_QCU_TXERR_S 0 422 #define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000 423 #define AR_ISR_S1_QCU_TXEOL_S 16 424 425 /* Bits for AR_ISR_S2. */ 426 #define AR_ISR_S2_QCU_TXURN_M 0x000003ff 427 #define AR_ISR_S2_QCU_TXURN_S 0 428 #define AR_ISR_S2_BB_WATCHDOG 0x00010000 429 #define AR_ISR_S2_CST 0x00400000 430 #define AR_ISR_S2_GTT 0x00800000 431 #define AR_ISR_S2_TIM 0x01000000 432 #define AR_ISR_S2_CABEND 0x02000000 433 #define AR_ISR_S2_DTIMSYNC 0x04000000 434 #define AR_ISR_S2_BCNTO 0x08000000 435 #define AR_ISR_S2_CABTO 0x10000000 436 #define AR_ISR_S2_DTIM 0x20000000 437 #define AR_ISR_S2_TSFOOR 0x40000000 438 #define AR_ISR_S2_TBTT_TIME 0x80000000 439 440 /* Bits for AR_ISR_S3. */ 441 #define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff 442 #define AR_ISR_S3_QCU_QCBROVF_S 0 443 #define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000 444 #define AR_ISR_S3_QCU_QCBRURN_S 0 445 446 /* Bits for AR_ISR_S4. */ 447 #define AR_ISR_S4_QCU_QTRIG_M 0x000003ff 448 #define AR_ISR_S4_QCU_QTRIG_S 0 449 450 /* Bits for AR_ISR_S5. */ 451 #define AR_ISR_S5_TIMER_TRIG_M 0x000000ff 452 #define AR_ISR_S5_TIMER_TRIG_S 0 453 #define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00 454 #define AR_ISR_S5_TIMER_THRESH_S 9 455 #define AR_ISR_S5_TIM_TIMER 0x00000010 456 #define AR_ISR_S5_DTIM_TIMER 0x00000020 457 #define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80 458 #define AR_ISR_S5_GENTIMER_TRIG_S 0 459 #define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000 460 #define AR_ISR_S5_GENTIMER_THRESH_S 16 461 462 /* Bits for AR_IMR. */ 463 #define AR_IMR_RXOK 0x00000001 464 #define AR_IMR_HP_RXOK 0x00000001 465 #define AR_IMR_RXDESC 0x00000002 466 #define AR_IMR_LP_RXOK 0x00000002 467 #define AR_IMR_RXERR 0x00000004 468 #define AR_IMR_RXNOPKT 0x00000008 469 #define AR_IMR_RXEOL 0x00000010 470 #define AR_IMR_RXORN 0x00000020 471 #define AR_IMR_TXOK 0x00000040 472 #define AR_IMR_TXDESC 0x00000080 473 #define AR_IMR_TXERR 0x00000100 474 #define AR_IMR_TXNOPKT 0x00000200 475 #define AR_IMR_TXEOL 0x00000400 476 #define AR_IMR_TXURN 0x00000800 477 #define AR_IMR_MIB 0x00001000 478 #define AR_IMR_SWI 0x00002000 479 #define AR_IMR_RXPHY 0x00004000 480 #define AR_IMR_RXKCM 0x00008000 481 #define AR_IMR_SWBA 0x00010000 482 #define AR_IMR_BRSSI 0x00020000 483 #define AR_IMR_BMISS 0x00040000 484 #define AR_IMR_TXMINTR 0x00080000 485 #define AR_IMR_BNR 0x00100000 486 #define AR_IMR_RXCHIRP 0x00200000 487 #define AR_IMR_BCNMISC 0x00800000 488 #define AR_IMR_TIM 0x00800000 489 #define AR_IMR_RXMINTR 0x01000000 490 #define AR_IMR_QCBROVF 0x02000000 491 #define AR_IMR_QCBRURN 0x04000000 492 #define AR_IMR_QTRIG 0x08000000 493 #define AR_IMR_GENTMR 0x10000000 494 #define AR_IMR_TXINTM 0x40000000 495 #define AR_IMR_RXINTM 0x80000000 496 497 #define AR_IMR_DEFAULT \ 498 (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \ 499 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \ 500 AR_IMR_RXMINTR | AR_IMR_TXOK) 501 #define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB) 502 503 /* Bits for AR_IMR_S0. */ 504 #define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid)) 505 #define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid))) 506 507 /* Bits for AR_IMR_S1. */ 508 #define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid)) 509 #define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid))) 510 511 /* Bits for AR_IMR_S2. */ 512 #define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid)) 513 #define AR_IMR_S2_CST 0x00400000 514 #define AR_IMR_S2_GTT 0x00800000 515 #define AR_IMR_S2_TIM 0x01000000 516 #define AR_IMR_S2_CABEND 0x02000000 517 #define AR_IMR_S2_DTIMSYNC 0x04000000 518 #define AR_IMR_S2_BCNTO 0x08000000 519 #define AR_IMR_S2_CABTO 0x10000000 520 #define AR_IMR_S2_DTIM 0x20000000 521 #define AR_IMR_S2_TSFOOR 0x40000000 522 523 /* Bits for AR_IMR_S3. */ 524 #define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid)) 525 #define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid))) 526 527 /* Bits for AR_IMR_S4. */ 528 #define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid)) 529 530 /* Bits for AR_IMR_S5. */ 531 #define AR_IMR_S5_TIM_TIMER 0x00000010 532 #define AR_IMR_S5_DTIM_TIMER 0x00000020 533 #define AR_IMR_S5_TIMER_TRIG_M 0x000000ff 534 #define AR_IMR_S5_TIMER_TRIG_S 0 535 #define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00 536 #define AR_IMR_S5_TIMER_THRESH_S 0 537 538 #define AR_NUM_QCU 10 539 #define AR_QCU(x) (1 << (x)) 540 541 /* Bits for AR_Q_TXE. */ 542 #define AR_Q_TXE_M 0x000003ff 543 #define AR_Q_TXE_S 0 544 545 /* Bits for AR_Q_TXD. */ 546 #define AR_Q_TXD_M 0x000003ff 547 #define AR_Q_TXD_S 0 548 549 /* Bits for AR_QCBRCFG_*. */ 550 #define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff 551 #define AR_Q_CBRCFG_INTERVAL_S 0 552 #define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000 553 #define AR_Q_CBRCFG_OVF_THRESH_S 24 554 555 /* Bits for AR_QRDYTIMECFG_*. */ 556 #define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff 557 #define AR_Q_RDYTIMECFG_DURATION_S 0 558 #define AR_Q_RDYTIMECFG_EN 0x01000000 559 560 /* Bits for AR_QMISC_*. */ 561 #define AR_Q_MISC_FSP_M 0x0000000f 562 #define AR_Q_MISC_FSP_S 0 563 #define AR_Q_MISC_FSP_ASAP 0 564 #define AR_Q_MISC_FSP_CBR 1 565 #define AR_Q_MISC_FSP_DBA_GATED 2 566 #define AR_Q_MISC_FSP_TIM_GATED 3 567 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 568 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 569 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 570 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 571 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 572 #define AR_Q_MISC_BEACON_USE 0x00000080 573 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 574 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 575 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 576 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 577 578 /* Bits for AR_QSTS_*. */ 579 #define AR_Q_STS_PEND_FR_CNT_M 0x00000003 580 #define AR_Q_STS_PEND_FR_CNT_S 0 581 #define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00 582 #define AR_Q_STS_CBR_EXP_CNT_S 8 583 584 /* Bits for AR_Q_DESC_CRCCHK. */ 585 #define AR_Q_DESC_CRCCHK_EN 0x00000001 586 587 #define AR_NUM_DCU 10 588 #define AR_DCU(x) (1 << (x)) 589 590 /* Bits for AR_D_QCUMASK_*. */ 591 #define AR_D_QCUMASK_M 0x000003ff 592 #define AR_D_QCUMASK_S 0 593 594 /* Bits for AR_D_GBL_IFS_SIFS. */ 595 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab 596 597 /* Bits for AR_D_TXBLK_CMD. */ 598 #define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff 599 #define AR_D_TXBLK_WRITE_BITMASK_S 0 600 #define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000 601 #define AR_D_TXBLK_WRITE_SLICE_S 16 602 #define AR_D_TXBLK_WRITE_DCU_M 0x00f00000 603 #define AR_D_TXBLK_WRITE_DCU_S 20 604 #define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000 605 #define AR_D_TXBLK_WRITE_COMMAND_S 24 606 607 /* Bits for AR_DLCL_IFS. */ 608 #define AR_D_LCL_IFS_CWMIN_M 0x000003ff 609 #define AR_D_LCL_IFS_CWMIN_S 0 610 #define AR_D_LCL_IFS_CWMAX_M 0x000ffc00 611 #define AR_D_LCL_IFS_CWMAX_S 10 612 #define AR_D_LCL_IFS_AIFS_M 0x0ff00000 613 #define AR_D_LCL_IFS_AIFS_S 20 614 615 /* Bits for AR_D_GBL_IFS_SLOT. */ 616 #define AR_D_GBL_IFS_SLOT_M 0x0000ffff 617 #define AR_D_GBL_IFS_SLOT_S 0 618 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 619 620 /* Bits for AR_DRETRY_LIMIT_*. */ 621 #define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f 622 #define AR_D_RETRY_LIMIT_FR_SH_S 0 623 #define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00 624 #define AR_D_RETRY_LIMIT_STA_SH_S 8 625 #define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000 626 #define AR_D_RETRY_LIMIT_STA_LG_S 14 627 628 /* Bits for AR_D_GBL_IFS_EIFS. */ 629 #define AR_D_GBL_IFS_EIFS_M 0x0000ffff 630 #define AR_D_GBL_IFS_EIFS_S 0 631 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb 632 633 /* Bits for AR_DCHNTIME_*. */ 634 #define AR_D_CHNTIME_DUR_M 0x000fffff 635 #define AR_D_CHNTIME_DUR_S 0 636 #define AR_D_CHNTIME_EN 0x00100000 637 638 /* Bits for AR_D_GBL_IFS_MISC. */ 639 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 640 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 641 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00 642 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 643 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 644 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 645 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 646 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 647 648 /* Bits for AR_DMISC_*. */ 649 #define AR_D_MISC_BKOFF_THRESH_M 0x0000003f 650 #define AR_D_MISC_BKOFF_THRESH_S 0 651 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 652 #define AR_D_MISC_CW_RESET_EN 0x00000080 653 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 654 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 655 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 656 #define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000 657 #define AR_D_MISC_VIR_COL_HANDLING_S 14 658 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 659 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 660 #define AR_D_MISC_BEACON_USE 0x00010000 661 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 662 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 663 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 664 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 665 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 666 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 667 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 668 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 669 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 670 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 671 672 /* Bits for AR_D_FPCTL. */ 673 #define AR_D_FPCTL_DCU_M 0x0000000f 674 #define AR_D_FPCTL_DCU_S 0 675 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 676 #define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0 677 #define AR_D_FPCTL_BURST_PREFETCH_S 5 678 679 /* Bits for AR_D_TXPSE. */ 680 #define AR_D_TXPSE_CTRL_M 0x000003ff 681 #define AR_D_TXPSE_CTRL_S 0 682 #define AR_D_TXPSE_STATUS 0x00010000 683 684 /* Bits for AR_D_TXSLOTMASK. */ 685 #define AR_D_TXSLOTMASK_NUM 0x0000000f 686 687 /* Bits for AR_MAC_SLEEP. */ 688 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 689 690 /* Bits for AR_CFG_LED. */ 691 #define AR_CFG_SCLK_RATE_IND_M 0x00000003 692 #define AR_CFG_SCLK_RATE_IND_S 0 693 #define AR_CFG_SCLK_32MHZ 0 694 #define AR_CFG_SCLK_4MHZ 1 695 #define AR_CFG_SCLK_1MHZ 2 696 #define AR_CFG_SCLK_32KHZ 3 697 #define AR_CFG_LED_BLINK_SLOW 0x00000008 698 #define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070 699 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 700 #define AR_CFG_LED_MODE_SEL_M 0x00000380 701 #define AR_CFG_LED_MODE_SEL_S 7 702 #define AR_CFG_LED_POWER_M 0x00000280 703 #define AR_CFG_LED_POWER_S 7 704 #define AR_CFG_LED_NETWORK_M 0x00000300 705 #define AR_CFG_LED_NETWORK_S 7 706 #define AR_CFG_LED_MODE_PROP 0 707 #define AR_CFG_LED_MODE_RPROP 1 708 #define AR_CFG_LED_MODE_SPLIT 2 709 #define AR_CFG_LED_MODE_RAND 3 710 #define AR_CFG_LED_MODE_POWER_OFF 4 711 #define AR_CFG_LED_MODE_POWER_ON 5 712 #define AR_CFG_LED_MODE_NETWORK_OFF 4 713 #define AR_CFG_LED_MODE_NETWORK_ON 6 714 #define AR_CFG_LED_ASSOC_CTL_M 0x00000c00 715 #define AR_CFG_LED_ASSOC_CTL_S 10 716 #define AR_CFG_LED_ASSOC_NONE 0 717 #define AR_CFG_LED_ASSOC_ACTIVE 1 718 #define AR_CFG_LED_ASSOC_PENDING 2 719 720 /* Bit for AR_RC. */ 721 #define AR_RC_AHB 0x00000001 722 #define AR_RC_APB 0x00000002 723 #define AR_RC_HOSTIF 0x00000100 724 725 /* Bits for AR_WA. */ 726 #define AR5416_WA_DEFAULT 0x0000073f 727 #define AR9280_WA_DEFAULT 0x0040073b 728 #define AR9285_WA_DEFAULT 0x004a050b 729 #define AR_WA_UNTIE_RESET_EN 0x00008000 730 #define AR_WA_RESET_EN 0x00040000 731 #define AR_WA_ANALOG_SHIFT 0x00100000 732 #define AR_WA_POR_SHORT 0x00200000 733 734 /* Bits for AR_PM_STATE. */ 735 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 736 737 /* Bits for AR_PCIE_PM_CTRL. */ 738 #define AR_PCIE_PM_CTRL_ENA 0x00080000 739 740 /* Bits for AR_HOST_TIMEOUT. */ 741 #define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff 742 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 743 #define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000 744 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 745 746 /* Bits for AR_EEPROM. */ 747 #define AR_EEPROM_ABSENT 0x00000100 748 #define AR_EEPROM_CORRUPT 0x00000200 749 #define AR_EEPROM_PROT_MASK_M 0x03fffc00 750 #define AR_EEPROM_PROT_MASK_S 10 751 752 /* Bits for AR_SREV. */ 753 #define AR_SREV_ID_M 0x000000ff 754 #define AR_SREV_ID_S 0 755 #define AR_SREV_REVISION_M 0x00000007 756 #define AR_SREV_REVISION_S 0 757 #define AR_SREV_VERSION_M 0x000000f0 758 #define AR_SREV_VERSION_S 4 759 #define AR_SREV_VERSION2_M 0xfffc0000 760 #define AR_SREV_VERSION2_S 12 /* XXX Hack. */ 761 #define AR_SREV_TYPE2_M 0x0003f000 762 #define AR_SREV_TYPE2_S 12 763 #define AR_SREV_TYPE2_CHAIN 0x00001000 764 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 765 #define AR_SREV_REVISION2_M 0x00000f00 766 #define AR_SREV_REVISION2_S 8 767 #define AR_SREV_VERSION_5416_PCI 0x00d 768 #define AR_SREV_VERSION_5416_PCIE 0x00c 769 #define AR_SREV_REVISION_5416_10 0 770 #define AR_SREV_REVISION_5416_20 1 771 #define AR_SREV_REVISION_5416_22 2 772 #define AR_SREV_VERSION_9100 0x014 773 #define AR_SREV_VERSION_9160 0x040 774 #define AR_SREV_REVISION_9160_10 0 775 #define AR_SREV_REVISION_9160_11 1 776 #define AR_SREV_VERSION_9280 0x080 777 #define AR_SREV_REVISION_9280_10 0 778 #define AR_SREV_REVISION_9280_20 1 779 #define AR_SREV_REVISION_9280_21 2 780 #define AR_SREV_VERSION_9285 0x0c0 781 #define AR_SREV_REVISION_9285_10 0 782 #define AR_SREV_REVISION_9285_11 1 783 #define AR_SREV_REVISION_9285_12 2 784 #define AR_SREV_VERSION_9271 0x140 785 #define AR_SREV_REVISION_9271_10 0 786 #define AR_SREV_REVISION_9271_11 1 787 #define AR_SREV_VERSION_9287 0x180 788 #define AR_SREV_REVISION_9287_10 0 789 #define AR_SREV_REVISION_9287_11 1 790 #define AR_SREV_REVISION_9287_12 2 791 #define AR_SREV_REVISION_9287_13 3 792 #define AR_SREV_VERSION_9380 0x1c0 793 #define AR_SREV_REVISION_9380_10 0 794 #define AR_SREV_REVISION_9380_20 2 795 #define AR_SREV_VERSION_9485 0x240 796 #define AR_SREV_REVISION_9485_10 0 797 798 /* Bits for AR_AHB_MODE. */ 799 #define AR_AHB_EXACT_WR_EN 0x00000000 800 #define AR_AHB_BUF_WR_EN 0x00000001 801 #define AR_AHB_EXACT_RD_EN 0x00000000 802 #define AR_AHB_CACHELINE_RD_EN 0x00000002 803 #define AR_AHB_PREFETCH_RD_EN 0x00000004 804 #define AR_AHB_PAGE_SIZE_1K 0x00000000 805 #define AR_AHB_PAGE_SIZE_2K 0x00000008 806 #define AR_AHB_PAGE_SIZE_4K 0x00000010 807 #define AR_AHB_CUSTOM_BURST_M 0x000000c0 808 #define AR_AHB_CUSTOM_BURST_S 6 809 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 810 811 /* Bits for AR_INTR_SYNC_CAUSE. */ 812 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 813 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 814 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 815 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 816 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 817 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 818 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 819 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 820 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 821 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 822 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 823 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 824 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 825 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 826 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 827 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 828 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 829 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 830 #define AR_INTR_SYNC_ALL 0x0003ffff 831 #define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i))) 832 833 #define AR_INTR_SYNC_DEFAULT \ 834 (AR_INTR_SYNC_HOST1_FATAL | \ 835 AR_INTR_SYNC_HOST1_PERR | \ 836 AR_INTR_SYNC_RADM_CPL_EP | \ 837 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 838 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \ 839 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 840 AR_INTR_SYNC_RADM_CPL_TIMEOUT | \ 841 AR_INTR_SYNC_LOCAL_TIMEOUT | \ 842 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 843 844 /* Bits for AR_INTR_ASYNC_CAUSE. */ 845 #define AR_INTR_RTC_IRQ 0x00000001 846 #define AR_INTR_MAC_IRQ 0x00000002 847 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 848 #define AR_INTR_MAC_AWAKE 0x00020000 849 #define AR_INTR_MAC_ASLEEP 0x00040000 850 #define AR_INTR_GPIO_PIN(i) (1 << (18 + (i))) 851 #define AR_INTR_SPURIOUS 0xffffffff 852 853 /* Bits for AR_GPIO_OE_OUT. */ 854 #define AR_GPIO_OE_OUT_DRV_M 0x00000003 855 #define AR_GPIO_OE_OUT_DRV_S 0 856 #define AR_GPIO_OE_OUT_DRV_NO 0 857 #define AR_GPIO_OE_OUT_DRV_LOW 1 858 #define AR_GPIO_OE_OUT_DRV_HI 2 859 #define AR_GPIO_OE_OUT_DRV_ALL 3 860 861 /* Bits for AR_GPIO_INTR_POL. */ 862 #define AR_GPIO_INTR_POL_PIN(i) (1 << (i)) 863 864 /* Bits for AR_GPIO_INPUT_EN_VAL. */ 865 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 866 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 867 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 868 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 869 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 870 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 871 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 872 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 873 #define AR_GPIO_JTAG_DISABLE 0x00020000 874 875 /* Bits for AR_GPIO_INPUT_MUX1. */ 876 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00 877 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 878 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000 879 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 880 881 /* Bits for AR_GPIO_INPUT_MUX2. */ 882 #define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f 883 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 884 #define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0 885 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 886 #define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00 887 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 888 889 /* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */ 890 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 891 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 892 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 893 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 894 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 895 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 896 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 897 898 /* Bits for AR_EEPROM_STATUS_DATA. */ 899 #define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff 900 #define AR_EEPROM_STATUS_DATA_VAL_S 0 901 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 902 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 903 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 904 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 905 906 /* Bits for AR_PCIE_MSI. */ 907 #define AR_PCIE_MSI_ENABLE 0x00000001 908 909 /* Bits for AR_RTC_RC. */ 910 #define AR_RTC_RC_MAC_WARM 0x00000001 911 #define AR_RTC_RC_MAC_COLD 0x00000002 912 #define AR_RTC_RC_COLD_RESET 0x00000004 913 #define AR_RTC_RC_WARM_RESET 0x00000008 914 915 /* Bits for AR_RTC_REG_CONTROL1. */ 916 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 917 918 /* Bits for AR_RTC_PLL_CONTROL. */ 919 #define AR_RTC_PLL_DIV_M 0x0000001f 920 #define AR_RTC_PLL_DIV_S 0 921 #define AR_RTC_PLL_DIV2 0x00000020 922 #define AR_RTC_PLL_REFDIV_5 0x000000c0 923 #define AR_RTC_PLL_CLKSEL_M 0x00000300 924 #define AR_RTC_PLL_CLKSEL_S 8 925 #define AR_RTC_9160_PLL_DIV_M 0x000003ff 926 #define AR_RTC_9160_PLL_DIV_S 0 927 #define AR_RTC_9160_PLL_REFDIV_M 0x00003c00 928 #define AR_RTC_9160_PLL_REFDIV_S 10 929 #define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000 930 #define AR_RTC_9160_PLL_CLKSEL_S 14 931 932 /* Bits for AR_RTC_RESET. */ 933 #define AR_RTC_RESET_EN 0x00000001 934 935 /* Bits for AR_RTC_STATUS. */ 936 #define AR_RTC_STATUS_M 0x0000000f 937 #define AR_RTC_STATUS_S 0 938 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 939 #define AR_RTC_STATUS_ON 0x00000002 940 #define AR_RTC_STATUS_SLEEP 0x00000004 941 #define AR_RTC_STATUS_WAKEUP 0x00000008 942 943 /* Bits for AR_RTC_SLEEP_CLK. */ 944 #define AR_RTC_FORCE_DERIVED_CLK 0x00000002 945 #define AR_RTC_FORCE_SWREG_PRD 0x00000004 946 947 /* Bits for AR_RTC_FORCE_WAKE. */ 948 #define AR_RTC_FORCE_WAKE_EN 0x00000001 949 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 950 951 /* Bits for AR_STA_ID1. */ 952 #define AR_STA_ID1_SADH_M 0x0000ffff 953 #define AR_STA_ID1_SADH_S 0 954 #define AR_STA_ID1_STA_AP 0x00010000 955 #define AR_STA_ID1_ADHOC 0x00020000 956 #define AR_STA_ID1_PWR_SAV 0x00040000 957 #define AR_STA_ID1_KSRCHDIS 0x00080000 958 #define AR_STA_ID1_PCF 0x00100000 959 #define AR_STA_ID1_USE_DEFANT 0x00200000 960 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 961 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 962 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 963 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 964 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 965 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 966 #define AR_STA_ID1_KSRCH_MODE 0x10000000 967 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 968 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 969 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 970 971 /* Bits for AR_BSS_ID1. */ 972 #define AR_BSS_ID1_U16_M 0x0000ffff 973 #define AR_BSS_ID1_U16_S 0 974 #define AR_BSS_ID1_AID_M 0x07ff0000 975 #define AR_BSS_ID1_AID_S 16 976 977 /* Bits for AR_TIME_OUT. */ 978 #define AR_TIME_OUT_ACK_M 0x00003fff 979 #define AR_TIME_OUT_ACK_S 0 980 #define AR_TIME_OUT_CTS_M 0x3fff0000 981 #define AR_TIME_OUT_CTS_S 16 982 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56 983 984 /* Bits for AR_RSSI_THR. */ 985 #define AR_RSSI_THR_M 0x000000ff 986 #define AR_RSSI_THR_S 0 987 #define AR_RSSI_THR_BM_THR_M 0x0000ff00 988 #define AR_RSSI_THR_BM_THR_S 8 989 #define AR_RSSI_BCN_WEIGHT_M 0x1f000000 990 #define AR_RSSI_BCN_WEIGHT_S 24 991 #define AR_RSSI_BCN_RSSI_RST 0x20000000 992 993 /* Bits for AR_USEC. */ 994 #define AR_USEC_USEC_M 0x0000007f 995 #define AR_USEC_USEC_S 0 996 #define AR_USEC_TX_LAT_M 0x007fc000 997 #define AR_USEC_TX_LAT_S 14 998 #define AR_USEC_RX_LAT_M 0x1f800000 999 #define AR_USEC_RX_LAT_S 23 1000 #define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1001 1002 /* Bits for AR_RESET_TSF. */ 1003 #define AR_RESET_TSF_ONCE 0x01000000 1004 1005 /* Bits for AR_RX_FILTER. */ 1006 #define AR_RX_FILTER_UCAST 0x00000001 1007 #define AR_RX_FILTER_MCAST 0x00000002 1008 #define AR_RX_FILTER_BCAST 0x00000004 1009 #define AR_RX_FILTER_CONTROL 0x00000008 1010 #define AR_RX_FILTER_BEACON 0x00000010 1011 #define AR_RX_FILTER_PROM 0x00000020 1012 #define AR_RX_FILTER_PROBEREQ 0x00000080 1013 #define AR_RX_FILTER_MYBEACON 0x00000200 1014 #define AR_RX_FILTER_COMPR_BAR 0x00000400 1015 #define AR_RX_FILTER_PSPOLL 0x00004000 1016 1017 /* Bits for AR_DIAG_SW. */ 1018 #define AR_DIAG_CACHE_ACK 0x00000001 1019 #define AR_DIAG_ACK_DIS 0x00000002 1020 #define AR_DIAG_CTS_DIS 0x00000004 1021 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1022 #define AR_DIAG_DECRYPT_DIS 0x00000010 1023 #define AR_DIAG_RX_DIS 0x00000020 1024 #define AR_DIAG_LOOP_BACK 0x00000040 1025 #define AR_DIAG_CORR_FCS 0x00000080 1026 #define AR_DIAG_CHAN_INFO 0x00000100 1027 #define AR_DIAG_SCRAM_SEED_M 0x0001fe00 1028 #define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */ 1029 #define AR_DIAG_FRAME_NV0 0x00020000 1030 #define AR_DIAG_OBS_PT_SEL1_M 0x000c0000 1031 #define AR_DIAG_OBS_PT_SEL1_S 18 1032 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1033 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1034 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1035 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1036 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1037 #define AR_DIAG_RX_ABORT 0x02000000 1038 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1039 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1040 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1041 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1042 1043 /* Bits for AR_AES_MUTE_MASK0. */ 1044 #define AR_AES_MUTE_MASK0_FC_M 0x0000ffff 1045 #define AR_AES_MUTE_MASK0_FC_S 0 1046 #define AR_AES_MUTE_MASK0_QOS_M 0xffff0000 1047 #define AR_AES_MUTE_MASK0_QOS_S 16 1048 1049 /* Bits for AR_AES_MUTE_MASK1. */ 1050 #define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff 1051 #define AR_AES_MUTE_MASK1_SEQ_S 0 1052 #define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000 1053 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1054 #define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000 1055 #define AR_AES_MUTE_MASK1_FC0_MGMT_S 16 1056 #define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000 1057 #define AR_AES_MUTE_MASK1_FC1_MGMT_S 24 1058 1059 /* Bits for AR_GATED_CLKS. */ 1060 #define AR_GATED_CLKS_TX 0x00000002 1061 #define AR_GATED_CLKS_RX 0x00000004 1062 #define AR_GATED_CLKS_REG 0x00000008 1063 1064 /* Bits for AR_OBS_BUS_CTRL. */ 1065 #define AR_OBS_BUS_SEL_1 0x00040000 1066 #define AR_OBS_BUS_SEL_2 0x00080000 1067 #define AR_OBS_BUS_SEL_3 0x000c0000 1068 #define AR_OBS_BUS_SEL_4 0x08040000 1069 #define AR_OBS_BUS_SEL_5 0x08080000 1070 1071 /* Bits for AR_OBS_BUS_1. */ 1072 #define AR_OBS_BUS_1_PCU 0x00000001 1073 #define AR_OBS_BUS_1_RX_END 0x00000002 1074 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1075 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1076 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1077 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1078 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1079 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1080 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1081 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1082 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1083 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1084 #define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000 1085 #define AR_OBS_BUS_1_WEP_STATE_S 12 1086 #define AR_OBS_BUS_1_RX_STATE_M 0x01f00000 1087 #define AR_OBS_BUS_1_RX_STATE_S 20 1088 #define AR_OBS_BUS_1_TX_STATE_M 0x7e000000 1089 #define AR_OBS_BUS_1_TX_STATE_S 25 1090 1091 /* Bits for AR_SLEEP1. */ 1092 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1093 #define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000 1094 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1095 /* Default value. */ 1096 #define AR_CAB_TIMEOUT_VAL 10 1097 1098 /* Bits for AR_SLEEP2. */ 1099 #define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000 1100 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1101 1102 /* Bits for AR_TPC. */ 1103 #define AR_TPC_ACK_M 0x0000003f 1104 #define AR_TPC_ACK_S 0 1105 #define AR_TPC_CTS_M 0x00003f00 1106 #define AR_TPC_CTS_S 8 1107 #define AR_TPC_CHIRP_M 0x003f0000 1108 #define AR_TPC_CHIRP_S 16 1109 1110 /* Bits for AR_QUIET1. */ 1111 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1112 #define AR_QUIET1_NEXT_QUIET_S 0 1113 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1114 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1115 1116 /* Bits for AR_QUIET2. */ 1117 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1118 #define AR_QUIET2_QUIET_PERIOD_S 0 1119 #define AR_QUIET2_QUIET_DUR_M 0xffff0000 1120 #define AR_QUIET2_QUIET_DUR_S 16 1121 1122 /* Bits for AR_TSF_PARM. */ 1123 #define AR_TSF_INCREMENT_M 0x000000ff 1124 #define AR_TSF_INCREMENT_S 0 1125 1126 /* Bits for AR_QOS_NO_ACK. */ 1127 #define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f 1128 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1129 #define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f 1130 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1131 #define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180 1132 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1133 1134 /* Bits for AR_PHY_ERR. */ 1135 #define AR_PHY_ERR_DCHIRP 0x00000008 1136 #define AR_PHY_ERR_RADAR 0x00000020 1137 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1138 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1139 1140 /* Bits for AR_PCU_MISC. */ 1141 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1142 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1143 #define AR_PCU_TX_ADD_TSF 0x00000008 1144 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1145 #define AR_PCU_RX_ANT_UPDT 0x00000800 1146 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1147 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1148 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1149 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1150 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1151 #define AR_PCU_TBTT_PROTECT 0x00200000 1152 #define AR_PCU_CLEAR_VMF 0x01000000 1153 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1154 1155 /* Bits for AR_BT_COEX_MODE. */ 1156 #define AR_BT_TIME_EXTEND_M 0x000000ff 1157 #define AR_BT_TIME_EXTEND_S 0 1158 #define AR_BT_TXSTATE_EXTEND 0x00000100 1159 #define AR_BT_TX_FRAME_EXTEND 0x00000200 1160 #define AR_BT_MODE_M 0x00000c00 1161 #define AR_BT_MODE_S 10 1162 #define AR_BT_MODE_LEGACY 0 1163 #define AR_BT_MODE_UNSLOTTED 1 1164 #define AR_BT_MODE_SLOTTED 2 1165 #define AR_BT_MODE_DISABLED 3 1166 #define AR_BT_QUIET 0x00001000 1167 #define AR_BT_QCU_THRESH_M 0x0001e000 1168 #define AR_BT_QCU_THRESH_S 13 1169 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1170 #define AR_BT_PRIORITY_TIME_M 0x00fc0000 1171 #define AR_BT_PRIORITY_TIME_S 18 1172 #define AR_BT_FIRST_SLOT_TIME_M 0xff000000 1173 #define AR_BT_FIRST_SLOT_TIME_S 24 1174 1175 /* Bits for AR_BT_COEX_WEIGHT. */ 1176 #define AR_BTCOEX_BT_WGHT_M 0x0000ffff 1177 #define AR_BTCOEX_BT_WGHT_S 0 1178 #define AR_STOMP_LOW_BT_WGHT 0xff55 1179 #define AR_BTCOEX_WL_WGHT_M 0xffff0000 1180 #define AR_BTCOEX_WL_WGHT_S 16 1181 #define AR_STOMP_LOW_WL_WGHT 0xaaa8 1182 1183 /* Bits for AR_BT_COEX_MODE2. */ 1184 #define AR_BT_BCN_MISS_THRESH_M 0x000000ff 1185 #define AR_BT_BCN_MISS_THRESH_S 0 1186 #define AR_BT_BCN_MISS_CNT_M 0x0000ff00 1187 #define AR_BT_BCN_MISS_CNT_S 8 1188 #define AR_BT_HOLD_RX_CLEAR 0x00010000 1189 #define AR_BT_DISABLE_BT_ANT 0x00100000 1190 1191 /* Bits for AR_PCU_TXBUF_CTRL. */ 1192 #define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff 1193 #define AR_PCU_TXBUF_CTRL_SIZE_S 0 1194 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792 1195 #define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2) 1196 1197 /* Bits for AR_PCU_MISC_MODE2. */ 1198 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1199 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1200 #define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX 0x00000008 1201 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1202 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1203 #define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00 1204 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1205 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000 1206 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1207 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1208 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1209 1210 /* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */ 1211 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1212 1213 /* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */ 1214 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1215 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1216 1217 /* Bits for AR_PHY_ERR_[123]. */ 1218 #define AR_PHY_ERR_COUNT_M 0x00ffffff 1219 #define AR_PHY_ERR_COUNT_S 0 1220 1221 /* Bits for AR_TSFOOR_THRESHOLD. */ 1222 #define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff 1223 #define AR_TSFOOR_THRESHOLD_VAL_S 0 1224 1225 /* Bit for AR_TXSIFS. */ 1226 #define AR_TXSIFS_TIME_M 0x000000ff 1227 #define AR_TXSIFS_TIME_S 0 1228 #define AR_TXSIFS_TX_LATENCY_M 0x00000f00 1229 #define AR_TXSIFS_TX_LATENCY_S 8 1230 #define AR_TXSIFS_ACK_SHIFT_M 0x00007000 1231 #define AR_TXSIFS_ACK_SHIFT_S 12 1232 1233 /* Bits for AR_TXOP_X. */ 1234 #define AR_TXOP_X_VAL 0x000000ff 1235 1236 /* Bits for AR_TIMER_MODE. */ 1237 #define AR_TBTT_TIMER_EN 0x00000001 1238 #define AR_DBA_TIMER_EN 0x00000002 1239 #define AR_SWBA_TIMER_EN 0x00000004 1240 #define AR_HCF_TIMER_EN 0x00000008 1241 #define AR_TIM_TIMER_EN 0x00000010 1242 #define AR_DTIM_TIMER_EN 0x00000020 1243 #define AR_QUIET_TIMER_EN 0x00000040 1244 #define AR_NDP_TIMER_EN 0x00000080 1245 #define AR_TIMER_OVERFLOW_INDEX_M 0x00000700 1246 #define AR_TIMER_OVERFLOW_INDEX_S 8 1247 #define AR_TIMER_THRESH_M 0xfffff000 1248 #define AR_TIMER_THRESH_S 12 1249 1250 /* Bits for AR_SLP32_MODE. */ 1251 #define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff 1252 #define AR_SLP32_HALF_CLK_LATENCY_S 0 1253 #define AR_SLP32_ENA 0x00100000 1254 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1255 1256 /* Bits for AR_SLP32_WAKE. */ 1257 #define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff 1258 #define AR_SLP32_WAKE_XTL_TIME_S 0 1259 1260 /* Bits for AR_SLP_MIB_CTRL. */ 1261 #define AR_SLP_MIB_CLEAR 0x00000001 1262 #define AR_SLP_MIB_PENDING 0x00000002 1263 1264 /* Bits for AR_2040_MODE. */ 1265 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1266 1267 /* Bits for AR_KEYTABLE_TYPE. */ 1268 #define AR_KEYTABLE_TYPE_M 0x00000007 1269 #define AR_KEYTABLE_TYPE_S 0 1270 #define AR_KEYTABLE_TYPE_40 0 1271 #define AR_KEYTABLE_TYPE_104 1 1272 #define AR_KEYTABLE_TYPE_128 3 1273 #define AR_KEYTABLE_TYPE_TKIP 4 1274 #define AR_KEYTABLE_TYPE_AES 5 1275 #define AR_KEYTABLE_TYPE_CCM 6 1276 #define AR_KEYTABLE_TYPE_CLR 7 1277 #define AR_KEYTABLE_ANT 0x00000008 1278 #define AR_KEYTABLE_VALID 0x00008000 1279 1280 /* 1281 * AR9271 specific registers. 1282 */ 1283 #define AR9271_RESET_POWER_DOWN_CONTROL 0x050044 1284 #define AR9271_FIRMWARE 0x501000 1285 #define AR9271_FIRMWARE_TEXT 0x903000 1286 #define AR7010_FIRMWARE_TEXT 0x906000 1287 1288 /* Bits for AR9271_RESET_POWER_DOWN_CONTROL. */ 1289 #define AR9271_RADIO_RF_RST 0x00000020 1290 #define AR9271_GATE_MAC_CTL 0x00004000 1291 1292 1293 #define AR_BASE_PHY_ACTIVE_DELAY 100 1294 1295 #define AR_CLOCK_RATE_CCK 22 1296 #define AR_CLOCK_RATE_5GHZ_OFDM 40 1297 #define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44 1298 #define AR_CLOCK_RATE_2GHZ_OFDM 44 1299 1300 #define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ 1301 #define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ 1302 1303 #define AR_SLEEP_SLOP 3 /* TUs */ 1304 1305 #define AR_MIN_BEACON_TIMEOUT_VAL 1 1306 #define AR_FUDGE 2 1307 #define AR_BEACON_DMA_DELAY 2 1308 #define AR_SWBA_DELAY 10 1309 /* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */ 1310 #define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10) 1311 1312 #define AR_KEY_CACHE_SIZE 128 1313 #define AR_RSVD_KEYTABLE_ENTRIES 4 1314 1315 #define AR_CAL_SAMPLES 64 /* XXX AR9280? */ 1316 #define AR_MAX_LOG_CAL 2 /* XXX AR9280? */ 1317 1318 /* Maximum number of chains supported by any chipset. */ 1319 #define AR_MAX_CHAINS 3 1320 1321 /* Default number of key cache entries. */ 1322 #define AR_KEYTABLE_SIZE 128 1323 1324 /* GPIO pins. */ 1325 #define AR_GPIO_WLANACTIVE_PIN 5 1326 #define AR_GPIO_BTACTIVE_PIN 6 1327 #define AR_GPIO_BTPRIORITY_PIN 7 1328 1329 #define AR_SREV_5416(sc) \ 1330 ((sc)->sc_mac_ver == AR_SREV_VERSION_5416_PCI || \ 1331 (sc)->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 1332 #define AR_SREV_5416_20_OR_LATER(sc) \ 1333 ((AR_SREV_5416(sc) && \ 1334 (sc)->sc_mac_rev >= AR_SREV_REVISION_5416_20) || \ 1335 (sc)->sc_mac_ver >= AR_SREV_VERSION_9100) 1336 #define AR_SREV_5416_22_OR_LATER(sc) \ 1337 ((AR_SREV_5416(sc) && \ 1338 (sc)->sc_mac_rev >= AR_SREV_REVISION_5416_22) || \ 1339 (sc)->sc_mac_ver >= AR_SREV_VERSION_9100) 1340 1341 #define AR_SREV_9160(sc) \ 1342 ((sc)->sc_mac_ver == AR_SREV_VERSION_9160) 1343 #define AR_SREV_9160_10_OR_LATER(sc) \ 1344 ((sc)->sc_mac_ver >= AR_SREV_VERSION_9160) 1345 #define AR_SREV_9160_11(sc) \ 1346 (AR_SREV_9160(sc) && \ 1347 (sc)->sc_mac_rev == AR_SREV_REVISION_9160_11) 1348 1349 #define AR_SREV_9280(sc) \ 1350 ((sc)->sc_mac_ver == AR_SREV_VERSION_9280) 1351 #define AR_SREV_9280_10_OR_LATER(sc) \ 1352 ((sc)->sc_mac_ver >= AR_SREV_VERSION_9280) 1353 #define AR_SREV_9280_10(sc) \ 1354 (AR_SREV_9280(sc) && \ 1355 (sc)->sc_mac_rev == AR_SREV_REVISION_9280_10) 1356 #define AR_SREV_9280_20(sc) \ 1357 (AR_SREV_9280(sc) && \ 1358 (sc)->sc_mac_rev >= AR_SREV_REVISION_9280_20) 1359 #define AR_SREV_9280_20_OR_LATER(sc) \ 1360 ((sc)->sc_mac_ver > AR_SREV_VERSION_9280 || \ 1361 (AR_SREV_9280(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9280_20)) 1362 1363 #define AR_SREV_9285(sc) \ 1364 ((sc)->sc_mac_ver == AR_SREV_VERSION_9285) 1365 #define AR_SREV_9285_10_OR_LATER(sc) \ 1366 ((sc)->sc_mac_ver >= AR_SREV_VERSION_9285) 1367 #define AR_SREV_9285_11(sc) \ 1368 (AR_SREV_9285(sc) && \ 1369 (sc)->sc_mac_rev == AR_SREV_REVISION_9285_11) 1370 #define AR_SREV_9285_11_OR_LATER(sc) \ 1371 ((sc)->sc_mac_ver > AR_SREV_VERSION_9285 || \ 1372 (AR_SREV_9285(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9285_11)) 1373 #define AR_SREV_9285_12(sc) \ 1374 (AR_SREV_9285(sc) && \ 1375 ((sc)->sc_mac_rev == AR_SREV_REVISION_9285_12)) 1376 #define AR_SREV_9285_12_OR_LATER(sc) \ 1377 ((sc)->sc_mac_ver > AR_SREV_VERSION_9285 || \ 1378 (AR_SREV_9285(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9285_12)) 1379 1380 #define AR_SREV_9271(sc) \ 1381 ((sc)->sc_mac_ver == AR_SREV_VERSION_9271) 1382 #define AR_SREV_9271_10(sc) \ 1383 (AR_SREV_9271(sc) && \ 1384 (sc)->sc_mac_rev == AR_SREV_REVISION_9271_10) 1385 1386 #define AR_SREV_9287(sc) \ 1387 ((sc)->sc_mac_ver == AR_SREV_VERSION_9287) 1388 #define AR_SREV_9287_10_OR_LATER(sc) \ 1389 ((sc)->sc_mac_ver >= AR_SREV_VERSION_9287) 1390 #define AR_SREV_9287_10(sc) \ 1391 ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \ 1392 (sc)->sc_mac_rev == AR_SREV_REVISION_9287_10) 1393 #define AR_SREV_9287_11(sc) \ 1394 ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \ 1395 (sc)->sc_mac_rev == AR_SREV_REVISION_9287_11) 1396 #define AR_SREV_9287_11_OR_LATER(sc) \ 1397 ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \ 1398 (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_11)) 1399 #define AR_SREV_9287_12(sc) \ 1400 ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \ 1401 (sc)->sc_mac_rev == AR_SREV_REVISION_9287_12) 1402 #define AR_SREV_9287_12_OR_LATER(sc) \ 1403 ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \ 1404 (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_12)) 1405 #define AR_SREV_9287_13_OR_LATER(sc) \ 1406 ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \ 1407 (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_13)) 1408 1409 #define AR_SREV_9380(sc) \ 1410 ((sc)->sc_mac_ver == AR_SREV_VERSION_9380) 1411 #define AR_SREV_9380_10_OR_LATER(sc) \ 1412 ((sc)->sc_mac_ver >= AR_SREV_VERSION_9380) 1413 #define AR_SREV_9380_20(sc) \ 1414 (AR_SREV_9380(sc) && \ 1415 (sc)->sc_mac_rev == AR_SREV_REVISION_9380_20) 1416 #define AR_SREV_9380_20_OR_LATER(sc) \ 1417 ((sc)->sc_mac_ver > AR_SREV_VERSION_9380 || \ 1418 (AR_SREV_9380(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9380_20)) 1419 1420 #define AR_SREV_9485(sc) \ 1421 ((sc)->sc_mac_ver == AR_SREV_VERSION_9485) 1422 1423 #define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc) 1424 1425 #define AR_RADIO_SREV_MAJOR 0xf0 1426 #define AR_RAD5133_SREV_MAJOR 0xc0 1427 #define AR_RAD2133_SREV_MAJOR 0xd0 1428 #define AR_RAD5122_SREV_MAJOR 0xe0 1429 #define AR_RAD2122_SREV_MAJOR 0xf0 1430 1431 #define AR_BCHAN_UNUSED 0xff 1432 #define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */ 1433 #define AR_MAX_RATE_POWER 63 1434 1435 #define AR_HT40_POWER_INC_FOR_PDADC 2 1436 #define AR_PWR_TABLE_OFFSET_DB (-5) 1437 #define AR9280_TX_GAIN_TABLE_SIZE 22 1438 #define AR9003_TX_GAIN_TABLE_SIZE 32 1439 #define AR9003_PAPRD_MEM_TAB_SIZE 24 1440 1441 #define AR_BASE_FREQ_2GHZ 2300 1442 #define AR_BASE_FREQ_5GHZ 4900 1443 1444 #define AR_SD_NO_CTL 0xe0 1445 #define AR_NO_CTL 0xff 1446 #define AR_CTL_MODE_M 0x07 1447 #define AR_CTL_MODE_S 0 1448 #define AR_CTL_11A 0 1449 #define AR_CTL_11B 1 1450 #define AR_CTL_11G 2 1451 #define AR_CTL_2GHT20 5 1452 #define AR_CTL_5GHT20 6 1453 #define AR_CTL_2GHT40 7 1454 #define AR_CTL_5GHT40 8 1455 1456 /* 1457 * Macros to access registers. 1458 */ 1459 #define AR_READ(sc, reg) \ 1460 (sc)->sc_ops.read((sc), (reg)) 1461 1462 #define AR_WRITE(sc, reg, val) \ 1463 (sc)->sc_ops.write((sc), (reg), (val)) 1464 1465 #define AR_WRITE_BARRIER(sc) \ 1466 (sc)->sc_ops.write_barrier((sc)) 1467 1468 #define AR_SETBITS(sc, reg, mask) \ 1469 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 1470 1471 #define AR_CLRBITS(sc, reg, mask) \ 1472 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask)) 1473 1474 /* 1475 * Macros to access subfields in registers. 1476 */ 1477 /* Mask and Shift (getter). */ 1478 #define MS(val, field) \ 1479 (((val) & field##_M) >> field##_S) 1480 1481 /* Shift and Mask (setter). */ 1482 #define SM(field, val) \ 1483 (((val) << field##_S) & field##_M) 1484 1485 /* Rewrite. */ 1486 #define RW(var, field, val) \ 1487 (((var) & ~field##_M) | SM(field, val)) 1488 1489 #endif /* _ATHNREG_H_ */ 1490
Indexes created Mon Sep 29 13:09:55 GMT 2025