athvar.h revision 1.9.2.7
1 1.9.2.7 christos /* $NetBSD: athvar.h,v 1.9.2.7 2005/12/11 10:28:50 christos Exp $ */ 2 1.9.2.2 skrll 3 1.9.2.2 skrll /*- 4 1.9.2.6 skrll * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 1.9.2.2 skrll * All rights reserved. 6 1.9.2.2 skrll * 7 1.9.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.9.2.2 skrll * modification, are permitted provided that the following conditions 9 1.9.2.2 skrll * are met: 10 1.9.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.9.2.2 skrll * notice, this list of conditions and the following disclaimer, 12 1.9.2.2 skrll * without modification. 13 1.9.2.2 skrll * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 1.9.2.2 skrll * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 1.9.2.2 skrll * redistribution must be conditioned upon including a substantially 16 1.9.2.2 skrll * similar Disclaimer requirement for further binary redistribution. 17 1.9.2.2 skrll * 3. Neither the names of the above-listed copyright holders nor the names 18 1.9.2.2 skrll * of any contributors may be used to endorse or promote products derived 19 1.9.2.2 skrll * from this software without specific prior written permission. 20 1.9.2.2 skrll * 21 1.9.2.2 skrll * Alternatively, this software may be distributed under the terms of the 22 1.9.2.2 skrll * GNU General Public License ("GPL") version 2 as published by the Free 23 1.9.2.2 skrll * Software Foundation. 24 1.9.2.2 skrll * 25 1.9.2.2 skrll * NO WARRANTY 26 1.9.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 1.9.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 1.9.2.2 skrll * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 1.9.2.2 skrll * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 1.9.2.2 skrll * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 1.9.2.2 skrll * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.9.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.9.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 1.9.2.2 skrll * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.9.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 1.9.2.2 skrll * THE POSSIBILITY OF SUCH DAMAGES. 37 1.9.2.2 skrll * 38 1.9.2.7 christos * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $ 39 1.9.2.2 skrll */ 40 1.9.2.2 skrll 41 1.9.2.2 skrll /* 42 1.9.2.2 skrll * Defintions for the Atheros Wireless LAN controller driver. 43 1.9.2.2 skrll */ 44 1.9.2.2 skrll #ifndef _DEV_ATH_ATHVAR_H 45 1.9.2.2 skrll #define _DEV_ATH_ATHVAR_H 46 1.9.2.2 skrll 47 1.9.2.6 skrll #include <dev/ic/ath_netbsd.h> 48 1.9.2.6 skrll #include <contrib/dev/ic/athhal.h> 49 1.9.2.2 skrll #include <net80211/ieee80211_radiotap.h> 50 1.9.2.2 skrll #include <dev/ic/athioctl.h> 51 1.9.2.6 skrll #include <dev/ic/athrate.h> 52 1.9.2.2 skrll 53 1.9.2.2 skrll #define ATH_TIMEOUT 1000 54 1.9.2.2 skrll 55 1.9.2.2 skrll #define ATH_RXBUF 40 /* number of RX buffers */ 56 1.9.2.6 skrll #define ATH_TXBUF 100 /* number of TX buffers */ 57 1.9.2.6 skrll #define ATH_TXDESC 10 /* number of descriptors per buffer */ 58 1.9.2.6 skrll #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 59 1.9.2.6 skrll #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 60 1.9.2.6 skrll 61 1.9.2.6 skrll #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 62 1.9.2.6 skrll #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 63 1.9.2.6 skrll #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 64 1.9.2.2 skrll 65 1.9.2.6 skrll /* 66 1.9.2.6 skrll * The key cache is used for h/w cipher state and also for 67 1.9.2.6 skrll * tracking station state such as the current tx antenna. 68 1.9.2.6 skrll * We also setup a mapping table between key cache slot indices 69 1.9.2.6 skrll * and station state to short-circuit node lookups on rx. 70 1.9.2.6 skrll * Different parts have different size key caches. We handle 71 1.9.2.6 skrll * up to ATH_KEYMAX entries (could dynamically allocate state). 72 1.9.2.6 skrll */ 73 1.9.2.6 skrll #define ATH_KEYMAX 128 /* max key cache size we handle */ 74 1.9.2.6 skrll #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 75 1.9.2.2 skrll 76 1.9.2.6 skrll /* driver-specific node state */ 77 1.9.2.2 skrll struct ath_node { 78 1.9.2.2 skrll struct ieee80211_node an_node; /* base class */ 79 1.9.2.6 skrll u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 80 1.9.2.6 skrll u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ 81 1.9.2.6 skrll u_int32_t an_avgrssi; /* average rssi over all rx frames */ 82 1.9.2.6 skrll HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ 83 1.9.2.6 skrll /* variable-length rate control state follows */ 84 1.9.2.2 skrll }; 85 1.9.2.6 skrll #define ATH_NODE(ni) ((struct ath_node *)(ni)) 86 1.9.2.6 skrll #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 87 1.9.2.6 skrll 88 1.9.2.6 skrll #define ATH_RSSI_LPF_LEN 10 89 1.9.2.6 skrll #define ATH_RSSI_DUMMY_MARKER 0x127 90 1.9.2.6 skrll #define ATH_EP_MUL(x, mul) ((x) * (mul)) 91 1.9.2.6 skrll #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 92 1.9.2.6 skrll #define ATH_LPF_RSSI(x, y, len) \ 93 1.9.2.6 skrll ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 94 1.9.2.6 skrll #define ATH_RSSI_LPF(x, y) do { \ 95 1.9.2.6 skrll if ((y) >= -20) \ 96 1.9.2.6 skrll x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 97 1.9.2.6 skrll } while (0) 98 1.9.2.2 skrll 99 1.9.2.2 skrll struct ath_buf { 100 1.9.2.6 skrll STAILQ_ENTRY(ath_buf) bf_list; 101 1.9.2.2 skrll #define bf_nseg bf_dmamap->dm_nsegs 102 1.9.2.6 skrll int bf_flags; /* tx descriptor flags */ 103 1.9.2.2 skrll struct ath_desc *bf_desc; /* virtual addr of desc */ 104 1.9.2.2 skrll bus_addr_t bf_daddr; /* physical addr of desc */ 105 1.9.2.6 skrll bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 106 1.9.2.2 skrll struct mbuf *bf_m; /* mbuf for buf */ 107 1.9.2.2 skrll struct ieee80211_node *bf_node; /* pointer to the node */ 108 1.9.2.6 skrll #define bf_mapsize bf_dmamap->dm_mapsize 109 1.9.2.6 skrll #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 110 1.9.2.6 skrll #define bf_segs bf_dmamap->dm_segs 111 1.9.2.6 skrll }; 112 1.9.2.6 skrll typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 113 1.9.2.6 skrll 114 1.9.2.6 skrll /* 115 1.9.2.6 skrll * DMA state for tx/rx descriptors. 116 1.9.2.6 skrll */ 117 1.9.2.6 skrll struct ath_descdma { 118 1.9.2.6 skrll const char* dd_name; 119 1.9.2.6 skrll struct ath_desc *dd_desc; /* descriptors */ 120 1.9.2.6 skrll bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 121 1.9.2.6 skrll bus_addr_t dd_desc_len; /* size of dd_desc */ 122 1.9.2.6 skrll bus_dma_segment_t dd_dseg; 123 1.9.2.6 skrll int dd_dnseg; /* number of segments */ 124 1.9.2.6 skrll bus_dma_tag_t dd_dmat; /* bus DMA tag */ 125 1.9.2.6 skrll bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 126 1.9.2.6 skrll struct ath_buf *dd_bufptr; /* associated buffers */ 127 1.9.2.6 skrll }; 128 1.9.2.6 skrll 129 1.9.2.6 skrll /* 130 1.9.2.6 skrll * Data transmit queue state. One of these exists for each 131 1.9.2.6 skrll * hardware transmit queue. Packets sent to us from above 132 1.9.2.6 skrll * are assigned to queues based on their priority. Not all 133 1.9.2.6 skrll * devices support a complete set of hardware transmit queues. 134 1.9.2.6 skrll * For those devices the array sc_ac2q will map multiple 135 1.9.2.6 skrll * priorities to fewer hardware queues (typically all to one 136 1.9.2.6 skrll * hardware queue). 137 1.9.2.6 skrll */ 138 1.9.2.6 skrll struct ath_txq { 139 1.9.2.6 skrll u_int axq_qnum; /* hardware q number */ 140 1.9.2.6 skrll u_int axq_depth; /* queue depth (stat only) */ 141 1.9.2.6 skrll u_int axq_intrcnt; /* interrupt count */ 142 1.9.2.6 skrll u_int32_t *axq_link; /* link ptr in last TX desc */ 143 1.9.2.6 skrll STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 144 1.9.2.6 skrll ath_txq_lock_t axq_lock; /* lock on q and link */ 145 1.9.2.6 skrll /* 146 1.9.2.6 skrll * State for patching up CTS when bursting. 147 1.9.2.6 skrll */ 148 1.9.2.6 skrll struct ath_buf *axq_linkbuf; /* va of last buffer */ 149 1.9.2.6 skrll struct ath_desc *axq_lastdsWithCTS; 150 1.9.2.6 skrll /* first desc of last descriptor 151 1.9.2.6 skrll * that contains CTS 152 1.9.2.6 skrll */ 153 1.9.2.6 skrll struct ath_desc *axq_gatingds; /* final desc of the gating desc 154 1.9.2.6 skrll * that determines whether 155 1.9.2.6 skrll * lastdsWithCTS has been DMA'ed 156 1.9.2.6 skrll * or not 157 1.9.2.6 skrll */ 158 1.9.2.2 skrll }; 159 1.9.2.2 skrll 160 1.9.2.6 skrll #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 161 1.9.2.6 skrll STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 162 1.9.2.6 skrll (_tq)->axq_depth++; \ 163 1.9.2.6 skrll } while (0) 164 1.9.2.6 skrll #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 165 1.9.2.6 skrll STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 166 1.9.2.6 skrll (_tq)->axq_depth--; \ 167 1.9.2.6 skrll } while (0) 168 1.9.2.6 skrll 169 1.9.2.2 skrll struct ath_softc { 170 1.9.2.2 skrll struct device sc_dev; 171 1.9.2.6 skrll struct ethercom sc_ec; /* interface common */ 172 1.9.2.6 skrll struct ath_stats sc_stats; /* interface statistics */ 173 1.9.2.2 skrll struct ieee80211com sc_ic; /* IEEE 802.11 common */ 174 1.9.2.2 skrll int (*sc_enable)(struct ath_softc *); 175 1.9.2.2 skrll void (*sc_disable)(struct ath_softc *); 176 1.9.2.2 skrll void (*sc_power)(struct ath_softc *, int); 177 1.9.2.6 skrll int sc_regdomain; 178 1.9.2.6 skrll int sc_countrycode; 179 1.9.2.6 skrll int sc_debug; 180 1.9.2.6 skrll struct sysctllog *sc_sysctllog; 181 1.9.2.6 skrll void (*sc_recv_mgmt)(struct ieee80211com *, 182 1.9.2.6 skrll struct mbuf *, 183 1.9.2.6 skrll struct ieee80211_node *, 184 1.9.2.6 skrll int, int, u_int32_t); 185 1.9.2.2 skrll int (*sc_newstate)(struct ieee80211com *, 186 1.9.2.2 skrll enum ieee80211_state, int); 187 1.9.2.6 skrll void (*sc_node_free)(struct ieee80211_node *); 188 1.9.2.2 skrll bus_space_tag_t sc_st; /* bus space tag */ 189 1.9.2.2 skrll bus_space_handle_t sc_sh; /* bus space handle */ 190 1.9.2.2 skrll bus_dma_tag_t sc_dmat; /* bus DMA tag */ 191 1.9.2.6 skrll ath_lock_t sc_mtx; /* master lock (recursive) */ 192 1.9.2.2 skrll struct ath_hal *sc_ah; /* Atheros HAL */ 193 1.9.2.6 skrll struct ath_ratectrl *sc_rc; /* tx rate control support */ 194 1.9.2.6 skrll void (*sc_setdefantenna)(struct ath_softc *, u_int); 195 1.9.2.6 skrll unsigned int sc_invalid : 1, /* disable hardware accesses */ 196 1.9.2.6 skrll sc_mrretry : 1, /* multi-rate retry support */ 197 1.9.2.6 skrll sc_softled : 1, /* enable LED gpio status */ 198 1.9.2.6 skrll sc_splitmic: 1, /* split TKIP MIC keys */ 199 1.9.2.6 skrll sc_needmib : 1, /* enable MIB stats intr */ 200 1.9.2.6 skrll sc_diversity : 1,/* enable rx diversity */ 201 1.9.2.6 skrll sc_hasveol : 1, /* tx VEOL support */ 202 1.9.2.6 skrll sc_ledstate: 1, /* LED on/off state */ 203 1.9.2.6 skrll sc_blinking: 1, /* LED blink operation active */ 204 1.9.2.6 skrll sc_mcastkey: 1, /* mcast key cache search */ 205 1.9.2.6 skrll sc_hasclrkey:1; /* CLR key supported */ 206 1.9.2.2 skrll /* rate tables */ 207 1.9.2.2 skrll const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 208 1.9.2.2 skrll const HAL_RATE_TABLE *sc_currates; /* current rate table */ 209 1.9.2.2 skrll enum ieee80211_phymode sc_curmode; /* current phy mode */ 210 1.9.2.6 skrll u_int16_t sc_curtxpow; /* current tx power limit */ 211 1.9.2.6 skrll HAL_CHANNEL sc_curchan; /* current h/w channel */ 212 1.9.2.2 skrll u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 213 1.9.2.6 skrll struct { 214 1.9.2.6 skrll u_int8_t ieeerate; /* IEEE rate */ 215 1.9.2.6 skrll u_int8_t rxflags; /* radiotap rx flags */ 216 1.9.2.6 skrll u_int8_t txflags; /* radiotap tx flags */ 217 1.9.2.6 skrll u_int16_t ledon; /* softled on time */ 218 1.9.2.6 skrll u_int16_t ledoff; /* softled off time */ 219 1.9.2.6 skrll } sc_hwmap[32]; /* h/w rate ix mappings */ 220 1.9.2.6 skrll u_int8_t sc_protrix; /* protection rate index */ 221 1.9.2.6 skrll u_int sc_txantenna; /* tx antenna (fixed or auto) */ 222 1.9.2.2 skrll HAL_INT sc_imask; /* interrupt mask copy */ 223 1.9.2.6 skrll u_int sc_keymax; /* size of key cache */ 224 1.9.2.6 skrll u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 225 1.9.2.6 skrll 226 1.9.2.6 skrll u_int sc_ledpin; /* GPIO pin for driving LED */ 227 1.9.2.6 skrll u_int sc_ledon; /* pin setting for LED on */ 228 1.9.2.6 skrll u_int sc_ledidle; /* idle polling interval */ 229 1.9.2.6 skrll int sc_ledevent; /* time of last LED event */ 230 1.9.2.6 skrll u_int8_t sc_rxrate; /* current rx rate for LED */ 231 1.9.2.6 skrll u_int8_t sc_txrate; /* current tx rate for LED */ 232 1.9.2.6 skrll u_int16_t sc_ledoff; /* off time for current blink */ 233 1.9.2.6 skrll struct callout sc_ledtimer; /* led off timer */ 234 1.9.2.2 skrll 235 1.9.2.2 skrll caddr_t sc_drvbpf; 236 1.9.2.2 skrll union { 237 1.9.2.2 skrll struct ath_tx_radiotap_header th; 238 1.9.2.2 skrll u_int8_t pad[64]; 239 1.9.2.2 skrll } u_tx_rt; 240 1.9.2.2 skrll int sc_tx_th_len; 241 1.9.2.2 skrll union { 242 1.9.2.2 skrll struct ath_rx_radiotap_header th; 243 1.9.2.2 skrll u_int8_t pad[64]; 244 1.9.2.2 skrll } u_rx_rt; 245 1.9.2.2 skrll int sc_rx_th_len; 246 1.9.2.2 skrll 247 1.9.2.2 skrll ath_task_t sc_fataltask; /* fatal int processing */ 248 1.9.2.2 skrll 249 1.9.2.6 skrll struct ath_descdma sc_rxdma; /* RX descriptos */ 250 1.9.2.6 skrll ath_bufhead sc_rxbuf; /* receive buffer */ 251 1.9.2.2 skrll u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 252 1.9.2.2 skrll ath_task_t sc_rxtask; /* rx int processing */ 253 1.9.2.6 skrll ath_task_t sc_rxorntask; /* rxorn int processing */ 254 1.9.2.6 skrll u_int8_t sc_defant; /* current default antenna */ 255 1.9.2.6 skrll u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 256 1.9.2.2 skrll 257 1.9.2.6 skrll struct ath_descdma sc_txdma; /* TX descriptors */ 258 1.9.2.6 skrll ath_bufhead sc_txbuf; /* transmit buffer */ 259 1.9.2.6 skrll ath_txbuf_lock_t sc_txbuflock; /* txbuf lock */ 260 1.9.2.2 skrll int sc_tx_timer; /* transmit timeout */ 261 1.9.2.6 skrll u_int sc_txqsetup; /* h/w queues setup */ 262 1.9.2.6 skrll u_int sc_txintrperiod;/* tx interrupt batching */ 263 1.9.2.6 skrll struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 264 1.9.2.6 skrll struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 265 1.9.2.2 skrll ath_task_t sc_txtask; /* tx int processing */ 266 1.9.2.2 skrll 267 1.9.2.6 skrll struct ath_descdma sc_bdma; /* beacon descriptors */ 268 1.9.2.6 skrll ath_bufhead sc_bbuf; /* beacon buffers */ 269 1.9.2.2 skrll u_int sc_bhalq; /* HAL q for outgoing beacons */ 270 1.9.2.6 skrll u_int sc_bmisscount; /* missed beacon transmits */ 271 1.9.2.6 skrll u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 272 1.9.2.6 skrll struct ath_txq *sc_cabq; /* tx q for cab frames */ 273 1.9.2.6 skrll struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 274 1.9.2.2 skrll ath_task_t sc_bmisstask; /* bmiss int processing */ 275 1.9.2.6 skrll ath_task_t sc_bstucktask; /* stuck beacon processing */ 276 1.9.2.6 skrll enum { 277 1.9.2.6 skrll OK, /* no change needed */ 278 1.9.2.6 skrll UPDATE, /* update pending */ 279 1.9.2.6 skrll COMMIT /* beacon sent, commit change */ 280 1.9.2.6 skrll } sc_updateslot; /* slot time update fsm */ 281 1.9.2.2 skrll 282 1.9.2.2 skrll struct callout sc_cal_ch; /* callout handle for cals */ 283 1.9.2.2 skrll struct callout sc_scan_ch; /* callout handle for scan */ 284 1.9.2.2 skrll void *sc_sdhook; /* shutdown hook */ 285 1.9.2.2 skrll void *sc_powerhook; /* power management hook */ 286 1.9.2.2 skrll u_int sc_flags; /* misc flags */ 287 1.9.2.2 skrll }; 288 1.9.2.6 skrll #define sc_if sc_ec.ec_if 289 1.9.2.6 skrll #define sc_tx_th u_tx_rt.th 290 1.9.2.6 skrll #define sc_rx_th u_rx_rt.th 291 1.9.2.6 skrll 292 1.9.2.2 skrll #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 293 1.9.2.2 skrll #define ATH_ENABLED 0x0002 /* chip is enabled */ 294 1.9.2.2 skrll 295 1.9.2.2 skrll #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 296 1.9.2.2 skrll 297 1.9.2.6 skrll #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 298 1.9.2.2 skrll 299 1.9.2.2 skrll int ath_attach(u_int16_t, struct ath_softc *); 300 1.9.2.2 skrll int ath_detach(struct ath_softc *); 301 1.9.2.2 skrll void ath_resume(struct ath_softc *, int); 302 1.9.2.2 skrll void ath_suspend(struct ath_softc *, int); 303 1.9.2.2 skrll int ath_activate(struct device *, enum devact); 304 1.9.2.2 skrll void ath_power(int, void *); 305 1.9.2.2 skrll void ath_shutdown(void *); 306 1.9.2.2 skrll int ath_intr(void *); 307 1.9.2.6 skrll int ath_reset(struct ifnet *); 308 1.9.2.6 skrll void ath_sysctlattach(struct ath_softc *); 309 1.9.2.6 skrll 310 1.9.2.6 skrll extern int ath_dwelltime; 311 1.9.2.6 skrll extern int ath_calinterval; 312 1.9.2.6 skrll extern int ath_outdoor; 313 1.9.2.6 skrll extern int ath_xchanmode; 314 1.9.2.6 skrll extern int ath_countrycode; 315 1.9.2.6 skrll extern int ath_regdomain; 316 1.9.2.6 skrll extern int ath_debug; 317 1.9.2.2 skrll 318 1.9.2.2 skrll /* 319 1.9.2.2 skrll * HAL definitions to comply with local coding convention. 320 1.9.2.2 skrll */ 321 1.9.2.6 skrll #define ath_hal_detach(_ah) \ 322 1.9.2.6 skrll ((*(_ah)->ah_detach)((_ah))) 323 1.9.2.2 skrll #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 324 1.9.2.2 skrll ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 325 1.9.2.2 skrll #define ath_hal_getratetable(_ah, _mode) \ 326 1.9.2.2 skrll ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 327 1.9.2.2 skrll #define ath_hal_getmac(_ah, _mac) \ 328 1.9.2.2 skrll ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 329 1.9.2.2 skrll #define ath_hal_setmac(_ah, _mac) \ 330 1.9.2.2 skrll ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 331 1.9.2.2 skrll #define ath_hal_intrset(_ah, _mask) \ 332 1.9.2.2 skrll ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 333 1.9.2.2 skrll #define ath_hal_intrget(_ah) \ 334 1.9.2.2 skrll ((*(_ah)->ah_getInterrupts)((_ah))) 335 1.9.2.2 skrll #define ath_hal_intrpend(_ah) \ 336 1.9.2.2 skrll ((*(_ah)->ah_isInterruptPending)((_ah))) 337 1.9.2.2 skrll #define ath_hal_getisr(_ah, _pmask) \ 338 1.9.2.2 skrll ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 339 1.9.2.2 skrll #define ath_hal_updatetxtriglevel(_ah, _inc) \ 340 1.9.2.2 skrll ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 341 1.9.2.2 skrll #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 342 1.9.2.2 skrll ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 343 1.9.2.6 skrll #define ath_hal_keycachesize(_ah) \ 344 1.9.2.6 skrll ((*(_ah)->ah_getKeyCacheSize)((_ah))) 345 1.9.2.2 skrll #define ath_hal_keyreset(_ah, _ix) \ 346 1.9.2.2 skrll ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 347 1.9.2.6 skrll #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 348 1.9.2.6 skrll ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 349 1.9.2.2 skrll #define ath_hal_keyisvalid(_ah, _ix) \ 350 1.9.2.2 skrll (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 351 1.9.2.2 skrll #define ath_hal_keysetmac(_ah, _ix, _mac) \ 352 1.9.2.2 skrll ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 353 1.9.2.2 skrll #define ath_hal_getrxfilter(_ah) \ 354 1.9.2.2 skrll ((*(_ah)->ah_getRxFilter)((_ah))) 355 1.9.2.2 skrll #define ath_hal_setrxfilter(_ah, _filter) \ 356 1.9.2.2 skrll ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 357 1.9.2.2 skrll #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 358 1.9.2.2 skrll ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 359 1.9.2.2 skrll #define ath_hal_waitforbeacon(_ah, _bf) \ 360 1.9.2.2 skrll ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 361 1.9.2.2 skrll #define ath_hal_putrxbuf(_ah, _bufaddr) \ 362 1.9.2.2 skrll ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 363 1.9.2.2 skrll #define ath_hal_gettsf32(_ah) \ 364 1.9.2.2 skrll ((*(_ah)->ah_getTsf32)((_ah))) 365 1.9.2.2 skrll #define ath_hal_gettsf64(_ah) \ 366 1.9.2.2 skrll ((*(_ah)->ah_getTsf64)((_ah))) 367 1.9.2.2 skrll #define ath_hal_resettsf(_ah) \ 368 1.9.2.2 skrll ((*(_ah)->ah_resetTsf)((_ah))) 369 1.9.2.2 skrll #define ath_hal_rxena(_ah) \ 370 1.9.2.2 skrll ((*(_ah)->ah_enableReceive)((_ah))) 371 1.9.2.2 skrll #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 372 1.9.2.2 skrll ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 373 1.9.2.2 skrll #define ath_hal_gettxbuf(_ah, _q) \ 374 1.9.2.2 skrll ((*(_ah)->ah_getTxDP)((_ah), (_q))) 375 1.9.2.6 skrll #define ath_hal_numtxpending(_ah, _q) \ 376 1.9.2.6 skrll ((*(_ah)->ah_numTxPending)((_ah), (_q))) 377 1.9.2.2 skrll #define ath_hal_getrxbuf(_ah) \ 378 1.9.2.2 skrll ((*(_ah)->ah_getRxDP)((_ah))) 379 1.9.2.2 skrll #define ath_hal_txstart(_ah, _q) \ 380 1.9.2.2 skrll ((*(_ah)->ah_startTxDma)((_ah), (_q))) 381 1.9.2.2 skrll #define ath_hal_setchannel(_ah, _chan) \ 382 1.9.2.2 skrll ((*(_ah)->ah_setChannel)((_ah), (_chan))) 383 1.9.2.2 skrll #define ath_hal_calibrate(_ah, _chan) \ 384 1.9.2.2 skrll ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 385 1.9.2.2 skrll #define ath_hal_setledstate(_ah, _state) \ 386 1.9.2.2 skrll ((*(_ah)->ah_setLedState)((_ah), (_state))) 387 1.9.2.2 skrll #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 388 1.9.2.2 skrll ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 389 1.9.2.2 skrll #define ath_hal_beaconreset(_ah) \ 390 1.9.2.2 skrll ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 391 1.9.2.6 skrll #define ath_hal_beacontimers(_ah, _bs) \ 392 1.9.2.6 skrll ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 393 1.9.2.2 skrll #define ath_hal_setassocid(_ah, _bss, _associd) \ 394 1.9.2.6 skrll ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 395 1.9.2.6 skrll #define ath_hal_phydisable(_ah) \ 396 1.9.2.6 skrll ((*(_ah)->ah_phyDisable)((_ah))) 397 1.9.2.2 skrll #define ath_hal_setopmode(_ah) \ 398 1.9.2.2 skrll ((*(_ah)->ah_setPCUConfig)((_ah))) 399 1.9.2.2 skrll #define ath_hal_stoptxdma(_ah, _qnum) \ 400 1.9.2.2 skrll ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 401 1.9.2.2 skrll #define ath_hal_stoppcurecv(_ah) \ 402 1.9.2.2 skrll ((*(_ah)->ah_stopPcuReceive)((_ah))) 403 1.9.2.2 skrll #define ath_hal_startpcurecv(_ah) \ 404 1.9.2.2 skrll ((*(_ah)->ah_startPcuReceive)((_ah))) 405 1.9.2.2 skrll #define ath_hal_stopdmarecv(_ah) \ 406 1.9.2.2 skrll ((*(_ah)->ah_stopDmaReceive)((_ah))) 407 1.9.2.2 skrll #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 408 1.9.2.2 skrll ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 409 1.9.2.2 skrll (_indata), (_insize), (_outdata), (_outsize))) 410 1.9.2.6 skrll #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 411 1.9.2.6 skrll ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 412 1.9.2.2 skrll #define ath_hal_resettxqueue(_ah, _q) \ 413 1.9.2.2 skrll ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 414 1.9.2.2 skrll #define ath_hal_releasetxqueue(_ah, _q) \ 415 1.9.2.2 skrll ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 416 1.9.2.6 skrll #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 417 1.9.2.6 skrll ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 418 1.9.2.6 skrll #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 419 1.9.2.6 skrll ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 420 1.9.2.2 skrll #define ath_hal_getrfgain(_ah) \ 421 1.9.2.2 skrll ((*(_ah)->ah_getRfGain)((_ah))) 422 1.9.2.6 skrll #define ath_hal_getdefantenna(_ah) \ 423 1.9.2.6 skrll ((*(_ah)->ah_getDefAntenna)((_ah))) 424 1.9.2.6 skrll #define ath_hal_setdefantenna(_ah, _ant) \ 425 1.9.2.6 skrll ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 426 1.9.2.6 skrll #define ath_hal_rxmonitor(_ah, _arg) \ 427 1.9.2.6 skrll ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 428 1.9.2.6 skrll #define ath_hal_mibevent(_ah, _stats) \ 429 1.9.2.6 skrll ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 430 1.9.2.6 skrll #define ath_hal_setslottime(_ah, _us) \ 431 1.9.2.6 skrll ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 432 1.9.2.6 skrll #define ath_hal_getslottime(_ah) \ 433 1.9.2.6 skrll ((*(_ah)->ah_getSlotTime)((_ah))) 434 1.9.2.6 skrll #define ath_hal_setacktimeout(_ah, _us) \ 435 1.9.2.6 skrll ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 436 1.9.2.6 skrll #define ath_hal_getacktimeout(_ah) \ 437 1.9.2.6 skrll ((*(_ah)->ah_getAckTimeout)((_ah))) 438 1.9.2.6 skrll #define ath_hal_setctstimeout(_ah, _us) \ 439 1.9.2.6 skrll ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 440 1.9.2.6 skrll #define ath_hal_getctstimeout(_ah) \ 441 1.9.2.6 skrll ((*(_ah)->ah_getCTSTimeout)((_ah))) 442 1.9.2.6 skrll #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 443 1.9.2.6 skrll ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 444 1.9.2.6 skrll #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 445 1.9.2.6 skrll ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 446 1.9.2.6 skrll #define ath_hal_ciphersupported(_ah, _cipher) \ 447 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 448 1.9.2.6 skrll #define ath_hal_getregdomain(_ah, _prd) \ 449 1.9.2.6 skrll ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 450 1.9.2.6 skrll #define ath_hal_getcountrycode(_ah, _pcc) \ 451 1.9.2.6 skrll (*(_pcc) = (_ah)->ah_countryCode) 452 1.9.2.6 skrll #define ath_hal_tkipsplit(_ah) \ 453 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 454 1.9.2.6 skrll #define ath_hal_hwphycounters(_ah) \ 455 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 456 1.9.2.6 skrll #define ath_hal_hasdiversity(_ah) \ 457 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 458 1.9.2.6 skrll #define ath_hal_getdiversity(_ah) \ 459 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 460 1.9.2.6 skrll #define ath_hal_setdiversity(_ah, _v) \ 461 1.9.2.6 skrll ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 462 1.9.2.6 skrll #define ath_hal_getdiag(_ah, _pv) \ 463 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 464 1.9.2.6 skrll #define ath_hal_setdiag(_ah, _v) \ 465 1.9.2.6 skrll ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 466 1.9.2.6 skrll #define ath_hal_getnumtxqueues(_ah, _pv) \ 467 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 468 1.9.2.6 skrll #define ath_hal_hasveol(_ah) \ 469 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 470 1.9.2.6 skrll #define ath_hal_hastxpowlimit(_ah) \ 471 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 472 1.9.2.6 skrll #define ath_hal_settxpowlimit(_ah, _pow) \ 473 1.9.2.6 skrll ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 474 1.9.2.6 skrll #define ath_hal_gettxpowlimit(_ah, _ppow) \ 475 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 476 1.9.2.6 skrll #define ath_hal_getmaxtxpow(_ah, _ppow) \ 477 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 478 1.9.2.6 skrll #define ath_hal_gettpscale(_ah, _scale) \ 479 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 480 1.9.2.6 skrll #define ath_hal_settpscale(_ah, _v) \ 481 1.9.2.6 skrll ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 482 1.9.2.6 skrll #define ath_hal_hastpc(_ah) \ 483 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 484 1.9.2.6 skrll #define ath_hal_gettpc(_ah) \ 485 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 486 1.9.2.6 skrll #define ath_hal_settpc(_ah, _v) \ 487 1.9.2.6 skrll ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 488 1.9.2.6 skrll #define ath_hal_hasbursting(_ah) \ 489 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 490 1.9.2.6 skrll #ifdef notyet 491 1.9.2.6 skrll #define ath_hal_hasmcastkeysearch(_ah) \ 492 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 493 1.9.2.6 skrll #define ath_hal_getmcastkeysearch(_ah) \ 494 1.9.2.6 skrll (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 495 1.9.2.6 skrll #else 496 1.9.2.6 skrll #define ath_hal_getmcastkeysearch(_ah) 0 497 1.9.2.6 skrll #endif 498 1.9.2.2 skrll 499 1.9.2.2 skrll #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 500 1.9.2.2 skrll ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 501 1.9.2.2 skrll #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 502 1.9.2.2 skrll ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 503 1.9.2.2 skrll #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 504 1.9.2.2 skrll _txr0, _txtr0, _keyix, _ant, _flags, \ 505 1.9.2.2 skrll _rtsrate, _rtsdura) \ 506 1.9.2.2 skrll ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 507 1.9.2.2 skrll (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 508 1.9.2.2 skrll (_flags), (_rtsrate), (_rtsdura))) 509 1.9.2.2 skrll #define ath_hal_setupxtxdesc(_ah, _ds, \ 510 1.9.2.2 skrll _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 511 1.9.2.2 skrll ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 512 1.9.2.2 skrll (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 513 1.9.2.6 skrll #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 514 1.9.2.6 skrll ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 515 1.9.2.2 skrll #define ath_hal_txprocdesc(_ah, _ds) \ 516 1.9.2.2 skrll ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 517 1.9.2.6 skrll #define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \ 518 1.9.2.6 skrll _gatingds, _txOpLimit, _ctsDuration) \ 519 1.9.2.6 skrll ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \ 520 1.9.2.6 skrll (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration))) 521 1.9.2.6 skrll 522 1.9.2.6 skrll #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 523 1.9.2.6 skrll ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 524 1.9.2.6 skrll #define ath_hal_gpioset(_ah, _gpio, _b) \ 525 1.9.2.6 skrll ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 526 1.9.2.2 skrll 527 1.9.2.2 skrll #endif /* _DEV_ATH_ATHVAR_H */ 528
Indexes created Tue Oct 21 07:10:13 GMT 2025