athvar.h revision 1.1
1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.6 2003/09/05 22:22:49 sam Exp $ 37 */ 38 39 /* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42 #ifndef _DEV_ATH_ATHVAR_H 43 #define _DEV_ATH_ATHVAR_H 44 45 #include <sys/taskqueue.h> 46 47 #include <contrib/dev/ath/ah.h> 48 #include <net80211/ieee80211_radiotap.h> 49 #include <dev/ath/if_athioctl.h> 50 51 #define ATH_TIMEOUT 1000 52 53 #define ATH_RXBUF 40 /* number of RX buffers */ 54 #define ATH_TXBUF 60 /* number of TX buffers */ 55 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 56 57 /* driver-specific node */ 58 struct ath_node { 59 struct ieee80211_node an_node; /* base class */ 60 u_int an_tx_ok; /* tx ok pkt */ 61 u_int an_tx_err; /* tx !ok pkt */ 62 u_int an_tx_retr; /* tx retry count */ 63 int an_tx_upper; /* tx upper rate req cnt */ 64 u_int an_tx_antenna; /* antenna for last good frame */ 65 u_int an_rx_antenna; /* antenna for last rcvd frame */ 66 }; 67 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 68 69 struct ath_buf { 70 TAILQ_ENTRY(ath_buf) bf_list; 71 int bf_nseg; 72 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 73 struct ath_desc *bf_desc; /* virtual addr of desc */ 74 bus_addr_t bf_daddr; /* physical addr of desc */ 75 struct mbuf *bf_m; /* mbuf for buf */ 76 struct ieee80211_node *bf_node; /* pointer to the node */ 77 bus_size_t bf_mapsize; 78 #define ATH_MAX_SCATTER 64 79 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 80 }; 81 82 struct ath_softc { 83 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 84 int (*sc_newstate)(struct ieee80211com *, 85 enum ieee80211_state, int); 86 device_t sc_dev; 87 bus_space_tag_t sc_st; /* bus space tag */ 88 bus_space_handle_t sc_sh; /* bus space handle */ 89 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 90 struct mtx sc_mtx; /* master lock (recursive) */ 91 struct ath_hal *sc_ah; /* Atheros HAL */ 92 unsigned int sc_invalid : 1,/* disable hardware accesses */ 93 sc_have11g : 1,/* have 11g support */ 94 sc_doani : 1,/* dynamic noise immunity */ 95 sc_probing : 1;/* probing AP on beacon miss */ 96 /* rate tables */ 97 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 98 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 99 enum ieee80211_phymode sc_curmode; /* current phy mode */ 100 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 101 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 102 HAL_INT sc_imask; /* interrupt mask copy */ 103 104 struct bpf_if *sc_drvbpf; 105 union { 106 struct ath_tx_radiotap_header th; 107 u_int8_t pad[64]; 108 } u_tx_rt; 109 union { 110 struct ath_rx_radiotap_header th; 111 u_int8_t pad[64]; 112 } u_rx_rt; 113 114 struct ath_desc *sc_desc; /* TX/RX descriptors */ 115 bus_dma_segment_t sc_dseg; 116 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 117 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 118 bus_addr_t sc_desc_len; /* size of sc_desc */ 119 120 struct task sc_fataltask; /* fatal int processing */ 121 struct task sc_rxorntask; /* rxorn int processing */ 122 123 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 124 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 125 struct task sc_rxtask; /* rx int processing */ 126 127 u_int sc_txhalq; /* HAL q for outgoing frames */ 128 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 129 int sc_tx_timer; /* transmit timeout */ 130 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 131 struct mtx sc_txbuflock; /* txbuf lock */ 132 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 133 struct mtx sc_txqlock; /* lock on txq and txlink */ 134 struct task sc_txtask; /* tx int processing */ 135 136 u_int sc_bhalq; /* HAL q for outgoing beacons */ 137 struct ath_buf *sc_bcbuf; /* beacon buffer */ 138 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 139 struct task sc_swbatask; /* swba int processing */ 140 struct task sc_bmisstask; /* bmiss int processing */ 141 142 struct callout sc_cal_ch; /* callout handle for cals */ 143 struct callout sc_scan_ch; /* callout handle for scan */ 144 struct ath_stats sc_stats; /* interface statistics */ 145 }; 146 #define sc_tx_th u_tx_rt.th 147 #define sc_rx_th u_rx_rt.th 148 149 int ath_attach(u_int16_t, struct ath_softc *); 150 int ath_detach(struct ath_softc *); 151 void ath_resume(struct ath_softc *); 152 void ath_suspend(struct ath_softc *); 153 void ath_shutdown(struct ath_softc *); 154 void ath_intr(void *); 155 156 /* 157 * HAL definitions to comply with local coding convention. 158 */ 159 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 160 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 161 #define ath_hal_getratetable(_ah, _mode) \ 162 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 163 #define ath_hal_getregdomain(_ah) \ 164 ((*(_ah)->ah_getRegDomain)((_ah))) 165 #define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 166 #define ath_hal_getmac(_ah, _mac) \ 167 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 168 #define ath_hal_detach(_ah) \ 169 ((*(_ah)->ah_detach)((_ah))) 170 #define ath_hal_intrset(_ah, _mask) \ 171 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 172 #define ath_hal_intrget(_ah) \ 173 ((*(_ah)->ah_getInterrupts)((_ah))) 174 #define ath_hal_intrpend(_ah) \ 175 ((*(_ah)->ah_isInterruptPending)((_ah))) 176 #define ath_hal_getisr(_ah, _pmask) \ 177 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 178 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 179 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 180 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 181 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 182 #define ath_hal_keyreset(_ah, _ix) \ 183 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 184 #define ath_hal_keyset(_ah, _ix, _pk) \ 185 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 186 #define ath_hal_keyisvalid(_ah, _ix) \ 187 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 188 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 189 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 190 #define ath_hal_getrxfilter(_ah) \ 191 ((*(_ah)->ah_getRxFilter)((_ah))) 192 #define ath_hal_setrxfilter(_ah, _filter) \ 193 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 194 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 195 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 196 #define ath_hal_waitforbeacon(_ah, _bf) \ 197 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 198 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 199 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 200 #define ath_hal_gettsf32(_ah) \ 201 ((*(_ah)->ah_getTsf32)((_ah))) 202 #define ath_hal_gettsf64(_ah) \ 203 ((*(_ah)->ah_getTsf64)((_ah))) 204 #define ath_hal_resettsf(_ah) \ 205 ((*(_ah)->ah_resetTsf)((_ah))) 206 #define ath_hal_rxena(_ah) \ 207 ((*(_ah)->ah_enableReceive)((_ah))) 208 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 209 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 210 #define ath_hal_gettxbuf(_ah, _q) \ 211 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 212 #define ath_hal_getrxbuf(_ah) \ 213 ((*(_ah)->ah_getRxDP)((_ah))) 214 #define ath_hal_txstart(_ah, _q) \ 215 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 216 #define ath_hal_setchannel(_ah, _chan) \ 217 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 218 #define ath_hal_calibrate(_ah, _chan) \ 219 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 220 #define ath_hal_setledstate(_ah, _state) \ 221 ((*(_ah)->ah_setLedState)((_ah), (_state))) 222 #define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 223 ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 224 #define ath_hal_beaconreset(_ah) \ 225 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 226 #define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 227 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 228 (_dc), (_cc))) 229 #define ath_hal_setassocid(_ah, _bss, _associd) \ 230 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 231 #define ath_hal_setopmode(_ah, _opmode) \ 232 ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 233 #define ath_hal_stoptxdma(_ah, _qnum) \ 234 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 235 #define ath_hal_stoppcurecv(_ah) \ 236 ((*(_ah)->ah_stopPcuReceive)((_ah))) 237 #define ath_hal_startpcurecv(_ah) \ 238 ((*(_ah)->ah_startPcuReceive)((_ah))) 239 #define ath_hal_stopdmarecv(_ah) \ 240 ((*(_ah)->ah_stopDmaReceive)((_ah))) 241 #define ath_hal_dumpstate(_ah) \ 242 ((*(_ah)->ah_dumpState)((_ah))) 243 #define ath_hal_dumpeeprom(_ah) \ 244 ((*(_ah)->ah_dumpEeprom)((_ah))) 245 #define ath_hal_dumprfgain(_ah) \ 246 ((*(_ah)->ah_dumpRfGain)((_ah))) 247 #define ath_hal_dumpani(_ah) \ 248 ((*(_ah)->ah_dumpAni)((_ah))) 249 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 250 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 251 #define ath_hal_resettxqueue(_ah, _q) \ 252 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 253 #define ath_hal_releasetxqueue(_ah, _q) \ 254 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 255 #define ath_hal_hasveol(_ah) \ 256 ((*(_ah)->ah_hasVEOL)((_ah))) 257 #define ath_hal_getrfgain(_ah) \ 258 ((*(_ah)->ah_getRfGain)((_ah))) 259 #define ath_hal_rxmonitor(_ah) \ 260 ((*(_ah)->ah_rxMonitor)((_ah))) 261 262 #define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 263 _rate, _antmode) \ 264 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 265 (_flen), (_hlen), (_rate), (_antmode))) 266 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 267 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 268 #define ath_hal_rxprocdesc(_ah, _ds) \ 269 ((*(_ah)->ah_procRxDesc)((_ah), (_ds))) 270 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 271 _txr0, _txtr0, _keyix, _ant, _flags, \ 272 _rtsrate, _rtsdura) \ 273 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 274 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 275 (_flags), (_rtsrate), (_rtsdura))) 276 #define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 277 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 278 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 279 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 280 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 281 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 282 #define ath_hal_txprocdesc(_ah, _ds) \ 283 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 284 285 #endif /* _DEV_ATH_ATHVAR_H */ 286
Indexes created Fri Sep 26 20:09:58 GMT 2025