athvar.h revision 1.1.1.3
1 /*- 2 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.14 2004/04/03 03:33:02 sam Exp $ 37 */ 38 39 /* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42 #ifndef _DEV_ATH_ATHVAR_H 43 #define _DEV_ATH_ATHVAR_H 44 45 #include <sys/taskqueue.h> 46 47 #include <contrib/dev/ath/ah.h> 48 #include <net80211/ieee80211_radiotap.h> 49 #include <dev/ath/if_athioctl.h> 50 51 #define ATH_TIMEOUT 1000 52 53 #define ATH_RXBUF 40 /* number of RX buffers */ 54 #define ATH_TXBUF 60 /* number of TX buffers */ 55 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 56 57 struct ath_recv_hist { 58 int arh_ticks; /* sample time by system clock */ 59 u_int8_t arh_rssi; /* rssi */ 60 u_int8_t arh_antenna; /* antenna */ 61 }; 62 #define ATH_RHIST_SIZE 16 /* number of samples */ 63 #define ATH_RHIST_NOTIME (~0) 64 65 /* driver-specific node */ 66 struct ath_node { 67 struct ieee80211_node an_node; /* base class */ 68 u_int an_tx_ok; /* tx ok pkt */ 69 u_int an_tx_err; /* tx !ok pkt */ 70 u_int an_tx_retr; /* tx retry count */ 71 int an_tx_upper; /* tx upper rate req cnt */ 72 u_int an_tx_antenna; /* antenna for last good frame */ 73 u_int an_rx_antenna; /* antenna for last rcvd frame */ 74 struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 75 u_int an_rx_hist_next;/* index of next ``free entry'' */ 76 }; 77 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 78 79 struct ath_buf { 80 TAILQ_ENTRY(ath_buf) bf_list; 81 int bf_nseg; 82 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 83 struct ath_desc *bf_desc; /* virtual addr of desc */ 84 bus_addr_t bf_daddr; /* physical addr of desc */ 85 struct mbuf *bf_m; /* mbuf for buf */ 86 struct ieee80211_node *bf_node; /* pointer to the node */ 87 bus_size_t bf_mapsize; 88 #define ATH_MAX_SCATTER 64 89 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 90 }; 91 92 struct ath_softc { 93 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 94 int (*sc_newstate)(struct ieee80211com *, 95 enum ieee80211_state, int); 96 void (*sc_node_free)(struct ieee80211com *, 97 struct ieee80211_node *); 98 void (*sc_node_copy)(struct ieee80211com *, 99 struct ieee80211_node *, 100 const struct ieee80211_node *); 101 device_t sc_dev; 102 bus_space_tag_t sc_st; /* bus space tag */ 103 bus_space_handle_t sc_sh; /* bus space handle */ 104 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 105 struct mtx sc_mtx; /* master lock (recursive) */ 106 struct ath_hal *sc_ah; /* Atheros HAL */ 107 unsigned int sc_invalid : 1,/* disable hardware accesses */ 108 sc_doani : 1,/* dynamic noise immunity */ 109 sc_probing : 1;/* probing AP on beacon miss */ 110 /* rate tables */ 111 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 112 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 113 enum ieee80211_phymode sc_curmode; /* current phy mode */ 114 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 115 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 116 HAL_INT sc_imask; /* interrupt mask copy */ 117 118 struct bpf_if *sc_drvbpf; 119 union { 120 struct ath_tx_radiotap_header th; 121 u_int8_t pad[64]; 122 } u_tx_rt; 123 int sc_tx_th_len; 124 union { 125 struct ath_rx_radiotap_header th; 126 u_int8_t pad[64]; 127 } u_rx_rt; 128 int sc_rx_th_len; 129 130 struct ath_desc *sc_desc; /* TX/RX descriptors */ 131 bus_dma_segment_t sc_dseg; 132 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 133 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 134 bus_addr_t sc_desc_len; /* size of sc_desc */ 135 136 struct task sc_fataltask; /* fatal int processing */ 137 struct task sc_rxorntask; /* rxorn int processing */ 138 139 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 140 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 141 struct task sc_rxtask; /* rx int processing */ 142 143 u_int sc_txhalq; /* HAL q for outgoing frames */ 144 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 145 int sc_tx_timer; /* transmit timeout */ 146 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 147 struct mtx sc_txbuflock; /* txbuf lock */ 148 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 149 struct mtx sc_txqlock; /* lock on txq and txlink */ 150 struct task sc_txtask; /* tx int processing */ 151 152 u_int sc_bhalq; /* HAL q for outgoing beacons */ 153 struct ath_buf *sc_bcbuf; /* beacon buffer */ 154 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 155 struct task sc_bmisstask; /* bmiss int processing */ 156 157 struct callout sc_cal_ch; /* callout handle for cals */ 158 struct callout sc_scan_ch; /* callout handle for scan */ 159 struct ath_stats sc_stats; /* interface statistics */ 160 }; 161 #define sc_tx_th u_tx_rt.th 162 #define sc_rx_th u_rx_rt.th 163 164 #define ATH_LOCK_INIT(_sc) \ 165 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 166 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 167 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 168 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 169 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 170 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 171 172 #define ATH_TXBUF_LOCK_INIT(_sc) \ 173 mtx_init(&(_sc)->sc_txbuflock, \ 174 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 175 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 176 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 177 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 178 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 179 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 180 181 #define ATH_TXQ_LOCK_INIT(_sc) \ 182 mtx_init(&(_sc)->sc_txqlock, \ 183 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 184 #define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 185 #define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 186 #define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 187 #define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 188 189 int ath_attach(u_int16_t, struct ath_softc *); 190 int ath_detach(struct ath_softc *); 191 void ath_resume(struct ath_softc *); 192 void ath_suspend(struct ath_softc *); 193 void ath_shutdown(struct ath_softc *); 194 void ath_intr(void *); 195 196 /* 197 * HAL definitions to comply with local coding convention. 198 */ 199 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 200 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 201 #define ath_hal_getratetable(_ah, _mode) \ 202 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 203 #define ath_hal_getregdomain(_ah) \ 204 ((*(_ah)->ah_getRegDomain)((_ah))) 205 #define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 206 #define ath_hal_getmac(_ah, _mac) \ 207 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 208 #define ath_hal_detach(_ah) \ 209 ((*(_ah)->ah_detach)((_ah))) 210 #define ath_hal_intrset(_ah, _mask) \ 211 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 212 #define ath_hal_intrget(_ah) \ 213 ((*(_ah)->ah_getInterrupts)((_ah))) 214 #define ath_hal_intrpend(_ah) \ 215 ((*(_ah)->ah_isInterruptPending)((_ah))) 216 #define ath_hal_getisr(_ah, _pmask) \ 217 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 218 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 219 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 220 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 221 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 222 #define ath_hal_keyreset(_ah, _ix) \ 223 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 224 #define ath_hal_keyset(_ah, _ix, _pk) \ 225 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 226 #define ath_hal_keyisvalid(_ah, _ix) \ 227 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 228 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 229 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 230 #define ath_hal_getrxfilter(_ah) \ 231 ((*(_ah)->ah_getRxFilter)((_ah))) 232 #define ath_hal_setrxfilter(_ah, _filter) \ 233 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 234 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 235 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 236 #define ath_hal_waitforbeacon(_ah, _bf) \ 237 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 238 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 239 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 240 #define ath_hal_gettsf32(_ah) \ 241 ((*(_ah)->ah_getTsf32)((_ah))) 242 #define ath_hal_gettsf64(_ah) \ 243 ((*(_ah)->ah_getTsf64)((_ah))) 244 #define ath_hal_resettsf(_ah) \ 245 ((*(_ah)->ah_resetTsf)((_ah))) 246 #define ath_hal_rxena(_ah) \ 247 ((*(_ah)->ah_enableReceive)((_ah))) 248 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 249 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 250 #define ath_hal_gettxbuf(_ah, _q) \ 251 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 252 #define ath_hal_getrxbuf(_ah) \ 253 ((*(_ah)->ah_getRxDP)((_ah))) 254 #define ath_hal_txstart(_ah, _q) \ 255 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 256 #define ath_hal_setchannel(_ah, _chan) \ 257 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 258 #define ath_hal_calibrate(_ah, _chan) \ 259 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 260 #define ath_hal_setledstate(_ah, _state) \ 261 ((*(_ah)->ah_setLedState)((_ah), (_state))) 262 #define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 263 ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 264 #define ath_hal_beaconreset(_ah) \ 265 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 266 #define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 267 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 268 (_dc), (_cc))) 269 #define ath_hal_setassocid(_ah, _bss, _associd) \ 270 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 271 #define ath_hal_setopmode(_ah, _opmode) \ 272 ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 273 #define ath_hal_stoptxdma(_ah, _qnum) \ 274 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 275 #define ath_hal_stoppcurecv(_ah) \ 276 ((*(_ah)->ah_stopPcuReceive)((_ah))) 277 #define ath_hal_startpcurecv(_ah) \ 278 ((*(_ah)->ah_startPcuReceive)((_ah))) 279 #define ath_hal_stopdmarecv(_ah) \ 280 ((*(_ah)->ah_stopDmaReceive)((_ah))) 281 #define ath_hal_dumpstate(_ah) \ 282 ((*(_ah)->ah_dumpState)((_ah))) 283 #define ath_hal_getdiagstate(_ah, _id, _data, _size) \ 284 ((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size))) 285 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 286 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 287 #define ath_hal_resettxqueue(_ah, _q) \ 288 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 289 #define ath_hal_releasetxqueue(_ah, _q) \ 290 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 291 #define ath_hal_hasveol(_ah) \ 292 ((*(_ah)->ah_hasVEOL)((_ah))) 293 #define ath_hal_getrfgain(_ah) \ 294 ((*(_ah)->ah_getRfGain)((_ah))) 295 #define ath_hal_rxmonitor(_ah) \ 296 ((*(_ah)->ah_rxMonitor)((_ah))) 297 298 #define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 299 _rate, _antmode) \ 300 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 301 (_flen), (_hlen), (_rate), (_antmode))) 302 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 303 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 304 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 305 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 306 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 307 _txr0, _txtr0, _keyix, _ant, _flags, \ 308 _rtsrate, _rtsdura) \ 309 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 310 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 311 (_flags), (_rtsrate), (_rtsdura))) 312 #define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 313 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 314 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 315 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 316 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 317 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 318 #define ath_hal_txprocdesc(_ah, _ds) \ 319 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 320 321 #endif /* _DEV_ATH_ATHVAR_H */ 322
Indexes created Sat Oct 18 17:09:52 GMT 2025