athvar.h revision 1.11
1 /* $NetBSD: athvar.h,v 1.11 2005/06/22 06:15:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 * 38 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.20 2005/01/24 20:31:24 sam Exp $ 39 */ 40 41 /* 42 * Defintions for the Atheros Wireless LAN controller driver. 43 */ 44 #ifndef _DEV_ATH_ATHVAR_H 45 #define _DEV_ATH_ATHVAR_H 46 47 #include <dev/ic/ath_netbsd.h> 48 #include <contrib/dev/ic/athhal.h> 49 #include <net80211/ieee80211_radiotap.h> 50 #include <dev/ic/athioctl.h> 51 #include <dev/ic/athrate.h> 52 53 #define ATH_TIMEOUT 1000 54 55 #define ATH_RXBUF 40 /* number of RX buffers */ 56 #define ATH_TXBUF 100 /* number of TX buffers */ 57 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 58 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 59 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 60 61 /* driver-specific node state */ 62 struct ath_node { 63 struct ieee80211_node an_node; /* base class */ 64 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 65 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ 66 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 67 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ 68 /* variable-length rate control state follows */ 69 }; 70 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 71 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 72 73 #define ATH_RSSI_LPF_LEN 10 74 #define ATH_RSSI_DUMMY_MARKER 0x127 75 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 76 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 77 #define ATH_LPF_RSSI(x, y, len) \ 78 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 79 #define ATH_RSSI_LPF(x, y) do { \ 80 if ((y) >= -20) \ 81 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 82 } while (0) 83 84 struct ath_buf { 85 STAILQ_ENTRY(ath_buf) bf_list; 86 #define bf_nseg bf_dmamap->dm_nsegs 87 struct ath_desc *bf_desc; /* virtual addr of desc */ 88 bus_addr_t bf_daddr; /* physical addr of desc */ 89 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 90 struct mbuf *bf_m; /* mbuf for buf */ 91 struct ieee80211_node *bf_node; /* pointer to the node */ 92 #define bf_mapsize bf_dmamap->dm_mapsize 93 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 94 #define bf_segs bf_dmamap->dm_segs 95 }; 96 typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 97 98 /* 99 * DMA state for tx/rx descriptors. 100 */ 101 struct ath_descdma { 102 const char* dd_name; 103 struct ath_desc *dd_desc; /* descriptors */ 104 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 105 bus_addr_t dd_desc_len; /* size of dd_desc */ 106 bus_dma_segment_t dd_dseg; 107 int dd_dnseg; /* number of segments */ 108 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 109 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 110 struct ath_buf *dd_bufptr; /* associated buffers */ 111 }; 112 113 /* 114 * Data transmit queue state. One of these exists for each 115 * hardware transmit queue. Packets sent to us from above 116 * are assigned to queues based on their priority. Not all 117 * devices support a complete set of hardware transmit queues. 118 * For those devices the array sc_ac2q will map multiple 119 * priorities to fewer hardware queues (typically all to one 120 * hardware queue). 121 */ 122 struct ath_txq { 123 u_int axq_qnum; /* hardware q number */ 124 u_int axq_depth; /* queue depth (stat only) */ 125 u_int axq_intrcnt; /* interrupt count */ 126 u_int32_t *axq_link; /* link ptr in last TX desc */ 127 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 128 ath_txq_lock_t axq_lock; /* lock on q and link */ 129 /* 130 * State for patching up CTS when bursting. 131 */ 132 struct ath_buf *axq_linkbuf; /* va of last buffer */ 133 struct ath_desc *axq_lastdsWithCTS; 134 /* first desc of last descriptor 135 * that contains CTS 136 */ 137 struct ath_desc *axq_gatingds; /* final desc of the gating desc 138 * that determines whether 139 * lastdsWithCTS has been DMA'ed 140 * or not 141 */ 142 }; 143 144 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 145 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 146 (_tq)->axq_depth++; \ 147 } while (0) 148 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 149 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 150 (_tq)->axq_depth--; \ 151 } while (0) 152 153 struct ath_softc { 154 struct device sc_dev; 155 struct ethercom sc_ec; /* interface common */ 156 struct ath_stats sc_stats; /* interface statistics */ 157 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 158 int (*sc_enable)(struct ath_softc *); 159 void (*sc_disable)(struct ath_softc *); 160 void (*sc_power)(struct ath_softc *, int); 161 int sc_regdomain; 162 int sc_countrycode; 163 int sc_debug; 164 struct sysctllog *sc_sysctllog; 165 void (*sc_recv_mgmt)(struct ieee80211com *, 166 struct mbuf *, 167 struct ieee80211_node *, 168 int, int, u_int32_t); 169 int (*sc_newstate)(struct ieee80211com *, 170 enum ieee80211_state, int); 171 void (*sc_node_free)(struct ieee80211_node *); 172 bus_space_tag_t sc_st; /* bus space tag */ 173 bus_space_handle_t sc_sh; /* bus space handle */ 174 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 175 ath_lock_t sc_mtx; /* master lock (recursive) */ 176 struct ath_hal *sc_ah; /* Atheros HAL */ 177 struct ath_ratectrl *sc_rc; /* tx rate control support */ 178 void (*sc_setdefantenna)(struct ath_softc *, u_int); 179 unsigned int sc_invalid : 1,/* disable hardware accesses */ 180 sc_mrretry : 1, /* multi-rate retry support */ 181 sc_softled : 1, /* enable LED gpio status */ 182 sc_splitmic: 1, /* split TKIP MIC keys */ 183 sc_needmib : 1, /* enable MIB stats intr */ 184 sc_hasdiversity : 1,/* rx diversity available */ 185 sc_diversity : 1,/* enable rx diversity */ 186 sc_hasveol : 1, /* tx VEOL support */ 187 sc_hastpc : 1, /* per-packet TPC support */ 188 sc_ledstate: 1, /* LED on/off state */ 189 sc_blinking: 1, /* LED blink operation active */ 190 sc_mcastkey: 1; /* mcast key cache search */ 191 /* rate tables */ 192 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 193 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 194 enum ieee80211_phymode sc_curmode; /* current phy mode */ 195 u_int16_t sc_curtxpow; /* current tx power limit */ 196 HAL_CHANNEL sc_curchan; /* current h/w channel */ 197 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 198 struct { 199 u_int8_t ieeerate; /* IEEE rate */ 200 u_int8_t rxflags; /* radiotap rx flags */ 201 u_int8_t txflags; /* radiotap tx flags */ 202 u_int16_t ledon; /* softled on time */ 203 u_int16_t ledoff; /* softled off time */ 204 } sc_hwmap[32]; /* h/w rate ix mappings */ 205 u_int8_t sc_protrix; /* protection rate index */ 206 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 207 HAL_INT sc_imask; /* interrupt mask copy */ 208 u_int sc_keymax; /* size of key cache */ 209 u_int8_t sc_keymap[16]; /* bit map of key cache use */ 210 211 u_int sc_ledpin; /* GPIO pin for driving LED */ 212 u_int sc_ledon; /* pin setting for LED on */ 213 u_int sc_ledidle; /* idle polling interval */ 214 int sc_ledevent; /* time of last LED event */ 215 u_int8_t sc_rxrate; /* current rx rate for LED */ 216 u_int8_t sc_txrate; /* current tx rate for LED */ 217 u_int16_t sc_ledoff; /* off time for current blink */ 218 struct callout sc_ledtimer; /* led off timer */ 219 220 caddr_t sc_drvbpf; 221 union { 222 struct ath_tx_radiotap_header th; 223 u_int8_t pad[64]; 224 } u_tx_rt; 225 int sc_tx_th_len; 226 union { 227 struct ath_rx_radiotap_header th; 228 u_int8_t pad[64]; 229 } u_rx_rt; 230 int sc_rx_th_len; 231 232 ath_task_t sc_fataltask; /* fatal int processing */ 233 234 struct ath_descdma sc_rxdma; /* RX descriptos */ 235 ath_bufhead sc_rxbuf; /* receive buffer */ 236 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 237 ath_task_t sc_rxtask; /* rx int processing */ 238 ath_task_t sc_rxorntask; /* rxorn int processing */ 239 u_int8_t sc_defant; /* current default antenna */ 240 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 241 242 struct ath_descdma sc_txdma; /* TX descriptors */ 243 ath_bufhead sc_txbuf; /* transmit buffer */ 244 ath_txbuf_lock_t sc_txbuflock; /* txbuf lock */ 245 int sc_tx_timer; /* transmit timeout */ 246 u_int sc_txqsetup; /* h/w queues setup */ 247 u_int sc_txintrperiod;/* tx interrupt batching */ 248 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 249 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 250 ath_task_t sc_txtask; /* tx int processing */ 251 252 struct ath_descdma sc_bdma; /* beacon descriptors */ 253 ath_bufhead sc_bbuf; /* beacon buffers */ 254 u_int sc_bhalq; /* HAL q for outgoing beacons */ 255 u_int sc_bmisscount; /* missed beacon transmits */ 256 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 257 struct ath_txq *sc_cabq; /* tx q for cab frames */ 258 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 259 ath_task_t sc_bmisstask; /* bmiss int processing */ 260 ath_task_t sc_bstucktask; /* stuck beacon processing */ 261 enum { 262 OK, /* no change needed */ 263 UPDATE, /* update pending */ 264 COMMIT /* beacon sent, commit change */ 265 } sc_updateslot; /* slot time update fsm */ 266 267 struct callout sc_cal_ch; /* callout handle for cals */ 268 struct callout sc_scan_ch; /* callout handle for scan */ 269 void *sc_sdhook; /* shutdown hook */ 270 void *sc_powerhook; /* power management hook */ 271 u_int sc_flags; /* misc flags */ 272 }; 273 #define sc_if sc_ec.ec_if 274 #define sc_tx_th u_tx_rt.th 275 #define sc_rx_th u_rx_rt.th 276 277 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 278 #define ATH_ENABLED 0x0002 /* chip is enabled */ 279 280 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 281 282 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 283 284 int ath_attach(u_int16_t, struct ath_softc *); 285 int ath_detach(struct ath_softc *); 286 void ath_resume(struct ath_softc *, int); 287 void ath_suspend(struct ath_softc *, int); 288 int ath_activate(struct device *, enum devact); 289 void ath_power(int, void *); 290 void ath_shutdown(void *); 291 int ath_intr(void *); 292 int ath_reset(struct ifnet *); 293 void ath_sysctlattach(struct ath_softc *); 294 295 extern int ath_dwelltime; 296 extern int ath_calinterval; 297 extern int ath_outdoor; 298 extern int ath_xchanmode; 299 extern int ath_countrycode; 300 extern int ath_regdomain; 301 extern int ath_debug; 302 303 /* 304 * HAL definitions to comply with local coding convention. 305 */ 306 #define ath_hal_detach(_ah) \ 307 ((*(_ah)->ah_detach)((_ah))) 308 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 309 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 310 #define ath_hal_getratetable(_ah, _mode) \ 311 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 312 #define ath_hal_getmac(_ah, _mac) \ 313 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 314 #define ath_hal_setmac(_ah, _mac) \ 315 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 316 #define ath_hal_intrset(_ah, _mask) \ 317 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 318 #define ath_hal_intrget(_ah) \ 319 ((*(_ah)->ah_getInterrupts)((_ah))) 320 #define ath_hal_intrpend(_ah) \ 321 ((*(_ah)->ah_isInterruptPending)((_ah))) 322 #define ath_hal_getisr(_ah, _pmask) \ 323 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 324 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 325 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 326 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 327 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 328 #define ath_hal_keycachesize(_ah) \ 329 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 330 #define ath_hal_keyreset(_ah, _ix) \ 331 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 332 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 333 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 334 #define ath_hal_keyisvalid(_ah, _ix) \ 335 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 336 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 337 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 338 #define ath_hal_getrxfilter(_ah) \ 339 ((*(_ah)->ah_getRxFilter)((_ah))) 340 #define ath_hal_setrxfilter(_ah, _filter) \ 341 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 342 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 343 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 344 #define ath_hal_waitforbeacon(_ah, _bf) \ 345 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 346 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 347 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 348 #define ath_hal_gettsf32(_ah) \ 349 ((*(_ah)->ah_getTsf32)((_ah))) 350 #define ath_hal_gettsf64(_ah) \ 351 ((*(_ah)->ah_getTsf64)((_ah))) 352 #define ath_hal_resettsf(_ah) \ 353 ((*(_ah)->ah_resetTsf)((_ah))) 354 #define ath_hal_rxena(_ah) \ 355 ((*(_ah)->ah_enableReceive)((_ah))) 356 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 357 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 358 #define ath_hal_gettxbuf(_ah, _q) \ 359 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 360 #define ath_hal_numtxpending(_ah, _q) \ 361 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 362 #define ath_hal_getrxbuf(_ah) \ 363 ((*(_ah)->ah_getRxDP)((_ah))) 364 #define ath_hal_txstart(_ah, _q) \ 365 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 366 #define ath_hal_setchannel(_ah, _chan) \ 367 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 368 #define ath_hal_calibrate(_ah, _chan) \ 369 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 370 #define ath_hal_setledstate(_ah, _state) \ 371 ((*(_ah)->ah_setLedState)((_ah), (_state))) 372 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 373 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 374 #define ath_hal_beaconreset(_ah) \ 375 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 376 #define ath_hal_beacontimers(_ah, _bs) \ 377 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 378 #define ath_hal_setassocid(_ah, _bss, _associd) \ 379 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 380 #define ath_hal_phydisable(_ah) \ 381 ((*(_ah)->ah_phyDisable)((_ah))) 382 #define ath_hal_setopmode(_ah) \ 383 ((*(_ah)->ah_setPCUConfig)((_ah))) 384 #define ath_hal_stoptxdma(_ah, _qnum) \ 385 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 386 #define ath_hal_stoppcurecv(_ah) \ 387 ((*(_ah)->ah_stopPcuReceive)((_ah))) 388 #define ath_hal_startpcurecv(_ah) \ 389 ((*(_ah)->ah_startPcuReceive)((_ah))) 390 #define ath_hal_stopdmarecv(_ah) \ 391 ((*(_ah)->ah_stopDmaReceive)((_ah))) 392 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 393 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 394 (_indata), (_insize), (_outdata), (_outsize))) 395 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 396 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 397 #define ath_hal_resettxqueue(_ah, _q) \ 398 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 399 #define ath_hal_releasetxqueue(_ah, _q) \ 400 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 401 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 402 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 403 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 404 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 405 #define ath_hal_getrfgain(_ah) \ 406 ((*(_ah)->ah_getRfGain)((_ah))) 407 #define ath_hal_getdefantenna(_ah) \ 408 ((*(_ah)->ah_getDefAntenna)((_ah))) 409 #define ath_hal_setdefantenna(_ah, _ant) \ 410 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 411 #define ath_hal_rxmonitor(_ah, _arg) \ 412 ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 413 #define ath_hal_mibevent(_ah, _stats) \ 414 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 415 #define ath_hal_setslottime(_ah, _us) \ 416 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 417 #define ath_hal_getslottime(_ah) \ 418 ((*(_ah)->ah_getSlotTime)((_ah))) 419 #define ath_hal_setacktimeout(_ah, _us) \ 420 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 421 #define ath_hal_getacktimeout(_ah) \ 422 ((*(_ah)->ah_getAckTimeout)((_ah))) 423 #define ath_hal_setctstimeout(_ah, _us) \ 424 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 425 #define ath_hal_getctstimeout(_ah) \ 426 ((*(_ah)->ah_getCTSTimeout)((_ah))) 427 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 428 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 429 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 430 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 431 #define ath_hal_ciphersupported(_ah, _cipher) \ 432 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 433 #define ath_hal_getregdomain(_ah, _prd) \ 434 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 435 #define ath_hal_getcountrycode(_ah, _pcc) \ 436 (*(_pcc) = (_ah)->ah_countryCode) 437 #define ath_hal_tkipsplit(_ah) \ 438 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 439 #define ath_hal_hwphycounters(_ah) \ 440 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 441 #define ath_hal_hasdiversity(_ah) \ 442 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 443 #define ath_hal_getdiversity(_ah) \ 444 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 445 #define ath_hal_setdiversity(_ah, _v) \ 446 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 447 #define ath_hal_getdiag(_ah, _pv) \ 448 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 449 #define ath_hal_setdiag(_ah, _v) \ 450 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 451 #define ath_hal_getnumtxqueues(_ah, _pv) \ 452 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 453 #define ath_hal_hasveol(_ah) \ 454 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 455 #define ath_hal_hastxpowlimit(_ah) \ 456 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 457 #define ath_hal_settxpowlimit(_ah, _pow) \ 458 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 459 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 460 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 461 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 462 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 463 #define ath_hal_gettpscale(_ah, _scale) \ 464 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 465 #define ath_hal_settpscale(_ah, _v) \ 466 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 467 #define ath_hal_hastpc(_ah) \ 468 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 469 #define ath_hal_gettpc(_ah) \ 470 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 471 #define ath_hal_settpc(_ah, _v) \ 472 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 473 #define ath_hal_hasbursting(_ah) \ 474 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 475 476 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 477 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 478 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 479 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 480 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 481 _txr0, _txtr0, _keyix, _ant, _flags, \ 482 _rtsrate, _rtsdura) \ 483 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 484 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 485 (_flags), (_rtsrate), (_rtsdura))) 486 #define ath_hal_setupxtxdesc(_ah, _ds, \ 487 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 488 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 489 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 490 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 491 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 492 #define ath_hal_txprocdesc(_ah, _ds) \ 493 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 494 #define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \ 495 _gatingds, _txOpLimit, _ctsDuration) \ 496 ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \ 497 (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration))) 498 499 #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 500 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 501 #define ath_hal_gpioset(_ah, _gpio, _b) \ 502 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 503 504 #endif /* _DEV_ATH_ATHVAR_H */ 505
Indexes created Fri Sep 26 20:09:58 GMT 2025