athvar.h revision 1.14
1 /* $NetBSD: athvar.h,v 1.14 2005/11/18 16:48:31 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 * 38 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $ 39 */ 40 41 /* 42 * Defintions for the Atheros Wireless LAN controller driver. 43 */ 44 #ifndef _DEV_ATH_ATHVAR_H 45 #define _DEV_ATH_ATHVAR_H 46 47 #include <dev/ic/ath_netbsd.h> 48 #include <contrib/dev/ic/athhal.h> 49 #include <net80211/ieee80211_radiotap.h> 50 #include <dev/ic/athioctl.h> 51 #include <dev/ic/athrate.h> 52 53 #define ATH_TIMEOUT 1000 54 55 #define ATH_RXBUF 40 /* number of RX buffers */ 56 #define ATH_TXBUF 100 /* number of TX buffers */ 57 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 58 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 59 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 60 61 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 62 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 63 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 64 65 /* 66 * The key cache is used for h/w cipher state and also for 67 * tracking station state such as the current tx antenna. 68 * We also setup a mapping table between key cache slot indices 69 * and station state to short-circuit node lookups on rx. 70 * Different parts have different size key caches. We handle 71 * up to ATH_KEYMAX entries (could dynamically allocate state). 72 */ 73 #define ATH_KEYMAX 128 /* max key cache size we handle */ 74 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 75 76 /* driver-specific node state */ 77 struct ath_node { 78 struct ieee80211_node an_node; /* base class */ 79 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 80 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ 81 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 82 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ 83 /* variable-length rate control state follows */ 84 }; 85 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 86 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 87 88 #define ATH_RSSI_LPF_LEN 10 89 #define ATH_RSSI_DUMMY_MARKER 0x127 90 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 91 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 92 #define ATH_LPF_RSSI(x, y, len) \ 93 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 94 #define ATH_RSSI_LPF(x, y) do { \ 95 if ((y) >= -20) \ 96 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 97 } while (0) 98 99 struct ath_buf { 100 STAILQ_ENTRY(ath_buf) bf_list; 101 #define bf_nseg bf_dmamap->dm_nsegs 102 int bf_flags; /* tx descriptor flags */ 103 struct ath_desc *bf_desc; /* virtual addr of desc */ 104 bus_addr_t bf_daddr; /* physical addr of desc */ 105 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 106 struct mbuf *bf_m; /* mbuf for buf */ 107 struct ieee80211_node *bf_node; /* pointer to the node */ 108 #define bf_mapsize bf_dmamap->dm_mapsize 109 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 110 #define bf_segs bf_dmamap->dm_segs 111 }; 112 typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 113 114 /* 115 * DMA state for tx/rx descriptors. 116 */ 117 struct ath_descdma { 118 const char* dd_name; 119 struct ath_desc *dd_desc; /* descriptors */ 120 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 121 bus_addr_t dd_desc_len; /* size of dd_desc */ 122 bus_dma_segment_t dd_dseg; 123 int dd_dnseg; /* number of segments */ 124 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 125 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 126 struct ath_buf *dd_bufptr; /* associated buffers */ 127 }; 128 129 /* 130 * Data transmit queue state. One of these exists for each 131 * hardware transmit queue. Packets sent to us from above 132 * are assigned to queues based on their priority. Not all 133 * devices support a complete set of hardware transmit queues. 134 * For those devices the array sc_ac2q will map multiple 135 * priorities to fewer hardware queues (typically all to one 136 * hardware queue). 137 */ 138 struct ath_txq { 139 u_int axq_qnum; /* hardware q number */ 140 u_int axq_depth; /* queue depth (stat only) */ 141 u_int axq_intrcnt; /* interrupt count */ 142 u_int32_t *axq_link; /* link ptr in last TX desc */ 143 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 144 ath_txq_lock_t axq_lock; /* lock on q and link */ 145 /* 146 * State for patching up CTS when bursting. 147 */ 148 struct ath_buf *axq_linkbuf; /* va of last buffer */ 149 struct ath_desc *axq_lastdsWithCTS; 150 /* first desc of last descriptor 151 * that contains CTS 152 */ 153 struct ath_desc *axq_gatingds; /* final desc of the gating desc 154 * that determines whether 155 * lastdsWithCTS has been DMA'ed 156 * or not 157 */ 158 }; 159 160 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 161 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 162 (_tq)->axq_depth++; \ 163 } while (0) 164 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 165 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 166 (_tq)->axq_depth--; \ 167 } while (0) 168 169 struct ath_softc { 170 struct device sc_dev; 171 struct ethercom sc_ec; /* interface common */ 172 struct ath_stats sc_stats; /* interface statistics */ 173 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 174 int (*sc_enable)(struct ath_softc *); 175 void (*sc_disable)(struct ath_softc *); 176 void (*sc_power)(struct ath_softc *, int); 177 int sc_regdomain; 178 int sc_countrycode; 179 int sc_debug; 180 struct sysctllog *sc_sysctllog; 181 void (*sc_recv_mgmt)(struct ieee80211com *, 182 struct mbuf *, 183 struct ieee80211_node *, 184 int, int, u_int32_t); 185 int (*sc_newstate)(struct ieee80211com *, 186 enum ieee80211_state, int); 187 void (*sc_node_free)(struct ieee80211_node *); 188 bus_space_tag_t sc_st; /* bus space tag */ 189 bus_space_handle_t sc_sh; /* bus space handle */ 190 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 191 ath_lock_t sc_mtx; /* master lock (recursive) */ 192 struct ath_hal *sc_ah; /* Atheros HAL */ 193 struct ath_ratectrl *sc_rc; /* tx rate control support */ 194 void (*sc_setdefantenna)(struct ath_softc *, u_int); 195 unsigned int sc_invalid : 1, /* disable hardware accesses */ 196 sc_mrretry : 1, /* multi-rate retry support */ 197 sc_softled : 1, /* enable LED gpio status */ 198 sc_splitmic: 1, /* split TKIP MIC keys */ 199 sc_needmib : 1, /* enable MIB stats intr */ 200 sc_diversity : 1,/* enable rx diversity */ 201 sc_hasveol : 1, /* tx VEOL support */ 202 sc_ledstate: 1, /* LED on/off state */ 203 sc_blinking: 1, /* LED blink operation active */ 204 sc_mcastkey: 1, /* mcast key cache search */ 205 sc_hasclrkey:1; /* CLR key supported */ 206 /* rate tables */ 207 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 208 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 209 enum ieee80211_phymode sc_curmode; /* current phy mode */ 210 u_int16_t sc_curtxpow; /* current tx power limit */ 211 HAL_CHANNEL sc_curchan; /* current h/w channel */ 212 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 213 struct { 214 u_int8_t ieeerate; /* IEEE rate */ 215 u_int8_t rxflags; /* radiotap rx flags */ 216 u_int8_t txflags; /* radiotap tx flags */ 217 u_int16_t ledon; /* softled on time */ 218 u_int16_t ledoff; /* softled off time */ 219 } sc_hwmap[32]; /* h/w rate ix mappings */ 220 u_int8_t sc_protrix; /* protection rate index */ 221 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 222 HAL_INT sc_imask; /* interrupt mask copy */ 223 u_int sc_keymax; /* size of key cache */ 224 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 225 226 u_int sc_ledpin; /* GPIO pin for driving LED */ 227 u_int sc_ledon; /* pin setting for LED on */ 228 u_int sc_ledidle; /* idle polling interval */ 229 int sc_ledevent; /* time of last LED event */ 230 u_int8_t sc_rxrate; /* current rx rate for LED */ 231 u_int8_t sc_txrate; /* current tx rate for LED */ 232 u_int16_t sc_ledoff; /* off time for current blink */ 233 struct callout sc_ledtimer; /* led off timer */ 234 235 caddr_t sc_drvbpf; 236 union { 237 struct ath_tx_radiotap_header th; 238 u_int8_t pad[64]; 239 } u_tx_rt; 240 int sc_tx_th_len; 241 union { 242 struct ath_rx_radiotap_header th; 243 u_int8_t pad[64]; 244 } u_rx_rt; 245 int sc_rx_th_len; 246 247 ath_task_t sc_fataltask; /* fatal int processing */ 248 249 struct ath_descdma sc_rxdma; /* RX descriptos */ 250 ath_bufhead sc_rxbuf; /* receive buffer */ 251 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 252 ath_task_t sc_rxtask; /* rx int processing */ 253 ath_task_t sc_rxorntask; /* rxorn int processing */ 254 u_int8_t sc_defant; /* current default antenna */ 255 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 256 257 struct ath_descdma sc_txdma; /* TX descriptors */ 258 ath_bufhead sc_txbuf; /* transmit buffer */ 259 ath_txbuf_lock_t sc_txbuflock; /* txbuf lock */ 260 int sc_tx_timer; /* transmit timeout */ 261 u_int sc_txqsetup; /* h/w queues setup */ 262 u_int sc_txintrperiod;/* tx interrupt batching */ 263 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 264 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 265 ath_task_t sc_txtask; /* tx int processing */ 266 267 struct ath_descdma sc_bdma; /* beacon descriptors */ 268 ath_bufhead sc_bbuf; /* beacon buffers */ 269 u_int sc_bhalq; /* HAL q for outgoing beacons */ 270 u_int sc_bmisscount; /* missed beacon transmits */ 271 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 272 struct ath_txq *sc_cabq; /* tx q for cab frames */ 273 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 274 ath_task_t sc_bmisstask; /* bmiss int processing */ 275 ath_task_t sc_bstucktask; /* stuck beacon processing */ 276 enum { 277 OK, /* no change needed */ 278 UPDATE, /* update pending */ 279 COMMIT /* beacon sent, commit change */ 280 } sc_updateslot; /* slot time update fsm */ 281 282 struct callout sc_cal_ch; /* callout handle for cals */ 283 struct callout sc_scan_ch; /* callout handle for scan */ 284 void *sc_sdhook; /* shutdown hook */ 285 void *sc_powerhook; /* power management hook */ 286 u_int sc_flags; /* misc flags */ 287 }; 288 #define sc_if sc_ec.ec_if 289 #define sc_tx_th u_tx_rt.th 290 #define sc_rx_th u_rx_rt.th 291 292 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 293 #define ATH_ENABLED 0x0002 /* chip is enabled */ 294 295 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 296 297 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 298 299 int ath_attach(u_int16_t, struct ath_softc *); 300 int ath_detach(struct ath_softc *); 301 void ath_resume(struct ath_softc *, int); 302 void ath_suspend(struct ath_softc *, int); 303 int ath_activate(struct device *, enum devact); 304 void ath_power(int, void *); 305 void ath_shutdown(void *); 306 int ath_intr(void *); 307 int ath_reset(struct ifnet *); 308 void ath_sysctlattach(struct ath_softc *); 309 310 extern int ath_dwelltime; 311 extern int ath_calinterval; 312 extern int ath_outdoor; 313 extern int ath_xchanmode; 314 extern int ath_countrycode; 315 extern int ath_regdomain; 316 extern int ath_debug; 317 318 /* 319 * HAL definitions to comply with local coding convention. 320 */ 321 #define ath_hal_detach(_ah) \ 322 ((*(_ah)->ah_detach)((_ah))) 323 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 324 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 325 #define ath_hal_getratetable(_ah, _mode) \ 326 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 327 #define ath_hal_getmac(_ah, _mac) \ 328 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 329 #define ath_hal_setmac(_ah, _mac) \ 330 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 331 #define ath_hal_intrset(_ah, _mask) \ 332 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 333 #define ath_hal_intrget(_ah) \ 334 ((*(_ah)->ah_getInterrupts)((_ah))) 335 #define ath_hal_intrpend(_ah) \ 336 ((*(_ah)->ah_isInterruptPending)((_ah))) 337 #define ath_hal_getisr(_ah, _pmask) \ 338 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 339 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 340 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 341 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 342 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 343 #define ath_hal_keycachesize(_ah) \ 344 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 345 #define ath_hal_keyreset(_ah, _ix) \ 346 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 347 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 348 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 349 #define ath_hal_keyisvalid(_ah, _ix) \ 350 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 351 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 352 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 353 #define ath_hal_getrxfilter(_ah) \ 354 ((*(_ah)->ah_getRxFilter)((_ah))) 355 #define ath_hal_setrxfilter(_ah, _filter) \ 356 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 357 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 358 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 359 #define ath_hal_waitforbeacon(_ah, _bf) \ 360 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 361 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 362 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 363 #define ath_hal_gettsf32(_ah) \ 364 ((*(_ah)->ah_getTsf32)((_ah))) 365 #define ath_hal_gettsf64(_ah) \ 366 ((*(_ah)->ah_getTsf64)((_ah))) 367 #define ath_hal_resettsf(_ah) \ 368 ((*(_ah)->ah_resetTsf)((_ah))) 369 #define ath_hal_rxena(_ah) \ 370 ((*(_ah)->ah_enableReceive)((_ah))) 371 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 372 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 373 #define ath_hal_gettxbuf(_ah, _q) \ 374 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 375 #define ath_hal_numtxpending(_ah, _q) \ 376 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 377 #define ath_hal_getrxbuf(_ah) \ 378 ((*(_ah)->ah_getRxDP)((_ah))) 379 #define ath_hal_txstart(_ah, _q) \ 380 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 381 #define ath_hal_setchannel(_ah, _chan) \ 382 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 383 #define ath_hal_calibrate(_ah, _chan) \ 384 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 385 #define ath_hal_setledstate(_ah, _state) \ 386 ((*(_ah)->ah_setLedState)((_ah), (_state))) 387 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 388 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 389 #define ath_hal_beaconreset(_ah) \ 390 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 391 #define ath_hal_beacontimers(_ah, _bs) \ 392 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 393 #define ath_hal_setassocid(_ah, _bss, _associd) \ 394 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 395 #define ath_hal_phydisable(_ah) \ 396 ((*(_ah)->ah_phyDisable)((_ah))) 397 #define ath_hal_setopmode(_ah) \ 398 ((*(_ah)->ah_setPCUConfig)((_ah))) 399 #define ath_hal_stoptxdma(_ah, _qnum) \ 400 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 401 #define ath_hal_stoppcurecv(_ah) \ 402 ((*(_ah)->ah_stopPcuReceive)((_ah))) 403 #define ath_hal_startpcurecv(_ah) \ 404 ((*(_ah)->ah_startPcuReceive)((_ah))) 405 #define ath_hal_stopdmarecv(_ah) \ 406 ((*(_ah)->ah_stopDmaReceive)((_ah))) 407 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 408 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 409 (_indata), (_insize), (_outdata), (_outsize))) 410 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 411 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 412 #define ath_hal_resettxqueue(_ah, _q) \ 413 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 414 #define ath_hal_releasetxqueue(_ah, _q) \ 415 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 416 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 417 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 418 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 419 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 420 #define ath_hal_getrfgain(_ah) \ 421 ((*(_ah)->ah_getRfGain)((_ah))) 422 #define ath_hal_getdefantenna(_ah) \ 423 ((*(_ah)->ah_getDefAntenna)((_ah))) 424 #define ath_hal_setdefantenna(_ah, _ant) \ 425 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 426 #define ath_hal_rxmonitor(_ah, _arg) \ 427 ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 428 #define ath_hal_mibevent(_ah, _stats) \ 429 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 430 #define ath_hal_setslottime(_ah, _us) \ 431 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 432 #define ath_hal_getslottime(_ah) \ 433 ((*(_ah)->ah_getSlotTime)((_ah))) 434 #define ath_hal_setacktimeout(_ah, _us) \ 435 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 436 #define ath_hal_getacktimeout(_ah) \ 437 ((*(_ah)->ah_getAckTimeout)((_ah))) 438 #define ath_hal_setctstimeout(_ah, _us) \ 439 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 440 #define ath_hal_getctstimeout(_ah) \ 441 ((*(_ah)->ah_getCTSTimeout)((_ah))) 442 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 443 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 444 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 445 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 446 #define ath_hal_ciphersupported(_ah, _cipher) \ 447 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 448 #define ath_hal_getregdomain(_ah, _prd) \ 449 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 450 #define ath_hal_getcountrycode(_ah, _pcc) \ 451 (*(_pcc) = (_ah)->ah_countryCode) 452 #define ath_hal_tkipsplit(_ah) \ 453 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 454 #define ath_hal_hwphycounters(_ah) \ 455 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 456 #define ath_hal_hasdiversity(_ah) \ 457 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 458 #define ath_hal_getdiversity(_ah) \ 459 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 460 #define ath_hal_setdiversity(_ah, _v) \ 461 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 462 #define ath_hal_getdiag(_ah, _pv) \ 463 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 464 #define ath_hal_setdiag(_ah, _v) \ 465 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 466 #define ath_hal_getnumtxqueues(_ah, _pv) \ 467 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 468 #define ath_hal_hasveol(_ah) \ 469 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 470 #define ath_hal_hastxpowlimit(_ah) \ 471 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 472 #define ath_hal_settxpowlimit(_ah, _pow) \ 473 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 474 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 475 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 476 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 477 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 478 #define ath_hal_gettpscale(_ah, _scale) \ 479 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 480 #define ath_hal_settpscale(_ah, _v) \ 481 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 482 #define ath_hal_hastpc(_ah) \ 483 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 484 #define ath_hal_gettpc(_ah) \ 485 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 486 #define ath_hal_settpc(_ah, _v) \ 487 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 488 #define ath_hal_hasbursting(_ah) \ 489 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 490 #ifdef notyet 491 #define ath_hal_hasmcastkeysearch(_ah) \ 492 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 493 #define ath_hal_getmcastkeysearch(_ah) \ 494 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 495 #else 496 #define ath_hal_getmcastkeysearch(_ah) 0 497 #endif 498 499 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 500 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 501 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 502 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 503 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 504 _txr0, _txtr0, _keyix, _ant, _flags, \ 505 _rtsrate, _rtsdura) \ 506 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 507 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 508 (_flags), (_rtsrate), (_rtsdura))) 509 #define ath_hal_setupxtxdesc(_ah, _ds, \ 510 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 511 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 512 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 513 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 514 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 515 #define ath_hal_txprocdesc(_ah, _ds) \ 516 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 517 #define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \ 518 _gatingds, _txOpLimit, _ctsDuration) \ 519 ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \ 520 (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration))) 521 522 #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 523 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 524 #define ath_hal_gpioset(_ah, _gpio, _b) \ 525 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 526 527 #endif /* _DEV_ATH_ATHVAR_H */ 528
Indexes created Wed Sep 24 15:09:51 GMT 2025