athvar.h revision 1.3
1 /* $NetBSD: athvar.h,v 1.3 2003/10/14 17:47:03 ichiro Exp $ */ 2 /*- 3 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 3. Neither the names of the above-listed copyright holders nor the names 17 * of any contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 28 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGES. 36 * 37 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.6 2003/09/05 22:22:49 sam Exp $ 38 */ 39 40 /* 41 * Defintions for the Atheros Wireless LAN controller driver. 42 */ 43 #ifndef _DEV_ATH_ATHVAR_H 44 #define _DEV_ATH_ATHVAR_H 45 46 #ifdef __FreeBSD__ 47 #include <sys/taskqueue.h> 48 49 #include <contrib/dev/ic/ah.h> 50 #else 51 #include <../contrib/sys/dev/ic/athhal.h> 52 #endif 53 #include <net80211/ieee80211_radiotap.h> 54 #ifdef __FreeBSD__ 55 #include <dev/ath/if_athioctl.h> 56 #else 57 #include <dev/ic/athioctl.h> 58 #endif 59 60 #define ATH_TIMEOUT 1000 61 62 #define ATH_RXBUF 40 /* number of RX buffers */ 63 #define ATH_TXBUF 60 /* number of TX buffers */ 64 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 65 66 /* driver-specific node */ 67 struct ath_node { 68 struct ieee80211_node an_node; /* base class */ 69 u_int an_tx_ok; /* tx ok pkt */ 70 u_int an_tx_err; /* tx !ok pkt */ 71 u_int an_tx_retr; /* tx retry count */ 72 int an_tx_upper; /* tx upper rate req cnt */ 73 u_int an_tx_antenna; /* antenna for last good frame */ 74 u_int an_rx_antenna; /* antenna for last rcvd frame */ 75 }; 76 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 77 78 struct ath_buf { 79 TAILQ_ENTRY(ath_buf) bf_list; 80 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 81 #ifdef __FreeBSD__ 82 int bf_nseg; 83 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 84 bus_size_t bf_mapsize; 85 #else 86 #define bf_nseg bf_dmamap->dm_nsegs 87 #define bf_mapsize bf_dmamap->dm_mapsize 88 #define bf_segs bf_dmamap->dm_segs 89 #endif 90 struct ath_desc *bf_desc; /* virtual addr of desc */ 91 bus_addr_t bf_daddr; /* physical addr of desc */ 92 struct mbuf *bf_m; /* mbuf for buf */ 93 struct ieee80211_node *bf_node; /* pointer to the node */ 94 #define ATH_MAX_SCATTER 64 95 }; 96 97 struct ath_softc { 98 #ifdef __NetBSD__ 99 struct device sc_dev; 100 #endif 101 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 102 #ifndef __FreeBSD__ 103 int (*sc_enable)(struct ath_softc *); 104 void (*sc_disable)(struct ath_softc *); 105 void (*sc_power)(struct ath_softc *, int); 106 #endif 107 int (*sc_newstate)(struct ieee80211com *, 108 enum ieee80211_state, int); 109 #ifdef __FreeBSD__ 110 device_t sc_dev; 111 #endif 112 bus_space_tag_t sc_st; /* bus space tag */ 113 bus_space_handle_t sc_sh; /* bus space handle */ 114 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 115 #ifdef __FreeBSD__ 116 struct mtx sc_mtx; /* master lock (recursive) */ 117 #endif 118 struct ath_hal *sc_ah; /* Atheros HAL */ 119 unsigned int sc_invalid : 1,/* disable hardware accesses */ 120 sc_have11g : 1,/* have 11g support */ 121 sc_doani : 1,/* dynamic noise immunity */ 122 sc_probing : 1;/* probing AP on beacon miss */ 123 /* rate tables */ 124 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 125 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 126 enum ieee80211_phymode sc_curmode; /* current phy mode */ 127 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 128 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 129 HAL_INT sc_imask; /* interrupt mask copy */ 130 131 #ifdef __FreeBSD__ 132 struct bpf_if *sc_drvbpf; 133 #else 134 caddr_t sc_drvbpf; 135 #endif 136 union { 137 struct ath_tx_radiotap_header th; 138 u_int8_t pad[64]; 139 } u_tx_rt; 140 union { 141 struct ath_rx_radiotap_header th; 142 u_int8_t pad[64]; 143 } u_rx_rt; 144 145 struct ath_desc *sc_desc; /* TX/RX descriptors */ 146 bus_dma_segment_t sc_dseg; 147 #ifdef __NetBSD__ 148 int sc_dnseg; /* number of segments */ 149 #endif 150 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 151 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 152 bus_addr_t sc_desc_len; /* size of sc_desc */ 153 154 ath_task_t sc_fataltask; /* fatal int processing */ 155 ath_task_t sc_rxorntask; /* rxorn int processing */ 156 157 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 158 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 159 ath_task_t sc_rxtask; /* rx int processing */ 160 161 u_int sc_txhalq; /* HAL q for outgoing frames */ 162 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 163 int sc_tx_timer; /* transmit timeout */ 164 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 165 #ifdef __FreeBSD__ 166 struct mtx sc_txbuflock; /* txbuf lock */ 167 #endif 168 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 169 #ifdef __FreeBSD__ 170 struct mtx sc_txqlock; /* lock on txq and txlink */ 171 #endif 172 ath_task_t sc_txtask; /* tx int processing */ 173 174 u_int sc_bhalq; /* HAL q for outgoing beacons */ 175 struct ath_buf *sc_bcbuf; /* beacon buffer */ 176 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 177 ath_task_t sc_swbatask; /* swba int processing */ 178 ath_task_t sc_bmisstask; /* bmiss int processing */ 179 180 struct callout sc_cal_ch; /* callout handle for cals */ 181 struct callout sc_scan_ch; /* callout handle for scan */ 182 struct ath_stats sc_stats; /* interface statistics */ 183 184 #ifndef __FreeBSD__ 185 void *sc_sdhook; /* shutdown hook */ 186 void *sc_powerhook; /* power management hook */ 187 u_int sc_flags; /* misc flags */ 188 #endif 189 }; 190 #ifndef __FreeBSD__ 191 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 192 #define ATH_ENABLED 0x0002 /* chip is enabled */ 193 194 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 195 #endif 196 197 #define sc_tx_th u_tx_rt.th 198 #define sc_rx_th u_rx_rt.th 199 200 int ath_attach(u_int16_t, struct ath_softc *); 201 int ath_detach(struct ath_softc *); 202 void ath_resume(struct ath_softc *, int); 203 void ath_suspend(struct ath_softc *, int); 204 void ath_shutdown(struct ath_softc *); 205 #ifndef __FreeBSD__ 206 int ath_activate(struct device *, enum devact); 207 void ath_power(int, void *); 208 #endif 209 #ifdef __FreeBSD__ 210 void ath_intr(void *); 211 #else 212 int ath_intr(void *); 213 #endif 214 215 /* 216 * HAL definitions to comply with local coding convention. 217 */ 218 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 219 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 220 #define ath_hal_getratetable(_ah, _mode) \ 221 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 222 #define ath_hal_getregdomain(_ah) \ 223 ((*(_ah)->ah_getRegDomain)((_ah))) 224 #define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 225 #define ath_hal_getmac(_ah, _mac) \ 226 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 227 #define ath_hal_detach(_ah) \ 228 ((*(_ah)->ah_detach)((_ah))) 229 #define ath_hal_intrset(_ah, _mask) \ 230 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 231 #define ath_hal_intrget(_ah) \ 232 ((*(_ah)->ah_getInterrupts)((_ah))) 233 #define ath_hal_intrpend(_ah) \ 234 ((*(_ah)->ah_isInterruptPending)((_ah))) 235 #define ath_hal_getisr(_ah, _pmask) \ 236 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 237 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 238 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 239 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 240 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 241 #define ath_hal_keyreset(_ah, _ix) \ 242 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 243 #define ath_hal_keyset(_ah, _ix, _pk) \ 244 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 245 #define ath_hal_keyisvalid(_ah, _ix) \ 246 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 247 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 248 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 249 #define ath_hal_getrxfilter(_ah) \ 250 ((*(_ah)->ah_getRxFilter)((_ah))) 251 #define ath_hal_setrxfilter(_ah, _filter) \ 252 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 253 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 254 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 255 #define ath_hal_waitforbeacon(_ah, _bf) \ 256 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 257 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 258 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 259 #define ath_hal_gettsf32(_ah) \ 260 ((*(_ah)->ah_getTsf32)((_ah))) 261 #define ath_hal_gettsf64(_ah) \ 262 ((*(_ah)->ah_getTsf64)((_ah))) 263 #define ath_hal_resettsf(_ah) \ 264 ((*(_ah)->ah_resetTsf)((_ah))) 265 #define ath_hal_rxena(_ah) \ 266 ((*(_ah)->ah_enableReceive)((_ah))) 267 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 268 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 269 #define ath_hal_gettxbuf(_ah, _q) \ 270 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 271 #define ath_hal_getrxbuf(_ah) \ 272 ((*(_ah)->ah_getRxDP)((_ah))) 273 #define ath_hal_txstart(_ah, _q) \ 274 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 275 #define ath_hal_setchannel(_ah, _chan) \ 276 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 277 #define ath_hal_calibrate(_ah, _chan) \ 278 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 279 #define ath_hal_setledstate(_ah, _state) \ 280 ((*(_ah)->ah_setLedState)((_ah), (_state))) 281 #define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 282 ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 283 #define ath_hal_beaconreset(_ah) \ 284 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 285 #define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 286 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 287 (_dc), (_cc))) 288 #define ath_hal_setassocid(_ah, _bss, _associd) \ 289 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 290 #define ath_hal_setopmode(_ah, _opmode) \ 291 ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 292 #define ath_hal_stoptxdma(_ah, _qnum) \ 293 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 294 #define ath_hal_stoppcurecv(_ah) \ 295 ((*(_ah)->ah_stopPcuReceive)((_ah))) 296 #define ath_hal_startpcurecv(_ah) \ 297 ((*(_ah)->ah_startPcuReceive)((_ah))) 298 #define ath_hal_stopdmarecv(_ah) \ 299 ((*(_ah)->ah_stopDmaReceive)((_ah))) 300 #define ath_hal_dumpstate(_ah) \ 301 ((*(_ah)->ah_dumpState)((_ah))) 302 #define ath_hal_dumpeeprom(_ah) \ 303 ((*(_ah)->ah_dumpEeprom)((_ah))) 304 #define ath_hal_dumprfgain(_ah) \ 305 ((*(_ah)->ah_dumpRfGain)((_ah))) 306 #define ath_hal_dumpani(_ah) \ 307 ((*(_ah)->ah_dumpAni)((_ah))) 308 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 309 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 310 #define ath_hal_resettxqueue(_ah, _q) \ 311 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 312 #define ath_hal_releasetxqueue(_ah, _q) \ 313 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 314 #define ath_hal_hasveol(_ah) \ 315 ((*(_ah)->ah_hasVEOL)((_ah))) 316 #define ath_hal_getrfgain(_ah) \ 317 ((*(_ah)->ah_getRfGain)((_ah))) 318 #define ath_hal_rxmonitor(_ah) \ 319 ((*(_ah)->ah_rxMonitor)((_ah))) 320 321 #define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 322 _rate, _antmode) \ 323 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 324 (_flen), (_hlen), (_rate), (_antmode))) 325 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 326 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 327 #define ath_hal_rxprocdesc(_ah, _ds) \ 328 ((*(_ah)->ah_procRxDesc)((_ah), (_ds))) 329 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 330 _txr0, _txtr0, _keyix, _ant, _flags, \ 331 _rtsrate, _rtsdura) \ 332 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 333 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 334 (_flags), (_rtsrate), (_rtsdura))) 335 #define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 336 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 337 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 338 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 339 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 340 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 341 #define ath_hal_txprocdesc(_ah, _ds) \ 342 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 343 344 #endif /* _DEV_ATH_ATHVAR_H */ 345
Indexes created Fri Sep 26 20:09:58 GMT 2025