athvar.h revision 1.7
1 /* $NetBSD: athvar.h,v 1.7 2004/02/29 00:47:21 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 * 38 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.10 2003/11/29 01:23:59 sam Exp $ 39 */ 40 41 /* 42 * Defintions for the Atheros Wireless LAN controller driver. 43 */ 44 #ifndef _DEV_ATH_ATHVAR_H 45 #define _DEV_ATH_ATHVAR_H 46 47 #ifdef __FreeBSD__ 48 #include <sys/taskqueue.h> 49 50 #include <contrib/dev/ic/ah.h> 51 #else 52 #include <../contrib/sys/dev/ic/athhal.h> 53 #endif 54 #include <net80211/ieee80211_radiotap.h> 55 #ifdef __FreeBSD__ 56 #include <dev/ath/if_athioctl.h> 57 #else 58 #include <dev/ic/athioctl.h> 59 #endif 60 61 #define ATH_TIMEOUT 1000 62 63 #define ATH_RXBUF 40 /* number of RX buffers */ 64 #define ATH_TXBUF 60 /* number of TX buffers */ 65 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 66 67 struct ath_recv_hist { 68 int arh_ticks; /* sample time by system clock */ 69 u_int8_t arh_rssi; /* rssi */ 70 u_int8_t arh_antenna; /* antenna */ 71 }; 72 #define ATH_RHIST_SIZE 16 /* number of samples */ 73 #define ATH_RHIST_NOTIME (~0) 74 75 /* driver-specific node */ 76 struct ath_node { 77 struct ieee80211_node an_node; /* base class */ 78 u_int an_tx_ok; /* tx ok pkt */ 79 u_int an_tx_err; /* tx !ok pkt */ 80 u_int an_tx_retr; /* tx retry count */ 81 int an_tx_upper; /* tx upper rate req cnt */ 82 u_int an_tx_antenna; /* antenna for last good frame */ 83 u_int an_rx_antenna; /* antenna for last rcvd frame */ 84 struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 85 u_int an_rx_hist_next;/* index of next ``free entry'' */ 86 }; 87 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 88 89 struct ath_buf { 90 TAILQ_ENTRY(ath_buf) bf_list; 91 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 92 #ifdef __FreeBSD__ 93 int bf_nseg; 94 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 95 bus_size_t bf_mapsize; 96 #else 97 #define bf_nseg bf_dmamap->dm_nsegs 98 #define bf_mapsize bf_dmamap->dm_mapsize 99 #define bf_segs bf_dmamap->dm_segs 100 #endif 101 struct ath_desc *bf_desc; /* virtual addr of desc */ 102 bus_addr_t bf_daddr; /* physical addr of desc */ 103 struct mbuf *bf_m; /* mbuf for buf */ 104 struct ieee80211_node *bf_node; /* pointer to the node */ 105 #define ATH_MAX_SCATTER 64 106 }; 107 108 struct ath_softc { 109 #ifdef __NetBSD__ 110 struct device sc_dev; 111 #endif 112 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 113 #ifndef __FreeBSD__ 114 int (*sc_enable)(struct ath_softc *); 115 void (*sc_disable)(struct ath_softc *); 116 void (*sc_power)(struct ath_softc *, int); 117 #endif 118 int (*sc_newstate)(struct ieee80211com *, 119 enum ieee80211_state, int); 120 #ifdef __FreeBSD__ 121 device_t sc_dev; 122 #endif 123 bus_space_tag_t sc_st; /* bus space tag */ 124 bus_space_handle_t sc_sh; /* bus space handle */ 125 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 126 #ifdef __FreeBSD__ 127 struct mtx sc_mtx; /* master lock (recursive) */ 128 #endif 129 struct ath_hal *sc_ah; /* Atheros HAL */ 130 unsigned int sc_invalid : 1,/* disable hardware accesses */ 131 sc_doani : 1,/* dynamic noise immunity */ 132 sc_probing : 1;/* probing AP on beacon miss */ 133 /* rate tables */ 134 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 135 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 136 enum ieee80211_phymode sc_curmode; /* current phy mode */ 137 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 138 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 139 HAL_INT sc_imask; /* interrupt mask copy */ 140 141 #ifdef __FreeBSD__ 142 struct bpf_if *sc_drvbpf; 143 #else 144 caddr_t sc_drvbpf; 145 #endif 146 union { 147 struct ath_tx_radiotap_header th; 148 u_int8_t pad[64]; 149 } u_tx_rt; 150 union { 151 struct ath_rx_radiotap_header th; 152 u_int8_t pad[64]; 153 } u_rx_rt; 154 155 struct ath_desc *sc_desc; /* TX/RX descriptors */ 156 bus_dma_segment_t sc_dseg; 157 #ifdef __NetBSD__ 158 int sc_dnseg; /* number of segments */ 159 #endif 160 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 161 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 162 bus_addr_t sc_desc_len; /* size of sc_desc */ 163 164 ath_task_t sc_fataltask; /* fatal int processing */ 165 ath_task_t sc_rxorntask; /* rxorn int processing */ 166 167 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 168 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 169 ath_task_t sc_rxtask; /* rx int processing */ 170 171 u_int sc_txhalq; /* HAL q for outgoing frames */ 172 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 173 int sc_tx_timer; /* transmit timeout */ 174 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 175 #ifdef __FreeBSD__ 176 struct mtx sc_txbuflock; /* txbuf lock */ 177 #endif 178 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 179 #ifdef __FreeBSD__ 180 struct mtx sc_txqlock; /* lock on txq and txlink */ 181 #endif 182 ath_task_t sc_txtask; /* tx int processing */ 183 184 u_int sc_bhalq; /* HAL q for outgoing beacons */ 185 struct ath_buf *sc_bcbuf; /* beacon buffer */ 186 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 187 ath_task_t sc_swbatask; /* swba int processing */ 188 ath_task_t sc_bmisstask; /* bmiss int processing */ 189 190 struct callout sc_cal_ch; /* callout handle for cals */ 191 struct callout sc_scan_ch; /* callout handle for scan */ 192 struct ath_stats sc_stats; /* interface statistics */ 193 194 #ifndef __FreeBSD__ 195 void *sc_sdhook; /* shutdown hook */ 196 void *sc_powerhook; /* power management hook */ 197 u_int sc_flags; /* misc flags */ 198 #endif 199 }; 200 #ifndef __FreeBSD__ 201 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 202 #define ATH_ENABLED 0x0002 /* chip is enabled */ 203 204 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 205 #endif 206 207 #define sc_tx_th u_tx_rt.th 208 #define sc_rx_th u_rx_rt.th 209 210 #define ATH_LOCK_INIT(_sc) \ 211 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 212 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 213 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 214 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 215 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 216 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 217 218 #define ATH_TXBUF_LOCK_INIT(_sc) \ 219 mtx_init(&(_sc)->sc_txbuflock, \ 220 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 221 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 222 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 223 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 224 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 225 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 226 227 #define ATH_TXQ_LOCK_INIT(_sc) \ 228 mtx_init(&(_sc)->sc_txqlock, \ 229 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 230 #define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 231 #define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 232 #define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 233 #define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 234 235 int ath_attach(u_int16_t, struct ath_softc *); 236 int ath_detach(struct ath_softc *); 237 void ath_resume(struct ath_softc *, int); 238 void ath_suspend(struct ath_softc *, int); 239 #ifdef __NetBSD__ 240 int ath_activate(struct device *, enum devact); 241 void ath_power(int, void *); 242 #endif 243 #ifdef __FreeBSD__ 244 void ath_shutdown(struct ath_softc *); 245 void ath_intr(void *); 246 #else 247 void ath_shutdown(void *); 248 int ath_intr(void *); 249 #endif 250 251 /* 252 * HAL definitions to comply with local coding convention. 253 */ 254 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 255 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 256 #define ath_hal_getratetable(_ah, _mode) \ 257 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 258 #define ath_hal_getregdomain(_ah) \ 259 ((*(_ah)->ah_getRegDomain)((_ah))) 260 #define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 261 #define ath_hal_getmac(_ah, _mac) \ 262 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 263 #define ath_hal_detach(_ah) \ 264 ((*(_ah)->ah_detach)((_ah))) 265 #define ath_hal_intrset(_ah, _mask) \ 266 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 267 #define ath_hal_intrget(_ah) \ 268 ((*(_ah)->ah_getInterrupts)((_ah))) 269 #define ath_hal_intrpend(_ah) \ 270 ((*(_ah)->ah_isInterruptPending)((_ah))) 271 #define ath_hal_getisr(_ah, _pmask) \ 272 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 273 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 274 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 275 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 276 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 277 #define ath_hal_keyreset(_ah, _ix) \ 278 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 279 #define ath_hal_keyset(_ah, _ix, _pk) \ 280 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 281 #define ath_hal_keyisvalid(_ah, _ix) \ 282 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 283 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 284 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 285 #define ath_hal_getrxfilter(_ah) \ 286 ((*(_ah)->ah_getRxFilter)((_ah))) 287 #define ath_hal_setrxfilter(_ah, _filter) \ 288 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 289 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 290 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 291 #define ath_hal_waitforbeacon(_ah, _bf) \ 292 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 293 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 294 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 295 #define ath_hal_gettsf32(_ah) \ 296 ((*(_ah)->ah_getTsf32)((_ah))) 297 #define ath_hal_gettsf64(_ah) \ 298 ((*(_ah)->ah_getTsf64)((_ah))) 299 #define ath_hal_resettsf(_ah) \ 300 ((*(_ah)->ah_resetTsf)((_ah))) 301 #define ath_hal_rxena(_ah) \ 302 ((*(_ah)->ah_enableReceive)((_ah))) 303 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 304 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 305 #define ath_hal_gettxbuf(_ah, _q) \ 306 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 307 #define ath_hal_getrxbuf(_ah) \ 308 ((*(_ah)->ah_getRxDP)((_ah))) 309 #define ath_hal_txstart(_ah, _q) \ 310 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 311 #define ath_hal_setchannel(_ah, _chan) \ 312 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 313 #define ath_hal_calibrate(_ah, _chan) \ 314 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 315 #define ath_hal_setledstate(_ah, _state) \ 316 ((*(_ah)->ah_setLedState)((_ah), (_state))) 317 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 318 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 319 #define ath_hal_beaconreset(_ah) \ 320 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 321 #define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 322 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 323 (_dc), (_cc))) 324 #define ath_hal_setassocid(_ah, _bss, _associd) \ 325 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 326 #define ath_hal_setopmode(_ah) \ 327 ((*(_ah)->ah_setPCUConfig)((_ah))) 328 #define ath_hal_stoptxdma(_ah, _qnum) \ 329 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 330 #define ath_hal_stoppcurecv(_ah) \ 331 ((*(_ah)->ah_stopPcuReceive)((_ah))) 332 #define ath_hal_startpcurecv(_ah) \ 333 ((*(_ah)->ah_startPcuReceive)((_ah))) 334 #define ath_hal_stopdmarecv(_ah) \ 335 ((*(_ah)->ah_stopDmaReceive)((_ah))) 336 #define ath_hal_dumpstate(_ah) \ 337 ((*(_ah)->ah_dumpState)((_ah))) 338 #define ath_hal_getdiagstate(_ah, _id, _data, _size) \ 339 ((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size))) 340 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 341 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 342 #define ath_hal_resettxqueue(_ah, _q) \ 343 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 344 #define ath_hal_releasetxqueue(_ah, _q) \ 345 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 346 #define ath_hal_hasveol(_ah) \ 347 ((*(_ah)->ah_hasVEOL)((_ah))) 348 #define ath_hal_getrfgain(_ah) \ 349 ((*(_ah)->ah_getRfGain)((_ah))) 350 #define ath_hal_rxmonitor(_ah) \ 351 ((*(_ah)->ah_rxMonitor)((_ah))) 352 353 #define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 354 _rate, _antmode) \ 355 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 356 (_flen), (_hlen), (_rate), (_antmode))) 357 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 358 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 359 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 360 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 361 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 362 _txr0, _txtr0, _keyix, _ant, _flags, \ 363 _rtsrate, _rtsdura) \ 364 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 365 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 366 (_flags), (_rtsrate), (_rtsdura))) 367 #define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 368 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 369 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 370 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 371 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 372 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 373 #define ath_hal_txprocdesc(_ah, _ds) \ 374 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 375 376 #endif /* _DEV_ATH_ATHVAR_H */ 377
Indexes created Wed Sep 24 05:09:52 GMT 2025