atppc.c revision 1.1
1 /* 2 * Copyright (c) 2001 Alcove - Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $ 27 * 28 */ 29 30 #include "opt_atppc.h" 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/proc.h> 38 #include <sys/systm.h> 39 #include <sys/vnode.h> 40 #include <sys/syslog.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/isa/isareg.h> 46 #include <dev/isa/isavar.h> 47 48 #include <dev/ic/atppcreg.h> 49 #include <dev/ic/atppcvar.h> 50 51 #include <dev/ppbus/ppbus_conf.h> 52 #include <dev/ppbus/ppbus_msq.h> 53 #include <dev/ppbus/ppbus_io.h> 54 #include <dev/ppbus/ppbus_var.h> 55 56 #ifdef ATPPC_DEBUG 57 int atppc_debug = 1; 58 #endif 59 60 #ifdef ATPPC_VERBOSE 61 int atppc_verbose = 1; 62 #endif 63 64 /* List of supported chipsets detection routines */ 65 static int (*chipset_detect[])(struct atppc_softc *) = { 66 /* XXX Add these LATER: maybe as seperate devices? 67 atppc_pc873xx_detect, 68 atppc_smc37c66xgt_detect, 69 atppc_w83877f_detect, 70 atppc_smc37c935_detect, 71 */ 72 NULL 73 }; 74 75 76 /* Prototypes for functions. */ 77 78 /* Soft configuration attach */ 79 void atppc_sc_attach(struct atppc_softc *); 80 int atppc_sc_detach(struct atppc_softc *, int); 81 82 /* Interrupt handler for atppc device */ 83 int atppcintr(void *); 84 85 /* Print function for config_found_sm() */ 86 static int atppc_print(void * aux, const char * name); 87 88 /* Detection routines */ 89 static int atppc_detect_fifo(struct atppc_softc *); 90 static int atppc_detect_chipset(struct atppc_softc *); 91 static int atppc_detect_generic(struct atppc_softc *); 92 93 /* Routines for ppbus interface (bus + device) */ 94 static int atppc_read(struct device *, char *, int, int, size_t *); 95 static int atppc_write(struct device *, char *, int, int, size_t *); 96 static int atppc_setmode(struct device *, int); 97 static int atppc_getmode(struct device *); 98 static int atppc_check_epp_timeout(struct device *); 99 static void atppc_reset_epp_timeout(struct device *); 100 static void atppc_ecp_sync(struct device *); 101 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 102 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 103 static int atppc_read_ivar(struct device *, int, unsigned int *); 104 static int atppc_write_ivar(struct device *, int, unsigned int *); 105 static int atppc_add_handler(struct device *, void (*)(void *), void *); 106 static int atppc_remove_handler(struct device *, void (*)(void *)); 107 108 /* Utility functions */ 109 110 /* Functions to read bytes into device's input buffer */ 111 static void atppc_nibble_read(struct atppc_softc * const); 112 static void atppc_byte_read(struct atppc_softc * const); 113 static void atppc_epp_read(struct atppc_softc * const); 114 static void atppc_ecp_read(struct atppc_softc * const); 115 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 116 unsigned char); 117 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 118 unsigned char); 119 static void atppc_ecp_read_error(struct atppc_softc *, const unsigned int); 120 121 122 /* Functions to write bytes to device's output buffer */ 123 static void atppc_std_write(struct atppc_softc * const); 124 static void atppc_epp_write(struct atppc_softc * const); 125 static void atppc_fifo_write(struct atppc_softc * const); 126 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 127 unsigned char); 128 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 129 unsigned char); 130 static void atppc_fifo_write_error(struct atppc_softc * const, 131 const unsigned int); 132 133 /* Miscellaneous */ 134 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 135 const u_int8_t); 136 static int atppc_wait_interrupt(struct atppc_softc * const, const caddr_t, 137 const u_int8_t); 138 139 140 /* 141 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 142 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 143 */ 144 145 /* Soft configuration attach for atppc */ 146 void 147 atppc_sc_attach(struct atppc_softc * lsc) 148 { 149 /* Adapter used to configure ppbus device */ 150 struct parport_adapter sc_parport_adapter; 151 struct device * dev = (struct device *) lsc; 152 #ifdef ATPPC_VERBOSE 153 char buf[64]; 154 #endif 155 156 printf("\n"); 157 158 /* Probe and set up chipset */ 159 if(atppc_detect_chipset(lsc) != 0) { 160 if(atppc_detect_generic(lsc) != 0) { 161 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 162 dev->dv_xname)); 163 } 164 } 165 166 /* Probe and setup FIFO queue */ 167 if(atppc_detect_fifo(lsc) == 0) { 168 ATPPC_VPRINTF(("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 169 dev->dv_xname, lsc->sc_fifo, lsc->sc_wthr, 170 lsc->sc_rthr)); 171 } 172 173 #ifdef ATPPC_VERBOSE 174 /* Print out chipset capabilities */ 175 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 176 buf, sizeof(buf)); 177 ATPPC_VPRINTF(("%s: capabilities=%s\n", dev->dv_xname, buf)); 178 #endif 179 180 /* Initialize device's buffer pointers */ 181 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 182 = NULL; 183 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 184 185 /* Last configuration step: set mode to standard mode */ 186 if(atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 187 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 188 dev->dv_xname)); 189 } 190 191 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 192 /* Initialize lock structure */ 193 simple_lock_init(&(lsc->sc_lock)); 194 #endif 195 196 /* Set up parport_adapter structure */ 197 198 /* Set capabilites */ 199 sc_parport_adapter.capabilities = 0; 200 if(lsc->sc_has & ATPPC_HAS_INTR) { 201 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 202 } 203 if(lsc->sc_has & ATPPC_HAS_DMA) { 204 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 205 } 206 if(lsc->sc_has & ATPPC_HAS_FIFO) { 207 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 208 } 209 if(lsc->sc_has & ATPPC_HAS_PS2) { 210 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 211 } 212 if(lsc->sc_has & ATPPC_HAS_EPP) { 213 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 214 } 215 if(lsc->sc_has & ATPPC_HAS_ECP) { 216 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 217 } 218 219 /* Set function pointers */ 220 sc_parport_adapter.parport_io = atppc_io; 221 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 222 sc_parport_adapter.parport_reset_epp_timeout = 223 atppc_reset_epp_timeout; 224 sc_parport_adapter.parport_setmode = atppc_setmode; 225 sc_parport_adapter.parport_getmode = atppc_getmode; 226 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 227 sc_parport_adapter.parport_read = atppc_read; 228 sc_parport_adapter.parport_write = atppc_write; 229 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 230 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 231 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 232 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 233 sc_parport_adapter.parport_add_handler = atppc_add_handler; 234 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 235 236 /* Initialize handler list, may be added to by grandchildren */ 237 SLIST_INIT(&(lsc->sc_handler_listhead)); 238 239 /* Initialize interrupt state */ 240 lsc->sc_irqstat = ATPPC_IRQ_NONE; 241 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 242 243 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 244 lsc->sc_use = 0; 245 246 /* Configure child of the device. */ 247 lsc->child = config_found_sm(&(lsc->sc_dev), &(sc_parport_adapter), 248 atppc_print, NULL); 249 250 return; 251 } 252 253 /* Soft configuration detach */ 254 int atppc_sc_detach(struct atppc_softc * lsc, int flag) 255 { 256 struct device * dev = (struct device *) lsc; 257 258 /* Detach children devices */ 259 if(config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 260 printf("%s not able to detach child device, ", dev->dv_xname); 261 262 if(!(flag & DETACH_FORCE)) { 263 printf("cannot detach", dev->dv_xname); 264 return 1; 265 } 266 else { 267 printf("continuing (DETACH_FORCE)\n", dev->dv_xname); 268 } 269 } 270 271 if(!(flag & DETACH_QUIET)) 272 printf("%s detached", dev->dv_xname); 273 274 return 0; 275 } 276 277 /* Used by config_found_sm() to print out device information */ 278 static int 279 atppc_print(void * aux, const char * name) 280 { 281 /* Print out something on failure. */ 282 if(name != NULL) { 283 printf("%s: child devices", name); 284 return UNCONF; 285 } 286 287 return QUIET; 288 } 289 290 /* 291 * Machine independent detection routines for atppc driver. 292 */ 293 294 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 295 int 296 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 297 { 298 /* 299 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() * in original lpt driver. 300 * Write to data register common to all controllers and read back the 301 * values. Also tests control and status registers. 302 */ 303 304 /* 305 * Cannot use convenient macros because the device's config structure 306 * may not have been created yet: major change from FreeBSD code. 307 */ 308 309 int rval; 310 u_int8_t ctr_sav, dtr_sav, str_sav; 311 312 /* Store writtable registers' values and test if they can be read */ 313 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 314 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 315 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 316 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 317 BUS_SPACE_BARRIER_READ); 318 319 /* 320 * Ensure PS2 ports in output mode, also read back value of control 321 * register. 322 */ 323 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 324 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 325 BUS_SPACE_BARRIER_WRITE); 326 327 if(bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 328 rval = 0; 329 } 330 else { 331 /* 332 * Test if two values can be written and read from the data 333 * register. 334 */ 335 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 336 BUS_SPACE_BARRIER_READ); 337 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 338 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 339 BUS_SPACE_BARRIER_WRITE); 340 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 341 rval = 1; 342 } 343 else { 344 /* Second value to test */ 345 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 346 BUS_SPACE_BARRIER_READ); 347 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 348 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 349 BUS_SPACE_BARRIER_WRITE); 350 if(bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 351 rval = 1; 352 } 353 else { 354 rval = 0; 355 } 356 } 357 358 } 359 360 /* Restore registers */ 361 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 362 BUS_SPACE_BARRIER_READ); 363 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 364 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 365 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 366 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 367 BUS_SPACE_BARRIER_WRITE); 368 369 return rval; 370 } 371 372 /* Detect parallel port chipset. */ 373 static int 374 atppc_detect_chipset(struct atppc_softc * atppc) 375 { 376 /* Try each detection routine. */ 377 int i, mode; 378 for (i = 0; chipset_detect[i] != NULL; i++) { 379 if ((mode = chipset_detect[i](atppc)) != -1) { 380 atppc->sc_mode = mode; 381 return 0; 382 } 383 } 384 385 return 1; 386 } 387 388 /* Detect generic capabilities. */ 389 static int 390 atppc_detect_generic(struct atppc_softc * atppc) 391 { 392 u_int8_t ecr_sav = atppc_r_ecr(atppc); 393 u_int8_t ctr_sav = atppc_r_ctr(atppc); 394 u_int8_t str_sav = atppc_r_str(atppc); 395 u_int8_t tmp; 396 atppc_barrier_r(atppc); 397 398 /* Default to generic */ 399 atppc->sc_type = ATPPC_TYPE_GENERIC; 400 atppc->sc_model = GENERIC; 401 402 /* Check for ECP */ 403 tmp = atppc_r_ecr(atppc); 404 atppc_barrier_r(atppc); 405 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 406 atppc_w_ecr(atppc, 0x34); 407 atppc_barrier_w(atppc); 408 tmp = atppc_r_ecr(atppc); 409 atppc_barrier_r(atppc); 410 if(tmp == 0x35) { 411 atppc->sc_has |= ATPPC_HAS_ECP; 412 } 413 } 414 415 /* Allow search for SMC style ECP+EPP mode */ 416 if(atppc->sc_has & ATPPC_HAS_ECP) { 417 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 418 atppc_barrier_w(atppc); 419 } 420 /* Check for EPP by checking for timeout bit */ 421 if(atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 422 atppc->sc_has |= ATPPC_HAS_EPP; 423 atppc->sc_epp = ATPPC_EPP_1_9; 424 if(atppc->sc_has & ATPPC_HAS_ECP) { 425 /* SMC like chipset found */ 426 atppc->sc_model = SMC_LIKE; 427 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 428 } 429 } 430 431 /* Detect PS2 mode */ 432 if(atppc->sc_has & ATPPC_HAS_ECP) { 433 /* Put ECP port into PS2 mode */ 434 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 435 atppc_barrier_w(atppc); 436 } 437 /* Put PS2 port in input mode: writes should not be readable */ 438 atppc_w_ctr(atppc, 0x20); 439 atppc_barrier_w(atppc); 440 /* 441 * Write two values to data port: if neither are read back, 442 * bidirectional mode is functional. 443 */ 444 atppc_w_dtr(atppc, 0xaa); 445 atppc_barrier_w(atppc); 446 tmp = atppc_r_dtr(atppc); 447 atppc_barrier_r(atppc); 448 if(tmp != 0xaa) { 449 atppc_w_dtr(atppc, 0x55); 450 atppc_barrier_w(atppc); 451 tmp = atppc_r_dtr(atppc); 452 atppc_barrier_r(atppc); 453 if(tmp != 0x55) { 454 atppc->sc_has |= ATPPC_HAS_PS2; 455 } 456 } 457 458 /* Restore to previous state */ 459 atppc_w_ecr(atppc, ecr_sav); 460 atppc_w_ctr(atppc, ctr_sav); 461 atppc_w_str(atppc, str_sav); 462 atppc_barrier_w(atppc); 463 464 return 0; 465 } 466 467 /* 468 * Detect parallel port FIFO: taken from FreeBSD code directly. 469 */ 470 static int 471 atppc_detect_fifo(struct atppc_softc * atppc) 472 { 473 #ifdef ATPPC_DEBUG 474 struct device * dev = (struct device *)atppc; 475 #endif 476 u_int8_t ecr_sav; 477 u_int8_t ctr_sav; 478 u_int8_t str_sav; 479 u_int8_t cc; 480 short i; 481 482 /* If there is no ECP mode, we cannot config a FIFO */ 483 if(!(atppc->sc_has & ATPPC_HAS_ECP)) { 484 return (EINVAL); 485 } 486 487 /* save registers */ 488 ecr_sav = atppc_r_ecr(atppc); 489 ctr_sav = atppc_r_ctr(atppc); 490 str_sav = atppc_r_str(atppc); 491 atppc_barrier_r(atppc); 492 493 /* Enter ECP configuration mode, no interrupt, no DMA */ 494 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 495 ~ATPPC_ENABLE_DMA); 496 atppc_barrier_w(atppc); 497 498 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 499 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 500 atppc_barrier_r(atppc); 501 502 /* XXX 16 and 32 bits implementations not supported */ 503 if(atppc->sc_pword != ATPPC_PWORD_8) { 504 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 505 __func__, dev->dv_xname, atppc->sc_pword)); 506 goto error; 507 } 508 509 /* Byte mode, reverse direction, no interrupt, no DMA */ 510 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 511 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 512 /* enter ECP test mode, no interrupt, no DMA */ 513 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 514 atppc_barrier_w(atppc); 515 516 /* flush the FIFO */ 517 for (i = 0; i < 1024; i++) { 518 atppc_r_fifo(atppc); 519 atppc_barrier_r(atppc); 520 cc = atppc_r_ecr(atppc); 521 atppc_barrier_r(atppc); 522 if(cc & ATPPC_FIFO_EMPTY) 523 break; 524 } 525 if (i >= 1024) { 526 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 527 dev->dv_xname)); 528 goto error; 529 } 530 531 /* Test mode, enable interrupts, no DMA */ 532 atppc_w_ecr(atppc, ATPPC_ECR_TST); 533 atppc_barrier_w(atppc); 534 535 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 536 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 537 atppc_w_fifo(atppc, (char)i); 538 atppc_barrier_w(atppc); 539 cc = atppc_r_ecr(atppc); 540 atppc_barrier_r(atppc); 541 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 542 /* readThreshold reached */ 543 atppc->sc_rthr = i + 1; 544 } 545 if (cc & ATPPC_FIFO_FULL) { 546 atppc->sc_fifo = i + 1; 547 break; 548 } 549 } 550 if (i >= 1024) { 551 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 552 dev->dv_xname)); 553 goto error; 554 } 555 556 /* Change direction */ 557 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 558 atppc_barrier_w(atppc); 559 560 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 561 for(atppc->sc_wthr = 0; i > -1; i--) { 562 cc = atppc_r_fifo(atppc); 563 atppc_barrier_r(atppc); 564 if(cc != (char)(atppc->sc_fifo - i - 1)) { 565 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 566 __func__, dev->dv_xname)); 567 goto error; 568 } 569 570 cc = atppc_r_ecr(atppc); 571 atppc_barrier_r(atppc); 572 if((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 573 /* writeIntrThreshold reached */ 574 atppc->sc_wthr = atppc->sc_fifo - i; 575 } 576 577 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 578 /* If FIFO empty before the last byte, error */ 579 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 580 dev->dv_xname)); 581 goto error; 582 } 583 } 584 585 /* FIFO must be empty after the last byte */ 586 cc = atppc_r_ecr(atppc); 587 atppc_barrier_r(atppc); 588 if (!(cc & ATPPC_FIFO_EMPTY)) { 589 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 590 dev->dv_xname)); 591 goto error; 592 } 593 594 /* Restore original registers */ 595 atppc_w_ctr(atppc, ctr_sav); 596 atppc_w_str(atppc, str_sav); 597 atppc_w_ecr(atppc, ecr_sav); 598 atppc_barrier_w(atppc); 599 600 /* Update capabilities */ 601 atppc->sc_has |= ATPPC_HAS_FIFO; 602 603 return 0; 604 605 error: 606 /* Restore original registers */ 607 atppc_w_ctr(atppc, ctr_sav); 608 atppc_w_str(atppc, str_sav); 609 atppc_w_ecr(atppc, ecr_sav); 610 atppc_barrier_w(atppc); 611 612 return (EINVAL); 613 } 614 615 /* Interrupt handler for atppc device: wakes up read/write functions */ 616 int 617 atppcintr(void * arg) 618 { 619 struct atppc_softc * atppc = (struct atppc_softc *) arg; 620 struct device * dev = (struct device *) arg; 621 int error = 1; 622 enum { NONE, READER, WRITER } wake_up = NONE; 623 int s; 624 625 s = splatppc(); 626 ATPPC_LOCK(atppc); 627 628 /* Record registers' status */ 629 atppc->sc_str_intr = atppc_r_str(atppc); 630 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 631 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 632 atppc_barrier_r(atppc); 633 634 /* Determine cause of interrupt and wake up top half */ 635 switch(atppc->sc_mode) { 636 case ATPPC_MODE_STD: 637 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 638 atppc->sc_irqstat = ATPPC_IRQ_nACK; 639 if(atppc->sc_outb) 640 wake_up = WRITER; 641 else 642 error = -1; 643 break; 644 645 case ATPPC_MODE_NIBBLE: 646 case ATPPC_MODE_PS2: 647 /* nAck is set low by device and then high on ack */ 648 if(!(atppc->sc_str_intr & nACK)) { 649 error = 0; 650 break; 651 } 652 atppc->sc_irqstat = ATPPC_IRQ_nACK; 653 if(atppc->sc_inb) 654 wake_up = READER; 655 else 656 error = -1; 657 break; 658 659 case ATPPC_MODE_ECP: 660 case ATPPC_MODE_FAST: 661 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 662 if(atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 663 if(atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 664 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 665 else 666 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 667 668 /* Decide where top half will be waiting */ 669 if(atppc->sc_mode & ATPPC_MODE_ECP) { 670 if(atppc->sc_ctr_intr & PCD) { 671 if(atppc->sc_inb) 672 wake_up = READER; 673 else 674 error = -1; 675 } 676 else { 677 if(atppc->sc_outb) 678 wake_up = WRITER; 679 else 680 error = -1; 681 } 682 } 683 else { 684 if(atppc->sc_outb) 685 wake_up = WRITER; 686 else 687 error = -1; 688 } 689 } 690 /* Determine if nFault has occured */ 691 if((atppc->sc_mode & ATPPC_MODE_ECP) && 692 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 693 !(atppc->sc_str_intr & nFAULT)) { 694 695 /* Device is requesting the channel */ 696 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 697 } 698 break; 699 700 case ATPPC_MODE_EPP: 701 /* nAck pulsed for 5 usec, too fast to check reliably */ 702 atppc->sc_irqstat = ATPPC_IRQ_nACK; 703 if(atppc->sc_inb) 704 wake_up = WRITER; 705 else if(atppc->sc_outb) 706 wake_up = READER; 707 else 708 error = -1; 709 break; 710 711 default: 712 panic("%s: chipset is in invalid mode.", dev->dv_xname); 713 } 714 715 switch(wake_up) { 716 case NONE: 717 break; 718 719 case READER: 720 wakeup(atppc->sc_inb); 721 break; 722 723 case WRITER: 724 wakeup(atppc->sc_outb); 725 break; 726 727 default: 728 panic("%s: this code should not be reached.\n", __func__); 729 break; 730 } 731 732 ATPPC_UNLOCK(atppc); 733 734 /* Call all of the installed handlers */ 735 { 736 struct atppc_handler_node * callback; 737 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 738 entries) { 739 (*callback->func)(callback->arg); 740 } 741 } 742 743 splx(s); 744 745 return error; 746 } 747 748 749 /* Functions which support ppbus interface */ 750 751 752 /* Check EPP mode timeout */ 753 static int 754 atppc_check_epp_timeout(struct device * dev) 755 { 756 struct atppc_softc * atppc = (struct atppc_softc *) dev; 757 int s; 758 int error; 759 760 s = splatppc(); 761 ATPPC_LOCK(atppc); 762 763 atppc_reset_epp_timeout(dev); 764 error = !(atppc_r_str(atppc) & TIMEOUT); 765 atppc_barrier_r(atppc); 766 767 ATPPC_UNLOCK(atppc); 768 splx(s); 769 770 return (error); 771 } 772 773 /* 774 * EPP timeout, according to the PC87332 manual 775 * Semantics of clearing EPP timeout bit. 776 * PC87332 - reading SPP_STR does it... 777 * SMC - write 1 to EPP timeout bit XXX 778 * Others - (?) write 0 to EPP timeout bit 779 */ 780 static void 781 atppc_reset_epp_timeout(struct device * dev) 782 { 783 struct atppc_softc * atppc = (struct atppc_softc *) dev; 784 register unsigned char r; 785 786 r = atppc_r_str(atppc); 787 atppc_barrier_r(atppc); 788 atppc_w_str(atppc, r | 0x1); 789 atppc_barrier_w(atppc); 790 atppc_w_str(atppc, r & 0xfe); 791 atppc_barrier_w(atppc); 792 793 return; 794 } 795 796 797 /* Read from atppc device: returns 0 on success. */ 798 static int 799 atppc_read(struct device * dev, char * buf, int len, int ioflag, 800 size_t * cnt) 801 { 802 struct atppc_softc * atppc = (struct atppc_softc *) dev; 803 int error = 0; 804 int s; 805 806 s = splatppc(); 807 ATPPC_LOCK(atppc); 808 809 *cnt = 0; 810 811 /* Initialize buffer */ 812 atppc->sc_inb = atppc->sc_inbstart = buf; 813 atppc->sc_inb_nbytes = len; 814 815 /* Initialize device input error state for new operation */ 816 atppc->sc_inerr = 0; 817 818 /* Call appropriate function to read bytes */ 819 switch(atppc->sc_mode) { 820 case ATPPC_MODE_STD: 821 case ATPPC_MODE_FAST: 822 error = ENODEV; 823 break; 824 825 case ATPPC_MODE_NIBBLE: 826 atppc_nibble_read(atppc); 827 break; 828 829 case ATPPC_MODE_PS2: 830 atppc_byte_read(atppc); 831 break; 832 833 case ATPPC_MODE_ECP: 834 atppc_ecp_read(atppc); 835 break; 836 837 case ATPPC_MODE_EPP: 838 atppc_epp_read(atppc); 839 break; 840 841 default: 842 panic("%s(%s): chipset in invalid mode.\n", __func__, 843 dev->dv_xname); 844 } 845 846 /* Update counter*/ 847 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 848 849 /* Reset buffer */ 850 atppc->sc_inb = atppc->sc_inbstart = NULL; 851 atppc->sc_inb_nbytes = 0; 852 853 if(!(error)) 854 error = atppc->sc_inerr; 855 856 ATPPC_UNLOCK(atppc); 857 splx(s); 858 859 return (error); 860 } 861 862 /* Write to atppc device: returns 0 on success. */ 863 static int 864 atppc_write(struct device * dev, char * buf, int len, int ioflag, size_t * cnt) 865 { 866 struct atppc_softc * const atppc = (struct atppc_softc *) dev; 867 int error = 0; 868 int s; 869 870 *cnt = 0; 871 872 s = splatppc(); 873 ATPPC_LOCK(atppc); 874 875 /* Set up line buffer */ 876 atppc->sc_outb = atppc->sc_outbstart = buf; 877 atppc->sc_outb_nbytes = len; 878 879 /* Initialize device output error state for new operation */ 880 atppc->sc_outerr = 0; 881 882 /* Call appropriate function to write bytes */ 883 switch(atppc->sc_mode) { 884 case ATPPC_MODE_STD: 885 atppc_std_write(atppc); 886 break; 887 888 case ATPPC_MODE_NIBBLE: 889 case ATPPC_MODE_PS2: 890 error = ENODEV; 891 break; 892 893 case ATPPC_MODE_FAST: 894 case ATPPC_MODE_ECP: 895 atppc_fifo_write(atppc); 896 break; 897 898 case ATPPC_MODE_EPP: 899 atppc_epp_write(atppc); 900 break; 901 902 default: 903 panic("%s(%s): chipset in invalid mode.\n", __func__, 904 dev->dv_xname); 905 } 906 907 /* Update counter*/ 908 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 909 910 /* Reset output buffer */ 911 atppc->sc_outb = atppc->sc_outbstart = NULL; 912 atppc->sc_outb_nbytes = 0; 913 914 if(!(error)) 915 error = atppc->sc_outerr; 916 917 ATPPC_UNLOCK(atppc); 918 splx(s); 919 920 return (error); 921 } 922 923 /* 924 * Set mode of chipset to mode argument. Modes not supported are ignored. If 925 * multiple modes are flagged, the mode is not changed. Mode's are those 926 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 927 * can change their mode of operation. However, ALL operation modes support 928 * centronics mode and nibble mode. Modes determine both hardware AND software 929 * behaviour. 930 * NOTE: the mode for ECP should only be changed when the channel is in 931 * forward idle mode. This function does not make sure FIFO's have flushed or 932 * any consistency checks. 933 */ 934 static int 935 atppc_setmode(struct device * dev, int mode) 936 { 937 struct atppc_softc * atppc = (struct atppc_softc *) dev; 938 u_int8_t ecr; 939 u_int8_t chipset_mode; 940 int s; 941 int rval = 0; 942 943 s = splatppc(); 944 ATPPC_LOCK(atppc); 945 946 /* If ECP capable, configure ecr register */ 947 if (atppc->sc_has & ATPPC_HAS_ECP) { 948 /* Read ECR with mode masked out */ 949 ecr = (atppc_r_ecr(atppc) & (unsigned)0x1f); 950 atppc_barrier_r(atppc); 951 952 switch(mode) { 953 case PPBUS_ECP: 954 /* Set ECP mode */ 955 ecr |= ATPPC_ECR_ECP; 956 chipset_mode = ATPPC_MODE_ECP; 957 break; 958 959 case PPBUS_EPP: 960 /* Set EPP mode */ 961 if(atppc->sc_has & ATPPC_HAS_EPP) { 962 ecr |= ATPPC_ECR_EPP; 963 chipset_mode = ATPPC_MODE_EPP; 964 } 965 else { 966 rval = ENODEV; 967 goto end; 968 } 969 break; 970 971 case PPBUS_FAST: 972 /* Set fast centronics mode */ 973 ecr |= ATPPC_ECR_FIFO; 974 chipset_mode = ATPPC_MODE_FAST; 975 break; 976 977 case PPBUS_PS2: 978 /* Set PS2 mode */ 979 ecr |= ATPPC_ECR_PS2; 980 chipset_mode = ATPPC_MODE_PS2; 981 break; 982 983 case PPBUS_COMPATIBLE: 984 /* Set standard mode */ 985 ecr |= ATPPC_ECR_STD; 986 chipset_mode = ATPPC_MODE_STD;; 987 break; 988 989 case PPBUS_NIBBLE: 990 /* Set nibble mode: uses chipset standard mode */ 991 ecr |= ATPPC_ECR_STD; 992 chipset_mode = ATPPC_MODE_NIBBLE; 993 break; 994 995 default: 996 /* Invalid mode specified for ECP chip */ 997 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 998 "argument.\n", __func__, dev->dv_xname)); 999 rval = ENODEV; 1000 goto end; 1001 } 1002 1003 /* Switch to byte mode to be able to change modes. */ 1004 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1005 atppc_barrier_w(atppc); 1006 1007 /* Update mode */ 1008 atppc_w_ecr(atppc, ecr); 1009 atppc_barrier_w(atppc); 1010 } 1011 else { 1012 switch(mode) { 1013 case PPBUS_EPP: 1014 if(atppc->sc_has & ATPPC_HAS_EPP) { 1015 chipset_mode = ATPPC_MODE_EPP; 1016 } 1017 else { 1018 rval = ENODEV; 1019 goto end; 1020 } 1021 break; 1022 1023 case PPBUS_PS2: 1024 if(atppc->sc_has & ATPPC_HAS_PS2) { 1025 chipset_mode = ATPPC_MODE_PS2; 1026 } 1027 else { 1028 rval = ENODEV; 1029 goto end; 1030 } 1031 break; 1032 1033 case PPBUS_NIBBLE: 1034 /* Set nibble mode (virtual) */ 1035 chipset_mode = ATPPC_MODE_NIBBLE; 1036 break; 1037 1038 case PPBUS_COMPATIBLE: 1039 chipset_mode = ATPPC_MODE_STD; 1040 break; 1041 1042 case PPBUS_ECP: 1043 rval = ENODEV; 1044 goto end; 1045 1046 default: 1047 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1048 "argument.\n", __func__, dev->dv_xname)); 1049 rval = ENODEV; 1050 goto end; 1051 } 1052 } 1053 1054 atppc->sc_mode = chipset_mode; 1055 if(chipset_mode == ATPPC_MODE_PS2) { 1056 /* Set direction bit to reverse */ 1057 ecr = atppc_r_ctr(atppc); 1058 atppc_barrier_r(atppc); 1059 ecr |= PCD; 1060 atppc_w_ctr(atppc, ecr); 1061 atppc_barrier_w(atppc); 1062 } 1063 1064 end: 1065 ATPPC_UNLOCK(atppc); 1066 splx(s); 1067 1068 return rval; 1069 } 1070 1071 /* Get the current mode of chipset */ 1072 static int 1073 atppc_getmode(struct device * dev) 1074 { 1075 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1076 int mode; 1077 int s; 1078 1079 s = splatppc(); 1080 ATPPC_LOCK(atppc); 1081 1082 /* The chipset can only be in one mode at a time logically */ 1083 switch(atppc->sc_mode) { 1084 case ATPPC_MODE_ECP: 1085 mode = PPBUS_ECP; 1086 break; 1087 1088 case ATPPC_MODE_EPP: 1089 mode = PPBUS_EPP; 1090 break; 1091 1092 case ATPPC_MODE_PS2: 1093 mode = PPBUS_PS2; 1094 break; 1095 1096 case ATPPC_MODE_STD: 1097 mode = PPBUS_COMPATIBLE; 1098 break; 1099 1100 case ATPPC_MODE_NIBBLE: 1101 mode = PPBUS_NIBBLE; 1102 break; 1103 1104 case ATPPC_MODE_FAST: 1105 mode = PPBUS_FAST; 1106 break; 1107 1108 default: 1109 panic("%s(%s): device is in invalid mode!", __func__, 1110 dev->dv_xname); 1111 break; 1112 } 1113 1114 ATPPC_UNLOCK(atppc); 1115 splx(s); 1116 1117 return mode; 1118 } 1119 1120 1121 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1122 static void 1123 atppc_ecp_sync(struct device * dev) 1124 { 1125 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1126 int i; 1127 int s; 1128 u_int8_t r; 1129 1130 s = splatppc(); 1131 ATPPC_LOCK(atppc); 1132 1133 /* 1134 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1135 * the mode is either ECP or Fast Centronics. 1136 */ 1137 r = atppc_r_ecr(atppc); 1138 atppc_barrier_r(atppc); 1139 r &= 0xe0; 1140 if(!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1141 && (r != ATPPC_ECR_FIFO))) { 1142 goto end; 1143 } 1144 1145 /* Wait for FIFO to empty */ 1146 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1147 r = atppc_r_ecr(atppc); 1148 atppc_barrier_r(atppc); 1149 if (r & ATPPC_FIFO_EMPTY) { 1150 goto end; 1151 } 1152 delay(100); /* Supposed to be a 100 usec delay */ 1153 } 1154 1155 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1156 dev->dv_xname)); 1157 1158 end: 1159 ATPPC_UNLOCK(atppc); 1160 splx(s); 1161 1162 return; 1163 } 1164 1165 /* Execute a microsequence to handle fast I/O operations. */ 1166 static int 1167 atppc_exec_microseq(struct device * dev, struct ppbus_microseq * * p_msq) 1168 { 1169 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1170 struct ppbus_microseq * mi = *p_msq; 1171 char cc, * p; 1172 int i, iter, len; 1173 int error; 1174 int s; 1175 register int reg; 1176 register unsigned char mask; 1177 register int accum = 0; 1178 register char * ptr = NULL; 1179 struct ppbus_microseq * stack = NULL; 1180 1181 s = splatppc(); 1182 ATPPC_LOCK(atppc); 1183 1184 /* microsequence registers are equivalent to PC-like port registers */ 1185 1186 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1187 (atppc)->sc_ioh, (register)) 1188 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1189 (atppc)->sc_ioh, (register), (byte)) 1190 1191 /* Loop until microsequence execution finishes (ending op code) */ 1192 for (;;) { 1193 switch (mi->opcode) { 1194 case MS_OP_RSET: 1195 cc = r_reg(mi->arg[0].i, atppc); 1196 atppc_barrier_r(atppc); 1197 cc &= (char)mi->arg[2].i; /* clear mask */ 1198 cc |= (char)mi->arg[1].i; /* assert mask */ 1199 w_reg(mi->arg[0].i, atppc, cc); 1200 atppc_barrier_w(atppc); 1201 mi++; 1202 break; 1203 1204 case MS_OP_RASSERT_P: 1205 reg = mi->arg[1].i; 1206 ptr = atppc->sc_ptr; 1207 1208 if((len = mi->arg[0].i) == MS_ACCUM) { 1209 accum = atppc->sc_accum; 1210 for (; accum; accum--) { 1211 w_reg(reg, atppc, *ptr++); 1212 atppc_barrier_w(atppc); 1213 } 1214 atppc->sc_accum = accum; 1215 } 1216 else { 1217 for(i = 0; i < len; i++) { 1218 w_reg(reg, atppc, *ptr++); 1219 atppc_barrier_w(atppc); 1220 } 1221 } 1222 1223 atppc->sc_ptr = ptr; 1224 mi++; 1225 break; 1226 1227 case MS_OP_RFETCH_P: 1228 reg = mi->arg[1].i; 1229 mask = (char)mi->arg[2].i; 1230 ptr = atppc->sc_ptr; 1231 1232 if((len = mi->arg[0].i) == MS_ACCUM) { 1233 accum = atppc->sc_accum; 1234 for (; accum; accum--) { 1235 *ptr++ = r_reg(reg, atppc) & mask; 1236 atppc_barrier_r(atppc); 1237 } 1238 atppc->sc_accum = accum; 1239 } 1240 else { 1241 for(i = 0; i < len; i++) { 1242 *ptr++ = r_reg(reg, atppc) & mask; 1243 atppc_barrier_r(atppc); 1244 } 1245 } 1246 1247 atppc->sc_ptr = ptr; 1248 mi++; 1249 break; 1250 1251 case MS_OP_RFETCH: 1252 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1253 (char)mi->arg[1].i; 1254 atppc_barrier_r(atppc); 1255 mi++; 1256 break; 1257 1258 case MS_OP_RASSERT: 1259 case MS_OP_DELAY: 1260 /* let's suppose the next instr. is the same */ 1261 do { 1262 for(;mi->opcode == MS_OP_RASSERT; mi++) { 1263 w_reg(mi->arg[0].i, atppc, 1264 (char)mi->arg[1].i); 1265 atppc_barrier_w(atppc); 1266 } 1267 1268 for(;mi->opcode == MS_OP_DELAY; mi++) { 1269 delay(mi->arg[0].i); 1270 } 1271 } while(mi->opcode == MS_OP_RASSERT); 1272 break; 1273 1274 case MS_OP_ADELAY: 1275 if(mi->arg[0].i) { 1276 tsleep(atppc, PPBUSPRI, "atppcdelay", 1277 mi->arg[0].i * (hz/1000)); 1278 } 1279 mi++; 1280 break; 1281 1282 case MS_OP_TRIG: 1283 reg = mi->arg[0].i; 1284 iter = mi->arg[1].i; 1285 p = (char *)mi->arg[2].p; 1286 1287 /* XXX delay limited to 255 us */ 1288 for(i = 0; i < iter; i++) { 1289 w_reg(reg, atppc, *p++); 1290 atppc_barrier_w(atppc); 1291 delay((unsigned char)*p++); 1292 } 1293 1294 mi++; 1295 break; 1296 1297 case MS_OP_SET: 1298 atppc->sc_accum = mi->arg[0].i; 1299 mi++; 1300 break; 1301 1302 case MS_OP_DBRA: 1303 if(--atppc->sc_accum > 0) { 1304 mi += mi->arg[0].i; 1305 } 1306 1307 mi++; 1308 break; 1309 1310 case MS_OP_BRSET: 1311 cc = atppc_r_str(atppc); 1312 atppc_barrier_r(atppc); 1313 if((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1314 mi += mi->arg[1].i; 1315 } 1316 mi++; 1317 break; 1318 1319 case MS_OP_BRCLEAR: 1320 cc = atppc_r_str(atppc); 1321 atppc_barrier_r(atppc); 1322 if((cc & (char)mi->arg[0].i) == 0) { 1323 mi += mi->arg[1].i; 1324 } 1325 mi++; 1326 break; 1327 1328 case MS_OP_BRSTAT: 1329 cc = atppc_r_str(atppc); 1330 atppc_barrier_r(atppc); 1331 if((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1332 (char)mi->arg[0].i) { 1333 mi += mi->arg[2].i; 1334 } 1335 mi++; 1336 break; 1337 1338 case MS_OP_C_CALL: 1339 /* 1340 * If the C call returns !0 then end the microseq. 1341 * The current state of ptr is passed to the C function 1342 */ 1343 if((error = mi->arg[0].f(mi->arg[1].p, 1344 atppc->sc_ptr))) { 1345 ATPPC_UNLOCK(atppc); 1346 splx(s); 1347 return (error); 1348 } 1349 mi++; 1350 break; 1351 1352 case MS_OP_PTR: 1353 atppc->sc_ptr = (char *)mi->arg[0].p; 1354 mi++; 1355 break; 1356 1357 case MS_OP_CALL: 1358 if (stack) { 1359 panic("%s - %s: too much calls", dev->dv_xname, 1360 __func__); 1361 } 1362 1363 if (mi->arg[0].p) { 1364 /* store state of the actual microsequence */ 1365 stack = mi; 1366 1367 /* jump to the new microsequence */ 1368 mi = (struct ppbus_microseq *)mi->arg[0].p; 1369 } 1370 else { 1371 mi++; 1372 } 1373 break; 1374 1375 case MS_OP_SUBRET: 1376 /* retrieve microseq and pc state before the call */ 1377 mi = stack; 1378 1379 /* reset the stack */ 1380 stack = 0; 1381 1382 /* XXX return code */ 1383 1384 mi++; 1385 break; 1386 1387 case MS_OP_PUT: 1388 case MS_OP_GET: 1389 case MS_OP_RET: 1390 /* 1391 * Can't return to atppc level during the execution 1392 * of a submicrosequence. 1393 */ 1394 if (stack) { 1395 panic("%s: cannot return to atppc level", 1396 __func__); 1397 } 1398 /* update pc for atppc level of execution */ 1399 *p_msq = mi; 1400 1401 ATPPC_UNLOCK(atppc); 1402 splx(s); 1403 return (0); 1404 break; 1405 1406 default: 1407 panic("%s: unknown microsequence " 1408 "opcode 0x%x", __func__, mi->opcode); 1409 break; 1410 } 1411 } 1412 1413 /* Should not be reached! */ 1414 #ifdef ATPPC_DEBUG 1415 panic("%s: unexpected code reached!\n", __func__); 1416 #endif 1417 } 1418 1419 /* General I/O routine */ 1420 static u_int8_t 1421 atppc_io(struct device * dev, int iop, u_char * addr, int cnt, u_char byte) 1422 { 1423 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1424 u_int8_t val = 0; 1425 int s; 1426 1427 s = splatppc(); 1428 ATPPC_LOCK(atppc); 1429 1430 switch (iop) { 1431 case PPBUS_OUTSB_EPP: 1432 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1433 ATPPC_EPP_DATA, addr, cnt); 1434 break; 1435 case PPBUS_OUTSW_EPP: 1436 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1437 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1438 break; 1439 case PPBUS_OUTSL_EPP: 1440 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1441 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1442 break; 1443 case PPBUS_INSB_EPP: 1444 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1445 ATPPC_EPP_DATA, addr, cnt); 1446 break; 1447 case PPBUS_INSW_EPP: 1448 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1449 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1450 break; 1451 case PPBUS_INSL_EPP: 1452 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1453 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1454 break; 1455 case PPBUS_RDTR: 1456 val = (atppc_r_dtr(atppc)); 1457 break; 1458 case PPBUS_RSTR: 1459 val = (atppc_r_str(atppc)); 1460 break; 1461 case PPBUS_RCTR: 1462 val = (atppc_r_ctr(atppc)); 1463 break; 1464 case PPBUS_REPP_A: 1465 val = (atppc_r_eppA(atppc)); 1466 break; 1467 case PPBUS_REPP_D: 1468 val = (atppc_r_eppD(atppc)); 1469 break; 1470 case PPBUS_RECR: 1471 val = (atppc_r_ecr(atppc)); 1472 break; 1473 case PPBUS_RFIFO: 1474 val = (atppc_r_fifo(atppc)); 1475 break; 1476 case PPBUS_WDTR: 1477 atppc_w_dtr(atppc, byte); 1478 break; 1479 case PPBUS_WSTR: 1480 atppc_w_str(atppc, byte); 1481 break; 1482 case PPBUS_WCTR: 1483 atppc_w_ctr(atppc, byte); 1484 break; 1485 case PPBUS_WEPP_A: 1486 atppc_w_eppA(atppc, byte); 1487 break; 1488 case PPBUS_WEPP_D: 1489 atppc_w_eppD(atppc, byte); 1490 break; 1491 case PPBUS_WECR: 1492 atppc_w_ecr(atppc, byte); 1493 break; 1494 case PPBUS_WFIFO: 1495 atppc_w_fifo(atppc, byte); 1496 break; 1497 default: 1498 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1499 __func__); 1500 break; 1501 } 1502 1503 atppc_barrier(atppc); 1504 1505 ATPPC_UNLOCK(atppc); 1506 splx(s); 1507 1508 return val; 1509 } 1510 1511 /* Read "instance variables" of atppc device */ 1512 static int 1513 atppc_read_ivar(struct device * dev, int index, unsigned int * val) 1514 { 1515 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1516 int rval = 0; 1517 int s; 1518 1519 s = splatppc(); 1520 ATPPC_LOCK(atppc); 1521 1522 switch(index) { 1523 case PPBUS_IVAR_EPP_PROTO: 1524 if(atppc->sc_epp == ATPPC_EPP_1_9) 1525 *val = PPBUS_EPP_1_9; 1526 else if(atppc->sc_epp == ATPPC_EPP_1_7) 1527 *val = PPBUS_EPP_1_7; 1528 break; 1529 1530 case PPBUS_IVAR_INTR: 1531 if(atppc->sc_use & ATPPC_USE_INTR) 1532 *val = 1; 1533 else 1534 *val = 0; 1535 break; 1536 1537 case PPBUS_IVAR_DMA: 1538 if(atppc->sc_use & ATPPC_USE_DMA) 1539 *val = 1; 1540 else 1541 *val = 0; 1542 break; 1543 break; 1544 1545 default: 1546 rval = ENODEV; 1547 } 1548 1549 ATPPC_UNLOCK(atppc); 1550 splx(s); 1551 1552 return rval; 1553 } 1554 1555 /* Write "instance varaibles" of atppc device */ 1556 static int 1557 atppc_write_ivar(struct device * dev, int index, unsigned int * val) 1558 { 1559 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1560 int rval = 0; 1561 int s; 1562 1563 s = splatppc(); 1564 ATPPC_LOCK(atppc); 1565 1566 switch(index) { 1567 case PPBUS_IVAR_EPP_PROTO: 1568 if(*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1569 atppc->sc_epp = *val; 1570 else 1571 rval = EINVAL; 1572 break; 1573 1574 case PPBUS_IVAR_INTR: 1575 if(*val == 0) 1576 atppc->sc_use &= ~ATPPC_USE_INTR; 1577 else if(atppc->sc_has & ATPPC_HAS_INTR) 1578 atppc->sc_use |= ATPPC_USE_INTR; 1579 else 1580 rval = ENODEV; 1581 break; 1582 1583 case PPBUS_IVAR_DMA: 1584 if(*val == 0) 1585 atppc->sc_use &= ~ATPPC_USE_DMA; 1586 else if(atppc->sc_has & ATPPC_HAS_DMA) 1587 atppc->sc_use |= ATPPC_USE_DMA; 1588 else 1589 rval = ENODEV; 1590 break; 1591 1592 default: 1593 rval = ENODEV; 1594 } 1595 1596 ATPPC_UNLOCK(atppc); 1597 splx(s); 1598 1599 return rval; 1600 } 1601 1602 /* Add a handler routine to be called by the interrupt handler */ 1603 static int 1604 atppc_add_handler(struct device * dev, void (*handler)(void *), void *arg) 1605 { 1606 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1607 struct atppc_handler_node * callback; 1608 int rval = 0; 1609 int s; 1610 1611 s = splatppc(); 1612 ATPPC_LOCK(atppc); 1613 1614 if(handler == NULL) { 1615 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1616 __func__, dev->dv_xname)); 1617 rval = EINVAL; 1618 } 1619 else { 1620 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1621 M_NOWAIT); 1622 if(callback) { 1623 callback->func = handler; 1624 callback->arg = arg; 1625 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1626 callback, entries); 1627 } 1628 else { 1629 rval = ENOMEM; 1630 } 1631 } 1632 1633 ATPPC_UNLOCK(atppc); 1634 splx(s); 1635 1636 return rval; 1637 } 1638 1639 /* Remove a handler added by atppc_add_handler() */ 1640 static int 1641 atppc_remove_handler(struct device * dev, void (*handler)(void *)) 1642 { 1643 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1644 struct atppc_handler_node * callback; 1645 int rval = EINVAL; 1646 int s; 1647 1648 s = splatppc(); 1649 ATPPC_LOCK(atppc); 1650 1651 if(SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1652 panic("%s(%s): attempt to remove handler from empty list.\n", 1653 __func__, dev->dv_xname); 1654 1655 /* Search list for handler */ 1656 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1657 if(callback->func == handler) { 1658 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1659 atppc_handler_node, entries); 1660 free(callback, M_DEVBUF); 1661 rval = 0; 1662 break; 1663 } 1664 } 1665 1666 ATPPC_UNLOCK(atppc); 1667 splx(s); 1668 1669 return rval; 1670 } 1671 1672 /* Utility functions */ 1673 1674 1675 /* 1676 * Functions that read bytes from port into buffer: called from interrupt 1677 * handler depending on current chipset mode and cause of interrupt. Return 1678 * value: number of bytes moved. 1679 */ 1680 1681 /* Only the lower 4 bits of the final value are valid */ 1682 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1683 1684 /* Read bytes in nibble mode */ 1685 static void 1686 atppc_nibble_read(struct atppc_softc * atppc) 1687 { 1688 int i; 1689 u_int8_t nibble[2]; 1690 u_int8_t ctr; 1691 u_int8_t str; 1692 1693 /* Enable interrupts if needed */ 1694 if(atppc->sc_use & ATPPC_USE_INTR) { 1695 ctr = atppc_r_ctr(atppc); 1696 atppc_barrier_r(atppc); 1697 if(!(ctr & IRQENABLE)) { 1698 ctr |= IRQENABLE; 1699 atppc_w_ctr(atppc, ctr); 1700 atppc_barrier_w(atppc); 1701 } 1702 } 1703 1704 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1705 /* Check if device has data to send in idle phase */ 1706 str = atppc_r_str(atppc); 1707 atppc_barrier_r(atppc); 1708 if(str & nDATAVAIL) { 1709 return; 1710 } 1711 1712 /* Nibble-mode handshake transfer */ 1713 for(i = 0; i < 2; i++) { 1714 /* Event 7 - ready to take data (HOSTBUSY low) */ 1715 ctr = atppc_r_ctr(atppc); 1716 atppc_barrier_r(atppc); 1717 ctr |= HOSTBUSY; 1718 atppc_w_ctr(atppc, ctr); 1719 atppc_barrier_w(atppc); 1720 1721 /* Event 8 - peripheral writes the first nibble */ 1722 1723 /* Event 9 - peripheral set nAck low */ 1724 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1725 if(atppc->sc_inerr) 1726 return; 1727 1728 /* read nibble */ 1729 nibble[i] = atppc_r_str(atppc); 1730 1731 /* Event 10 - ack, nibble received */ 1732 ctr &= ~HOSTBUSY; 1733 atppc_w_ctr(atppc, ctr); 1734 1735 /* Event 11 - wait ack from peripherial */ 1736 if(atppc->sc_use & ATPPC_USE_INTR) 1737 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1738 atppc->sc_inb, ATPPC_IRQ_nACK); 1739 else 1740 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1741 PTRCLK); 1742 if(atppc->sc_inerr) 1743 return; 1744 } 1745 1746 /* Store byte transfered */ 1747 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1748 (nibble2char(nibble[0]) & 0x0f); 1749 atppc->sc_inbstart++; 1750 } 1751 } 1752 1753 /* Read bytes in bidirectional mode */ 1754 static void 1755 atppc_byte_read(struct atppc_softc * const atppc) 1756 { 1757 u_int8_t ctr; 1758 u_int8_t str; 1759 1760 /* Check direction bit */ 1761 ctr = atppc_r_ctr(atppc); 1762 atppc_barrier_r(atppc); 1763 if(!(ctr & PCD)) { 1764 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1765 "bit set.", atppc->sc_dev.dv_xname)); 1766 atppc->sc_inerr = ENODEV; 1767 return; 1768 } 1769 /* Enable interrupts if needed */ 1770 if(atppc->sc_use & ATPPC_USE_INTR) { 1771 if(!(ctr & IRQENABLE)) { 1772 ctr |= IRQENABLE; 1773 atppc_w_ctr(atppc, ctr); 1774 atppc_barrier_w(atppc); 1775 } 1776 } 1777 1778 /* Byte-mode handshake transfer */ 1779 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1780 /* Check if device has data to send */ 1781 str = atppc_r_str(atppc); 1782 atppc_barrier_r(atppc); 1783 if(str & nDATAVAIL) { 1784 return; 1785 } 1786 1787 /* Event 7 - ready to take data (nAUTO low) */ 1788 ctr |= HOSTBUSY; 1789 atppc_w_ctr(atppc, ctr); 1790 atppc_barrier_w(atppc); 1791 1792 /* Event 9 - peripheral set nAck low */ 1793 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1794 if(atppc->sc_inerr) 1795 return; 1796 1797 /* Store byte transfered */ 1798 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1799 atppc_barrier_r(atppc); 1800 1801 /* Event 10 - data received, can't accept more */ 1802 ctr &= ~HOSTBUSY; 1803 atppc_w_ctr(atppc, ctr); 1804 atppc_barrier_w(atppc); 1805 1806 /* Event 11 - peripheral ack */ 1807 if(atppc->sc_use & ATPPC_USE_INTR) 1808 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1809 atppc->sc_inb, ATPPC_IRQ_nACK); 1810 else 1811 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1812 if(atppc->sc_inerr) 1813 return; 1814 1815 /* Event 16 - strobe */ 1816 str |= HOSTCLK; 1817 atppc_w_str(atppc, str); 1818 atppc_barrier_w(atppc); 1819 DELAY(1); 1820 str &= ~HOSTCLK; 1821 atppc_w_str(atppc, str); 1822 atppc_barrier_w(atppc); 1823 1824 /* Update counter */ 1825 atppc->sc_inbstart++; 1826 } 1827 } 1828 1829 /* Read bytes in EPP mode */ 1830 static void 1831 atppc_epp_read(struct atppc_softc * atppc) 1832 { 1833 if(atppc->sc_epp == ATPPC_EPP_1_9) { 1834 { 1835 uint8_t str; 1836 int i; 1837 1838 atppc_reset_epp_timeout((struct device *)atppc); 1839 for(i = 0; i < atppc->sc_inb_nbytes; i++) { 1840 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1841 atppc_barrier_r(atppc); 1842 str = atppc_r_str(atppc); 1843 atppc_barrier_r(atppc); 1844 if(str & TIMEOUT) { 1845 atppc->sc_inerr = EIO; 1846 break; 1847 } 1848 atppc->sc_inbstart++; 1849 } 1850 } 1851 } 1852 else { 1853 /* Read data block from EPP data register */ 1854 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1855 atppc->sc_inb_nbytes); 1856 atppc_barrier_r(atppc); 1857 /* Update buffer position, byte count and counter */ 1858 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1859 } 1860 1861 return; 1862 } 1863 1864 /* Read bytes in ECP mode */ 1865 static void 1866 atppc_ecp_read(struct atppc_softc * atppc) 1867 { 1868 u_int8_t ecr; 1869 u_int8_t ctr; 1870 u_int8_t str; 1871 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1872 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1873 unsigned int worklen; 1874 1875 /* Check direction bit */ 1876 ctr = ctr_sav; 1877 atppc_barrier_r(atppc); 1878 if(!(ctr & PCD)) { 1879 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1880 "bit set.", atppc->sc_dev.dv_xname)); 1881 atppc->sc_inerr = ENODEV; 1882 goto end; 1883 } 1884 1885 /* Clear device request if any */ 1886 if(atppc->sc_use & ATPPC_USE_INTR) 1887 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1888 1889 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1890 ecr = atppc_r_ecr(atppc); 1891 atppc_barrier_r(atppc); 1892 if(ecr & ATPPC_FIFO_EMPTY) { 1893 /* Check for invalid state */ 1894 if(ecr & ATPPC_FIFO_FULL) { 1895 atppc_ecp_read_error(atppc, worklen); 1896 break; 1897 } 1898 1899 /* Check if device has data to send */ 1900 str = atppc_r_str(atppc); 1901 atppc_barrier_r(atppc); 1902 if(str & nDATAVAIL) { 1903 break; 1904 } 1905 1906 if(atppc->sc_use & ATPPC_USE_INTR) { 1907 /* Enable interrupts */ 1908 ecr &= ~ATPPC_SERVICE_INTR; 1909 atppc_w_ecr(atppc, ecr); 1910 atppc_barrier_w(atppc); 1911 /* Wait for FIFO to fill */ 1912 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1913 atppc->sc_inb, ATPPC_IRQ_FIFO); 1914 if(atppc->sc_inerr) 1915 break; 1916 } 1917 else { 1918 DELAY(1); 1919 } 1920 continue; 1921 } 1922 else if(ecr & ATPPC_FIFO_FULL) { 1923 /* Transfer sc_fifo bytes */ 1924 worklen = atppc->sc_fifo; 1925 } 1926 else if(ecr & ATPPC_SERVICE_INTR) { 1927 /* Transfer sc_rthr bytes */ 1928 worklen = atppc->sc_rthr; 1929 } 1930 else { 1931 /* At least one byte is in the FIFO */ 1932 worklen = 1; 1933 } 1934 1935 if((atppc->sc_use & ATPPC_USE_INTR) && 1936 (atppc->sc_use & ATPPC_USE_DMA)) { 1937 1938 atppc_ecp_read_dma(atppc, &worklen, ecr); 1939 } 1940 else { 1941 atppc_ecp_read_pio(atppc, &worklen, ecr); 1942 } 1943 1944 if(atppc->sc_inerr) { 1945 atppc_ecp_read_error(atppc, worklen); 1946 break; 1947 } 1948 1949 /* Update counter */ 1950 atppc->sc_inbstart += worklen; 1951 } 1952 end: 1953 atppc_w_ctr(atppc, ctr_sav); 1954 atppc_w_ecr(atppc, ecr_sav); 1955 atppc_barrier_w(atppc); 1956 } 1957 1958 /* Read bytes in ECP mode using DMA transfers */ 1959 static void 1960 atppc_ecp_read_dma(struct atppc_softc * atppc, unsigned int * length, 1961 unsigned char ecr) 1962 { 1963 /* Limit transfer to maximum DMA size and start it */ 1964 *length = min(*length, atppc->sc_dma_maxsize); 1965 atppc->sc_dmastat = ATPPC_DMA_INIT; 1966 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1967 ATPPC_DMA_MODE_READ); 1968 1969 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1970 1971 /* Enable interrupts, DMA */ 1972 ecr &= ~ATPPC_SERVICE_INTR; 1973 ecr |= ATPPC_ENABLE_DMA; 1974 atppc_w_ecr(atppc, ecr); 1975 atppc_barrier_w(atppc); 1976 1977 /* Wait for DMA completion */ 1978 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1979 ATPPC_IRQ_DMA); 1980 if(atppc->sc_inerr) 1981 return; 1982 1983 /* Get register value recorded by interrupt handler */ 1984 ecr = atppc->sc_ecr_intr; 1985 /* Clear DMA programming */ 1986 atppc->sc_dma_finish(atppc); 1987 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1988 /* Disable DMA */ 1989 ecr &= ~ATPPC_ENABLE_DMA; 1990 atppc_w_ecr(atppc, ecr); 1991 atppc_barrier_w(atppc); 1992 } 1993 1994 /* Read bytes in ECP mode using PIO transfers */ 1995 static void 1996 atppc_ecp_read_pio(struct atppc_softc * atppc, unsigned int * length, 1997 unsigned char ecr) 1998 { 1999 /* Disable DMA */ 2000 ecr &= ~ATPPC_ENABLE_DMA; 2001 atppc_w_ecr(atppc, ecr); 2002 atppc_barrier_w(atppc); 2003 2004 /* Read from FIFO */ 2005 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 2006 } 2007 2008 /* Handle errors for ECP reads */ 2009 static void 2010 atppc_ecp_read_error(struct atppc_softc * atppc, const unsigned int worklen) 2011 { 2012 unsigned char ecr = atppc_r_ecr(atppc); 2013 2014 /* Abort DMA if not finished */ 2015 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2016 atppc->sc_dma_abort(atppc); 2017 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2018 } 2019 2020 /* Check for invalid states */ 2021 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2022 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2023 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2024 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2025 atppc_barrier_w(atppc); 2026 } 2027 } 2028 2029 /* 2030 * Functions that write bytes to port from buffer: called from atppc_write() 2031 * function depending on current chipset mode. Returns number of bytes moved. 2032 */ 2033 2034 /* Write bytes in std/bidirectional mode */ 2035 static void 2036 atppc_std_write(struct atppc_softc * const atppc) 2037 { 2038 unsigned int timecount; 2039 unsigned char ctr; 2040 2041 ctr = atppc_r_ctr(atppc); 2042 atppc_barrier_r(atppc); 2043 /* Enable interrupts if needed */ 2044 if(atppc->sc_use & ATPPC_USE_INTR) { 2045 if(!(ctr & IRQENABLE)) { 2046 ctr |= IRQENABLE; 2047 atppc_w_ctr(atppc, ctr); 2048 atppc_barrier_w(atppc); 2049 } 2050 } 2051 2052 while(atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2053 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2054 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2055 if(atppc->sc_outerr) 2056 return; 2057 2058 /* Put data in data register */ 2059 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2060 atppc_barrier_w(atppc); 2061 DELAY(1); 2062 2063 /* Pulse strobe to indicate valid data on lines */ 2064 ctr |= STROBE; 2065 atppc_w_ctr(atppc, ctr); 2066 atppc_barrier_w(atppc); 2067 DELAY(1); 2068 ctr &= ~STROBE; 2069 atppc_w_ctr(atppc, ctr); 2070 atppc_barrier_w(atppc); 2071 2072 /* Wait for nACK for MAXBUSYWAIT */ 2073 timecount = 0; 2074 if(atppc->sc_use & ATPPC_USE_INTR) { 2075 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2076 atppc->sc_outb, ATPPC_IRQ_nACK); 2077 if(atppc->sc_outerr) 2078 return; 2079 } 2080 else { 2081 /* Try to catch the pulsed acknowledgement */ 2082 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2083 if(atppc->sc_outerr) 2084 return; 2085 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2086 if(atppc->sc_outerr) 2087 return; 2088 } 2089 2090 /* Update buffer position, byte count and counter */ 2091 atppc->sc_outbstart++; 2092 } 2093 } 2094 2095 2096 /* Write bytes in EPP mode */ 2097 static void 2098 atppc_epp_write(struct atppc_softc * atppc) 2099 { 2100 if(atppc->sc_epp == ATPPC_EPP_1_9) { 2101 { 2102 uint8_t str; 2103 int i; 2104 2105 atppc_reset_epp_timeout((struct device *)atppc); 2106 for(i = 0; i < atppc->sc_outb_nbytes; i++) { 2107 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2108 atppc_barrier_w(atppc); 2109 str = atppc_r_str(atppc); 2110 atppc_barrier_r(atppc); 2111 if(str & TIMEOUT) { 2112 atppc->sc_outerr = EIO; 2113 break; 2114 } 2115 atppc->sc_outbstart++; 2116 } 2117 } 2118 } 2119 else { 2120 /* Write data block to EPP data register */ 2121 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2122 atppc->sc_outb_nbytes); 2123 atppc_barrier_w(atppc); 2124 /* Update buffer position, byte count and counter */ 2125 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2126 } 2127 2128 return; 2129 } 2130 2131 2132 /* Write bytes in ECP/Fast Centronics mode */ 2133 static void 2134 atppc_fifo_write(struct atppc_softc * const atppc) 2135 { 2136 unsigned char ctr; 2137 unsigned char ecr; 2138 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2139 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2140 2141 ctr = ctr_sav; 2142 ecr = ecr_sav; 2143 atppc_barrier_r(atppc); 2144 2145 /* Reset and flush FIFO */ 2146 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2147 atppc_barrier_w(atppc); 2148 /* Disable nAck interrupts and initialize port bits */ 2149 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2150 atppc_w_ctr(atppc, ctr); 2151 atppc_barrier_w(atppc); 2152 /* Restore mode */ 2153 atppc_w_ecr(atppc, ecr); 2154 atppc_barrier_w(atppc); 2155 2156 /* DMA or Programmed IO */ 2157 if((atppc->sc_use & ATPPC_USE_DMA) && 2158 (atppc->sc_use & ATPPC_USE_INTR)) { 2159 2160 atppc_fifo_write_dma(atppc, ecr, ctr); 2161 } 2162 else { 2163 atppc_fifo_write_pio(atppc, ecr, ctr); 2164 } 2165 2166 /* Restore original register values */ 2167 atppc_w_ctr(atppc, ctr_sav); 2168 atppc_w_ecr(atppc, ecr_sav); 2169 atppc_barrier_w(atppc); 2170 } 2171 2172 static void 2173 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2174 unsigned char ctr) 2175 { 2176 unsigned int len; 2177 unsigned int worklen; 2178 2179 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2180 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2181 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2182 2183 /* Wait for device to become ready */ 2184 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2185 if(atppc->sc_outerr) 2186 return; 2187 2188 /* Reset chipset for next DMA transfer */ 2189 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2190 atppc_barrier_w(atppc); 2191 atppc_w_ecr(atppc, ecr); 2192 atppc_barrier_w(atppc); 2193 2194 /* Limit transfer to minimum of space in FIFO and buffer */ 2195 worklen = min(len, atppc->sc_fifo); 2196 2197 /* Limit transfer to maximum DMA size and start it */ 2198 worklen = min(worklen, atppc->sc_dma_maxsize); 2199 atppc->sc_dmastat = ATPPC_DMA_INIT; 2200 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2201 worklen, ATPPC_DMA_MODE_WRITE); 2202 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2203 2204 /* Enable interrupts, DMA */ 2205 ecr &= ~ATPPC_SERVICE_INTR; 2206 ecr |= ATPPC_ENABLE_DMA; 2207 atppc_w_ecr(atppc, ecr); 2208 atppc_barrier_w(atppc); 2209 2210 /* Wait for DMA completion */ 2211 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2212 ATPPC_IRQ_DMA); 2213 if(atppc->sc_outerr) { 2214 atppc_fifo_write_error(atppc, worklen); 2215 return; 2216 } 2217 /* Get register value recorded by interrupt handler */ 2218 ecr = atppc->sc_ecr_intr; 2219 /* Clear DMA programming */ 2220 atppc->sc_dma_finish(atppc); 2221 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2222 /* Disable DMA */ 2223 ecr &= ~ATPPC_ENABLE_DMA; 2224 atppc_w_ecr(atppc, ecr); 2225 atppc_barrier_w(atppc); 2226 2227 /* Wait for FIFO to empty */ 2228 for(;;) { 2229 if(ecr & ATPPC_FIFO_EMPTY) { 2230 if(ecr & ATPPC_FIFO_FULL) { 2231 atppc->sc_outerr = EIO; 2232 atppc_fifo_write_error(atppc, worklen); 2233 return; 2234 } 2235 else { 2236 break; 2237 } 2238 } 2239 2240 /* Enable service interrupt */ 2241 ecr &= ~ATPPC_SERVICE_INTR; 2242 atppc_w_ecr(atppc, ecr); 2243 atppc_barrier_w(atppc); 2244 2245 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2246 atppc->sc_outb, ATPPC_IRQ_FIFO); 2247 if(atppc->sc_outerr) { 2248 atppc_fifo_write_error(atppc, worklen); 2249 return; 2250 } 2251 2252 /* Get register value recorded by interrupt handler */ 2253 ecr = atppc->sc_ecr_intr; 2254 } 2255 2256 /* Update pointer */ 2257 atppc->sc_outbstart += worklen; 2258 } 2259 } 2260 2261 static void 2262 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2263 unsigned char ctr) 2264 { 2265 unsigned int len; 2266 unsigned int worklen; 2267 unsigned int timecount; 2268 2269 /* Disable DMA */ 2270 ecr &= ~ATPPC_ENABLE_DMA; 2271 atppc_w_ecr(atppc, ecr); 2272 atppc_barrier_w(atppc); 2273 2274 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2275 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2276 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2277 2278 /* Wait for device to become ready */ 2279 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2280 if(atppc->sc_outerr) 2281 return; 2282 2283 /* Limit transfer to minimum of space in FIFO and buffer */ 2284 worklen = min(len, atppc->sc_fifo); 2285 2286 /* Write to FIFO */ 2287 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2288 2289 timecount = 0; 2290 if(atppc->sc_use & ATPPC_USE_INTR) { 2291 ecr = atppc_r_ecr(atppc); 2292 atppc_barrier_w(atppc); 2293 2294 /* Wait for interrupt */ 2295 for(;;) { 2296 if(ecr & ATPPC_FIFO_EMPTY) { 2297 if(ecr & ATPPC_FIFO_FULL) { 2298 atppc->sc_outerr = EIO; 2299 atppc_fifo_write_error(atppc, 2300 worklen); 2301 return; 2302 } 2303 else { 2304 break; 2305 } 2306 } 2307 2308 /* Enable service interrupt */ 2309 ecr &= ~ATPPC_SERVICE_INTR; 2310 atppc_w_ecr(atppc, ecr); 2311 atppc_barrier_w(atppc); 2312 2313 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2314 atppc->sc_outb, ATPPC_IRQ_FIFO); 2315 if(atppc->sc_outerr) { 2316 atppc_fifo_write_error(atppc, worklen); 2317 return; 2318 } 2319 2320 /* Get ECR value saved by interrupt handler */ 2321 ecr = atppc->sc_ecr_intr; 2322 } 2323 } 2324 else { 2325 for(; timecount < ((MAXBUSYWAIT/hz)*1000000); 2326 timecount++) { 2327 2328 ecr = atppc_r_ecr(atppc); 2329 atppc_barrier_r(atppc); 2330 if(ecr & ATPPC_FIFO_EMPTY) { 2331 if(ecr & ATPPC_FIFO_FULL) { 2332 atppc->sc_outerr = EIO; 2333 atppc_fifo_write_error(atppc, 2334 worklen); 2335 return; 2336 } 2337 else { 2338 break; 2339 } 2340 } 2341 DELAY(1); 2342 } 2343 2344 if(((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2345 atppc->sc_outerr = EIO; 2346 atppc_fifo_write_error(atppc, worklen); 2347 return; 2348 } 2349 } 2350 2351 /* Update pointer */ 2352 atppc->sc_outbstart += worklen; 2353 } 2354 } 2355 2356 static void 2357 atppc_fifo_write_error(struct atppc_softc * const atppc, 2358 const unsigned int worklen) 2359 { 2360 unsigned char ecr = atppc_r_ecr(atppc); 2361 2362 /* Abort DMA if not finished */ 2363 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2364 atppc->sc_dma_abort(atppc); 2365 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2366 } 2367 2368 /* Check for invalid states */ 2369 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2370 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2371 } 2372 else if(!(ecr & ATPPC_FIFO_EMPTY)) { 2373 unsigned char ctr = atppc_r_ctr(atppc); 2374 int bytes_left; 2375 int i; 2376 2377 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2378 atppc->sc_dev.dv_xname)); 2379 2380 /* Drive strobe low to stop data transfer */ 2381 ctr &= ~STROBE; 2382 atppc_w_ctr(atppc, ctr); 2383 atppc_barrier_w(atppc); 2384 2385 /* Determine how many bytes remain in FIFO */ 2386 for(i = 0; i < atppc->sc_fifo; i++) { 2387 atppc_w_fifo(atppc, (unsigned char)i); 2388 ecr = atppc_r_ecr(atppc); 2389 atppc_barrier_r(atppc); 2390 if(ecr & ATPPC_FIFO_FULL) 2391 break; 2392 } 2393 bytes_left = (atppc->sc_fifo) - (i + 1); 2394 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2395 bytes_left)); 2396 2397 /* Update counter */ 2398 atppc->sc_outbstart += (worklen - bytes_left); 2399 } 2400 else { 2401 /* Update counter */ 2402 atppc->sc_outbstart += worklen; 2403 } 2404 2405 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2406 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2407 atppc_barrier_w(atppc); 2408 } 2409 2410 /* 2411 * Poll status register using mask and status for MAXBUSYWAIT. 2412 * Returns 0 if device ready, error value otherwise. 2413 */ 2414 static int 2415 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2416 const u_int8_t mask) 2417 { 2418 unsigned int timecount; 2419 u_int8_t str; 2420 int error = EIO; 2421 2422 /* Wait for str to have status for MAXBUSYWAIT */ 2423 for(timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2424 timecount++) { 2425 2426 str = atppc_r_str(atppc); 2427 atppc_barrier_r(atppc); 2428 if((str & mask) == status) { 2429 error = 0; 2430 break; 2431 } 2432 DELAY(1); 2433 } 2434 2435 return error; 2436 } 2437 2438 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2439 static int 2440 atppc_wait_interrupt(struct atppc_softc * const atppc, const caddr_t where, 2441 const u_int8_t irqstat) 2442 { 2443 int error = EIO; 2444 2445 atppc->sc_irqstat &= ~irqstat; 2446 2447 /* Wait for interrupt for MAXBUSYWAIT */ 2448 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2449 ATPPC_SC_LOCK(atppc)); 2450 2451 if(!(error) && (atppc->sc_irqstat & irqstat)) { 2452 atppc->sc_irqstat &= ~irqstat; 2453 error = 0; 2454 } 2455 2456 return error; 2457 } 2458
Indexes created Thu Sep 25 16:09:42 GMT 2025