atppc.c revision 1.14
1 /* $NetBSD: atppc.c,v 1.14 2004/02/24 15:12:52 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * Copyright (c) 2003, 2004 Gary Thorpe <gathorpe (at) users.sourceforge.net> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: atppc.c,v 1.14 2004/02/24 15:12:52 wiz Exp $"); 35 36 #include "opt_atppc.h" 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/proc.h> 44 #include <sys/systm.h> 45 #include <sys/vnode.h> 46 #include <sys/syslog.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/isa/isareg.h> 52 53 #include <dev/ic/atppcreg.h> 54 #include <dev/ic/atppcvar.h> 55 56 #include <dev/ppbus/ppbus_conf.h> 57 #include <dev/ppbus/ppbus_msq.h> 58 #include <dev/ppbus/ppbus_io.h> 59 #include <dev/ppbus/ppbus_var.h> 60 61 #ifdef ATPPC_DEBUG 62 int atppc_debug = 1; 63 #endif 64 65 #ifdef ATPPC_VERBOSE 66 int atppc_verbose = 1; 67 #endif 68 69 /* List of supported chipsets detection routines */ 70 static int (*chipset_detect[])(struct atppc_softc *) = { 71 /* XXX Add these LATER: maybe as seperate devices? 72 atppc_pc873xx_detect, 73 atppc_smc37c66xgt_detect, 74 atppc_w83877f_detect, 75 atppc_smc37c935_detect, 76 */ 77 NULL 78 }; 79 80 81 /* Prototypes for functions. */ 82 83 /* Soft configuration attach */ 84 void atppc_sc_attach(struct atppc_softc *); 85 int atppc_sc_detach(struct atppc_softc *, int); 86 87 /* Interrupt handler for atppc device */ 88 int atppcintr(void *); 89 90 /* Print function for config_found_sm() */ 91 static int atppc_print(void *, const char *); 92 93 /* Detection routines */ 94 static int atppc_detect_fifo(struct atppc_softc *); 95 static int atppc_detect_chipset(struct atppc_softc *); 96 static int atppc_detect_generic(struct atppc_softc *); 97 98 /* Routines for ppbus interface (bus + device) */ 99 static int atppc_read(struct device *, char *, int, int, size_t *); 100 static int atppc_write(struct device *, char *, int, int, size_t *); 101 static int atppc_setmode(struct device *, int); 102 static int atppc_getmode(struct device *); 103 static int atppc_check_epp_timeout(struct device *); 104 static void atppc_reset_epp_timeout(struct device *); 105 static void atppc_ecp_sync(struct device *); 106 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 107 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 108 static int atppc_read_ivar(struct device *, int, unsigned int *); 109 static int atppc_write_ivar(struct device *, int, unsigned int *); 110 static int atppc_add_handler(struct device *, void (*)(void *), void *); 111 static int atppc_remove_handler(struct device *, void (*)(void *)); 112 113 /* Utility functions */ 114 115 /* Functions to read bytes into device's input buffer */ 116 static void atppc_nibble_read(struct atppc_softc * const); 117 static void atppc_byte_read(struct atppc_softc * const); 118 static void atppc_epp_read(struct atppc_softc * const); 119 static void atppc_ecp_read(struct atppc_softc * const); 120 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 121 unsigned char); 122 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 123 unsigned char); 124 static void atppc_ecp_read_error(struct atppc_softc *, const unsigned int); 125 126 127 /* Functions to write bytes to device's output buffer */ 128 static void atppc_std_write(struct atppc_softc * const); 129 static void atppc_epp_write(struct atppc_softc * const); 130 static void atppc_fifo_write(struct atppc_softc * const); 131 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 132 unsigned char); 133 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 134 unsigned char); 135 static void atppc_fifo_write_error(struct atppc_softc * const, 136 const unsigned int); 137 138 /* Miscellaneous */ 139 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 140 const u_int8_t); 141 static int atppc_wait_interrupt(struct atppc_softc * const, const caddr_t, 142 const u_int8_t); 143 144 145 /* 146 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 147 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 148 */ 149 150 /* Soft configuration attach for atppc */ 151 void 152 atppc_sc_attach(struct atppc_softc *lsc) 153 { 154 /* Adapter used to configure ppbus device */ 155 struct parport_adapter sc_parport_adapter; 156 char buf[64]; 157 158 /* Probe and set up chipset */ 159 if (atppc_detect_chipset(lsc) != 0) { 160 if (atppc_detect_generic(lsc) != 0) { 161 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 162 lsc->sc_dev.dv_xname)); 163 } 164 } 165 166 /* Probe and setup FIFO queue */ 167 if (atppc_detect_fifo(lsc) == 0) { 168 printf("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 169 lsc->sc_dev.dv_xname, lsc->sc_fifo, lsc->sc_wthr, 170 lsc->sc_rthr); 171 } 172 173 /* Print out chipset capabilities */ 174 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 175 buf, sizeof(buf)); 176 printf("%s: capabilities=%s\n", lsc->sc_dev.dv_xname, buf); 177 178 /* Initialize device's buffer pointers */ 179 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 180 = NULL; 181 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 182 183 /* Last configuration step: set mode to standard mode */ 184 if (atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 185 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 186 lsc->sc_dev.dv_xname)); 187 } 188 189 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 190 /* Initialize lock structure */ 191 simple_lock_init(&(lsc->sc_lock)); 192 #endif 193 194 /* Set up parport_adapter structure */ 195 196 /* Set capabilites */ 197 sc_parport_adapter.capabilities = 0; 198 if (lsc->sc_has & ATPPC_HAS_INTR) { 199 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 200 } 201 if (lsc->sc_has & ATPPC_HAS_DMA) { 202 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 203 } 204 if (lsc->sc_has & ATPPC_HAS_FIFO) { 205 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 206 } 207 if (lsc->sc_has & ATPPC_HAS_PS2) { 208 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 209 } 210 if (lsc->sc_has & ATPPC_HAS_EPP) { 211 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 212 } 213 if (lsc->sc_has & ATPPC_HAS_ECP) { 214 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 215 } 216 217 /* Set function pointers */ 218 sc_parport_adapter.parport_io = atppc_io; 219 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 220 sc_parport_adapter.parport_reset_epp_timeout = 221 atppc_reset_epp_timeout; 222 sc_parport_adapter.parport_setmode = atppc_setmode; 223 sc_parport_adapter.parport_getmode = atppc_getmode; 224 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 225 sc_parport_adapter.parport_read = atppc_read; 226 sc_parport_adapter.parport_write = atppc_write; 227 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 228 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 229 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 230 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 231 sc_parport_adapter.parport_add_handler = atppc_add_handler; 232 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 233 234 /* Initialize handler list, may be added to by grandchildren */ 235 SLIST_INIT(&(lsc->sc_handler_listhead)); 236 237 /* Initialize interrupt state */ 238 lsc->sc_irqstat = ATPPC_IRQ_NONE; 239 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 240 241 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 242 lsc->sc_use = 0; 243 244 /* Configure child of the device. */ 245 lsc->child = config_found_sm(&(lsc->sc_dev), &(sc_parport_adapter), 246 atppc_print, NULL); 247 248 return; 249 } 250 251 /* Soft configuration detach */ 252 int atppc_sc_detach(struct atppc_softc *lsc, int flag) 253 { 254 struct device *dev = (struct device *)lsc; 255 256 /* Detach children devices */ 257 if (config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 258 printf("%s not able to detach child device, ", dev->dv_xname); 259 260 if (!(flag & DETACH_FORCE)) { 261 printf("cannot detach\n"); 262 return 1; 263 } else { 264 printf("continuing (DETACH_FORCE)\n"); 265 } 266 } 267 268 if (!(flag & DETACH_QUIET)) 269 printf("%s detached", dev->dv_xname); 270 271 return 0; 272 } 273 274 /* Used by config_found_sm() to print out device information */ 275 static int 276 atppc_print(void *aux, const char *name) 277 { 278 /* Print out something on failure. */ 279 if (name != NULL) { 280 printf("%s: child devices", name); 281 return UNCONF; 282 } 283 284 return QUIET; 285 } 286 287 /* 288 * Machine independent detection routines for atppc driver. 289 */ 290 291 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 292 int 293 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 294 { 295 /* 296 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() 297 * in original lpt driver. 298 * Write to data register common to all controllers and read back the 299 * values. Also tests control and status registers. 300 */ 301 302 /* 303 * Cannot use convenient macros because the device's config structure 304 * may not have been created yet: major change from FreeBSD code. 305 */ 306 307 int rval; 308 u_int8_t ctr_sav, dtr_sav, str_sav; 309 310 /* Store writtable registers' values and test if they can be read */ 311 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 312 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 313 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 314 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 315 BUS_SPACE_BARRIER_READ); 316 317 /* 318 * Ensure PS2 ports in output mode, also read back value of control 319 * register. 320 */ 321 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 322 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 323 BUS_SPACE_BARRIER_WRITE); 324 325 if (bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 326 rval = 0; 327 } else { 328 /* 329 * Test if two values can be written and read from the data 330 * register. 331 */ 332 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 333 BUS_SPACE_BARRIER_READ); 334 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 335 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 336 BUS_SPACE_BARRIER_WRITE); 337 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 338 rval = 1; 339 } else { 340 /* Second value to test */ 341 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 342 BUS_SPACE_BARRIER_READ); 343 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 344 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 345 BUS_SPACE_BARRIER_WRITE); 346 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 347 rval = 1; 348 } else { 349 rval = 0; 350 } 351 } 352 353 } 354 355 /* Restore registers */ 356 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 357 BUS_SPACE_BARRIER_READ); 358 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 359 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 360 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 361 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 362 BUS_SPACE_BARRIER_WRITE); 363 364 return rval; 365 } 366 367 /* Detect parallel port chipset. */ 368 static int 369 atppc_detect_chipset(struct atppc_softc *atppc) 370 { 371 /* Try each detection routine. */ 372 int i, mode; 373 for (i = 0; chipset_detect[i] != NULL; i++) { 374 if ((mode = chipset_detect[i](atppc)) != -1) { 375 atppc->sc_mode = mode; 376 return 0; 377 } 378 } 379 380 return 1; 381 } 382 383 /* Detect generic capabilities. */ 384 static int 385 atppc_detect_generic(struct atppc_softc *atppc) 386 { 387 u_int8_t ecr_sav = atppc_r_ecr(atppc); 388 u_int8_t ctr_sav = atppc_r_ctr(atppc); 389 u_int8_t str_sav = atppc_r_str(atppc); 390 u_int8_t tmp; 391 atppc_barrier_r(atppc); 392 393 /* Default to generic */ 394 atppc->sc_type = ATPPC_TYPE_GENERIC; 395 atppc->sc_model = GENERIC; 396 397 /* Check for ECP */ 398 tmp = atppc_r_ecr(atppc); 399 atppc_barrier_r(atppc); 400 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 401 atppc_w_ecr(atppc, 0x34); 402 atppc_barrier_w(atppc); 403 tmp = atppc_r_ecr(atppc); 404 atppc_barrier_r(atppc); 405 if (tmp == 0x35) { 406 atppc->sc_has |= ATPPC_HAS_ECP; 407 } 408 } 409 410 /* Allow search for SMC style ECP+EPP mode */ 411 if (atppc->sc_has & ATPPC_HAS_ECP) { 412 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 413 atppc_barrier_w(atppc); 414 } 415 /* Check for EPP by checking for timeout bit */ 416 if (atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 417 atppc->sc_has |= ATPPC_HAS_EPP; 418 atppc->sc_epp = ATPPC_EPP_1_9; 419 if (atppc->sc_has & ATPPC_HAS_ECP) { 420 /* SMC like chipset found */ 421 atppc->sc_model = SMC_LIKE; 422 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 423 } 424 } 425 426 /* Detect PS2 mode */ 427 if (atppc->sc_has & ATPPC_HAS_ECP) { 428 /* Put ECP port into PS2 mode */ 429 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 430 atppc_barrier_w(atppc); 431 } 432 /* Put PS2 port in input mode: writes should not be readable */ 433 atppc_w_ctr(atppc, 0x20); 434 atppc_barrier_w(atppc); 435 /* 436 * Write two values to data port: if neither are read back, 437 * bidirectional mode is functional. 438 */ 439 atppc_w_dtr(atppc, 0xaa); 440 atppc_barrier_w(atppc); 441 tmp = atppc_r_dtr(atppc); 442 atppc_barrier_r(atppc); 443 if (tmp != 0xaa) { 444 atppc_w_dtr(atppc, 0x55); 445 atppc_barrier_w(atppc); 446 tmp = atppc_r_dtr(atppc); 447 atppc_barrier_r(atppc); 448 if (tmp != 0x55) { 449 atppc->sc_has |= ATPPC_HAS_PS2; 450 } 451 } 452 453 /* Restore to previous state */ 454 atppc_w_ecr(atppc, ecr_sav); 455 atppc_w_ctr(atppc, ctr_sav); 456 atppc_w_str(atppc, str_sav); 457 atppc_barrier_w(atppc); 458 459 return 0; 460 } 461 462 /* 463 * Detect parallel port FIFO: taken from FreeBSD code directly. 464 */ 465 static int 466 atppc_detect_fifo(struct atppc_softc *atppc) 467 { 468 #ifdef ATPPC_DEBUG 469 struct device *dev = (struct device *)atppc; 470 #endif 471 u_int8_t ecr_sav; 472 u_int8_t ctr_sav; 473 u_int8_t str_sav; 474 u_int8_t cc; 475 short i; 476 477 /* If there is no ECP mode, we cannot config a FIFO */ 478 if (!(atppc->sc_has & ATPPC_HAS_ECP)) { 479 return (EINVAL); 480 } 481 482 /* save registers */ 483 ecr_sav = atppc_r_ecr(atppc); 484 ctr_sav = atppc_r_ctr(atppc); 485 str_sav = atppc_r_str(atppc); 486 atppc_barrier_r(atppc); 487 488 /* Enter ECP configuration mode, no interrupt, no DMA */ 489 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 490 ~ATPPC_ENABLE_DMA); 491 atppc_barrier_w(atppc); 492 493 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 494 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 495 atppc_barrier_r(atppc); 496 497 /* XXX 16 and 32 bits implementations not supported */ 498 if (atppc->sc_pword != ATPPC_PWORD_8) { 499 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 500 __func__, dev->dv_xname, atppc->sc_pword)); 501 goto error; 502 } 503 504 /* Byte mode, reverse direction, no interrupt, no DMA */ 505 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 506 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 507 /* enter ECP test mode, no interrupt, no DMA */ 508 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 509 atppc_barrier_w(atppc); 510 511 /* flush the FIFO */ 512 for (i = 0; i < 1024; i++) { 513 atppc_r_fifo(atppc); 514 atppc_barrier_r(atppc); 515 cc = atppc_r_ecr(atppc); 516 atppc_barrier_r(atppc); 517 if (cc & ATPPC_FIFO_EMPTY) 518 break; 519 } 520 if (i >= 1024) { 521 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 522 dev->dv_xname)); 523 goto error; 524 } 525 526 /* Test mode, enable interrupts, no DMA */ 527 atppc_w_ecr(atppc, ATPPC_ECR_TST); 528 atppc_barrier_w(atppc); 529 530 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 531 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 532 atppc_w_fifo(atppc, (char)i); 533 atppc_barrier_w(atppc); 534 cc = atppc_r_ecr(atppc); 535 atppc_barrier_r(atppc); 536 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 537 /* readThreshold reached */ 538 atppc->sc_rthr = i + 1; 539 } 540 if (cc & ATPPC_FIFO_FULL) { 541 atppc->sc_fifo = i + 1; 542 break; 543 } 544 } 545 if (i >= 1024) { 546 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 547 dev->dv_xname)); 548 goto error; 549 } 550 551 /* Change direction */ 552 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 553 atppc_barrier_w(atppc); 554 555 /* Clear the serviceIntr bit we've already set in the above loop */ 556 atppc_w_ecr(atppc, ATPPC_ECR_TST); 557 atppc_barrier_w(atppc); 558 559 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 560 for (atppc->sc_wthr = 0; i > -1; i--) { 561 cc = atppc_r_fifo(atppc); 562 atppc_barrier_r(atppc); 563 if (cc != (char)(atppc->sc_fifo - i - 1)) { 564 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 565 __func__, dev->dv_xname)); 566 goto error; 567 } 568 569 cc = atppc_r_ecr(atppc); 570 atppc_barrier_r(atppc); 571 if ((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 572 /* writeIntrThreshold reached */ 573 atppc->sc_wthr = atppc->sc_fifo - i; 574 } 575 576 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 577 /* If FIFO empty before the last byte, error */ 578 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 579 dev->dv_xname)); 580 goto error; 581 } 582 } 583 584 /* FIFO must be empty after the last byte */ 585 cc = atppc_r_ecr(atppc); 586 atppc_barrier_r(atppc); 587 if (!(cc & ATPPC_FIFO_EMPTY)) { 588 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 589 dev->dv_xname)); 590 goto error; 591 } 592 593 /* Restore original registers */ 594 atppc_w_ctr(atppc, ctr_sav); 595 atppc_w_str(atppc, str_sav); 596 atppc_w_ecr(atppc, ecr_sav); 597 atppc_barrier_w(atppc); 598 599 /* Update capabilities */ 600 atppc->sc_has |= ATPPC_HAS_FIFO; 601 602 return 0; 603 604 error: 605 /* Restore original registers */ 606 atppc_w_ctr(atppc, ctr_sav); 607 atppc_w_str(atppc, str_sav); 608 atppc_w_ecr(atppc, ecr_sav); 609 atppc_barrier_w(atppc); 610 611 return (EINVAL); 612 } 613 614 /* Interrupt handler for atppc device: wakes up read/write functions */ 615 int 616 atppcintr(void *arg) 617 { 618 struct atppc_softc *atppc = (struct atppc_softc *)arg; 619 struct device *dev = &atppc->sc_dev; 620 int claim = 1; 621 enum { NONE, READER, WRITER } wake_up = NONE; 622 int s; 623 624 s = splatppc(); 625 ATPPC_LOCK(atppc); 626 627 /* Record registers' status */ 628 atppc->sc_str_intr = atppc_r_str(atppc); 629 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 630 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 631 atppc_barrier_r(atppc); 632 633 /* Determine cause of interrupt and wake up top half */ 634 switch (atppc->sc_mode) { 635 case ATPPC_MODE_STD: 636 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 637 atppc->sc_irqstat = ATPPC_IRQ_nACK; 638 if (atppc->sc_outb) 639 wake_up = WRITER; 640 else 641 claim = 0; 642 break; 643 644 case ATPPC_MODE_NIBBLE: 645 case ATPPC_MODE_PS2: 646 /* nAck is set low by device and then high on ack */ 647 if (!(atppc->sc_str_intr & nACK)) { 648 claim = 0; 649 break; 650 } 651 atppc->sc_irqstat = ATPPC_IRQ_nACK; 652 if (atppc->sc_inb) 653 wake_up = READER; 654 else 655 claim = 0; 656 break; 657 658 case ATPPC_MODE_ECP: 659 case ATPPC_MODE_FAST: 660 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 661 if (atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 662 if (atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 663 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 664 else 665 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 666 667 /* Decide where top half will be waiting */ 668 if (atppc->sc_mode & ATPPC_MODE_ECP) { 669 if (atppc->sc_ctr_intr & PCD) { 670 if (atppc->sc_inb) 671 wake_up = READER; 672 else 673 claim = 0; 674 } else { 675 if (atppc->sc_outb) 676 wake_up = WRITER; 677 else 678 claim = 0; 679 } 680 } else { 681 if (atppc->sc_outb) 682 wake_up = WRITER; 683 else 684 claim = 0; 685 } 686 } 687 /* Determine if nFault has occurred */ 688 if ((atppc->sc_mode & ATPPC_MODE_ECP) && 689 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 690 !(atppc->sc_str_intr & nFAULT)) { 691 692 /* Device is requesting the channel */ 693 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 694 claim = 1; 695 } 696 break; 697 698 case ATPPC_MODE_EPP: 699 /* nAck pulsed for 5 usec, too fast to check reliably */ 700 atppc->sc_irqstat = ATPPC_IRQ_nACK; 701 if (atppc->sc_inb) 702 wake_up = WRITER; 703 else if (atppc->sc_outb) 704 wake_up = READER; 705 else 706 claim = 0; 707 break; 708 709 default: 710 panic("%s: chipset is in invalid mode.", dev->dv_xname); 711 } 712 713 if (claim) { 714 switch (wake_up) { 715 case NONE: 716 break; 717 718 case READER: 719 wakeup(atppc->sc_inb); 720 break; 721 722 case WRITER: 723 wakeup(atppc->sc_outb); 724 break; 725 } 726 } 727 728 ATPPC_UNLOCK(atppc); 729 730 /* Call all of the installed handlers */ 731 if (claim) { 732 struct atppc_handler_node * callback; 733 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 734 entries) { 735 (*callback->func)(callback->arg); 736 } 737 } 738 739 splx(s); 740 741 return claim; 742 } 743 744 745 /* Functions which support ppbus interface */ 746 747 748 /* Check EPP mode timeout */ 749 static int 750 atppc_check_epp_timeout(struct device *dev) 751 { 752 struct atppc_softc *atppc = (struct atppc_softc *)dev; 753 int s; 754 int error; 755 756 s = splatppc(); 757 ATPPC_LOCK(atppc); 758 759 atppc_reset_epp_timeout(dev); 760 error = !(atppc_r_str(atppc) & TIMEOUT); 761 atppc_barrier_r(atppc); 762 763 ATPPC_UNLOCK(atppc); 764 splx(s); 765 766 return (error); 767 } 768 769 /* 770 * EPP timeout, according to the PC87332 manual 771 * Semantics of clearing EPP timeout bit. 772 * PC87332 - reading SPP_STR does it... 773 * SMC - write 1 to EPP timeout bit XXX 774 * Others - (?) write 0 to EPP timeout bit 775 */ 776 static void 777 atppc_reset_epp_timeout(struct device *dev) 778 { 779 struct atppc_softc *atppc = (struct atppc_softc *)dev; 780 register unsigned char r; 781 782 r = atppc_r_str(atppc); 783 atppc_barrier_r(atppc); 784 atppc_w_str(atppc, r | 0x1); 785 atppc_barrier_w(atppc); 786 atppc_w_str(atppc, r & 0xfe); 787 atppc_barrier_w(atppc); 788 789 return; 790 } 791 792 793 /* Read from atppc device: returns 0 on success. */ 794 static int 795 atppc_read(struct device *dev, char *buf, int len, int ioflag, 796 size_t *cnt) 797 { 798 struct atppc_softc *atppc = (struct atppc_softc *)dev; 799 int error = 0; 800 int s; 801 802 s = splatppc(); 803 ATPPC_LOCK(atppc); 804 805 *cnt = 0; 806 807 /* Initialize buffer */ 808 atppc->sc_inb = atppc->sc_inbstart = buf; 809 atppc->sc_inb_nbytes = len; 810 811 /* Initialize device input error state for new operation */ 812 atppc->sc_inerr = 0; 813 814 /* Call appropriate function to read bytes */ 815 switch(atppc->sc_mode) { 816 case ATPPC_MODE_STD: 817 case ATPPC_MODE_FAST: 818 error = ENODEV; 819 break; 820 821 case ATPPC_MODE_NIBBLE: 822 atppc_nibble_read(atppc); 823 break; 824 825 case ATPPC_MODE_PS2: 826 atppc_byte_read(atppc); 827 break; 828 829 case ATPPC_MODE_ECP: 830 atppc_ecp_read(atppc); 831 break; 832 833 case ATPPC_MODE_EPP: 834 atppc_epp_read(atppc); 835 break; 836 837 default: 838 panic("%s(%s): chipset in invalid mode.\n", __func__, 839 dev->dv_xname); 840 } 841 842 /* Update counter*/ 843 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 844 845 /* Reset buffer */ 846 atppc->sc_inb = atppc->sc_inbstart = NULL; 847 atppc->sc_inb_nbytes = 0; 848 849 if (!(error)) 850 error = atppc->sc_inerr; 851 852 ATPPC_UNLOCK(atppc); 853 splx(s); 854 855 return (error); 856 } 857 858 /* Write to atppc device: returns 0 on success. */ 859 static int 860 atppc_write(struct device *dev, char *buf, int len, int ioflag, size_t *cnt) 861 { 862 struct atppc_softc * const atppc = (struct atppc_softc *)dev; 863 int error = 0; 864 int s; 865 866 *cnt = 0; 867 868 s = splatppc(); 869 ATPPC_LOCK(atppc); 870 871 /* Set up line buffer */ 872 atppc->sc_outb = atppc->sc_outbstart = buf; 873 atppc->sc_outb_nbytes = len; 874 875 /* Initialize device output error state for new operation */ 876 atppc->sc_outerr = 0; 877 878 /* Call appropriate function to write bytes */ 879 switch (atppc->sc_mode) { 880 case ATPPC_MODE_STD: 881 atppc_std_write(atppc); 882 break; 883 884 case ATPPC_MODE_NIBBLE: 885 case ATPPC_MODE_PS2: 886 error = ENODEV; 887 break; 888 889 case ATPPC_MODE_FAST: 890 case ATPPC_MODE_ECP: 891 atppc_fifo_write(atppc); 892 break; 893 894 case ATPPC_MODE_EPP: 895 atppc_epp_write(atppc); 896 break; 897 898 default: 899 panic("%s(%s): chipset in invalid mode.\n", __func__, 900 dev->dv_xname); 901 } 902 903 /* Update counter*/ 904 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 905 906 /* Reset output buffer */ 907 atppc->sc_outb = atppc->sc_outbstart = NULL; 908 atppc->sc_outb_nbytes = 0; 909 910 if (!(error)) 911 error = atppc->sc_outerr; 912 913 ATPPC_UNLOCK(atppc); 914 splx(s); 915 916 return (error); 917 } 918 919 /* 920 * Set mode of chipset to mode argument. Modes not supported are ignored. If 921 * multiple modes are flagged, the mode is not changed. Mode's are those 922 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 923 * can change their mode of operation. However, ALL operation modes support 924 * centronics mode and nibble mode. Modes determine both hardware AND software 925 * behaviour. 926 * NOTE: the mode for ECP should only be changed when the channel is in 927 * forward idle mode. This function does not make sure FIFO's have flushed or 928 * any consistency checks. 929 */ 930 static int 931 atppc_setmode(struct device *dev, int mode) 932 { 933 struct atppc_softc *atppc = (struct atppc_softc *)dev; 934 u_int8_t ecr; 935 u_int8_t chipset_mode; 936 int s; 937 int rval = 0; 938 939 s = splatppc(); 940 ATPPC_LOCK(atppc); 941 942 /* If ECP capable, configure ecr register */ 943 if (atppc->sc_has & ATPPC_HAS_ECP) { 944 /* Read ECR with mode masked out */ 945 ecr = (atppc_r_ecr(atppc) & 0x1f); 946 atppc_barrier_r(atppc); 947 948 switch (mode) { 949 case PPBUS_ECP: 950 /* Set ECP mode */ 951 ecr |= ATPPC_ECR_ECP; 952 chipset_mode = ATPPC_MODE_ECP; 953 break; 954 955 case PPBUS_EPP: 956 /* Set EPP mode */ 957 if (atppc->sc_has & ATPPC_HAS_EPP) { 958 ecr |= ATPPC_ECR_EPP; 959 chipset_mode = ATPPC_MODE_EPP; 960 } else { 961 rval = ENODEV; 962 goto end; 963 } 964 break; 965 966 case PPBUS_FAST: 967 /* Set fast centronics mode */ 968 ecr |= ATPPC_ECR_FIFO; 969 chipset_mode = ATPPC_MODE_FAST; 970 break; 971 972 case PPBUS_PS2: 973 /* Set PS2 mode */ 974 ecr |= ATPPC_ECR_PS2; 975 chipset_mode = ATPPC_MODE_PS2; 976 break; 977 978 case PPBUS_COMPATIBLE: 979 /* Set standard mode */ 980 ecr |= ATPPC_ECR_STD; 981 chipset_mode = ATPPC_MODE_STD;; 982 break; 983 984 case PPBUS_NIBBLE: 985 /* Set nibble mode: uses chipset standard mode */ 986 ecr |= ATPPC_ECR_STD; 987 chipset_mode = ATPPC_MODE_NIBBLE; 988 break; 989 990 default: 991 /* Invalid mode specified for ECP chip */ 992 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 993 "argument.\n", __func__, dev->dv_xname)); 994 rval = ENODEV; 995 goto end; 996 } 997 998 /* Switch to byte mode to be able to change modes. */ 999 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1000 atppc_barrier_w(atppc); 1001 1002 /* Update mode */ 1003 atppc_w_ecr(atppc, ecr); 1004 atppc_barrier_w(atppc); 1005 } else { 1006 switch (mode) { 1007 case PPBUS_EPP: 1008 if (atppc->sc_has & ATPPC_HAS_EPP) { 1009 chipset_mode = ATPPC_MODE_EPP; 1010 } else { 1011 rval = ENODEV; 1012 goto end; 1013 } 1014 break; 1015 1016 case PPBUS_PS2: 1017 if (atppc->sc_has & ATPPC_HAS_PS2) { 1018 chipset_mode = ATPPC_MODE_PS2; 1019 } else { 1020 rval = ENODEV; 1021 goto end; 1022 } 1023 break; 1024 1025 case PPBUS_NIBBLE: 1026 /* Set nibble mode (virtual) */ 1027 chipset_mode = ATPPC_MODE_NIBBLE; 1028 break; 1029 1030 case PPBUS_COMPATIBLE: 1031 chipset_mode = ATPPC_MODE_STD; 1032 break; 1033 1034 case PPBUS_ECP: 1035 rval = ENODEV; 1036 goto end; 1037 1038 default: 1039 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1040 "argument.\n", __func__, dev->dv_xname)); 1041 rval = ENODEV; 1042 goto end; 1043 } 1044 } 1045 1046 atppc->sc_mode = chipset_mode; 1047 if (chipset_mode == ATPPC_MODE_PS2) { 1048 /* Set direction bit to reverse */ 1049 ecr = atppc_r_ctr(atppc); 1050 atppc_barrier_r(atppc); 1051 ecr |= PCD; 1052 atppc_w_ctr(atppc, ecr); 1053 atppc_barrier_w(atppc); 1054 } 1055 1056 end: 1057 ATPPC_UNLOCK(atppc); 1058 splx(s); 1059 1060 return rval; 1061 } 1062 1063 /* Get the current mode of chipset */ 1064 static int 1065 atppc_getmode(struct device *dev) 1066 { 1067 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1068 int mode; 1069 int s; 1070 1071 s = splatppc(); 1072 ATPPC_LOCK(atppc); 1073 1074 /* The chipset can only be in one mode at a time logically */ 1075 switch (atppc->sc_mode) { 1076 case ATPPC_MODE_ECP: 1077 mode = PPBUS_ECP; 1078 break; 1079 1080 case ATPPC_MODE_EPP: 1081 mode = PPBUS_EPP; 1082 break; 1083 1084 case ATPPC_MODE_PS2: 1085 mode = PPBUS_PS2; 1086 break; 1087 1088 case ATPPC_MODE_STD: 1089 mode = PPBUS_COMPATIBLE; 1090 break; 1091 1092 case ATPPC_MODE_NIBBLE: 1093 mode = PPBUS_NIBBLE; 1094 break; 1095 1096 case ATPPC_MODE_FAST: 1097 mode = PPBUS_FAST; 1098 break; 1099 1100 default: 1101 panic("%s(%s): device is in invalid mode!", __func__, 1102 dev->dv_xname); 1103 break; 1104 } 1105 1106 ATPPC_UNLOCK(atppc); 1107 splx(s); 1108 1109 return mode; 1110 } 1111 1112 1113 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1114 static void 1115 atppc_ecp_sync(struct device *dev) 1116 { 1117 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1118 int i; 1119 int s; 1120 u_int8_t r; 1121 1122 s = splatppc(); 1123 ATPPC_LOCK(atppc); 1124 1125 /* 1126 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1127 * the mode is either ECP or Fast Centronics. 1128 */ 1129 r = atppc_r_ecr(atppc); 1130 atppc_barrier_r(atppc); 1131 r &= 0xe0; 1132 if (!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1133 && (r != ATPPC_ECR_FIFO))) { 1134 goto end; 1135 } 1136 1137 /* Wait for FIFO to empty */ 1138 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1139 r = atppc_r_ecr(atppc); 1140 atppc_barrier_r(atppc); 1141 if (r & ATPPC_FIFO_EMPTY) { 1142 goto end; 1143 } 1144 delay(100); /* Supposed to be a 100 usec delay */ 1145 } 1146 1147 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1148 dev->dv_xname)); 1149 1150 end: 1151 ATPPC_UNLOCK(atppc); 1152 splx(s); 1153 1154 return; 1155 } 1156 1157 /* Execute a microsequence to handle fast I/O operations. */ 1158 static int 1159 atppc_exec_microseq(struct device *dev, struct ppbus_microseq **p_msq) 1160 { 1161 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1162 struct ppbus_microseq *mi = *p_msq; 1163 char cc, *p; 1164 int i, iter, len; 1165 int error; 1166 int s; 1167 register int reg; 1168 register unsigned char mask; 1169 register int accum = 0; 1170 register char *ptr = NULL; 1171 struct ppbus_microseq *stack = NULL; 1172 1173 s = splatppc(); 1174 ATPPC_LOCK(atppc); 1175 1176 /* microsequence registers are equivalent to PC-like port registers */ 1177 1178 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1179 (atppc)->sc_ioh, (register)) 1180 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1181 (atppc)->sc_ioh, (register), (byte)) 1182 1183 /* Loop until microsequence execution finishes (ending op code) */ 1184 for (;;) { 1185 switch (mi->opcode) { 1186 case MS_OP_RSET: 1187 cc = r_reg(mi->arg[0].i, atppc); 1188 atppc_barrier_r(atppc); 1189 cc &= (char)mi->arg[2].i; /* clear mask */ 1190 cc |= (char)mi->arg[1].i; /* assert mask */ 1191 w_reg(mi->arg[0].i, atppc, cc); 1192 atppc_barrier_w(atppc); 1193 mi++; 1194 break; 1195 1196 case MS_OP_RASSERT_P: 1197 reg = mi->arg[1].i; 1198 ptr = atppc->sc_ptr; 1199 1200 if ((len = mi->arg[0].i) == MS_ACCUM) { 1201 accum = atppc->sc_accum; 1202 for (; accum; accum--) { 1203 w_reg(reg, atppc, *ptr++); 1204 atppc_barrier_w(atppc); 1205 } 1206 atppc->sc_accum = accum; 1207 } else { 1208 for (i = 0; i < len; i++) { 1209 w_reg(reg, atppc, *ptr++); 1210 atppc_barrier_w(atppc); 1211 } 1212 } 1213 1214 atppc->sc_ptr = ptr; 1215 mi++; 1216 break; 1217 1218 case MS_OP_RFETCH_P: 1219 reg = mi->arg[1].i; 1220 mask = (char)mi->arg[2].i; 1221 ptr = atppc->sc_ptr; 1222 1223 if ((len = mi->arg[0].i) == MS_ACCUM) { 1224 accum = atppc->sc_accum; 1225 for (; accum; accum--) { 1226 *ptr++ = r_reg(reg, atppc) & mask; 1227 atppc_barrier_r(atppc); 1228 } 1229 atppc->sc_accum = accum; 1230 } else { 1231 for (i = 0; i < len; i++) { 1232 *ptr++ = r_reg(reg, atppc) & mask; 1233 atppc_barrier_r(atppc); 1234 } 1235 } 1236 1237 atppc->sc_ptr = ptr; 1238 mi++; 1239 break; 1240 1241 case MS_OP_RFETCH: 1242 *((char *)mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1243 (char)mi->arg[1].i; 1244 atppc_barrier_r(atppc); 1245 mi++; 1246 break; 1247 1248 case MS_OP_RASSERT: 1249 case MS_OP_DELAY: 1250 /* let's suppose the next instr. is the same */ 1251 do { 1252 for (;mi->opcode == MS_OP_RASSERT; mi++) { 1253 w_reg(mi->arg[0].i, atppc, 1254 (char)mi->arg[1].i); 1255 atppc_barrier_w(atppc); 1256 } 1257 1258 for (;mi->opcode == MS_OP_DELAY; mi++) { 1259 delay(mi->arg[0].i); 1260 } 1261 } while (mi->opcode == MS_OP_RASSERT); 1262 break; 1263 1264 case MS_OP_ADELAY: 1265 if (mi->arg[0].i) { 1266 tsleep(atppc, PPBUSPRI, "atppcdelay", 1267 mi->arg[0].i * (hz/1000)); 1268 } 1269 mi++; 1270 break; 1271 1272 case MS_OP_TRIG: 1273 reg = mi->arg[0].i; 1274 iter = mi->arg[1].i; 1275 p = (char *)mi->arg[2].p; 1276 1277 /* XXX delay limited to 255 us */ 1278 for (i = 0; i < iter; i++) { 1279 w_reg(reg, atppc, *p++); 1280 atppc_barrier_w(atppc); 1281 delay((unsigned char)*p++); 1282 } 1283 1284 mi++; 1285 break; 1286 1287 case MS_OP_SET: 1288 atppc->sc_accum = mi->arg[0].i; 1289 mi++; 1290 break; 1291 1292 case MS_OP_DBRA: 1293 if (--atppc->sc_accum > 0) { 1294 mi += mi->arg[0].i; 1295 } 1296 1297 mi++; 1298 break; 1299 1300 case MS_OP_BRSET: 1301 cc = atppc_r_str(atppc); 1302 atppc_barrier_r(atppc); 1303 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1304 mi += mi->arg[1].i; 1305 } 1306 mi++; 1307 break; 1308 1309 case MS_OP_BRCLEAR: 1310 cc = atppc_r_str(atppc); 1311 atppc_barrier_r(atppc); 1312 if ((cc & (char)mi->arg[0].i) == 0) { 1313 mi += mi->arg[1].i; 1314 } 1315 mi++; 1316 break; 1317 1318 case MS_OP_BRSTAT: 1319 cc = atppc_r_str(atppc); 1320 atppc_barrier_r(atppc); 1321 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1322 (char)mi->arg[0].i) { 1323 mi += mi->arg[2].i; 1324 } 1325 mi++; 1326 break; 1327 1328 case MS_OP_C_CALL: 1329 /* 1330 * If the C call returns !0 then end the microseq. 1331 * The current state of ptr is passed to the C function 1332 */ 1333 if ((error = mi->arg[0].f(mi->arg[1].p, 1334 atppc->sc_ptr))) { 1335 ATPPC_UNLOCK(atppc); 1336 splx(s); 1337 return (error); 1338 } 1339 mi++; 1340 break; 1341 1342 case MS_OP_PTR: 1343 atppc->sc_ptr = (char *)mi->arg[0].p; 1344 mi++; 1345 break; 1346 1347 case MS_OP_CALL: 1348 if (stack) { 1349 panic("%s - %s: too much calls", dev->dv_xname, 1350 __func__); 1351 } 1352 1353 if (mi->arg[0].p) { 1354 /* store state of the actual microsequence */ 1355 stack = mi; 1356 1357 /* jump to the new microsequence */ 1358 mi = (struct ppbus_microseq *)mi->arg[0].p; 1359 } else { 1360 mi++; 1361 } 1362 break; 1363 1364 case MS_OP_SUBRET: 1365 /* retrieve microseq and pc state before the call */ 1366 mi = stack; 1367 1368 /* reset the stack */ 1369 stack = 0; 1370 1371 /* XXX return code */ 1372 1373 mi++; 1374 break; 1375 1376 case MS_OP_PUT: 1377 case MS_OP_GET: 1378 case MS_OP_RET: 1379 /* 1380 * Can't return to atppc level during the execution 1381 * of a submicrosequence. 1382 */ 1383 if (stack) { 1384 panic("%s: cannot return to atppc level", 1385 __func__); 1386 } 1387 /* update pc for atppc level of execution */ 1388 *p_msq = mi; 1389 1390 ATPPC_UNLOCK(atppc); 1391 splx(s); 1392 return (0); 1393 break; 1394 1395 default: 1396 panic("%s: unknown microsequence " 1397 "opcode 0x%x", __func__, mi->opcode); 1398 break; 1399 } 1400 } 1401 1402 /* Should not be reached! */ 1403 #ifdef ATPPC_DEBUG 1404 panic("%s: unexpected code reached!\n", __func__); 1405 #endif 1406 } 1407 1408 /* General I/O routine */ 1409 static u_int8_t 1410 atppc_io(struct device *dev, int iop, u_char *addr, int cnt, u_char byte) 1411 { 1412 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1413 u_int8_t val = 0; 1414 int s; 1415 1416 s = splatppc(); 1417 ATPPC_LOCK(atppc); 1418 1419 switch (iop) { 1420 case PPBUS_OUTSB_EPP: 1421 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1422 ATPPC_EPP_DATA, addr, cnt); 1423 break; 1424 case PPBUS_OUTSW_EPP: 1425 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1426 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1427 break; 1428 case PPBUS_OUTSL_EPP: 1429 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1430 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1431 break; 1432 case PPBUS_INSB_EPP: 1433 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1434 ATPPC_EPP_DATA, addr, cnt); 1435 break; 1436 case PPBUS_INSW_EPP: 1437 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1438 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1439 break; 1440 case PPBUS_INSL_EPP: 1441 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1442 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1443 break; 1444 case PPBUS_RDTR: 1445 val = (atppc_r_dtr(atppc)); 1446 break; 1447 case PPBUS_RSTR: 1448 val = (atppc_r_str(atppc)); 1449 break; 1450 case PPBUS_RCTR: 1451 val = (atppc_r_ctr(atppc)); 1452 break; 1453 case PPBUS_REPP_A: 1454 val = (atppc_r_eppA(atppc)); 1455 break; 1456 case PPBUS_REPP_D: 1457 val = (atppc_r_eppD(atppc)); 1458 break; 1459 case PPBUS_RECR: 1460 val = (atppc_r_ecr(atppc)); 1461 break; 1462 case PPBUS_RFIFO: 1463 val = (atppc_r_fifo(atppc)); 1464 break; 1465 case PPBUS_WDTR: 1466 atppc_w_dtr(atppc, byte); 1467 break; 1468 case PPBUS_WSTR: 1469 atppc_w_str(atppc, byte); 1470 break; 1471 case PPBUS_WCTR: 1472 atppc_w_ctr(atppc, byte); 1473 break; 1474 case PPBUS_WEPP_A: 1475 atppc_w_eppA(atppc, byte); 1476 break; 1477 case PPBUS_WEPP_D: 1478 atppc_w_eppD(atppc, byte); 1479 break; 1480 case PPBUS_WECR: 1481 atppc_w_ecr(atppc, byte); 1482 break; 1483 case PPBUS_WFIFO: 1484 atppc_w_fifo(atppc, byte); 1485 break; 1486 default: 1487 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1488 __func__); 1489 break; 1490 } 1491 1492 atppc_barrier(atppc); 1493 1494 ATPPC_UNLOCK(atppc); 1495 splx(s); 1496 1497 return val; 1498 } 1499 1500 /* Read "instance variables" of atppc device */ 1501 static int 1502 atppc_read_ivar(struct device *dev, int index, unsigned int *val) 1503 { 1504 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1505 int rval = 0; 1506 int s; 1507 1508 s = splatppc(); 1509 ATPPC_LOCK(atppc); 1510 1511 switch(index) { 1512 case PPBUS_IVAR_EPP_PROTO: 1513 if (atppc->sc_epp == ATPPC_EPP_1_9) 1514 *val = PPBUS_EPP_1_9; 1515 else if (atppc->sc_epp == ATPPC_EPP_1_7) 1516 *val = PPBUS_EPP_1_7; 1517 /* XXX what if not using EPP ? */ 1518 break; 1519 1520 case PPBUS_IVAR_INTR: 1521 *val = ((atppc->sc_use & ATPPC_USE_INTR) != 0); 1522 break; 1523 1524 case PPBUS_IVAR_DMA: 1525 *val = ((atppc->sc_use & ATPPC_USE_DMA) != 0); 1526 break; 1527 1528 default: 1529 rval = ENODEV; 1530 } 1531 1532 ATPPC_UNLOCK(atppc); 1533 splx(s); 1534 1535 return rval; 1536 } 1537 1538 /* Write "instance varaibles" of atppc device */ 1539 static int 1540 atppc_write_ivar(struct device *dev, int index, unsigned int *val) 1541 { 1542 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1543 int rval = 0; 1544 int s; 1545 1546 s = splatppc(); 1547 ATPPC_LOCK(atppc); 1548 1549 switch(index) { 1550 case PPBUS_IVAR_EPP_PROTO: 1551 if (*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1552 atppc->sc_epp = *val; 1553 else 1554 rval = EINVAL; 1555 break; 1556 1557 case PPBUS_IVAR_INTR: 1558 if (*val == 0) 1559 atppc->sc_use &= ~ATPPC_USE_INTR; 1560 else if (atppc->sc_has & ATPPC_HAS_INTR) 1561 atppc->sc_use |= ATPPC_USE_INTR; 1562 else 1563 rval = ENODEV; 1564 break; 1565 1566 case PPBUS_IVAR_DMA: 1567 if (*val == 0) 1568 atppc->sc_use &= ~ATPPC_USE_DMA; 1569 else if (atppc->sc_has & ATPPC_HAS_DMA) 1570 atppc->sc_use |= ATPPC_USE_DMA; 1571 else 1572 rval = ENODEV; 1573 break; 1574 1575 default: 1576 rval = ENODEV; 1577 } 1578 1579 ATPPC_UNLOCK(atppc); 1580 splx(s); 1581 1582 return rval; 1583 } 1584 1585 /* Add a handler routine to be called by the interrupt handler */ 1586 static int 1587 atppc_add_handler(struct device *dev, void (*handler)(void *), void *arg) 1588 { 1589 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1590 struct atppc_handler_node *callback; 1591 int rval = 0; 1592 int s; 1593 1594 s = splatppc(); 1595 ATPPC_LOCK(atppc); 1596 1597 if (handler == NULL) { 1598 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1599 __func__, dev->dv_xname)); 1600 rval = EINVAL; 1601 } else { 1602 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1603 M_NOWAIT); 1604 if (callback) { 1605 callback->func = handler; 1606 callback->arg = arg; 1607 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1608 callback, entries); 1609 } else { 1610 rval = ENOMEM; 1611 } 1612 } 1613 1614 ATPPC_UNLOCK(atppc); 1615 splx(s); 1616 1617 return rval; 1618 } 1619 1620 /* Remove a handler added by atppc_add_handler() */ 1621 static int 1622 atppc_remove_handler(struct device *dev, void (*handler)(void *)) 1623 { 1624 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1625 struct atppc_handler_node *callback; 1626 int rval = EINVAL; 1627 int s; 1628 1629 s = splatppc(); 1630 ATPPC_LOCK(atppc); 1631 1632 if (SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1633 panic("%s(%s): attempt to remove handler from empty list.\n", 1634 __func__, dev->dv_xname); 1635 1636 /* Search list for handler */ 1637 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1638 if (callback->func == handler) { 1639 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1640 atppc_handler_node, entries); 1641 free(callback, M_DEVBUF); 1642 rval = 0; 1643 break; 1644 } 1645 } 1646 1647 ATPPC_UNLOCK(atppc); 1648 splx(s); 1649 1650 return rval; 1651 } 1652 1653 /* Utility functions */ 1654 1655 1656 /* 1657 * Functions that read bytes from port into buffer: called from interrupt 1658 * handler depending on current chipset mode and cause of interrupt. Return 1659 * value: number of bytes moved. 1660 */ 1661 1662 /* Only the lower 4 bits of the final value are valid */ 1663 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1664 1665 /* Read bytes in nibble mode */ 1666 static void 1667 atppc_nibble_read(struct atppc_softc *atppc) 1668 { 1669 int i; 1670 u_int8_t nibble[2]; 1671 u_int8_t ctr; 1672 u_int8_t str; 1673 1674 /* Enable interrupts if needed */ 1675 if (atppc->sc_use & ATPPC_USE_INTR) { 1676 ctr = atppc_r_ctr(atppc); 1677 atppc_barrier_r(atppc); 1678 if (!(ctr & IRQENABLE)) { 1679 ctr |= IRQENABLE; 1680 atppc_w_ctr(atppc, ctr); 1681 atppc_barrier_w(atppc); 1682 } 1683 } 1684 1685 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1686 /* Check if device has data to send in idle phase */ 1687 str = atppc_r_str(atppc); 1688 atppc_barrier_r(atppc); 1689 if (str & nDATAVAIL) { 1690 return; 1691 } 1692 1693 /* Nibble-mode handshake transfer */ 1694 for (i = 0; i < 2; i++) { 1695 /* Event 7 - ready to take data (HOSTBUSY low) */ 1696 ctr = atppc_r_ctr(atppc); 1697 atppc_barrier_r(atppc); 1698 ctr |= HOSTBUSY; 1699 atppc_w_ctr(atppc, ctr); 1700 atppc_barrier_w(atppc); 1701 1702 /* Event 8 - peripheral writes the first nibble */ 1703 1704 /* Event 9 - peripheral set nAck low */ 1705 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1706 if (atppc->sc_inerr) 1707 return; 1708 1709 /* read nibble */ 1710 nibble[i] = atppc_r_str(atppc); 1711 1712 /* Event 10 - ack, nibble received */ 1713 ctr &= ~HOSTBUSY; 1714 atppc_w_ctr(atppc, ctr); 1715 1716 /* Event 11 - wait ack from peripherial */ 1717 if (atppc->sc_use & ATPPC_USE_INTR) 1718 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1719 atppc->sc_inb, ATPPC_IRQ_nACK); 1720 else 1721 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1722 PTRCLK); 1723 if (atppc->sc_inerr) 1724 return; 1725 } 1726 1727 /* Store byte transfered */ 1728 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1729 (nibble2char(nibble[0]) & 0x0f); 1730 atppc->sc_inbstart++; 1731 } 1732 } 1733 1734 /* Read bytes in bidirectional mode */ 1735 static void 1736 atppc_byte_read(struct atppc_softc * const atppc) 1737 { 1738 u_int8_t ctr; 1739 u_int8_t str; 1740 1741 /* Check direction bit */ 1742 ctr = atppc_r_ctr(atppc); 1743 atppc_barrier_r(atppc); 1744 if (!(ctr & PCD)) { 1745 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1746 "bit set.", atppc->sc_dev.dv_xname)); 1747 atppc->sc_inerr = ENODEV; 1748 return; 1749 } 1750 /* Enable interrupts if needed */ 1751 if (atppc->sc_use & ATPPC_USE_INTR) { 1752 if (!(ctr & IRQENABLE)) { 1753 ctr |= IRQENABLE; 1754 atppc_w_ctr(atppc, ctr); 1755 atppc_barrier_w(atppc); 1756 } 1757 } 1758 1759 /* Byte-mode handshake transfer */ 1760 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1761 /* Check if device has data to send */ 1762 str = atppc_r_str(atppc); 1763 atppc_barrier_r(atppc); 1764 if (str & nDATAVAIL) { 1765 return; 1766 } 1767 1768 /* Event 7 - ready to take data (nAUTO low) */ 1769 ctr |= HOSTBUSY; 1770 atppc_w_ctr(atppc, ctr); 1771 atppc_barrier_w(atppc); 1772 1773 /* Event 9 - peripheral set nAck low */ 1774 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1775 if (atppc->sc_inerr) 1776 return; 1777 1778 /* Store byte transfered */ 1779 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1780 atppc_barrier_r(atppc); 1781 1782 /* Event 10 - data received, can't accept more */ 1783 ctr &= ~HOSTBUSY; 1784 atppc_w_ctr(atppc, ctr); 1785 atppc_barrier_w(atppc); 1786 1787 /* Event 11 - peripheral ack */ 1788 if (atppc->sc_use & ATPPC_USE_INTR) 1789 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1790 atppc->sc_inb, ATPPC_IRQ_nACK); 1791 else 1792 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1793 if (atppc->sc_inerr) 1794 return; 1795 1796 /* Event 16 - strobe */ 1797 str |= HOSTCLK; 1798 atppc_w_str(atppc, str); 1799 atppc_barrier_w(atppc); 1800 DELAY(1); 1801 str &= ~HOSTCLK; 1802 atppc_w_str(atppc, str); 1803 atppc_barrier_w(atppc); 1804 1805 /* Update counter */ 1806 atppc->sc_inbstart++; 1807 } 1808 } 1809 1810 /* Read bytes in EPP mode */ 1811 static void 1812 atppc_epp_read(struct atppc_softc * atppc) 1813 { 1814 if (atppc->sc_epp == ATPPC_EPP_1_9) { 1815 { 1816 uint8_t str; 1817 int i; 1818 1819 atppc_reset_epp_timeout((struct device *)atppc); 1820 for (i = 0; i < atppc->sc_inb_nbytes; i++) { 1821 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1822 atppc_barrier_r(atppc); 1823 str = atppc_r_str(atppc); 1824 atppc_barrier_r(atppc); 1825 if (str & TIMEOUT) { 1826 atppc->sc_inerr = EIO; 1827 break; 1828 } 1829 atppc->sc_inbstart++; 1830 } 1831 } 1832 } else { 1833 /* Read data block from EPP data register */ 1834 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1835 atppc->sc_inb_nbytes); 1836 atppc_barrier_r(atppc); 1837 /* Update buffer position, byte count and counter */ 1838 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1839 } 1840 1841 return; 1842 } 1843 1844 /* Read bytes in ECP mode */ 1845 static void 1846 atppc_ecp_read(struct atppc_softc *atppc) 1847 { 1848 u_int8_t ecr; 1849 u_int8_t ctr; 1850 u_int8_t str; 1851 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1852 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1853 unsigned int worklen; 1854 1855 /* Check direction bit */ 1856 ctr = ctr_sav; 1857 atppc_barrier_r(atppc); 1858 if (!(ctr & PCD)) { 1859 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1860 "bit set.", atppc->sc_dev.dv_xname)); 1861 atppc->sc_inerr = ENODEV; 1862 goto end; 1863 } 1864 1865 /* Clear device request if any */ 1866 if (atppc->sc_use & ATPPC_USE_INTR) 1867 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1868 1869 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1870 ecr = atppc_r_ecr(atppc); 1871 atppc_barrier_r(atppc); 1872 if (ecr & ATPPC_FIFO_EMPTY) { 1873 /* Check for invalid state */ 1874 if (ecr & ATPPC_FIFO_FULL) { 1875 atppc_ecp_read_error(atppc, worklen); 1876 break; 1877 } 1878 1879 /* Check if device has data to send */ 1880 str = atppc_r_str(atppc); 1881 atppc_barrier_r(atppc); 1882 if (str & nDATAVAIL) { 1883 break; 1884 } 1885 1886 if (atppc->sc_use & ATPPC_USE_INTR) { 1887 /* Enable interrupts */ 1888 ecr &= ~ATPPC_SERVICE_INTR; 1889 atppc_w_ecr(atppc, ecr); 1890 atppc_barrier_w(atppc); 1891 /* Wait for FIFO to fill */ 1892 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1893 atppc->sc_inb, ATPPC_IRQ_FIFO); 1894 if (atppc->sc_inerr) 1895 break; 1896 } else { 1897 DELAY(1); 1898 } 1899 continue; 1900 } 1901 else if (ecr & ATPPC_FIFO_FULL) { 1902 /* Transfer sc_fifo bytes */ 1903 worklen = atppc->sc_fifo; 1904 } 1905 else if (ecr & ATPPC_SERVICE_INTR) { 1906 /* Transfer sc_rthr bytes */ 1907 worklen = atppc->sc_rthr; 1908 } else { 1909 /* At least one byte is in the FIFO */ 1910 worklen = 1; 1911 } 1912 1913 if ((atppc->sc_use & ATPPC_USE_INTR) && 1914 (atppc->sc_use & ATPPC_USE_DMA)) { 1915 1916 atppc_ecp_read_dma(atppc, &worklen, ecr); 1917 } else { 1918 atppc_ecp_read_pio(atppc, &worklen, ecr); 1919 } 1920 1921 if (atppc->sc_inerr) { 1922 atppc_ecp_read_error(atppc, worklen); 1923 break; 1924 } 1925 1926 /* Update counter */ 1927 atppc->sc_inbstart += worklen; 1928 } 1929 end: 1930 atppc_w_ctr(atppc, ctr_sav); 1931 atppc_w_ecr(atppc, ecr_sav); 1932 atppc_barrier_w(atppc); 1933 } 1934 1935 /* Read bytes in ECP mode using DMA transfers */ 1936 static void 1937 atppc_ecp_read_dma(struct atppc_softc *atppc, unsigned int *length, 1938 unsigned char ecr) 1939 { 1940 /* Limit transfer to maximum DMA size and start it */ 1941 *length = min(*length, atppc->sc_dma_maxsize); 1942 atppc->sc_dmastat = ATPPC_DMA_INIT; 1943 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1944 ATPPC_DMA_MODE_READ); 1945 1946 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1947 1948 /* Enable interrupts, DMA */ 1949 ecr &= ~ATPPC_SERVICE_INTR; 1950 ecr |= ATPPC_ENABLE_DMA; 1951 atppc_w_ecr(atppc, ecr); 1952 atppc_barrier_w(atppc); 1953 1954 /* Wait for DMA completion */ 1955 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1956 ATPPC_IRQ_DMA); 1957 if (atppc->sc_inerr) 1958 return; 1959 1960 /* Get register value recorded by interrupt handler */ 1961 ecr = atppc->sc_ecr_intr; 1962 /* Clear DMA programming */ 1963 atppc->sc_dma_finish(atppc); 1964 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1965 /* Disable DMA */ 1966 ecr &= ~ATPPC_ENABLE_DMA; 1967 atppc_w_ecr(atppc, ecr); 1968 atppc_barrier_w(atppc); 1969 } 1970 1971 /* Read bytes in ECP mode using PIO transfers */ 1972 static void 1973 atppc_ecp_read_pio(struct atppc_softc *atppc, unsigned int *length, 1974 unsigned char ecr) 1975 { 1976 /* Disable DMA */ 1977 ecr &= ~ATPPC_ENABLE_DMA; 1978 atppc_w_ecr(atppc, ecr); 1979 atppc_barrier_w(atppc); 1980 1981 /* Read from FIFO */ 1982 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 1983 } 1984 1985 /* Handle errors for ECP reads */ 1986 static void 1987 atppc_ecp_read_error(struct atppc_softc *atppc, const unsigned int worklen) 1988 { 1989 unsigned char ecr = atppc_r_ecr(atppc); 1990 1991 /* Abort DMA if not finished */ 1992 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 1993 atppc->sc_dma_abort(atppc); 1994 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 1995 } 1996 1997 /* Check for invalid states */ 1998 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 1999 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2000 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2001 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2002 atppc_barrier_w(atppc); 2003 } 2004 } 2005 2006 /* 2007 * Functions that write bytes to port from buffer: called from atppc_write() 2008 * function depending on current chipset mode. Returns number of bytes moved. 2009 */ 2010 2011 /* Write bytes in std/bidirectional mode */ 2012 static void 2013 atppc_std_write(struct atppc_softc * const atppc) 2014 { 2015 unsigned int timecount; 2016 unsigned char ctr; 2017 2018 ctr = atppc_r_ctr(atppc); 2019 atppc_barrier_r(atppc); 2020 /* Enable interrupts if needed */ 2021 if (atppc->sc_use & ATPPC_USE_INTR) { 2022 if (!(ctr & IRQENABLE)) { 2023 ctr |= IRQENABLE; 2024 atppc_w_ctr(atppc, ctr); 2025 atppc_barrier_w(atppc); 2026 } 2027 } 2028 2029 while (atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2030 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2031 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2032 if (atppc->sc_outerr) 2033 return; 2034 2035 /* Put data in data register */ 2036 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2037 atppc_barrier_w(atppc); 2038 DELAY(1); 2039 2040 /* Pulse strobe to indicate valid data on lines */ 2041 ctr |= STROBE; 2042 atppc_w_ctr(atppc, ctr); 2043 atppc_barrier_w(atppc); 2044 DELAY(1); 2045 ctr &= ~STROBE; 2046 atppc_w_ctr(atppc, ctr); 2047 atppc_barrier_w(atppc); 2048 2049 /* Wait for nACK for MAXBUSYWAIT */ 2050 timecount = 0; 2051 if (atppc->sc_use & ATPPC_USE_INTR) { 2052 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2053 atppc->sc_outb, ATPPC_IRQ_nACK); 2054 if (atppc->sc_outerr) 2055 return; 2056 } else { 2057 /* Try to catch the pulsed acknowledgement */ 2058 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2059 if (atppc->sc_outerr) 2060 return; 2061 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2062 if (atppc->sc_outerr) 2063 return; 2064 } 2065 2066 /* Update buffer position, byte count and counter */ 2067 atppc->sc_outbstart++; 2068 } 2069 } 2070 2071 2072 /* Write bytes in EPP mode */ 2073 static void 2074 atppc_epp_write(struct atppc_softc *atppc) 2075 { 2076 if (atppc->sc_epp == ATPPC_EPP_1_9) { 2077 { 2078 uint8_t str; 2079 int i; 2080 2081 atppc_reset_epp_timeout((struct device *)atppc); 2082 for (i = 0; i < atppc->sc_outb_nbytes; i++) { 2083 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2084 atppc_barrier_w(atppc); 2085 str = atppc_r_str(atppc); 2086 atppc_barrier_r(atppc); 2087 if (str & TIMEOUT) { 2088 atppc->sc_outerr = EIO; 2089 break; 2090 } 2091 atppc->sc_outbstart++; 2092 } 2093 } 2094 } else { 2095 /* Write data block to EPP data register */ 2096 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2097 atppc->sc_outb_nbytes); 2098 atppc_barrier_w(atppc); 2099 /* Update buffer position, byte count and counter */ 2100 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2101 } 2102 2103 return; 2104 } 2105 2106 2107 /* Write bytes in ECP/Fast Centronics mode */ 2108 static void 2109 atppc_fifo_write(struct atppc_softc * const atppc) 2110 { 2111 unsigned char ctr; 2112 unsigned char ecr; 2113 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2114 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2115 2116 ctr = ctr_sav; 2117 ecr = ecr_sav; 2118 atppc_barrier_r(atppc); 2119 2120 /* Reset and flush FIFO */ 2121 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2122 atppc_barrier_w(atppc); 2123 /* Disable nAck interrupts and initialize port bits */ 2124 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2125 atppc_w_ctr(atppc, ctr); 2126 atppc_barrier_w(atppc); 2127 /* Restore mode */ 2128 atppc_w_ecr(atppc, ecr); 2129 atppc_barrier_w(atppc); 2130 2131 /* DMA or Programmed IO */ 2132 if ((atppc->sc_use & ATPPC_USE_DMA) && 2133 (atppc->sc_use & ATPPC_USE_INTR)) { 2134 2135 atppc_fifo_write_dma(atppc, ecr, ctr); 2136 } else { 2137 atppc_fifo_write_pio(atppc, ecr, ctr); 2138 } 2139 2140 /* Restore original register values */ 2141 atppc_w_ctr(atppc, ctr_sav); 2142 atppc_w_ecr(atppc, ecr_sav); 2143 atppc_barrier_w(atppc); 2144 } 2145 2146 static void 2147 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2148 unsigned char ctr) 2149 { 2150 unsigned int len; 2151 unsigned int worklen; 2152 2153 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2154 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2155 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2156 2157 /* Wait for device to become ready */ 2158 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2159 if (atppc->sc_outerr) 2160 return; 2161 2162 /* Reset chipset for next DMA transfer */ 2163 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2164 atppc_barrier_w(atppc); 2165 atppc_w_ecr(atppc, ecr); 2166 atppc_barrier_w(atppc); 2167 2168 /* Limit transfer to maximum DMA size and start it */ 2169 worklen = min(len, atppc->sc_dma_maxsize); 2170 atppc->sc_dmastat = ATPPC_DMA_INIT; 2171 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2172 worklen, ATPPC_DMA_MODE_WRITE); 2173 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2174 2175 /* Enable interrupts, DMA */ 2176 ecr &= ~ATPPC_SERVICE_INTR; 2177 ecr |= ATPPC_ENABLE_DMA; 2178 atppc_w_ecr(atppc, ecr); 2179 atppc_barrier_w(atppc); 2180 2181 /* Wait for DMA completion */ 2182 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2183 ATPPC_IRQ_DMA); 2184 if (atppc->sc_outerr) { 2185 atppc_fifo_write_error(atppc, worklen); 2186 return; 2187 } 2188 /* Get register value recorded by interrupt handler */ 2189 ecr = atppc->sc_ecr_intr; 2190 /* Clear DMA programming */ 2191 atppc->sc_dma_finish(atppc); 2192 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2193 /* Disable DMA */ 2194 ecr &= ~ATPPC_ENABLE_DMA; 2195 atppc_w_ecr(atppc, ecr); 2196 atppc_barrier_w(atppc); 2197 2198 /* Wait for FIFO to empty */ 2199 for (;;) { 2200 if (ecr & ATPPC_FIFO_EMPTY) { 2201 if (ecr & ATPPC_FIFO_FULL) { 2202 atppc->sc_outerr = EIO; 2203 atppc_fifo_write_error(atppc, worklen); 2204 return; 2205 } else { 2206 break; 2207 } 2208 } 2209 2210 /* Enable service interrupt */ 2211 ecr &= ~ATPPC_SERVICE_INTR; 2212 atppc_w_ecr(atppc, ecr); 2213 atppc_barrier_w(atppc); 2214 2215 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2216 atppc->sc_outb, ATPPC_IRQ_FIFO); 2217 if (atppc->sc_outerr) { 2218 atppc_fifo_write_error(atppc, worklen); 2219 return; 2220 } 2221 2222 /* Get register value recorded by interrupt handler */ 2223 ecr = atppc->sc_ecr_intr; 2224 } 2225 2226 /* Update pointer */ 2227 atppc->sc_outbstart += worklen; 2228 } 2229 } 2230 2231 static void 2232 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2233 unsigned char ctr) 2234 { 2235 unsigned int len; 2236 unsigned int worklen; 2237 unsigned int timecount; 2238 2239 /* Disable DMA */ 2240 ecr &= ~ATPPC_ENABLE_DMA; 2241 atppc_w_ecr(atppc, ecr); 2242 atppc_barrier_w(atppc); 2243 2244 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2245 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2246 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2247 2248 /* Wait for device to become ready */ 2249 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2250 if (atppc->sc_outerr) 2251 return; 2252 2253 /* Limit transfer to minimum of space in FIFO and buffer */ 2254 worklen = min(len, atppc->sc_fifo); 2255 2256 /* Write to FIFO */ 2257 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2258 2259 timecount = 0; 2260 if (atppc->sc_use & ATPPC_USE_INTR) { 2261 ecr = atppc_r_ecr(atppc); 2262 atppc_barrier_w(atppc); 2263 2264 /* Wait for interrupt */ 2265 for (;;) { 2266 if (ecr & ATPPC_FIFO_EMPTY) { 2267 if (ecr & ATPPC_FIFO_FULL) { 2268 atppc->sc_outerr = EIO; 2269 atppc_fifo_write_error(atppc, 2270 worklen); 2271 return; 2272 } else { 2273 break; 2274 } 2275 } 2276 2277 /* Enable service interrupt */ 2278 ecr &= ~ATPPC_SERVICE_INTR; 2279 atppc_w_ecr(atppc, ecr); 2280 atppc_barrier_w(atppc); 2281 2282 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2283 atppc->sc_outb, ATPPC_IRQ_FIFO); 2284 if (atppc->sc_outerr) { 2285 atppc_fifo_write_error(atppc, worklen); 2286 return; 2287 } 2288 2289 /* Get ECR value saved by interrupt handler */ 2290 ecr = atppc->sc_ecr_intr; 2291 } 2292 } else { 2293 for (; timecount < ((MAXBUSYWAIT/hz)*1000000); 2294 timecount++) { 2295 2296 ecr = atppc_r_ecr(atppc); 2297 atppc_barrier_r(atppc); 2298 if (ecr & ATPPC_FIFO_EMPTY) { 2299 if (ecr & ATPPC_FIFO_FULL) { 2300 atppc->sc_outerr = EIO; 2301 atppc_fifo_write_error(atppc, 2302 worklen); 2303 return; 2304 } else { 2305 break; 2306 } 2307 } 2308 DELAY(1); 2309 } 2310 2311 if (((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2312 atppc->sc_outerr = EIO; 2313 atppc_fifo_write_error(atppc, worklen); 2314 return; 2315 } 2316 } 2317 2318 /* Update pointer */ 2319 atppc->sc_outbstart += worklen; 2320 } 2321 } 2322 2323 static void 2324 atppc_fifo_write_error(struct atppc_softc * const atppc, 2325 const unsigned int worklen) 2326 { 2327 unsigned char ecr = atppc_r_ecr(atppc); 2328 2329 /* Abort DMA if not finished */ 2330 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2331 atppc->sc_dma_abort(atppc); 2332 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2333 } 2334 2335 /* Check for invalid states */ 2336 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2337 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2338 } else if (!(ecr & ATPPC_FIFO_EMPTY)) { 2339 unsigned char ctr = atppc_r_ctr(atppc); 2340 int bytes_left; 2341 int i; 2342 2343 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2344 atppc->sc_dev.dv_xname)); 2345 2346 /* Drive strobe low to stop data transfer */ 2347 ctr &= ~STROBE; 2348 atppc_w_ctr(atppc, ctr); 2349 atppc_barrier_w(atppc); 2350 2351 /* Determine how many bytes remain in FIFO */ 2352 for (i = 0; i < atppc->sc_fifo; i++) { 2353 atppc_w_fifo(atppc, (unsigned char)i); 2354 ecr = atppc_r_ecr(atppc); 2355 atppc_barrier_r(atppc); 2356 if (ecr & ATPPC_FIFO_FULL) 2357 break; 2358 } 2359 bytes_left = (atppc->sc_fifo) - (i + 1); 2360 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2361 bytes_left)); 2362 2363 /* Update counter */ 2364 atppc->sc_outbstart += (worklen - bytes_left); 2365 } else { 2366 /* Update counter */ 2367 atppc->sc_outbstart += worklen; 2368 } 2369 2370 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2371 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2372 atppc_barrier_w(atppc); 2373 } 2374 2375 /* 2376 * Poll status register using mask and status for MAXBUSYWAIT. 2377 * Returns 0 if device ready, error value otherwise. 2378 */ 2379 static int 2380 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2381 const u_int8_t mask) 2382 { 2383 unsigned int timecount; 2384 u_int8_t str; 2385 int error = EIO; 2386 2387 /* Wait for str to have status for MAXBUSYWAIT */ 2388 for (timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2389 timecount++) { 2390 2391 str = atppc_r_str(atppc); 2392 atppc_barrier_r(atppc); 2393 if ((str & mask) == status) { 2394 error = 0; 2395 break; 2396 } 2397 DELAY(1); 2398 } 2399 2400 return error; 2401 } 2402 2403 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2404 static int 2405 atppc_wait_interrupt(struct atppc_softc * const atppc, const caddr_t where, 2406 const u_int8_t irqstat) 2407 { 2408 int error = EIO; 2409 2410 atppc->sc_irqstat &= ~irqstat; 2411 2412 /* Wait for interrupt for MAXBUSYWAIT */ 2413 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2414 ATPPC_SC_LOCK(atppc)); 2415 2416 if (!(error) && (atppc->sc_irqstat & irqstat)) { 2417 atppc->sc_irqstat &= ~irqstat; 2418 error = 0; 2419 } 2420 2421 return error; 2422 } 2423
Indexes created Thu Sep 25 16:09:42 GMT 2025