atppc.c revision 1.23
1 /* $NetBSD: atppc.c,v 1.23 2007/03/04 06:01:50 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * Copyright (c) 2003, 2004 Gary Thorpe <gathorpe (at) users.sourceforge.net> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: atppc.c,v 1.23 2007/03/04 06:01:50 christos Exp $"); 35 36 #include "opt_atppc.h" 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/proc.h> 44 #include <sys/systm.h> 45 #include <sys/vnode.h> 46 #include <sys/syslog.h> 47 48 #include <machine/bus.h> 49 /*#include <machine/intr.h>*/ 50 51 #include <dev/isa/isareg.h> 52 53 #include <dev/ic/atppcreg.h> 54 #include <dev/ic/atppcvar.h> 55 56 #include <dev/ppbus/ppbus_conf.h> 57 #include <dev/ppbus/ppbus_msq.h> 58 #include <dev/ppbus/ppbus_io.h> 59 #include <dev/ppbus/ppbus_var.h> 60 61 #ifdef ATPPC_DEBUG 62 int atppc_debug = 1; 63 #endif 64 65 #ifdef ATPPC_VERBOSE 66 int atppc_verbose = 1; 67 #endif 68 69 /* List of supported chipsets detection routines */ 70 static int (*chipset_detect[])(struct atppc_softc *) = { 71 /* XXX Add these LATER: maybe as separate devices? 72 atppc_pc873xx_detect, 73 atppc_smc37c66xgt_detect, 74 atppc_w83877f_detect, 75 atppc_smc37c935_detect, 76 */ 77 NULL 78 }; 79 80 81 /* Prototypes for functions. */ 82 83 /* Print function for config_found() */ 84 static int atppc_print(void *, const char *); 85 86 /* Detection routines */ 87 static int atppc_detect_fifo(struct atppc_softc *); 88 static int atppc_detect_chipset(struct atppc_softc *); 89 static int atppc_detect_generic(struct atppc_softc *); 90 91 /* Routines for ppbus interface (bus + device) */ 92 static int atppc_read(struct device *, char *, int, int, size_t *); 93 static int atppc_write(struct device *, char *, int, int, size_t *); 94 static int atppc_setmode(struct device *, int); 95 static int atppc_getmode(struct device *); 96 static int atppc_check_epp_timeout(struct device *); 97 static void atppc_reset_epp_timeout(struct device *); 98 static void atppc_ecp_sync(struct device *); 99 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 100 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 101 static int atppc_read_ivar(struct device *, int, unsigned int *); 102 static int atppc_write_ivar(struct device *, int, unsigned int *); 103 static int atppc_add_handler(struct device *, void (*)(void *), void *); 104 static int atppc_remove_handler(struct device *, void (*)(void *)); 105 106 /* Utility functions */ 107 108 /* Functions to read bytes into device's input buffer */ 109 static void atppc_nibble_read(struct atppc_softc * const); 110 static void atppc_byte_read(struct atppc_softc * const); 111 static void atppc_epp_read(struct atppc_softc * const); 112 static void atppc_ecp_read(struct atppc_softc * const); 113 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 114 unsigned char); 115 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 116 unsigned char); 117 static void atppc_ecp_read_error(struct atppc_softc *); 118 119 120 /* Functions to write bytes to device's output buffer */ 121 static void atppc_std_write(struct atppc_softc * const); 122 static void atppc_epp_write(struct atppc_softc * const); 123 static void atppc_fifo_write(struct atppc_softc * const); 124 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 125 unsigned char); 126 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 127 unsigned char); 128 static void atppc_fifo_write_error(struct atppc_softc * const, 129 const unsigned int); 130 131 /* Miscellaneous */ 132 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 133 const u_int8_t); 134 static int atppc_wait_interrupt(struct atppc_softc * const, const void *, 135 const u_int8_t); 136 137 138 /* 139 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 140 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 141 */ 142 143 /* Soft configuration attach for atppc */ 144 void 145 atppc_sc_attach(struct atppc_softc *lsc) 146 { 147 /* Adapter used to configure ppbus device */ 148 struct parport_adapter sc_parport_adapter; 149 char buf[64]; 150 151 ATPPC_LOCK_INIT(lsc); 152 153 /* Probe and set up chipset */ 154 if (atppc_detect_chipset(lsc) != 0) { 155 if (atppc_detect_generic(lsc) != 0) { 156 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 157 lsc->sc_dev.dv_xname)); 158 } 159 } 160 161 /* Probe and setup FIFO queue */ 162 if (atppc_detect_fifo(lsc) == 0) { 163 printf("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 164 lsc->sc_dev.dv_xname, lsc->sc_fifo, lsc->sc_wthr, 165 lsc->sc_rthr); 166 } 167 168 /* Print out chipset capabilities */ 169 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 170 buf, sizeof(buf)); 171 printf("%s: capabilities=%s\n", lsc->sc_dev.dv_xname, buf); 172 173 /* Initialize device's buffer pointers */ 174 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 175 = NULL; 176 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 177 178 /* Last configuration step: set mode to standard mode */ 179 if (atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 180 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 181 lsc->sc_dev.dv_xname)); 182 } 183 184 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 185 /* Initialize lock structure */ 186 simple_lock_init(&(lsc->sc_lock)); 187 #endif 188 189 /* Set up parport_adapter structure */ 190 191 /* Set capabilites */ 192 sc_parport_adapter.capabilities = 0; 193 if (lsc->sc_has & ATPPC_HAS_INTR) { 194 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 195 } 196 if (lsc->sc_has & ATPPC_HAS_DMA) { 197 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 198 } 199 if (lsc->sc_has & ATPPC_HAS_FIFO) { 200 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 201 } 202 if (lsc->sc_has & ATPPC_HAS_PS2) { 203 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 204 } 205 if (lsc->sc_has & ATPPC_HAS_EPP) { 206 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 207 } 208 if (lsc->sc_has & ATPPC_HAS_ECP) { 209 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 210 } 211 212 /* Set function pointers */ 213 sc_parport_adapter.parport_io = atppc_io; 214 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 215 sc_parport_adapter.parport_reset_epp_timeout = 216 atppc_reset_epp_timeout; 217 sc_parport_adapter.parport_setmode = atppc_setmode; 218 sc_parport_adapter.parport_getmode = atppc_getmode; 219 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 220 sc_parport_adapter.parport_read = atppc_read; 221 sc_parport_adapter.parport_write = atppc_write; 222 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 223 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 224 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 225 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 226 sc_parport_adapter.parport_add_handler = atppc_add_handler; 227 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 228 229 /* Initialize handler list, may be added to by grandchildren */ 230 SLIST_INIT(&(lsc->sc_handler_listhead)); 231 232 /* Initialize interrupt state */ 233 lsc->sc_irqstat = ATPPC_IRQ_NONE; 234 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 235 236 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 237 lsc->sc_use = 0; 238 239 /* Configure child of the device. */ 240 lsc->child = config_found(&(lsc->sc_dev), &(sc_parport_adapter), 241 atppc_print); 242 243 return; 244 } 245 246 /* Soft configuration detach */ 247 int 248 atppc_sc_detach(struct atppc_softc *lsc, int flag) 249 { 250 struct device *dev = (struct device *)lsc; 251 252 /* Detach children devices */ 253 if (config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 254 printf("%s not able to detach child device, ", dev->dv_xname); 255 256 if (!(flag & DETACH_FORCE)) { 257 printf("cannot detach\n"); 258 return 1; 259 } else { 260 printf("continuing (DETACH_FORCE)\n"); 261 } 262 } 263 264 if (!(flag & DETACH_QUIET)) 265 printf("%s detached", dev->dv_xname); 266 267 return 0; 268 } 269 270 /* Used by config_found() to print out device information */ 271 static int 272 atppc_print(void *aux, const char *name) 273 { 274 /* Print out something on failure. */ 275 if (name != NULL) { 276 printf("%s: child devices", name); 277 return UNCONF; 278 } 279 280 return QUIET; 281 } 282 283 /* 284 * Machine independent detection routines for atppc driver. 285 */ 286 287 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 288 int 289 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 290 { 291 /* 292 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() 293 * in original lpt driver. 294 * Write to data register common to all controllers and read back the 295 * values. Also tests control and status registers. 296 */ 297 298 /* 299 * Cannot use convenient macros because the device's config structure 300 * may not have been created yet: major change from FreeBSD code. 301 */ 302 303 int rval; 304 u_int8_t ctr_sav, dtr_sav, str_sav; 305 306 /* Store writtable registers' values and test if they can be read */ 307 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 308 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 309 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 310 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 311 BUS_SPACE_BARRIER_READ); 312 313 /* 314 * Ensure PS2 ports in output mode, also read back value of control 315 * register. 316 */ 317 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 318 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 319 BUS_SPACE_BARRIER_WRITE); 320 321 if (bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 322 rval = 0; 323 } else { 324 /* 325 * Test if two values can be written and read from the data 326 * register. 327 */ 328 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 329 BUS_SPACE_BARRIER_READ); 330 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 331 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 332 BUS_SPACE_BARRIER_WRITE); 333 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 334 rval = 1; 335 } else { 336 /* Second value to test */ 337 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 338 BUS_SPACE_BARRIER_READ); 339 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 340 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 341 BUS_SPACE_BARRIER_WRITE); 342 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 343 rval = 1; 344 } else { 345 rval = 0; 346 } 347 } 348 349 } 350 351 /* Restore registers */ 352 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 353 BUS_SPACE_BARRIER_READ); 354 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 355 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 356 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 357 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 358 BUS_SPACE_BARRIER_WRITE); 359 360 return rval; 361 } 362 363 /* Detect parallel port chipset. */ 364 static int 365 atppc_detect_chipset(struct atppc_softc *atppc) 366 { 367 /* Try each detection routine. */ 368 int i, mode; 369 for (i = 0; chipset_detect[i] != NULL; i++) { 370 if ((mode = chipset_detect[i](atppc)) != -1) { 371 atppc->sc_mode = mode; 372 return 0; 373 } 374 } 375 376 return 1; 377 } 378 379 /* Detect generic capabilities. */ 380 static int 381 atppc_detect_generic(struct atppc_softc *atppc) 382 { 383 u_int8_t ecr_sav = atppc_r_ecr(atppc); 384 u_int8_t ctr_sav = atppc_r_ctr(atppc); 385 u_int8_t str_sav = atppc_r_str(atppc); 386 u_int8_t tmp; 387 atppc_barrier_r(atppc); 388 389 /* Default to generic */ 390 atppc->sc_type = ATPPC_TYPE_GENERIC; 391 atppc->sc_model = GENERIC; 392 393 /* Check for ECP */ 394 tmp = atppc_r_ecr(atppc); 395 atppc_barrier_r(atppc); 396 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 397 atppc_w_ecr(atppc, 0x34); 398 atppc_barrier_w(atppc); 399 tmp = atppc_r_ecr(atppc); 400 atppc_barrier_r(atppc); 401 if (tmp == 0x35) { 402 atppc->sc_has |= ATPPC_HAS_ECP; 403 } 404 } 405 406 /* Allow search for SMC style ECP+EPP mode */ 407 if (atppc->sc_has & ATPPC_HAS_ECP) { 408 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 409 atppc_barrier_w(atppc); 410 } 411 /* Check for EPP by checking for timeout bit */ 412 if (atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 413 atppc->sc_has |= ATPPC_HAS_EPP; 414 atppc->sc_epp = ATPPC_EPP_1_9; 415 if (atppc->sc_has & ATPPC_HAS_ECP) { 416 /* SMC like chipset found */ 417 atppc->sc_model = SMC_LIKE; 418 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 419 } 420 } 421 422 /* Detect PS2 mode */ 423 if (atppc->sc_has & ATPPC_HAS_ECP) { 424 /* Put ECP port into PS2 mode */ 425 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 426 atppc_barrier_w(atppc); 427 } 428 /* Put PS2 port in input mode: writes should not be readable */ 429 atppc_w_ctr(atppc, 0x20); 430 atppc_barrier_w(atppc); 431 /* 432 * Write two values to data port: if neither are read back, 433 * bidirectional mode is functional. 434 */ 435 atppc_w_dtr(atppc, 0xaa); 436 atppc_barrier_w(atppc); 437 tmp = atppc_r_dtr(atppc); 438 atppc_barrier_r(atppc); 439 if (tmp != 0xaa) { 440 atppc_w_dtr(atppc, 0x55); 441 atppc_barrier_w(atppc); 442 tmp = atppc_r_dtr(atppc); 443 atppc_barrier_r(atppc); 444 if (tmp != 0x55) { 445 atppc->sc_has |= ATPPC_HAS_PS2; 446 } 447 } 448 449 /* Restore to previous state */ 450 atppc_w_ecr(atppc, ecr_sav); 451 atppc_w_ctr(atppc, ctr_sav); 452 atppc_w_str(atppc, str_sav); 453 atppc_barrier_w(atppc); 454 455 return 0; 456 } 457 458 /* 459 * Detect parallel port FIFO: taken from FreeBSD code directly. 460 */ 461 static int 462 atppc_detect_fifo(struct atppc_softc *atppc) 463 { 464 #ifdef ATPPC_DEBUG 465 struct device *dev = (struct device *)atppc; 466 #endif 467 u_int8_t ecr_sav; 468 u_int8_t ctr_sav; 469 u_int8_t str_sav; 470 u_int8_t cc; 471 short i; 472 473 /* If there is no ECP mode, we cannot config a FIFO */ 474 if (!(atppc->sc_has & ATPPC_HAS_ECP)) { 475 return (EINVAL); 476 } 477 478 /* save registers */ 479 ecr_sav = atppc_r_ecr(atppc); 480 ctr_sav = atppc_r_ctr(atppc); 481 str_sav = atppc_r_str(atppc); 482 atppc_barrier_r(atppc); 483 484 /* Enter ECP configuration mode, no interrupt, no DMA */ 485 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 486 ~ATPPC_ENABLE_DMA); 487 atppc_barrier_w(atppc); 488 489 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 490 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 491 atppc_barrier_r(atppc); 492 493 /* XXX 16 and 32 bits implementations not supported */ 494 if (atppc->sc_pword != ATPPC_PWORD_8) { 495 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 496 __func__, dev->dv_xname, atppc->sc_pword)); 497 goto error; 498 } 499 500 /* Byte mode, reverse direction, no interrupt, no DMA */ 501 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 502 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 503 /* enter ECP test mode, no interrupt, no DMA */ 504 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 505 atppc_barrier_w(atppc); 506 507 /* flush the FIFO */ 508 for (i = 0; i < 1024; i++) { 509 atppc_r_fifo(atppc); 510 atppc_barrier_r(atppc); 511 cc = atppc_r_ecr(atppc); 512 atppc_barrier_r(atppc); 513 if (cc & ATPPC_FIFO_EMPTY) 514 break; 515 } 516 if (i >= 1024) { 517 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 518 dev->dv_xname)); 519 goto error; 520 } 521 522 /* Test mode, enable interrupts, no DMA */ 523 atppc_w_ecr(atppc, ATPPC_ECR_TST); 524 atppc_barrier_w(atppc); 525 526 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 527 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 528 atppc_w_fifo(atppc, (char)i); 529 atppc_barrier_w(atppc); 530 cc = atppc_r_ecr(atppc); 531 atppc_barrier_r(atppc); 532 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 533 /* readThreshold reached */ 534 atppc->sc_rthr = i + 1; 535 } 536 if (cc & ATPPC_FIFO_FULL) { 537 atppc->sc_fifo = i + 1; 538 break; 539 } 540 } 541 if (i >= 1024) { 542 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 543 dev->dv_xname)); 544 goto error; 545 } 546 547 /* Change direction */ 548 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 549 atppc_barrier_w(atppc); 550 551 /* Clear the serviceIntr bit we've already set in the above loop */ 552 atppc_w_ecr(atppc, ATPPC_ECR_TST); 553 atppc_barrier_w(atppc); 554 555 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 556 for (atppc->sc_wthr = 0; i > -1; i--) { 557 cc = atppc_r_fifo(atppc); 558 atppc_barrier_r(atppc); 559 if (cc != (char)(atppc->sc_fifo - i - 1)) { 560 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 561 __func__, dev->dv_xname)); 562 goto error; 563 } 564 565 cc = atppc_r_ecr(atppc); 566 atppc_barrier_r(atppc); 567 if ((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 568 /* writeIntrThreshold reached */ 569 atppc->sc_wthr = atppc->sc_fifo - i; 570 } 571 572 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 573 /* If FIFO empty before the last byte, error */ 574 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 575 dev->dv_xname)); 576 goto error; 577 } 578 } 579 580 /* FIFO must be empty after the last byte */ 581 cc = atppc_r_ecr(atppc); 582 atppc_barrier_r(atppc); 583 if (!(cc & ATPPC_FIFO_EMPTY)) { 584 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 585 dev->dv_xname)); 586 goto error; 587 } 588 589 /* Restore original registers */ 590 atppc_w_ctr(atppc, ctr_sav); 591 atppc_w_str(atppc, str_sav); 592 atppc_w_ecr(atppc, ecr_sav); 593 atppc_barrier_w(atppc); 594 595 /* Update capabilities */ 596 atppc->sc_has |= ATPPC_HAS_FIFO; 597 598 return 0; 599 600 error: 601 /* Restore original registers */ 602 atppc_w_ctr(atppc, ctr_sav); 603 atppc_w_str(atppc, str_sav); 604 atppc_w_ecr(atppc, ecr_sav); 605 atppc_barrier_w(atppc); 606 607 return (EINVAL); 608 } 609 610 /* Interrupt handler for atppc device: wakes up read/write functions */ 611 int 612 atppcintr(void *arg) 613 { 614 struct atppc_softc *atppc = (struct atppc_softc *)arg; 615 struct device *dev = &atppc->sc_dev; 616 int claim = 1; 617 enum { NONE, READER, WRITER } wake_up = NONE; 618 619 /* Record registers' status */ 620 atppc->sc_str_intr = atppc_r_str(atppc); 621 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 622 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 623 atppc_barrier_r(atppc); 624 625 /* Determine cause of interrupt and wake up top half */ 626 switch (atppc->sc_mode) { 627 case ATPPC_MODE_STD: 628 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 629 atppc->sc_irqstat = ATPPC_IRQ_nACK; 630 if (atppc->sc_outb) 631 wake_up = WRITER; 632 else 633 claim = 0; 634 break; 635 636 case ATPPC_MODE_NIBBLE: 637 case ATPPC_MODE_PS2: 638 /* nAck is set low by device and then high on ack */ 639 if (!(atppc->sc_str_intr & nACK)) { 640 claim = 0; 641 break; 642 } 643 atppc->sc_irqstat = ATPPC_IRQ_nACK; 644 if (atppc->sc_inb) 645 wake_up = READER; 646 break; 647 648 case ATPPC_MODE_ECP: 649 case ATPPC_MODE_FAST: 650 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 651 if (atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 652 if (atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 653 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 654 else 655 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 656 657 /* Decide where top half will be waiting */ 658 if (atppc->sc_mode & ATPPC_MODE_ECP) { 659 if (atppc->sc_ctr_intr & PCD) { 660 if (atppc->sc_inb) 661 wake_up = READER; 662 else 663 claim = 0; 664 } else { 665 if (atppc->sc_outb) 666 wake_up = WRITER; 667 else 668 claim = 0; 669 } 670 } else { 671 if (atppc->sc_outb) 672 wake_up = WRITER; 673 else 674 claim = 0; 675 } 676 } 677 /* Determine if nFault has occurred */ 678 if ((atppc->sc_mode & ATPPC_MODE_ECP) && 679 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 680 !(atppc->sc_str_intr & nFAULT)) { 681 682 /* Device is requesting the channel */ 683 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 684 claim = 1; 685 } 686 break; 687 688 case ATPPC_MODE_EPP: 689 /* nAck pulsed for 5 usec, too fast to check reliably */ 690 atppc->sc_irqstat = ATPPC_IRQ_nACK; 691 if (atppc->sc_inb) 692 wake_up = WRITER; 693 else if (atppc->sc_outb) 694 wake_up = READER; 695 else 696 claim = 0; 697 break; 698 699 default: 700 panic("%s: chipset is in invalid mode.", dev->dv_xname); 701 } 702 703 if (claim) { 704 switch (wake_up) { 705 case NONE: 706 break; 707 708 case READER: 709 wakeup(atppc->sc_inb); 710 break; 711 712 case WRITER: 713 wakeup(atppc->sc_outb); 714 break; 715 } 716 } 717 718 /* Call all of the installed handlers */ 719 if (claim) { 720 struct atppc_handler_node * callback; 721 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 722 entries) { 723 (*callback->func)(callback->arg); 724 } 725 } 726 727 return claim; 728 } 729 730 731 /* Functions which support ppbus interface */ 732 733 734 /* Check EPP mode timeout */ 735 static int 736 atppc_check_epp_timeout(struct device *dev) 737 { 738 struct atppc_softc *atppc = (struct atppc_softc *)dev; 739 int s; 740 int error; 741 742 s = splatppc(); 743 ATPPC_LOCK(atppc); 744 745 atppc_reset_epp_timeout(dev); 746 error = !(atppc_r_str(atppc) & TIMEOUT); 747 atppc_barrier_r(atppc); 748 749 ATPPC_UNLOCK(atppc); 750 splx(s); 751 752 return (error); 753 } 754 755 /* 756 * EPP timeout, according to the PC87332 manual 757 * Semantics of clearing EPP timeout bit. 758 * PC87332 - reading SPP_STR does it... 759 * SMC - write 1 to EPP timeout bit XXX 760 * Others - (?) write 0 to EPP timeout bit 761 */ 762 static void 763 atppc_reset_epp_timeout(struct device *dev) 764 { 765 struct atppc_softc *atppc = (struct atppc_softc *)dev; 766 register unsigned char r; 767 768 r = atppc_r_str(atppc); 769 atppc_barrier_r(atppc); 770 atppc_w_str(atppc, r | 0x1); 771 atppc_barrier_w(atppc); 772 atppc_w_str(atppc, r & 0xfe); 773 atppc_barrier_w(atppc); 774 775 return; 776 } 777 778 779 /* Read from atppc device: returns 0 on success. */ 780 static int 781 atppc_read(struct device *dev, char *buf, int len, int ioflag, 782 size_t *cnt) 783 { 784 struct atppc_softc *atppc = (struct atppc_softc *)dev; 785 int error = 0; 786 int s; 787 788 s = splatppc(); 789 ATPPC_LOCK(atppc); 790 791 *cnt = 0; 792 793 /* Initialize buffer */ 794 atppc->sc_inb = atppc->sc_inbstart = buf; 795 atppc->sc_inb_nbytes = len; 796 797 /* Initialize device input error state for new operation */ 798 atppc->sc_inerr = 0; 799 800 /* Call appropriate function to read bytes */ 801 switch(atppc->sc_mode) { 802 case ATPPC_MODE_STD: 803 case ATPPC_MODE_FAST: 804 error = ENODEV; 805 break; 806 807 case ATPPC_MODE_NIBBLE: 808 atppc_nibble_read(atppc); 809 break; 810 811 case ATPPC_MODE_PS2: 812 atppc_byte_read(atppc); 813 break; 814 815 case ATPPC_MODE_ECP: 816 atppc_ecp_read(atppc); 817 break; 818 819 case ATPPC_MODE_EPP: 820 atppc_epp_read(atppc); 821 break; 822 823 default: 824 panic("%s(%s): chipset in invalid mode.\n", __func__, 825 dev->dv_xname); 826 } 827 828 /* Update counter*/ 829 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 830 831 /* Reset buffer */ 832 atppc->sc_inb = atppc->sc_inbstart = NULL; 833 atppc->sc_inb_nbytes = 0; 834 835 if (!(error)) 836 error = atppc->sc_inerr; 837 838 ATPPC_UNLOCK(atppc); 839 splx(s); 840 841 return (error); 842 } 843 844 /* Write to atppc device: returns 0 on success. */ 845 static int 846 atppc_write(struct device *dev, char *buf, int len, int ioflag, size_t *cnt) 847 { 848 struct atppc_softc * const atppc = (struct atppc_softc *)dev; 849 int error = 0; 850 int s; 851 852 *cnt = 0; 853 854 s = splatppc(); 855 ATPPC_LOCK(atppc); 856 857 /* Set up line buffer */ 858 atppc->sc_outb = atppc->sc_outbstart = buf; 859 atppc->sc_outb_nbytes = len; 860 861 /* Initialize device output error state for new operation */ 862 atppc->sc_outerr = 0; 863 864 /* Call appropriate function to write bytes */ 865 switch (atppc->sc_mode) { 866 case ATPPC_MODE_STD: 867 atppc_std_write(atppc); 868 break; 869 870 case ATPPC_MODE_NIBBLE: 871 case ATPPC_MODE_PS2: 872 error = ENODEV; 873 break; 874 875 case ATPPC_MODE_FAST: 876 case ATPPC_MODE_ECP: 877 atppc_fifo_write(atppc); 878 break; 879 880 case ATPPC_MODE_EPP: 881 atppc_epp_write(atppc); 882 break; 883 884 default: 885 panic("%s(%s): chipset in invalid mode.\n", __func__, 886 dev->dv_xname); 887 } 888 889 /* Update counter*/ 890 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 891 892 /* Reset output buffer */ 893 atppc->sc_outb = atppc->sc_outbstart = NULL; 894 atppc->sc_outb_nbytes = 0; 895 896 if (!(error)) 897 error = atppc->sc_outerr; 898 899 ATPPC_UNLOCK(atppc); 900 splx(s); 901 902 return (error); 903 } 904 905 /* 906 * Set mode of chipset to mode argument. Modes not supported are ignored. If 907 * multiple modes are flagged, the mode is not changed. Mode's are those 908 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 909 * can change their mode of operation. However, ALL operation modes support 910 * centronics mode and nibble mode. Modes determine both hardware AND software 911 * behaviour. 912 * NOTE: the mode for ECP should only be changed when the channel is in 913 * forward idle mode. This function does not make sure FIFO's have flushed or 914 * any consistency checks. 915 */ 916 static int 917 atppc_setmode(struct device *dev, int mode) 918 { 919 struct atppc_softc *atppc = (struct atppc_softc *)dev; 920 u_int8_t ecr; 921 u_int8_t chipset_mode; 922 int s; 923 int rval = 0; 924 925 s = splatppc(); 926 ATPPC_LOCK(atppc); 927 928 /* If ECP capable, configure ecr register */ 929 if (atppc->sc_has & ATPPC_HAS_ECP) { 930 /* Read ECR with mode masked out */ 931 ecr = (atppc_r_ecr(atppc) & 0x1f); 932 atppc_barrier_r(atppc); 933 934 switch (mode) { 935 case PPBUS_ECP: 936 /* Set ECP mode */ 937 ecr |= ATPPC_ECR_ECP; 938 chipset_mode = ATPPC_MODE_ECP; 939 break; 940 941 case PPBUS_EPP: 942 /* Set EPP mode */ 943 if (atppc->sc_has & ATPPC_HAS_EPP) { 944 ecr |= ATPPC_ECR_EPP; 945 chipset_mode = ATPPC_MODE_EPP; 946 } else { 947 rval = ENODEV; 948 goto end; 949 } 950 break; 951 952 case PPBUS_FAST: 953 /* Set fast centronics mode */ 954 ecr |= ATPPC_ECR_FIFO; 955 chipset_mode = ATPPC_MODE_FAST; 956 break; 957 958 case PPBUS_PS2: 959 /* Set PS2 mode */ 960 ecr |= ATPPC_ECR_PS2; 961 chipset_mode = ATPPC_MODE_PS2; 962 break; 963 964 case PPBUS_COMPATIBLE: 965 /* Set standard mode */ 966 ecr |= ATPPC_ECR_STD; 967 chipset_mode = ATPPC_MODE_STD; 968 break; 969 970 case PPBUS_NIBBLE: 971 /* Set nibble mode: uses chipset standard mode */ 972 ecr |= ATPPC_ECR_STD; 973 chipset_mode = ATPPC_MODE_NIBBLE; 974 break; 975 976 default: 977 /* Invalid mode specified for ECP chip */ 978 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 979 "argument.\n", __func__, dev->dv_xname)); 980 rval = ENODEV; 981 goto end; 982 } 983 984 /* Switch to byte mode to be able to change modes. */ 985 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 986 atppc_barrier_w(atppc); 987 988 /* Update mode */ 989 atppc_w_ecr(atppc, ecr); 990 atppc_barrier_w(atppc); 991 } else { 992 switch (mode) { 993 case PPBUS_EPP: 994 if (atppc->sc_has & ATPPC_HAS_EPP) { 995 chipset_mode = ATPPC_MODE_EPP; 996 } else { 997 rval = ENODEV; 998 goto end; 999 } 1000 break; 1001 1002 case PPBUS_PS2: 1003 if (atppc->sc_has & ATPPC_HAS_PS2) { 1004 chipset_mode = ATPPC_MODE_PS2; 1005 } else { 1006 rval = ENODEV; 1007 goto end; 1008 } 1009 break; 1010 1011 case PPBUS_NIBBLE: 1012 /* Set nibble mode (virtual) */ 1013 chipset_mode = ATPPC_MODE_NIBBLE; 1014 break; 1015 1016 case PPBUS_COMPATIBLE: 1017 chipset_mode = ATPPC_MODE_STD; 1018 break; 1019 1020 case PPBUS_ECP: 1021 rval = ENODEV; 1022 goto end; 1023 1024 default: 1025 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1026 "argument.\n", __func__, dev->dv_xname)); 1027 rval = ENODEV; 1028 goto end; 1029 } 1030 } 1031 1032 atppc->sc_mode = chipset_mode; 1033 if (chipset_mode == ATPPC_MODE_PS2) { 1034 /* Set direction bit to reverse */ 1035 ecr = atppc_r_ctr(atppc); 1036 atppc_barrier_r(atppc); 1037 ecr |= PCD; 1038 atppc_w_ctr(atppc, ecr); 1039 atppc_barrier_w(atppc); 1040 } 1041 1042 end: 1043 ATPPC_UNLOCK(atppc); 1044 splx(s); 1045 1046 return rval; 1047 } 1048 1049 /* Get the current mode of chipset */ 1050 static int 1051 atppc_getmode(struct device *dev) 1052 { 1053 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1054 int mode; 1055 int s; 1056 1057 s = splatppc(); 1058 ATPPC_LOCK(atppc); 1059 1060 /* The chipset can only be in one mode at a time logically */ 1061 switch (atppc->sc_mode) { 1062 case ATPPC_MODE_ECP: 1063 mode = PPBUS_ECP; 1064 break; 1065 1066 case ATPPC_MODE_EPP: 1067 mode = PPBUS_EPP; 1068 break; 1069 1070 case ATPPC_MODE_PS2: 1071 mode = PPBUS_PS2; 1072 break; 1073 1074 case ATPPC_MODE_STD: 1075 mode = PPBUS_COMPATIBLE; 1076 break; 1077 1078 case ATPPC_MODE_NIBBLE: 1079 mode = PPBUS_NIBBLE; 1080 break; 1081 1082 case ATPPC_MODE_FAST: 1083 mode = PPBUS_FAST; 1084 break; 1085 1086 default: 1087 panic("%s(%s): device is in invalid mode!", __func__, 1088 dev->dv_xname); 1089 break; 1090 } 1091 1092 ATPPC_UNLOCK(atppc); 1093 splx(s); 1094 1095 return mode; 1096 } 1097 1098 1099 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1100 static void 1101 atppc_ecp_sync(struct device *dev) 1102 { 1103 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1104 int i; 1105 int s; 1106 u_int8_t r; 1107 1108 s = splatppc(); 1109 ATPPC_LOCK(atppc); 1110 1111 /* 1112 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1113 * the mode is either ECP or Fast Centronics. 1114 */ 1115 r = atppc_r_ecr(atppc); 1116 atppc_barrier_r(atppc); 1117 r &= 0xe0; 1118 if (!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1119 && (r != ATPPC_ECR_FIFO))) { 1120 goto end; 1121 } 1122 1123 /* Wait for FIFO to empty */ 1124 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1125 r = atppc_r_ecr(atppc); 1126 atppc_barrier_r(atppc); 1127 if (r & ATPPC_FIFO_EMPTY) { 1128 goto end; 1129 } 1130 delay(100); /* Supposed to be a 100 usec delay */ 1131 } 1132 1133 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1134 dev->dv_xname)); 1135 1136 end: 1137 ATPPC_UNLOCK(atppc); 1138 splx(s); 1139 1140 return; 1141 } 1142 1143 /* Execute a microsequence to handle fast I/O operations. */ 1144 static int 1145 atppc_exec_microseq(struct device *dev, struct ppbus_microseq **p_msq) 1146 { 1147 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1148 struct ppbus_microseq *mi = *p_msq; 1149 char cc, *p; 1150 int i, iter, len; 1151 int error; 1152 int s; 1153 register int reg; 1154 register unsigned char mask; 1155 register int accum = 0; 1156 register char *ptr = NULL; 1157 struct ppbus_microseq *stack = NULL; 1158 1159 s = splatppc(); 1160 ATPPC_LOCK(atppc); 1161 1162 /* microsequence registers are equivalent to PC-like port registers */ 1163 1164 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1165 (atppc)->sc_ioh, (register)) 1166 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1167 (atppc)->sc_ioh, (register), (byte)) 1168 1169 /* Loop until microsequence execution finishes (ending op code) */ 1170 for (;;) { 1171 switch (mi->opcode) { 1172 case MS_OP_RSET: 1173 cc = r_reg(mi->arg[0].i, atppc); 1174 atppc_barrier_r(atppc); 1175 cc &= (char)mi->arg[2].i; /* clear mask */ 1176 cc |= (char)mi->arg[1].i; /* assert mask */ 1177 w_reg(mi->arg[0].i, atppc, cc); 1178 atppc_barrier_w(atppc); 1179 mi++; 1180 break; 1181 1182 case MS_OP_RASSERT_P: 1183 reg = mi->arg[1].i; 1184 ptr = atppc->sc_ptr; 1185 1186 if ((len = mi->arg[0].i) == MS_ACCUM) { 1187 accum = atppc->sc_accum; 1188 for (; accum; accum--) { 1189 w_reg(reg, atppc, *ptr++); 1190 atppc_barrier_w(atppc); 1191 } 1192 atppc->sc_accum = accum; 1193 } else { 1194 for (i = 0; i < len; i++) { 1195 w_reg(reg, atppc, *ptr++); 1196 atppc_barrier_w(atppc); 1197 } 1198 } 1199 1200 atppc->sc_ptr = ptr; 1201 mi++; 1202 break; 1203 1204 case MS_OP_RFETCH_P: 1205 reg = mi->arg[1].i; 1206 mask = (char)mi->arg[2].i; 1207 ptr = atppc->sc_ptr; 1208 1209 if ((len = mi->arg[0].i) == MS_ACCUM) { 1210 accum = atppc->sc_accum; 1211 for (; accum; accum--) { 1212 *ptr++ = r_reg(reg, atppc) & mask; 1213 atppc_barrier_r(atppc); 1214 } 1215 atppc->sc_accum = accum; 1216 } else { 1217 for (i = 0; i < len; i++) { 1218 *ptr++ = r_reg(reg, atppc) & mask; 1219 atppc_barrier_r(atppc); 1220 } 1221 } 1222 1223 atppc->sc_ptr = ptr; 1224 mi++; 1225 break; 1226 1227 case MS_OP_RFETCH: 1228 *((char *)mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1229 (char)mi->arg[1].i; 1230 atppc_barrier_r(atppc); 1231 mi++; 1232 break; 1233 1234 case MS_OP_RASSERT: 1235 case MS_OP_DELAY: 1236 /* let's suppose the next instr. is the same */ 1237 do { 1238 for (;mi->opcode == MS_OP_RASSERT; mi++) { 1239 w_reg(mi->arg[0].i, atppc, 1240 (char)mi->arg[1].i); 1241 atppc_barrier_w(atppc); 1242 } 1243 1244 for (;mi->opcode == MS_OP_DELAY; mi++) { 1245 delay(mi->arg[0].i); 1246 } 1247 } while (mi->opcode == MS_OP_RASSERT); 1248 break; 1249 1250 case MS_OP_ADELAY: 1251 if (mi->arg[0].i) { 1252 tsleep(atppc, PPBUSPRI, "atppcdelay", 1253 mi->arg[0].i * (hz/1000)); 1254 } 1255 mi++; 1256 break; 1257 1258 case MS_OP_TRIG: 1259 reg = mi->arg[0].i; 1260 iter = mi->arg[1].i; 1261 p = (char *)mi->arg[2].p; 1262 1263 /* XXX delay limited to 255 us */ 1264 for (i = 0; i < iter; i++) { 1265 w_reg(reg, atppc, *p++); 1266 atppc_barrier_w(atppc); 1267 delay((unsigned char)*p++); 1268 } 1269 1270 mi++; 1271 break; 1272 1273 case MS_OP_SET: 1274 atppc->sc_accum = mi->arg[0].i; 1275 mi++; 1276 break; 1277 1278 case MS_OP_DBRA: 1279 if (--atppc->sc_accum > 0) { 1280 mi += mi->arg[0].i; 1281 } 1282 1283 mi++; 1284 break; 1285 1286 case MS_OP_BRSET: 1287 cc = atppc_r_str(atppc); 1288 atppc_barrier_r(atppc); 1289 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1290 mi += mi->arg[1].i; 1291 } 1292 mi++; 1293 break; 1294 1295 case MS_OP_BRCLEAR: 1296 cc = atppc_r_str(atppc); 1297 atppc_barrier_r(atppc); 1298 if ((cc & (char)mi->arg[0].i) == 0) { 1299 mi += mi->arg[1].i; 1300 } 1301 mi++; 1302 break; 1303 1304 case MS_OP_BRSTAT: 1305 cc = atppc_r_str(atppc); 1306 atppc_barrier_r(atppc); 1307 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1308 (char)mi->arg[0].i) { 1309 mi += mi->arg[2].i; 1310 } 1311 mi++; 1312 break; 1313 1314 case MS_OP_C_CALL: 1315 /* 1316 * If the C call returns !0 then end the microseq. 1317 * The current state of ptr is passed to the C function 1318 */ 1319 if ((error = mi->arg[0].f(mi->arg[1].p, 1320 atppc->sc_ptr))) { 1321 ATPPC_UNLOCK(atppc); 1322 splx(s); 1323 return (error); 1324 } 1325 mi++; 1326 break; 1327 1328 case MS_OP_PTR: 1329 atppc->sc_ptr = (char *)mi->arg[0].p; 1330 mi++; 1331 break; 1332 1333 case MS_OP_CALL: 1334 if (stack) { 1335 panic("%s - %s: too much calls", dev->dv_xname, 1336 __func__); 1337 } 1338 1339 if (mi->arg[0].p) { 1340 /* store state of the actual microsequence */ 1341 stack = mi; 1342 1343 /* jump to the new microsequence */ 1344 mi = (struct ppbus_microseq *)mi->arg[0].p; 1345 } else { 1346 mi++; 1347 } 1348 break; 1349 1350 case MS_OP_SUBRET: 1351 /* retrieve microseq and pc state before the call */ 1352 mi = stack; 1353 1354 /* reset the stack */ 1355 stack = 0; 1356 1357 /* XXX return code */ 1358 1359 mi++; 1360 break; 1361 1362 case MS_OP_PUT: 1363 case MS_OP_GET: 1364 case MS_OP_RET: 1365 /* 1366 * Can't return to atppc level during the execution 1367 * of a submicrosequence. 1368 */ 1369 if (stack) { 1370 panic("%s: cannot return to atppc level", 1371 __func__); 1372 } 1373 /* update pc for atppc level of execution */ 1374 *p_msq = mi; 1375 1376 ATPPC_UNLOCK(atppc); 1377 splx(s); 1378 return (0); 1379 break; 1380 1381 default: 1382 panic("%s: unknown microsequence " 1383 "opcode 0x%x", __func__, mi->opcode); 1384 break; 1385 } 1386 } 1387 1388 /* Should not be reached! */ 1389 #ifdef ATPPC_DEBUG 1390 panic("%s: unexpected code reached!\n", __func__); 1391 #endif 1392 } 1393 1394 /* General I/O routine */ 1395 static u_int8_t 1396 atppc_io(struct device *dev, int iop, u_char *addr, int cnt, u_char byte) 1397 { 1398 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1399 u_int8_t val = 0; 1400 int s; 1401 1402 s = splatppc(); 1403 ATPPC_LOCK(atppc); 1404 1405 switch (iop) { 1406 case PPBUS_OUTSB_EPP: 1407 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1408 ATPPC_EPP_DATA, addr, cnt); 1409 break; 1410 case PPBUS_OUTSW_EPP: 1411 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1412 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1413 break; 1414 case PPBUS_OUTSL_EPP: 1415 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1416 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1417 break; 1418 case PPBUS_INSB_EPP: 1419 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1420 ATPPC_EPP_DATA, addr, cnt); 1421 break; 1422 case PPBUS_INSW_EPP: 1423 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1424 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1425 break; 1426 case PPBUS_INSL_EPP: 1427 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1428 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1429 break; 1430 case PPBUS_RDTR: 1431 val = (atppc_r_dtr(atppc)); 1432 break; 1433 case PPBUS_RSTR: 1434 val = (atppc_r_str(atppc)); 1435 break; 1436 case PPBUS_RCTR: 1437 val = (atppc_r_ctr(atppc)); 1438 break; 1439 case PPBUS_REPP_A: 1440 val = (atppc_r_eppA(atppc)); 1441 break; 1442 case PPBUS_REPP_D: 1443 val = (atppc_r_eppD(atppc)); 1444 break; 1445 case PPBUS_RECR: 1446 val = (atppc_r_ecr(atppc)); 1447 break; 1448 case PPBUS_RFIFO: 1449 val = (atppc_r_fifo(atppc)); 1450 break; 1451 case PPBUS_WDTR: 1452 atppc_w_dtr(atppc, byte); 1453 break; 1454 case PPBUS_WSTR: 1455 atppc_w_str(atppc, byte); 1456 break; 1457 case PPBUS_WCTR: 1458 atppc_w_ctr(atppc, byte); 1459 break; 1460 case PPBUS_WEPP_A: 1461 atppc_w_eppA(atppc, byte); 1462 break; 1463 case PPBUS_WEPP_D: 1464 atppc_w_eppD(atppc, byte); 1465 break; 1466 case PPBUS_WECR: 1467 atppc_w_ecr(atppc, byte); 1468 break; 1469 case PPBUS_WFIFO: 1470 atppc_w_fifo(atppc, byte); 1471 break; 1472 default: 1473 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1474 __func__); 1475 break; 1476 } 1477 1478 atppc_barrier(atppc); 1479 1480 ATPPC_UNLOCK(atppc); 1481 splx(s); 1482 1483 return val; 1484 } 1485 1486 /* Read "instance variables" of atppc device */ 1487 static int 1488 atppc_read_ivar(struct device *dev, int index, unsigned int *val) 1489 { 1490 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1491 int rval = 0; 1492 int s; 1493 1494 s = splatppc(); 1495 ATPPC_LOCK(atppc); 1496 1497 switch(index) { 1498 case PPBUS_IVAR_EPP_PROTO: 1499 if (atppc->sc_epp == ATPPC_EPP_1_9) 1500 *val = PPBUS_EPP_1_9; 1501 else if (atppc->sc_epp == ATPPC_EPP_1_7) 1502 *val = PPBUS_EPP_1_7; 1503 /* XXX what if not using EPP ? */ 1504 break; 1505 1506 case PPBUS_IVAR_INTR: 1507 *val = ((atppc->sc_use & ATPPC_USE_INTR) != 0); 1508 break; 1509 1510 case PPBUS_IVAR_DMA: 1511 *val = ((atppc->sc_use & ATPPC_USE_DMA) != 0); 1512 break; 1513 1514 default: 1515 rval = ENODEV; 1516 } 1517 1518 ATPPC_UNLOCK(atppc); 1519 splx(s); 1520 1521 return rval; 1522 } 1523 1524 /* Write "instance varaibles" of atppc device */ 1525 static int 1526 atppc_write_ivar(struct device *dev, int index, unsigned int *val) 1527 { 1528 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1529 int rval = 0; 1530 int s; 1531 1532 s = splatppc(); 1533 ATPPC_LOCK(atppc); 1534 1535 switch(index) { 1536 case PPBUS_IVAR_EPP_PROTO: 1537 if (*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1538 atppc->sc_epp = *val; 1539 else 1540 rval = EINVAL; 1541 break; 1542 1543 case PPBUS_IVAR_INTR: 1544 if (*val == 0) 1545 atppc->sc_use &= ~ATPPC_USE_INTR; 1546 else if (atppc->sc_has & ATPPC_HAS_INTR) 1547 atppc->sc_use |= ATPPC_USE_INTR; 1548 else 1549 rval = ENODEV; 1550 break; 1551 1552 case PPBUS_IVAR_DMA: 1553 if (*val == 0) 1554 atppc->sc_use &= ~ATPPC_USE_DMA; 1555 else if (atppc->sc_has & ATPPC_HAS_DMA) 1556 atppc->sc_use |= ATPPC_USE_DMA; 1557 else 1558 rval = ENODEV; 1559 break; 1560 1561 default: 1562 rval = ENODEV; 1563 } 1564 1565 ATPPC_UNLOCK(atppc); 1566 splx(s); 1567 1568 return rval; 1569 } 1570 1571 /* Add a handler routine to be called by the interrupt handler */ 1572 static int 1573 atppc_add_handler(struct device *dev, void (*handler)(void *), void *arg) 1574 { 1575 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1576 struct atppc_handler_node *callback; 1577 int rval = 0; 1578 int s; 1579 1580 s = splatppc(); 1581 ATPPC_LOCK(atppc); 1582 1583 if (handler == NULL) { 1584 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1585 __func__, dev->dv_xname)); 1586 rval = EINVAL; 1587 } else { 1588 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1589 M_NOWAIT); 1590 if (callback) { 1591 callback->func = handler; 1592 callback->arg = arg; 1593 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1594 callback, entries); 1595 } else { 1596 rval = ENOMEM; 1597 } 1598 } 1599 1600 ATPPC_UNLOCK(atppc); 1601 splx(s); 1602 1603 return rval; 1604 } 1605 1606 /* Remove a handler added by atppc_add_handler() */ 1607 static int 1608 atppc_remove_handler(struct device *dev, void (*handler)(void *)) 1609 { 1610 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1611 struct atppc_handler_node *callback; 1612 int rval = EINVAL; 1613 int s; 1614 1615 s = splatppc(); 1616 ATPPC_LOCK(atppc); 1617 1618 if (SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1619 panic("%s(%s): attempt to remove handler from empty list.\n", 1620 __func__, dev->dv_xname); 1621 1622 /* Search list for handler */ 1623 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1624 if (callback->func == handler) { 1625 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1626 atppc_handler_node, entries); 1627 free(callback, M_DEVBUF); 1628 rval = 0; 1629 break; 1630 } 1631 } 1632 1633 ATPPC_UNLOCK(atppc); 1634 splx(s); 1635 1636 return rval; 1637 } 1638 1639 /* Utility functions */ 1640 1641 1642 /* 1643 * Functions that read bytes from port into buffer: called from interrupt 1644 * handler depending on current chipset mode and cause of interrupt. Return 1645 * value: number of bytes moved. 1646 */ 1647 1648 /* Only the lower 4 bits of the final value are valid */ 1649 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1650 1651 /* Read bytes in nibble mode */ 1652 static void 1653 atppc_nibble_read(struct atppc_softc *atppc) 1654 { 1655 int i; 1656 u_int8_t nibble[2]; 1657 u_int8_t ctr; 1658 u_int8_t str; 1659 1660 /* Enable interrupts if needed */ 1661 if (atppc->sc_use & ATPPC_USE_INTR) { 1662 ctr = atppc_r_ctr(atppc); 1663 atppc_barrier_r(atppc); 1664 if (!(ctr & IRQENABLE)) { 1665 ctr |= IRQENABLE; 1666 atppc_w_ctr(atppc, ctr); 1667 atppc_barrier_w(atppc); 1668 } 1669 } 1670 1671 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1672 /* Check if device has data to send in idle phase */ 1673 str = atppc_r_str(atppc); 1674 atppc_barrier_r(atppc); 1675 if (str & nDATAVAIL) { 1676 return; 1677 } 1678 1679 /* Nibble-mode handshake transfer */ 1680 for (i = 0; i < 2; i++) { 1681 /* Event 7 - ready to take data (HOSTBUSY low) */ 1682 ctr = atppc_r_ctr(atppc); 1683 atppc_barrier_r(atppc); 1684 ctr |= HOSTBUSY; 1685 atppc_w_ctr(atppc, ctr); 1686 atppc_barrier_w(atppc); 1687 1688 /* Event 8 - peripheral writes the first nibble */ 1689 1690 /* Event 9 - peripheral set nAck low */ 1691 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1692 if (atppc->sc_inerr) 1693 return; 1694 1695 /* read nibble */ 1696 nibble[i] = atppc_r_str(atppc); 1697 1698 /* Event 10 - ack, nibble received */ 1699 ctr &= ~HOSTBUSY; 1700 atppc_w_ctr(atppc, ctr); 1701 1702 /* Event 11 - wait ack from peripherial */ 1703 if (atppc->sc_use & ATPPC_USE_INTR) 1704 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1705 atppc->sc_inb, ATPPC_IRQ_nACK); 1706 else 1707 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1708 PTRCLK); 1709 if (atppc->sc_inerr) 1710 return; 1711 } 1712 1713 /* Store byte transfered */ 1714 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1715 (nibble2char(nibble[0]) & 0x0f); 1716 atppc->sc_inbstart++; 1717 } 1718 } 1719 1720 /* Read bytes in bidirectional mode */ 1721 static void 1722 atppc_byte_read(struct atppc_softc * const atppc) 1723 { 1724 u_int8_t ctr; 1725 u_int8_t str; 1726 1727 /* Check direction bit */ 1728 ctr = atppc_r_ctr(atppc); 1729 atppc_barrier_r(atppc); 1730 if (!(ctr & PCD)) { 1731 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1732 "bit set.", atppc->sc_dev.dv_xname)); 1733 atppc->sc_inerr = ENODEV; 1734 return; 1735 } 1736 /* Enable interrupts if needed */ 1737 if (atppc->sc_use & ATPPC_USE_INTR) { 1738 if (!(ctr & IRQENABLE)) { 1739 ctr |= IRQENABLE; 1740 atppc_w_ctr(atppc, ctr); 1741 atppc_barrier_w(atppc); 1742 } 1743 } 1744 1745 /* Byte-mode handshake transfer */ 1746 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1747 /* Check if device has data to send */ 1748 str = atppc_r_str(atppc); 1749 atppc_barrier_r(atppc); 1750 if (str & nDATAVAIL) { 1751 return; 1752 } 1753 1754 /* Event 7 - ready to take data (nAUTO low) */ 1755 ctr |= HOSTBUSY; 1756 atppc_w_ctr(atppc, ctr); 1757 atppc_barrier_w(atppc); 1758 1759 /* Event 9 - peripheral set nAck low */ 1760 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1761 if (atppc->sc_inerr) 1762 return; 1763 1764 /* Store byte transfered */ 1765 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1766 atppc_barrier_r(atppc); 1767 1768 /* Event 10 - data received, can't accept more */ 1769 ctr &= ~HOSTBUSY; 1770 atppc_w_ctr(atppc, ctr); 1771 atppc_barrier_w(atppc); 1772 1773 /* Event 11 - peripheral ack */ 1774 if (atppc->sc_use & ATPPC_USE_INTR) 1775 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1776 atppc->sc_inb, ATPPC_IRQ_nACK); 1777 else 1778 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1779 if (atppc->sc_inerr) 1780 return; 1781 1782 /* Event 16 - strobe */ 1783 str |= HOSTCLK; 1784 atppc_w_str(atppc, str); 1785 atppc_barrier_w(atppc); 1786 DELAY(1); 1787 str &= ~HOSTCLK; 1788 atppc_w_str(atppc, str); 1789 atppc_barrier_w(atppc); 1790 1791 /* Update counter */ 1792 atppc->sc_inbstart++; 1793 } 1794 } 1795 1796 /* Read bytes in EPP mode */ 1797 static void 1798 atppc_epp_read(struct atppc_softc * atppc) 1799 { 1800 if (atppc->sc_epp == ATPPC_EPP_1_9) { 1801 { 1802 uint8_t str; 1803 int i; 1804 1805 atppc_reset_epp_timeout((struct device *)atppc); 1806 for (i = 0; i < atppc->sc_inb_nbytes; i++) { 1807 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1808 atppc_barrier_r(atppc); 1809 str = atppc_r_str(atppc); 1810 atppc_barrier_r(atppc); 1811 if (str & TIMEOUT) { 1812 atppc->sc_inerr = EIO; 1813 break; 1814 } 1815 atppc->sc_inbstart++; 1816 } 1817 } 1818 } else { 1819 /* Read data block from EPP data register */ 1820 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1821 atppc->sc_inb_nbytes); 1822 atppc_barrier_r(atppc); 1823 /* Update buffer position, byte count and counter */ 1824 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1825 } 1826 1827 return; 1828 } 1829 1830 /* Read bytes in ECP mode */ 1831 static void 1832 atppc_ecp_read(struct atppc_softc *atppc) 1833 { 1834 u_int8_t ecr; 1835 u_int8_t ctr; 1836 u_int8_t str; 1837 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1838 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1839 unsigned int worklen; 1840 1841 /* Check direction bit */ 1842 ctr = ctr_sav; 1843 atppc_barrier_r(atppc); 1844 if (!(ctr & PCD)) { 1845 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1846 "bit set.", atppc->sc_dev.dv_xname)); 1847 atppc->sc_inerr = ENODEV; 1848 goto end; 1849 } 1850 1851 /* Clear device request if any */ 1852 if (atppc->sc_use & ATPPC_USE_INTR) 1853 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1854 1855 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1856 ecr = atppc_r_ecr(atppc); 1857 atppc_barrier_r(atppc); 1858 if (ecr & ATPPC_FIFO_EMPTY) { 1859 /* Check for invalid state */ 1860 if (ecr & ATPPC_FIFO_FULL) { 1861 atppc_ecp_read_error(atppc); 1862 break; 1863 } 1864 1865 /* Check if device has data to send */ 1866 str = atppc_r_str(atppc); 1867 atppc_barrier_r(atppc); 1868 if (str & nDATAVAIL) { 1869 break; 1870 } 1871 1872 if (atppc->sc_use & ATPPC_USE_INTR) { 1873 /* Enable interrupts */ 1874 ecr &= ~ATPPC_SERVICE_INTR; 1875 atppc_w_ecr(atppc, ecr); 1876 atppc_barrier_w(atppc); 1877 /* Wait for FIFO to fill */ 1878 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1879 atppc->sc_inb, ATPPC_IRQ_FIFO); 1880 if (atppc->sc_inerr) 1881 break; 1882 } else { 1883 DELAY(1); 1884 } 1885 continue; 1886 } 1887 else if (ecr & ATPPC_FIFO_FULL) { 1888 /* Transfer sc_fifo bytes */ 1889 worklen = atppc->sc_fifo; 1890 } 1891 else if (ecr & ATPPC_SERVICE_INTR) { 1892 /* Transfer sc_rthr bytes */ 1893 worklen = atppc->sc_rthr; 1894 } else { 1895 /* At least one byte is in the FIFO */ 1896 worklen = 1; 1897 } 1898 1899 if ((atppc->sc_use & ATPPC_USE_INTR) && 1900 (atppc->sc_use & ATPPC_USE_DMA)) { 1901 1902 atppc_ecp_read_dma(atppc, &worklen, ecr); 1903 } else { 1904 atppc_ecp_read_pio(atppc, &worklen, ecr); 1905 } 1906 1907 if (atppc->sc_inerr) { 1908 atppc_ecp_read_error(atppc); 1909 break; 1910 } 1911 1912 /* Update counter */ 1913 atppc->sc_inbstart += worklen; 1914 } 1915 end: 1916 atppc_w_ctr(atppc, ctr_sav); 1917 atppc_w_ecr(atppc, ecr_sav); 1918 atppc_barrier_w(atppc); 1919 } 1920 1921 /* Read bytes in ECP mode using DMA transfers */ 1922 static void 1923 atppc_ecp_read_dma(struct atppc_softc *atppc, unsigned int *length, 1924 unsigned char ecr) 1925 { 1926 /* Limit transfer to maximum DMA size and start it */ 1927 *length = min(*length, atppc->sc_dma_maxsize); 1928 atppc->sc_dmastat = ATPPC_DMA_INIT; 1929 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1930 ATPPC_DMA_MODE_READ); 1931 1932 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1933 1934 /* Enable interrupts, DMA */ 1935 ecr &= ~ATPPC_SERVICE_INTR; 1936 ecr |= ATPPC_ENABLE_DMA; 1937 atppc_w_ecr(atppc, ecr); 1938 atppc_barrier_w(atppc); 1939 1940 /* Wait for DMA completion */ 1941 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1942 ATPPC_IRQ_DMA); 1943 if (atppc->sc_inerr) 1944 return; 1945 1946 /* Get register value recorded by interrupt handler */ 1947 ecr = atppc->sc_ecr_intr; 1948 /* Clear DMA programming */ 1949 atppc->sc_dma_finish(atppc); 1950 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1951 /* Disable DMA */ 1952 ecr &= ~ATPPC_ENABLE_DMA; 1953 atppc_w_ecr(atppc, ecr); 1954 atppc_barrier_w(atppc); 1955 } 1956 1957 /* Read bytes in ECP mode using PIO transfers */ 1958 static void 1959 atppc_ecp_read_pio(struct atppc_softc *atppc, unsigned int *length, 1960 unsigned char ecr) 1961 { 1962 /* Disable DMA */ 1963 ecr &= ~ATPPC_ENABLE_DMA; 1964 atppc_w_ecr(atppc, ecr); 1965 atppc_barrier_w(atppc); 1966 1967 /* Read from FIFO */ 1968 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 1969 } 1970 1971 /* Handle errors for ECP reads */ 1972 static void 1973 atppc_ecp_read_error(struct atppc_softc *atppc) 1974 { 1975 unsigned char ecr = atppc_r_ecr(atppc); 1976 1977 /* Abort DMA if not finished */ 1978 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 1979 atppc->sc_dma_abort(atppc); 1980 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 1981 } 1982 1983 /* Check for invalid states */ 1984 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 1985 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 1986 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 1987 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1988 atppc_barrier_w(atppc); 1989 } 1990 } 1991 1992 /* 1993 * Functions that write bytes to port from buffer: called from atppc_write() 1994 * function depending on current chipset mode. Returns number of bytes moved. 1995 */ 1996 1997 /* Write bytes in std/bidirectional mode */ 1998 static void 1999 atppc_std_write(struct atppc_softc * const atppc) 2000 { 2001 unsigned int timecount; 2002 unsigned char ctr; 2003 2004 ctr = atppc_r_ctr(atppc); 2005 atppc_barrier_r(atppc); 2006 /* Enable interrupts if needed */ 2007 if (atppc->sc_use & ATPPC_USE_INTR) { 2008 if (!(ctr & IRQENABLE)) { 2009 ctr |= IRQENABLE; 2010 atppc_w_ctr(atppc, ctr); 2011 atppc_barrier_w(atppc); 2012 } 2013 } 2014 2015 while (atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2016 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2017 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2018 if (atppc->sc_outerr) 2019 return; 2020 2021 /* Put data in data register */ 2022 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2023 atppc_barrier_w(atppc); 2024 DELAY(1); 2025 2026 /* Pulse strobe to indicate valid data on lines */ 2027 ctr |= STROBE; 2028 atppc_w_ctr(atppc, ctr); 2029 atppc_barrier_w(atppc); 2030 DELAY(1); 2031 ctr &= ~STROBE; 2032 atppc_w_ctr(atppc, ctr); 2033 atppc_barrier_w(atppc); 2034 2035 /* Wait for nACK for MAXBUSYWAIT */ 2036 timecount = 0; 2037 if (atppc->sc_use & ATPPC_USE_INTR) { 2038 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2039 atppc->sc_outb, ATPPC_IRQ_nACK); 2040 if (atppc->sc_outerr) 2041 return; 2042 } else { 2043 /* Try to catch the pulsed acknowledgement */ 2044 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2045 if (atppc->sc_outerr) 2046 return; 2047 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2048 if (atppc->sc_outerr) 2049 return; 2050 } 2051 2052 /* Update buffer position, byte count and counter */ 2053 atppc->sc_outbstart++; 2054 } 2055 } 2056 2057 2058 /* Write bytes in EPP mode */ 2059 static void 2060 atppc_epp_write(struct atppc_softc *atppc) 2061 { 2062 if (atppc->sc_epp == ATPPC_EPP_1_9) { 2063 { 2064 uint8_t str; 2065 int i; 2066 2067 atppc_reset_epp_timeout((struct device *)atppc); 2068 for (i = 0; i < atppc->sc_outb_nbytes; i++) { 2069 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2070 atppc_barrier_w(atppc); 2071 str = atppc_r_str(atppc); 2072 atppc_barrier_r(atppc); 2073 if (str & TIMEOUT) { 2074 atppc->sc_outerr = EIO; 2075 break; 2076 } 2077 atppc->sc_outbstart++; 2078 } 2079 } 2080 } else { 2081 /* Write data block to EPP data register */ 2082 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2083 atppc->sc_outb_nbytes); 2084 atppc_barrier_w(atppc); 2085 /* Update buffer position, byte count and counter */ 2086 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2087 } 2088 2089 return; 2090 } 2091 2092 2093 /* Write bytes in ECP/Fast Centronics mode */ 2094 static void 2095 atppc_fifo_write(struct atppc_softc * const atppc) 2096 { 2097 unsigned char ctr; 2098 unsigned char ecr; 2099 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2100 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2101 2102 ctr = ctr_sav; 2103 ecr = ecr_sav; 2104 atppc_barrier_r(atppc); 2105 2106 /* Reset and flush FIFO */ 2107 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2108 atppc_barrier_w(atppc); 2109 /* Disable nAck interrupts and initialize port bits */ 2110 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2111 atppc_w_ctr(atppc, ctr); 2112 atppc_barrier_w(atppc); 2113 /* Restore mode */ 2114 atppc_w_ecr(atppc, ecr); 2115 atppc_barrier_w(atppc); 2116 2117 /* DMA or Programmed IO */ 2118 if ((atppc->sc_use & ATPPC_USE_DMA) && 2119 (atppc->sc_use & ATPPC_USE_INTR)) { 2120 2121 atppc_fifo_write_dma(atppc, ecr, ctr); 2122 } else { 2123 atppc_fifo_write_pio(atppc, ecr, ctr); 2124 } 2125 2126 /* Restore original register values */ 2127 atppc_w_ctr(atppc, ctr_sav); 2128 atppc_w_ecr(atppc, ecr_sav); 2129 atppc_barrier_w(atppc); 2130 } 2131 2132 static void 2133 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2134 unsigned char ctr) 2135 { 2136 unsigned int len; 2137 unsigned int worklen; 2138 2139 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2140 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2141 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2142 2143 /* Wait for device to become ready */ 2144 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2145 if (atppc->sc_outerr) 2146 return; 2147 2148 /* Reset chipset for next DMA transfer */ 2149 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2150 atppc_barrier_w(atppc); 2151 atppc_w_ecr(atppc, ecr); 2152 atppc_barrier_w(atppc); 2153 2154 /* Limit transfer to maximum DMA size and start it */ 2155 worklen = min(len, atppc->sc_dma_maxsize); 2156 atppc->sc_dmastat = ATPPC_DMA_INIT; 2157 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2158 worklen, ATPPC_DMA_MODE_WRITE); 2159 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2160 2161 /* Enable interrupts, DMA */ 2162 ecr &= ~ATPPC_SERVICE_INTR; 2163 ecr |= ATPPC_ENABLE_DMA; 2164 atppc_w_ecr(atppc, ecr); 2165 atppc_barrier_w(atppc); 2166 2167 /* Wait for DMA completion */ 2168 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2169 ATPPC_IRQ_DMA); 2170 if (atppc->sc_outerr) { 2171 atppc_fifo_write_error(atppc, worklen); 2172 return; 2173 } 2174 /* Get register value recorded by interrupt handler */ 2175 ecr = atppc->sc_ecr_intr; 2176 /* Clear DMA programming */ 2177 atppc->sc_dma_finish(atppc); 2178 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2179 /* Disable DMA */ 2180 ecr &= ~ATPPC_ENABLE_DMA; 2181 atppc_w_ecr(atppc, ecr); 2182 atppc_barrier_w(atppc); 2183 2184 /* Wait for FIFO to empty */ 2185 for (;;) { 2186 if (ecr & ATPPC_FIFO_EMPTY) { 2187 if (ecr & ATPPC_FIFO_FULL) { 2188 atppc->sc_outerr = EIO; 2189 atppc_fifo_write_error(atppc, worklen); 2190 return; 2191 } else { 2192 break; 2193 } 2194 } 2195 2196 /* Enable service interrupt */ 2197 ecr &= ~ATPPC_SERVICE_INTR; 2198 atppc_w_ecr(atppc, ecr); 2199 atppc_barrier_w(atppc); 2200 2201 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2202 atppc->sc_outb, ATPPC_IRQ_FIFO); 2203 if (atppc->sc_outerr) { 2204 atppc_fifo_write_error(atppc, worklen); 2205 return; 2206 } 2207 2208 /* Get register value recorded by interrupt handler */ 2209 ecr = atppc->sc_ecr_intr; 2210 } 2211 2212 /* Update pointer */ 2213 atppc->sc_outbstart += worklen; 2214 } 2215 } 2216 2217 static void 2218 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2219 unsigned char ctr) 2220 { 2221 unsigned int len; 2222 unsigned int worklen; 2223 unsigned int timecount; 2224 2225 /* Disable DMA */ 2226 ecr &= ~ATPPC_ENABLE_DMA; 2227 atppc_w_ecr(atppc, ecr); 2228 atppc_barrier_w(atppc); 2229 2230 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2231 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2232 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2233 2234 /* Wait for device to become ready */ 2235 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2236 if (atppc->sc_outerr) 2237 return; 2238 2239 /* Limit transfer to minimum of space in FIFO and buffer */ 2240 worklen = min(len, atppc->sc_fifo); 2241 2242 /* Write to FIFO */ 2243 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2244 2245 timecount = 0; 2246 if (atppc->sc_use & ATPPC_USE_INTR) { 2247 ecr = atppc_r_ecr(atppc); 2248 atppc_barrier_w(atppc); 2249 2250 /* Wait for interrupt */ 2251 for (;;) { 2252 if (ecr & ATPPC_FIFO_EMPTY) { 2253 if (ecr & ATPPC_FIFO_FULL) { 2254 atppc->sc_outerr = EIO; 2255 atppc_fifo_write_error(atppc, 2256 worklen); 2257 return; 2258 } else { 2259 break; 2260 } 2261 } 2262 2263 /* Enable service interrupt */ 2264 ecr &= ~ATPPC_SERVICE_INTR; 2265 atppc_w_ecr(atppc, ecr); 2266 atppc_barrier_w(atppc); 2267 2268 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2269 atppc->sc_outb, ATPPC_IRQ_FIFO); 2270 if (atppc->sc_outerr) { 2271 atppc_fifo_write_error(atppc, worklen); 2272 return; 2273 } 2274 2275 /* Get ECR value saved by interrupt handler */ 2276 ecr = atppc->sc_ecr_intr; 2277 } 2278 } else { 2279 for (; timecount < ((MAXBUSYWAIT/hz)*1000000); 2280 timecount++) { 2281 2282 ecr = atppc_r_ecr(atppc); 2283 atppc_barrier_r(atppc); 2284 if (ecr & ATPPC_FIFO_EMPTY) { 2285 if (ecr & ATPPC_FIFO_FULL) { 2286 atppc->sc_outerr = EIO; 2287 atppc_fifo_write_error(atppc, 2288 worklen); 2289 return; 2290 } else { 2291 break; 2292 } 2293 } 2294 DELAY(1); 2295 } 2296 2297 if (((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2298 atppc->sc_outerr = EIO; 2299 atppc_fifo_write_error(atppc, worklen); 2300 return; 2301 } 2302 } 2303 2304 /* Update pointer */ 2305 atppc->sc_outbstart += worklen; 2306 } 2307 } 2308 2309 static void 2310 atppc_fifo_write_error(struct atppc_softc * const atppc, 2311 const unsigned int worklen) 2312 { 2313 unsigned char ecr = atppc_r_ecr(atppc); 2314 2315 /* Abort DMA if not finished */ 2316 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2317 atppc->sc_dma_abort(atppc); 2318 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2319 } 2320 2321 /* Check for invalid states */ 2322 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2323 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2324 } else if (!(ecr & ATPPC_FIFO_EMPTY)) { 2325 unsigned char ctr = atppc_r_ctr(atppc); 2326 int bytes_left; 2327 int i; 2328 2329 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2330 atppc->sc_dev.dv_xname)); 2331 2332 /* Drive strobe low to stop data transfer */ 2333 ctr &= ~STROBE; 2334 atppc_w_ctr(atppc, ctr); 2335 atppc_barrier_w(atppc); 2336 2337 /* Determine how many bytes remain in FIFO */ 2338 for (i = 0; i < atppc->sc_fifo; i++) { 2339 atppc_w_fifo(atppc, (unsigned char)i); 2340 ecr = atppc_r_ecr(atppc); 2341 atppc_barrier_r(atppc); 2342 if (ecr & ATPPC_FIFO_FULL) 2343 break; 2344 } 2345 bytes_left = (atppc->sc_fifo) - (i + 1); 2346 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2347 bytes_left)); 2348 2349 /* Update counter */ 2350 atppc->sc_outbstart += (worklen - bytes_left); 2351 } else { 2352 /* Update counter */ 2353 atppc->sc_outbstart += worklen; 2354 } 2355 2356 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2357 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2358 atppc_barrier_w(atppc); 2359 } 2360 2361 /* 2362 * Poll status register using mask and status for MAXBUSYWAIT. 2363 * Returns 0 if device ready, error value otherwise. 2364 */ 2365 static int 2366 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2367 const u_int8_t mask) 2368 { 2369 unsigned int timecount; 2370 u_int8_t str; 2371 int error = EIO; 2372 2373 /* Wait for str to have status for MAXBUSYWAIT */ 2374 for (timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2375 timecount++) { 2376 2377 str = atppc_r_str(atppc); 2378 atppc_barrier_r(atppc); 2379 if ((str & mask) == status) { 2380 error = 0; 2381 break; 2382 } 2383 DELAY(1); 2384 } 2385 2386 return error; 2387 } 2388 2389 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2390 static int 2391 atppc_wait_interrupt(struct atppc_softc * const atppc, const void *where, 2392 const u_int8_t irqstat) 2393 { 2394 int error = EIO; 2395 2396 atppc->sc_irqstat &= ~irqstat; 2397 2398 /* Wait for interrupt for MAXBUSYWAIT */ 2399 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2400 ATPPC_SC_LOCK(atppc)); 2401 2402 if (!(error) && (atppc->sc_irqstat & irqstat)) { 2403 atppc->sc_irqstat &= ~irqstat; 2404 error = 0; 2405 } 2406 2407 return error; 2408 } 2409
Indexes created Fri Sep 26 08:10:20 GMT 2025