atppc.c revision 1.3
1 /* $NetBSD: atppc.c,v 1.3 2004/01/21 00:33:37 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $ 29 * 30 */ 31 32 #include "opt_atppc.h" 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/systm.h> 41 #include <sys/vnode.h> 42 #include <sys/syslog.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/isa/isareg.h> 48 #include <dev/isa/isavar.h> 49 50 #include <dev/ic/atppcreg.h> 51 #include <dev/ic/atppcvar.h> 52 53 #include <dev/ppbus/ppbus_conf.h> 54 #include <dev/ppbus/ppbus_msq.h> 55 #include <dev/ppbus/ppbus_io.h> 56 #include <dev/ppbus/ppbus_var.h> 57 58 #ifdef ATPPC_DEBUG 59 int atppc_debug = 1; 60 #endif 61 62 #ifdef ATPPC_VERBOSE 63 int atppc_verbose = 1; 64 #endif 65 66 /* List of supported chipsets detection routines */ 67 static int (*chipset_detect[])(struct atppc_softc *) = { 68 /* XXX Add these LATER: maybe as seperate devices? 69 atppc_pc873xx_detect, 70 atppc_smc37c66xgt_detect, 71 atppc_w83877f_detect, 72 atppc_smc37c935_detect, 73 */ 74 NULL 75 }; 76 77 78 /* Prototypes for functions. */ 79 80 /* Soft configuration attach */ 81 void atppc_sc_attach(struct atppc_softc *); 82 int atppc_sc_detach(struct atppc_softc *, int); 83 84 /* Interrupt handler for atppc device */ 85 int atppcintr(void *); 86 87 /* Print function for config_found_sm() */ 88 static int atppc_print(void * aux, const char * name); 89 90 /* Detection routines */ 91 static int atppc_detect_fifo(struct atppc_softc *); 92 static int atppc_detect_chipset(struct atppc_softc *); 93 static int atppc_detect_generic(struct atppc_softc *); 94 95 /* Routines for ppbus interface (bus + device) */ 96 static int atppc_read(struct device *, char *, int, int, size_t *); 97 static int atppc_write(struct device *, char *, int, int, size_t *); 98 static int atppc_setmode(struct device *, int); 99 static int atppc_getmode(struct device *); 100 static int atppc_check_epp_timeout(struct device *); 101 static void atppc_reset_epp_timeout(struct device *); 102 static void atppc_ecp_sync(struct device *); 103 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 104 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 105 static int atppc_read_ivar(struct device *, int, unsigned int *); 106 static int atppc_write_ivar(struct device *, int, unsigned int *); 107 static int atppc_add_handler(struct device *, void (*)(void *), void *); 108 static int atppc_remove_handler(struct device *, void (*)(void *)); 109 110 /* Utility functions */ 111 112 /* Functions to read bytes into device's input buffer */ 113 static void atppc_nibble_read(struct atppc_softc * const); 114 static void atppc_byte_read(struct atppc_softc * const); 115 static void atppc_epp_read(struct atppc_softc * const); 116 static void atppc_ecp_read(struct atppc_softc * const); 117 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 118 unsigned char); 119 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 120 unsigned char); 121 static void atppc_ecp_read_error(struct atppc_softc *, const unsigned int); 122 123 124 /* Functions to write bytes to device's output buffer */ 125 static void atppc_std_write(struct atppc_softc * const); 126 static void atppc_epp_write(struct atppc_softc * const); 127 static void atppc_fifo_write(struct atppc_softc * const); 128 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 129 unsigned char); 130 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 131 unsigned char); 132 static void atppc_fifo_write_error(struct atppc_softc * const, 133 const unsigned int); 134 135 /* Miscellaneous */ 136 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 137 const u_int8_t); 138 static int atppc_wait_interrupt(struct atppc_softc * const, const caddr_t, 139 const u_int8_t); 140 141 142 /* 143 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 144 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 145 */ 146 147 /* Soft configuration attach for atppc */ 148 void 149 atppc_sc_attach(struct atppc_softc * lsc) 150 { 151 /* Adapter used to configure ppbus device */ 152 struct parport_adapter sc_parport_adapter; 153 struct device * dev = (struct device *) lsc; 154 #ifdef ATPPC_VERBOSE 155 char buf[64]; 156 #endif 157 158 printf("\n"); 159 160 /* Probe and set up chipset */ 161 if(atppc_detect_chipset(lsc) != 0) { 162 if(atppc_detect_generic(lsc) != 0) { 163 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 164 dev->dv_xname)); 165 } 166 } 167 168 /* Probe and setup FIFO queue */ 169 if(atppc_detect_fifo(lsc) == 0) { 170 ATPPC_VPRINTF(("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 171 dev->dv_xname, lsc->sc_fifo, lsc->sc_wthr, 172 lsc->sc_rthr)); 173 } 174 175 #ifdef ATPPC_VERBOSE 176 /* Print out chipset capabilities */ 177 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 178 buf, sizeof(buf)); 179 ATPPC_VPRINTF(("%s: capabilities=%s\n", dev->dv_xname, buf)); 180 #endif 181 182 /* Initialize device's buffer pointers */ 183 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 184 = NULL; 185 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 186 187 /* Last configuration step: set mode to standard mode */ 188 if(atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 189 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 190 dev->dv_xname)); 191 } 192 193 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 194 /* Initialize lock structure */ 195 simple_lock_init(&(lsc->sc_lock)); 196 #endif 197 198 /* Set up parport_adapter structure */ 199 200 /* Set capabilites */ 201 sc_parport_adapter.capabilities = 0; 202 if(lsc->sc_has & ATPPC_HAS_INTR) { 203 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 204 } 205 if(lsc->sc_has & ATPPC_HAS_DMA) { 206 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 207 } 208 if(lsc->sc_has & ATPPC_HAS_FIFO) { 209 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 210 } 211 if(lsc->sc_has & ATPPC_HAS_PS2) { 212 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 213 } 214 if(lsc->sc_has & ATPPC_HAS_EPP) { 215 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 216 } 217 if(lsc->sc_has & ATPPC_HAS_ECP) { 218 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 219 } 220 221 /* Set function pointers */ 222 sc_parport_adapter.parport_io = atppc_io; 223 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 224 sc_parport_adapter.parport_reset_epp_timeout = 225 atppc_reset_epp_timeout; 226 sc_parport_adapter.parport_setmode = atppc_setmode; 227 sc_parport_adapter.parport_getmode = atppc_getmode; 228 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 229 sc_parport_adapter.parport_read = atppc_read; 230 sc_parport_adapter.parport_write = atppc_write; 231 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 232 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 233 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 234 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 235 sc_parport_adapter.parport_add_handler = atppc_add_handler; 236 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 237 238 /* Initialize handler list, may be added to by grandchildren */ 239 SLIST_INIT(&(lsc->sc_handler_listhead)); 240 241 /* Initialize interrupt state */ 242 lsc->sc_irqstat = ATPPC_IRQ_NONE; 243 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 244 245 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 246 lsc->sc_use = 0; 247 248 /* Configure child of the device. */ 249 lsc->child = config_found_sm(&(lsc->sc_dev), &(sc_parport_adapter), 250 atppc_print, NULL); 251 252 return; 253 } 254 255 /* Soft configuration detach */ 256 int atppc_sc_detach(struct atppc_softc * lsc, int flag) 257 { 258 struct device * dev = (struct device *) lsc; 259 260 /* Detach children devices */ 261 if(config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 262 printf("%s not able to detach child device, ", dev->dv_xname); 263 264 if(!(flag & DETACH_FORCE)) { 265 printf("cannot detach\n"); 266 return 1; 267 } 268 else { 269 printf("continuing (DETACH_FORCE)\n"); 270 } 271 } 272 273 if(!(flag & DETACH_QUIET)) 274 printf("%s detached", dev->dv_xname); 275 276 return 0; 277 } 278 279 /* Used by config_found_sm() to print out device information */ 280 static int 281 atppc_print(void * aux, const char * name) 282 { 283 /* Print out something on failure. */ 284 if(name != NULL) { 285 printf("%s: child devices", name); 286 return UNCONF; 287 } 288 289 return QUIET; 290 } 291 292 /* 293 * Machine independent detection routines for atppc driver. 294 */ 295 296 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 297 int 298 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 299 { 300 /* 301 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() * in original lpt driver. 302 * Write to data register common to all controllers and read back the 303 * values. Also tests control and status registers. 304 */ 305 306 /* 307 * Cannot use convenient macros because the device's config structure 308 * may not have been created yet: major change from FreeBSD code. 309 */ 310 311 int rval; 312 u_int8_t ctr_sav, dtr_sav, str_sav; 313 314 /* Store writtable registers' values and test if they can be read */ 315 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 316 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 317 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 318 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 319 BUS_SPACE_BARRIER_READ); 320 321 /* 322 * Ensure PS2 ports in output mode, also read back value of control 323 * register. 324 */ 325 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 326 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 327 BUS_SPACE_BARRIER_WRITE); 328 329 if(bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 330 rval = 0; 331 } 332 else { 333 /* 334 * Test if two values can be written and read from the data 335 * register. 336 */ 337 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 338 BUS_SPACE_BARRIER_READ); 339 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 340 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 341 BUS_SPACE_BARRIER_WRITE); 342 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 343 rval = 1; 344 } 345 else { 346 /* Second value to test */ 347 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 348 BUS_SPACE_BARRIER_READ); 349 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 350 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 351 BUS_SPACE_BARRIER_WRITE); 352 if(bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 353 rval = 1; 354 } 355 else { 356 rval = 0; 357 } 358 } 359 360 } 361 362 /* Restore registers */ 363 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 364 BUS_SPACE_BARRIER_READ); 365 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 366 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 367 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 368 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 369 BUS_SPACE_BARRIER_WRITE); 370 371 return rval; 372 } 373 374 /* Detect parallel port chipset. */ 375 static int 376 atppc_detect_chipset(struct atppc_softc * atppc) 377 { 378 /* Try each detection routine. */ 379 int i, mode; 380 for (i = 0; chipset_detect[i] != NULL; i++) { 381 if ((mode = chipset_detect[i](atppc)) != -1) { 382 atppc->sc_mode = mode; 383 return 0; 384 } 385 } 386 387 return 1; 388 } 389 390 /* Detect generic capabilities. */ 391 static int 392 atppc_detect_generic(struct atppc_softc * atppc) 393 { 394 u_int8_t ecr_sav = atppc_r_ecr(atppc); 395 u_int8_t ctr_sav = atppc_r_ctr(atppc); 396 u_int8_t str_sav = atppc_r_str(atppc); 397 u_int8_t tmp; 398 atppc_barrier_r(atppc); 399 400 /* Default to generic */ 401 atppc->sc_type = ATPPC_TYPE_GENERIC; 402 atppc->sc_model = GENERIC; 403 404 /* Check for ECP */ 405 tmp = atppc_r_ecr(atppc); 406 atppc_barrier_r(atppc); 407 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 408 atppc_w_ecr(atppc, 0x34); 409 atppc_barrier_w(atppc); 410 tmp = atppc_r_ecr(atppc); 411 atppc_barrier_r(atppc); 412 if(tmp == 0x35) { 413 atppc->sc_has |= ATPPC_HAS_ECP; 414 } 415 } 416 417 /* Allow search for SMC style ECP+EPP mode */ 418 if(atppc->sc_has & ATPPC_HAS_ECP) { 419 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 420 atppc_barrier_w(atppc); 421 } 422 /* Check for EPP by checking for timeout bit */ 423 if(atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 424 atppc->sc_has |= ATPPC_HAS_EPP; 425 atppc->sc_epp = ATPPC_EPP_1_9; 426 if(atppc->sc_has & ATPPC_HAS_ECP) { 427 /* SMC like chipset found */ 428 atppc->sc_model = SMC_LIKE; 429 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 430 } 431 } 432 433 /* Detect PS2 mode */ 434 if(atppc->sc_has & ATPPC_HAS_ECP) { 435 /* Put ECP port into PS2 mode */ 436 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 437 atppc_barrier_w(atppc); 438 } 439 /* Put PS2 port in input mode: writes should not be readable */ 440 atppc_w_ctr(atppc, 0x20); 441 atppc_barrier_w(atppc); 442 /* 443 * Write two values to data port: if neither are read back, 444 * bidirectional mode is functional. 445 */ 446 atppc_w_dtr(atppc, 0xaa); 447 atppc_barrier_w(atppc); 448 tmp = atppc_r_dtr(atppc); 449 atppc_barrier_r(atppc); 450 if(tmp != 0xaa) { 451 atppc_w_dtr(atppc, 0x55); 452 atppc_barrier_w(atppc); 453 tmp = atppc_r_dtr(atppc); 454 atppc_barrier_r(atppc); 455 if(tmp != 0x55) { 456 atppc->sc_has |= ATPPC_HAS_PS2; 457 } 458 } 459 460 /* Restore to previous state */ 461 atppc_w_ecr(atppc, ecr_sav); 462 atppc_w_ctr(atppc, ctr_sav); 463 atppc_w_str(atppc, str_sav); 464 atppc_barrier_w(atppc); 465 466 return 0; 467 } 468 469 /* 470 * Detect parallel port FIFO: taken from FreeBSD code directly. 471 */ 472 static int 473 atppc_detect_fifo(struct atppc_softc * atppc) 474 { 475 #ifdef ATPPC_DEBUG 476 struct device * dev = (struct device *)atppc; 477 #endif 478 u_int8_t ecr_sav; 479 u_int8_t ctr_sav; 480 u_int8_t str_sav; 481 u_int8_t cc; 482 short i; 483 484 /* If there is no ECP mode, we cannot config a FIFO */ 485 if(!(atppc->sc_has & ATPPC_HAS_ECP)) { 486 return (EINVAL); 487 } 488 489 /* save registers */ 490 ecr_sav = atppc_r_ecr(atppc); 491 ctr_sav = atppc_r_ctr(atppc); 492 str_sav = atppc_r_str(atppc); 493 atppc_barrier_r(atppc); 494 495 /* Enter ECP configuration mode, no interrupt, no DMA */ 496 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 497 ~ATPPC_ENABLE_DMA); 498 atppc_barrier_w(atppc); 499 500 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 501 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 502 atppc_barrier_r(atppc); 503 504 /* XXX 16 and 32 bits implementations not supported */ 505 if(atppc->sc_pword != ATPPC_PWORD_8) { 506 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 507 __func__, dev->dv_xname, atppc->sc_pword)); 508 goto error; 509 } 510 511 /* Byte mode, reverse direction, no interrupt, no DMA */ 512 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 513 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 514 /* enter ECP test mode, no interrupt, no DMA */ 515 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 516 atppc_barrier_w(atppc); 517 518 /* flush the FIFO */ 519 for (i = 0; i < 1024; i++) { 520 atppc_r_fifo(atppc); 521 atppc_barrier_r(atppc); 522 cc = atppc_r_ecr(atppc); 523 atppc_barrier_r(atppc); 524 if(cc & ATPPC_FIFO_EMPTY) 525 break; 526 } 527 if (i >= 1024) { 528 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 529 dev->dv_xname)); 530 goto error; 531 } 532 533 /* Test mode, enable interrupts, no DMA */ 534 atppc_w_ecr(atppc, ATPPC_ECR_TST); 535 atppc_barrier_w(atppc); 536 537 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 538 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 539 atppc_w_fifo(atppc, (char)i); 540 atppc_barrier_w(atppc); 541 cc = atppc_r_ecr(atppc); 542 atppc_barrier_r(atppc); 543 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 544 /* readThreshold reached */ 545 atppc->sc_rthr = i + 1; 546 } 547 if (cc & ATPPC_FIFO_FULL) { 548 atppc->sc_fifo = i + 1; 549 break; 550 } 551 } 552 if (i >= 1024) { 553 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 554 dev->dv_xname)); 555 goto error; 556 } 557 558 /* Change direction */ 559 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 560 atppc_barrier_w(atppc); 561 562 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 563 for(atppc->sc_wthr = 0; i > -1; i--) { 564 cc = atppc_r_fifo(atppc); 565 atppc_barrier_r(atppc); 566 if(cc != (char)(atppc->sc_fifo - i - 1)) { 567 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 568 __func__, dev->dv_xname)); 569 goto error; 570 } 571 572 cc = atppc_r_ecr(atppc); 573 atppc_barrier_r(atppc); 574 if((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 575 /* writeIntrThreshold reached */ 576 atppc->sc_wthr = atppc->sc_fifo - i; 577 } 578 579 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 580 /* If FIFO empty before the last byte, error */ 581 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 582 dev->dv_xname)); 583 goto error; 584 } 585 } 586 587 /* FIFO must be empty after the last byte */ 588 cc = atppc_r_ecr(atppc); 589 atppc_barrier_r(atppc); 590 if (!(cc & ATPPC_FIFO_EMPTY)) { 591 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 592 dev->dv_xname)); 593 goto error; 594 } 595 596 /* Restore original registers */ 597 atppc_w_ctr(atppc, ctr_sav); 598 atppc_w_str(atppc, str_sav); 599 atppc_w_ecr(atppc, ecr_sav); 600 atppc_barrier_w(atppc); 601 602 /* Update capabilities */ 603 atppc->sc_has |= ATPPC_HAS_FIFO; 604 605 return 0; 606 607 error: 608 /* Restore original registers */ 609 atppc_w_ctr(atppc, ctr_sav); 610 atppc_w_str(atppc, str_sav); 611 atppc_w_ecr(atppc, ecr_sav); 612 atppc_barrier_w(atppc); 613 614 return (EINVAL); 615 } 616 617 /* Interrupt handler for atppc device: wakes up read/write functions */ 618 int 619 atppcintr(void * arg) 620 { 621 struct atppc_softc * atppc = (struct atppc_softc *) arg; 622 struct device * dev = (struct device *) arg; 623 int error = 1; 624 enum { NONE, READER, WRITER } wake_up = NONE; 625 int s; 626 627 s = splatppc(); 628 ATPPC_LOCK(atppc); 629 630 /* Record registers' status */ 631 atppc->sc_str_intr = atppc_r_str(atppc); 632 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 633 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 634 atppc_barrier_r(atppc); 635 636 /* Determine cause of interrupt and wake up top half */ 637 switch(atppc->sc_mode) { 638 case ATPPC_MODE_STD: 639 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 640 atppc->sc_irqstat = ATPPC_IRQ_nACK; 641 if(atppc->sc_outb) 642 wake_up = WRITER; 643 else 644 error = -1; 645 break; 646 647 case ATPPC_MODE_NIBBLE: 648 case ATPPC_MODE_PS2: 649 /* nAck is set low by device and then high on ack */ 650 if(!(atppc->sc_str_intr & nACK)) { 651 error = 0; 652 break; 653 } 654 atppc->sc_irqstat = ATPPC_IRQ_nACK; 655 if(atppc->sc_inb) 656 wake_up = READER; 657 else 658 error = -1; 659 break; 660 661 case ATPPC_MODE_ECP: 662 case ATPPC_MODE_FAST: 663 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 664 if(atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 665 if(atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 666 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 667 else 668 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 669 670 /* Decide where top half will be waiting */ 671 if(atppc->sc_mode & ATPPC_MODE_ECP) { 672 if(atppc->sc_ctr_intr & PCD) { 673 if(atppc->sc_inb) 674 wake_up = READER; 675 else 676 error = -1; 677 } 678 else { 679 if(atppc->sc_outb) 680 wake_up = WRITER; 681 else 682 error = -1; 683 } 684 } 685 else { 686 if(atppc->sc_outb) 687 wake_up = WRITER; 688 else 689 error = -1; 690 } 691 } 692 /* Determine if nFault has occured */ 693 if((atppc->sc_mode & ATPPC_MODE_ECP) && 694 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 695 !(atppc->sc_str_intr & nFAULT)) { 696 697 /* Device is requesting the channel */ 698 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 699 } 700 break; 701 702 case ATPPC_MODE_EPP: 703 /* nAck pulsed for 5 usec, too fast to check reliably */ 704 atppc->sc_irqstat = ATPPC_IRQ_nACK; 705 if(atppc->sc_inb) 706 wake_up = WRITER; 707 else if(atppc->sc_outb) 708 wake_up = READER; 709 else 710 error = -1; 711 break; 712 713 default: 714 panic("%s: chipset is in invalid mode.", dev->dv_xname); 715 } 716 717 switch(wake_up) { 718 case NONE: 719 break; 720 721 case READER: 722 wakeup(atppc->sc_inb); 723 break; 724 725 case WRITER: 726 wakeup(atppc->sc_outb); 727 break; 728 729 default: 730 panic("%s: this code should not be reached.\n", __func__); 731 break; 732 } 733 734 ATPPC_UNLOCK(atppc); 735 736 /* Call all of the installed handlers */ 737 { 738 struct atppc_handler_node * callback; 739 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 740 entries) { 741 (*callback->func)(callback->arg); 742 } 743 } 744 745 splx(s); 746 747 return error; 748 } 749 750 751 /* Functions which support ppbus interface */ 752 753 754 /* Check EPP mode timeout */ 755 static int 756 atppc_check_epp_timeout(struct device * dev) 757 { 758 struct atppc_softc * atppc = (struct atppc_softc *) dev; 759 int s; 760 int error; 761 762 s = splatppc(); 763 ATPPC_LOCK(atppc); 764 765 atppc_reset_epp_timeout(dev); 766 error = !(atppc_r_str(atppc) & TIMEOUT); 767 atppc_barrier_r(atppc); 768 769 ATPPC_UNLOCK(atppc); 770 splx(s); 771 772 return (error); 773 } 774 775 /* 776 * EPP timeout, according to the PC87332 manual 777 * Semantics of clearing EPP timeout bit. 778 * PC87332 - reading SPP_STR does it... 779 * SMC - write 1 to EPP timeout bit XXX 780 * Others - (?) write 0 to EPP timeout bit 781 */ 782 static void 783 atppc_reset_epp_timeout(struct device * dev) 784 { 785 struct atppc_softc * atppc = (struct atppc_softc *) dev; 786 register unsigned char r; 787 788 r = atppc_r_str(atppc); 789 atppc_barrier_r(atppc); 790 atppc_w_str(atppc, r | 0x1); 791 atppc_barrier_w(atppc); 792 atppc_w_str(atppc, r & 0xfe); 793 atppc_barrier_w(atppc); 794 795 return; 796 } 797 798 799 /* Read from atppc device: returns 0 on success. */ 800 static int 801 atppc_read(struct device * dev, char * buf, int len, int ioflag, 802 size_t * cnt) 803 { 804 struct atppc_softc * atppc = (struct atppc_softc *) dev; 805 int error = 0; 806 int s; 807 808 s = splatppc(); 809 ATPPC_LOCK(atppc); 810 811 *cnt = 0; 812 813 /* Initialize buffer */ 814 atppc->sc_inb = atppc->sc_inbstart = buf; 815 atppc->sc_inb_nbytes = len; 816 817 /* Initialize device input error state for new operation */ 818 atppc->sc_inerr = 0; 819 820 /* Call appropriate function to read bytes */ 821 switch(atppc->sc_mode) { 822 case ATPPC_MODE_STD: 823 case ATPPC_MODE_FAST: 824 error = ENODEV; 825 break; 826 827 case ATPPC_MODE_NIBBLE: 828 atppc_nibble_read(atppc); 829 break; 830 831 case ATPPC_MODE_PS2: 832 atppc_byte_read(atppc); 833 break; 834 835 case ATPPC_MODE_ECP: 836 atppc_ecp_read(atppc); 837 break; 838 839 case ATPPC_MODE_EPP: 840 atppc_epp_read(atppc); 841 break; 842 843 default: 844 panic("%s(%s): chipset in invalid mode.\n", __func__, 845 dev->dv_xname); 846 } 847 848 /* Update counter*/ 849 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 850 851 /* Reset buffer */ 852 atppc->sc_inb = atppc->sc_inbstart = NULL; 853 atppc->sc_inb_nbytes = 0; 854 855 if(!(error)) 856 error = atppc->sc_inerr; 857 858 ATPPC_UNLOCK(atppc); 859 splx(s); 860 861 return (error); 862 } 863 864 /* Write to atppc device: returns 0 on success. */ 865 static int 866 atppc_write(struct device * dev, char * buf, int len, int ioflag, size_t * cnt) 867 { 868 struct atppc_softc * const atppc = (struct atppc_softc *) dev; 869 int error = 0; 870 int s; 871 872 *cnt = 0; 873 874 s = splatppc(); 875 ATPPC_LOCK(atppc); 876 877 /* Set up line buffer */ 878 atppc->sc_outb = atppc->sc_outbstart = buf; 879 atppc->sc_outb_nbytes = len; 880 881 /* Initialize device output error state for new operation */ 882 atppc->sc_outerr = 0; 883 884 /* Call appropriate function to write bytes */ 885 switch(atppc->sc_mode) { 886 case ATPPC_MODE_STD: 887 atppc_std_write(atppc); 888 break; 889 890 case ATPPC_MODE_NIBBLE: 891 case ATPPC_MODE_PS2: 892 error = ENODEV; 893 break; 894 895 case ATPPC_MODE_FAST: 896 case ATPPC_MODE_ECP: 897 atppc_fifo_write(atppc); 898 break; 899 900 case ATPPC_MODE_EPP: 901 atppc_epp_write(atppc); 902 break; 903 904 default: 905 panic("%s(%s): chipset in invalid mode.\n", __func__, 906 dev->dv_xname); 907 } 908 909 /* Update counter*/ 910 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 911 912 /* Reset output buffer */ 913 atppc->sc_outb = atppc->sc_outbstart = NULL; 914 atppc->sc_outb_nbytes = 0; 915 916 if(!(error)) 917 error = atppc->sc_outerr; 918 919 ATPPC_UNLOCK(atppc); 920 splx(s); 921 922 return (error); 923 } 924 925 /* 926 * Set mode of chipset to mode argument. Modes not supported are ignored. If 927 * multiple modes are flagged, the mode is not changed. Mode's are those 928 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 929 * can change their mode of operation. However, ALL operation modes support 930 * centronics mode and nibble mode. Modes determine both hardware AND software 931 * behaviour. 932 * NOTE: the mode for ECP should only be changed when the channel is in 933 * forward idle mode. This function does not make sure FIFO's have flushed or 934 * any consistency checks. 935 */ 936 static int 937 atppc_setmode(struct device * dev, int mode) 938 { 939 struct atppc_softc * atppc = (struct atppc_softc *) dev; 940 u_int8_t ecr; 941 u_int8_t chipset_mode; 942 int s; 943 int rval = 0; 944 945 s = splatppc(); 946 ATPPC_LOCK(atppc); 947 948 /* If ECP capable, configure ecr register */ 949 if (atppc->sc_has & ATPPC_HAS_ECP) { 950 /* Read ECR with mode masked out */ 951 ecr = (atppc_r_ecr(atppc) & (unsigned)0x1f); 952 atppc_barrier_r(atppc); 953 954 switch(mode) { 955 case PPBUS_ECP: 956 /* Set ECP mode */ 957 ecr |= ATPPC_ECR_ECP; 958 chipset_mode = ATPPC_MODE_ECP; 959 break; 960 961 case PPBUS_EPP: 962 /* Set EPP mode */ 963 if(atppc->sc_has & ATPPC_HAS_EPP) { 964 ecr |= ATPPC_ECR_EPP; 965 chipset_mode = ATPPC_MODE_EPP; 966 } 967 else { 968 rval = ENODEV; 969 goto end; 970 } 971 break; 972 973 case PPBUS_FAST: 974 /* Set fast centronics mode */ 975 ecr |= ATPPC_ECR_FIFO; 976 chipset_mode = ATPPC_MODE_FAST; 977 break; 978 979 case PPBUS_PS2: 980 /* Set PS2 mode */ 981 ecr |= ATPPC_ECR_PS2; 982 chipset_mode = ATPPC_MODE_PS2; 983 break; 984 985 case PPBUS_COMPATIBLE: 986 /* Set standard mode */ 987 ecr |= ATPPC_ECR_STD; 988 chipset_mode = ATPPC_MODE_STD;; 989 break; 990 991 case PPBUS_NIBBLE: 992 /* Set nibble mode: uses chipset standard mode */ 993 ecr |= ATPPC_ECR_STD; 994 chipset_mode = ATPPC_MODE_NIBBLE; 995 break; 996 997 default: 998 /* Invalid mode specified for ECP chip */ 999 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1000 "argument.\n", __func__, dev->dv_xname)); 1001 rval = ENODEV; 1002 goto end; 1003 } 1004 1005 /* Switch to byte mode to be able to change modes. */ 1006 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1007 atppc_barrier_w(atppc); 1008 1009 /* Update mode */ 1010 atppc_w_ecr(atppc, ecr); 1011 atppc_barrier_w(atppc); 1012 } 1013 else { 1014 switch(mode) { 1015 case PPBUS_EPP: 1016 if(atppc->sc_has & ATPPC_HAS_EPP) { 1017 chipset_mode = ATPPC_MODE_EPP; 1018 } 1019 else { 1020 rval = ENODEV; 1021 goto end; 1022 } 1023 break; 1024 1025 case PPBUS_PS2: 1026 if(atppc->sc_has & ATPPC_HAS_PS2) { 1027 chipset_mode = ATPPC_MODE_PS2; 1028 } 1029 else { 1030 rval = ENODEV; 1031 goto end; 1032 } 1033 break; 1034 1035 case PPBUS_NIBBLE: 1036 /* Set nibble mode (virtual) */ 1037 chipset_mode = ATPPC_MODE_NIBBLE; 1038 break; 1039 1040 case PPBUS_COMPATIBLE: 1041 chipset_mode = ATPPC_MODE_STD; 1042 break; 1043 1044 case PPBUS_ECP: 1045 rval = ENODEV; 1046 goto end; 1047 1048 default: 1049 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1050 "argument.\n", __func__, dev->dv_xname)); 1051 rval = ENODEV; 1052 goto end; 1053 } 1054 } 1055 1056 atppc->sc_mode = chipset_mode; 1057 if(chipset_mode == ATPPC_MODE_PS2) { 1058 /* Set direction bit to reverse */ 1059 ecr = atppc_r_ctr(atppc); 1060 atppc_barrier_r(atppc); 1061 ecr |= PCD; 1062 atppc_w_ctr(atppc, ecr); 1063 atppc_barrier_w(atppc); 1064 } 1065 1066 end: 1067 ATPPC_UNLOCK(atppc); 1068 splx(s); 1069 1070 return rval; 1071 } 1072 1073 /* Get the current mode of chipset */ 1074 static int 1075 atppc_getmode(struct device * dev) 1076 { 1077 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1078 int mode; 1079 int s; 1080 1081 s = splatppc(); 1082 ATPPC_LOCK(atppc); 1083 1084 /* The chipset can only be in one mode at a time logically */ 1085 switch(atppc->sc_mode) { 1086 case ATPPC_MODE_ECP: 1087 mode = PPBUS_ECP; 1088 break; 1089 1090 case ATPPC_MODE_EPP: 1091 mode = PPBUS_EPP; 1092 break; 1093 1094 case ATPPC_MODE_PS2: 1095 mode = PPBUS_PS2; 1096 break; 1097 1098 case ATPPC_MODE_STD: 1099 mode = PPBUS_COMPATIBLE; 1100 break; 1101 1102 case ATPPC_MODE_NIBBLE: 1103 mode = PPBUS_NIBBLE; 1104 break; 1105 1106 case ATPPC_MODE_FAST: 1107 mode = PPBUS_FAST; 1108 break; 1109 1110 default: 1111 panic("%s(%s): device is in invalid mode!", __func__, 1112 dev->dv_xname); 1113 break; 1114 } 1115 1116 ATPPC_UNLOCK(atppc); 1117 splx(s); 1118 1119 return mode; 1120 } 1121 1122 1123 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1124 static void 1125 atppc_ecp_sync(struct device * dev) 1126 { 1127 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1128 int i; 1129 int s; 1130 u_int8_t r; 1131 1132 s = splatppc(); 1133 ATPPC_LOCK(atppc); 1134 1135 /* 1136 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1137 * the mode is either ECP or Fast Centronics. 1138 */ 1139 r = atppc_r_ecr(atppc); 1140 atppc_barrier_r(atppc); 1141 r &= 0xe0; 1142 if(!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1143 && (r != ATPPC_ECR_FIFO))) { 1144 goto end; 1145 } 1146 1147 /* Wait for FIFO to empty */ 1148 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1149 r = atppc_r_ecr(atppc); 1150 atppc_barrier_r(atppc); 1151 if (r & ATPPC_FIFO_EMPTY) { 1152 goto end; 1153 } 1154 delay(100); /* Supposed to be a 100 usec delay */ 1155 } 1156 1157 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1158 dev->dv_xname)); 1159 1160 end: 1161 ATPPC_UNLOCK(atppc); 1162 splx(s); 1163 1164 return; 1165 } 1166 1167 /* Execute a microsequence to handle fast I/O operations. */ 1168 static int 1169 atppc_exec_microseq(struct device * dev, struct ppbus_microseq * * p_msq) 1170 { 1171 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1172 struct ppbus_microseq * mi = *p_msq; 1173 char cc, * p; 1174 int i, iter, len; 1175 int error; 1176 int s; 1177 register int reg; 1178 register unsigned char mask; 1179 register int accum = 0; 1180 register char * ptr = NULL; 1181 struct ppbus_microseq * stack = NULL; 1182 1183 s = splatppc(); 1184 ATPPC_LOCK(atppc); 1185 1186 /* microsequence registers are equivalent to PC-like port registers */ 1187 1188 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1189 (atppc)->sc_ioh, (register)) 1190 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1191 (atppc)->sc_ioh, (register), (byte)) 1192 1193 /* Loop until microsequence execution finishes (ending op code) */ 1194 for (;;) { 1195 switch (mi->opcode) { 1196 case MS_OP_RSET: 1197 cc = r_reg(mi->arg[0].i, atppc); 1198 atppc_barrier_r(atppc); 1199 cc &= (char)mi->arg[2].i; /* clear mask */ 1200 cc |= (char)mi->arg[1].i; /* assert mask */ 1201 w_reg(mi->arg[0].i, atppc, cc); 1202 atppc_barrier_w(atppc); 1203 mi++; 1204 break; 1205 1206 case MS_OP_RASSERT_P: 1207 reg = mi->arg[1].i; 1208 ptr = atppc->sc_ptr; 1209 1210 if((len = mi->arg[0].i) == MS_ACCUM) { 1211 accum = atppc->sc_accum; 1212 for (; accum; accum--) { 1213 w_reg(reg, atppc, *ptr++); 1214 atppc_barrier_w(atppc); 1215 } 1216 atppc->sc_accum = accum; 1217 } 1218 else { 1219 for(i = 0; i < len; i++) { 1220 w_reg(reg, atppc, *ptr++); 1221 atppc_barrier_w(atppc); 1222 } 1223 } 1224 1225 atppc->sc_ptr = ptr; 1226 mi++; 1227 break; 1228 1229 case MS_OP_RFETCH_P: 1230 reg = mi->arg[1].i; 1231 mask = (char)mi->arg[2].i; 1232 ptr = atppc->sc_ptr; 1233 1234 if((len = mi->arg[0].i) == MS_ACCUM) { 1235 accum = atppc->sc_accum; 1236 for (; accum; accum--) { 1237 *ptr++ = r_reg(reg, atppc) & mask; 1238 atppc_barrier_r(atppc); 1239 } 1240 atppc->sc_accum = accum; 1241 } 1242 else { 1243 for(i = 0; i < len; i++) { 1244 *ptr++ = r_reg(reg, atppc) & mask; 1245 atppc_barrier_r(atppc); 1246 } 1247 } 1248 1249 atppc->sc_ptr = ptr; 1250 mi++; 1251 break; 1252 1253 case MS_OP_RFETCH: 1254 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1255 (char)mi->arg[1].i; 1256 atppc_barrier_r(atppc); 1257 mi++; 1258 break; 1259 1260 case MS_OP_RASSERT: 1261 case MS_OP_DELAY: 1262 /* let's suppose the next instr. is the same */ 1263 do { 1264 for(;mi->opcode == MS_OP_RASSERT; mi++) { 1265 w_reg(mi->arg[0].i, atppc, 1266 (char)mi->arg[1].i); 1267 atppc_barrier_w(atppc); 1268 } 1269 1270 for(;mi->opcode == MS_OP_DELAY; mi++) { 1271 delay(mi->arg[0].i); 1272 } 1273 } while(mi->opcode == MS_OP_RASSERT); 1274 break; 1275 1276 case MS_OP_ADELAY: 1277 if(mi->arg[0].i) { 1278 tsleep(atppc, PPBUSPRI, "atppcdelay", 1279 mi->arg[0].i * (hz/1000)); 1280 } 1281 mi++; 1282 break; 1283 1284 case MS_OP_TRIG: 1285 reg = mi->arg[0].i; 1286 iter = mi->arg[1].i; 1287 p = (char *)mi->arg[2].p; 1288 1289 /* XXX delay limited to 255 us */ 1290 for(i = 0; i < iter; i++) { 1291 w_reg(reg, atppc, *p++); 1292 atppc_barrier_w(atppc); 1293 delay((unsigned char)*p++); 1294 } 1295 1296 mi++; 1297 break; 1298 1299 case MS_OP_SET: 1300 atppc->sc_accum = mi->arg[0].i; 1301 mi++; 1302 break; 1303 1304 case MS_OP_DBRA: 1305 if(--atppc->sc_accum > 0) { 1306 mi += mi->arg[0].i; 1307 } 1308 1309 mi++; 1310 break; 1311 1312 case MS_OP_BRSET: 1313 cc = atppc_r_str(atppc); 1314 atppc_barrier_r(atppc); 1315 if((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1316 mi += mi->arg[1].i; 1317 } 1318 mi++; 1319 break; 1320 1321 case MS_OP_BRCLEAR: 1322 cc = atppc_r_str(atppc); 1323 atppc_barrier_r(atppc); 1324 if((cc & (char)mi->arg[0].i) == 0) { 1325 mi += mi->arg[1].i; 1326 } 1327 mi++; 1328 break; 1329 1330 case MS_OP_BRSTAT: 1331 cc = atppc_r_str(atppc); 1332 atppc_barrier_r(atppc); 1333 if((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1334 (char)mi->arg[0].i) { 1335 mi += mi->arg[2].i; 1336 } 1337 mi++; 1338 break; 1339 1340 case MS_OP_C_CALL: 1341 /* 1342 * If the C call returns !0 then end the microseq. 1343 * The current state of ptr is passed to the C function 1344 */ 1345 if((error = mi->arg[0].f(mi->arg[1].p, 1346 atppc->sc_ptr))) { 1347 ATPPC_UNLOCK(atppc); 1348 splx(s); 1349 return (error); 1350 } 1351 mi++; 1352 break; 1353 1354 case MS_OP_PTR: 1355 atppc->sc_ptr = (char *)mi->arg[0].p; 1356 mi++; 1357 break; 1358 1359 case MS_OP_CALL: 1360 if (stack) { 1361 panic("%s - %s: too much calls", dev->dv_xname, 1362 __func__); 1363 } 1364 1365 if (mi->arg[0].p) { 1366 /* store state of the actual microsequence */ 1367 stack = mi; 1368 1369 /* jump to the new microsequence */ 1370 mi = (struct ppbus_microseq *)mi->arg[0].p; 1371 } 1372 else { 1373 mi++; 1374 } 1375 break; 1376 1377 case MS_OP_SUBRET: 1378 /* retrieve microseq and pc state before the call */ 1379 mi = stack; 1380 1381 /* reset the stack */ 1382 stack = 0; 1383 1384 /* XXX return code */ 1385 1386 mi++; 1387 break; 1388 1389 case MS_OP_PUT: 1390 case MS_OP_GET: 1391 case MS_OP_RET: 1392 /* 1393 * Can't return to atppc level during the execution 1394 * of a submicrosequence. 1395 */ 1396 if (stack) { 1397 panic("%s: cannot return to atppc level", 1398 __func__); 1399 } 1400 /* update pc for atppc level of execution */ 1401 *p_msq = mi; 1402 1403 ATPPC_UNLOCK(atppc); 1404 splx(s); 1405 return (0); 1406 break; 1407 1408 default: 1409 panic("%s: unknown microsequence " 1410 "opcode 0x%x", __func__, mi->opcode); 1411 break; 1412 } 1413 } 1414 1415 /* Should not be reached! */ 1416 #ifdef ATPPC_DEBUG 1417 panic("%s: unexpected code reached!\n", __func__); 1418 #endif 1419 } 1420 1421 /* General I/O routine */ 1422 static u_int8_t 1423 atppc_io(struct device * dev, int iop, u_char * addr, int cnt, u_char byte) 1424 { 1425 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1426 u_int8_t val = 0; 1427 int s; 1428 1429 s = splatppc(); 1430 ATPPC_LOCK(atppc); 1431 1432 switch (iop) { 1433 case PPBUS_OUTSB_EPP: 1434 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1435 ATPPC_EPP_DATA, addr, cnt); 1436 break; 1437 case PPBUS_OUTSW_EPP: 1438 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1439 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1440 break; 1441 case PPBUS_OUTSL_EPP: 1442 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1443 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1444 break; 1445 case PPBUS_INSB_EPP: 1446 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1447 ATPPC_EPP_DATA, addr, cnt); 1448 break; 1449 case PPBUS_INSW_EPP: 1450 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1451 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1452 break; 1453 case PPBUS_INSL_EPP: 1454 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1455 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1456 break; 1457 case PPBUS_RDTR: 1458 val = (atppc_r_dtr(atppc)); 1459 break; 1460 case PPBUS_RSTR: 1461 val = (atppc_r_str(atppc)); 1462 break; 1463 case PPBUS_RCTR: 1464 val = (atppc_r_ctr(atppc)); 1465 break; 1466 case PPBUS_REPP_A: 1467 val = (atppc_r_eppA(atppc)); 1468 break; 1469 case PPBUS_REPP_D: 1470 val = (atppc_r_eppD(atppc)); 1471 break; 1472 case PPBUS_RECR: 1473 val = (atppc_r_ecr(atppc)); 1474 break; 1475 case PPBUS_RFIFO: 1476 val = (atppc_r_fifo(atppc)); 1477 break; 1478 case PPBUS_WDTR: 1479 atppc_w_dtr(atppc, byte); 1480 break; 1481 case PPBUS_WSTR: 1482 atppc_w_str(atppc, byte); 1483 break; 1484 case PPBUS_WCTR: 1485 atppc_w_ctr(atppc, byte); 1486 break; 1487 case PPBUS_WEPP_A: 1488 atppc_w_eppA(atppc, byte); 1489 break; 1490 case PPBUS_WEPP_D: 1491 atppc_w_eppD(atppc, byte); 1492 break; 1493 case PPBUS_WECR: 1494 atppc_w_ecr(atppc, byte); 1495 break; 1496 case PPBUS_WFIFO: 1497 atppc_w_fifo(atppc, byte); 1498 break; 1499 default: 1500 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1501 __func__); 1502 break; 1503 } 1504 1505 atppc_barrier(atppc); 1506 1507 ATPPC_UNLOCK(atppc); 1508 splx(s); 1509 1510 return val; 1511 } 1512 1513 /* Read "instance variables" of atppc device */ 1514 static int 1515 atppc_read_ivar(struct device * dev, int index, unsigned int * val) 1516 { 1517 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1518 int rval = 0; 1519 int s; 1520 1521 s = splatppc(); 1522 ATPPC_LOCK(atppc); 1523 1524 switch(index) { 1525 case PPBUS_IVAR_EPP_PROTO: 1526 if(atppc->sc_epp == ATPPC_EPP_1_9) 1527 *val = PPBUS_EPP_1_9; 1528 else if(atppc->sc_epp == ATPPC_EPP_1_7) 1529 *val = PPBUS_EPP_1_7; 1530 break; 1531 1532 case PPBUS_IVAR_INTR: 1533 if(atppc->sc_use & ATPPC_USE_INTR) 1534 *val = 1; 1535 else 1536 *val = 0; 1537 break; 1538 1539 case PPBUS_IVAR_DMA: 1540 if(atppc->sc_use & ATPPC_USE_DMA) 1541 *val = 1; 1542 else 1543 *val = 0; 1544 break; 1545 break; 1546 1547 default: 1548 rval = ENODEV; 1549 } 1550 1551 ATPPC_UNLOCK(atppc); 1552 splx(s); 1553 1554 return rval; 1555 } 1556 1557 /* Write "instance varaibles" of atppc device */ 1558 static int 1559 atppc_write_ivar(struct device * dev, int index, unsigned int * val) 1560 { 1561 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1562 int rval = 0; 1563 int s; 1564 1565 s = splatppc(); 1566 ATPPC_LOCK(atppc); 1567 1568 switch(index) { 1569 case PPBUS_IVAR_EPP_PROTO: 1570 if(*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1571 atppc->sc_epp = *val; 1572 else 1573 rval = EINVAL; 1574 break; 1575 1576 case PPBUS_IVAR_INTR: 1577 if(*val == 0) 1578 atppc->sc_use &= ~ATPPC_USE_INTR; 1579 else if(atppc->sc_has & ATPPC_HAS_INTR) 1580 atppc->sc_use |= ATPPC_USE_INTR; 1581 else 1582 rval = ENODEV; 1583 break; 1584 1585 case PPBUS_IVAR_DMA: 1586 if(*val == 0) 1587 atppc->sc_use &= ~ATPPC_USE_DMA; 1588 else if(atppc->sc_has & ATPPC_HAS_DMA) 1589 atppc->sc_use |= ATPPC_USE_DMA; 1590 else 1591 rval = ENODEV; 1592 break; 1593 1594 default: 1595 rval = ENODEV; 1596 } 1597 1598 ATPPC_UNLOCK(atppc); 1599 splx(s); 1600 1601 return rval; 1602 } 1603 1604 /* Add a handler routine to be called by the interrupt handler */ 1605 static int 1606 atppc_add_handler(struct device * dev, void (*handler)(void *), void *arg) 1607 { 1608 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1609 struct atppc_handler_node * callback; 1610 int rval = 0; 1611 int s; 1612 1613 s = splatppc(); 1614 ATPPC_LOCK(atppc); 1615 1616 if(handler == NULL) { 1617 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1618 __func__, dev->dv_xname)); 1619 rval = EINVAL; 1620 } 1621 else { 1622 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1623 M_NOWAIT); 1624 if(callback) { 1625 callback->func = handler; 1626 callback->arg = arg; 1627 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1628 callback, entries); 1629 } 1630 else { 1631 rval = ENOMEM; 1632 } 1633 } 1634 1635 ATPPC_UNLOCK(atppc); 1636 splx(s); 1637 1638 return rval; 1639 } 1640 1641 /* Remove a handler added by atppc_add_handler() */ 1642 static int 1643 atppc_remove_handler(struct device * dev, void (*handler)(void *)) 1644 { 1645 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1646 struct atppc_handler_node * callback; 1647 int rval = EINVAL; 1648 int s; 1649 1650 s = splatppc(); 1651 ATPPC_LOCK(atppc); 1652 1653 if(SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1654 panic("%s(%s): attempt to remove handler from empty list.\n", 1655 __func__, dev->dv_xname); 1656 1657 /* Search list for handler */ 1658 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1659 if(callback->func == handler) { 1660 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1661 atppc_handler_node, entries); 1662 free(callback, M_DEVBUF); 1663 rval = 0; 1664 break; 1665 } 1666 } 1667 1668 ATPPC_UNLOCK(atppc); 1669 splx(s); 1670 1671 return rval; 1672 } 1673 1674 /* Utility functions */ 1675 1676 1677 /* 1678 * Functions that read bytes from port into buffer: called from interrupt 1679 * handler depending on current chipset mode and cause of interrupt. Return 1680 * value: number of bytes moved. 1681 */ 1682 1683 /* Only the lower 4 bits of the final value are valid */ 1684 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1685 1686 /* Read bytes in nibble mode */ 1687 static void 1688 atppc_nibble_read(struct atppc_softc * atppc) 1689 { 1690 int i; 1691 u_int8_t nibble[2]; 1692 u_int8_t ctr; 1693 u_int8_t str; 1694 1695 /* Enable interrupts if needed */ 1696 if(atppc->sc_use & ATPPC_USE_INTR) { 1697 ctr = atppc_r_ctr(atppc); 1698 atppc_barrier_r(atppc); 1699 if(!(ctr & IRQENABLE)) { 1700 ctr |= IRQENABLE; 1701 atppc_w_ctr(atppc, ctr); 1702 atppc_barrier_w(atppc); 1703 } 1704 } 1705 1706 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1707 /* Check if device has data to send in idle phase */ 1708 str = atppc_r_str(atppc); 1709 atppc_barrier_r(atppc); 1710 if(str & nDATAVAIL) { 1711 return; 1712 } 1713 1714 /* Nibble-mode handshake transfer */ 1715 for(i = 0; i < 2; i++) { 1716 /* Event 7 - ready to take data (HOSTBUSY low) */ 1717 ctr = atppc_r_ctr(atppc); 1718 atppc_barrier_r(atppc); 1719 ctr |= HOSTBUSY; 1720 atppc_w_ctr(atppc, ctr); 1721 atppc_barrier_w(atppc); 1722 1723 /* Event 8 - peripheral writes the first nibble */ 1724 1725 /* Event 9 - peripheral set nAck low */ 1726 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1727 if(atppc->sc_inerr) 1728 return; 1729 1730 /* read nibble */ 1731 nibble[i] = atppc_r_str(atppc); 1732 1733 /* Event 10 - ack, nibble received */ 1734 ctr &= ~HOSTBUSY; 1735 atppc_w_ctr(atppc, ctr); 1736 1737 /* Event 11 - wait ack from peripherial */ 1738 if(atppc->sc_use & ATPPC_USE_INTR) 1739 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1740 atppc->sc_inb, ATPPC_IRQ_nACK); 1741 else 1742 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1743 PTRCLK); 1744 if(atppc->sc_inerr) 1745 return; 1746 } 1747 1748 /* Store byte transfered */ 1749 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1750 (nibble2char(nibble[0]) & 0x0f); 1751 atppc->sc_inbstart++; 1752 } 1753 } 1754 1755 /* Read bytes in bidirectional mode */ 1756 static void 1757 atppc_byte_read(struct atppc_softc * const atppc) 1758 { 1759 u_int8_t ctr; 1760 u_int8_t str; 1761 1762 /* Check direction bit */ 1763 ctr = atppc_r_ctr(atppc); 1764 atppc_barrier_r(atppc); 1765 if(!(ctr & PCD)) { 1766 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1767 "bit set.", atppc->sc_dev.dv_xname)); 1768 atppc->sc_inerr = ENODEV; 1769 return; 1770 } 1771 /* Enable interrupts if needed */ 1772 if(atppc->sc_use & ATPPC_USE_INTR) { 1773 if(!(ctr & IRQENABLE)) { 1774 ctr |= IRQENABLE; 1775 atppc_w_ctr(atppc, ctr); 1776 atppc_barrier_w(atppc); 1777 } 1778 } 1779 1780 /* Byte-mode handshake transfer */ 1781 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1782 /* Check if device has data to send */ 1783 str = atppc_r_str(atppc); 1784 atppc_barrier_r(atppc); 1785 if(str & nDATAVAIL) { 1786 return; 1787 } 1788 1789 /* Event 7 - ready to take data (nAUTO low) */ 1790 ctr |= HOSTBUSY; 1791 atppc_w_ctr(atppc, ctr); 1792 atppc_barrier_w(atppc); 1793 1794 /* Event 9 - peripheral set nAck low */ 1795 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1796 if(atppc->sc_inerr) 1797 return; 1798 1799 /* Store byte transfered */ 1800 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1801 atppc_barrier_r(atppc); 1802 1803 /* Event 10 - data received, can't accept more */ 1804 ctr &= ~HOSTBUSY; 1805 atppc_w_ctr(atppc, ctr); 1806 atppc_barrier_w(atppc); 1807 1808 /* Event 11 - peripheral ack */ 1809 if(atppc->sc_use & ATPPC_USE_INTR) 1810 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1811 atppc->sc_inb, ATPPC_IRQ_nACK); 1812 else 1813 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1814 if(atppc->sc_inerr) 1815 return; 1816 1817 /* Event 16 - strobe */ 1818 str |= HOSTCLK; 1819 atppc_w_str(atppc, str); 1820 atppc_barrier_w(atppc); 1821 DELAY(1); 1822 str &= ~HOSTCLK; 1823 atppc_w_str(atppc, str); 1824 atppc_barrier_w(atppc); 1825 1826 /* Update counter */ 1827 atppc->sc_inbstart++; 1828 } 1829 } 1830 1831 /* Read bytes in EPP mode */ 1832 static void 1833 atppc_epp_read(struct atppc_softc * atppc) 1834 { 1835 if(atppc->sc_epp == ATPPC_EPP_1_9) { 1836 { 1837 uint8_t str; 1838 int i; 1839 1840 atppc_reset_epp_timeout((struct device *)atppc); 1841 for(i = 0; i < atppc->sc_inb_nbytes; i++) { 1842 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1843 atppc_barrier_r(atppc); 1844 str = atppc_r_str(atppc); 1845 atppc_barrier_r(atppc); 1846 if(str & TIMEOUT) { 1847 atppc->sc_inerr = EIO; 1848 break; 1849 } 1850 atppc->sc_inbstart++; 1851 } 1852 } 1853 } 1854 else { 1855 /* Read data block from EPP data register */ 1856 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1857 atppc->sc_inb_nbytes); 1858 atppc_barrier_r(atppc); 1859 /* Update buffer position, byte count and counter */ 1860 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1861 } 1862 1863 return; 1864 } 1865 1866 /* Read bytes in ECP mode */ 1867 static void 1868 atppc_ecp_read(struct atppc_softc * atppc) 1869 { 1870 u_int8_t ecr; 1871 u_int8_t ctr; 1872 u_int8_t str; 1873 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1874 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1875 unsigned int worklen; 1876 1877 /* Check direction bit */ 1878 ctr = ctr_sav; 1879 atppc_barrier_r(atppc); 1880 if(!(ctr & PCD)) { 1881 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1882 "bit set.", atppc->sc_dev.dv_xname)); 1883 atppc->sc_inerr = ENODEV; 1884 goto end; 1885 } 1886 1887 /* Clear device request if any */ 1888 if(atppc->sc_use & ATPPC_USE_INTR) 1889 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1890 1891 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1892 ecr = atppc_r_ecr(atppc); 1893 atppc_barrier_r(atppc); 1894 if(ecr & ATPPC_FIFO_EMPTY) { 1895 /* Check for invalid state */ 1896 if(ecr & ATPPC_FIFO_FULL) { 1897 atppc_ecp_read_error(atppc, worklen); 1898 break; 1899 } 1900 1901 /* Check if device has data to send */ 1902 str = atppc_r_str(atppc); 1903 atppc_barrier_r(atppc); 1904 if(str & nDATAVAIL) { 1905 break; 1906 } 1907 1908 if(atppc->sc_use & ATPPC_USE_INTR) { 1909 /* Enable interrupts */ 1910 ecr &= ~ATPPC_SERVICE_INTR; 1911 atppc_w_ecr(atppc, ecr); 1912 atppc_barrier_w(atppc); 1913 /* Wait for FIFO to fill */ 1914 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1915 atppc->sc_inb, ATPPC_IRQ_FIFO); 1916 if(atppc->sc_inerr) 1917 break; 1918 } 1919 else { 1920 DELAY(1); 1921 } 1922 continue; 1923 } 1924 else if(ecr & ATPPC_FIFO_FULL) { 1925 /* Transfer sc_fifo bytes */ 1926 worklen = atppc->sc_fifo; 1927 } 1928 else if(ecr & ATPPC_SERVICE_INTR) { 1929 /* Transfer sc_rthr bytes */ 1930 worklen = atppc->sc_rthr; 1931 } 1932 else { 1933 /* At least one byte is in the FIFO */ 1934 worklen = 1; 1935 } 1936 1937 if((atppc->sc_use & ATPPC_USE_INTR) && 1938 (atppc->sc_use & ATPPC_USE_DMA)) { 1939 1940 atppc_ecp_read_dma(atppc, &worklen, ecr); 1941 } 1942 else { 1943 atppc_ecp_read_pio(atppc, &worklen, ecr); 1944 } 1945 1946 if(atppc->sc_inerr) { 1947 atppc_ecp_read_error(atppc, worklen); 1948 break; 1949 } 1950 1951 /* Update counter */ 1952 atppc->sc_inbstart += worklen; 1953 } 1954 end: 1955 atppc_w_ctr(atppc, ctr_sav); 1956 atppc_w_ecr(atppc, ecr_sav); 1957 atppc_barrier_w(atppc); 1958 } 1959 1960 /* Read bytes in ECP mode using DMA transfers */ 1961 static void 1962 atppc_ecp_read_dma(struct atppc_softc * atppc, unsigned int * length, 1963 unsigned char ecr) 1964 { 1965 /* Limit transfer to maximum DMA size and start it */ 1966 *length = min(*length, atppc->sc_dma_maxsize); 1967 atppc->sc_dmastat = ATPPC_DMA_INIT; 1968 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1969 ATPPC_DMA_MODE_READ); 1970 1971 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1972 1973 /* Enable interrupts, DMA */ 1974 ecr &= ~ATPPC_SERVICE_INTR; 1975 ecr |= ATPPC_ENABLE_DMA; 1976 atppc_w_ecr(atppc, ecr); 1977 atppc_barrier_w(atppc); 1978 1979 /* Wait for DMA completion */ 1980 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1981 ATPPC_IRQ_DMA); 1982 if(atppc->sc_inerr) 1983 return; 1984 1985 /* Get register value recorded by interrupt handler */ 1986 ecr = atppc->sc_ecr_intr; 1987 /* Clear DMA programming */ 1988 atppc->sc_dma_finish(atppc); 1989 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1990 /* Disable DMA */ 1991 ecr &= ~ATPPC_ENABLE_DMA; 1992 atppc_w_ecr(atppc, ecr); 1993 atppc_barrier_w(atppc); 1994 } 1995 1996 /* Read bytes in ECP mode using PIO transfers */ 1997 static void 1998 atppc_ecp_read_pio(struct atppc_softc * atppc, unsigned int * length, 1999 unsigned char ecr) 2000 { 2001 /* Disable DMA */ 2002 ecr &= ~ATPPC_ENABLE_DMA; 2003 atppc_w_ecr(atppc, ecr); 2004 atppc_barrier_w(atppc); 2005 2006 /* Read from FIFO */ 2007 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 2008 } 2009 2010 /* Handle errors for ECP reads */ 2011 static void 2012 atppc_ecp_read_error(struct atppc_softc * atppc, const unsigned int worklen) 2013 { 2014 unsigned char ecr = atppc_r_ecr(atppc); 2015 2016 /* Abort DMA if not finished */ 2017 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2018 atppc->sc_dma_abort(atppc); 2019 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2020 } 2021 2022 /* Check for invalid states */ 2023 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2024 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2025 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2026 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2027 atppc_barrier_w(atppc); 2028 } 2029 } 2030 2031 /* 2032 * Functions that write bytes to port from buffer: called from atppc_write() 2033 * function depending on current chipset mode. Returns number of bytes moved. 2034 */ 2035 2036 /* Write bytes in std/bidirectional mode */ 2037 static void 2038 atppc_std_write(struct atppc_softc * const atppc) 2039 { 2040 unsigned int timecount; 2041 unsigned char ctr; 2042 2043 ctr = atppc_r_ctr(atppc); 2044 atppc_barrier_r(atppc); 2045 /* Enable interrupts if needed */ 2046 if(atppc->sc_use & ATPPC_USE_INTR) { 2047 if(!(ctr & IRQENABLE)) { 2048 ctr |= IRQENABLE; 2049 atppc_w_ctr(atppc, ctr); 2050 atppc_barrier_w(atppc); 2051 } 2052 } 2053 2054 while(atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2055 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2056 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2057 if(atppc->sc_outerr) 2058 return; 2059 2060 /* Put data in data register */ 2061 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2062 atppc_barrier_w(atppc); 2063 DELAY(1); 2064 2065 /* Pulse strobe to indicate valid data on lines */ 2066 ctr |= STROBE; 2067 atppc_w_ctr(atppc, ctr); 2068 atppc_barrier_w(atppc); 2069 DELAY(1); 2070 ctr &= ~STROBE; 2071 atppc_w_ctr(atppc, ctr); 2072 atppc_barrier_w(atppc); 2073 2074 /* Wait for nACK for MAXBUSYWAIT */ 2075 timecount = 0; 2076 if(atppc->sc_use & ATPPC_USE_INTR) { 2077 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2078 atppc->sc_outb, ATPPC_IRQ_nACK); 2079 if(atppc->sc_outerr) 2080 return; 2081 } 2082 else { 2083 /* Try to catch the pulsed acknowledgement */ 2084 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2085 if(atppc->sc_outerr) 2086 return; 2087 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2088 if(atppc->sc_outerr) 2089 return; 2090 } 2091 2092 /* Update buffer position, byte count and counter */ 2093 atppc->sc_outbstart++; 2094 } 2095 } 2096 2097 2098 /* Write bytes in EPP mode */ 2099 static void 2100 atppc_epp_write(struct atppc_softc * atppc) 2101 { 2102 if(atppc->sc_epp == ATPPC_EPP_1_9) { 2103 { 2104 uint8_t str; 2105 int i; 2106 2107 atppc_reset_epp_timeout((struct device *)atppc); 2108 for(i = 0; i < atppc->sc_outb_nbytes; i++) { 2109 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2110 atppc_barrier_w(atppc); 2111 str = atppc_r_str(atppc); 2112 atppc_barrier_r(atppc); 2113 if(str & TIMEOUT) { 2114 atppc->sc_outerr = EIO; 2115 break; 2116 } 2117 atppc->sc_outbstart++; 2118 } 2119 } 2120 } 2121 else { 2122 /* Write data block to EPP data register */ 2123 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2124 atppc->sc_outb_nbytes); 2125 atppc_barrier_w(atppc); 2126 /* Update buffer position, byte count and counter */ 2127 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2128 } 2129 2130 return; 2131 } 2132 2133 2134 /* Write bytes in ECP/Fast Centronics mode */ 2135 static void 2136 atppc_fifo_write(struct atppc_softc * const atppc) 2137 { 2138 unsigned char ctr; 2139 unsigned char ecr; 2140 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2141 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2142 2143 ctr = ctr_sav; 2144 ecr = ecr_sav; 2145 atppc_barrier_r(atppc); 2146 2147 /* Reset and flush FIFO */ 2148 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2149 atppc_barrier_w(atppc); 2150 /* Disable nAck interrupts and initialize port bits */ 2151 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2152 atppc_w_ctr(atppc, ctr); 2153 atppc_barrier_w(atppc); 2154 /* Restore mode */ 2155 atppc_w_ecr(atppc, ecr); 2156 atppc_barrier_w(atppc); 2157 2158 /* DMA or Programmed IO */ 2159 if((atppc->sc_use & ATPPC_USE_DMA) && 2160 (atppc->sc_use & ATPPC_USE_INTR)) { 2161 2162 atppc_fifo_write_dma(atppc, ecr, ctr); 2163 } 2164 else { 2165 atppc_fifo_write_pio(atppc, ecr, ctr); 2166 } 2167 2168 /* Restore original register values */ 2169 atppc_w_ctr(atppc, ctr_sav); 2170 atppc_w_ecr(atppc, ecr_sav); 2171 atppc_barrier_w(atppc); 2172 } 2173 2174 static void 2175 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2176 unsigned char ctr) 2177 { 2178 unsigned int len; 2179 unsigned int worklen; 2180 2181 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2182 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2183 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2184 2185 /* Wait for device to become ready */ 2186 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2187 if(atppc->sc_outerr) 2188 return; 2189 2190 /* Reset chipset for next DMA transfer */ 2191 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2192 atppc_barrier_w(atppc); 2193 atppc_w_ecr(atppc, ecr); 2194 atppc_barrier_w(atppc); 2195 2196 /* Limit transfer to minimum of space in FIFO and buffer */ 2197 worklen = min(len, atppc->sc_fifo); 2198 2199 /* Limit transfer to maximum DMA size and start it */ 2200 worklen = min(worklen, atppc->sc_dma_maxsize); 2201 atppc->sc_dmastat = ATPPC_DMA_INIT; 2202 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2203 worklen, ATPPC_DMA_MODE_WRITE); 2204 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2205 2206 /* Enable interrupts, DMA */ 2207 ecr &= ~ATPPC_SERVICE_INTR; 2208 ecr |= ATPPC_ENABLE_DMA; 2209 atppc_w_ecr(atppc, ecr); 2210 atppc_barrier_w(atppc); 2211 2212 /* Wait for DMA completion */ 2213 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2214 ATPPC_IRQ_DMA); 2215 if(atppc->sc_outerr) { 2216 atppc_fifo_write_error(atppc, worklen); 2217 return; 2218 } 2219 /* Get register value recorded by interrupt handler */ 2220 ecr = atppc->sc_ecr_intr; 2221 /* Clear DMA programming */ 2222 atppc->sc_dma_finish(atppc); 2223 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2224 /* Disable DMA */ 2225 ecr &= ~ATPPC_ENABLE_DMA; 2226 atppc_w_ecr(atppc, ecr); 2227 atppc_barrier_w(atppc); 2228 2229 /* Wait for FIFO to empty */ 2230 for(;;) { 2231 if(ecr & ATPPC_FIFO_EMPTY) { 2232 if(ecr & ATPPC_FIFO_FULL) { 2233 atppc->sc_outerr = EIO; 2234 atppc_fifo_write_error(atppc, worklen); 2235 return; 2236 } 2237 else { 2238 break; 2239 } 2240 } 2241 2242 /* Enable service interrupt */ 2243 ecr &= ~ATPPC_SERVICE_INTR; 2244 atppc_w_ecr(atppc, ecr); 2245 atppc_barrier_w(atppc); 2246 2247 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2248 atppc->sc_outb, ATPPC_IRQ_FIFO); 2249 if(atppc->sc_outerr) { 2250 atppc_fifo_write_error(atppc, worklen); 2251 return; 2252 } 2253 2254 /* Get register value recorded by interrupt handler */ 2255 ecr = atppc->sc_ecr_intr; 2256 } 2257 2258 /* Update pointer */ 2259 atppc->sc_outbstart += worklen; 2260 } 2261 } 2262 2263 static void 2264 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2265 unsigned char ctr) 2266 { 2267 unsigned int len; 2268 unsigned int worklen; 2269 unsigned int timecount; 2270 2271 /* Disable DMA */ 2272 ecr &= ~ATPPC_ENABLE_DMA; 2273 atppc_w_ecr(atppc, ecr); 2274 atppc_barrier_w(atppc); 2275 2276 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2277 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2278 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2279 2280 /* Wait for device to become ready */ 2281 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2282 if(atppc->sc_outerr) 2283 return; 2284 2285 /* Limit transfer to minimum of space in FIFO and buffer */ 2286 worklen = min(len, atppc->sc_fifo); 2287 2288 /* Write to FIFO */ 2289 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2290 2291 timecount = 0; 2292 if(atppc->sc_use & ATPPC_USE_INTR) { 2293 ecr = atppc_r_ecr(atppc); 2294 atppc_barrier_w(atppc); 2295 2296 /* Wait for interrupt */ 2297 for(;;) { 2298 if(ecr & ATPPC_FIFO_EMPTY) { 2299 if(ecr & ATPPC_FIFO_FULL) { 2300 atppc->sc_outerr = EIO; 2301 atppc_fifo_write_error(atppc, 2302 worklen); 2303 return; 2304 } 2305 else { 2306 break; 2307 } 2308 } 2309 2310 /* Enable service interrupt */ 2311 ecr &= ~ATPPC_SERVICE_INTR; 2312 atppc_w_ecr(atppc, ecr); 2313 atppc_barrier_w(atppc); 2314 2315 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2316 atppc->sc_outb, ATPPC_IRQ_FIFO); 2317 if(atppc->sc_outerr) { 2318 atppc_fifo_write_error(atppc, worklen); 2319 return; 2320 } 2321 2322 /* Get ECR value saved by interrupt handler */ 2323 ecr = atppc->sc_ecr_intr; 2324 } 2325 } 2326 else { 2327 for(; timecount < ((MAXBUSYWAIT/hz)*1000000); 2328 timecount++) { 2329 2330 ecr = atppc_r_ecr(atppc); 2331 atppc_barrier_r(atppc); 2332 if(ecr & ATPPC_FIFO_EMPTY) { 2333 if(ecr & ATPPC_FIFO_FULL) { 2334 atppc->sc_outerr = EIO; 2335 atppc_fifo_write_error(atppc, 2336 worklen); 2337 return; 2338 } 2339 else { 2340 break; 2341 } 2342 } 2343 DELAY(1); 2344 } 2345 2346 if(((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2347 atppc->sc_outerr = EIO; 2348 atppc_fifo_write_error(atppc, worklen); 2349 return; 2350 } 2351 } 2352 2353 /* Update pointer */ 2354 atppc->sc_outbstart += worklen; 2355 } 2356 } 2357 2358 static void 2359 atppc_fifo_write_error(struct atppc_softc * const atppc, 2360 const unsigned int worklen) 2361 { 2362 unsigned char ecr = atppc_r_ecr(atppc); 2363 2364 /* Abort DMA if not finished */ 2365 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2366 atppc->sc_dma_abort(atppc); 2367 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2368 } 2369 2370 /* Check for invalid states */ 2371 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2372 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2373 } 2374 else if(!(ecr & ATPPC_FIFO_EMPTY)) { 2375 unsigned char ctr = atppc_r_ctr(atppc); 2376 int bytes_left; 2377 int i; 2378 2379 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2380 atppc->sc_dev.dv_xname)); 2381 2382 /* Drive strobe low to stop data transfer */ 2383 ctr &= ~STROBE; 2384 atppc_w_ctr(atppc, ctr); 2385 atppc_barrier_w(atppc); 2386 2387 /* Determine how many bytes remain in FIFO */ 2388 for(i = 0; i < atppc->sc_fifo; i++) { 2389 atppc_w_fifo(atppc, (unsigned char)i); 2390 ecr = atppc_r_ecr(atppc); 2391 atppc_barrier_r(atppc); 2392 if(ecr & ATPPC_FIFO_FULL) 2393 break; 2394 } 2395 bytes_left = (atppc->sc_fifo) - (i + 1); 2396 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2397 bytes_left)); 2398 2399 /* Update counter */ 2400 atppc->sc_outbstart += (worklen - bytes_left); 2401 } 2402 else { 2403 /* Update counter */ 2404 atppc->sc_outbstart += worklen; 2405 } 2406 2407 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2408 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2409 atppc_barrier_w(atppc); 2410 } 2411 2412 /* 2413 * Poll status register using mask and status for MAXBUSYWAIT. 2414 * Returns 0 if device ready, error value otherwise. 2415 */ 2416 static int 2417 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2418 const u_int8_t mask) 2419 { 2420 unsigned int timecount; 2421 u_int8_t str; 2422 int error = EIO; 2423 2424 /* Wait for str to have status for MAXBUSYWAIT */ 2425 for(timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2426 timecount++) { 2427 2428 str = atppc_r_str(atppc); 2429 atppc_barrier_r(atppc); 2430 if((str & mask) == status) { 2431 error = 0; 2432 break; 2433 } 2434 DELAY(1); 2435 } 2436 2437 return error; 2438 } 2439 2440 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2441 static int 2442 atppc_wait_interrupt(struct atppc_softc * const atppc, const caddr_t where, 2443 const u_int8_t irqstat) 2444 { 2445 int error = EIO; 2446 2447 atppc->sc_irqstat &= ~irqstat; 2448 2449 /* Wait for interrupt for MAXBUSYWAIT */ 2450 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2451 ATPPC_SC_LOCK(atppc)); 2452 2453 if(!(error) && (atppc->sc_irqstat & irqstat)) { 2454 atppc->sc_irqstat &= ~irqstat; 2455 error = 0; 2456 } 2457 2458 return error; 2459 } 2460
Indexes created Sun Sep 28 16:09:52 GMT 2025