atppc.c revision 1.8
1 /* $NetBSD: atppc.c,v 1.8 2004/01/25 11:41:17 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: atppc.c,v 1.8 2004/01/25 11:41:17 jdolecek Exp $"); 34 35 #include "opt_atppc.h" 36 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 #include <sys/systm.h> 44 #include <sys/vnode.h> 45 #include <sys/syslog.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/isa/isareg.h> 51 52 #include <dev/ic/atppcreg.h> 53 #include <dev/ic/atppcvar.h> 54 55 #include <dev/ppbus/ppbus_conf.h> 56 #include <dev/ppbus/ppbus_msq.h> 57 #include <dev/ppbus/ppbus_io.h> 58 #include <dev/ppbus/ppbus_var.h> 59 60 #ifdef ATPPC_DEBUG 61 int atppc_debug = 1; 62 #endif 63 64 #ifdef ATPPC_VERBOSE 65 int atppc_verbose = 1; 66 #endif 67 68 /* List of supported chipsets detection routines */ 69 static int (*chipset_detect[])(struct atppc_softc *) = { 70 /* XXX Add these LATER: maybe as seperate devices? 71 atppc_pc873xx_detect, 72 atppc_smc37c66xgt_detect, 73 atppc_w83877f_detect, 74 atppc_smc37c935_detect, 75 */ 76 NULL 77 }; 78 79 80 /* Prototypes for functions. */ 81 82 /* Soft configuration attach */ 83 void atppc_sc_attach(struct atppc_softc *); 84 int atppc_sc_detach(struct atppc_softc *, int); 85 86 /* Interrupt handler for atppc device */ 87 int atppcintr(void *); 88 89 /* Print function for config_found_sm() */ 90 static int atppc_print(void * aux, const char * name); 91 92 /* Detection routines */ 93 static int atppc_detect_fifo(struct atppc_softc *); 94 static int atppc_detect_chipset(struct atppc_softc *); 95 static int atppc_detect_generic(struct atppc_softc *); 96 97 /* Routines for ppbus interface (bus + device) */ 98 static int atppc_read(struct device *, char *, int, int, size_t *); 99 static int atppc_write(struct device *, char *, int, int, size_t *); 100 static int atppc_setmode(struct device *, int); 101 static int atppc_getmode(struct device *); 102 static int atppc_check_epp_timeout(struct device *); 103 static void atppc_reset_epp_timeout(struct device *); 104 static void atppc_ecp_sync(struct device *); 105 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 106 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 107 static int atppc_read_ivar(struct device *, int, unsigned int *); 108 static int atppc_write_ivar(struct device *, int, unsigned int *); 109 static int atppc_add_handler(struct device *, void (*)(void *), void *); 110 static int atppc_remove_handler(struct device *, void (*)(void *)); 111 112 /* Utility functions */ 113 114 /* Functions to read bytes into device's input buffer */ 115 static void atppc_nibble_read(struct atppc_softc * const); 116 static void atppc_byte_read(struct atppc_softc * const); 117 static void atppc_epp_read(struct atppc_softc * const); 118 static void atppc_ecp_read(struct atppc_softc * const); 119 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 120 unsigned char); 121 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 122 unsigned char); 123 static void atppc_ecp_read_error(struct atppc_softc *, const unsigned int); 124 125 126 /* Functions to write bytes to device's output buffer */ 127 static void atppc_std_write(struct atppc_softc * const); 128 static void atppc_epp_write(struct atppc_softc * const); 129 static void atppc_fifo_write(struct atppc_softc * const); 130 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 131 unsigned char); 132 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 133 unsigned char); 134 static void atppc_fifo_write_error(struct atppc_softc * const, 135 const unsigned int); 136 137 /* Miscellaneous */ 138 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 139 const u_int8_t); 140 static int atppc_wait_interrupt(struct atppc_softc * const, const caddr_t, 141 const u_int8_t); 142 143 144 /* 145 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 146 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 147 */ 148 149 /* Soft configuration attach for atppc */ 150 void 151 atppc_sc_attach(struct atppc_softc * lsc) 152 { 153 /* Adapter used to configure ppbus device */ 154 struct parport_adapter sc_parport_adapter; 155 char buf[64]; 156 157 /* Probe and set up chipset */ 158 if(atppc_detect_chipset(lsc) != 0) { 159 if(atppc_detect_generic(lsc) != 0) { 160 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 161 dev->dv_xname)); 162 } 163 } 164 165 /* Probe and setup FIFO queue */ 166 if (atppc_detect_fifo(lsc) == 0) { 167 printf("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 168 lsc->sc_dev.dv_xname, lsc->sc_fifo, lsc->sc_wthr, 169 lsc->sc_rthr); 170 } 171 172 /* Print out chipset capabilities */ 173 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 174 buf, sizeof(buf)); 175 printf("%s: capabilities=%s\n", lsc->sc_dev.dv_xname, buf); 176 177 /* Initialize device's buffer pointers */ 178 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 179 = NULL; 180 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 181 182 /* Last configuration step: set mode to standard mode */ 183 if(atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 184 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 185 lsc->sc_dev.dv_xname)); 186 } 187 188 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 189 /* Initialize lock structure */ 190 simple_lock_init(&(lsc->sc_lock)); 191 #endif 192 193 /* Set up parport_adapter structure */ 194 195 /* Set capabilites */ 196 sc_parport_adapter.capabilities = 0; 197 if(lsc->sc_has & ATPPC_HAS_INTR) { 198 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 199 } 200 if(lsc->sc_has & ATPPC_HAS_DMA) { 201 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 202 } 203 if(lsc->sc_has & ATPPC_HAS_FIFO) { 204 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 205 } 206 if(lsc->sc_has & ATPPC_HAS_PS2) { 207 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 208 } 209 if(lsc->sc_has & ATPPC_HAS_EPP) { 210 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 211 } 212 if(lsc->sc_has & ATPPC_HAS_ECP) { 213 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 214 } 215 216 /* Set function pointers */ 217 sc_parport_adapter.parport_io = atppc_io; 218 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 219 sc_parport_adapter.parport_reset_epp_timeout = 220 atppc_reset_epp_timeout; 221 sc_parport_adapter.parport_setmode = atppc_setmode; 222 sc_parport_adapter.parport_getmode = atppc_getmode; 223 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 224 sc_parport_adapter.parport_read = atppc_read; 225 sc_parport_adapter.parport_write = atppc_write; 226 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 227 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 228 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 229 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 230 sc_parport_adapter.parport_add_handler = atppc_add_handler; 231 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 232 233 /* Initialize handler list, may be added to by grandchildren */ 234 SLIST_INIT(&(lsc->sc_handler_listhead)); 235 236 /* Initialize interrupt state */ 237 lsc->sc_irqstat = ATPPC_IRQ_NONE; 238 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 239 240 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 241 lsc->sc_use = 0; 242 243 /* Configure child of the device. */ 244 lsc->child = config_found_sm(&(lsc->sc_dev), &(sc_parport_adapter), 245 atppc_print, NULL); 246 247 return; 248 } 249 250 /* Soft configuration detach */ 251 int atppc_sc_detach(struct atppc_softc * lsc, int flag) 252 { 253 struct device * dev = (struct device *) lsc; 254 255 /* Detach children devices */ 256 if(config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 257 printf("%s not able to detach child device, ", dev->dv_xname); 258 259 if(!(flag & DETACH_FORCE)) { 260 printf("cannot detach\n"); 261 return 1; 262 } 263 else { 264 printf("continuing (DETACH_FORCE)\n"); 265 } 266 } 267 268 if(!(flag & DETACH_QUIET)) 269 printf("%s detached", dev->dv_xname); 270 271 return 0; 272 } 273 274 /* Used by config_found_sm() to print out device information */ 275 static int 276 atppc_print(void * aux, const char * name) 277 { 278 /* Print out something on failure. */ 279 if(name != NULL) { 280 printf("%s: child devices", name); 281 return UNCONF; 282 } 283 284 return QUIET; 285 } 286 287 /* 288 * Machine independent detection routines for atppc driver. 289 */ 290 291 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 292 int 293 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 294 { 295 /* 296 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() * in original lpt driver. 297 * Write to data register common to all controllers and read back the 298 * values. Also tests control and status registers. 299 */ 300 301 /* 302 * Cannot use convenient macros because the device's config structure 303 * may not have been created yet: major change from FreeBSD code. 304 */ 305 306 int rval; 307 u_int8_t ctr_sav, dtr_sav, str_sav; 308 309 /* Store writtable registers' values and test if they can be read */ 310 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 311 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 312 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 313 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 314 BUS_SPACE_BARRIER_READ); 315 316 /* 317 * Ensure PS2 ports in output mode, also read back value of control 318 * register. 319 */ 320 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 321 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 322 BUS_SPACE_BARRIER_WRITE); 323 324 if(bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 325 rval = 0; 326 } 327 else { 328 /* 329 * Test if two values can be written and read from the data 330 * register. 331 */ 332 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 333 BUS_SPACE_BARRIER_READ); 334 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 335 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 336 BUS_SPACE_BARRIER_WRITE); 337 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 338 rval = 1; 339 } 340 else { 341 /* Second value to test */ 342 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 343 BUS_SPACE_BARRIER_READ); 344 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 345 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 346 BUS_SPACE_BARRIER_WRITE); 347 if(bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 348 rval = 1; 349 } 350 else { 351 rval = 0; 352 } 353 } 354 355 } 356 357 /* Restore registers */ 358 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 359 BUS_SPACE_BARRIER_READ); 360 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 361 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 362 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 363 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 364 BUS_SPACE_BARRIER_WRITE); 365 366 return rval; 367 } 368 369 /* Detect parallel port chipset. */ 370 static int 371 atppc_detect_chipset(struct atppc_softc * atppc) 372 { 373 /* Try each detection routine. */ 374 int i, mode; 375 for (i = 0; chipset_detect[i] != NULL; i++) { 376 if ((mode = chipset_detect[i](atppc)) != -1) { 377 atppc->sc_mode = mode; 378 return 0; 379 } 380 } 381 382 return 1; 383 } 384 385 /* Detect generic capabilities. */ 386 static int 387 atppc_detect_generic(struct atppc_softc * atppc) 388 { 389 u_int8_t ecr_sav = atppc_r_ecr(atppc); 390 u_int8_t ctr_sav = atppc_r_ctr(atppc); 391 u_int8_t str_sav = atppc_r_str(atppc); 392 u_int8_t tmp; 393 atppc_barrier_r(atppc); 394 395 /* Default to generic */ 396 atppc->sc_type = ATPPC_TYPE_GENERIC; 397 atppc->sc_model = GENERIC; 398 399 /* Check for ECP */ 400 tmp = atppc_r_ecr(atppc); 401 atppc_barrier_r(atppc); 402 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 403 atppc_w_ecr(atppc, 0x34); 404 atppc_barrier_w(atppc); 405 tmp = atppc_r_ecr(atppc); 406 atppc_barrier_r(atppc); 407 if(tmp == 0x35) { 408 atppc->sc_has |= ATPPC_HAS_ECP; 409 } 410 } 411 412 /* Allow search for SMC style ECP+EPP mode */ 413 if(atppc->sc_has & ATPPC_HAS_ECP) { 414 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 415 atppc_barrier_w(atppc); 416 } 417 /* Check for EPP by checking for timeout bit */ 418 if(atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 419 atppc->sc_has |= ATPPC_HAS_EPP; 420 atppc->sc_epp = ATPPC_EPP_1_9; 421 if(atppc->sc_has & ATPPC_HAS_ECP) { 422 /* SMC like chipset found */ 423 atppc->sc_model = SMC_LIKE; 424 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 425 } 426 } 427 428 /* Detect PS2 mode */ 429 if(atppc->sc_has & ATPPC_HAS_ECP) { 430 /* Put ECP port into PS2 mode */ 431 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 432 atppc_barrier_w(atppc); 433 } 434 /* Put PS2 port in input mode: writes should not be readable */ 435 atppc_w_ctr(atppc, 0x20); 436 atppc_barrier_w(atppc); 437 /* 438 * Write two values to data port: if neither are read back, 439 * bidirectional mode is functional. 440 */ 441 atppc_w_dtr(atppc, 0xaa); 442 atppc_barrier_w(atppc); 443 tmp = atppc_r_dtr(atppc); 444 atppc_barrier_r(atppc); 445 if(tmp != 0xaa) { 446 atppc_w_dtr(atppc, 0x55); 447 atppc_barrier_w(atppc); 448 tmp = atppc_r_dtr(atppc); 449 atppc_barrier_r(atppc); 450 if(tmp != 0x55) { 451 atppc->sc_has |= ATPPC_HAS_PS2; 452 } 453 } 454 455 /* Restore to previous state */ 456 atppc_w_ecr(atppc, ecr_sav); 457 atppc_w_ctr(atppc, ctr_sav); 458 atppc_w_str(atppc, str_sav); 459 atppc_barrier_w(atppc); 460 461 return 0; 462 } 463 464 /* 465 * Detect parallel port FIFO: taken from FreeBSD code directly. 466 */ 467 static int 468 atppc_detect_fifo(struct atppc_softc * atppc) 469 { 470 #ifdef ATPPC_DEBUG 471 struct device * dev = (struct device *)atppc; 472 #endif 473 u_int8_t ecr_sav; 474 u_int8_t ctr_sav; 475 u_int8_t str_sav; 476 u_int8_t cc; 477 short i; 478 479 /* If there is no ECP mode, we cannot config a FIFO */ 480 if(!(atppc->sc_has & ATPPC_HAS_ECP)) { 481 return (EINVAL); 482 } 483 484 /* save registers */ 485 ecr_sav = atppc_r_ecr(atppc); 486 ctr_sav = atppc_r_ctr(atppc); 487 str_sav = atppc_r_str(atppc); 488 atppc_barrier_r(atppc); 489 490 /* Enter ECP configuration mode, no interrupt, no DMA */ 491 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 492 ~ATPPC_ENABLE_DMA); 493 atppc_barrier_w(atppc); 494 495 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 496 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 497 atppc_barrier_r(atppc); 498 499 /* XXX 16 and 32 bits implementations not supported */ 500 if(atppc->sc_pword != ATPPC_PWORD_8) { 501 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 502 __func__, dev->dv_xname, atppc->sc_pword)); 503 goto error; 504 } 505 506 /* Byte mode, reverse direction, no interrupt, no DMA */ 507 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 508 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 509 /* enter ECP test mode, no interrupt, no DMA */ 510 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 511 atppc_barrier_w(atppc); 512 513 /* flush the FIFO */ 514 for (i = 0; i < 1024; i++) { 515 atppc_r_fifo(atppc); 516 atppc_barrier_r(atppc); 517 cc = atppc_r_ecr(atppc); 518 atppc_barrier_r(atppc); 519 if(cc & ATPPC_FIFO_EMPTY) 520 break; 521 } 522 if (i >= 1024) { 523 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 524 dev->dv_xname)); 525 goto error; 526 } 527 528 /* Test mode, enable interrupts, no DMA */ 529 atppc_w_ecr(atppc, ATPPC_ECR_TST); 530 atppc_barrier_w(atppc); 531 532 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 533 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 534 atppc_w_fifo(atppc, (char)i); 535 atppc_barrier_w(atppc); 536 cc = atppc_r_ecr(atppc); 537 atppc_barrier_r(atppc); 538 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 539 /* readThreshold reached */ 540 atppc->sc_rthr = i + 1; 541 } 542 if (cc & ATPPC_FIFO_FULL) { 543 atppc->sc_fifo = i + 1; 544 break; 545 } 546 } 547 if (i >= 1024) { 548 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 549 dev->dv_xname)); 550 goto error; 551 } 552 553 /* Change direction */ 554 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 555 atppc_barrier_w(atppc); 556 557 /* Clear the serviceIntr bit we've already set in the above loop */ 558 atppc_w_ecr(atppc, ATPPC_ECR_TST); 559 atppc_barrier_w(atppc); 560 561 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 562 for(atppc->sc_wthr = 0; i > -1; i--) { 563 cc = atppc_r_fifo(atppc); 564 atppc_barrier_r(atppc); 565 if(cc != (char)(atppc->sc_fifo - i - 1)) { 566 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 567 __func__, dev->dv_xname)); 568 goto error; 569 } 570 571 cc = atppc_r_ecr(atppc); 572 atppc_barrier_r(atppc); 573 if((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 574 /* writeIntrThreshold reached */ 575 atppc->sc_wthr = atppc->sc_fifo - i; 576 } 577 578 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 579 /* If FIFO empty before the last byte, error */ 580 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 581 dev->dv_xname)); 582 goto error; 583 } 584 } 585 586 /* FIFO must be empty after the last byte */ 587 cc = atppc_r_ecr(atppc); 588 atppc_barrier_r(atppc); 589 if (!(cc & ATPPC_FIFO_EMPTY)) { 590 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 591 dev->dv_xname)); 592 goto error; 593 } 594 595 /* Restore original registers */ 596 atppc_w_ctr(atppc, ctr_sav); 597 atppc_w_str(atppc, str_sav); 598 atppc_w_ecr(atppc, ecr_sav); 599 atppc_barrier_w(atppc); 600 601 /* Update capabilities */ 602 atppc->sc_has |= ATPPC_HAS_FIFO; 603 604 return 0; 605 606 error: 607 /* Restore original registers */ 608 atppc_w_ctr(atppc, ctr_sav); 609 atppc_w_str(atppc, str_sav); 610 atppc_w_ecr(atppc, ecr_sav); 611 atppc_barrier_w(atppc); 612 613 return (EINVAL); 614 } 615 616 /* Interrupt handler for atppc device: wakes up read/write functions */ 617 int 618 atppcintr(void * arg) 619 { 620 struct atppc_softc * atppc = (struct atppc_softc *) arg; 621 struct device * dev = (struct device *) arg; 622 int error = 1; 623 enum { NONE, READER, WRITER } wake_up = NONE; 624 int s; 625 626 s = splatppc(); 627 ATPPC_LOCK(atppc); 628 629 /* Record registers' status */ 630 atppc->sc_str_intr = atppc_r_str(atppc); 631 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 632 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 633 atppc_barrier_r(atppc); 634 635 /* Determine cause of interrupt and wake up top half */ 636 switch(atppc->sc_mode) { 637 case ATPPC_MODE_STD: 638 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 639 atppc->sc_irqstat = ATPPC_IRQ_nACK; 640 if(atppc->sc_outb) 641 wake_up = WRITER; 642 else 643 error = -1; 644 break; 645 646 case ATPPC_MODE_NIBBLE: 647 case ATPPC_MODE_PS2: 648 /* nAck is set low by device and then high on ack */ 649 if(!(atppc->sc_str_intr & nACK)) { 650 error = 0; 651 break; 652 } 653 atppc->sc_irqstat = ATPPC_IRQ_nACK; 654 if(atppc->sc_inb) 655 wake_up = READER; 656 else 657 error = -1; 658 break; 659 660 case ATPPC_MODE_ECP: 661 case ATPPC_MODE_FAST: 662 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 663 if(atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 664 if(atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 665 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 666 else 667 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 668 669 /* Decide where top half will be waiting */ 670 if(atppc->sc_mode & ATPPC_MODE_ECP) { 671 if(atppc->sc_ctr_intr & PCD) { 672 if(atppc->sc_inb) 673 wake_up = READER; 674 else 675 error = -1; 676 } 677 else { 678 if(atppc->sc_outb) 679 wake_up = WRITER; 680 else 681 error = -1; 682 } 683 } 684 else { 685 if(atppc->sc_outb) 686 wake_up = WRITER; 687 else 688 error = -1; 689 } 690 } 691 /* Determine if nFault has occured */ 692 if((atppc->sc_mode & ATPPC_MODE_ECP) && 693 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 694 !(atppc->sc_str_intr & nFAULT)) { 695 696 /* Device is requesting the channel */ 697 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 698 } 699 break; 700 701 case ATPPC_MODE_EPP: 702 /* nAck pulsed for 5 usec, too fast to check reliably */ 703 atppc->sc_irqstat = ATPPC_IRQ_nACK; 704 if(atppc->sc_inb) 705 wake_up = WRITER; 706 else if(atppc->sc_outb) 707 wake_up = READER; 708 else 709 error = -1; 710 break; 711 712 default: 713 panic("%s: chipset is in invalid mode.", dev->dv_xname); 714 } 715 716 switch(wake_up) { 717 case NONE: 718 break; 719 720 case READER: 721 wakeup(atppc->sc_inb); 722 break; 723 724 case WRITER: 725 wakeup(atppc->sc_outb); 726 break; 727 728 default: 729 panic("%s: this code should not be reached.\n", __func__); 730 break; 731 } 732 733 ATPPC_UNLOCK(atppc); 734 735 /* Call all of the installed handlers */ 736 { 737 struct atppc_handler_node * callback; 738 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 739 entries) { 740 (*callback->func)(callback->arg); 741 } 742 } 743 744 splx(s); 745 746 return error; 747 } 748 749 750 /* Functions which support ppbus interface */ 751 752 753 /* Check EPP mode timeout */ 754 static int 755 atppc_check_epp_timeout(struct device * dev) 756 { 757 struct atppc_softc * atppc = (struct atppc_softc *) dev; 758 int s; 759 int error; 760 761 s = splatppc(); 762 ATPPC_LOCK(atppc); 763 764 atppc_reset_epp_timeout(dev); 765 error = !(atppc_r_str(atppc) & TIMEOUT); 766 atppc_barrier_r(atppc); 767 768 ATPPC_UNLOCK(atppc); 769 splx(s); 770 771 return (error); 772 } 773 774 /* 775 * EPP timeout, according to the PC87332 manual 776 * Semantics of clearing EPP timeout bit. 777 * PC87332 - reading SPP_STR does it... 778 * SMC - write 1 to EPP timeout bit XXX 779 * Others - (?) write 0 to EPP timeout bit 780 */ 781 static void 782 atppc_reset_epp_timeout(struct device * dev) 783 { 784 struct atppc_softc * atppc = (struct atppc_softc *) dev; 785 register unsigned char r; 786 787 r = atppc_r_str(atppc); 788 atppc_barrier_r(atppc); 789 atppc_w_str(atppc, r | 0x1); 790 atppc_barrier_w(atppc); 791 atppc_w_str(atppc, r & 0xfe); 792 atppc_barrier_w(atppc); 793 794 return; 795 } 796 797 798 /* Read from atppc device: returns 0 on success. */ 799 static int 800 atppc_read(struct device * dev, char * buf, int len, int ioflag, 801 size_t * cnt) 802 { 803 struct atppc_softc * atppc = (struct atppc_softc *) dev; 804 int error = 0; 805 int s; 806 807 s = splatppc(); 808 ATPPC_LOCK(atppc); 809 810 *cnt = 0; 811 812 /* Initialize buffer */ 813 atppc->sc_inb = atppc->sc_inbstart = buf; 814 atppc->sc_inb_nbytes = len; 815 816 /* Initialize device input error state for new operation */ 817 atppc->sc_inerr = 0; 818 819 /* Call appropriate function to read bytes */ 820 switch(atppc->sc_mode) { 821 case ATPPC_MODE_STD: 822 case ATPPC_MODE_FAST: 823 error = ENODEV; 824 break; 825 826 case ATPPC_MODE_NIBBLE: 827 atppc_nibble_read(atppc); 828 break; 829 830 case ATPPC_MODE_PS2: 831 atppc_byte_read(atppc); 832 break; 833 834 case ATPPC_MODE_ECP: 835 atppc_ecp_read(atppc); 836 break; 837 838 case ATPPC_MODE_EPP: 839 atppc_epp_read(atppc); 840 break; 841 842 default: 843 panic("%s(%s): chipset in invalid mode.\n", __func__, 844 dev->dv_xname); 845 } 846 847 /* Update counter*/ 848 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 849 850 /* Reset buffer */ 851 atppc->sc_inb = atppc->sc_inbstart = NULL; 852 atppc->sc_inb_nbytes = 0; 853 854 if(!(error)) 855 error = atppc->sc_inerr; 856 857 ATPPC_UNLOCK(atppc); 858 splx(s); 859 860 return (error); 861 } 862 863 /* Write to atppc device: returns 0 on success. */ 864 static int 865 atppc_write(struct device * dev, char * buf, int len, int ioflag, size_t * cnt) 866 { 867 struct atppc_softc * const atppc = (struct atppc_softc *) dev; 868 int error = 0; 869 int s; 870 871 *cnt = 0; 872 873 s = splatppc(); 874 ATPPC_LOCK(atppc); 875 876 /* Set up line buffer */ 877 atppc->sc_outb = atppc->sc_outbstart = buf; 878 atppc->sc_outb_nbytes = len; 879 880 /* Initialize device output error state for new operation */ 881 atppc->sc_outerr = 0; 882 883 /* Call appropriate function to write bytes */ 884 switch(atppc->sc_mode) { 885 case ATPPC_MODE_STD: 886 atppc_std_write(atppc); 887 break; 888 889 case ATPPC_MODE_NIBBLE: 890 case ATPPC_MODE_PS2: 891 error = ENODEV; 892 break; 893 894 case ATPPC_MODE_FAST: 895 case ATPPC_MODE_ECP: 896 atppc_fifo_write(atppc); 897 break; 898 899 case ATPPC_MODE_EPP: 900 atppc_epp_write(atppc); 901 break; 902 903 default: 904 panic("%s(%s): chipset in invalid mode.\n", __func__, 905 dev->dv_xname); 906 } 907 908 /* Update counter*/ 909 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 910 911 /* Reset output buffer */ 912 atppc->sc_outb = atppc->sc_outbstart = NULL; 913 atppc->sc_outb_nbytes = 0; 914 915 if(!(error)) 916 error = atppc->sc_outerr; 917 918 ATPPC_UNLOCK(atppc); 919 splx(s); 920 921 return (error); 922 } 923 924 /* 925 * Set mode of chipset to mode argument. Modes not supported are ignored. If 926 * multiple modes are flagged, the mode is not changed. Mode's are those 927 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 928 * can change their mode of operation. However, ALL operation modes support 929 * centronics mode and nibble mode. Modes determine both hardware AND software 930 * behaviour. 931 * NOTE: the mode for ECP should only be changed when the channel is in 932 * forward idle mode. This function does not make sure FIFO's have flushed or 933 * any consistency checks. 934 */ 935 static int 936 atppc_setmode(struct device * dev, int mode) 937 { 938 struct atppc_softc * atppc = (struct atppc_softc *) dev; 939 u_int8_t ecr; 940 u_int8_t chipset_mode; 941 int s; 942 int rval = 0; 943 944 s = splatppc(); 945 ATPPC_LOCK(atppc); 946 947 /* If ECP capable, configure ecr register */ 948 if (atppc->sc_has & ATPPC_HAS_ECP) { 949 /* Read ECR with mode masked out */ 950 ecr = (atppc_r_ecr(atppc) & (unsigned)0x1f); 951 atppc_barrier_r(atppc); 952 953 switch(mode) { 954 case PPBUS_ECP: 955 /* Set ECP mode */ 956 ecr |= ATPPC_ECR_ECP; 957 chipset_mode = ATPPC_MODE_ECP; 958 break; 959 960 case PPBUS_EPP: 961 /* Set EPP mode */ 962 if(atppc->sc_has & ATPPC_HAS_EPP) { 963 ecr |= ATPPC_ECR_EPP; 964 chipset_mode = ATPPC_MODE_EPP; 965 } 966 else { 967 rval = ENODEV; 968 goto end; 969 } 970 break; 971 972 case PPBUS_FAST: 973 /* Set fast centronics mode */ 974 ecr |= ATPPC_ECR_FIFO; 975 chipset_mode = ATPPC_MODE_FAST; 976 break; 977 978 case PPBUS_PS2: 979 /* Set PS2 mode */ 980 ecr |= ATPPC_ECR_PS2; 981 chipset_mode = ATPPC_MODE_PS2; 982 break; 983 984 case PPBUS_COMPATIBLE: 985 /* Set standard mode */ 986 ecr |= ATPPC_ECR_STD; 987 chipset_mode = ATPPC_MODE_STD;; 988 break; 989 990 case PPBUS_NIBBLE: 991 /* Set nibble mode: uses chipset standard mode */ 992 ecr |= ATPPC_ECR_STD; 993 chipset_mode = ATPPC_MODE_NIBBLE; 994 break; 995 996 default: 997 /* Invalid mode specified for ECP chip */ 998 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 999 "argument.\n", __func__, dev->dv_xname)); 1000 rval = ENODEV; 1001 goto end; 1002 } 1003 1004 /* Switch to byte mode to be able to change modes. */ 1005 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1006 atppc_barrier_w(atppc); 1007 1008 /* Update mode */ 1009 atppc_w_ecr(atppc, ecr); 1010 atppc_barrier_w(atppc); 1011 } 1012 else { 1013 switch(mode) { 1014 case PPBUS_EPP: 1015 if(atppc->sc_has & ATPPC_HAS_EPP) { 1016 chipset_mode = ATPPC_MODE_EPP; 1017 } 1018 else { 1019 rval = ENODEV; 1020 goto end; 1021 } 1022 break; 1023 1024 case PPBUS_PS2: 1025 if(atppc->sc_has & ATPPC_HAS_PS2) { 1026 chipset_mode = ATPPC_MODE_PS2; 1027 } 1028 else { 1029 rval = ENODEV; 1030 goto end; 1031 } 1032 break; 1033 1034 case PPBUS_NIBBLE: 1035 /* Set nibble mode (virtual) */ 1036 chipset_mode = ATPPC_MODE_NIBBLE; 1037 break; 1038 1039 case PPBUS_COMPATIBLE: 1040 chipset_mode = ATPPC_MODE_STD; 1041 break; 1042 1043 case PPBUS_ECP: 1044 rval = ENODEV; 1045 goto end; 1046 1047 default: 1048 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1049 "argument.\n", __func__, dev->dv_xname)); 1050 rval = ENODEV; 1051 goto end; 1052 } 1053 } 1054 1055 atppc->sc_mode = chipset_mode; 1056 if(chipset_mode == ATPPC_MODE_PS2) { 1057 /* Set direction bit to reverse */ 1058 ecr = atppc_r_ctr(atppc); 1059 atppc_barrier_r(atppc); 1060 ecr |= PCD; 1061 atppc_w_ctr(atppc, ecr); 1062 atppc_barrier_w(atppc); 1063 } 1064 1065 end: 1066 ATPPC_UNLOCK(atppc); 1067 splx(s); 1068 1069 return rval; 1070 } 1071 1072 /* Get the current mode of chipset */ 1073 static int 1074 atppc_getmode(struct device * dev) 1075 { 1076 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1077 int mode; 1078 int s; 1079 1080 s = splatppc(); 1081 ATPPC_LOCK(atppc); 1082 1083 /* The chipset can only be in one mode at a time logically */ 1084 switch(atppc->sc_mode) { 1085 case ATPPC_MODE_ECP: 1086 mode = PPBUS_ECP; 1087 break; 1088 1089 case ATPPC_MODE_EPP: 1090 mode = PPBUS_EPP; 1091 break; 1092 1093 case ATPPC_MODE_PS2: 1094 mode = PPBUS_PS2; 1095 break; 1096 1097 case ATPPC_MODE_STD: 1098 mode = PPBUS_COMPATIBLE; 1099 break; 1100 1101 case ATPPC_MODE_NIBBLE: 1102 mode = PPBUS_NIBBLE; 1103 break; 1104 1105 case ATPPC_MODE_FAST: 1106 mode = PPBUS_FAST; 1107 break; 1108 1109 default: 1110 panic("%s(%s): device is in invalid mode!", __func__, 1111 dev->dv_xname); 1112 break; 1113 } 1114 1115 ATPPC_UNLOCK(atppc); 1116 splx(s); 1117 1118 return mode; 1119 } 1120 1121 1122 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1123 static void 1124 atppc_ecp_sync(struct device * dev) 1125 { 1126 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1127 int i; 1128 int s; 1129 u_int8_t r; 1130 1131 s = splatppc(); 1132 ATPPC_LOCK(atppc); 1133 1134 /* 1135 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1136 * the mode is either ECP or Fast Centronics. 1137 */ 1138 r = atppc_r_ecr(atppc); 1139 atppc_barrier_r(atppc); 1140 r &= 0xe0; 1141 if(!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1142 && (r != ATPPC_ECR_FIFO))) { 1143 goto end; 1144 } 1145 1146 /* Wait for FIFO to empty */ 1147 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1148 r = atppc_r_ecr(atppc); 1149 atppc_barrier_r(atppc); 1150 if (r & ATPPC_FIFO_EMPTY) { 1151 goto end; 1152 } 1153 delay(100); /* Supposed to be a 100 usec delay */ 1154 } 1155 1156 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1157 dev->dv_xname)); 1158 1159 end: 1160 ATPPC_UNLOCK(atppc); 1161 splx(s); 1162 1163 return; 1164 } 1165 1166 /* Execute a microsequence to handle fast I/O operations. */ 1167 static int 1168 atppc_exec_microseq(struct device * dev, struct ppbus_microseq * * p_msq) 1169 { 1170 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1171 struct ppbus_microseq * mi = *p_msq; 1172 char cc, * p; 1173 int i, iter, len; 1174 int error; 1175 int s; 1176 register int reg; 1177 register unsigned char mask; 1178 register int accum = 0; 1179 register char * ptr = NULL; 1180 struct ppbus_microseq * stack = NULL; 1181 1182 s = splatppc(); 1183 ATPPC_LOCK(atppc); 1184 1185 /* microsequence registers are equivalent to PC-like port registers */ 1186 1187 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1188 (atppc)->sc_ioh, (register)) 1189 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1190 (atppc)->sc_ioh, (register), (byte)) 1191 1192 /* Loop until microsequence execution finishes (ending op code) */ 1193 for (;;) { 1194 switch (mi->opcode) { 1195 case MS_OP_RSET: 1196 cc = r_reg(mi->arg[0].i, atppc); 1197 atppc_barrier_r(atppc); 1198 cc &= (char)mi->arg[2].i; /* clear mask */ 1199 cc |= (char)mi->arg[1].i; /* assert mask */ 1200 w_reg(mi->arg[0].i, atppc, cc); 1201 atppc_barrier_w(atppc); 1202 mi++; 1203 break; 1204 1205 case MS_OP_RASSERT_P: 1206 reg = mi->arg[1].i; 1207 ptr = atppc->sc_ptr; 1208 1209 if((len = mi->arg[0].i) == MS_ACCUM) { 1210 accum = atppc->sc_accum; 1211 for (; accum; accum--) { 1212 w_reg(reg, atppc, *ptr++); 1213 atppc_barrier_w(atppc); 1214 } 1215 atppc->sc_accum = accum; 1216 } 1217 else { 1218 for(i = 0; i < len; i++) { 1219 w_reg(reg, atppc, *ptr++); 1220 atppc_barrier_w(atppc); 1221 } 1222 } 1223 1224 atppc->sc_ptr = ptr; 1225 mi++; 1226 break; 1227 1228 case MS_OP_RFETCH_P: 1229 reg = mi->arg[1].i; 1230 mask = (char)mi->arg[2].i; 1231 ptr = atppc->sc_ptr; 1232 1233 if((len = mi->arg[0].i) == MS_ACCUM) { 1234 accum = atppc->sc_accum; 1235 for (; accum; accum--) { 1236 *ptr++ = r_reg(reg, atppc) & mask; 1237 atppc_barrier_r(atppc); 1238 } 1239 atppc->sc_accum = accum; 1240 } 1241 else { 1242 for(i = 0; i < len; i++) { 1243 *ptr++ = r_reg(reg, atppc) & mask; 1244 atppc_barrier_r(atppc); 1245 } 1246 } 1247 1248 atppc->sc_ptr = ptr; 1249 mi++; 1250 break; 1251 1252 case MS_OP_RFETCH: 1253 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1254 (char)mi->arg[1].i; 1255 atppc_barrier_r(atppc); 1256 mi++; 1257 break; 1258 1259 case MS_OP_RASSERT: 1260 case MS_OP_DELAY: 1261 /* let's suppose the next instr. is the same */ 1262 do { 1263 for(;mi->opcode == MS_OP_RASSERT; mi++) { 1264 w_reg(mi->arg[0].i, atppc, 1265 (char)mi->arg[1].i); 1266 atppc_barrier_w(atppc); 1267 } 1268 1269 for(;mi->opcode == MS_OP_DELAY; mi++) { 1270 delay(mi->arg[0].i); 1271 } 1272 } while(mi->opcode == MS_OP_RASSERT); 1273 break; 1274 1275 case MS_OP_ADELAY: 1276 if(mi->arg[0].i) { 1277 tsleep(atppc, PPBUSPRI, "atppcdelay", 1278 mi->arg[0].i * (hz/1000)); 1279 } 1280 mi++; 1281 break; 1282 1283 case MS_OP_TRIG: 1284 reg = mi->arg[0].i; 1285 iter = mi->arg[1].i; 1286 p = (char *)mi->arg[2].p; 1287 1288 /* XXX delay limited to 255 us */ 1289 for(i = 0; i < iter; i++) { 1290 w_reg(reg, atppc, *p++); 1291 atppc_barrier_w(atppc); 1292 delay((unsigned char)*p++); 1293 } 1294 1295 mi++; 1296 break; 1297 1298 case MS_OP_SET: 1299 atppc->sc_accum = mi->arg[0].i; 1300 mi++; 1301 break; 1302 1303 case MS_OP_DBRA: 1304 if(--atppc->sc_accum > 0) { 1305 mi += mi->arg[0].i; 1306 } 1307 1308 mi++; 1309 break; 1310 1311 case MS_OP_BRSET: 1312 cc = atppc_r_str(atppc); 1313 atppc_barrier_r(atppc); 1314 if((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1315 mi += mi->arg[1].i; 1316 } 1317 mi++; 1318 break; 1319 1320 case MS_OP_BRCLEAR: 1321 cc = atppc_r_str(atppc); 1322 atppc_barrier_r(atppc); 1323 if((cc & (char)mi->arg[0].i) == 0) { 1324 mi += mi->arg[1].i; 1325 } 1326 mi++; 1327 break; 1328 1329 case MS_OP_BRSTAT: 1330 cc = atppc_r_str(atppc); 1331 atppc_barrier_r(atppc); 1332 if((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1333 (char)mi->arg[0].i) { 1334 mi += mi->arg[2].i; 1335 } 1336 mi++; 1337 break; 1338 1339 case MS_OP_C_CALL: 1340 /* 1341 * If the C call returns !0 then end the microseq. 1342 * The current state of ptr is passed to the C function 1343 */ 1344 if((error = mi->arg[0].f(mi->arg[1].p, 1345 atppc->sc_ptr))) { 1346 ATPPC_UNLOCK(atppc); 1347 splx(s); 1348 return (error); 1349 } 1350 mi++; 1351 break; 1352 1353 case MS_OP_PTR: 1354 atppc->sc_ptr = (char *)mi->arg[0].p; 1355 mi++; 1356 break; 1357 1358 case MS_OP_CALL: 1359 if (stack) { 1360 panic("%s - %s: too much calls", dev->dv_xname, 1361 __func__); 1362 } 1363 1364 if (mi->arg[0].p) { 1365 /* store state of the actual microsequence */ 1366 stack = mi; 1367 1368 /* jump to the new microsequence */ 1369 mi = (struct ppbus_microseq *)mi->arg[0].p; 1370 } 1371 else { 1372 mi++; 1373 } 1374 break; 1375 1376 case MS_OP_SUBRET: 1377 /* retrieve microseq and pc state before the call */ 1378 mi = stack; 1379 1380 /* reset the stack */ 1381 stack = 0; 1382 1383 /* XXX return code */ 1384 1385 mi++; 1386 break; 1387 1388 case MS_OP_PUT: 1389 case MS_OP_GET: 1390 case MS_OP_RET: 1391 /* 1392 * Can't return to atppc level during the execution 1393 * of a submicrosequence. 1394 */ 1395 if (stack) { 1396 panic("%s: cannot return to atppc level", 1397 __func__); 1398 } 1399 /* update pc for atppc level of execution */ 1400 *p_msq = mi; 1401 1402 ATPPC_UNLOCK(atppc); 1403 splx(s); 1404 return (0); 1405 break; 1406 1407 default: 1408 panic("%s: unknown microsequence " 1409 "opcode 0x%x", __func__, mi->opcode); 1410 break; 1411 } 1412 } 1413 1414 /* Should not be reached! */ 1415 #ifdef ATPPC_DEBUG 1416 panic("%s: unexpected code reached!\n", __func__); 1417 #endif 1418 } 1419 1420 /* General I/O routine */ 1421 static u_int8_t 1422 atppc_io(struct device * dev, int iop, u_char * addr, int cnt, u_char byte) 1423 { 1424 struct atppc_softc * atppc = (struct atppc_softc *) dev; 1425 u_int8_t val = 0; 1426 int s; 1427 1428 s = splatppc(); 1429 ATPPC_LOCK(atppc); 1430 1431 switch (iop) { 1432 case PPBUS_OUTSB_EPP: 1433 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1434 ATPPC_EPP_DATA, addr, cnt); 1435 break; 1436 case PPBUS_OUTSW_EPP: 1437 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1438 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1439 break; 1440 case PPBUS_OUTSL_EPP: 1441 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1442 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1443 break; 1444 case PPBUS_INSB_EPP: 1445 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1446 ATPPC_EPP_DATA, addr, cnt); 1447 break; 1448 case PPBUS_INSW_EPP: 1449 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1450 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1451 break; 1452 case PPBUS_INSL_EPP: 1453 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1454 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1455 break; 1456 case PPBUS_RDTR: 1457 val = (atppc_r_dtr(atppc)); 1458 break; 1459 case PPBUS_RSTR: 1460 val = (atppc_r_str(atppc)); 1461 break; 1462 case PPBUS_RCTR: 1463 val = (atppc_r_ctr(atppc)); 1464 break; 1465 case PPBUS_REPP_A: 1466 val = (atppc_r_eppA(atppc)); 1467 break; 1468 case PPBUS_REPP_D: 1469 val = (atppc_r_eppD(atppc)); 1470 break; 1471 case PPBUS_RECR: 1472 val = (atppc_r_ecr(atppc)); 1473 break; 1474 case PPBUS_RFIFO: 1475 val = (atppc_r_fifo(atppc)); 1476 break; 1477 case PPBUS_WDTR: 1478 atppc_w_dtr(atppc, byte); 1479 break; 1480 case PPBUS_WSTR: 1481 atppc_w_str(atppc, byte); 1482 break; 1483 case PPBUS_WCTR: 1484 atppc_w_ctr(atppc, byte); 1485 break; 1486 case PPBUS_WEPP_A: 1487 atppc_w_eppA(atppc, byte); 1488 break; 1489 case PPBUS_WEPP_D: 1490 atppc_w_eppD(atppc, byte); 1491 break; 1492 case PPBUS_WECR: 1493 atppc_w_ecr(atppc, byte); 1494 break; 1495 case PPBUS_WFIFO: 1496 atppc_w_fifo(atppc, byte); 1497 break; 1498 default: 1499 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1500 __func__); 1501 break; 1502 } 1503 1504 atppc_barrier(atppc); 1505 1506 ATPPC_UNLOCK(atppc); 1507 splx(s); 1508 1509 return val; 1510 } 1511 1512 /* Read "instance variables" of atppc device */ 1513 static int 1514 atppc_read_ivar(struct device * dev, int index, unsigned int * val) 1515 { 1516 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1517 int rval = 0; 1518 int s; 1519 1520 s = splatppc(); 1521 ATPPC_LOCK(atppc); 1522 1523 switch(index) { 1524 case PPBUS_IVAR_EPP_PROTO: 1525 if(atppc->sc_epp == ATPPC_EPP_1_9) 1526 *val = PPBUS_EPP_1_9; 1527 else if(atppc->sc_epp == ATPPC_EPP_1_7) 1528 *val = PPBUS_EPP_1_7; 1529 break; 1530 1531 case PPBUS_IVAR_INTR: 1532 if(atppc->sc_use & ATPPC_USE_INTR) 1533 *val = 1; 1534 else 1535 *val = 0; 1536 break; 1537 1538 case PPBUS_IVAR_DMA: 1539 if(atppc->sc_use & ATPPC_USE_DMA) 1540 *val = 1; 1541 else 1542 *val = 0; 1543 break; 1544 break; 1545 1546 default: 1547 rval = ENODEV; 1548 } 1549 1550 ATPPC_UNLOCK(atppc); 1551 splx(s); 1552 1553 return rval; 1554 } 1555 1556 /* Write "instance varaibles" of atppc device */ 1557 static int 1558 atppc_write_ivar(struct device * dev, int index, unsigned int * val) 1559 { 1560 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1561 int rval = 0; 1562 int s; 1563 1564 s = splatppc(); 1565 ATPPC_LOCK(atppc); 1566 1567 switch(index) { 1568 case PPBUS_IVAR_EPP_PROTO: 1569 if(*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1570 atppc->sc_epp = *val; 1571 else 1572 rval = EINVAL; 1573 break; 1574 1575 case PPBUS_IVAR_INTR: 1576 if(*val == 0) 1577 atppc->sc_use &= ~ATPPC_USE_INTR; 1578 else if(atppc->sc_has & ATPPC_HAS_INTR) 1579 atppc->sc_use |= ATPPC_USE_INTR; 1580 else 1581 rval = ENODEV; 1582 break; 1583 1584 case PPBUS_IVAR_DMA: 1585 if(*val == 0) 1586 atppc->sc_use &= ~ATPPC_USE_DMA; 1587 else if(atppc->sc_has & ATPPC_HAS_DMA) 1588 atppc->sc_use |= ATPPC_USE_DMA; 1589 else 1590 rval = ENODEV; 1591 break; 1592 1593 default: 1594 rval = ENODEV; 1595 } 1596 1597 ATPPC_UNLOCK(atppc); 1598 splx(s); 1599 1600 return rval; 1601 } 1602 1603 /* Add a handler routine to be called by the interrupt handler */ 1604 static int 1605 atppc_add_handler(struct device * dev, void (*handler)(void *), void *arg) 1606 { 1607 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1608 struct atppc_handler_node * callback; 1609 int rval = 0; 1610 int s; 1611 1612 s = splatppc(); 1613 ATPPC_LOCK(atppc); 1614 1615 if(handler == NULL) { 1616 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1617 __func__, dev->dv_xname)); 1618 rval = EINVAL; 1619 } 1620 else { 1621 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1622 M_NOWAIT); 1623 if(callback) { 1624 callback->func = handler; 1625 callback->arg = arg; 1626 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1627 callback, entries); 1628 } 1629 else { 1630 rval = ENOMEM; 1631 } 1632 } 1633 1634 ATPPC_UNLOCK(atppc); 1635 splx(s); 1636 1637 return rval; 1638 } 1639 1640 /* Remove a handler added by atppc_add_handler() */ 1641 static int 1642 atppc_remove_handler(struct device * dev, void (*handler)(void *)) 1643 { 1644 struct atppc_softc * atppc = (struct atppc_softc *)dev; 1645 struct atppc_handler_node * callback; 1646 int rval = EINVAL; 1647 int s; 1648 1649 s = splatppc(); 1650 ATPPC_LOCK(atppc); 1651 1652 if(SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1653 panic("%s(%s): attempt to remove handler from empty list.\n", 1654 __func__, dev->dv_xname); 1655 1656 /* Search list for handler */ 1657 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1658 if(callback->func == handler) { 1659 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1660 atppc_handler_node, entries); 1661 free(callback, M_DEVBUF); 1662 rval = 0; 1663 break; 1664 } 1665 } 1666 1667 ATPPC_UNLOCK(atppc); 1668 splx(s); 1669 1670 return rval; 1671 } 1672 1673 /* Utility functions */ 1674 1675 1676 /* 1677 * Functions that read bytes from port into buffer: called from interrupt 1678 * handler depending on current chipset mode and cause of interrupt. Return 1679 * value: number of bytes moved. 1680 */ 1681 1682 /* Only the lower 4 bits of the final value are valid */ 1683 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1684 1685 /* Read bytes in nibble mode */ 1686 static void 1687 atppc_nibble_read(struct atppc_softc * atppc) 1688 { 1689 int i; 1690 u_int8_t nibble[2]; 1691 u_int8_t ctr; 1692 u_int8_t str; 1693 1694 /* Enable interrupts if needed */ 1695 if(atppc->sc_use & ATPPC_USE_INTR) { 1696 ctr = atppc_r_ctr(atppc); 1697 atppc_barrier_r(atppc); 1698 if(!(ctr & IRQENABLE)) { 1699 ctr |= IRQENABLE; 1700 atppc_w_ctr(atppc, ctr); 1701 atppc_barrier_w(atppc); 1702 } 1703 } 1704 1705 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1706 /* Check if device has data to send in idle phase */ 1707 str = atppc_r_str(atppc); 1708 atppc_barrier_r(atppc); 1709 if(str & nDATAVAIL) { 1710 return; 1711 } 1712 1713 /* Nibble-mode handshake transfer */ 1714 for(i = 0; i < 2; i++) { 1715 /* Event 7 - ready to take data (HOSTBUSY low) */ 1716 ctr = atppc_r_ctr(atppc); 1717 atppc_barrier_r(atppc); 1718 ctr |= HOSTBUSY; 1719 atppc_w_ctr(atppc, ctr); 1720 atppc_barrier_w(atppc); 1721 1722 /* Event 8 - peripheral writes the first nibble */ 1723 1724 /* Event 9 - peripheral set nAck low */ 1725 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1726 if(atppc->sc_inerr) 1727 return; 1728 1729 /* read nibble */ 1730 nibble[i] = atppc_r_str(atppc); 1731 1732 /* Event 10 - ack, nibble received */ 1733 ctr &= ~HOSTBUSY; 1734 atppc_w_ctr(atppc, ctr); 1735 1736 /* Event 11 - wait ack from peripherial */ 1737 if(atppc->sc_use & ATPPC_USE_INTR) 1738 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1739 atppc->sc_inb, ATPPC_IRQ_nACK); 1740 else 1741 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1742 PTRCLK); 1743 if(atppc->sc_inerr) 1744 return; 1745 } 1746 1747 /* Store byte transfered */ 1748 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1749 (nibble2char(nibble[0]) & 0x0f); 1750 atppc->sc_inbstart++; 1751 } 1752 } 1753 1754 /* Read bytes in bidirectional mode */ 1755 static void 1756 atppc_byte_read(struct atppc_softc * const atppc) 1757 { 1758 u_int8_t ctr; 1759 u_int8_t str; 1760 1761 /* Check direction bit */ 1762 ctr = atppc_r_ctr(atppc); 1763 atppc_barrier_r(atppc); 1764 if(!(ctr & PCD)) { 1765 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1766 "bit set.", atppc->sc_dev.dv_xname)); 1767 atppc->sc_inerr = ENODEV; 1768 return; 1769 } 1770 /* Enable interrupts if needed */ 1771 if(atppc->sc_use & ATPPC_USE_INTR) { 1772 if(!(ctr & IRQENABLE)) { 1773 ctr |= IRQENABLE; 1774 atppc_w_ctr(atppc, ctr); 1775 atppc_barrier_w(atppc); 1776 } 1777 } 1778 1779 /* Byte-mode handshake transfer */ 1780 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1781 /* Check if device has data to send */ 1782 str = atppc_r_str(atppc); 1783 atppc_barrier_r(atppc); 1784 if(str & nDATAVAIL) { 1785 return; 1786 } 1787 1788 /* Event 7 - ready to take data (nAUTO low) */ 1789 ctr |= HOSTBUSY; 1790 atppc_w_ctr(atppc, ctr); 1791 atppc_barrier_w(atppc); 1792 1793 /* Event 9 - peripheral set nAck low */ 1794 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1795 if(atppc->sc_inerr) 1796 return; 1797 1798 /* Store byte transfered */ 1799 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1800 atppc_barrier_r(atppc); 1801 1802 /* Event 10 - data received, can't accept more */ 1803 ctr &= ~HOSTBUSY; 1804 atppc_w_ctr(atppc, ctr); 1805 atppc_barrier_w(atppc); 1806 1807 /* Event 11 - peripheral ack */ 1808 if(atppc->sc_use & ATPPC_USE_INTR) 1809 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1810 atppc->sc_inb, ATPPC_IRQ_nACK); 1811 else 1812 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1813 if(atppc->sc_inerr) 1814 return; 1815 1816 /* Event 16 - strobe */ 1817 str |= HOSTCLK; 1818 atppc_w_str(atppc, str); 1819 atppc_barrier_w(atppc); 1820 DELAY(1); 1821 str &= ~HOSTCLK; 1822 atppc_w_str(atppc, str); 1823 atppc_barrier_w(atppc); 1824 1825 /* Update counter */ 1826 atppc->sc_inbstart++; 1827 } 1828 } 1829 1830 /* Read bytes in EPP mode */ 1831 static void 1832 atppc_epp_read(struct atppc_softc * atppc) 1833 { 1834 if(atppc->sc_epp == ATPPC_EPP_1_9) { 1835 { 1836 uint8_t str; 1837 int i; 1838 1839 atppc_reset_epp_timeout((struct device *)atppc); 1840 for(i = 0; i < atppc->sc_inb_nbytes; i++) { 1841 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1842 atppc_barrier_r(atppc); 1843 str = atppc_r_str(atppc); 1844 atppc_barrier_r(atppc); 1845 if(str & TIMEOUT) { 1846 atppc->sc_inerr = EIO; 1847 break; 1848 } 1849 atppc->sc_inbstart++; 1850 } 1851 } 1852 } 1853 else { 1854 /* Read data block from EPP data register */ 1855 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1856 atppc->sc_inb_nbytes); 1857 atppc_barrier_r(atppc); 1858 /* Update buffer position, byte count and counter */ 1859 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1860 } 1861 1862 return; 1863 } 1864 1865 /* Read bytes in ECP mode */ 1866 static void 1867 atppc_ecp_read(struct atppc_softc * atppc) 1868 { 1869 u_int8_t ecr; 1870 u_int8_t ctr; 1871 u_int8_t str; 1872 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1873 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1874 unsigned int worklen; 1875 1876 /* Check direction bit */ 1877 ctr = ctr_sav; 1878 atppc_barrier_r(atppc); 1879 if(!(ctr & PCD)) { 1880 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1881 "bit set.", atppc->sc_dev.dv_xname)); 1882 atppc->sc_inerr = ENODEV; 1883 goto end; 1884 } 1885 1886 /* Clear device request if any */ 1887 if(atppc->sc_use & ATPPC_USE_INTR) 1888 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1889 1890 while(atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1891 ecr = atppc_r_ecr(atppc); 1892 atppc_barrier_r(atppc); 1893 if(ecr & ATPPC_FIFO_EMPTY) { 1894 /* Check for invalid state */ 1895 if(ecr & ATPPC_FIFO_FULL) { 1896 atppc_ecp_read_error(atppc, worklen); 1897 break; 1898 } 1899 1900 /* Check if device has data to send */ 1901 str = atppc_r_str(atppc); 1902 atppc_barrier_r(atppc); 1903 if(str & nDATAVAIL) { 1904 break; 1905 } 1906 1907 if(atppc->sc_use & ATPPC_USE_INTR) { 1908 /* Enable interrupts */ 1909 ecr &= ~ATPPC_SERVICE_INTR; 1910 atppc_w_ecr(atppc, ecr); 1911 atppc_barrier_w(atppc); 1912 /* Wait for FIFO to fill */ 1913 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1914 atppc->sc_inb, ATPPC_IRQ_FIFO); 1915 if(atppc->sc_inerr) 1916 break; 1917 } 1918 else { 1919 DELAY(1); 1920 } 1921 continue; 1922 } 1923 else if(ecr & ATPPC_FIFO_FULL) { 1924 /* Transfer sc_fifo bytes */ 1925 worklen = atppc->sc_fifo; 1926 } 1927 else if(ecr & ATPPC_SERVICE_INTR) { 1928 /* Transfer sc_rthr bytes */ 1929 worklen = atppc->sc_rthr; 1930 } 1931 else { 1932 /* At least one byte is in the FIFO */ 1933 worklen = 1; 1934 } 1935 1936 if((atppc->sc_use & ATPPC_USE_INTR) && 1937 (atppc->sc_use & ATPPC_USE_DMA)) { 1938 1939 atppc_ecp_read_dma(atppc, &worklen, ecr); 1940 } 1941 else { 1942 atppc_ecp_read_pio(atppc, &worklen, ecr); 1943 } 1944 1945 if(atppc->sc_inerr) { 1946 atppc_ecp_read_error(atppc, worklen); 1947 break; 1948 } 1949 1950 /* Update counter */ 1951 atppc->sc_inbstart += worklen; 1952 } 1953 end: 1954 atppc_w_ctr(atppc, ctr_sav); 1955 atppc_w_ecr(atppc, ecr_sav); 1956 atppc_barrier_w(atppc); 1957 } 1958 1959 /* Read bytes in ECP mode using DMA transfers */ 1960 static void 1961 atppc_ecp_read_dma(struct atppc_softc * atppc, unsigned int * length, 1962 unsigned char ecr) 1963 { 1964 /* Limit transfer to maximum DMA size and start it */ 1965 *length = min(*length, atppc->sc_dma_maxsize); 1966 atppc->sc_dmastat = ATPPC_DMA_INIT; 1967 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1968 ATPPC_DMA_MODE_READ); 1969 1970 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1971 1972 /* Enable interrupts, DMA */ 1973 ecr &= ~ATPPC_SERVICE_INTR; 1974 ecr |= ATPPC_ENABLE_DMA; 1975 atppc_w_ecr(atppc, ecr); 1976 atppc_barrier_w(atppc); 1977 1978 /* Wait for DMA completion */ 1979 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1980 ATPPC_IRQ_DMA); 1981 if(atppc->sc_inerr) 1982 return; 1983 1984 /* Get register value recorded by interrupt handler */ 1985 ecr = atppc->sc_ecr_intr; 1986 /* Clear DMA programming */ 1987 atppc->sc_dma_finish(atppc); 1988 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1989 /* Disable DMA */ 1990 ecr &= ~ATPPC_ENABLE_DMA; 1991 atppc_w_ecr(atppc, ecr); 1992 atppc_barrier_w(atppc); 1993 } 1994 1995 /* Read bytes in ECP mode using PIO transfers */ 1996 static void 1997 atppc_ecp_read_pio(struct atppc_softc * atppc, unsigned int * length, 1998 unsigned char ecr) 1999 { 2000 /* Disable DMA */ 2001 ecr &= ~ATPPC_ENABLE_DMA; 2002 atppc_w_ecr(atppc, ecr); 2003 atppc_barrier_w(atppc); 2004 2005 /* Read from FIFO */ 2006 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 2007 } 2008 2009 /* Handle errors for ECP reads */ 2010 static void 2011 atppc_ecp_read_error(struct atppc_softc * atppc, const unsigned int worklen) 2012 { 2013 unsigned char ecr = atppc_r_ecr(atppc); 2014 2015 /* Abort DMA if not finished */ 2016 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2017 atppc->sc_dma_abort(atppc); 2018 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2019 } 2020 2021 /* Check for invalid states */ 2022 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2023 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2024 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2025 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2026 atppc_barrier_w(atppc); 2027 } 2028 } 2029 2030 /* 2031 * Functions that write bytes to port from buffer: called from atppc_write() 2032 * function depending on current chipset mode. Returns number of bytes moved. 2033 */ 2034 2035 /* Write bytes in std/bidirectional mode */ 2036 static void 2037 atppc_std_write(struct atppc_softc * const atppc) 2038 { 2039 unsigned int timecount; 2040 unsigned char ctr; 2041 2042 ctr = atppc_r_ctr(atppc); 2043 atppc_barrier_r(atppc); 2044 /* Enable interrupts if needed */ 2045 if(atppc->sc_use & ATPPC_USE_INTR) { 2046 if(!(ctr & IRQENABLE)) { 2047 ctr |= IRQENABLE; 2048 atppc_w_ctr(atppc, ctr); 2049 atppc_barrier_w(atppc); 2050 } 2051 } 2052 2053 while(atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2054 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2055 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2056 if(atppc->sc_outerr) 2057 return; 2058 2059 /* Put data in data register */ 2060 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2061 atppc_barrier_w(atppc); 2062 DELAY(1); 2063 2064 /* Pulse strobe to indicate valid data on lines */ 2065 ctr |= STROBE; 2066 atppc_w_ctr(atppc, ctr); 2067 atppc_barrier_w(atppc); 2068 DELAY(1); 2069 ctr &= ~STROBE; 2070 atppc_w_ctr(atppc, ctr); 2071 atppc_barrier_w(atppc); 2072 2073 /* Wait for nACK for MAXBUSYWAIT */ 2074 timecount = 0; 2075 if(atppc->sc_use & ATPPC_USE_INTR) { 2076 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2077 atppc->sc_outb, ATPPC_IRQ_nACK); 2078 if(atppc->sc_outerr) 2079 return; 2080 } 2081 else { 2082 /* Try to catch the pulsed acknowledgement */ 2083 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2084 if(atppc->sc_outerr) 2085 return; 2086 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2087 if(atppc->sc_outerr) 2088 return; 2089 } 2090 2091 /* Update buffer position, byte count and counter */ 2092 atppc->sc_outbstart++; 2093 } 2094 } 2095 2096 2097 /* Write bytes in EPP mode */ 2098 static void 2099 atppc_epp_write(struct atppc_softc * atppc) 2100 { 2101 if(atppc->sc_epp == ATPPC_EPP_1_9) { 2102 { 2103 uint8_t str; 2104 int i; 2105 2106 atppc_reset_epp_timeout((struct device *)atppc); 2107 for(i = 0; i < atppc->sc_outb_nbytes; i++) { 2108 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2109 atppc_barrier_w(atppc); 2110 str = atppc_r_str(atppc); 2111 atppc_barrier_r(atppc); 2112 if(str & TIMEOUT) { 2113 atppc->sc_outerr = EIO; 2114 break; 2115 } 2116 atppc->sc_outbstart++; 2117 } 2118 } 2119 } 2120 else { 2121 /* Write data block to EPP data register */ 2122 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2123 atppc->sc_outb_nbytes); 2124 atppc_barrier_w(atppc); 2125 /* Update buffer position, byte count and counter */ 2126 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2127 } 2128 2129 return; 2130 } 2131 2132 2133 /* Write bytes in ECP/Fast Centronics mode */ 2134 static void 2135 atppc_fifo_write(struct atppc_softc * const atppc) 2136 { 2137 unsigned char ctr; 2138 unsigned char ecr; 2139 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2140 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2141 2142 ctr = ctr_sav; 2143 ecr = ecr_sav; 2144 atppc_barrier_r(atppc); 2145 2146 /* Reset and flush FIFO */ 2147 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2148 atppc_barrier_w(atppc); 2149 /* Disable nAck interrupts and initialize port bits */ 2150 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2151 atppc_w_ctr(atppc, ctr); 2152 atppc_barrier_w(atppc); 2153 /* Restore mode */ 2154 atppc_w_ecr(atppc, ecr); 2155 atppc_barrier_w(atppc); 2156 2157 /* DMA or Programmed IO */ 2158 if((atppc->sc_use & ATPPC_USE_DMA) && 2159 (atppc->sc_use & ATPPC_USE_INTR)) { 2160 2161 atppc_fifo_write_dma(atppc, ecr, ctr); 2162 } 2163 else { 2164 atppc_fifo_write_pio(atppc, ecr, ctr); 2165 } 2166 2167 /* Restore original register values */ 2168 atppc_w_ctr(atppc, ctr_sav); 2169 atppc_w_ecr(atppc, ecr_sav); 2170 atppc_barrier_w(atppc); 2171 } 2172 2173 static void 2174 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2175 unsigned char ctr) 2176 { 2177 unsigned int len; 2178 unsigned int worklen; 2179 2180 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2181 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2182 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2183 2184 /* Wait for device to become ready */ 2185 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2186 if(atppc->sc_outerr) 2187 return; 2188 2189 /* Reset chipset for next DMA transfer */ 2190 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2191 atppc_barrier_w(atppc); 2192 atppc_w_ecr(atppc, ecr); 2193 atppc_barrier_w(atppc); 2194 2195 /* Limit transfer to minimum of space in FIFO and buffer */ 2196 worklen = min(len, atppc->sc_fifo); 2197 2198 /* Limit transfer to maximum DMA size and start it */ 2199 worklen = min(worklen, atppc->sc_dma_maxsize); 2200 atppc->sc_dmastat = ATPPC_DMA_INIT; 2201 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2202 worklen, ATPPC_DMA_MODE_WRITE); 2203 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2204 2205 /* Enable interrupts, DMA */ 2206 ecr &= ~ATPPC_SERVICE_INTR; 2207 ecr |= ATPPC_ENABLE_DMA; 2208 atppc_w_ecr(atppc, ecr); 2209 atppc_barrier_w(atppc); 2210 2211 /* Wait for DMA completion */ 2212 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2213 ATPPC_IRQ_DMA); 2214 if(atppc->sc_outerr) { 2215 atppc_fifo_write_error(atppc, worklen); 2216 return; 2217 } 2218 /* Get register value recorded by interrupt handler */ 2219 ecr = atppc->sc_ecr_intr; 2220 /* Clear DMA programming */ 2221 atppc->sc_dma_finish(atppc); 2222 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2223 /* Disable DMA */ 2224 ecr &= ~ATPPC_ENABLE_DMA; 2225 atppc_w_ecr(atppc, ecr); 2226 atppc_barrier_w(atppc); 2227 2228 /* Wait for FIFO to empty */ 2229 for(;;) { 2230 if(ecr & ATPPC_FIFO_EMPTY) { 2231 if(ecr & ATPPC_FIFO_FULL) { 2232 atppc->sc_outerr = EIO; 2233 atppc_fifo_write_error(atppc, worklen); 2234 return; 2235 } 2236 else { 2237 break; 2238 } 2239 } 2240 2241 /* Enable service interrupt */ 2242 ecr &= ~ATPPC_SERVICE_INTR; 2243 atppc_w_ecr(atppc, ecr); 2244 atppc_barrier_w(atppc); 2245 2246 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2247 atppc->sc_outb, ATPPC_IRQ_FIFO); 2248 if(atppc->sc_outerr) { 2249 atppc_fifo_write_error(atppc, worklen); 2250 return; 2251 } 2252 2253 /* Get register value recorded by interrupt handler */ 2254 ecr = atppc->sc_ecr_intr; 2255 } 2256 2257 /* Update pointer */ 2258 atppc->sc_outbstart += worklen; 2259 } 2260 } 2261 2262 static void 2263 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2264 unsigned char ctr) 2265 { 2266 unsigned int len; 2267 unsigned int worklen; 2268 unsigned int timecount; 2269 2270 /* Disable DMA */ 2271 ecr &= ~ATPPC_ENABLE_DMA; 2272 atppc_w_ecr(atppc, ecr); 2273 atppc_barrier_w(atppc); 2274 2275 for(len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2276 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2277 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2278 2279 /* Wait for device to become ready */ 2280 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2281 if(atppc->sc_outerr) 2282 return; 2283 2284 /* Limit transfer to minimum of space in FIFO and buffer */ 2285 worklen = min(len, atppc->sc_fifo); 2286 2287 /* Write to FIFO */ 2288 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2289 2290 timecount = 0; 2291 if(atppc->sc_use & ATPPC_USE_INTR) { 2292 ecr = atppc_r_ecr(atppc); 2293 atppc_barrier_w(atppc); 2294 2295 /* Wait for interrupt */ 2296 for(;;) { 2297 if(ecr & ATPPC_FIFO_EMPTY) { 2298 if(ecr & ATPPC_FIFO_FULL) { 2299 atppc->sc_outerr = EIO; 2300 atppc_fifo_write_error(atppc, 2301 worklen); 2302 return; 2303 } 2304 else { 2305 break; 2306 } 2307 } 2308 2309 /* Enable service interrupt */ 2310 ecr &= ~ATPPC_SERVICE_INTR; 2311 atppc_w_ecr(atppc, ecr); 2312 atppc_barrier_w(atppc); 2313 2314 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2315 atppc->sc_outb, ATPPC_IRQ_FIFO); 2316 if(atppc->sc_outerr) { 2317 atppc_fifo_write_error(atppc, worklen); 2318 return; 2319 } 2320 2321 /* Get ECR value saved by interrupt handler */ 2322 ecr = atppc->sc_ecr_intr; 2323 } 2324 } 2325 else { 2326 for(; timecount < ((MAXBUSYWAIT/hz)*1000000); 2327 timecount++) { 2328 2329 ecr = atppc_r_ecr(atppc); 2330 atppc_barrier_r(atppc); 2331 if(ecr & ATPPC_FIFO_EMPTY) { 2332 if(ecr & ATPPC_FIFO_FULL) { 2333 atppc->sc_outerr = EIO; 2334 atppc_fifo_write_error(atppc, 2335 worklen); 2336 return; 2337 } 2338 else { 2339 break; 2340 } 2341 } 2342 DELAY(1); 2343 } 2344 2345 if(((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2346 atppc->sc_outerr = EIO; 2347 atppc_fifo_write_error(atppc, worklen); 2348 return; 2349 } 2350 } 2351 2352 /* Update pointer */ 2353 atppc->sc_outbstart += worklen; 2354 } 2355 } 2356 2357 static void 2358 atppc_fifo_write_error(struct atppc_softc * const atppc, 2359 const unsigned int worklen) 2360 { 2361 unsigned char ecr = atppc_r_ecr(atppc); 2362 2363 /* Abort DMA if not finished */ 2364 if(atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2365 atppc->sc_dma_abort(atppc); 2366 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2367 } 2368 2369 /* Check for invalid states */ 2370 if((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2371 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2372 } 2373 else if(!(ecr & ATPPC_FIFO_EMPTY)) { 2374 unsigned char ctr = atppc_r_ctr(atppc); 2375 int bytes_left; 2376 int i; 2377 2378 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2379 atppc->sc_dev.dv_xname)); 2380 2381 /* Drive strobe low to stop data transfer */ 2382 ctr &= ~STROBE; 2383 atppc_w_ctr(atppc, ctr); 2384 atppc_barrier_w(atppc); 2385 2386 /* Determine how many bytes remain in FIFO */ 2387 for(i = 0; i < atppc->sc_fifo; i++) { 2388 atppc_w_fifo(atppc, (unsigned char)i); 2389 ecr = atppc_r_ecr(atppc); 2390 atppc_barrier_r(atppc); 2391 if(ecr & ATPPC_FIFO_FULL) 2392 break; 2393 } 2394 bytes_left = (atppc->sc_fifo) - (i + 1); 2395 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2396 bytes_left)); 2397 2398 /* Update counter */ 2399 atppc->sc_outbstart += (worklen - bytes_left); 2400 } 2401 else { 2402 /* Update counter */ 2403 atppc->sc_outbstart += worklen; 2404 } 2405 2406 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2407 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2408 atppc_barrier_w(atppc); 2409 } 2410 2411 /* 2412 * Poll status register using mask and status for MAXBUSYWAIT. 2413 * Returns 0 if device ready, error value otherwise. 2414 */ 2415 static int 2416 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2417 const u_int8_t mask) 2418 { 2419 unsigned int timecount; 2420 u_int8_t str; 2421 int error = EIO; 2422 2423 /* Wait for str to have status for MAXBUSYWAIT */ 2424 for(timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2425 timecount++) { 2426 2427 str = atppc_r_str(atppc); 2428 atppc_barrier_r(atppc); 2429 if((str & mask) == status) { 2430 error = 0; 2431 break; 2432 } 2433 DELAY(1); 2434 } 2435 2436 return error; 2437 } 2438 2439 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2440 static int 2441 atppc_wait_interrupt(struct atppc_softc * const atppc, const caddr_t where, 2442 const u_int8_t irqstat) 2443 { 2444 int error = EIO; 2445 2446 atppc->sc_irqstat &= ~irqstat; 2447 2448 /* Wait for interrupt for MAXBUSYWAIT */ 2449 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2450 ATPPC_SC_LOCK(atppc)); 2451 2452 if(!(error) && (atppc->sc_irqstat & irqstat)) { 2453 atppc->sc_irqstat &= ~irqstat; 2454 error = 0; 2455 } 2456 2457 return error; 2458 } 2459
Indexes created Fri Sep 26 20:09:58 GMT 2025