atppc.c revision 1.9
1 /* $NetBSD: atppc.c,v 1.9 2004/01/28 14:26:24 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: atppc.c,v 1.9 2004/01/28 14:26:24 drochner Exp $"); 34 35 #include "opt_atppc.h" 36 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 #include <sys/systm.h> 44 #include <sys/vnode.h> 45 #include <sys/syslog.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/isa/isareg.h> 51 52 #include <dev/ic/atppcreg.h> 53 #include <dev/ic/atppcvar.h> 54 55 #include <dev/ppbus/ppbus_conf.h> 56 #include <dev/ppbus/ppbus_msq.h> 57 #include <dev/ppbus/ppbus_io.h> 58 #include <dev/ppbus/ppbus_var.h> 59 60 #ifdef ATPPC_DEBUG 61 int atppc_debug = 1; 62 #endif 63 64 #ifdef ATPPC_VERBOSE 65 int atppc_verbose = 1; 66 #endif 67 68 /* List of supported chipsets detection routines */ 69 static int (*chipset_detect[])(struct atppc_softc *) = { 70 /* XXX Add these LATER: maybe as seperate devices? 71 atppc_pc873xx_detect, 72 atppc_smc37c66xgt_detect, 73 atppc_w83877f_detect, 74 atppc_smc37c935_detect, 75 */ 76 NULL 77 }; 78 79 80 /* Prototypes for functions. */ 81 82 /* Soft configuration attach */ 83 void atppc_sc_attach(struct atppc_softc *); 84 int atppc_sc_detach(struct atppc_softc *, int); 85 86 /* Interrupt handler for atppc device */ 87 int atppcintr(void *); 88 89 /* Print function for config_found_sm() */ 90 static int atppc_print(void *, const char *); 91 92 /* Detection routines */ 93 static int atppc_detect_fifo(struct atppc_softc *); 94 static int atppc_detect_chipset(struct atppc_softc *); 95 static int atppc_detect_generic(struct atppc_softc *); 96 97 /* Routines for ppbus interface (bus + device) */ 98 static int atppc_read(struct device *, char *, int, int, size_t *); 99 static int atppc_write(struct device *, char *, int, int, size_t *); 100 static int atppc_setmode(struct device *, int); 101 static int atppc_getmode(struct device *); 102 static int atppc_check_epp_timeout(struct device *); 103 static void atppc_reset_epp_timeout(struct device *); 104 static void atppc_ecp_sync(struct device *); 105 static int atppc_exec_microseq(struct device *, struct ppbus_microseq * *); 106 static u_int8_t atppc_io(struct device *, int, u_char *, int, u_char); 107 static int atppc_read_ivar(struct device *, int, unsigned int *); 108 static int atppc_write_ivar(struct device *, int, unsigned int *); 109 static int atppc_add_handler(struct device *, void (*)(void *), void *); 110 static int atppc_remove_handler(struct device *, void (*)(void *)); 111 112 /* Utility functions */ 113 114 /* Functions to read bytes into device's input buffer */ 115 static void atppc_nibble_read(struct atppc_softc * const); 116 static void atppc_byte_read(struct atppc_softc * const); 117 static void atppc_epp_read(struct atppc_softc * const); 118 static void atppc_ecp_read(struct atppc_softc * const); 119 static void atppc_ecp_read_dma(struct atppc_softc *, unsigned int *, 120 unsigned char); 121 static void atppc_ecp_read_pio(struct atppc_softc *, unsigned int *, 122 unsigned char); 123 static void atppc_ecp_read_error(struct atppc_softc *, const unsigned int); 124 125 126 /* Functions to write bytes to device's output buffer */ 127 static void atppc_std_write(struct atppc_softc * const); 128 static void atppc_epp_write(struct atppc_softc * const); 129 static void atppc_fifo_write(struct atppc_softc * const); 130 static void atppc_fifo_write_dma(struct atppc_softc * const, unsigned char, 131 unsigned char); 132 static void atppc_fifo_write_pio(struct atppc_softc * const, unsigned char, 133 unsigned char); 134 static void atppc_fifo_write_error(struct atppc_softc * const, 135 const unsigned int); 136 137 /* Miscellaneous */ 138 static int atppc_poll_str(const struct atppc_softc * const, const u_int8_t, 139 const u_int8_t); 140 static int atppc_wait_interrupt(struct atppc_softc * const, const caddr_t, 141 const u_int8_t); 142 143 144 /* 145 * Generic attach and detach functions for atppc device. If sc_dev_ok in soft 146 * configuration data is not ATPPC_ATTACHED, these should be skipped altogether. 147 */ 148 149 /* Soft configuration attach for atppc */ 150 void 151 atppc_sc_attach(struct atppc_softc *lsc) 152 { 153 /* Adapter used to configure ppbus device */ 154 struct parport_adapter sc_parport_adapter; 155 char buf[64]; 156 157 /* Probe and set up chipset */ 158 if (atppc_detect_chipset(lsc) != 0) { 159 if (atppc_detect_generic(lsc) != 0) { 160 ATPPC_DPRINTF(("%s: Error detecting chipset\n", 161 lsc->sc_dev.dv_xname)); 162 } 163 } 164 165 /* Probe and setup FIFO queue */ 166 if (atppc_detect_fifo(lsc) == 0) { 167 printf("%s: FIFO <depth,wthr,rthr>=<%d,%d,%d>\n", 168 lsc->sc_dev.dv_xname, lsc->sc_fifo, lsc->sc_wthr, 169 lsc->sc_rthr); 170 } 171 172 /* Print out chipset capabilities */ 173 bitmask_snprintf(lsc->sc_has, "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 174 buf, sizeof(buf)); 175 printf("%s: capabilities=%s\n", lsc->sc_dev.dv_xname, buf); 176 177 /* Initialize device's buffer pointers */ 178 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 179 = NULL; 180 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 181 182 /* Last configuration step: set mode to standard mode */ 183 if (atppc_setmode(&(lsc->sc_dev), PPBUS_COMPATIBLE) != 0) { 184 ATPPC_DPRINTF(("%s: unable to initialize mode.\n", 185 lsc->sc_dev.dv_xname)); 186 } 187 188 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 189 /* Initialize lock structure */ 190 simple_lock_init(&(lsc->sc_lock)); 191 #endif 192 193 /* Set up parport_adapter structure */ 194 195 /* Set capabilites */ 196 sc_parport_adapter.capabilities = 0; 197 if (lsc->sc_has & ATPPC_HAS_INTR) { 198 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 199 } 200 if (lsc->sc_has & ATPPC_HAS_DMA) { 201 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 202 } 203 if (lsc->sc_has & ATPPC_HAS_FIFO) { 204 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 205 } 206 if (lsc->sc_has & ATPPC_HAS_PS2) { 207 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 208 } 209 if (lsc->sc_has & ATPPC_HAS_EPP) { 210 sc_parport_adapter.capabilities |= PPBUS_HAS_EPP; 211 } 212 if (lsc->sc_has & ATPPC_HAS_ECP) { 213 sc_parport_adapter.capabilities |= PPBUS_HAS_ECP; 214 } 215 216 /* Set function pointers */ 217 sc_parport_adapter.parport_io = atppc_io; 218 sc_parport_adapter.parport_exec_microseq = atppc_exec_microseq; 219 sc_parport_adapter.parport_reset_epp_timeout = 220 atppc_reset_epp_timeout; 221 sc_parport_adapter.parport_setmode = atppc_setmode; 222 sc_parport_adapter.parport_getmode = atppc_getmode; 223 sc_parport_adapter.parport_ecp_sync = atppc_ecp_sync; 224 sc_parport_adapter.parport_read = atppc_read; 225 sc_parport_adapter.parport_write = atppc_write; 226 sc_parport_adapter.parport_read_ivar = atppc_read_ivar; 227 sc_parport_adapter.parport_write_ivar = atppc_write_ivar; 228 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 229 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 230 sc_parport_adapter.parport_add_handler = atppc_add_handler; 231 sc_parport_adapter.parport_remove_handler = atppc_remove_handler; 232 233 /* Initialize handler list, may be added to by grandchildren */ 234 SLIST_INIT(&(lsc->sc_handler_listhead)); 235 236 /* Initialize interrupt state */ 237 lsc->sc_irqstat = ATPPC_IRQ_NONE; 238 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 239 240 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 241 lsc->sc_use = 0; 242 243 /* Configure child of the device. */ 244 lsc->child = config_found_sm(&(lsc->sc_dev), &(sc_parport_adapter), 245 atppc_print, NULL); 246 247 return; 248 } 249 250 /* Soft configuration detach */ 251 int atppc_sc_detach(struct atppc_softc *lsc, int flag) 252 { 253 struct device *dev = (struct device *)lsc; 254 255 /* Detach children devices */ 256 if (config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 257 printf("%s not able to detach child device, ", dev->dv_xname); 258 259 if (!(flag & DETACH_FORCE)) { 260 printf("cannot detach\n"); 261 return 1; 262 } else { 263 printf("continuing (DETACH_FORCE)\n"); 264 } 265 } 266 267 if (!(flag & DETACH_QUIET)) 268 printf("%s detached", dev->dv_xname); 269 270 return 0; 271 } 272 273 /* Used by config_found_sm() to print out device information */ 274 static int 275 atppc_print(void *aux, const char *name) 276 { 277 /* Print out something on failure. */ 278 if (name != NULL) { 279 printf("%s: child devices", name); 280 return UNCONF; 281 } 282 283 return QUIET; 284 } 285 286 /* 287 * Machine independent detection routines for atppc driver. 288 */ 289 290 /* Detect parallel port I/O port: taken from FreeBSD code directly. */ 291 int 292 atppc_detect_port(bus_space_tag_t iot, bus_space_handle_t ioh) 293 { 294 /* 295 * Much shorter than scheme used by lpt_isa_probe() and lpt_port_test() 296 * in original lpt driver. 297 * Write to data register common to all controllers and read back the 298 * values. Also tests control and status registers. 299 */ 300 301 /* 302 * Cannot use convenient macros because the device's config structure 303 * may not have been created yet: major change from FreeBSD code. 304 */ 305 306 int rval; 307 u_int8_t ctr_sav, dtr_sav, str_sav; 308 309 /* Store writtable registers' values and test if they can be read */ 310 str_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_STR); 311 ctr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_CTR); 312 dtr_sav = bus_space_read_1(iot, ioh, ATPPC_SPP_DTR); 313 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 314 BUS_SPACE_BARRIER_READ); 315 316 /* 317 * Ensure PS2 ports in output mode, also read back value of control 318 * register. 319 */ 320 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, 0x0c); 321 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 322 BUS_SPACE_BARRIER_WRITE); 323 324 if (bus_space_read_1(iot, ioh, ATPPC_SPP_CTR) != 0x0c) { 325 rval = 0; 326 } else { 327 /* 328 * Test if two values can be written and read from the data 329 * register. 330 */ 331 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 332 BUS_SPACE_BARRIER_READ); 333 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0xaa); 334 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 335 BUS_SPACE_BARRIER_WRITE); 336 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0xaa) { 337 rval = 1; 338 } else { 339 /* Second value to test */ 340 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 341 BUS_SPACE_BARRIER_READ); 342 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, 0x55); 343 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 344 BUS_SPACE_BARRIER_WRITE); 345 if (bus_space_read_1(iot, ioh, ATPPC_SPP_DTR) != 0x55) { 346 rval = 1; 347 } else { 348 rval = 0; 349 } 350 } 351 352 } 353 354 /* Restore registers */ 355 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 356 BUS_SPACE_BARRIER_READ); 357 bus_space_write_1(iot, ioh, ATPPC_SPP_CTR, ctr_sav); 358 bus_space_write_1(iot, ioh, ATPPC_SPP_DTR, dtr_sav); 359 bus_space_write_1(iot, ioh, ATPPC_SPP_STR, str_sav); 360 bus_space_barrier(iot, ioh, 0, IO_LPTSIZE, 361 BUS_SPACE_BARRIER_WRITE); 362 363 return rval; 364 } 365 366 /* Detect parallel port chipset. */ 367 static int 368 atppc_detect_chipset(struct atppc_softc *atppc) 369 { 370 /* Try each detection routine. */ 371 int i, mode; 372 for (i = 0; chipset_detect[i] != NULL; i++) { 373 if ((mode = chipset_detect[i](atppc)) != -1) { 374 atppc->sc_mode = mode; 375 return 0; 376 } 377 } 378 379 return 1; 380 } 381 382 /* Detect generic capabilities. */ 383 static int 384 atppc_detect_generic(struct atppc_softc *atppc) 385 { 386 u_int8_t ecr_sav = atppc_r_ecr(atppc); 387 u_int8_t ctr_sav = atppc_r_ctr(atppc); 388 u_int8_t str_sav = atppc_r_str(atppc); 389 u_int8_t tmp; 390 atppc_barrier_r(atppc); 391 392 /* Default to generic */ 393 atppc->sc_type = ATPPC_TYPE_GENERIC; 394 atppc->sc_model = GENERIC; 395 396 /* Check for ECP */ 397 tmp = atppc_r_ecr(atppc); 398 atppc_barrier_r(atppc); 399 if ((tmp & ATPPC_FIFO_EMPTY) && !(tmp & ATPPC_FIFO_FULL)) { 400 atppc_w_ecr(atppc, 0x34); 401 atppc_barrier_w(atppc); 402 tmp = atppc_r_ecr(atppc); 403 atppc_barrier_r(atppc); 404 if (tmp == 0x35) { 405 atppc->sc_has |= ATPPC_HAS_ECP; 406 } 407 } 408 409 /* Allow search for SMC style ECP+EPP mode */ 410 if (atppc->sc_has & ATPPC_HAS_ECP) { 411 atppc_w_ecr(atppc, ATPPC_ECR_EPP); 412 atppc_barrier_w(atppc); 413 } 414 /* Check for EPP by checking for timeout bit */ 415 if (atppc_check_epp_timeout(&(atppc->sc_dev)) != 0) { 416 atppc->sc_has |= ATPPC_HAS_EPP; 417 atppc->sc_epp = ATPPC_EPP_1_9; 418 if (atppc->sc_has & ATPPC_HAS_ECP) { 419 /* SMC like chipset found */ 420 atppc->sc_model = SMC_LIKE; 421 atppc->sc_type = ATPPC_TYPE_SMCLIKE; 422 } 423 } 424 425 /* Detect PS2 mode */ 426 if (atppc->sc_has & ATPPC_HAS_ECP) { 427 /* Put ECP port into PS2 mode */ 428 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 429 atppc_barrier_w(atppc); 430 } 431 /* Put PS2 port in input mode: writes should not be readable */ 432 atppc_w_ctr(atppc, 0x20); 433 atppc_barrier_w(atppc); 434 /* 435 * Write two values to data port: if neither are read back, 436 * bidirectional mode is functional. 437 */ 438 atppc_w_dtr(atppc, 0xaa); 439 atppc_barrier_w(atppc); 440 tmp = atppc_r_dtr(atppc); 441 atppc_barrier_r(atppc); 442 if (tmp != 0xaa) { 443 atppc_w_dtr(atppc, 0x55); 444 atppc_barrier_w(atppc); 445 tmp = atppc_r_dtr(atppc); 446 atppc_barrier_r(atppc); 447 if (tmp != 0x55) { 448 atppc->sc_has |= ATPPC_HAS_PS2; 449 } 450 } 451 452 /* Restore to previous state */ 453 atppc_w_ecr(atppc, ecr_sav); 454 atppc_w_ctr(atppc, ctr_sav); 455 atppc_w_str(atppc, str_sav); 456 atppc_barrier_w(atppc); 457 458 return 0; 459 } 460 461 /* 462 * Detect parallel port FIFO: taken from FreeBSD code directly. 463 */ 464 static int 465 atppc_detect_fifo(struct atppc_softc *atppc) 466 { 467 #ifdef ATPPC_DEBUG 468 struct device *dev = (struct device *)atppc; 469 #endif 470 u_int8_t ecr_sav; 471 u_int8_t ctr_sav; 472 u_int8_t str_sav; 473 u_int8_t cc; 474 short i; 475 476 /* If there is no ECP mode, we cannot config a FIFO */ 477 if (!(atppc->sc_has & ATPPC_HAS_ECP)) { 478 return (EINVAL); 479 } 480 481 /* save registers */ 482 ecr_sav = atppc_r_ecr(atppc); 483 ctr_sav = atppc_r_ctr(atppc); 484 str_sav = atppc_r_str(atppc); 485 atppc_barrier_r(atppc); 486 487 /* Enter ECP configuration mode, no interrupt, no DMA */ 488 atppc_w_ecr(atppc, (ATPPC_ECR_CFG | ATPPC_SERVICE_INTR) & 489 ~ATPPC_ENABLE_DMA); 490 atppc_barrier_w(atppc); 491 492 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 493 atppc->sc_pword = (atppc_r_cnfgA(atppc) & ATPPC_PWORD_MASK); 494 atppc_barrier_r(atppc); 495 496 /* XXX 16 and 32 bits implementations not supported */ 497 if (atppc->sc_pword != ATPPC_PWORD_8) { 498 ATPPC_DPRINTF(("%s(%s): FIFO PWord(%d) not supported.\n", 499 __func__, dev->dv_xname, atppc->sc_pword)); 500 goto error; 501 } 502 503 /* Byte mode, reverse direction, no interrupt, no DMA */ 504 atppc_w_ecr(atppc, ATPPC_ECR_PS2 | ATPPC_SERVICE_INTR); 505 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) | PCD); 506 /* enter ECP test mode, no interrupt, no DMA */ 507 atppc_w_ecr(atppc, ATPPC_ECR_TST | ATPPC_SERVICE_INTR); 508 atppc_barrier_w(atppc); 509 510 /* flush the FIFO */ 511 for (i = 0; i < 1024; i++) { 512 atppc_r_fifo(atppc); 513 atppc_barrier_r(atppc); 514 cc = atppc_r_ecr(atppc); 515 atppc_barrier_r(atppc); 516 if (cc & ATPPC_FIFO_EMPTY) 517 break; 518 } 519 if (i >= 1024) { 520 ATPPC_DPRINTF(("%s(%s): cannot flush FIFO.\n", __func__, 521 dev->dv_xname)); 522 goto error; 523 } 524 525 /* Test mode, enable interrupts, no DMA */ 526 atppc_w_ecr(atppc, ATPPC_ECR_TST); 527 atppc_barrier_w(atppc); 528 529 /* Determine readIntrThreshold - fill FIFO until serviceIntr is set */ 530 for (i = atppc->sc_rthr = atppc->sc_fifo = 0; i < 1024; i++) { 531 atppc_w_fifo(atppc, (char)i); 532 atppc_barrier_w(atppc); 533 cc = atppc_r_ecr(atppc); 534 atppc_barrier_r(atppc); 535 if ((atppc->sc_rthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 536 /* readThreshold reached */ 537 atppc->sc_rthr = i + 1; 538 } 539 if (cc & ATPPC_FIFO_FULL) { 540 atppc->sc_fifo = i + 1; 541 break; 542 } 543 } 544 if (i >= 1024) { 545 ATPPC_DPRINTF(("%s(%s): cannot fill FIFO.\n", __func__, 546 dev->dv_xname)); 547 goto error; 548 } 549 550 /* Change direction */ 551 atppc_w_ctr(atppc, (ctr_sav & ~IRQENABLE) & ~PCD); 552 atppc_barrier_w(atppc); 553 554 /* Clear the serviceIntr bit we've already set in the above loop */ 555 atppc_w_ecr(atppc, ATPPC_ECR_TST); 556 atppc_barrier_w(atppc); 557 558 /* Determine writeIntrThreshold - empty FIFO until serviceIntr is set */ 559 for (atppc->sc_wthr = 0; i > -1; i--) { 560 cc = atppc_r_fifo(atppc); 561 atppc_barrier_r(atppc); 562 if (cc != (char)(atppc->sc_fifo - i - 1)) { 563 ATPPC_DPRINTF(("%s(%s): invalid data in FIFO.\n", 564 __func__, dev->dv_xname)); 565 goto error; 566 } 567 568 cc = atppc_r_ecr(atppc); 569 atppc_barrier_r(atppc); 570 if ((atppc->sc_wthr == 0) && (cc & ATPPC_SERVICE_INTR)) { 571 /* writeIntrThreshold reached */ 572 atppc->sc_wthr = atppc->sc_fifo - i; 573 } 574 575 if (i > 0 && (cc & ATPPC_FIFO_EMPTY)) { 576 /* If FIFO empty before the last byte, error */ 577 ATPPC_DPRINTF(("%s(%s): data lost in FIFO.\n", __func__, 578 dev->dv_xname)); 579 goto error; 580 } 581 } 582 583 /* FIFO must be empty after the last byte */ 584 cc = atppc_r_ecr(atppc); 585 atppc_barrier_r(atppc); 586 if (!(cc & ATPPC_FIFO_EMPTY)) { 587 ATPPC_DPRINTF(("%s(%s): cannot empty the FIFO.\n", __func__, 588 dev->dv_xname)); 589 goto error; 590 } 591 592 /* Restore original registers */ 593 atppc_w_ctr(atppc, ctr_sav); 594 atppc_w_str(atppc, str_sav); 595 atppc_w_ecr(atppc, ecr_sav); 596 atppc_barrier_w(atppc); 597 598 /* Update capabilities */ 599 atppc->sc_has |= ATPPC_HAS_FIFO; 600 601 return 0; 602 603 error: 604 /* Restore original registers */ 605 atppc_w_ctr(atppc, ctr_sav); 606 atppc_w_str(atppc, str_sav); 607 atppc_w_ecr(atppc, ecr_sav); 608 atppc_barrier_w(atppc); 609 610 return (EINVAL); 611 } 612 613 /* Interrupt handler for atppc device: wakes up read/write functions */ 614 int 615 atppcintr(void *arg) 616 { 617 struct atppc_softc *atppc = (struct atppc_softc *)arg; 618 struct device *dev = &atppc->sc_dev; 619 int error = 1; 620 enum { NONE, READER, WRITER } wake_up = NONE; 621 int s; 622 623 s = splatppc(); 624 ATPPC_LOCK(atppc); 625 626 /* Record registers' status */ 627 atppc->sc_str_intr = atppc_r_str(atppc); 628 atppc->sc_ctr_intr = atppc_r_ctr(atppc); 629 atppc->sc_ecr_intr = atppc_r_ecr(atppc); 630 atppc_barrier_r(atppc); 631 632 /* Determine cause of interrupt and wake up top half */ 633 switch (atppc->sc_mode) { 634 case ATPPC_MODE_STD: 635 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 636 atppc->sc_irqstat = ATPPC_IRQ_nACK; 637 if (atppc->sc_outb) 638 wake_up = WRITER; 639 else 640 error = -1; 641 break; 642 643 case ATPPC_MODE_NIBBLE: 644 case ATPPC_MODE_PS2: 645 /* nAck is set low by device and then high on ack */ 646 if (!(atppc->sc_str_intr & nACK)) { 647 error = 0; 648 break; 649 } 650 atppc->sc_irqstat = ATPPC_IRQ_nACK; 651 if (atppc->sc_inb) 652 wake_up = READER; 653 else 654 error = -1; 655 break; 656 657 case ATPPC_MODE_ECP: 658 case ATPPC_MODE_FAST: 659 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 660 if (atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 661 if (atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 662 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 663 else 664 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 665 666 /* Decide where top half will be waiting */ 667 if (atppc->sc_mode & ATPPC_MODE_ECP) { 668 if (atppc->sc_ctr_intr & PCD) { 669 if (atppc->sc_inb) 670 wake_up = READER; 671 else 672 error = -1; 673 } else { 674 if (atppc->sc_outb) 675 wake_up = WRITER; 676 else 677 error = -1; 678 } 679 } else { 680 if (atppc->sc_outb) 681 wake_up = WRITER; 682 else 683 error = -1; 684 } 685 } 686 /* Determine if nFault has occured */ 687 if ((atppc->sc_mode & ATPPC_MODE_ECP) && 688 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 689 !(atppc->sc_str_intr & nFAULT)) { 690 691 /* Device is requesting the channel */ 692 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 693 } 694 break; 695 696 case ATPPC_MODE_EPP: 697 /* nAck pulsed for 5 usec, too fast to check reliably */ 698 atppc->sc_irqstat = ATPPC_IRQ_nACK; 699 if (atppc->sc_inb) 700 wake_up = WRITER; 701 else if (atppc->sc_outb) 702 wake_up = READER; 703 else 704 error = -1; 705 break; 706 707 default: 708 panic("%s: chipset is in invalid mode.", dev->dv_xname); 709 } 710 711 switch (wake_up) { 712 case NONE: 713 break; 714 715 case READER: 716 wakeup(atppc->sc_inb); 717 break; 718 719 case WRITER: 720 wakeup(atppc->sc_outb); 721 break; 722 723 default: 724 panic("%s: this code should not be reached.\n", __func__); 725 break; 726 } 727 728 ATPPC_UNLOCK(atppc); 729 730 /* Call all of the installed handlers */ 731 { 732 struct atppc_handler_node * callback; 733 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 734 entries) { 735 (*callback->func)(callback->arg); 736 } 737 } 738 739 splx(s); 740 741 return error; 742 } 743 744 745 /* Functions which support ppbus interface */ 746 747 748 /* Check EPP mode timeout */ 749 static int 750 atppc_check_epp_timeout(struct device *dev) 751 { 752 struct atppc_softc *atppc = (struct atppc_softc *)dev; 753 int s; 754 int error; 755 756 s = splatppc(); 757 ATPPC_LOCK(atppc); 758 759 atppc_reset_epp_timeout(dev); 760 error = !(atppc_r_str(atppc) & TIMEOUT); 761 atppc_barrier_r(atppc); 762 763 ATPPC_UNLOCK(atppc); 764 splx(s); 765 766 return (error); 767 } 768 769 /* 770 * EPP timeout, according to the PC87332 manual 771 * Semantics of clearing EPP timeout bit. 772 * PC87332 - reading SPP_STR does it... 773 * SMC - write 1 to EPP timeout bit XXX 774 * Others - (?) write 0 to EPP timeout bit 775 */ 776 static void 777 atppc_reset_epp_timeout(struct device *dev) 778 { 779 struct atppc_softc *atppc = (struct atppc_softc *)dev; 780 register unsigned char r; 781 782 r = atppc_r_str(atppc); 783 atppc_barrier_r(atppc); 784 atppc_w_str(atppc, r | 0x1); 785 atppc_barrier_w(atppc); 786 atppc_w_str(atppc, r & 0xfe); 787 atppc_barrier_w(atppc); 788 789 return; 790 } 791 792 793 /* Read from atppc device: returns 0 on success. */ 794 static int 795 atppc_read(struct device *dev, char *buf, int len, int ioflag, 796 size_t *cnt) 797 { 798 struct atppc_softc *atppc = (struct atppc_softc *)dev; 799 int error = 0; 800 int s; 801 802 s = splatppc(); 803 ATPPC_LOCK(atppc); 804 805 *cnt = 0; 806 807 /* Initialize buffer */ 808 atppc->sc_inb = atppc->sc_inbstart = buf; 809 atppc->sc_inb_nbytes = len; 810 811 /* Initialize device input error state for new operation */ 812 atppc->sc_inerr = 0; 813 814 /* Call appropriate function to read bytes */ 815 switch(atppc->sc_mode) { 816 case ATPPC_MODE_STD: 817 case ATPPC_MODE_FAST: 818 error = ENODEV; 819 break; 820 821 case ATPPC_MODE_NIBBLE: 822 atppc_nibble_read(atppc); 823 break; 824 825 case ATPPC_MODE_PS2: 826 atppc_byte_read(atppc); 827 break; 828 829 case ATPPC_MODE_ECP: 830 atppc_ecp_read(atppc); 831 break; 832 833 case ATPPC_MODE_EPP: 834 atppc_epp_read(atppc); 835 break; 836 837 default: 838 panic("%s(%s): chipset in invalid mode.\n", __func__, 839 dev->dv_xname); 840 } 841 842 /* Update counter*/ 843 *cnt = (atppc->sc_inbstart - atppc->sc_inb); 844 845 /* Reset buffer */ 846 atppc->sc_inb = atppc->sc_inbstart = NULL; 847 atppc->sc_inb_nbytes = 0; 848 849 if (!(error)) 850 error = atppc->sc_inerr; 851 852 ATPPC_UNLOCK(atppc); 853 splx(s); 854 855 return (error); 856 } 857 858 /* Write to atppc device: returns 0 on success. */ 859 static int 860 atppc_write(struct device *dev, char *buf, int len, int ioflag, size_t *cnt) 861 { 862 struct atppc_softc * const atppc = (struct atppc_softc *)dev; 863 int error = 0; 864 int s; 865 866 *cnt = 0; 867 868 s = splatppc(); 869 ATPPC_LOCK(atppc); 870 871 /* Set up line buffer */ 872 atppc->sc_outb = atppc->sc_outbstart = buf; 873 atppc->sc_outb_nbytes = len; 874 875 /* Initialize device output error state for new operation */ 876 atppc->sc_outerr = 0; 877 878 /* Call appropriate function to write bytes */ 879 switch (atppc->sc_mode) { 880 case ATPPC_MODE_STD: 881 atppc_std_write(atppc); 882 break; 883 884 case ATPPC_MODE_NIBBLE: 885 case ATPPC_MODE_PS2: 886 error = ENODEV; 887 break; 888 889 case ATPPC_MODE_FAST: 890 case ATPPC_MODE_ECP: 891 atppc_fifo_write(atppc); 892 break; 893 894 case ATPPC_MODE_EPP: 895 atppc_epp_write(atppc); 896 break; 897 898 default: 899 panic("%s(%s): chipset in invalid mode.\n", __func__, 900 dev->dv_xname); 901 } 902 903 /* Update counter*/ 904 *cnt = (atppc->sc_outbstart - atppc->sc_outb); 905 906 /* Reset output buffer */ 907 atppc->sc_outb = atppc->sc_outbstart = NULL; 908 atppc->sc_outb_nbytes = 0; 909 910 if (!(error)) 911 error = atppc->sc_outerr; 912 913 ATPPC_UNLOCK(atppc); 914 splx(s); 915 916 return (error); 917 } 918 919 /* 920 * Set mode of chipset to mode argument. Modes not supported are ignored. If 921 * multiple modes are flagged, the mode is not changed. Mode's are those 922 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 923 * can change their mode of operation. However, ALL operation modes support 924 * centronics mode and nibble mode. Modes determine both hardware AND software 925 * behaviour. 926 * NOTE: the mode for ECP should only be changed when the channel is in 927 * forward idle mode. This function does not make sure FIFO's have flushed or 928 * any consistency checks. 929 */ 930 static int 931 atppc_setmode(struct device *dev, int mode) 932 { 933 struct atppc_softc *atppc = (struct atppc_softc *)dev; 934 u_int8_t ecr; 935 u_int8_t chipset_mode; 936 int s; 937 int rval = 0; 938 939 s = splatppc(); 940 ATPPC_LOCK(atppc); 941 942 /* If ECP capable, configure ecr register */ 943 if (atppc->sc_has & ATPPC_HAS_ECP) { 944 /* Read ECR with mode masked out */ 945 ecr = (atppc_r_ecr(atppc) & (unsigned)0x1f); 946 atppc_barrier_r(atppc); 947 948 switch (mode) { 949 case PPBUS_ECP: 950 /* Set ECP mode */ 951 ecr |= ATPPC_ECR_ECP; 952 chipset_mode = ATPPC_MODE_ECP; 953 break; 954 955 case PPBUS_EPP: 956 /* Set EPP mode */ 957 if (atppc->sc_has & ATPPC_HAS_EPP) { 958 ecr |= ATPPC_ECR_EPP; 959 chipset_mode = ATPPC_MODE_EPP; 960 } else { 961 rval = ENODEV; 962 goto end; 963 } 964 break; 965 966 case PPBUS_FAST: 967 /* Set fast centronics mode */ 968 ecr |= ATPPC_ECR_FIFO; 969 chipset_mode = ATPPC_MODE_FAST; 970 break; 971 972 case PPBUS_PS2: 973 /* Set PS2 mode */ 974 ecr |= ATPPC_ECR_PS2; 975 chipset_mode = ATPPC_MODE_PS2; 976 break; 977 978 case PPBUS_COMPATIBLE: 979 /* Set standard mode */ 980 ecr |= ATPPC_ECR_STD; 981 chipset_mode = ATPPC_MODE_STD;; 982 break; 983 984 case PPBUS_NIBBLE: 985 /* Set nibble mode: uses chipset standard mode */ 986 ecr |= ATPPC_ECR_STD; 987 chipset_mode = ATPPC_MODE_NIBBLE; 988 break; 989 990 default: 991 /* Invalid mode specified for ECP chip */ 992 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 993 "argument.\n", __func__, dev->dv_xname)); 994 rval = ENODEV; 995 goto end; 996 } 997 998 /* Switch to byte mode to be able to change modes. */ 999 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 1000 atppc_barrier_w(atppc); 1001 1002 /* Update mode */ 1003 atppc_w_ecr(atppc, ecr); 1004 atppc_barrier_w(atppc); 1005 } else { 1006 switch (mode) { 1007 case PPBUS_EPP: 1008 if (atppc->sc_has & ATPPC_HAS_EPP) { 1009 chipset_mode = ATPPC_MODE_EPP; 1010 } else { 1011 rval = ENODEV; 1012 goto end; 1013 } 1014 break; 1015 1016 case PPBUS_PS2: 1017 if (atppc->sc_has & ATPPC_HAS_PS2) { 1018 chipset_mode = ATPPC_MODE_PS2; 1019 } else { 1020 rval = ENODEV; 1021 goto end; 1022 } 1023 break; 1024 1025 case PPBUS_NIBBLE: 1026 /* Set nibble mode (virtual) */ 1027 chipset_mode = ATPPC_MODE_NIBBLE; 1028 break; 1029 1030 case PPBUS_COMPATIBLE: 1031 chipset_mode = ATPPC_MODE_STD; 1032 break; 1033 1034 case PPBUS_ECP: 1035 rval = ENODEV; 1036 goto end; 1037 1038 default: 1039 ATPPC_DPRINTF(("%s(%s): invalid mode passed as " 1040 "argument.\n", __func__, dev->dv_xname)); 1041 rval = ENODEV; 1042 goto end; 1043 } 1044 } 1045 1046 atppc->sc_mode = chipset_mode; 1047 if (chipset_mode == ATPPC_MODE_PS2) { 1048 /* Set direction bit to reverse */ 1049 ecr = atppc_r_ctr(atppc); 1050 atppc_barrier_r(atppc); 1051 ecr |= PCD; 1052 atppc_w_ctr(atppc, ecr); 1053 atppc_barrier_w(atppc); 1054 } 1055 1056 end: 1057 ATPPC_UNLOCK(atppc); 1058 splx(s); 1059 1060 return rval; 1061 } 1062 1063 /* Get the current mode of chipset */ 1064 static int 1065 atppc_getmode(struct device *dev) 1066 { 1067 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1068 int mode; 1069 int s; 1070 1071 s = splatppc(); 1072 ATPPC_LOCK(atppc); 1073 1074 /* The chipset can only be in one mode at a time logically */ 1075 switch (atppc->sc_mode) { 1076 case ATPPC_MODE_ECP: 1077 mode = PPBUS_ECP; 1078 break; 1079 1080 case ATPPC_MODE_EPP: 1081 mode = PPBUS_EPP; 1082 break; 1083 1084 case ATPPC_MODE_PS2: 1085 mode = PPBUS_PS2; 1086 break; 1087 1088 case ATPPC_MODE_STD: 1089 mode = PPBUS_COMPATIBLE; 1090 break; 1091 1092 case ATPPC_MODE_NIBBLE: 1093 mode = PPBUS_NIBBLE; 1094 break; 1095 1096 case ATPPC_MODE_FAST: 1097 mode = PPBUS_FAST; 1098 break; 1099 1100 default: 1101 panic("%s(%s): device is in invalid mode!", __func__, 1102 dev->dv_xname); 1103 break; 1104 } 1105 1106 ATPPC_UNLOCK(atppc); 1107 splx(s); 1108 1109 return mode; 1110 } 1111 1112 1113 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 1114 static void 1115 atppc_ecp_sync(struct device *dev) 1116 { 1117 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1118 int i; 1119 int s; 1120 u_int8_t r; 1121 1122 s = splatppc(); 1123 ATPPC_LOCK(atppc); 1124 1125 /* 1126 * Only wait for FIFO to empty if mode is chipset is ECP-capable AND 1127 * the mode is either ECP or Fast Centronics. 1128 */ 1129 r = atppc_r_ecr(atppc); 1130 atppc_barrier_r(atppc); 1131 r &= 0xe0; 1132 if (!(atppc->sc_has & ATPPC_HAS_ECP) || ((r != ATPPC_ECR_ECP) 1133 && (r != ATPPC_ECR_FIFO))) { 1134 goto end; 1135 } 1136 1137 /* Wait for FIFO to empty */ 1138 for (i = 0; i < ((MAXBUSYWAIT/hz) * 1000000); i += 100) { 1139 r = atppc_r_ecr(atppc); 1140 atppc_barrier_r(atppc); 1141 if (r & ATPPC_FIFO_EMPTY) { 1142 goto end; 1143 } 1144 delay(100); /* Supposed to be a 100 usec delay */ 1145 } 1146 1147 ATPPC_DPRINTF(("%s: ECP sync failed, data still in FIFO.\n", 1148 dev->dv_xname)); 1149 1150 end: 1151 ATPPC_UNLOCK(atppc); 1152 splx(s); 1153 1154 return; 1155 } 1156 1157 /* Execute a microsequence to handle fast I/O operations. */ 1158 static int 1159 atppc_exec_microseq(struct device *dev, struct ppbus_microseq **p_msq) 1160 { 1161 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1162 struct ppbus_microseq *mi = *p_msq; 1163 char cc, *p; 1164 int i, iter, len; 1165 int error; 1166 int s; 1167 register int reg; 1168 register unsigned char mask; 1169 register int accum = 0; 1170 register char *ptr = NULL; 1171 struct ppbus_microseq *stack = NULL; 1172 1173 s = splatppc(); 1174 ATPPC_LOCK(atppc); 1175 1176 /* microsequence registers are equivalent to PC-like port registers */ 1177 1178 #define r_reg(register,atppc) bus_space_read_1((atppc)->sc_iot, \ 1179 (atppc)->sc_ioh, (register)) 1180 #define w_reg(register, atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 1181 (atppc)->sc_ioh, (register), (byte)) 1182 1183 /* Loop until microsequence execution finishes (ending op code) */ 1184 for (;;) { 1185 switch (mi->opcode) { 1186 case MS_OP_RSET: 1187 cc = r_reg(mi->arg[0].i, atppc); 1188 atppc_barrier_r(atppc); 1189 cc &= (char)mi->arg[2].i; /* clear mask */ 1190 cc |= (char)mi->arg[1].i; /* assert mask */ 1191 w_reg(mi->arg[0].i, atppc, cc); 1192 atppc_barrier_w(atppc); 1193 mi++; 1194 break; 1195 1196 case MS_OP_RASSERT_P: 1197 reg = mi->arg[1].i; 1198 ptr = atppc->sc_ptr; 1199 1200 if ((len = mi->arg[0].i) == MS_ACCUM) { 1201 accum = atppc->sc_accum; 1202 for (; accum; accum--) { 1203 w_reg(reg, atppc, *ptr++); 1204 atppc_barrier_w(atppc); 1205 } 1206 atppc->sc_accum = accum; 1207 } else { 1208 for (i = 0; i < len; i++) { 1209 w_reg(reg, atppc, *ptr++); 1210 atppc_barrier_w(atppc); 1211 } 1212 } 1213 1214 atppc->sc_ptr = ptr; 1215 mi++; 1216 break; 1217 1218 case MS_OP_RFETCH_P: 1219 reg = mi->arg[1].i; 1220 mask = (char)mi->arg[2].i; 1221 ptr = atppc->sc_ptr; 1222 1223 if ((len = mi->arg[0].i) == MS_ACCUM) { 1224 accum = atppc->sc_accum; 1225 for (; accum; accum--) { 1226 *ptr++ = r_reg(reg, atppc) & mask; 1227 atppc_barrier_r(atppc); 1228 } 1229 atppc->sc_accum = accum; 1230 } else { 1231 for (i = 0; i < len; i++) { 1232 *ptr++ = r_reg(reg, atppc) & mask; 1233 atppc_barrier_r(atppc); 1234 } 1235 } 1236 1237 atppc->sc_ptr = ptr; 1238 mi++; 1239 break; 1240 1241 case MS_OP_RFETCH: 1242 *((char *)mi->arg[2].p) = r_reg(mi->arg[0].i, atppc) & 1243 (char)mi->arg[1].i; 1244 atppc_barrier_r(atppc); 1245 mi++; 1246 break; 1247 1248 case MS_OP_RASSERT: 1249 case MS_OP_DELAY: 1250 /* let's suppose the next instr. is the same */ 1251 do { 1252 for (;mi->opcode == MS_OP_RASSERT; mi++) { 1253 w_reg(mi->arg[0].i, atppc, 1254 (char)mi->arg[1].i); 1255 atppc_barrier_w(atppc); 1256 } 1257 1258 for (;mi->opcode == MS_OP_DELAY; mi++) { 1259 delay(mi->arg[0].i); 1260 } 1261 } while (mi->opcode == MS_OP_RASSERT); 1262 break; 1263 1264 case MS_OP_ADELAY: 1265 if (mi->arg[0].i) { 1266 tsleep(atppc, PPBUSPRI, "atppcdelay", 1267 mi->arg[0].i * (hz/1000)); 1268 } 1269 mi++; 1270 break; 1271 1272 case MS_OP_TRIG: 1273 reg = mi->arg[0].i; 1274 iter = mi->arg[1].i; 1275 p = (char *)mi->arg[2].p; 1276 1277 /* XXX delay limited to 255 us */ 1278 for (i = 0; i < iter; i++) { 1279 w_reg(reg, atppc, *p++); 1280 atppc_barrier_w(atppc); 1281 delay((unsigned char)*p++); 1282 } 1283 1284 mi++; 1285 break; 1286 1287 case MS_OP_SET: 1288 atppc->sc_accum = mi->arg[0].i; 1289 mi++; 1290 break; 1291 1292 case MS_OP_DBRA: 1293 if (--atppc->sc_accum > 0) { 1294 mi += mi->arg[0].i; 1295 } 1296 1297 mi++; 1298 break; 1299 1300 case MS_OP_BRSET: 1301 cc = atppc_r_str(atppc); 1302 atppc_barrier_r(atppc); 1303 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 1304 mi += mi->arg[1].i; 1305 } 1306 mi++; 1307 break; 1308 1309 case MS_OP_BRCLEAR: 1310 cc = atppc_r_str(atppc); 1311 atppc_barrier_r(atppc); 1312 if ((cc & (char)mi->arg[0].i) == 0) { 1313 mi += mi->arg[1].i; 1314 } 1315 mi++; 1316 break; 1317 1318 case MS_OP_BRSTAT: 1319 cc = atppc_r_str(atppc); 1320 atppc_barrier_r(atppc); 1321 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1322 (char)mi->arg[0].i) { 1323 mi += mi->arg[2].i; 1324 } 1325 mi++; 1326 break; 1327 1328 case MS_OP_C_CALL: 1329 /* 1330 * If the C call returns !0 then end the microseq. 1331 * The current state of ptr is passed to the C function 1332 */ 1333 if ((error = mi->arg[0].f(mi->arg[1].p, 1334 atppc->sc_ptr))) { 1335 ATPPC_UNLOCK(atppc); 1336 splx(s); 1337 return (error); 1338 } 1339 mi++; 1340 break; 1341 1342 case MS_OP_PTR: 1343 atppc->sc_ptr = (char *)mi->arg[0].p; 1344 mi++; 1345 break; 1346 1347 case MS_OP_CALL: 1348 if (stack) { 1349 panic("%s - %s: too much calls", dev->dv_xname, 1350 __func__); 1351 } 1352 1353 if (mi->arg[0].p) { 1354 /* store state of the actual microsequence */ 1355 stack = mi; 1356 1357 /* jump to the new microsequence */ 1358 mi = (struct ppbus_microseq *)mi->arg[0].p; 1359 } else { 1360 mi++; 1361 } 1362 break; 1363 1364 case MS_OP_SUBRET: 1365 /* retrieve microseq and pc state before the call */ 1366 mi = stack; 1367 1368 /* reset the stack */ 1369 stack = 0; 1370 1371 /* XXX return code */ 1372 1373 mi++; 1374 break; 1375 1376 case MS_OP_PUT: 1377 case MS_OP_GET: 1378 case MS_OP_RET: 1379 /* 1380 * Can't return to atppc level during the execution 1381 * of a submicrosequence. 1382 */ 1383 if (stack) { 1384 panic("%s: cannot return to atppc level", 1385 __func__); 1386 } 1387 /* update pc for atppc level of execution */ 1388 *p_msq = mi; 1389 1390 ATPPC_UNLOCK(atppc); 1391 splx(s); 1392 return (0); 1393 break; 1394 1395 default: 1396 panic("%s: unknown microsequence " 1397 "opcode 0x%x", __func__, mi->opcode); 1398 break; 1399 } 1400 } 1401 1402 /* Should not be reached! */ 1403 #ifdef ATPPC_DEBUG 1404 panic("%s: unexpected code reached!\n", __func__); 1405 #endif 1406 } 1407 1408 /* General I/O routine */ 1409 static u_int8_t 1410 atppc_io(struct device *dev, int iop, u_char *addr, int cnt, u_char byte) 1411 { 1412 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1413 u_int8_t val = 0; 1414 int s; 1415 1416 s = splatppc(); 1417 ATPPC_LOCK(atppc); 1418 1419 switch (iop) { 1420 case PPBUS_OUTSB_EPP: 1421 bus_space_write_multi_1(atppc->sc_iot, atppc->sc_ioh, 1422 ATPPC_EPP_DATA, addr, cnt); 1423 break; 1424 case PPBUS_OUTSW_EPP: 1425 bus_space_write_multi_2(atppc->sc_iot, atppc->sc_ioh, 1426 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1427 break; 1428 case PPBUS_OUTSL_EPP: 1429 bus_space_write_multi_4(atppc->sc_iot, atppc->sc_ioh, 1430 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1431 break; 1432 case PPBUS_INSB_EPP: 1433 bus_space_read_multi_1(atppc->sc_iot, atppc->sc_ioh, 1434 ATPPC_EPP_DATA, addr, cnt); 1435 break; 1436 case PPBUS_INSW_EPP: 1437 bus_space_read_multi_2(atppc->sc_iot, atppc->sc_ioh, 1438 ATPPC_EPP_DATA, (u_int16_t *)addr, cnt); 1439 break; 1440 case PPBUS_INSL_EPP: 1441 bus_space_read_multi_4(atppc->sc_iot, atppc->sc_ioh, 1442 ATPPC_EPP_DATA, (u_int32_t *)addr, cnt); 1443 break; 1444 case PPBUS_RDTR: 1445 val = (atppc_r_dtr(atppc)); 1446 break; 1447 case PPBUS_RSTR: 1448 val = (atppc_r_str(atppc)); 1449 break; 1450 case PPBUS_RCTR: 1451 val = (atppc_r_ctr(atppc)); 1452 break; 1453 case PPBUS_REPP_A: 1454 val = (atppc_r_eppA(atppc)); 1455 break; 1456 case PPBUS_REPP_D: 1457 val = (atppc_r_eppD(atppc)); 1458 break; 1459 case PPBUS_RECR: 1460 val = (atppc_r_ecr(atppc)); 1461 break; 1462 case PPBUS_RFIFO: 1463 val = (atppc_r_fifo(atppc)); 1464 break; 1465 case PPBUS_WDTR: 1466 atppc_w_dtr(atppc, byte); 1467 break; 1468 case PPBUS_WSTR: 1469 atppc_w_str(atppc, byte); 1470 break; 1471 case PPBUS_WCTR: 1472 atppc_w_ctr(atppc, byte); 1473 break; 1474 case PPBUS_WEPP_A: 1475 atppc_w_eppA(atppc, byte); 1476 break; 1477 case PPBUS_WEPP_D: 1478 atppc_w_eppD(atppc, byte); 1479 break; 1480 case PPBUS_WECR: 1481 atppc_w_ecr(atppc, byte); 1482 break; 1483 case PPBUS_WFIFO: 1484 atppc_w_fifo(atppc, byte); 1485 break; 1486 default: 1487 panic("%s(%s): unknown I/O operation", dev->dv_xname, 1488 __func__); 1489 break; 1490 } 1491 1492 atppc_barrier(atppc); 1493 1494 ATPPC_UNLOCK(atppc); 1495 splx(s); 1496 1497 return val; 1498 } 1499 1500 /* Read "instance variables" of atppc device */ 1501 static int 1502 atppc_read_ivar(struct device *dev, int index, unsigned int *val) 1503 { 1504 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1505 int rval = 0; 1506 int s; 1507 1508 s = splatppc(); 1509 ATPPC_LOCK(atppc); 1510 1511 switch(index) { 1512 case PPBUS_IVAR_EPP_PROTO: 1513 if (atppc->sc_epp == ATPPC_EPP_1_9) 1514 *val = PPBUS_EPP_1_9; 1515 else if (atppc->sc_epp == ATPPC_EPP_1_7) 1516 *val = PPBUS_EPP_1_7; 1517 break; 1518 1519 case PPBUS_IVAR_INTR: 1520 if (atppc->sc_use & ATPPC_USE_INTR) 1521 *val = 1; 1522 else 1523 *val = 0; 1524 break; 1525 1526 case PPBUS_IVAR_DMA: 1527 if (atppc->sc_use & ATPPC_USE_DMA) 1528 *val = 1; 1529 else 1530 *val = 0; 1531 break; 1532 break; 1533 1534 default: 1535 rval = ENODEV; 1536 } 1537 1538 ATPPC_UNLOCK(atppc); 1539 splx(s); 1540 1541 return rval; 1542 } 1543 1544 /* Write "instance varaibles" of atppc device */ 1545 static int 1546 atppc_write_ivar(struct device *dev, int index, unsigned int *val) 1547 { 1548 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1549 int rval = 0; 1550 int s; 1551 1552 s = splatppc(); 1553 ATPPC_LOCK(atppc); 1554 1555 switch(index) { 1556 case PPBUS_IVAR_EPP_PROTO: 1557 if (*val == PPBUS_EPP_1_9 || *val == PPBUS_EPP_1_7) 1558 atppc->sc_epp = *val; 1559 else 1560 rval = EINVAL; 1561 break; 1562 1563 case PPBUS_IVAR_INTR: 1564 if (*val == 0) 1565 atppc->sc_use &= ~ATPPC_USE_INTR; 1566 else if (atppc->sc_has & ATPPC_HAS_INTR) 1567 atppc->sc_use |= ATPPC_USE_INTR; 1568 else 1569 rval = ENODEV; 1570 break; 1571 1572 case PPBUS_IVAR_DMA: 1573 if (*val == 0) 1574 atppc->sc_use &= ~ATPPC_USE_DMA; 1575 else if (atppc->sc_has & ATPPC_HAS_DMA) 1576 atppc->sc_use |= ATPPC_USE_DMA; 1577 else 1578 rval = ENODEV; 1579 break; 1580 1581 default: 1582 rval = ENODEV; 1583 } 1584 1585 ATPPC_UNLOCK(atppc); 1586 splx(s); 1587 1588 return rval; 1589 } 1590 1591 /* Add a handler routine to be called by the interrupt handler */ 1592 static int 1593 atppc_add_handler(struct device *dev, void (*handler)(void *), void *arg) 1594 { 1595 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1596 struct atppc_handler_node *callback; 1597 int rval = 0; 1598 int s; 1599 1600 s = splatppc(); 1601 ATPPC_LOCK(atppc); 1602 1603 if (handler == NULL) { 1604 ATPPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1605 __func__, dev->dv_xname)); 1606 rval = EINVAL; 1607 } else { 1608 callback = malloc(sizeof(struct atppc_handler_node), M_DEVBUF, 1609 M_NOWAIT); 1610 if (callback) { 1611 callback->func = handler; 1612 callback->arg = arg; 1613 SLIST_INSERT_HEAD(&(atppc->sc_handler_listhead), 1614 callback, entries); 1615 } else { 1616 rval = ENOMEM; 1617 } 1618 } 1619 1620 ATPPC_UNLOCK(atppc); 1621 splx(s); 1622 1623 return rval; 1624 } 1625 1626 /* Remove a handler added by atppc_add_handler() */ 1627 static int 1628 atppc_remove_handler(struct device *dev, void (*handler)(void *)) 1629 { 1630 struct atppc_softc *atppc = (struct atppc_softc *)dev; 1631 struct atppc_handler_node *callback; 1632 int rval = EINVAL; 1633 int s; 1634 1635 s = splatppc(); 1636 ATPPC_LOCK(atppc); 1637 1638 if (SLIST_EMPTY(&(atppc->sc_handler_listhead))) 1639 panic("%s(%s): attempt to remove handler from empty list.\n", 1640 __func__, dev->dv_xname); 1641 1642 /* Search list for handler */ 1643 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), entries) { 1644 if (callback->func == handler) { 1645 SLIST_REMOVE(&(atppc->sc_handler_listhead), callback, 1646 atppc_handler_node, entries); 1647 free(callback, M_DEVBUF); 1648 rval = 0; 1649 break; 1650 } 1651 } 1652 1653 ATPPC_UNLOCK(atppc); 1654 splx(s); 1655 1656 return rval; 1657 } 1658 1659 /* Utility functions */ 1660 1661 1662 /* 1663 * Functions that read bytes from port into buffer: called from interrupt 1664 * handler depending on current chipset mode and cause of interrupt. Return 1665 * value: number of bytes moved. 1666 */ 1667 1668 /* Only the lower 4 bits of the final value are valid */ 1669 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1670 1671 /* Read bytes in nibble mode */ 1672 static void 1673 atppc_nibble_read(struct atppc_softc *atppc) 1674 { 1675 int i; 1676 u_int8_t nibble[2]; 1677 u_int8_t ctr; 1678 u_int8_t str; 1679 1680 /* Enable interrupts if needed */ 1681 if (atppc->sc_use & ATPPC_USE_INTR) { 1682 ctr = atppc_r_ctr(atppc); 1683 atppc_barrier_r(atppc); 1684 if (!(ctr & IRQENABLE)) { 1685 ctr |= IRQENABLE; 1686 atppc_w_ctr(atppc, ctr); 1687 atppc_barrier_w(atppc); 1688 } 1689 } 1690 1691 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1692 /* Check if device has data to send in idle phase */ 1693 str = atppc_r_str(atppc); 1694 atppc_barrier_r(atppc); 1695 if (str & nDATAVAIL) { 1696 return; 1697 } 1698 1699 /* Nibble-mode handshake transfer */ 1700 for (i = 0; i < 2; i++) { 1701 /* Event 7 - ready to take data (HOSTBUSY low) */ 1702 ctr = atppc_r_ctr(atppc); 1703 atppc_barrier_r(atppc); 1704 ctr |= HOSTBUSY; 1705 atppc_w_ctr(atppc, ctr); 1706 atppc_barrier_w(atppc); 1707 1708 /* Event 8 - peripheral writes the first nibble */ 1709 1710 /* Event 9 - peripheral set nAck low */ 1711 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1712 if (atppc->sc_inerr) 1713 return; 1714 1715 /* read nibble */ 1716 nibble[i] = atppc_r_str(atppc); 1717 1718 /* Event 10 - ack, nibble received */ 1719 ctr &= ~HOSTBUSY; 1720 atppc_w_ctr(atppc, ctr); 1721 1722 /* Event 11 - wait ack from peripherial */ 1723 if (atppc->sc_use & ATPPC_USE_INTR) 1724 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1725 atppc->sc_inb, ATPPC_IRQ_nACK); 1726 else 1727 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, 1728 PTRCLK); 1729 if (atppc->sc_inerr) 1730 return; 1731 } 1732 1733 /* Store byte transfered */ 1734 *(atppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1735 (nibble2char(nibble[0]) & 0x0f); 1736 atppc->sc_inbstart++; 1737 } 1738 } 1739 1740 /* Read bytes in bidirectional mode */ 1741 static void 1742 atppc_byte_read(struct atppc_softc * const atppc) 1743 { 1744 u_int8_t ctr; 1745 u_int8_t str; 1746 1747 /* Check direction bit */ 1748 ctr = atppc_r_ctr(atppc); 1749 atppc_barrier_r(atppc); 1750 if (!(ctr & PCD)) { 1751 ATPPC_DPRINTF(("%s: byte-mode read attempted without direction " 1752 "bit set.", atppc->sc_dev.dv_xname)); 1753 atppc->sc_inerr = ENODEV; 1754 return; 1755 } 1756 /* Enable interrupts if needed */ 1757 if (atppc->sc_use & ATPPC_USE_INTR) { 1758 if (!(ctr & IRQENABLE)) { 1759 ctr |= IRQENABLE; 1760 atppc_w_ctr(atppc, ctr); 1761 atppc_barrier_w(atppc); 1762 } 1763 } 1764 1765 /* Byte-mode handshake transfer */ 1766 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1767 /* Check if device has data to send */ 1768 str = atppc_r_str(atppc); 1769 atppc_barrier_r(atppc); 1770 if (str & nDATAVAIL) { 1771 return; 1772 } 1773 1774 /* Event 7 - ready to take data (nAUTO low) */ 1775 ctr |= HOSTBUSY; 1776 atppc_w_ctr(atppc, ctr); 1777 atppc_barrier_w(atppc); 1778 1779 /* Event 9 - peripheral set nAck low */ 1780 atppc->sc_inerr = atppc_poll_str(atppc, 0, PTRCLK); 1781 if (atppc->sc_inerr) 1782 return; 1783 1784 /* Store byte transfered */ 1785 *(atppc->sc_inbstart) = atppc_r_dtr(atppc); 1786 atppc_barrier_r(atppc); 1787 1788 /* Event 10 - data received, can't accept more */ 1789 ctr &= ~HOSTBUSY; 1790 atppc_w_ctr(atppc, ctr); 1791 atppc_barrier_w(atppc); 1792 1793 /* Event 11 - peripheral ack */ 1794 if (atppc->sc_use & ATPPC_USE_INTR) 1795 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1796 atppc->sc_inb, ATPPC_IRQ_nACK); 1797 else 1798 atppc->sc_inerr = atppc_poll_str(atppc, PTRCLK, PTRCLK); 1799 if (atppc->sc_inerr) 1800 return; 1801 1802 /* Event 16 - strobe */ 1803 str |= HOSTCLK; 1804 atppc_w_str(atppc, str); 1805 atppc_barrier_w(atppc); 1806 DELAY(1); 1807 str &= ~HOSTCLK; 1808 atppc_w_str(atppc, str); 1809 atppc_barrier_w(atppc); 1810 1811 /* Update counter */ 1812 atppc->sc_inbstart++; 1813 } 1814 } 1815 1816 /* Read bytes in EPP mode */ 1817 static void 1818 atppc_epp_read(struct atppc_softc * atppc) 1819 { 1820 if (atppc->sc_epp == ATPPC_EPP_1_9) { 1821 { 1822 uint8_t str; 1823 int i; 1824 1825 atppc_reset_epp_timeout((struct device *)atppc); 1826 for (i = 0; i < atppc->sc_inb_nbytes; i++) { 1827 *(atppc->sc_inbstart) = atppc_r_eppD(atppc); 1828 atppc_barrier_r(atppc); 1829 str = atppc_r_str(atppc); 1830 atppc_barrier_r(atppc); 1831 if (str & TIMEOUT) { 1832 atppc->sc_inerr = EIO; 1833 break; 1834 } 1835 atppc->sc_inbstart++; 1836 } 1837 } 1838 } else { 1839 /* Read data block from EPP data register */ 1840 atppc_r_eppD_multi(atppc, atppc->sc_inbstart, 1841 atppc->sc_inb_nbytes); 1842 atppc_barrier_r(atppc); 1843 /* Update buffer position, byte count and counter */ 1844 atppc->sc_inbstart += atppc->sc_inb_nbytes; 1845 } 1846 1847 return; 1848 } 1849 1850 /* Read bytes in ECP mode */ 1851 static void 1852 atppc_ecp_read(struct atppc_softc *atppc) 1853 { 1854 u_int8_t ecr; 1855 u_int8_t ctr; 1856 u_int8_t str; 1857 const unsigned char ctr_sav = atppc_r_ctr(atppc); 1858 const unsigned char ecr_sav = atppc_r_ecr(atppc); 1859 unsigned int worklen; 1860 1861 /* Check direction bit */ 1862 ctr = ctr_sav; 1863 atppc_barrier_r(atppc); 1864 if (!(ctr & PCD)) { 1865 ATPPC_DPRINTF(("%s: ecp-mode read attempted without direction " 1866 "bit set.", atppc->sc_dev.dv_xname)); 1867 atppc->sc_inerr = ENODEV; 1868 goto end; 1869 } 1870 1871 /* Clear device request if any */ 1872 if (atppc->sc_use & ATPPC_USE_INTR) 1873 atppc->sc_irqstat &= ~ATPPC_IRQ_nFAULT; 1874 1875 while (atppc->sc_inbstart < (atppc->sc_inb + atppc->sc_inb_nbytes)) { 1876 ecr = atppc_r_ecr(atppc); 1877 atppc_barrier_r(atppc); 1878 if (ecr & ATPPC_FIFO_EMPTY) { 1879 /* Check for invalid state */ 1880 if (ecr & ATPPC_FIFO_FULL) { 1881 atppc_ecp_read_error(atppc, worklen); 1882 break; 1883 } 1884 1885 /* Check if device has data to send */ 1886 str = atppc_r_str(atppc); 1887 atppc_barrier_r(atppc); 1888 if (str & nDATAVAIL) { 1889 break; 1890 } 1891 1892 if (atppc->sc_use & ATPPC_USE_INTR) { 1893 /* Enable interrupts */ 1894 ecr &= ~ATPPC_SERVICE_INTR; 1895 atppc_w_ecr(atppc, ecr); 1896 atppc_barrier_w(atppc); 1897 /* Wait for FIFO to fill */ 1898 atppc->sc_inerr = atppc_wait_interrupt(atppc, 1899 atppc->sc_inb, ATPPC_IRQ_FIFO); 1900 if (atppc->sc_inerr) 1901 break; 1902 } else { 1903 DELAY(1); 1904 } 1905 continue; 1906 } 1907 else if (ecr & ATPPC_FIFO_FULL) { 1908 /* Transfer sc_fifo bytes */ 1909 worklen = atppc->sc_fifo; 1910 } 1911 else if (ecr & ATPPC_SERVICE_INTR) { 1912 /* Transfer sc_rthr bytes */ 1913 worklen = atppc->sc_rthr; 1914 } else { 1915 /* At least one byte is in the FIFO */ 1916 worklen = 1; 1917 } 1918 1919 if ((atppc->sc_use & ATPPC_USE_INTR) && 1920 (atppc->sc_use & ATPPC_USE_DMA)) { 1921 1922 atppc_ecp_read_dma(atppc, &worklen, ecr); 1923 } else { 1924 atppc_ecp_read_pio(atppc, &worklen, ecr); 1925 } 1926 1927 if (atppc->sc_inerr) { 1928 atppc_ecp_read_error(atppc, worklen); 1929 break; 1930 } 1931 1932 /* Update counter */ 1933 atppc->sc_inbstart += worklen; 1934 } 1935 end: 1936 atppc_w_ctr(atppc, ctr_sav); 1937 atppc_w_ecr(atppc, ecr_sav); 1938 atppc_barrier_w(atppc); 1939 } 1940 1941 /* Read bytes in ECP mode using DMA transfers */ 1942 static void 1943 atppc_ecp_read_dma(struct atppc_softc *atppc, unsigned int *length, 1944 unsigned char ecr) 1945 { 1946 /* Limit transfer to maximum DMA size and start it */ 1947 *length = min(*length, atppc->sc_dma_maxsize); 1948 atppc->sc_dmastat = ATPPC_DMA_INIT; 1949 atppc->sc_dma_start(atppc, atppc->sc_inbstart, *length, 1950 ATPPC_DMA_MODE_READ); 1951 1952 atppc->sc_dmastat = ATPPC_DMA_STARTED; 1953 1954 /* Enable interrupts, DMA */ 1955 ecr &= ~ATPPC_SERVICE_INTR; 1956 ecr |= ATPPC_ENABLE_DMA; 1957 atppc_w_ecr(atppc, ecr); 1958 atppc_barrier_w(atppc); 1959 1960 /* Wait for DMA completion */ 1961 atppc->sc_inerr = atppc_wait_interrupt(atppc, atppc->sc_inb, 1962 ATPPC_IRQ_DMA); 1963 if (atppc->sc_inerr) 1964 return; 1965 1966 /* Get register value recorded by interrupt handler */ 1967 ecr = atppc->sc_ecr_intr; 1968 /* Clear DMA programming */ 1969 atppc->sc_dma_finish(atppc); 1970 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 1971 /* Disable DMA */ 1972 ecr &= ~ATPPC_ENABLE_DMA; 1973 atppc_w_ecr(atppc, ecr); 1974 atppc_barrier_w(atppc); 1975 } 1976 1977 /* Read bytes in ECP mode using PIO transfers */ 1978 static void 1979 atppc_ecp_read_pio(struct atppc_softc *atppc, unsigned int *length, 1980 unsigned char ecr) 1981 { 1982 /* Disable DMA */ 1983 ecr &= ~ATPPC_ENABLE_DMA; 1984 atppc_w_ecr(atppc, ecr); 1985 atppc_barrier_w(atppc); 1986 1987 /* Read from FIFO */ 1988 atppc_r_fifo_multi(atppc, atppc->sc_inbstart, *length); 1989 } 1990 1991 /* Handle errors for ECP reads */ 1992 static void 1993 atppc_ecp_read_error(struct atppc_softc *atppc, const unsigned int worklen) 1994 { 1995 unsigned char ecr = atppc_r_ecr(atppc); 1996 1997 /* Abort DMA if not finished */ 1998 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 1999 atppc->sc_dma_abort(atppc); 2000 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2001 } 2002 2003 /* Check for invalid states */ 2004 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2005 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2006 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2007 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2008 atppc_barrier_w(atppc); 2009 } 2010 } 2011 2012 /* 2013 * Functions that write bytes to port from buffer: called from atppc_write() 2014 * function depending on current chipset mode. Returns number of bytes moved. 2015 */ 2016 2017 /* Write bytes in std/bidirectional mode */ 2018 static void 2019 atppc_std_write(struct atppc_softc * const atppc) 2020 { 2021 unsigned int timecount; 2022 unsigned char ctr; 2023 2024 ctr = atppc_r_ctr(atppc); 2025 atppc_barrier_r(atppc); 2026 /* Enable interrupts if needed */ 2027 if (atppc->sc_use & ATPPC_USE_INTR) { 2028 if (!(ctr & IRQENABLE)) { 2029 ctr |= IRQENABLE; 2030 atppc_w_ctr(atppc, ctr); 2031 atppc_barrier_w(atppc); 2032 } 2033 } 2034 2035 while (atppc->sc_outbstart < (atppc->sc_outb + atppc->sc_outb_nbytes)) { 2036 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 2037 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2038 if (atppc->sc_outerr) 2039 return; 2040 2041 /* Put data in data register */ 2042 atppc_w_dtr(atppc, *(atppc->sc_outbstart)); 2043 atppc_barrier_w(atppc); 2044 DELAY(1); 2045 2046 /* Pulse strobe to indicate valid data on lines */ 2047 ctr |= STROBE; 2048 atppc_w_ctr(atppc, ctr); 2049 atppc_barrier_w(atppc); 2050 DELAY(1); 2051 ctr &= ~STROBE; 2052 atppc_w_ctr(atppc, ctr); 2053 atppc_barrier_w(atppc); 2054 2055 /* Wait for nACK for MAXBUSYWAIT */ 2056 timecount = 0; 2057 if (atppc->sc_use & ATPPC_USE_INTR) { 2058 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2059 atppc->sc_outb, ATPPC_IRQ_nACK); 2060 if (atppc->sc_outerr) 2061 return; 2062 } else { 2063 /* Try to catch the pulsed acknowledgement */ 2064 atppc->sc_outerr = atppc_poll_str(atppc, 0, nACK); 2065 if (atppc->sc_outerr) 2066 return; 2067 atppc->sc_outerr = atppc_poll_str(atppc, nACK, nACK); 2068 if (atppc->sc_outerr) 2069 return; 2070 } 2071 2072 /* Update buffer position, byte count and counter */ 2073 atppc->sc_outbstart++; 2074 } 2075 } 2076 2077 2078 /* Write bytes in EPP mode */ 2079 static void 2080 atppc_epp_write(struct atppc_softc *atppc) 2081 { 2082 if (atppc->sc_epp == ATPPC_EPP_1_9) { 2083 { 2084 uint8_t str; 2085 int i; 2086 2087 atppc_reset_epp_timeout((struct device *)atppc); 2088 for (i = 0; i < atppc->sc_outb_nbytes; i++) { 2089 atppc_w_eppD(atppc, *(atppc->sc_outbstart)); 2090 atppc_barrier_w(atppc); 2091 str = atppc_r_str(atppc); 2092 atppc_barrier_r(atppc); 2093 if (str & TIMEOUT) { 2094 atppc->sc_outerr = EIO; 2095 break; 2096 } 2097 atppc->sc_outbstart++; 2098 } 2099 } 2100 } else { 2101 /* Write data block to EPP data register */ 2102 atppc_w_eppD_multi(atppc, atppc->sc_outbstart, 2103 atppc->sc_outb_nbytes); 2104 atppc_barrier_w(atppc); 2105 /* Update buffer position, byte count and counter */ 2106 atppc->sc_outbstart += atppc->sc_outb_nbytes; 2107 } 2108 2109 return; 2110 } 2111 2112 2113 /* Write bytes in ECP/Fast Centronics mode */ 2114 static void 2115 atppc_fifo_write(struct atppc_softc * const atppc) 2116 { 2117 unsigned char ctr; 2118 unsigned char ecr; 2119 const unsigned char ctr_sav = atppc_r_ctr(atppc); 2120 const unsigned char ecr_sav = atppc_r_ecr(atppc); 2121 2122 ctr = ctr_sav; 2123 ecr = ecr_sav; 2124 atppc_barrier_r(atppc); 2125 2126 /* Reset and flush FIFO */ 2127 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2128 atppc_barrier_w(atppc); 2129 /* Disable nAck interrupts and initialize port bits */ 2130 ctr &= ~(IRQENABLE | STROBE | AUTOFEED); 2131 atppc_w_ctr(atppc, ctr); 2132 atppc_barrier_w(atppc); 2133 /* Restore mode */ 2134 atppc_w_ecr(atppc, ecr); 2135 atppc_barrier_w(atppc); 2136 2137 /* DMA or Programmed IO */ 2138 if ((atppc->sc_use & ATPPC_USE_DMA) && 2139 (atppc->sc_use & ATPPC_USE_INTR)) { 2140 2141 atppc_fifo_write_dma(atppc, ecr, ctr); 2142 } else { 2143 atppc_fifo_write_pio(atppc, ecr, ctr); 2144 } 2145 2146 /* Restore original register values */ 2147 atppc_w_ctr(atppc, ctr_sav); 2148 atppc_w_ecr(atppc, ecr_sav); 2149 atppc_barrier_w(atppc); 2150 } 2151 2152 static void 2153 atppc_fifo_write_dma(struct atppc_softc * const atppc, unsigned char ecr, 2154 unsigned char ctr) 2155 { 2156 unsigned int len; 2157 unsigned int worklen; 2158 2159 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2160 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2161 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2162 2163 /* Wait for device to become ready */ 2164 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2165 if (atppc->sc_outerr) 2166 return; 2167 2168 /* Reset chipset for next DMA transfer */ 2169 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2170 atppc_barrier_w(atppc); 2171 atppc_w_ecr(atppc, ecr); 2172 atppc_barrier_w(atppc); 2173 2174 /* Limit transfer to minimum of space in FIFO and buffer */ 2175 worklen = min(len, atppc->sc_fifo); 2176 2177 /* Limit transfer to maximum DMA size and start it */ 2178 worklen = min(worklen, atppc->sc_dma_maxsize); 2179 atppc->sc_dmastat = ATPPC_DMA_INIT; 2180 atppc->sc_dma_start(atppc, atppc->sc_outbstart, 2181 worklen, ATPPC_DMA_MODE_WRITE); 2182 atppc->sc_dmastat = ATPPC_DMA_STARTED; 2183 2184 /* Enable interrupts, DMA */ 2185 ecr &= ~ATPPC_SERVICE_INTR; 2186 ecr |= ATPPC_ENABLE_DMA; 2187 atppc_w_ecr(atppc, ecr); 2188 atppc_barrier_w(atppc); 2189 2190 /* Wait for DMA completion */ 2191 atppc->sc_outerr = atppc_wait_interrupt(atppc, atppc->sc_outb, 2192 ATPPC_IRQ_DMA); 2193 if (atppc->sc_outerr) { 2194 atppc_fifo_write_error(atppc, worklen); 2195 return; 2196 } 2197 /* Get register value recorded by interrupt handler */ 2198 ecr = atppc->sc_ecr_intr; 2199 /* Clear DMA programming */ 2200 atppc->sc_dma_finish(atppc); 2201 atppc->sc_dmastat = ATPPC_DMA_COMPLETE; 2202 /* Disable DMA */ 2203 ecr &= ~ATPPC_ENABLE_DMA; 2204 atppc_w_ecr(atppc, ecr); 2205 atppc_barrier_w(atppc); 2206 2207 /* Wait for FIFO to empty */ 2208 for (;;) { 2209 if (ecr & ATPPC_FIFO_EMPTY) { 2210 if (ecr & ATPPC_FIFO_FULL) { 2211 atppc->sc_outerr = EIO; 2212 atppc_fifo_write_error(atppc, worklen); 2213 return; 2214 } else { 2215 break; 2216 } 2217 } 2218 2219 /* Enable service interrupt */ 2220 ecr &= ~ATPPC_SERVICE_INTR; 2221 atppc_w_ecr(atppc, ecr); 2222 atppc_barrier_w(atppc); 2223 2224 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2225 atppc->sc_outb, ATPPC_IRQ_FIFO); 2226 if (atppc->sc_outerr) { 2227 atppc_fifo_write_error(atppc, worklen); 2228 return; 2229 } 2230 2231 /* Get register value recorded by interrupt handler */ 2232 ecr = atppc->sc_ecr_intr; 2233 } 2234 2235 /* Update pointer */ 2236 atppc->sc_outbstart += worklen; 2237 } 2238 } 2239 2240 static void 2241 atppc_fifo_write_pio(struct atppc_softc * const atppc, unsigned char ecr, 2242 unsigned char ctr) 2243 { 2244 unsigned int len; 2245 unsigned int worklen; 2246 unsigned int timecount; 2247 2248 /* Disable DMA */ 2249 ecr &= ~ATPPC_ENABLE_DMA; 2250 atppc_w_ecr(atppc, ecr); 2251 atppc_barrier_w(atppc); 2252 2253 for (len = (atppc->sc_outb + atppc->sc_outb_nbytes) - 2254 atppc->sc_outbstart; len > 0; len = (atppc->sc_outb + 2255 atppc->sc_outb_nbytes) - atppc->sc_outbstart) { 2256 2257 /* Wait for device to become ready */ 2258 atppc->sc_outerr = atppc_poll_str(atppc, SPP_READY, SPP_MASK); 2259 if (atppc->sc_outerr) 2260 return; 2261 2262 /* Limit transfer to minimum of space in FIFO and buffer */ 2263 worklen = min(len, atppc->sc_fifo); 2264 2265 /* Write to FIFO */ 2266 atppc_w_fifo_multi(atppc, atppc->sc_outbstart, worklen); 2267 2268 timecount = 0; 2269 if (atppc->sc_use & ATPPC_USE_INTR) { 2270 ecr = atppc_r_ecr(atppc); 2271 atppc_barrier_w(atppc); 2272 2273 /* Wait for interrupt */ 2274 for (;;) { 2275 if (ecr & ATPPC_FIFO_EMPTY) { 2276 if (ecr & ATPPC_FIFO_FULL) { 2277 atppc->sc_outerr = EIO; 2278 atppc_fifo_write_error(atppc, 2279 worklen); 2280 return; 2281 } else { 2282 break; 2283 } 2284 } 2285 2286 /* Enable service interrupt */ 2287 ecr &= ~ATPPC_SERVICE_INTR; 2288 atppc_w_ecr(atppc, ecr); 2289 atppc_barrier_w(atppc); 2290 2291 atppc->sc_outerr = atppc_wait_interrupt(atppc, 2292 atppc->sc_outb, ATPPC_IRQ_FIFO); 2293 if (atppc->sc_outerr) { 2294 atppc_fifo_write_error(atppc, worklen); 2295 return; 2296 } 2297 2298 /* Get ECR value saved by interrupt handler */ 2299 ecr = atppc->sc_ecr_intr; 2300 } 2301 } else { 2302 for (; timecount < ((MAXBUSYWAIT/hz)*1000000); 2303 timecount++) { 2304 2305 ecr = atppc_r_ecr(atppc); 2306 atppc_barrier_r(atppc); 2307 if (ecr & ATPPC_FIFO_EMPTY) { 2308 if (ecr & ATPPC_FIFO_FULL) { 2309 atppc->sc_outerr = EIO; 2310 atppc_fifo_write_error(atppc, 2311 worklen); 2312 return; 2313 } else { 2314 break; 2315 } 2316 } 2317 DELAY(1); 2318 } 2319 2320 if (((timecount*hz)/1000000) >= MAXBUSYWAIT) { 2321 atppc->sc_outerr = EIO; 2322 atppc_fifo_write_error(atppc, worklen); 2323 return; 2324 } 2325 } 2326 2327 /* Update pointer */ 2328 atppc->sc_outbstart += worklen; 2329 } 2330 } 2331 2332 static void 2333 atppc_fifo_write_error(struct atppc_softc * const atppc, 2334 const unsigned int worklen) 2335 { 2336 unsigned char ecr = atppc_r_ecr(atppc); 2337 2338 /* Abort DMA if not finished */ 2339 if (atppc->sc_dmastat == ATPPC_DMA_STARTED) { 2340 atppc->sc_dma_abort(atppc); 2341 ATPPC_DPRINTF(("%s: DMA interrupted.\n", __func__)); 2342 } 2343 2344 /* Check for invalid states */ 2345 if ((ecr & ATPPC_FIFO_EMPTY) && (ecr & ATPPC_FIFO_FULL)) { 2346 ATPPC_DPRINTF(("%s: FIFO full+empty bits set.\n", __func__)); 2347 } else if (!(ecr & ATPPC_FIFO_EMPTY)) { 2348 unsigned char ctr = atppc_r_ctr(atppc); 2349 int bytes_left; 2350 int i; 2351 2352 ATPPC_DPRINTF(("%s(%s): FIFO not empty.\n", __func__, 2353 atppc->sc_dev.dv_xname)); 2354 2355 /* Drive strobe low to stop data transfer */ 2356 ctr &= ~STROBE; 2357 atppc_w_ctr(atppc, ctr); 2358 atppc_barrier_w(atppc); 2359 2360 /* Determine how many bytes remain in FIFO */ 2361 for (i = 0; i < atppc->sc_fifo; i++) { 2362 atppc_w_fifo(atppc, (unsigned char)i); 2363 ecr = atppc_r_ecr(atppc); 2364 atppc_barrier_r(atppc); 2365 if (ecr & ATPPC_FIFO_FULL) 2366 break; 2367 } 2368 bytes_left = (atppc->sc_fifo) - (i + 1); 2369 ATPPC_DPRINTF(("%s: %d bytes left in FIFO.\n", __func__, 2370 bytes_left)); 2371 2372 /* Update counter */ 2373 atppc->sc_outbstart += (worklen - bytes_left); 2374 } else { 2375 /* Update counter */ 2376 atppc->sc_outbstart += worklen; 2377 } 2378 2379 ATPPC_DPRINTF(("%s: reseting FIFO.\n", __func__)); 2380 atppc_w_ecr(atppc, ATPPC_ECR_PS2); 2381 atppc_barrier_w(atppc); 2382 } 2383 2384 /* 2385 * Poll status register using mask and status for MAXBUSYWAIT. 2386 * Returns 0 if device ready, error value otherwise. 2387 */ 2388 static int 2389 atppc_poll_str(const struct atppc_softc * const atppc, const u_int8_t status, 2390 const u_int8_t mask) 2391 { 2392 unsigned int timecount; 2393 u_int8_t str; 2394 int error = EIO; 2395 2396 /* Wait for str to have status for MAXBUSYWAIT */ 2397 for (timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 2398 timecount++) { 2399 2400 str = atppc_r_str(atppc); 2401 atppc_barrier_r(atppc); 2402 if ((str & mask) == status) { 2403 error = 0; 2404 break; 2405 } 2406 DELAY(1); 2407 } 2408 2409 return error; 2410 } 2411 2412 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 2413 static int 2414 atppc_wait_interrupt(struct atppc_softc * const atppc, const caddr_t where, 2415 const u_int8_t irqstat) 2416 { 2417 int error = EIO; 2418 2419 atppc->sc_irqstat &= ~irqstat; 2420 2421 /* Wait for interrupt for MAXBUSYWAIT */ 2422 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 2423 ATPPC_SC_LOCK(atppc)); 2424 2425 if (!(error) && (atppc->sc_irqstat & irqstat)) { 2426 atppc->sc_irqstat &= ~irqstat; 2427 error = 0; 2428 } 2429 2430 return error; 2431 } 2432
Indexes created Sat Sep 27 14:09:57 GMT 2025