atppcreg.h revision 1.1
1 /*- 2 * Copyright (c) 2001 Alcove - Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp $ 27 * 28 */ 29 30 #ifndef __ATPPCREG_H 31 #define __ATPPCREG_H 32 33 /* Generic register definitions as offsets from a base address */ 34 35 #define ATPPC_SPP_DTR 0 /* SPP data register */ 36 #define ATPPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 37 #define ATPPC_SPP_STR 1 /* SPP status register */ 38 #define ATPPC_SPP_CTR 2 /* SPP control register */ 39 #define ATPPC_EPP_ADDR 3 /* EPP address register (8 bit) */ 40 #define ATPPC_EPP_DATA 4 /* EPP data register (8, 16, 32 bit) */ 41 #define ATPPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 42 #define ATPPC_ECP_CNFGA 0x400 /* Configuration register A */ 43 #define ATPPC_ECP_CNFGB 0x401 /* Configuration register B */ 44 #define ATPPC_ECP_ECR 0x402 /* ECP extended control register */ 45 46 /* ECP control register commands/modes */ 47 #define ATPPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 48 #define ATPPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 49 #define ATPPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 50 #define ATPPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 51 #define ATPPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 52 /* ecr register - bits 5 through 7 */ 53 #define ATPPC_ECR_STD 0x00 /* Standard mode */ 54 #define ATPPC_ECR_PS2 0x20 /* Bidirectional mode */ 55 #define ATPPC_ECR_FIFO 0x40 /* Fast Centronics mode */ 56 #define ATPPC_ECR_ECP 0x60 /* ECP mode */ 57 #define ATPPC_ECR_EPP 0x80 /* EPP mode */ 58 #define ATPPC_ECR_TST 0xd0 /* Test mode*/ 59 #define ATPPC_ECR_CFG 0xe0 /* Test mode*/ 60 61 62 63 /* To set "inverted" flags, do AND. Otherwise, do OR */ 64 /* 0 & x = 0, 1 | x = 1 */ 65 66 /* Clear flags: n(var) is equivalent to var = 0. 67 #define n(flags) (~(flags) & (flags))*/ 68 69 /* Invert flags 70 #define inv(flags) (~(flags))*/ 71 72 /* SPP mode control register bit positions. */ 73 #define STROBE 0x01 74 #define AUTOFEED 0x02 75 #define nINIT 0x04 76 #define SELECTIN 0x08 77 #define IRQENABLE 0x10 78 #define PCD 0x20 79 80 /* 81 #define nSTROBE inv(STROBE) 82 #define nAUTOFEED inv(AUTOFEED) 83 #define INIT inv(nINIT) 84 #define nSELECTIN inv(SELECTIN) 85 #define nPCD inv(PCD) 86 */ 87 88 /* SPP status register bit positions. */ 89 #define TIMEOUT 0x01 90 #define nFAULT 0x08 91 #define SELECT 0x10 92 #define PERROR 0x20 93 #define nACK 0x40 94 #define nBUSY 0x80 95 96 /* Flags indicating ready condition */ 97 #define SPP_READY (SELECT | nFAULT | nBUSY) 98 #define SPP_MASK (SELECT | nFAULT | PERROR | nBUSY) 99 100 /* Byte mode signals */ 101 #define HOSTCLK STROBE /* Also ECP mode signal */ 102 #define HOSTBUSY AUTOFEED 103 #define ACTIVE1284 SELECTIN /* Also ECP mode signal */ 104 #define PTRCLK nACK 105 #define PTRBUSY nBUSY 106 #define ACKDATAREQ PERROR 107 #define XFLAG SELECT /* Also ECP mode signal */ 108 #define nDATAVAIL nFAULT 109 110 /* ECP mode signals */ 111 #define HOSTACK AUTOFEED 112 #define nREVREQ nINIT 113 #define PERICLK nACK 114 #define PERIACK nBUSY 115 #define nACKREV PERROR 116 #define nPERIREQ nFAULT 117 118 /* EPP mode signals */ 119 #define nWRITE STROBE 120 #define nDATASTB AUTOFEED 121 #define nADDRSTB SELECTIN 122 #define nWAIT nBUSY 123 #define nRESET nINIT 124 #define nINTR nACK 125 126 127 /* 128 * Useful macros for reading/writing registers. 129 */ 130 131 /* Reading macros */ 132 #define atppc_r_dtr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 133 ATPPC_SPP_DTR) 134 #define atppc_r_str(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 135 ATPPC_SPP_STR) 136 #define atppc_r_ctr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 137 ATPPC_SPP_CTR) 138 #define atppc_r_eppA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 139 ATPPC_EPP_ADDR) 140 #define atppc_r_eppD(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 141 ATPPC_EPP_DATA) 142 #define atppc_r_eppD_multi(atppc, buf, count) bus_space_read_multi_1( \ 143 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count)) 144 #define atppc_r_cnfgA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 145 ATPPC_ECP_CNFGA) 146 #define atppc_r_cnfgB(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 147 ATPPC_ECP_CNFGB) 148 #define atppc_r_ecr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 149 ATPPC_ECP_ECR) 150 #define atppc_r_fifo(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 151 ATPPC_ECP_D_FIFO) 152 #define atppc_r_fifo_multi(atppc, buf, count) bus_space_read_multi_1( \ 153 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count)) 154 155 /* Writing macros */ 156 #define atppc_w_dtr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 157 (atppc)->sc_ioh, ATPPC_SPP_DTR, (byte)) 158 #define atppc_w_str(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 159 (atppc)->sc_ioh, ATPPC_SPP_STR, (byte)) 160 #define atppc_w_ctr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 161 (atppc)->sc_ioh, ATPPC_SPP_CTR, (byte)) 162 #define atppc_w_eppA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 163 (atppc)->sc_ioh, ATPPC_EPP_ADDR, (byte)) 164 #define atppc_w_eppD(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 165 (atppc)->sc_ioh, ATPPC_EPP_DATA, (byte)) 166 #define atppc_w_eppD_multi(atppc, buf, count) bus_space_write_multi_1( \ 167 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count)) 168 #define atppc_w_cnfgA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 169 (atppc)->sc_ioh, ATPPC_ECP_CNFGA, (byte)) 170 #define atppc_w_cnfgB(atppc, byte) bus_space_read_1((atppc)->sc_iot, \ 171 (atppc)->sc_ioh, ATPPC_ECP_CNFGB, (byte)) 172 #define atppc_w_ecr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 173 (atppc)->sc_ioh, ATPPC_ECP_ECR, (byte)) 174 #define atppc_w_fifo(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 175 (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (byte)) 176 #define atppc_w_fifo_multi(atppc, buf, count) bus_space_write_multi_1( \ 177 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count)) 178 179 /* Barrier macros for reads/writes */ 180 #define atppc_barrier_r(atppc) bus_space_barrier((atppc)->sc_iot, \ 181 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ) 182 #define atppc_barrier_w(atppc) bus_space_barrier((atppc)->sc_iot, \ 183 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE) 184 #define atppc_barrier(atppc) bus_space_barrier((atppc)->sc_iot, \ 185 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE | \ 186 BUS_SPACE_BARRIER_READ) 187 188 /* These are defined in man pages but don't actually exist for all acrhs */ 189 #define atppc_barrier_rr(atppc) bus_space_barrier((atppc)->sc_iot, \ 190 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_READ) 191 #define atppc_barrier_rw(atppc) bus_space_barrier((atppc)->sc_iot, \ 192 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 193 #define atppc_barrier_rb(atppc) bus_space_barrier((atppc)->sc_iot, \ 194 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_READ | \ 195 BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 196 #define atppc_barrier_wr(atppc) bus_space_barrier((atppc)->sc_iot, \ 197 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 198 #define atppc_barrier_ww(atppc) bus_space_barrier((atppc)->sc_iot, \ 199 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 200 #define atppc_barrier_wb(atppc) bus_space_barrier((atppc)->sc_iot, \ 201 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 202 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 203 #define atppc_barrier_sync(atppc) bus_space_barrier((atppc)->sc_iot, \ 204 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_SYNC) 205 206 /* 207 * Register defines for the PC873xx parts 208 */ 209 210 #define PC873_FER 0x00 211 #define PC873_PPENABLE (1<<0) 212 #define PC873_FAR 0x01 213 #define PC873_PTR 0x02 214 #define PC873_CFGLOCK (1<<6) 215 #define PC873_EPPRDIR (1<<7) 216 #define PC873_EXTENDED (1<<7) 217 #define PC873_LPTBIRQ7 (1<<3) 218 #define PC873_FCR 0x03 219 #define PC873_ZWS (1<<5) 220 #define PC873_ZWSPWDN (1<<6) 221 #define PC873_PCR 0x04 222 #define PC873_EPPEN (1<<0) 223 #define PC873_EPP19 (1<<1) 224 #define PC873_ECPEN (1<<2) 225 #define PC873_ECPCLK (1<<3) 226 #define PC873_PMC 0x06 227 #define PC873_TUP 0x07 228 #define PC873_SID 0x08 229 #define PC873_PNP0 0x1b 230 #define PC873_PNP1 0x1c 231 #define PC873_LPTBA 0x19 232 233 /* 234 * Register defines for the SMC FDC37C66xGT parts 235 */ 236 237 /* Init codes */ 238 #define SMC665_iCODE 0x55 239 #define SMC666_iCODE 0x44 240 241 /* Base configuration ports */ 242 #define SMC66x_CSR 0x3F0 243 #define SMC666_CSR 0x370 /* hard-configured value for 666 */ 244 245 /* Bits */ 246 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 247 #define SMC_CR1_MODE (1<<3) /* bit 3 */ 248 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 249 #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 250 251 /* Extended modes */ 252 #define SMC_SPP 0x0 /* SPP */ 253 #define SMC_EPPSPP 0x1 /* EPP and SPP */ 254 #define SMC_ECP 0x2 /* ECP */ 255 #define SMC_ECPEPP 0x3 /* ECP and EPP */ 256 257 /* 258 * Register defines for the SMC FDC37C935 parts 259 */ 260 261 /* Configuration ports */ 262 #define SMC935_CFG 0x370 263 #define SMC935_IND 0x370 264 #define SMC935_DAT 0x371 265 266 /* Registers */ 267 #define SMC935_LOGDEV 0x7 268 #define SMC935_ID 0x20 269 #define SMC935_PORTHI 0x60 270 #define SMC935_PORTLO 0x61 271 #define SMC935_PPMODE 0xf0 272 273 /* Parallel port modes */ 274 #define SMC935_SPP 0x38 + 0 275 #define SMC935_EPP19SPP 0x38 + 1 276 #define SMC935_ECP 0x38 + 2 277 #define SMC935_ECPEPP19 0x38 + 3 278 #define SMC935_CENT 0x38 + 4 279 #define SMC935_EPP17SPP 0x38 + 5 280 #define SMC935_UNUSED 0x38 + 6 281 #define SMC935_ECPEPP17 0x38 + 7 282 283 /* 284 * Register defines for the Winbond W83877F parts 285 */ 286 287 #define WINB_W83877F_ID 0xa 288 #define WINB_W83877AF_ID 0xb 289 290 /* Configuration bits */ 291 #define WINB_HEFERE (1<<5) /* CROC bit 5 */ 292 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 293 294 #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 295 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 296 297 #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 298 #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 299 #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 300 301 /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 302 #define WINB_W83757 0x0 303 #define WINB_EXTFDC 0x4 304 #define WINB_EXTADP 0x8 305 #define WINB_EXT2FDD 0xc 306 #define WINB_JOYSTICK 0x80 307 308 #define WINB_PARALLEL 0x80 309 #define WINB_EPP_SPP 0x4 310 #define WINB_ECP 0x8 311 #define WINB_ECP_EPP 0xc 312 313 #endif /* __ATPPCREG_H */ 314
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