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atw.c revision 1.105.6.1
      1  1.105.6.1   simonb /*	$NetBSD: atw.c,v 1.105.6.1 2006/04/22 11:38:55 simonb Exp $  */
      2        1.1   dyoung 
      3        1.1   dyoung /*-
      4        1.1   dyoung  * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc.
      5        1.1   dyoung  * All rights reserved.
      6        1.1   dyoung  *
      7        1.1   dyoung  * This code is derived from software contributed to The NetBSD Foundation
      8        1.1   dyoung  * by David Young, by Jason R. Thorpe, and by Charles M. Hannum.
      9        1.1   dyoung  *
     10        1.1   dyoung  * Redistribution and use in source and binary forms, with or without
     11        1.1   dyoung  * modification, are permitted provided that the following conditions
     12        1.1   dyoung  * are met:
     13        1.1   dyoung  * 1. Redistributions of source code must retain the above copyright
     14        1.1   dyoung  *    notice, this list of conditions and the following disclaimer.
     15        1.1   dyoung  * 2. Redistributions in binary form must reproduce the above copyright
     16        1.1   dyoung  *    notice, this list of conditions and the following disclaimer in the
     17        1.1   dyoung  *    documentation and/or other materials provided with the distribution.
     18        1.1   dyoung  * 3. All advertising materials mentioning features or use of this software
     19        1.1   dyoung  *    must display the following acknowledgement:
     20        1.1   dyoung  *	This product includes software developed by the NetBSD
     21        1.1   dyoung  *	Foundation, Inc. and its contributors.
     22        1.1   dyoung  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23        1.1   dyoung  *    contributors may be used to endorse or promote products derived
     24        1.1   dyoung  *    from this software without specific prior written permission.
     25        1.1   dyoung  *
     26        1.1   dyoung  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27        1.1   dyoung  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28        1.1   dyoung  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29        1.1   dyoung  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30        1.1   dyoung  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31        1.1   dyoung  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32        1.1   dyoung  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33        1.1   dyoung  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34        1.1   dyoung  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35        1.1   dyoung  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36        1.1   dyoung  * POSSIBILITY OF SUCH DAMAGE.
     37        1.1   dyoung  */
     38        1.1   dyoung 
     39        1.1   dyoung /*
     40        1.1   dyoung  * Device driver for the ADMtek ADM8211 802.11 MAC/BBP.
     41        1.1   dyoung  */
     42        1.1   dyoung 
     43        1.1   dyoung #include <sys/cdefs.h>
     44  1.105.6.1   simonb __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.105.6.1 2006/04/22 11:38:55 simonb Exp $");
     45        1.1   dyoung 
     46        1.1   dyoung #include "bpfilter.h"
     47        1.1   dyoung 
     48        1.1   dyoung #include <sys/param.h>
     49       1.84    perry #include <sys/systm.h>
     50        1.1   dyoung #include <sys/callout.h>
     51       1.84    perry #include <sys/mbuf.h>
     52        1.1   dyoung #include <sys/malloc.h>
     53        1.1   dyoung #include <sys/kernel.h>
     54        1.1   dyoung #include <sys/socket.h>
     55        1.1   dyoung #include <sys/ioctl.h>
     56        1.1   dyoung #include <sys/errno.h>
     57        1.1   dyoung #include <sys/device.h>
     58        1.1   dyoung #include <sys/time.h>
     59  1.105.6.1   simonb #include <lib/libkern/libkern.h>
     60        1.1   dyoung 
     61        1.1   dyoung #include <machine/endian.h>
     62        1.1   dyoung 
     63        1.1   dyoung #include <uvm/uvm_extern.h>
     64       1.84    perry 
     65        1.1   dyoung #include <net/if.h>
     66        1.1   dyoung #include <net/if_dl.h>
     67        1.1   dyoung #include <net/if_media.h>
     68        1.1   dyoung #include <net/if_ether.h>
     69        1.3   dyoung 
     70       1.85   dyoung #include <net80211/ieee80211_netbsd.h>
     71        1.3   dyoung #include <net80211/ieee80211_var.h>
     72       1.12   dyoung #include <net80211/ieee80211_radiotap.h>
     73        1.1   dyoung 
     74       1.84    perry #if NBPFILTER > 0
     75        1.1   dyoung #include <net/bpf.h>
     76       1.84    perry #endif
     77        1.1   dyoung 
     78        1.1   dyoung #include <machine/bus.h>
     79        1.1   dyoung #include <machine/intr.h>
     80        1.1   dyoung 
     81        1.1   dyoung #include <dev/ic/atwreg.h>
     82       1.24   dyoung #include <dev/ic/rf3000reg.h>
     83       1.24   dyoung #include <dev/ic/si4136reg.h>
     84        1.1   dyoung #include <dev/ic/atwvar.h>
     85        1.1   dyoung #include <dev/ic/smc93cx6var.h>
     86        1.1   dyoung 
     87        1.1   dyoung /* XXX TBD open questions
     88        1.1   dyoung  *
     89        1.1   dyoung  *
     90        1.1   dyoung  * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps
     91        1.1   dyoung  * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC
     92        1.1   dyoung  * handle this for me?
     93        1.1   dyoung  *
     94        1.1   dyoung  */
     95        1.1   dyoung /* device attachment
     96        1.1   dyoung  *
     97        1.1   dyoung  *    print TOFS[012]
     98        1.1   dyoung  *
     99        1.1   dyoung  * device initialization
    100        1.1   dyoung  *
    101        1.1   dyoung  *    clear ATW_FRCTL_MAXPSP to disable max power saving
    102        1.1   dyoung  *    set ATW_TXBR_ALCUPDATE to enable ALC
    103        1.1   dyoung  *    set TOFS[012]? (hope not)
    104        1.1   dyoung  *    disable rx/tx
    105        1.1   dyoung  *    set ATW_PAR_SWR (software reset)
    106        1.1   dyoung  *    wait for ATW_PAR_SWR clear
    107        1.1   dyoung  *    disable interrupts
    108       1.84    perry  *    ack status register
    109       1.84    perry  *    enable interrupts
    110        1.1   dyoung  *
    111        1.1   dyoung  * rx/tx initialization
    112        1.1   dyoung  *
    113        1.1   dyoung  *    disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
    114        1.1   dyoung  *    allocate and init descriptor rings
    115        1.1   dyoung  *    write ATW_PAR_DSL (descriptor skip length)
    116       1.84    perry  *    write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB
    117        1.1   dyoung  *    write ATW_NAR_SQ for one/both transmit descriptor rings
    118        1.1   dyoung  *    write ATW_NAR_SQ for one/both transmit descriptor rings
    119        1.1   dyoung  *    enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
    120        1.1   dyoung  *
    121        1.1   dyoung  * rx/tx end
    122        1.1   dyoung  *
    123        1.1   dyoung  *    stop DMA
    124        1.1   dyoung  *    disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
    125        1.1   dyoung  *    flush tx w/ ATW_NAR_HF
    126        1.1   dyoung  *
    127        1.1   dyoung  * scan
    128        1.1   dyoung  *
    129        1.1   dyoung  *    initialize rx/tx
    130        1.1   dyoung  *
    131        1.1   dyoung  * BSS join: (re)association response
    132        1.1   dyoung  *
    133        1.1   dyoung  *    set ATW_FRCTL_AID
    134        1.1   dyoung  *
    135        1.1   dyoung  * optimizations ???
    136        1.1   dyoung  *
    137        1.1   dyoung  */
    138        1.1   dyoung 
    139       1.59   dyoung #define ATW_REFSLAVE	/* slavishly do what the reference driver does */
    140       1.59   dyoung 
    141        1.1   dyoung #define	VOODOO_DUR_11_ROUNDING		0x01 /* necessary */
    142        1.1   dyoung #define	VOODOO_DUR_2_4_SPECIALCASE	0x02 /* NOT necessary */
    143        1.1   dyoung int atw_voodoo = VOODOO_DUR_11_ROUNDING;
    144        1.1   dyoung 
    145       1.70   dyoung int atw_pseudo_milli = 1;
    146       1.70   dyoung int atw_magic_delay1 = 100 * 1000;
    147       1.70   dyoung int atw_magic_delay2 = 100 * 1000;
    148       1.70   dyoung /* more magic multi-millisecond delays (units: microseconds) */
    149       1.70   dyoung int atw_nar_delay = 20 * 1000;
    150       1.70   dyoung int atw_magic_delay4 = 10 * 1000;
    151       1.70   dyoung int atw_rf_delay1 = 10 * 1000;
    152       1.70   dyoung int atw_rf_delay2 = 5 * 1000;
    153       1.70   dyoung int atw_plcphd_delay = 2 * 1000;
    154       1.59   dyoung int atw_bbp_io_enable_delay = 20 * 1000;
    155       1.59   dyoung int atw_bbp_io_disable_delay = 2 * 1000;
    156       1.59   dyoung int atw_writewep_delay = 1000;
    157        1.1   dyoung int atw_beacon_len_adjust = 4;
    158        1.3   dyoung int atw_dwelltime = 200;
    159       1.59   dyoung int atw_xindiv2 = 0;
    160        1.1   dyoung 
    161        1.1   dyoung #ifdef ATW_DEBUG
    162        1.1   dyoung int atw_debug = 0;
    163        1.1   dyoung 
    164        1.1   dyoung #define ATW_DPRINTF(x)	if (atw_debug > 0) printf x
    165        1.1   dyoung #define ATW_DPRINTF2(x)	if (atw_debug > 1) printf x
    166        1.1   dyoung #define ATW_DPRINTF3(x)	if (atw_debug > 2) printf x
    167       1.85   dyoung #define	DPRINTF(sc, x)	if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x
    168       1.85   dyoung #define	DPRINTF2(sc, x)	if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x)
    169       1.85   dyoung #define	DPRINTF3(sc, x)	if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x)
    170       1.39   dyoung 
    171       1.74   dyoung static void	atw_dump_pkt(struct ifnet *, struct mbuf *);
    172       1.74   dyoung static void	atw_print_regs(struct atw_softc *, const char *);
    173       1.39   dyoung 
    174       1.39   dyoung /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */
    175       1.84    perry #	ifdef ATW_BBPDEBUG
    176       1.74   dyoung static void	atw_rf3000_print(struct atw_softc *);
    177       1.74   dyoung static int	atw_rf3000_read(struct atw_softc *sc, u_int, u_int *);
    178       1.39   dyoung #	endif /* ATW_BBPDEBUG */
    179       1.39   dyoung 
    180       1.84    perry #	ifdef ATW_SYNDEBUG
    181       1.74   dyoung static void	atw_si4126_print(struct atw_softc *);
    182       1.74   dyoung static int	atw_si4126_read(struct atw_softc *, u_int, u_int *);
    183       1.39   dyoung #	endif /* ATW_SYNDEBUG */
    184       1.39   dyoung 
    185        1.1   dyoung #else
    186        1.1   dyoung #define ATW_DPRINTF(x)
    187        1.1   dyoung #define ATW_DPRINTF2(x)
    188        1.1   dyoung #define ATW_DPRINTF3(x)
    189        1.1   dyoung #define	DPRINTF(sc, x)	/* nothing */
    190        1.1   dyoung #define	DPRINTF2(sc, x)	/* nothing */
    191        1.1   dyoung #define	DPRINTF3(sc, x)	/* nothing */
    192        1.1   dyoung #endif
    193        1.1   dyoung 
    194       1.61   dyoung /* ifnet methods */
    195       1.74   dyoung int	atw_init(struct ifnet *);
    196       1.74   dyoung int	atw_ioctl(struct ifnet *, u_long, caddr_t);
    197       1.23   dyoung void	atw_start(struct ifnet *);
    198       1.74   dyoung void	atw_stop(struct ifnet *, int);
    199       1.23   dyoung void	atw_watchdog(struct ifnet *);
    200       1.23   dyoung 
    201       1.61   dyoung /* Device attachment */
    202       1.61   dyoung void	atw_attach(struct atw_softc *);
    203       1.61   dyoung int	atw_detach(struct atw_softc *);
    204       1.23   dyoung 
    205       1.61   dyoung /* Rx/Tx process */
    206       1.74   dyoung int	atw_add_rxbuf(struct atw_softc *, int);
    207       1.74   dyoung void	atw_idle(struct atw_softc *, u_int32_t);
    208       1.23   dyoung void	atw_rxdrain(struct atw_softc *);
    209       1.61   dyoung void	atw_txdrain(struct atw_softc *);
    210       1.23   dyoung 
    211       1.61   dyoung /* Device (de)activation and power state */
    212       1.74   dyoung void	atw_disable(struct atw_softc *);
    213       1.23   dyoung int	atw_enable(struct atw_softc *);
    214       1.23   dyoung void	atw_power(int, void *);
    215       1.74   dyoung void	atw_reset(struct atw_softc *);
    216       1.61   dyoung void	atw_shutdown(void *);
    217       1.23   dyoung 
    218       1.61   dyoung /* Interrupt handlers */
    219       1.74   dyoung void	atw_linkintr(struct atw_softc *, u_int32_t);
    220       1.23   dyoung void	atw_rxintr(struct atw_softc *);
    221       1.23   dyoung void	atw_txintr(struct atw_softc *);
    222        1.1   dyoung 
    223       1.61   dyoung /* 802.11 state machine */
    224       1.61   dyoung static int	atw_newstate(struct ieee80211com *, enum ieee80211_state, int);
    225       1.74   dyoung static void	atw_next_scan(void *);
    226       1.61   dyoung static void	atw_recv_mgmt(struct ieee80211com *, struct mbuf *,
    227       1.61   dyoung 		              struct ieee80211_node *, int, int, u_int32_t);
    228       1.74   dyoung static int	atw_tune(struct atw_softc *);
    229       1.61   dyoung 
    230       1.61   dyoung /* Device initialization */
    231       1.74   dyoung static void	atw_bbp_io_init(struct atw_softc *);
    232       1.74   dyoung static void	atw_cfp_init(struct atw_softc *);
    233       1.61   dyoung static void	atw_cmdr_init(struct atw_softc *);
    234       1.74   dyoung static void	atw_ifs_init(struct atw_softc *);
    235       1.74   dyoung static void	atw_nar_init(struct atw_softc *);
    236       1.74   dyoung static void	atw_response_times_init(struct atw_softc *);
    237       1.74   dyoung static void	atw_rf_reset(struct atw_softc *);
    238       1.74   dyoung static void	atw_test1_init(struct atw_softc *);
    239       1.74   dyoung static void	atw_tofs0_init(struct atw_softc *);
    240       1.61   dyoung static void	atw_tofs2_init(struct atw_softc *);
    241       1.61   dyoung static void	atw_txlmt_init(struct atw_softc *);
    242       1.74   dyoung static void	atw_wcsr_init(struct atw_softc *);
    243       1.61   dyoung 
    244       1.85   dyoung /* Key management */
    245       1.85   dyoung static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *);
    246       1.85   dyoung static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *,
    247       1.85   dyoung 	const u_int8_t[IEEE80211_ADDR_LEN]);
    248       1.85   dyoung static void atw_key_update_begin(struct ieee80211com *);
    249       1.85   dyoung static void atw_key_update_end(struct ieee80211com *);
    250       1.85   dyoung 
    251       1.61   dyoung /* RAM/ROM utilities */
    252       1.61   dyoung static void	atw_clear_sram(struct atw_softc *);
    253       1.61   dyoung static void	atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int);
    254       1.61   dyoung static int	atw_read_srom(struct atw_softc *);
    255       1.61   dyoung 
    256       1.61   dyoung /* BSS setup */
    257       1.76   dyoung static void	atw_predict_beacon(struct atw_softc *);
    258       1.61   dyoung static void	atw_start_beacon(struct atw_softc *, int);
    259       1.61   dyoung static void	atw_write_bssid(struct atw_softc *);
    260       1.61   dyoung static void	atw_write_ssid(struct atw_softc *);
    261       1.61   dyoung static void	atw_write_sup_rates(struct atw_softc *);
    262       1.61   dyoung static void	atw_write_wep(struct atw_softc *);
    263       1.61   dyoung 
    264       1.61   dyoung /* Media */
    265       1.61   dyoung static int	atw_media_change(struct ifnet *);
    266       1.61   dyoung 
    267       1.61   dyoung static void	atw_filter_setup(struct atw_softc *);
    268       1.61   dyoung 
    269       1.61   dyoung /* 802.11 utilities */
    270       1.78   dyoung static uint64_t			atw_get_tsft(struct atw_softc *);
    271       1.92    perry static inline uint32_t	atw_last_even_tsft(uint32_t, uint32_t,
    272       1.61   dyoung 				                   uint32_t);
    273       1.85   dyoung static struct ieee80211_node	*atw_node_alloc(struct ieee80211_node_table *);
    274       1.85   dyoung static void			atw_node_free(struct ieee80211_node *);
    275        1.1   dyoung 
    276       1.61   dyoung /*
    277       1.61   dyoung  * Tuner/transceiver/modem
    278       1.61   dyoung  */
    279       1.61   dyoung static void	atw_bbp_io_enable(struct atw_softc *, int);
    280        1.1   dyoung 
    281        1.1   dyoung /* RFMD RF3000 Baseband Processor */
    282       1.74   dyoung static int	atw_rf3000_init(struct atw_softc *);
    283       1.74   dyoung static int	atw_rf3000_tune(struct atw_softc *, u_int);
    284       1.74   dyoung static int	atw_rf3000_write(struct atw_softc *, u_int, u_int);
    285        1.1   dyoung 
    286        1.1   dyoung /* Silicon Laboratories Si4126 RF/IF Synthesizer */
    287       1.74   dyoung static void	atw_si4126_tune(struct atw_softc *, u_int);
    288       1.74   dyoung static void	atw_si4126_write(struct atw_softc *, u_int, u_int);
    289        1.1   dyoung 
    290        1.1   dyoung const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE;
    291        1.1   dyoung const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE;
    292        1.1   dyoung 
    293        1.1   dyoung const char *atw_tx_state[] = {
    294        1.1   dyoung 	"STOPPED",
    295       1.26   dyoung 	"RUNNING - read descriptor",
    296       1.26   dyoung 	"RUNNING - transmitting",
    297       1.26   dyoung 	"RUNNING - filling fifo",	/* XXX */
    298        1.1   dyoung 	"SUSPENDED",
    299       1.26   dyoung 	"RUNNING -- write descriptor",
    300       1.26   dyoung 	"RUNNING -- write last descriptor",
    301       1.26   dyoung 	"RUNNING - fifo full"
    302        1.1   dyoung };
    303        1.1   dyoung 
    304        1.1   dyoung const char *atw_rx_state[] = {
    305        1.1   dyoung 	"STOPPED",
    306       1.26   dyoung 	"RUNNING - read descriptor",
    307       1.26   dyoung 	"RUNNING - check this packet, pre-fetch next",
    308       1.26   dyoung 	"RUNNING - wait for reception",
    309        1.1   dyoung 	"SUSPENDED",
    310       1.26   dyoung 	"RUNNING - write descriptor",
    311       1.26   dyoung 	"RUNNING - flush fifo",
    312       1.26   dyoung 	"RUNNING - fifo drain"
    313        1.1   dyoung };
    314        1.1   dyoung 
    315      1.104   dyoung static inline int
    316      1.104   dyoung is_running(struct ifnet *ifp)
    317      1.104   dyoung {
    318      1.104   dyoung 	return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP);
    319      1.104   dyoung }
    320      1.104   dyoung 
    321        1.1   dyoung int
    322        1.1   dyoung atw_activate(struct device *self, enum devact act)
    323        1.1   dyoung {
    324        1.1   dyoung 	struct atw_softc *sc = (struct atw_softc *)self;
    325        1.1   dyoung 	int rv = 0, s;
    326        1.1   dyoung 
    327        1.1   dyoung 	s = splnet();
    328        1.1   dyoung 	switch (act) {
    329        1.1   dyoung 	case DVACT_ACTIVATE:
    330        1.1   dyoung 		rv = EOPNOTSUPP;
    331        1.1   dyoung 		break;
    332        1.1   dyoung 
    333        1.1   dyoung 	case DVACT_DEACTIVATE:
    334       1.85   dyoung 		if_deactivate(&sc->sc_if);
    335        1.1   dyoung 		break;
    336        1.1   dyoung 	}
    337        1.1   dyoung 	splx(s);
    338        1.1   dyoung 	return rv;
    339        1.1   dyoung }
    340        1.1   dyoung 
    341        1.1   dyoung /*
    342        1.1   dyoung  * atw_enable:
    343        1.1   dyoung  *
    344        1.1   dyoung  *	Enable the ADM8211 chip.
    345        1.1   dyoung  */
    346        1.1   dyoung int
    347       1.23   dyoung atw_enable(struct atw_softc *sc)
    348        1.1   dyoung {
    349        1.1   dyoung 
    350        1.1   dyoung 	if (ATW_IS_ENABLED(sc) == 0) {
    351        1.1   dyoung 		if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) {
    352        1.1   dyoung 			printf("%s: device enable failed\n",
    353        1.1   dyoung 			    sc->sc_dev.dv_xname);
    354        1.1   dyoung 			return (EIO);
    355        1.1   dyoung 		}
    356        1.1   dyoung 		sc->sc_flags |= ATWF_ENABLED;
    357  1.105.6.1   simonb                 /* Power may have been removed, and WEP keys thus
    358  1.105.6.1   simonb                  * reset.
    359  1.105.6.1   simonb 		 */
    360  1.105.6.1   simonb 		sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
    361        1.1   dyoung 	}
    362        1.1   dyoung 	return (0);
    363        1.1   dyoung }
    364        1.1   dyoung 
    365        1.1   dyoung /*
    366        1.1   dyoung  * atw_disable:
    367        1.1   dyoung  *
    368        1.1   dyoung  *	Disable the ADM8211 chip.
    369        1.1   dyoung  */
    370        1.1   dyoung void
    371       1.23   dyoung atw_disable(struct atw_softc *sc)
    372        1.1   dyoung {
    373        1.1   dyoung 	if (!ATW_IS_ENABLED(sc))
    374        1.1   dyoung 		return;
    375        1.1   dyoung 	if (sc->sc_disable != NULL)
    376        1.1   dyoung 		(*sc->sc_disable)(sc);
    377        1.1   dyoung 	sc->sc_flags &= ~ATWF_ENABLED;
    378        1.1   dyoung }
    379        1.1   dyoung 
    380        1.1   dyoung /* Returns -1 on failure. */
    381       1.62   dyoung static int
    382        1.1   dyoung atw_read_srom(struct atw_softc *sc)
    383        1.1   dyoung {
    384        1.1   dyoung 	struct seeprom_descriptor sd;
    385       1.69   dyoung 	uint32_t test0, fail_bits;
    386        1.1   dyoung 
    387        1.1   dyoung 	(void)memset(&sd, 0, sizeof(sd));
    388        1.1   dyoung 
    389       1.69   dyoung 	test0 = ATW_READ(sc, ATW_TEST0);
    390        1.1   dyoung 
    391       1.69   dyoung 	switch (sc->sc_rev) {
    392       1.69   dyoung 	case ATW_REVISION_BA:
    393       1.69   dyoung 	case ATW_REVISION_CA:
    394       1.69   dyoung 		fail_bits = ATW_TEST0_EPNE;
    395       1.69   dyoung 		break;
    396       1.69   dyoung 	default:
    397       1.69   dyoung 		fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM;
    398       1.69   dyoung 		break;
    399       1.69   dyoung 	}
    400       1.69   dyoung 	if ((test0 & fail_bits) != 0) {
    401        1.1   dyoung 		printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname);
    402        1.1   dyoung 		return -1;
    403        1.1   dyoung 	}
    404        1.1   dyoung 
    405       1.69   dyoung 	switch (test0 & ATW_TEST0_EPTYP_MASK) {
    406        1.1   dyoung 	case ATW_TEST0_EPTYP_93c66:
    407        1.1   dyoung 		ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname));
    408        1.1   dyoung 		sc->sc_sromsz = 512;
    409        1.1   dyoung 		sd.sd_chip = C56_66;
    410        1.1   dyoung 		break;
    411        1.1   dyoung 	case ATW_TEST0_EPTYP_93c46:
    412        1.1   dyoung 		ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname));
    413        1.1   dyoung 		sc->sc_sromsz = 128;
    414        1.1   dyoung 		sd.sd_chip = C46;
    415        1.1   dyoung 		break;
    416        1.1   dyoung 	default:
    417        1.1   dyoung 		printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname,
    418  1.105.6.1   simonb 		    SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK));
    419        1.1   dyoung 		return -1;
    420        1.1   dyoung 	}
    421        1.1   dyoung 
    422        1.1   dyoung 	sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT);
    423        1.1   dyoung 
    424        1.1   dyoung 	if (sc->sc_srom == NULL) {
    425        1.1   dyoung 		printf("%s: unable to allocate SROM buffer\n",
    426        1.1   dyoung 		    sc->sc_dev.dv_xname);
    427        1.1   dyoung 		return -1;
    428        1.1   dyoung 	}
    429        1.1   dyoung 
    430        1.1   dyoung 	(void)memset(sc->sc_srom, 0, sc->sc_sromsz);
    431        1.1   dyoung 
    432        1.1   dyoung 	/* ADM8211 has a single 32-bit register for controlling the
    433        1.1   dyoung 	 * 93cx6 SROM.  Bit SRS enables the serial port. There is no
    434        1.1   dyoung 	 * "ready" bit. The ADM8211 input/output sense is the reverse
    435        1.1   dyoung 	 * of read_seeprom's.
    436        1.1   dyoung 	 */
    437        1.1   dyoung 	sd.sd_tag = sc->sc_st;
    438        1.1   dyoung 	sd.sd_bsh = sc->sc_sh;
    439        1.1   dyoung 	sd.sd_regsize = 4;
    440        1.1   dyoung 	sd.sd_control_offset = ATW_SPR;
    441        1.1   dyoung 	sd.sd_status_offset = ATW_SPR;
    442        1.1   dyoung 	sd.sd_dataout_offset = ATW_SPR;
    443        1.1   dyoung 	sd.sd_CK = ATW_SPR_SCLK;
    444        1.1   dyoung 	sd.sd_CS = ATW_SPR_SCS;
    445        1.1   dyoung 	sd.sd_DI = ATW_SPR_SDO;
    446        1.1   dyoung 	sd.sd_DO = ATW_SPR_SDI;
    447        1.1   dyoung 	sd.sd_MS = ATW_SPR_SRS;
    448        1.1   dyoung 	sd.sd_RDY = 0;
    449        1.1   dyoung 
    450        1.1   dyoung 	if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) {
    451        1.1   dyoung 		printf("%s: could not read SROM\n", sc->sc_dev.dv_xname);
    452        1.1   dyoung 		free(sc->sc_srom, M_DEVBUF);
    453        1.1   dyoung 		return -1;
    454        1.1   dyoung 	}
    455        1.1   dyoung #ifdef ATW_DEBUG
    456        1.1   dyoung 	{
    457        1.1   dyoung 		int i;
    458       1.15   dyoung 		ATW_DPRINTF(("\nSerial EEPROM:\n\t"));
    459        1.1   dyoung 		for (i = 0; i < sc->sc_sromsz/2; i = i + 1) {
    460        1.1   dyoung 			if (((i % 8) == 0) && (i != 0)) {
    461       1.15   dyoung 				ATW_DPRINTF(("\n\t"));
    462        1.1   dyoung 			}
    463       1.15   dyoung 			ATW_DPRINTF((" 0x%x", sc->sc_srom[i]));
    464        1.1   dyoung 		}
    465       1.15   dyoung 		ATW_DPRINTF(("\n"));
    466        1.1   dyoung 	}
    467        1.1   dyoung #endif /* ATW_DEBUG */
    468        1.1   dyoung 	return 0;
    469        1.1   dyoung }
    470        1.1   dyoung 
    471        1.1   dyoung #ifdef ATW_DEBUG
    472        1.1   dyoung static void
    473        1.1   dyoung atw_print_regs(struct atw_softc *sc, const char *where)
    474        1.1   dyoung {
    475        1.1   dyoung #define PRINTREG(sc, reg) \
    476        1.1   dyoung 	ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \
    477        1.1   dyoung 	    sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg)))
    478        1.1   dyoung 
    479        1.1   dyoung 	ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where));
    480        1.1   dyoung 
    481        1.1   dyoung 	PRINTREG(sc, ATW_PAR);
    482        1.1   dyoung 	PRINTREG(sc, ATW_FRCTL);
    483        1.1   dyoung 	PRINTREG(sc, ATW_TDR);
    484        1.1   dyoung 	PRINTREG(sc, ATW_WTDP);
    485        1.1   dyoung 	PRINTREG(sc, ATW_RDR);
    486        1.1   dyoung 	PRINTREG(sc, ATW_WRDP);
    487        1.1   dyoung 	PRINTREG(sc, ATW_RDB);
    488        1.1   dyoung 	PRINTREG(sc, ATW_CSR3A);
    489        1.1   dyoung 	PRINTREG(sc, ATW_TDBD);
    490        1.1   dyoung 	PRINTREG(sc, ATW_TDBP);
    491        1.1   dyoung 	PRINTREG(sc, ATW_STSR);
    492        1.1   dyoung 	PRINTREG(sc, ATW_CSR5A);
    493        1.1   dyoung 	PRINTREG(sc, ATW_NAR);
    494        1.1   dyoung 	PRINTREG(sc, ATW_CSR6A);
    495        1.1   dyoung 	PRINTREG(sc, ATW_IER);
    496        1.1   dyoung 	PRINTREG(sc, ATW_CSR7A);
    497        1.1   dyoung 	PRINTREG(sc, ATW_LPC);
    498        1.1   dyoung 	PRINTREG(sc, ATW_TEST1);
    499        1.1   dyoung 	PRINTREG(sc, ATW_SPR);
    500        1.1   dyoung 	PRINTREG(sc, ATW_TEST0);
    501        1.1   dyoung 	PRINTREG(sc, ATW_WCSR);
    502        1.1   dyoung 	PRINTREG(sc, ATW_WPDR);
    503        1.1   dyoung 	PRINTREG(sc, ATW_GPTMR);
    504        1.1   dyoung 	PRINTREG(sc, ATW_GPIO);
    505        1.1   dyoung 	PRINTREG(sc, ATW_BBPCTL);
    506        1.1   dyoung 	PRINTREG(sc, ATW_SYNCTL);
    507        1.1   dyoung 	PRINTREG(sc, ATW_PLCPHD);
    508        1.1   dyoung 	PRINTREG(sc, ATW_MMIWADDR);
    509        1.1   dyoung 	PRINTREG(sc, ATW_MMIRADDR1);
    510        1.1   dyoung 	PRINTREG(sc, ATW_MMIRADDR2);
    511        1.1   dyoung 	PRINTREG(sc, ATW_TXBR);
    512        1.1   dyoung 	PRINTREG(sc, ATW_CSR15A);
    513        1.1   dyoung 	PRINTREG(sc, ATW_ALCSTAT);
    514        1.1   dyoung 	PRINTREG(sc, ATW_TOFS2);
    515        1.1   dyoung 	PRINTREG(sc, ATW_CMDR);
    516        1.1   dyoung 	PRINTREG(sc, ATW_PCIC);
    517        1.1   dyoung 	PRINTREG(sc, ATW_PMCSR);
    518        1.1   dyoung 	PRINTREG(sc, ATW_PAR0);
    519        1.1   dyoung 	PRINTREG(sc, ATW_PAR1);
    520        1.1   dyoung 	PRINTREG(sc, ATW_MAR0);
    521        1.1   dyoung 	PRINTREG(sc, ATW_MAR1);
    522        1.1   dyoung 	PRINTREG(sc, ATW_ATIMDA0);
    523        1.1   dyoung 	PRINTREG(sc, ATW_ABDA1);
    524        1.1   dyoung 	PRINTREG(sc, ATW_BSSID0);
    525        1.1   dyoung 	PRINTREG(sc, ATW_TXLMT);
    526        1.1   dyoung 	PRINTREG(sc, ATW_MIBCNT);
    527        1.1   dyoung 	PRINTREG(sc, ATW_BCNT);
    528        1.1   dyoung 	PRINTREG(sc, ATW_TSFTH);
    529        1.1   dyoung 	PRINTREG(sc, ATW_TSC);
    530        1.1   dyoung 	PRINTREG(sc, ATW_SYNRF);
    531        1.1   dyoung 	PRINTREG(sc, ATW_BPLI);
    532        1.1   dyoung 	PRINTREG(sc, ATW_CAP0);
    533        1.1   dyoung 	PRINTREG(sc, ATW_CAP1);
    534        1.1   dyoung 	PRINTREG(sc, ATW_RMD);
    535        1.1   dyoung 	PRINTREG(sc, ATW_CFPP);
    536        1.1   dyoung 	PRINTREG(sc, ATW_TOFS0);
    537        1.1   dyoung 	PRINTREG(sc, ATW_TOFS1);
    538        1.1   dyoung 	PRINTREG(sc, ATW_IFST);
    539        1.1   dyoung 	PRINTREG(sc, ATW_RSPT);
    540        1.1   dyoung 	PRINTREG(sc, ATW_TSFTL);
    541        1.1   dyoung 	PRINTREG(sc, ATW_WEPCTL);
    542        1.1   dyoung 	PRINTREG(sc, ATW_WESK);
    543        1.1   dyoung 	PRINTREG(sc, ATW_WEPCNT);
    544        1.1   dyoung 	PRINTREG(sc, ATW_MACTEST);
    545        1.1   dyoung 	PRINTREG(sc, ATW_FER);
    546        1.1   dyoung 	PRINTREG(sc, ATW_FEMR);
    547        1.1   dyoung 	PRINTREG(sc, ATW_FPSR);
    548        1.1   dyoung 	PRINTREG(sc, ATW_FFER);
    549        1.1   dyoung #undef PRINTREG
    550        1.1   dyoung }
    551        1.1   dyoung #endif /* ATW_DEBUG */
    552        1.1   dyoung 
    553        1.1   dyoung /*
    554        1.1   dyoung  * Finish attaching an ADMtek ADM8211 MAC.  Called by bus-specific front-end.
    555        1.1   dyoung  */
    556        1.1   dyoung void
    557        1.1   dyoung atw_attach(struct atw_softc *sc)
    558        1.1   dyoung {
    559       1.14   dyoung 	static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
    560       1.14   dyoung 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00
    561       1.14   dyoung 	};
    562        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
    563       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
    564       1.69   dyoung 	int country_code, error, i, nrate, srom_major;
    565        1.1   dyoung 	u_int32_t reg;
    566        1.1   dyoung 	static const char *type_strings[] = {"Intersil (not supported)",
    567        1.1   dyoung 	    "RFMD", "Marvel (not supported)"};
    568        1.1   dyoung 
    569        1.1   dyoung 	sc->sc_txth = atw_txthresh_tab_lo;
    570        1.1   dyoung 
    571        1.1   dyoung 	SIMPLEQ_INIT(&sc->sc_txfreeq);
    572        1.1   dyoung 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
    573        1.1   dyoung 
    574        1.1   dyoung #ifdef ATW_DEBUG
    575        1.1   dyoung 	atw_print_regs(sc, "atw_attach");
    576        1.1   dyoung #endif /* ATW_DEBUG */
    577        1.1   dyoung 
    578        1.1   dyoung 	/*
    579        1.1   dyoung 	 * Allocate the control data structures, and create and load the
    580        1.1   dyoung 	 * DMA map for it.
    581        1.1   dyoung 	 */
    582        1.1   dyoung 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    583        1.1   dyoung 	    sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
    584        1.1   dyoung 	    1, &sc->sc_cdnseg, 0)) != 0) {
    585        1.1   dyoung 		printf("%s: unable to allocate control data, error = %d\n",
    586        1.1   dyoung 		    sc->sc_dev.dv_xname, error);
    587        1.1   dyoung 		goto fail_0;
    588        1.1   dyoung 	}
    589        1.1   dyoung 
    590        1.1   dyoung 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg,
    591        1.1   dyoung 	    sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data,
    592        1.1   dyoung 	    BUS_DMA_COHERENT)) != 0) {
    593        1.1   dyoung 		printf("%s: unable to map control data, error = %d\n",
    594        1.1   dyoung 		    sc->sc_dev.dv_xname, error);
    595        1.1   dyoung 		goto fail_1;
    596        1.1   dyoung 	}
    597        1.1   dyoung 
    598        1.1   dyoung 	if ((error = bus_dmamap_create(sc->sc_dmat,
    599        1.1   dyoung 	    sizeof(struct atw_control_data), 1,
    600        1.1   dyoung 	    sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
    601        1.1   dyoung 		printf("%s: unable to create control data DMA map, "
    602        1.1   dyoung 		    "error = %d\n", sc->sc_dev.dv_xname, error);
    603        1.1   dyoung 		goto fail_2;
    604        1.1   dyoung 	}
    605        1.1   dyoung 
    606        1.1   dyoung 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
    607        1.1   dyoung 	    sc->sc_control_data, sizeof(struct atw_control_data), NULL,
    608        1.1   dyoung 	    0)) != 0) {
    609        1.1   dyoung 		printf("%s: unable to load control data DMA map, error = %d\n",
    610        1.1   dyoung 		    sc->sc_dev.dv_xname, error);
    611        1.1   dyoung 		goto fail_3;
    612        1.1   dyoung 	}
    613        1.1   dyoung 
    614        1.1   dyoung 	/*
    615        1.1   dyoung 	 * Create the transmit buffer DMA maps.
    616        1.1   dyoung 	 */
    617        1.1   dyoung 	sc->sc_ntxsegs = ATW_NTXSEGS;
    618        1.1   dyoung 	for (i = 0; i < ATW_TXQUEUELEN; i++) {
    619        1.1   dyoung 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
    620        1.1   dyoung 		    sc->sc_ntxsegs, MCLBYTES, 0, 0,
    621        1.1   dyoung 		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
    622        1.1   dyoung 			printf("%s: unable to create tx DMA map %d, "
    623        1.1   dyoung 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
    624        1.1   dyoung 			goto fail_4;
    625        1.1   dyoung 		}
    626        1.1   dyoung 	}
    627        1.1   dyoung 
    628        1.1   dyoung 	/*
    629        1.1   dyoung 	 * Create the receive buffer DMA maps.
    630        1.1   dyoung 	 */
    631        1.1   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
    632        1.1   dyoung 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
    633        1.1   dyoung 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
    634        1.1   dyoung 			printf("%s: unable to create rx DMA map %d, "
    635        1.1   dyoung 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
    636        1.1   dyoung 			goto fail_5;
    637        1.1   dyoung 		}
    638       1.14   dyoung 	}
    639       1.14   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
    640        1.1   dyoung 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
    641        1.1   dyoung 	}
    642        1.1   dyoung 
    643       1.69   dyoung 	switch (sc->sc_rev) {
    644       1.69   dyoung 	case ATW_REVISION_AB:
    645       1.69   dyoung 	case ATW_REVISION_AF:
    646       1.69   dyoung 		sc->sc_sramlen = ATW_SRAM_A_SIZE;
    647       1.69   dyoung 		break;
    648       1.69   dyoung 	case ATW_REVISION_BA:
    649       1.69   dyoung 	case ATW_REVISION_CA:
    650       1.69   dyoung 		sc->sc_sramlen = ATW_SRAM_B_SIZE;
    651       1.69   dyoung 		break;
    652       1.69   dyoung 	}
    653       1.69   dyoung 
    654        1.1   dyoung 	/* Reset the chip to a known state. */
    655        1.1   dyoung 	atw_reset(sc);
    656        1.1   dyoung 
    657        1.1   dyoung 	if (atw_read_srom(sc) == -1)
    658        1.1   dyoung 		return;
    659        1.1   dyoung 
    660  1.105.6.1   simonb 	sc->sc_rftype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
    661        1.1   dyoung 	    ATW_SR_RFTYPE_MASK);
    662        1.1   dyoung 
    663  1.105.6.1   simonb 	sc->sc_bbptype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
    664        1.1   dyoung 	    ATW_SR_BBPTYPE_MASK);
    665        1.1   dyoung 
    666  1.105.6.1   simonb 	if (sc->sc_rftype >= __arraycount(type_strings)) {
    667        1.1   dyoung 		printf("%s: unknown RF\n", sc->sc_dev.dv_xname);
    668        1.1   dyoung 		return;
    669        1.1   dyoung 	}
    670  1.105.6.1   simonb 	if (sc->sc_bbptype >= __arraycount(type_strings)) {
    671        1.1   dyoung 		printf("%s: unknown BBP\n", sc->sc_dev.dv_xname);
    672        1.1   dyoung 		return;
    673        1.1   dyoung 	}
    674        1.1   dyoung 
    675        1.1   dyoung 	printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname,
    676        1.1   dyoung 	    type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]);
    677        1.1   dyoung 
    678        1.1   dyoung 	/* XXX There exists a Linux driver which seems to use RFType = 0 for
    679        1.1   dyoung 	 * MARVEL. My bug, or theirs?
    680        1.1   dyoung 	 */
    681        1.1   dyoung 
    682  1.105.6.1   simonb 	reg = SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
    683        1.1   dyoung 
    684        1.1   dyoung 	switch (sc->sc_rftype) {
    685        1.1   dyoung 	case ATW_RFTYPE_INTERSIL:
    686        1.1   dyoung 		reg |= ATW_SYNCTL_CS1;
    687        1.1   dyoung 		break;
    688        1.1   dyoung 	case ATW_RFTYPE_RFMD:
    689        1.1   dyoung 		reg |= ATW_SYNCTL_CS0;
    690        1.1   dyoung 		break;
    691        1.1   dyoung 	case ATW_RFTYPE_MARVEL:
    692        1.1   dyoung 		break;
    693        1.1   dyoung 	}
    694        1.1   dyoung 
    695        1.1   dyoung 	sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
    696        1.1   dyoung 	sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
    697        1.1   dyoung 
    698  1.105.6.1   simonb 	reg = SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
    699        1.1   dyoung 
    700        1.1   dyoung 	switch (sc->sc_bbptype) {
    701       1.33   dyoung 	case ATW_BBPTYPE_INTERSIL:
    702        1.1   dyoung 		reg |= ATW_BBPCTL_TWI;
    703        1.1   dyoung 		break;
    704       1.33   dyoung 	case ATW_BBPTYPE_RFMD:
    705        1.1   dyoung 		reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |
    706        1.1   dyoung 		    ATW_BBPCTL_CCA_ACTLO;
    707        1.1   dyoung 		break;
    708       1.33   dyoung 	case ATW_BBPTYPE_MARVEL:
    709        1.1   dyoung 		break;
    710       1.35   dyoung 	case ATW_C_BBPTYPE_RFMD:
    711       1.35   dyoung 		printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n",
    712       1.35   dyoung 		    sc->sc_dev.dv_xname);
    713       1.35   dyoung 		break;
    714        1.1   dyoung 	}
    715        1.1   dyoung 
    716        1.1   dyoung 	sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;
    717        1.1   dyoung 	sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;
    718        1.1   dyoung 
    719        1.1   dyoung 	/*
    720        1.1   dyoung 	 * From this point forward, the attachment cannot fail.  A failure
    721        1.1   dyoung 	 * before this point releases all resources that may have been
    722        1.1   dyoung 	 * allocated.
    723        1.1   dyoung 	 */
    724        1.1   dyoung 	sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */;
    725        1.1   dyoung 
    726       1.15   dyoung 	ATW_DPRINTF((" SROM MAC %04x%04x%04x",
    727        1.1   dyoung 	    htole16(sc->sc_srom[ATW_SR_MAC00]),
    728        1.1   dyoung 	    htole16(sc->sc_srom[ATW_SR_MAC01]),
    729        1.1   dyoung 	    htole16(sc->sc_srom[ATW_SR_MAC10])));
    730        1.1   dyoung 
    731  1.105.6.1   simonb 	srom_major = SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION],
    732       1.69   dyoung 	    ATW_SR_MAJOR_MASK);
    733       1.69   dyoung 
    734       1.69   dyoung 	if (srom_major < 2)
    735       1.69   dyoung 		sc->sc_rf3000_options1 = 0;
    736       1.69   dyoung 	else if (sc->sc_rev == ATW_REVISION_BA) {
    737       1.69   dyoung 		sc->sc_rf3000_options1 =
    738  1.105.6.1   simonb 		    SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03],
    739       1.69   dyoung 		    ATW_SR_CR28_MASK);
    740       1.69   dyoung 	} else
    741       1.69   dyoung 		sc->sc_rf3000_options1 = 0;
    742       1.69   dyoung 
    743  1.105.6.1   simonb 	sc->sc_rf3000_options2 = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
    744       1.69   dyoung 	    ATW_SR_CR29_MASK);
    745       1.69   dyoung 
    746  1.105.6.1   simonb 	country_code = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
    747        1.1   dyoung 	    ATW_SR_CTRY_MASK);
    748        1.1   dyoung 
    749        1.3   dyoung #define ADD_CHANNEL(_ic, _chan) do {					\
    750        1.3   dyoung 	_ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B;		\
    751        1.3   dyoung 	_ic->ic_channels[_chan].ic_freq =				\
    752        1.3   dyoung 	    ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\
    753        1.3   dyoung } while (0)
    754        1.3   dyoung 
    755        1.1   dyoung 	/* Find available channels */
    756        1.1   dyoung 	switch (country_code) {
    757        1.1   dyoung 	case COUNTRY_MMK2:	/* 1-14 */
    758        1.3   dyoung 		ADD_CHANNEL(ic, 14);
    759        1.2   dyoung 		/*FALLTHROUGH*/
    760        1.1   dyoung 	case COUNTRY_ETSI:	/* 1-13 */
    761        1.1   dyoung 		for (i = 1; i <= 13; i++)
    762        1.3   dyoung 			ADD_CHANNEL(ic, i);
    763        1.1   dyoung 		break;
    764        1.1   dyoung 	case COUNTRY_FCC:	/* 1-11 */
    765        1.1   dyoung 	case COUNTRY_IC:	/* 1-11 */
    766        1.1   dyoung 		for (i = 1; i <= 11; i++)
    767        1.3   dyoung 			ADD_CHANNEL(ic, i);
    768        1.1   dyoung 		break;
    769        1.1   dyoung 	case COUNTRY_MMK:	/* 14 */
    770        1.3   dyoung 		ADD_CHANNEL(ic, 14);
    771        1.1   dyoung 		break;
    772        1.1   dyoung 	case COUNTRY_FRANCE:	/* 10-13 */
    773        1.1   dyoung 		for (i = 10; i <= 13; i++)
    774        1.3   dyoung 			ADD_CHANNEL(ic, i);
    775        1.1   dyoung 		break;
    776        1.1   dyoung 	default:	/* assume channels 10-11 */
    777        1.1   dyoung 	case COUNTRY_SPAIN:	/* 10-11 */
    778        1.1   dyoung 		for (i = 10; i <= 11; i++)
    779        1.3   dyoung 			ADD_CHANNEL(ic, i);
    780        1.1   dyoung 		break;
    781        1.1   dyoung 	}
    782        1.1   dyoung 
    783        1.1   dyoung 	/* Read the MAC address. */
    784        1.1   dyoung 	reg = ATW_READ(sc, ATW_PAR0);
    785  1.105.6.1   simonb 	ic->ic_myaddr[0] = SHIFTOUT(reg, ATW_PAR0_PAB0_MASK);
    786  1.105.6.1   simonb 	ic->ic_myaddr[1] = SHIFTOUT(reg, ATW_PAR0_PAB1_MASK);
    787  1.105.6.1   simonb 	ic->ic_myaddr[2] = SHIFTOUT(reg, ATW_PAR0_PAB2_MASK);
    788  1.105.6.1   simonb 	ic->ic_myaddr[3] = SHIFTOUT(reg, ATW_PAR0_PAB3_MASK);
    789        1.1   dyoung 	reg = ATW_READ(sc, ATW_PAR1);
    790  1.105.6.1   simonb 	ic->ic_myaddr[4] = SHIFTOUT(reg, ATW_PAR1_PAB4_MASK);
    791  1.105.6.1   simonb 	ic->ic_myaddr[5] = SHIFTOUT(reg, ATW_PAR1_PAB5_MASK);
    792        1.1   dyoung 
    793        1.1   dyoung 	if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) {
    794        1.1   dyoung 		printf(" could not get mac address, attach failed\n");
    795        1.1   dyoung 		return;
    796        1.1   dyoung 	}
    797        1.1   dyoung 
    798        1.1   dyoung 	printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr));
    799        1.1   dyoung 
    800        1.1   dyoung 	memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
    801        1.1   dyoung 	ifp->if_softc = sc;
    802        1.1   dyoung 	ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST |
    803        1.1   dyoung 	    IFF_NOTRAILERS;
    804        1.1   dyoung 	ifp->if_ioctl = atw_ioctl;
    805        1.1   dyoung 	ifp->if_start = atw_start;
    806        1.1   dyoung 	ifp->if_watchdog = atw_watchdog;
    807        1.1   dyoung 	ifp->if_init = atw_init;
    808        1.1   dyoung 	ifp->if_stop = atw_stop;
    809        1.1   dyoung 	IFQ_SET_READY(&ifp->if_snd);
    810        1.1   dyoung 
    811       1.85   dyoung 	ic->ic_ifp = ifp;
    812        1.1   dyoung 	ic->ic_phytype = IEEE80211_T_DS;
    813        1.1   dyoung 	ic->ic_opmode = IEEE80211_M_STA;
    814        1.3   dyoung 	ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS |
    815       1.85   dyoung 	    IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR;
    816        1.1   dyoung 
    817        1.1   dyoung 	nrate = 0;
    818        1.3   dyoung 	ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2;
    819        1.3   dyoung 	ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4;
    820        1.3   dyoung 	ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11;
    821        1.3   dyoung 	ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22;
    822        1.3   dyoung 	ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate;
    823        1.1   dyoung 
    824        1.1   dyoung 	/*
    825        1.1   dyoung 	 * Call MI attach routines.
    826        1.1   dyoung 	 */
    827        1.1   dyoung 
    828        1.1   dyoung 	if_attach(ifp);
    829       1.85   dyoung 	ieee80211_ifattach(ic);
    830        1.1   dyoung 
    831        1.3   dyoung 	sc->sc_newstate = ic->ic_newstate;
    832        1.3   dyoung 	ic->ic_newstate = atw_newstate;
    833        1.1   dyoung 
    834        1.3   dyoung 	sc->sc_recv_mgmt = ic->ic_recv_mgmt;
    835        1.3   dyoung 	ic->ic_recv_mgmt = atw_recv_mgmt;
    836        1.1   dyoung 
    837        1.3   dyoung 	sc->sc_node_free = ic->ic_node_free;
    838        1.3   dyoung 	ic->ic_node_free = atw_node_free;
    839        1.3   dyoung 
    840        1.3   dyoung 	sc->sc_node_alloc = ic->ic_node_alloc;
    841        1.3   dyoung 	ic->ic_node_alloc = atw_node_alloc;
    842        1.1   dyoung 
    843       1.85   dyoung 	ic->ic_crypto.cs_key_delete = atw_key_delete;
    844       1.85   dyoung 	ic->ic_crypto.cs_key_set = atw_key_set;
    845       1.85   dyoung 	ic->ic_crypto.cs_key_update_begin = atw_key_update_begin;
    846       1.85   dyoung 	ic->ic_crypto.cs_key_update_end = atw_key_update_end;
    847       1.85   dyoung 
    848        1.1   dyoung 	/* possibly we should fill in our own sc_send_prresp, since
    849        1.1   dyoung 	 * the ADM8211 is probably sending probe responses in ad hoc
    850        1.1   dyoung 	 * mode.
    851        1.1   dyoung 	 */
    852        1.1   dyoung 
    853        1.3   dyoung 	/* complete initialization */
    854       1.96   dyoung 	ieee80211_media_init(ic, atw_media_change, ieee80211_media_status);
    855        1.3   dyoung 	callout_init(&sc->sc_scan_ch);
    856        1.3   dyoung 
    857        1.1   dyoung #if NBPFILTER > 0
    858       1.12   dyoung 	bpfattach2(ifp, DLT_IEEE802_11_RADIO,
    859       1.12   dyoung 	    sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
    860        1.1   dyoung #endif
    861        1.1   dyoung 
    862        1.1   dyoung 	/*
    863        1.1   dyoung 	 * Make sure the interface is shutdown during reboot.
    864        1.1   dyoung 	 */
    865        1.1   dyoung 	sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc);
    866        1.1   dyoung 	if (sc->sc_sdhook == NULL)
    867        1.1   dyoung 		printf("%s: WARNING: unable to establish shutdown hook\n",
    868        1.1   dyoung 		    sc->sc_dev.dv_xname);
    869        1.1   dyoung 
    870        1.1   dyoung 	/*
    871        1.1   dyoung 	 * Add a suspend hook to make sure we come back up after a
    872        1.1   dyoung 	 * resume.
    873        1.1   dyoung 	 */
    874        1.1   dyoung 	sc->sc_powerhook = powerhook_establish(atw_power, sc);
    875        1.1   dyoung 	if (sc->sc_powerhook == NULL)
    876        1.1   dyoung 		printf("%s: WARNING: unable to establish power hook\n",
    877        1.1   dyoung 		    sc->sc_dev.dv_xname);
    878        1.1   dyoung 
    879       1.12   dyoung 	memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu));
    880  1.105.6.1   simonb 	sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
    881  1.105.6.1   simonb 	sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT);
    882       1.12   dyoung 
    883       1.12   dyoung 	memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu));
    884  1.105.6.1   simonb 	sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
    885  1.105.6.1   simonb 	sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT);
    886       1.12   dyoung 
    887       1.88   dyoung 	ieee80211_announce(ic);
    888        1.1   dyoung 	return;
    889        1.1   dyoung 
    890        1.1   dyoung 	/*
    891        1.1   dyoung 	 * Free any resources we've allocated during the failed attach
    892        1.1   dyoung 	 * attempt.  Do this in reverse order and fall through.
    893        1.1   dyoung 	 */
    894        1.1   dyoung  fail_5:
    895        1.1   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
    896        1.1   dyoung 		if (sc->sc_rxsoft[i].rxs_dmamap == NULL)
    897        1.1   dyoung 			continue;
    898        1.1   dyoung 		bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap);
    899        1.1   dyoung 	}
    900        1.1   dyoung  fail_4:
    901        1.1   dyoung 	for (i = 0; i < ATW_TXQUEUELEN; i++) {
    902        1.1   dyoung 		if (sc->sc_txsoft[i].txs_dmamap == NULL)
    903        1.1   dyoung 			continue;
    904        1.1   dyoung 		bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap);
    905        1.1   dyoung 	}
    906        1.1   dyoung 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
    907        1.1   dyoung  fail_3:
    908        1.1   dyoung 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
    909        1.1   dyoung  fail_2:
    910        1.1   dyoung 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
    911        1.1   dyoung 	    sizeof(struct atw_control_data));
    912        1.1   dyoung  fail_1:
    913        1.1   dyoung 	bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
    914        1.1   dyoung  fail_0:
    915        1.1   dyoung 	return;
    916        1.1   dyoung }
    917        1.1   dyoung 
    918        1.3   dyoung static struct ieee80211_node *
    919       1.85   dyoung atw_node_alloc(struct ieee80211_node_table *nt)
    920        1.3   dyoung {
    921       1.85   dyoung 	struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc;
    922       1.85   dyoung 	struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt);
    923        1.3   dyoung 
    924        1.3   dyoung 	DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
    925        1.3   dyoung 	return ni;
    926        1.3   dyoung }
    927        1.3   dyoung 
    928        1.3   dyoung static void
    929       1.85   dyoung atw_node_free(struct ieee80211_node *ni)
    930        1.3   dyoung {
    931       1.85   dyoung 	struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc;
    932        1.3   dyoung 
    933        1.3   dyoung 	DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
    934        1.3   dyoung 	    ether_sprintf(ni->ni_bssid)));
    935       1.85   dyoung 	(*sc->sc_node_free)(ni);
    936        1.3   dyoung }
    937        1.3   dyoung 
    938       1.69   dyoung 
    939       1.69   dyoung static void
    940       1.69   dyoung atw_test1_reset(struct atw_softc *sc)
    941       1.69   dyoung {
    942       1.69   dyoung 	switch (sc->sc_rev) {
    943       1.69   dyoung 	case ATW_REVISION_BA:
    944       1.69   dyoung 		if (1 /* XXX condition on transceiver type */) {
    945       1.69   dyoung 			ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR);
    946       1.69   dyoung 		}
    947       1.69   dyoung 		break;
    948       1.69   dyoung 	case ATW_REVISION_CA:
    949       1.69   dyoung 		ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK);
    950       1.69   dyoung 		break;
    951       1.69   dyoung 	default:
    952       1.69   dyoung 		break;
    953       1.69   dyoung 	}
    954       1.69   dyoung }
    955       1.69   dyoung 
    956        1.1   dyoung /*
    957        1.1   dyoung  * atw_reset:
    958        1.1   dyoung  *
    959        1.1   dyoung  *	Perform a soft reset on the ADM8211.
    960        1.1   dyoung  */
    961        1.1   dyoung void
    962       1.23   dyoung atw_reset(struct atw_softc *sc)
    963        1.1   dyoung {
    964        1.1   dyoung 	int i;
    965       1.63   dyoung 	uint32_t lpc;
    966       1.63   dyoung 
    967       1.63   dyoung 	ATW_WRITE(sc, ATW_NAR, 0x0);
    968       1.70   dyoung 	DELAY(atw_nar_delay);
    969       1.63   dyoung 
    970       1.63   dyoung 	/* Reference driver has a cryptic remark indicating that this might
    971       1.63   dyoung 	 * power-on the chip.  I know that it turns off power-saving....
    972       1.63   dyoung 	 */
    973       1.63   dyoung 	ATW_WRITE(sc, ATW_FRCTL, 0x0);
    974        1.1   dyoung 
    975        1.1   dyoung 	ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR);
    976        1.1   dyoung 
    977       1.70   dyoung 	for (i = 0; i < 50000 / atw_pseudo_milli; i++) {
    978      1.100   dyoung 		if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0)
    979        1.1   dyoung 			break;
    980       1.70   dyoung 		DELAY(atw_pseudo_milli);
    981        1.1   dyoung 	}
    982        1.1   dyoung 
    983       1.63   dyoung 	/* ... and then pause 100ms longer for good measure. */
    984       1.70   dyoung 	DELAY(atw_magic_delay1);
    985       1.63   dyoung 
    986        1.1   dyoung 	DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i));
    987        1.1   dyoung 
    988        1.1   dyoung 	if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR))
    989        1.1   dyoung 		printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
    990        1.1   dyoung 
    991       1.63   dyoung 	/*
    992       1.63   dyoung 	 * Initialize the PCI Access Register.
    993       1.63   dyoung 	 */
    994       1.63   dyoung 	sc->sc_busmode = ATW_PAR_PBL_8DW;
    995       1.63   dyoung 
    996       1.63   dyoung 	ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
    997       1.63   dyoung 	DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname,
    998       1.63   dyoung 	    ATW_READ(sc, ATW_PAR), sc->sc_busmode));
    999       1.63   dyoung 
   1000      1.100   dyoung 	atw_test1_reset(sc);
   1001      1.100   dyoung 
   1002      1.100   dyoung 	/* Turn off maximum power saving, etc. */
   1003       1.63   dyoung 	ATW_WRITE(sc, ATW_FRCTL, 0x0);
   1004       1.63   dyoung 
   1005       1.70   dyoung 	DELAY(atw_magic_delay2);
   1006        1.1   dyoung 
   1007        1.1   dyoung 	/* Recall EEPROM. */
   1008        1.1   dyoung 	ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD);
   1009        1.1   dyoung 
   1010       1.70   dyoung 	DELAY(atw_magic_delay4);
   1011        1.1   dyoung 
   1012       1.63   dyoung 	lpc = ATW_READ(sc, ATW_LPC);
   1013       1.63   dyoung 
   1014       1.63   dyoung 	DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc));
   1015       1.63   dyoung 
   1016        1.1   dyoung 	/* A reset seems to affect the SRAM contents, so put them into
   1017        1.1   dyoung 	 * a known state.
   1018        1.1   dyoung 	 */
   1019        1.1   dyoung 	atw_clear_sram(sc);
   1020        1.1   dyoung 
   1021       1.63   dyoung 	memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid));
   1022        1.1   dyoung }
   1023        1.1   dyoung 
   1024        1.1   dyoung static void
   1025       1.23   dyoung atw_clear_sram(struct atw_softc *sc)
   1026        1.1   dyoung {
   1027        1.1   dyoung 	memset(sc->sc_sram, 0, sizeof(sc->sc_sram));
   1028       1.85   dyoung 	sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
   1029        1.1   dyoung 	/* XXX not for revision 0x20. */
   1030       1.69   dyoung 	atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen);
   1031        1.1   dyoung }
   1032        1.1   dyoung 
   1033        1.1   dyoung /* TBD atw_init
   1034        1.1   dyoung  *
   1035        1.3   dyoung  * set MAC based on ic->ic_bss->myaddr
   1036        1.1   dyoung  * write WEP keys
   1037        1.1   dyoung  * set TX rate
   1038        1.1   dyoung  */
   1039        1.1   dyoung 
   1040       1.64   dyoung /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass
   1041       1.64   dyoung  * without receiving a beacon with the preferred BSSID & SSID.
   1042       1.64   dyoung  * atw_write_bssid & atw_write_ssid set the BSSID & SSID.
   1043        1.1   dyoung  */
   1044       1.64   dyoung static void
   1045       1.64   dyoung atw_wcsr_init(struct atw_softc *sc)
   1046        1.1   dyoung {
   1047       1.64   dyoung 	uint32_t wcsr;
   1048        1.1   dyoung 
   1049       1.64   dyoung 	wcsr = ATW_READ(sc, ATW_WCSR);
   1050       1.64   dyoung 	wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
   1051  1.105.6.1   simonb 	wcsr |= SHIFTIN(7, ATW_WCSR_BLN_MASK);
   1052       1.64   dyoung 	ATW_WRITE(sc, ATW_WCSR, wcsr);	/* XXX resets wake-up status bits */
   1053        1.1   dyoung 
   1054       1.64   dyoung 	DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n",
   1055       1.64   dyoung 	    sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR)));
   1056       1.64   dyoung }
   1057        1.1   dyoung 
   1058       1.64   dyoung /* Turn off power management.  Set Rx store-and-forward mode. */
   1059       1.64   dyoung static void
   1060       1.64   dyoung atw_cmdr_init(struct atw_softc *sc)
   1061       1.64   dyoung {
   1062       1.64   dyoung 	uint32_t cmdr;
   1063       1.64   dyoung 	cmdr = ATW_READ(sc, ATW_CMDR);
   1064       1.64   dyoung 	cmdr &= ~ATW_CMDR_APM;
   1065       1.64   dyoung 	cmdr |= ATW_CMDR_RTE;
   1066       1.64   dyoung 	cmdr &= ~ATW_CMDR_DRT_MASK;
   1067       1.64   dyoung 	cmdr |= ATW_CMDR_DRT_SF;
   1068        1.3   dyoung 
   1069       1.64   dyoung 	ATW_WRITE(sc, ATW_CMDR, cmdr);
   1070       1.64   dyoung }
   1071        1.1   dyoung 
   1072       1.64   dyoung static void
   1073       1.64   dyoung atw_tofs2_init(struct atw_softc *sc)
   1074       1.64   dyoung {
   1075       1.64   dyoung 	uint32_t tofs2;
   1076       1.14   dyoung 	/* XXX this magic can probably be figured out from the RFMD docs */
   1077       1.64   dyoung #ifndef ATW_REFSLAVE
   1078  1.105.6.1   simonb 	tofs2 = SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK)    | /* 8 ms = 4 * 2 ms */
   1079  1.105.6.1   simonb 	      SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
   1080  1.105.6.1   simonb 	      SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK)  | /* 8 us */
   1081  1.105.6.1   simonb 	      SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK)  | /* 5 us */
   1082  1.105.6.1   simonb 	      SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
   1083  1.105.6.1   simonb 	      SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK)  | /* 13 us */
   1084  1.105.6.1   simonb 	      SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK)   | /* 4 us */
   1085  1.105.6.1   simonb 	      SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK);  /* 5 us */
   1086       1.64   dyoung #else
   1087       1.64   dyoung 	/* XXX new magic from reference driver source */
   1088  1.105.6.1   simonb 	tofs2 = SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK)    | /* 8 ms = 4 * 2 ms */
   1089  1.105.6.1   simonb 	      SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */
   1090  1.105.6.1   simonb 	      SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK)  | /* 1 us */
   1091  1.105.6.1   simonb 	      SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK)  | /* 5 us */
   1092  1.105.6.1   simonb 	      SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
   1093  1.105.6.1   simonb 	      SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK)  | /* 13 us */
   1094  1.105.6.1   simonb 	      SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK)   | /* 1 us */
   1095  1.105.6.1   simonb 	      SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK);  /* 8 us */
   1096       1.64   dyoung #endif
   1097       1.64   dyoung 	ATW_WRITE(sc, ATW_TOFS2, tofs2);
   1098       1.64   dyoung }
   1099        1.1   dyoung 
   1100       1.64   dyoung static void
   1101       1.64   dyoung atw_nar_init(struct atw_softc *sc)
   1102       1.64   dyoung {
   1103       1.64   dyoung 	ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB);
   1104       1.64   dyoung }
   1105       1.64   dyoung 
   1106       1.64   dyoung static void
   1107       1.64   dyoung atw_txlmt_init(struct atw_softc *sc)
   1108       1.64   dyoung {
   1109  1.105.6.1   simonb 	ATW_WRITE(sc, ATW_TXLMT, SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) |
   1110  1.105.6.1   simonb 	                         SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK));
   1111       1.64   dyoung }
   1112        1.1   dyoung 
   1113       1.64   dyoung static void
   1114       1.64   dyoung atw_test1_init(struct atw_softc *sc)
   1115       1.64   dyoung {
   1116       1.64   dyoung 	uint32_t test1;
   1117       1.64   dyoung 
   1118       1.64   dyoung 	test1 = ATW_READ(sc, ATW_TEST1);
   1119       1.64   dyoung 	test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL);
   1120       1.64   dyoung 	/* XXX magic 0x1 */
   1121  1.105.6.1   simonb 	test1 |= SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
   1122       1.64   dyoung 	ATW_WRITE(sc, ATW_TEST1, test1);
   1123       1.64   dyoung }
   1124       1.64   dyoung 
   1125       1.64   dyoung static void
   1126       1.64   dyoung atw_rf_reset(struct atw_softc *sc)
   1127       1.64   dyoung {
   1128        1.1   dyoung 	/* XXX this resets an Intersil RF front-end? */
   1129        1.1   dyoung 	/* TBD condition on Intersil RFType? */
   1130        1.1   dyoung 	ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
   1131       1.70   dyoung 	DELAY(atw_rf_delay1);
   1132        1.1   dyoung 	ATW_WRITE(sc, ATW_SYNRF, 0);
   1133       1.70   dyoung 	DELAY(atw_rf_delay2);
   1134       1.64   dyoung }
   1135       1.64   dyoung 
   1136       1.64   dyoung /* Set 16 TU max duration for the contention-free period (CFP). */
   1137       1.64   dyoung static void
   1138       1.64   dyoung atw_cfp_init(struct atw_softc *sc)
   1139       1.64   dyoung {
   1140       1.64   dyoung 	uint32_t cfpp;
   1141        1.1   dyoung 
   1142       1.64   dyoung 	cfpp = ATW_READ(sc, ATW_CFPP);
   1143       1.64   dyoung 	cfpp &= ~ATW_CFPP_CFPMD;
   1144  1.105.6.1   simonb 	cfpp |= SHIFTIN(16, ATW_CFPP_CFPMD);
   1145       1.64   dyoung 	ATW_WRITE(sc, ATW_CFPP, cfpp);
   1146       1.64   dyoung }
   1147        1.1   dyoung 
   1148       1.64   dyoung static void
   1149       1.64   dyoung atw_tofs0_init(struct atw_softc *sc)
   1150       1.64   dyoung {
   1151  1.105.6.1   simonb 	/* XXX I guess that the Cardbus clock is 22 MHz?
   1152        1.1   dyoung 	 * I am assuming that the role of ATW_TOFS0_USCNT is
   1153  1.105.6.1   simonb 	 * to divide the bus clock to get a 1 MHz clock---the datasheet is not
   1154        1.1   dyoung 	 * very clear on this point. It says in the datasheet that it is
   1155  1.105.6.1   simonb 	 * possible for the ADM8211 to accomodate bus speeds between 22 MHz
   1156  1.105.6.1   simonb 	 * and 33 MHz; maybe this is the way? I see a binary-only driver write
   1157        1.1   dyoung 	 * these values. These values are also the power-on default.
   1158        1.1   dyoung 	 */
   1159        1.1   dyoung 	ATW_WRITE(sc, ATW_TOFS0,
   1160  1.105.6.1   simonb 	    SHIFTIN(22, ATW_TOFS0_USCNT_MASK) |
   1161        1.1   dyoung 	    ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
   1162       1.64   dyoung }
   1163        1.1   dyoung 
   1164       1.64   dyoung /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */
   1165       1.64   dyoung static void
   1166       1.64   dyoung atw_ifs_init(struct atw_softc *sc)
   1167       1.64   dyoung {
   1168       1.64   dyoung 	uint32_t ifst;
   1169       1.64   dyoung 	/* XXX EIFS=0x64, SIFS=110 are used by the reference driver.
   1170       1.64   dyoung 	 * Go figure.
   1171        1.1   dyoung 	 */
   1172  1.105.6.1   simonb 	ifst = SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
   1173  1.105.6.1   simonb 	      SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */,
   1174        1.1   dyoung 	             ATW_IFST_SIFS_MASK) |
   1175  1.105.6.1   simonb 	      SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
   1176  1.105.6.1   simonb 	      SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
   1177        1.1   dyoung 
   1178       1.64   dyoung 	ATW_WRITE(sc, ATW_IFST, ifst);
   1179       1.64   dyoung }
   1180        1.1   dyoung 
   1181       1.64   dyoung static void
   1182       1.64   dyoung atw_response_times_init(struct atw_softc *sc)
   1183       1.64   dyoung {
   1184       1.64   dyoung 	/* XXX More magic. Relates to ACK timing?  The datasheet seems to
   1185       1.64   dyoung 	 * indicate that the MAC expects at least SIFS + MIRT microseconds
   1186       1.64   dyoung 	 * to pass after it transmits a frame that requires a response;
   1187       1.64   dyoung 	 * it waits at most SIFS + MART microseconds for the response.
   1188       1.64   dyoung 	 * Surely this is not the ACK timeout?
   1189       1.64   dyoung 	 */
   1190  1.105.6.1   simonb 	ATW_WRITE(sc, ATW_RSPT, SHIFTIN(0xffff, ATW_RSPT_MART_MASK) |
   1191  1.105.6.1   simonb 	    SHIFTIN(0xff, ATW_RSPT_MIRT_MASK));
   1192       1.64   dyoung }
   1193        1.1   dyoung 
   1194       1.64   dyoung /* Set up the MMI read/write addresses for the baseband. The Tx/Rx
   1195       1.64   dyoung  * engines read and write baseband registers after Rx and before
   1196       1.64   dyoung  * Tx, respectively.
   1197       1.64   dyoung  */
   1198       1.64   dyoung static void
   1199       1.64   dyoung atw_bbp_io_init(struct atw_softc *sc)
   1200       1.64   dyoung {
   1201       1.69   dyoung 	uint32_t mmiraddr2;
   1202       1.69   dyoung 
   1203       1.69   dyoung 	/* XXX The reference driver does this, but is it *really*
   1204       1.69   dyoung 	 * necessary?
   1205       1.69   dyoung 	 */
   1206       1.69   dyoung 	switch (sc->sc_rev) {
   1207       1.69   dyoung 	case ATW_REVISION_AB:
   1208       1.69   dyoung 	case ATW_REVISION_AF:
   1209       1.69   dyoung 		mmiraddr2 = 0x0;
   1210       1.69   dyoung 		break;
   1211       1.69   dyoung 	default:
   1212       1.69   dyoung 		mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2);
   1213       1.69   dyoung 		mmiraddr2 &=
   1214       1.69   dyoung 		    ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK);
   1215       1.69   dyoung 		break;
   1216       1.69   dyoung 	}
   1217       1.69   dyoung 
   1218        1.1   dyoung 	switch (sc->sc_bbptype) {
   1219        1.1   dyoung 	case ATW_BBPTYPE_INTERSIL:
   1220        1.1   dyoung 		ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL);
   1221        1.1   dyoung 		ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL);
   1222       1.69   dyoung 		mmiraddr2 |= ATW_MMIRADDR2_INTERSIL;
   1223        1.1   dyoung 		break;
   1224        1.1   dyoung 	case ATW_BBPTYPE_MARVEL:
   1225       1.64   dyoung 		/* TBD find out the Marvel settings. */
   1226        1.1   dyoung 		break;
   1227        1.1   dyoung 	case ATW_BBPTYPE_RFMD:
   1228       1.64   dyoung 	default:
   1229        1.1   dyoung 		ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD);
   1230        1.1   dyoung 		ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD);
   1231       1.69   dyoung 		mmiraddr2 |= ATW_MMIRADDR2_RFMD;
   1232        1.1   dyoung 		break;
   1233        1.1   dyoung 	}
   1234       1.69   dyoung 	ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2);
   1235       1.64   dyoung 	ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK);
   1236       1.64   dyoung }
   1237        1.1   dyoung 
   1238       1.64   dyoung /*
   1239       1.64   dyoung  * atw_init:		[ ifnet interface function ]
   1240       1.64   dyoung  *
   1241       1.64   dyoung  *	Initialize the interface.  Must be called at splnet().
   1242       1.64   dyoung  */
   1243       1.64   dyoung int
   1244       1.64   dyoung atw_init(struct ifnet *ifp)
   1245       1.64   dyoung {
   1246       1.64   dyoung 	struct atw_softc *sc = ifp->if_softc;
   1247       1.64   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   1248       1.64   dyoung 	struct atw_txsoft *txs;
   1249       1.64   dyoung 	struct atw_rxsoft *rxs;
   1250       1.64   dyoung 	int i, error = 0;
   1251        1.1   dyoung 
   1252       1.64   dyoung 	if ((error = atw_enable(sc)) != 0)
   1253        1.1   dyoung 		goto out;
   1254        1.1   dyoung 
   1255        1.1   dyoung 	/*
   1256       1.64   dyoung 	 * Cancel any pending I/O. This also resets.
   1257        1.1   dyoung 	 */
   1258       1.64   dyoung 	atw_stop(ifp, 0);
   1259       1.64   dyoung 
   1260       1.64   dyoung 	DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n",
   1261       1.90    skrll 	    __func__, ieee80211_chan2ieee(ic, ic->ic_curchan),
   1262       1.90    skrll 	    ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
   1263        1.1   dyoung 
   1264       1.64   dyoung 	atw_wcsr_init(sc);
   1265       1.64   dyoung 
   1266       1.64   dyoung 	atw_cmdr_init(sc);
   1267       1.64   dyoung 
   1268       1.64   dyoung 	/* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s.
   1269        1.1   dyoung 	 *
   1270       1.64   dyoung 	 * XXX Set transmit power for ATIM, RTS, Beacon.
   1271        1.1   dyoung 	 */
   1272  1.105.6.1   simonb 	ATW_WRITE(sc, ATW_PLCPHD, SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) |
   1273  1.105.6.1   simonb 	    SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK));
   1274       1.64   dyoung 
   1275       1.64   dyoung 	atw_tofs2_init(sc);
   1276       1.64   dyoung 
   1277       1.64   dyoung 	atw_nar_init(sc);
   1278       1.64   dyoung 
   1279       1.64   dyoung 	atw_txlmt_init(sc);
   1280       1.64   dyoung 
   1281       1.64   dyoung 	atw_test1_init(sc);
   1282       1.64   dyoung 
   1283       1.64   dyoung 	atw_rf_reset(sc);
   1284       1.64   dyoung 
   1285       1.64   dyoung 	atw_cfp_init(sc);
   1286       1.64   dyoung 
   1287       1.64   dyoung 	atw_tofs0_init(sc);
   1288       1.64   dyoung 
   1289       1.64   dyoung 	atw_ifs_init(sc);
   1290       1.64   dyoung 
   1291       1.64   dyoung 	/* XXX Fall asleep after one second of inactivity.
   1292       1.64   dyoung 	 * XXX A frame may only dribble in for 65536us.
   1293       1.64   dyoung 	 */
   1294       1.64   dyoung 	ATW_WRITE(sc, ATW_RMD,
   1295  1.105.6.1   simonb 	    SHIFTIN(1, ATW_RMD_PCNT) | SHIFTIN(0xffff, ATW_RMD_RMRD_MASK));
   1296       1.64   dyoung 
   1297       1.64   dyoung 	atw_response_times_init(sc);
   1298       1.64   dyoung 
   1299       1.64   dyoung 	atw_bbp_io_init(sc);
   1300       1.64   dyoung 
   1301       1.64   dyoung 	ATW_WRITE(sc, ATW_STSR, 0xffffffff);
   1302        1.1   dyoung 
   1303       1.64   dyoung 	if ((error = atw_rf3000_init(sc)) != 0)
   1304       1.64   dyoung 		goto out;
   1305        1.1   dyoung 
   1306        1.1   dyoung 	ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
   1307        1.1   dyoung 	DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname,
   1308        1.1   dyoung 	    ATW_READ(sc, ATW_PAR), sc->sc_busmode));
   1309        1.1   dyoung 
   1310        1.1   dyoung 	/*
   1311        1.1   dyoung 	 * Initialize the transmit descriptor ring.
   1312        1.1   dyoung 	 */
   1313        1.1   dyoung 	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
   1314        1.1   dyoung 	for (i = 0; i < ATW_NTXDESC; i++) {
   1315       1.51   dyoung 		sc->sc_txdescs[i].at_ctl = 0;
   1316        1.1   dyoung 		/* no transmit chaining */
   1317       1.51   dyoung 		sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */;
   1318        1.1   dyoung 		sc->sc_txdescs[i].at_buf2 =
   1319        1.1   dyoung 		    htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i)));
   1320        1.1   dyoung 	}
   1321        1.1   dyoung 	/* use ring mode */
   1322       1.51   dyoung 	sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER);
   1323        1.1   dyoung 	ATW_CDTXSYNC(sc, 0, ATW_NTXDESC,
   1324        1.1   dyoung 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1325        1.1   dyoung 	sc->sc_txfree = ATW_NTXDESC;
   1326        1.1   dyoung 	sc->sc_txnext = 0;
   1327        1.1   dyoung 
   1328        1.1   dyoung 	/*
   1329        1.1   dyoung 	 * Initialize the transmit job descriptors.
   1330        1.1   dyoung 	 */
   1331        1.1   dyoung 	SIMPLEQ_INIT(&sc->sc_txfreeq);
   1332        1.1   dyoung 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
   1333        1.1   dyoung 	for (i = 0; i < ATW_TXQUEUELEN; i++) {
   1334        1.1   dyoung 		txs = &sc->sc_txsoft[i];
   1335        1.1   dyoung 		txs->txs_mbuf = NULL;
   1336        1.1   dyoung 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
   1337        1.1   dyoung 	}
   1338        1.1   dyoung 
   1339        1.1   dyoung 	/*
   1340        1.1   dyoung 	 * Initialize the receive descriptor and receive job
   1341        1.1   dyoung 	 * descriptor rings.
   1342        1.1   dyoung 	 */
   1343        1.1   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
   1344        1.1   dyoung 		rxs = &sc->sc_rxsoft[i];
   1345        1.1   dyoung 		if (rxs->rxs_mbuf == NULL) {
   1346        1.1   dyoung 			if ((error = atw_add_rxbuf(sc, i)) != 0) {
   1347        1.1   dyoung 				printf("%s: unable to allocate or map rx "
   1348        1.1   dyoung 				    "buffer %d, error = %d\n",
   1349        1.1   dyoung 				    sc->sc_dev.dv_xname, i, error);
   1350        1.1   dyoung 				/*
   1351        1.1   dyoung 				 * XXX Should attempt to run with fewer receive
   1352        1.1   dyoung 				 * XXX buffers instead of just failing.
   1353        1.1   dyoung 				 */
   1354        1.1   dyoung 				atw_rxdrain(sc);
   1355        1.1   dyoung 				goto out;
   1356        1.1   dyoung 			}
   1357        1.1   dyoung 		} else
   1358        1.1   dyoung 			ATW_INIT_RXDESC(sc, i);
   1359        1.1   dyoung 	}
   1360        1.1   dyoung 	sc->sc_rxptr = 0;
   1361        1.1   dyoung 
   1362        1.1   dyoung 	/*
   1363        1.1   dyoung 	 * Initialize the interrupt mask and enable interrupts.
   1364        1.1   dyoung 	 */
   1365        1.1   dyoung 	/* normal interrupts */
   1366        1.1   dyoung 	sc->sc_inten =  ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI |
   1367        1.1   dyoung 	    ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC;
   1368        1.1   dyoung 
   1369        1.1   dyoung 	/* abnormal interrupts */
   1370        1.1   dyoung 	sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT |
   1371        1.1   dyoung 	    ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS |
   1372        1.1   dyoung 	    ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
   1373        1.1   dyoung 
   1374        1.1   dyoung 	sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF |
   1375        1.1   dyoung 	    ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
   1376        1.1   dyoung 	sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU;
   1377        1.1   dyoung 	sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT |
   1378        1.1   dyoung 	    ATW_INTR_TRT;
   1379        1.1   dyoung 
   1380        1.1   dyoung 	sc->sc_linkint_mask &= sc->sc_inten;
   1381        1.1   dyoung 	sc->sc_rxint_mask &= sc->sc_inten;
   1382        1.1   dyoung 	sc->sc_txint_mask &= sc->sc_inten;
   1383        1.1   dyoung 
   1384        1.1   dyoung 	ATW_WRITE(sc, ATW_IER, sc->sc_inten);
   1385        1.1   dyoung 	ATW_WRITE(sc, ATW_STSR, 0xffffffff);
   1386        1.1   dyoung 
   1387        1.1   dyoung 	DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n",
   1388        1.1   dyoung 	    sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten));
   1389        1.1   dyoung 
   1390        1.1   dyoung 	/*
   1391        1.1   dyoung 	 * Give the transmit and receive rings to the ADM8211.
   1392        1.1   dyoung 	 */
   1393       1.64   dyoung 	ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr));
   1394        1.1   dyoung 	ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext));
   1395       1.64   dyoung 
   1396       1.64   dyoung 	sc->sc_txthresh = 0;
   1397       1.64   dyoung 	sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST |
   1398       1.64   dyoung 	    sc->sc_txth[sc->sc_txthresh].txth_opmode;
   1399        1.1   dyoung 
   1400        1.1   dyoung 	/* common 802.11 configuration */
   1401        1.1   dyoung 	ic->ic_flags &= ~IEEE80211_F_IBSSON;
   1402        1.1   dyoung 	switch (ic->ic_opmode) {
   1403        1.1   dyoung 	case IEEE80211_M_STA:
   1404        1.1   dyoung 		break;
   1405        1.1   dyoung 	case IEEE80211_M_AHDEMO: /* XXX */
   1406        1.1   dyoung 	case IEEE80211_M_IBSS:
   1407       1.16   dyoung 		ic->ic_flags |= IEEE80211_F_IBSSON;
   1408       1.16   dyoung 		/*FALLTHROUGH*/
   1409       1.16   dyoung 	case IEEE80211_M_HOSTAP: /* XXX */
   1410        1.1   dyoung 		break;
   1411        1.1   dyoung 	case IEEE80211_M_MONITOR: /* XXX */
   1412        1.1   dyoung 		break;
   1413        1.1   dyoung 	}
   1414        1.1   dyoung 
   1415        1.1   dyoung 	switch (ic->ic_opmode) {
   1416        1.1   dyoung 	case IEEE80211_M_AHDEMO:
   1417        1.1   dyoung 	case IEEE80211_M_HOSTAP:
   1418       1.87   dyoung #ifndef IEEE80211_NO_HOSTAP
   1419        1.3   dyoung 		ic->ic_bss->ni_intval = ic->ic_lintval;
   1420        1.3   dyoung 		ic->ic_bss->ni_rssi = 0;
   1421        1.3   dyoung 		ic->ic_bss->ni_rstamp = 0;
   1422       1.87   dyoung #endif /* !IEEE80211_NO_HOSTAP */
   1423        1.1   dyoung 		break;
   1424       1.10   dyoung 	default:					/* XXX */
   1425        1.1   dyoung 		break;
   1426        1.1   dyoung 	}
   1427        1.1   dyoung 
   1428       1.64   dyoung 	sc->sc_wepctl = 0;
   1429       1.64   dyoung 
   1430        1.1   dyoung 	atw_write_ssid(sc);
   1431        1.1   dyoung 	atw_write_sup_rates(sc);
   1432       1.94   dyoung 	atw_write_wep(sc);
   1433        1.1   dyoung 
   1434       1.64   dyoung 	ic->ic_state = IEEE80211_S_INIT;
   1435       1.64   dyoung 
   1436        1.1   dyoung 	/*
   1437        1.1   dyoung 	 * Set the receive filter.  This will start the transmit and
   1438        1.1   dyoung 	 * receive processes.
   1439        1.1   dyoung 	 */
   1440        1.1   dyoung 	atw_filter_setup(sc);
   1441        1.1   dyoung 
   1442        1.1   dyoung 	/*
   1443        1.1   dyoung 	 * Start the receive process.
   1444        1.1   dyoung 	 */
   1445        1.1   dyoung 	ATW_WRITE(sc, ATW_RDR, 0x1);
   1446        1.1   dyoung 
   1447        1.1   dyoung 	/*
   1448        1.1   dyoung 	 * Note that the interface is now running.
   1449        1.1   dyoung 	 */
   1450        1.1   dyoung 	ifp->if_flags |= IFF_RUNNING;
   1451        1.1   dyoung 	ifp->if_flags &= ~IFF_OACTIVE;
   1452        1.1   dyoung 
   1453       1.64   dyoung 	/* send no beacons, yet. */
   1454       1.64   dyoung 	atw_start_beacon(sc, 0);
   1455       1.64   dyoung 
   1456       1.64   dyoung 	if (ic->ic_opmode == IEEE80211_M_MONITOR)
   1457       1.64   dyoung 		error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
   1458       1.64   dyoung 	else
   1459       1.10   dyoung 		error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
   1460        1.1   dyoung  out:
   1461        1.1   dyoung 	if (error) {
   1462        1.1   dyoung 		ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   1463       1.91   dyoung 		sc->sc_tx_timer = 0;
   1464        1.1   dyoung 		ifp->if_timer = 0;
   1465        1.1   dyoung 		printf("%s: interface not running\n", sc->sc_dev.dv_xname);
   1466        1.1   dyoung 	}
   1467        1.1   dyoung #ifdef ATW_DEBUG
   1468        1.1   dyoung 	atw_print_regs(sc, "end of init");
   1469        1.1   dyoung #endif /* ATW_DEBUG */
   1470        1.1   dyoung 
   1471        1.1   dyoung 	return (error);
   1472        1.1   dyoung }
   1473        1.1   dyoung 
   1474        1.1   dyoung /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL.
   1475        1.1   dyoung  *           0: MAC control of RF3000/Si4126.
   1476        1.1   dyoung  *
   1477        1.1   dyoung  * Applies power, or selects RF front-end? Sets reset condition.
   1478        1.1   dyoung  *
   1479        1.1   dyoung  * TBD support non-RFMD BBP, non-SiLabs synth.
   1480        1.1   dyoung  */
   1481        1.1   dyoung static void
   1482       1.59   dyoung atw_bbp_io_enable(struct atw_softc *sc, int enable)
   1483        1.1   dyoung {
   1484        1.1   dyoung 	if (enable) {
   1485        1.1   dyoung 		ATW_WRITE(sc, ATW_SYNRF,
   1486        1.1   dyoung 		    ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST);
   1487       1.59   dyoung 		DELAY(atw_bbp_io_enable_delay);
   1488        1.1   dyoung 	} else {
   1489        1.1   dyoung 		ATW_WRITE(sc, ATW_SYNRF, 0);
   1490       1.59   dyoung 		DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */
   1491        1.1   dyoung 	}
   1492        1.1   dyoung }
   1493        1.1   dyoung 
   1494        1.1   dyoung static int
   1495       1.23   dyoung atw_tune(struct atw_softc *sc)
   1496        1.1   dyoung {
   1497        1.1   dyoung 	int rc;
   1498       1.59   dyoung 	u_int chan;
   1499        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   1500        1.1   dyoung 
   1501       1.90    skrll 	chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
   1502        1.3   dyoung 	if (chan == IEEE80211_CHAN_ANY)
   1503        1.3   dyoung 		panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__);
   1504        1.3   dyoung 
   1505        1.3   dyoung 	if (chan == sc->sc_cur_chan)
   1506        1.3   dyoung 		return 0;
   1507        1.1   dyoung 
   1508        1.1   dyoung 	DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname,
   1509        1.1   dyoung 	    sc->sc_cur_chan, chan));
   1510        1.1   dyoung 
   1511        1.1   dyoung 	atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST);
   1512        1.1   dyoung 
   1513       1.59   dyoung 	atw_si4126_tune(sc, chan);
   1514       1.59   dyoung 	if ((rc = atw_rf3000_tune(sc, chan)) != 0)
   1515        1.1   dyoung 		printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname,
   1516        1.1   dyoung 		    chan);
   1517        1.1   dyoung 
   1518        1.1   dyoung 	ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
   1519       1.70   dyoung 	DELAY(atw_nar_delay);
   1520       1.59   dyoung 	ATW_WRITE(sc, ATW_RDR, 0x1);
   1521        1.1   dyoung 
   1522        1.1   dyoung 	if (rc == 0)
   1523        1.1   dyoung 		sc->sc_cur_chan = chan;
   1524        1.1   dyoung 
   1525        1.1   dyoung 	return rc;
   1526        1.1   dyoung }
   1527        1.1   dyoung 
   1528       1.59   dyoung #ifdef ATW_SYNDEBUG
   1529        1.1   dyoung static void
   1530       1.23   dyoung atw_si4126_print(struct atw_softc *sc)
   1531        1.1   dyoung {
   1532       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   1533        1.1   dyoung 	u_int addr, val;
   1534        1.1   dyoung 
   1535        1.1   dyoung 	if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
   1536        1.1   dyoung 		return;
   1537        1.1   dyoung 
   1538        1.1   dyoung 	for (addr = 0; addr <= 8; addr++) {
   1539        1.1   dyoung 		printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr);
   1540        1.1   dyoung 		if (atw_si4126_read(sc, addr, &val) == 0) {
   1541        1.1   dyoung 			printf("<unknown> (quitting print-out)\n");
   1542        1.1   dyoung 			break;
   1543        1.1   dyoung 		}
   1544        1.1   dyoung 		printf("%05x\n", val);
   1545        1.1   dyoung 	}
   1546        1.1   dyoung }
   1547       1.59   dyoung #endif /* ATW_SYNDEBUG */
   1548        1.1   dyoung 
   1549        1.1   dyoung /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer.
   1550        1.1   dyoung  *
   1551        1.1   dyoung  * The RF/IF synthesizer produces two reference frequencies for
   1552        1.1   dyoung  * the RF2948B transceiver.  The first frequency the RF2948B requires
   1553        1.1   dyoung  * is two times the so-called "intermediate frequency" (IF). Since
   1554  1.105.6.1   simonb  * a SAW filter on the radio fixes the IF at 374 MHz, I program the
   1555  1.105.6.1   simonb  * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz.  The second
   1556        1.1   dyoung  * frequency required by the transceiver is the radio frequency
   1557        1.1   dyoung  * (RF). This is a superheterodyne transceiver; for f(chan) the
   1558        1.1   dyoung  * center frequency of the channel we are tuning, RF = f(chan) -
   1559        1.1   dyoung  * IF.
   1560        1.1   dyoung  *
   1561        1.1   dyoung  * XXX I am told by SiLabs that the Si4126 will accept a broader range
   1562  1.105.6.1   simonb  * of XIN than the 2-25 MHz mentioned by the datasheet, even *without*
   1563        1.1   dyoung  * XINDIV2 = 1.  I've tried this (it is necessary to double R) and it
   1564        1.1   dyoung  * works, but I have still programmed for XINDIV2 = 1 to be safe.
   1565        1.1   dyoung  */
   1566       1.59   dyoung static void
   1567       1.59   dyoung atw_si4126_tune(struct atw_softc *sc, u_int chan)
   1568        1.1   dyoung {
   1569        1.1   dyoung 	u_int mhz;
   1570        1.1   dyoung 	u_int R;
   1571       1.59   dyoung 	u_int32_t gpio;
   1572        1.1   dyoung 	u_int16_t gain;
   1573        1.1   dyoung 
   1574       1.59   dyoung #ifdef ATW_SYNDEBUG
   1575        1.1   dyoung 	atw_si4126_print(sc);
   1576       1.59   dyoung #endif /* ATW_SYNDEBUG */
   1577        1.1   dyoung 
   1578        1.1   dyoung 	if (chan == 14)
   1579        1.1   dyoung 		mhz = 2484;
   1580       1.84    perry 	else
   1581        1.1   dyoung 		mhz = 2412 + 5 * (chan - 1);
   1582        1.1   dyoung 
   1583  1.105.6.1   simonb 	/* Tune IF to 748 MHz to suit the IF LO input of the
   1584        1.1   dyoung 	 * RF2494B, which is 2 x IF. No need to set an IF divider
   1585  1.105.6.1   simonb          * because an IF in 526 MHz - 952 MHz is allowed.
   1586        1.1   dyoung 	 *
   1587  1.105.6.1   simonb 	 * XIN is 44.000 MHz, so divide it by two to get allowable
   1588  1.105.6.1   simonb 	 * range of 2-25 MHz. SiLabs tells me that this is not
   1589        1.1   dyoung 	 * strictly necessary.
   1590        1.1   dyoung 	 */
   1591        1.1   dyoung 
   1592       1.59   dyoung 	if (atw_xindiv2)
   1593       1.59   dyoung 		R = 44;
   1594       1.59   dyoung 	else
   1595       1.59   dyoung 		R = 88;
   1596        1.1   dyoung 
   1597       1.59   dyoung 	/* Power-up RF, IF synthesizers. */
   1598       1.59   dyoung 	atw_si4126_write(sc, SI4126_POWER,
   1599       1.59   dyoung 	    SI4126_POWER_PDIB|SI4126_POWER_PDRB);
   1600        1.1   dyoung 
   1601       1.59   dyoung 	/* set LPWR, too? */
   1602       1.59   dyoung 	atw_si4126_write(sc, SI4126_MAIN,
   1603       1.59   dyoung 	    (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0);
   1604        1.1   dyoung 
   1605       1.59   dyoung 	/* Set the phase-locked loop gain.  If RF2 N > 2047, then
   1606       1.59   dyoung 	 * set KP2 to 1.
   1607       1.59   dyoung 	 *
   1608       1.59   dyoung 	 * REFDIF This is different from the reference driver, which
   1609       1.59   dyoung 	 * always sets SI4126_GAIN to 0.
   1610       1.59   dyoung 	 */
   1611  1.105.6.1   simonb 	gain = SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);
   1612        1.1   dyoung 
   1613       1.59   dyoung 	atw_si4126_write(sc, SI4126_GAIN, gain);
   1614        1.1   dyoung 
   1615  1.105.6.1   simonb 	/* XIN = 44 MHz.
   1616       1.59   dyoung 	 *
   1617       1.59   dyoung 	 * If XINDIV2 = 1, IF = N/(2 * R) * XIN.  I choose N = 1496,
   1618  1.105.6.1   simonb 	 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz.
   1619       1.59   dyoung 	 *
   1620       1.59   dyoung 	 * If XINDIV2 = 0, IF = N/R * XIN.  I choose N = 1496, R = 88
   1621  1.105.6.1   simonb 	 * so that 1496/88 * 44 MHz = 748 MHz.
   1622        1.1   dyoung 	 */
   1623       1.59   dyoung 	atw_si4126_write(sc, SI4126_IFN, 1496);
   1624        1.1   dyoung 
   1625       1.59   dyoung 	atw_si4126_write(sc, SI4126_IFR, R);
   1626        1.1   dyoung 
   1627       1.59   dyoung #ifndef ATW_REFSLAVE
   1628        1.1   dyoung 	/* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because
   1629        1.1   dyoung 	 * then RF1 becomes the active RF synthesizer, even on the Si4126,
   1630        1.1   dyoung 	 * which has no RF1!
   1631        1.1   dyoung 	 */
   1632       1.59   dyoung 	atw_si4126_write(sc, SI4126_RF1R, R);
   1633        1.1   dyoung 
   1634       1.59   dyoung 	atw_si4126_write(sc, SI4126_RF1N, mhz - 374);
   1635       1.59   dyoung #endif
   1636        1.1   dyoung 
   1637  1.105.6.1   simonb 	/* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF,
   1638  1.105.6.1   simonb 	 * where IF = 374 MHz.  Let's divide XIN to 1 MHz. So R = 44.
   1639        1.1   dyoung 	 * Now let's multiply it to mhz. So mhz - IF = N.
   1640        1.1   dyoung 	 */
   1641       1.59   dyoung 	atw_si4126_write(sc, SI4126_RF2R, R);
   1642        1.1   dyoung 
   1643       1.59   dyoung 	atw_si4126_write(sc, SI4126_RF2N, mhz - 374);
   1644        1.1   dyoung 
   1645        1.1   dyoung 	/* wait 100us from power-up for RF, IF to settle */
   1646        1.1   dyoung 	DELAY(100);
   1647        1.1   dyoung 
   1648       1.59   dyoung 	gpio = ATW_READ(sc, ATW_GPIO);
   1649       1.59   dyoung 	gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK);
   1650  1.105.6.1   simonb 	gpio |= SHIFTIN(1, ATW_GPIO_EN_MASK);
   1651       1.59   dyoung 
   1652       1.59   dyoung 	if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) {
   1653       1.59   dyoung 		/* Set a Prism RF front-end to a special mode for channel 14?
   1654       1.59   dyoung 		 *
   1655       1.59   dyoung 		 * Apparently the SMC2635W needs this, although I don't think
   1656       1.59   dyoung 		 * it has a Prism RF.
   1657       1.59   dyoung 		 */
   1658  1.105.6.1   simonb 		gpio |= SHIFTIN(1, ATW_GPIO_O_MASK);
   1659        1.1   dyoung 	}
   1660       1.59   dyoung 	ATW_WRITE(sc, ATW_GPIO, gpio);
   1661        1.1   dyoung 
   1662       1.59   dyoung #ifdef ATW_SYNDEBUG
   1663        1.1   dyoung 	atw_si4126_print(sc);
   1664       1.59   dyoung #endif /* ATW_SYNDEBUG */
   1665        1.1   dyoung }
   1666        1.1   dyoung 
   1667       1.14   dyoung /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna
   1668       1.14   dyoung  * diversity.
   1669        1.1   dyoung  *
   1670       1.59   dyoung  * !!!
   1671       1.59   dyoung  * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR).
   1672       1.59   dyoung  * !!!
   1673        1.1   dyoung  */
   1674        1.1   dyoung static int
   1675       1.23   dyoung atw_rf3000_init(struct atw_softc *sc)
   1676        1.1   dyoung {
   1677        1.1   dyoung 	int rc = 0;
   1678        1.1   dyoung 
   1679       1.59   dyoung 	atw_bbp_io_enable(sc, 1);
   1680       1.59   dyoung 
   1681       1.84    perry 	/* CCA is acquisition sensitive */
   1682       1.59   dyoung 	rc = atw_rf3000_write(sc, RF3000_CCACTL,
   1683  1.105.6.1   simonb 	    SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));
   1684        1.1   dyoung 
   1685       1.59   dyoung 	if (rc != 0)
   1686       1.59   dyoung 		goto out;
   1687        1.1   dyoung 
   1688        1.1   dyoung 	/* enable diversity */
   1689        1.1   dyoung 	rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE);
   1690        1.1   dyoung 
   1691        1.1   dyoung 	if (rc != 0)
   1692        1.1   dyoung 		goto out;
   1693        1.1   dyoung 
   1694        1.1   dyoung 	/* sensible setting from a binary-only driver */
   1695        1.1   dyoung 	rc = atw_rf3000_write(sc, RF3000_GAINCTL,
   1696  1.105.6.1   simonb 	    SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK));
   1697        1.1   dyoung 
   1698        1.1   dyoung 	if (rc != 0)
   1699        1.1   dyoung 		goto out;
   1700        1.1   dyoung 
   1701        1.1   dyoung 	/* magic from a binary-only driver */
   1702        1.1   dyoung 	rc = atw_rf3000_write(sc, RF3000_LOGAINCAL,
   1703  1.105.6.1   simonb 	    SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK));
   1704        1.1   dyoung 
   1705        1.1   dyoung 	if (rc != 0)
   1706        1.1   dyoung 		goto out;
   1707        1.1   dyoung 
   1708        1.1   dyoung 	rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD);
   1709        1.1   dyoung 
   1710        1.1   dyoung 	if (rc != 0)
   1711        1.1   dyoung 		goto out;
   1712        1.1   dyoung 
   1713       1.59   dyoung 	/* XXX Reference driver remarks that Abocom sets this to 50.
   1714       1.59   dyoung 	 * Meaning 0x50, I think....  50 = 0x32, which would set a bit
   1715       1.59   dyoung 	 * in the "reserved" area of register RF3000_OPTIONS1.
   1716       1.59   dyoung 	 */
   1717       1.69   dyoung 	rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1);
   1718        1.1   dyoung 
   1719        1.1   dyoung 	if (rc != 0)
   1720        1.1   dyoung 		goto out;
   1721        1.1   dyoung 
   1722       1.69   dyoung 	rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2);
   1723        1.1   dyoung 
   1724        1.1   dyoung 	if (rc != 0)
   1725        1.1   dyoung 		goto out;
   1726        1.1   dyoung 
   1727        1.1   dyoung out:
   1728       1.59   dyoung 	atw_bbp_io_enable(sc, 0);
   1729        1.1   dyoung 	return rc;
   1730        1.1   dyoung }
   1731        1.1   dyoung 
   1732       1.59   dyoung #ifdef ATW_BBPDEBUG
   1733        1.1   dyoung static void
   1734       1.23   dyoung atw_rf3000_print(struct atw_softc *sc)
   1735        1.1   dyoung {
   1736       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   1737        1.1   dyoung 	u_int addr, val;
   1738        1.1   dyoung 
   1739        1.1   dyoung 	if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
   1740        1.1   dyoung 		return;
   1741        1.1   dyoung 
   1742        1.1   dyoung 	for (addr = 0x01; addr <= 0x15; addr++) {
   1743        1.1   dyoung 		printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr);
   1744        1.1   dyoung 		if (atw_rf3000_read(sc, addr, &val) != 0) {
   1745        1.1   dyoung 			printf("<unknown> (quitting print-out)\n");
   1746        1.1   dyoung 			break;
   1747        1.1   dyoung 		}
   1748        1.1   dyoung 		printf("%08x\n", val);
   1749        1.1   dyoung 	}
   1750        1.1   dyoung }
   1751       1.59   dyoung #endif /* ATW_BBPDEBUG */
   1752        1.1   dyoung 
   1753        1.1   dyoung /* Set the power settings on the BBP for channel `chan'. */
   1754        1.1   dyoung static int
   1755       1.59   dyoung atw_rf3000_tune(struct atw_softc *sc, u_int chan)
   1756        1.1   dyoung {
   1757        1.1   dyoung 	int rc = 0;
   1758        1.1   dyoung 	u_int32_t reg;
   1759        1.1   dyoung 	u_int16_t txpower, lpf_cutoff, lna_gs_thresh;
   1760        1.1   dyoung 
   1761        1.1   dyoung 	txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)];
   1762        1.1   dyoung 	lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)];
   1763        1.1   dyoung 	lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)];
   1764        1.1   dyoung 
   1765        1.1   dyoung 	/* odd channels: LSB, even channels: MSB */
   1766        1.1   dyoung 	if (chan % 2 == 1) {
   1767        1.1   dyoung 		txpower &= 0xFF;
   1768        1.1   dyoung 		lpf_cutoff &= 0xFF;
   1769        1.1   dyoung 		lna_gs_thresh &= 0xFF;
   1770        1.1   dyoung 	} else {
   1771        1.1   dyoung 		txpower >>= 8;
   1772        1.1   dyoung 		lpf_cutoff >>= 8;
   1773        1.1   dyoung 		lna_gs_thresh >>= 8;
   1774        1.1   dyoung 	}
   1775        1.1   dyoung 
   1776       1.84    perry #ifdef ATW_BBPDEBUG
   1777        1.1   dyoung 	atw_rf3000_print(sc);
   1778       1.59   dyoung #endif /* ATW_BBPDEBUG */
   1779        1.1   dyoung 
   1780        1.1   dyoung 	DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, "
   1781        1.1   dyoung 	    "lna_gs_thresh %02x\n",
   1782        1.1   dyoung 	    sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh));
   1783        1.1   dyoung 
   1784       1.59   dyoung 	atw_bbp_io_enable(sc, 1);
   1785       1.17   dyoung 
   1786        1.1   dyoung 	if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL,
   1787  1.105.6.1   simonb 	    SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)
   1788        1.1   dyoung 		goto out;
   1789        1.1   dyoung 
   1790        1.1   dyoung 	if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0)
   1791        1.1   dyoung 		goto out;
   1792        1.1   dyoung 
   1793        1.1   dyoung 	if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0)
   1794        1.1   dyoung 		goto out;
   1795        1.1   dyoung 
   1796       1.59   dyoung 	rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0);
   1797       1.59   dyoung 
   1798       1.59   dyoung 	if (rc != 0)
   1799       1.59   dyoung 		goto out;
   1800       1.59   dyoung 
   1801       1.59   dyoung 	rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY);
   1802       1.59   dyoung 
   1803       1.59   dyoung 	if (rc != 0)
   1804       1.59   dyoung 		goto out;
   1805       1.59   dyoung 
   1806       1.84    perry #ifdef ATW_BBPDEBUG
   1807       1.59   dyoung 	atw_rf3000_print(sc);
   1808       1.59   dyoung #endif /* ATW_BBPDEBUG */
   1809       1.59   dyoung 
   1810       1.59   dyoung out:
   1811       1.59   dyoung 	atw_bbp_io_enable(sc, 0);
   1812       1.59   dyoung 
   1813       1.59   dyoung 	/* set beacon, rts, atim transmit power */
   1814        1.1   dyoung 	reg = ATW_READ(sc, ATW_PLCPHD);
   1815        1.1   dyoung 	reg &= ~ATW_PLCPHD_SERVICE_MASK;
   1816  1.105.6.1   simonb 	reg |= SHIFTIN(SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK),
   1817       1.28   dyoung 	    ATW_PLCPHD_SERVICE_MASK);
   1818        1.1   dyoung 	ATW_WRITE(sc, ATW_PLCPHD, reg);
   1819       1.70   dyoung 	DELAY(atw_plcphd_delay);
   1820        1.1   dyoung 
   1821        1.1   dyoung 	return rc;
   1822        1.1   dyoung }
   1823        1.1   dyoung 
   1824        1.1   dyoung /* Write a register on the RF3000 baseband processor using the
   1825        1.1   dyoung  * registers provided by the ADM8211 for this purpose.
   1826        1.1   dyoung  *
   1827        1.1   dyoung  * Return 0 on success.
   1828        1.1   dyoung  */
   1829        1.1   dyoung static int
   1830       1.23   dyoung atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
   1831        1.1   dyoung {
   1832        1.1   dyoung 	u_int32_t reg;
   1833        1.1   dyoung 	int i;
   1834        1.1   dyoung 
   1835        1.1   dyoung 	reg = sc->sc_bbpctl_wr |
   1836  1.105.6.1   simonb 	     SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) |
   1837  1.105.6.1   simonb 	     SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
   1838        1.1   dyoung 
   1839       1.70   dyoung 	for (i = 20000 / atw_pseudo_milli; --i >= 0; ) {
   1840       1.58   dyoung 		ATW_WRITE(sc, ATW_BBPCTL, reg);
   1841       1.70   dyoung 		DELAY(2 * atw_pseudo_milli);
   1842        1.1   dyoung 		if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0)
   1843        1.1   dyoung 			break;
   1844        1.1   dyoung 	}
   1845        1.1   dyoung 
   1846        1.1   dyoung 	if (i < 0) {
   1847       1.58   dyoung 		printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname);
   1848        1.1   dyoung 		return ETIMEDOUT;
   1849        1.1   dyoung 	}
   1850        1.1   dyoung 	return 0;
   1851        1.1   dyoung }
   1852        1.1   dyoung 
   1853        1.1   dyoung /* Read a register on the RF3000 baseband processor using the registers
   1854        1.1   dyoung  * the ADM8211 provides for this purpose.
   1855        1.1   dyoung  *
   1856        1.1   dyoung  * The 7-bit register address is addr.  Record the 8-bit data in the register
   1857        1.1   dyoung  * in *val.
   1858        1.1   dyoung  *
   1859        1.1   dyoung  * Return 0 on success.
   1860        1.1   dyoung  *
   1861        1.1   dyoung  * XXX This does not seem to work. The ADM8211 must require more or
   1862        1.1   dyoung  * different magic to read the chip than to write it. Possibly some
   1863        1.1   dyoung  * of the magic I have derived from a binary-only driver concerns
   1864        1.1   dyoung  * the "chip address" (see the RF3000 manual).
   1865        1.1   dyoung  */
   1866       1.84    perry #ifdef ATW_BBPDEBUG
   1867        1.1   dyoung static int
   1868       1.23   dyoung atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val)
   1869        1.1   dyoung {
   1870        1.1   dyoung 	u_int32_t reg;
   1871        1.1   dyoung 	int i;
   1872        1.1   dyoung 
   1873        1.1   dyoung 	for (i = 1000; --i >= 0; ) {
   1874        1.1   dyoung 		if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0)
   1875        1.1   dyoung 			break;
   1876        1.1   dyoung 		DELAY(100);
   1877        1.1   dyoung 	}
   1878        1.1   dyoung 
   1879        1.1   dyoung 	if (i < 0) {
   1880        1.1   dyoung 		printf("%s: start atw_rf3000_read, BBPCTL busy\n",
   1881        1.1   dyoung 		    sc->sc_dev.dv_xname);
   1882        1.1   dyoung 		return ETIMEDOUT;
   1883        1.1   dyoung 	}
   1884        1.1   dyoung 
   1885  1.105.6.1   simonb 	reg = sc->sc_bbpctl_rd | SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
   1886        1.1   dyoung 
   1887        1.1   dyoung 	ATW_WRITE(sc, ATW_BBPCTL, reg);
   1888        1.1   dyoung 
   1889        1.1   dyoung 	for (i = 1000; --i >= 0; ) {
   1890        1.1   dyoung 		DELAY(100);
   1891        1.1   dyoung 		if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0)
   1892        1.1   dyoung 			break;
   1893        1.1   dyoung 	}
   1894        1.1   dyoung 
   1895        1.1   dyoung 	ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD);
   1896        1.1   dyoung 
   1897        1.1   dyoung 	if (i < 0) {
   1898        1.1   dyoung 		printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n",
   1899        1.1   dyoung 		    sc->sc_dev.dv_xname, reg);
   1900        1.1   dyoung 		return ETIMEDOUT;
   1901        1.1   dyoung 	}
   1902        1.1   dyoung 	if (val != NULL)
   1903  1.105.6.1   simonb 		*val = SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK);
   1904        1.1   dyoung 	return 0;
   1905        1.1   dyoung }
   1906       1.59   dyoung #endif /* ATW_BBPDEBUG */
   1907        1.1   dyoung 
   1908        1.1   dyoung /* Write a register on the Si4126 RF/IF synthesizer using the registers
   1909        1.1   dyoung  * provided by the ADM8211 for that purpose.
   1910        1.1   dyoung  *
   1911        1.1   dyoung  * val is 18 bits of data, and val is the 4-bit address of the register.
   1912        1.1   dyoung  *
   1913        1.1   dyoung  * Return 0 on success.
   1914        1.1   dyoung  */
   1915       1.59   dyoung static void
   1916       1.23   dyoung atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val)
   1917        1.1   dyoung {
   1918       1.59   dyoung 	uint32_t bits, mask, reg;
   1919       1.59   dyoung 	const int nbits = 22;
   1920        1.1   dyoung 
   1921  1.105.6.1   simonb 	KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
   1922  1.105.6.1   simonb 	KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0);
   1923       1.24   dyoung 
   1924  1.105.6.1   simonb 	bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) |
   1925  1.105.6.1   simonb 	       SHIFTIN(addr, SI4126_TWI_ADDR_MASK);
   1926       1.24   dyoung 
   1927       1.59   dyoung 	reg = ATW_SYNRF_SELSYN;
   1928       1.59   dyoung 	/* reference driver: reset Si4126 serial bus to initial
   1929       1.59   dyoung 	 * conditions?
   1930       1.59   dyoung 	 */
   1931       1.59   dyoung 	ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
   1932       1.59   dyoung 	ATW_WRITE(sc, ATW_SYNRF, reg);
   1933       1.59   dyoung 
   1934  1.105.6.1   simonb 	for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) {
   1935       1.59   dyoung 		if ((bits & mask) != 0)
   1936       1.59   dyoung 			reg |= ATW_SYNRF_SYNDATA;
   1937       1.59   dyoung 		else
   1938       1.59   dyoung 			reg &= ~ATW_SYNRF_SYNDATA;
   1939       1.59   dyoung 		ATW_WRITE(sc, ATW_SYNRF, reg);
   1940       1.59   dyoung 		ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);
   1941       1.59   dyoung 		ATW_WRITE(sc, ATW_SYNRF, reg);
   1942        1.1   dyoung 	}
   1943       1.59   dyoung 	ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
   1944       1.59   dyoung 	ATW_WRITE(sc, ATW_SYNRF, 0x0);
   1945        1.1   dyoung }
   1946        1.1   dyoung 
   1947        1.1   dyoung /* Read 18-bit data from the 4-bit address addr in Si4126
   1948        1.1   dyoung  * RF synthesizer and write the data to *val. Return 0 on success.
   1949        1.1   dyoung  *
   1950        1.1   dyoung  * XXX This does not seem to work. The ADM8211 must require more or
   1951        1.1   dyoung  * different magic to read the chip than to write it.
   1952        1.1   dyoung  */
   1953       1.84    perry #ifdef ATW_SYNDEBUG
   1954        1.1   dyoung static int
   1955       1.23   dyoung atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val)
   1956        1.1   dyoung {
   1957        1.1   dyoung 	u_int32_t reg;
   1958        1.1   dyoung 	int i;
   1959        1.1   dyoung 
   1960  1.105.6.1   simonb 	KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
   1961       1.24   dyoung 
   1962        1.1   dyoung 	for (i = 1000; --i >= 0; ) {
   1963        1.1   dyoung 		if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0)
   1964        1.1   dyoung 			break;
   1965        1.1   dyoung 		DELAY(100);
   1966        1.1   dyoung 	}
   1967        1.1   dyoung 
   1968        1.1   dyoung 	if (i < 0) {
   1969        1.1   dyoung 		printf("%s: start atw_si4126_read, SYNCTL busy\n",
   1970        1.1   dyoung 		    sc->sc_dev.dv_xname);
   1971        1.1   dyoung 		return ETIMEDOUT;
   1972        1.1   dyoung 	}
   1973        1.1   dyoung 
   1974  1.105.6.1   simonb 	reg = sc->sc_synctl_rd | SHIFTIN(addr, ATW_SYNCTL_DATA_MASK);
   1975        1.1   dyoung 
   1976        1.1   dyoung 	ATW_WRITE(sc, ATW_SYNCTL, reg);
   1977        1.1   dyoung 
   1978        1.1   dyoung 	for (i = 1000; --i >= 0; ) {
   1979        1.1   dyoung 		DELAY(100);
   1980        1.1   dyoung 		if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0)
   1981        1.1   dyoung 			break;
   1982        1.1   dyoung 	}
   1983        1.1   dyoung 
   1984        1.1   dyoung 	ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD);
   1985        1.1   dyoung 
   1986        1.1   dyoung 	if (i < 0) {
   1987       1.59   dyoung 		printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n",
   1988        1.1   dyoung 		    sc->sc_dev.dv_xname, reg);
   1989        1.1   dyoung 		return ETIMEDOUT;
   1990        1.1   dyoung 	}
   1991        1.1   dyoung 	if (val != NULL)
   1992  1.105.6.1   simonb 		*val = SHIFTOUT(ATW_READ(sc, ATW_SYNCTL),
   1993        1.1   dyoung 		                       ATW_SYNCTL_DATA_MASK);
   1994        1.1   dyoung 	return 0;
   1995        1.1   dyoung }
   1996       1.59   dyoung #endif /* ATW_SYNDEBUG */
   1997        1.1   dyoung 
   1998        1.1   dyoung /* XXX is the endianness correct? test. */
   1999        1.1   dyoung #define	atw_calchash(addr) \
   2000  1.105.6.1   simonb 	(ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0))
   2001        1.1   dyoung 
   2002        1.1   dyoung /*
   2003        1.1   dyoung  * atw_filter_setup:
   2004        1.1   dyoung  *
   2005        1.1   dyoung  *	Set the ADM8211's receive filter.
   2006        1.1   dyoung  */
   2007        1.1   dyoung static void
   2008       1.23   dyoung atw_filter_setup(struct atw_softc *sc)
   2009        1.1   dyoung {
   2010        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2011       1.85   dyoung 	struct ethercom *ec = &sc->sc_ec;
   2012       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   2013        1.1   dyoung 	int hash;
   2014       1.57   dyoung 	u_int32_t hashes[2];
   2015        1.1   dyoung 	struct ether_multi *enm;
   2016        1.1   dyoung 	struct ether_multistep step;
   2017        1.1   dyoung 
   2018       1.57   dyoung 	/* According to comments in tlp_al981_filter_setup
   2019       1.57   dyoung 	 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its
   2020       1.57   dyoung 	 * multicast filter to be set while it is running.  Hopefully
   2021       1.57   dyoung 	 * the ADM8211 is not the same!
   2022        1.1   dyoung 	 */
   2023       1.57   dyoung 	if ((ifp->if_flags & IFF_RUNNING) != 0)
   2024        1.1   dyoung 		atw_idle(sc, ATW_NAR_SR);
   2025        1.1   dyoung 
   2026        1.1   dyoung 	sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM);
   2027       1.91   dyoung 	ifp->if_flags &= ~IFF_ALLMULTI;
   2028        1.1   dyoung 
   2029       1.57   dyoung 	/* XXX in scan mode, do not filter packets.  Maybe this is
   2030       1.57   dyoung 	 * unnecessary.
   2031       1.57   dyoung 	 */
   2032       1.57   dyoung 	if (ic->ic_state == IEEE80211_S_SCAN ||
   2033       1.57   dyoung 	    (ifp->if_flags & IFF_PROMISC) != 0) {
   2034        1.1   dyoung 		sc->sc_opmode |= ATW_NAR_PR;
   2035       1.57   dyoung 		goto allmulti;
   2036        1.1   dyoung 	}
   2037        1.1   dyoung 
   2038       1.57   dyoung 	hashes[0] = hashes[1] = 0x0;
   2039       1.57   dyoung 
   2040        1.1   dyoung 	/*
   2041        1.1   dyoung 	 * Program the 64-bit multicast hash filter.
   2042        1.1   dyoung 	 */
   2043        1.1   dyoung 	ETHER_FIRST_MULTI(step, ec, enm);
   2044        1.1   dyoung 	while (enm != NULL) {
   2045        1.1   dyoung 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
   2046        1.1   dyoung 		    ETHER_ADDR_LEN) != 0)
   2047        1.1   dyoung 			goto allmulti;
   2048        1.1   dyoung 
   2049        1.1   dyoung 		hash = atw_calchash(enm->enm_addrlo);
   2050        1.1   dyoung 		hashes[hash >> 5] |= 1 << (hash & 0x1f);
   2051        1.1   dyoung 		ETHER_NEXT_MULTI(step, enm);
   2052       1.75   dyoung 		sc->sc_opmode |= ATW_NAR_MM;
   2053        1.1   dyoung 	}
   2054       1.57   dyoung 	ifp->if_flags &= ~IFF_ALLMULTI;
   2055       1.57   dyoung 	goto setit;
   2056        1.1   dyoung 
   2057       1.57   dyoung allmulti:
   2058       1.75   dyoung 	sc->sc_opmode |= ATW_NAR_MM;
   2059       1.57   dyoung 	ifp->if_flags |= IFF_ALLMULTI;
   2060       1.57   dyoung 	hashes[0] = hashes[1] = 0xffffffff;
   2061        1.1   dyoung 
   2062       1.57   dyoung setit:
   2063        1.1   dyoung 	ATW_WRITE(sc, ATW_MAR0, hashes[0]);
   2064        1.1   dyoung 	ATW_WRITE(sc, ATW_MAR1, hashes[1]);
   2065        1.1   dyoung 	ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
   2066       1.70   dyoung 	DELAY(atw_nar_delay);
   2067      1.101   dyoung 	ATW_WRITE(sc, ATW_RDR, 0x1);
   2068       1.57   dyoung 
   2069        1.1   dyoung 	DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname,
   2070        1.1   dyoung 	    ATW_READ(sc, ATW_NAR), sc->sc_opmode));
   2071        1.1   dyoung }
   2072        1.1   dyoung 
   2073        1.1   dyoung /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match
   2074        1.1   dyoung  * a beacon's BSSID and SSID against the preferred BSSID and SSID
   2075        1.1   dyoung  * before it will raise ATW_INTR_LINKON. When the ADM8211 receives
   2076        1.1   dyoung  * no beacon with the preferred BSSID and SSID in the number of
   2077        1.1   dyoung  * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF.
   2078        1.1   dyoung  */
   2079        1.1   dyoung static void
   2080       1.23   dyoung atw_write_bssid(struct atw_softc *sc)
   2081        1.1   dyoung {
   2082        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2083        1.1   dyoung 	u_int8_t *bssid;
   2084        1.1   dyoung 
   2085        1.3   dyoung 	bssid = ic->ic_bss->ni_bssid;
   2086        1.1   dyoung 
   2087       1.52   dyoung 	ATW_WRITE(sc, ATW_BSSID0,
   2088  1.105.6.1   simonb 	    SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |
   2089  1.105.6.1   simonb 	    SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |
   2090  1.105.6.1   simonb 	    SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |
   2091  1.105.6.1   simonb 	    SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK));
   2092       1.52   dyoung 
   2093        1.1   dyoung 	ATW_WRITE(sc, ATW_ABDA1,
   2094        1.1   dyoung 	    (ATW_READ(sc, ATW_ABDA1) &
   2095        1.1   dyoung 	    ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) |
   2096  1.105.6.1   simonb 	    SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |
   2097  1.105.6.1   simonb 	    SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK));
   2098        1.1   dyoung 
   2099        1.1   dyoung 	DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname,
   2100        1.1   dyoung 	    ether_sprintf(sc->sc_bssid)));
   2101        1.1   dyoung 	DPRINTF(sc, ("%s\n", ether_sprintf(bssid)));
   2102        1.1   dyoung 
   2103        1.1   dyoung 	memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid));
   2104        1.1   dyoung }
   2105        1.1   dyoung 
   2106        1.1   dyoung /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th
   2107        1.1   dyoung  * 16-bit word.
   2108        1.1   dyoung  */
   2109        1.1   dyoung static void
   2110       1.23   dyoung atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen)
   2111        1.1   dyoung {
   2112        1.1   dyoung 	u_int i;
   2113        1.1   dyoung 	u_int8_t *ptr;
   2114        1.1   dyoung 
   2115        1.1   dyoung 	memcpy(&sc->sc_sram[ofs], buf, buflen);
   2116        1.1   dyoung 
   2117       1.65   dyoung 	KASSERT(ofs % 2 == 0 && buflen % 2 == 0);
   2118        1.1   dyoung 
   2119       1.69   dyoung 	KASSERT(buflen + ofs <= sc->sc_sramlen);
   2120        1.1   dyoung 
   2121        1.1   dyoung 	ptr = &sc->sc_sram[ofs];
   2122        1.1   dyoung 
   2123        1.1   dyoung 	for (i = 0; i < buflen; i += 2) {
   2124        1.1   dyoung 		ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR |
   2125  1.105.6.1   simonb 		    SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));
   2126        1.1   dyoung 		DELAY(atw_writewep_delay);
   2127        1.1   dyoung 
   2128        1.1   dyoung 		ATW_WRITE(sc, ATW_WESK,
   2129  1.105.6.1   simonb 		    SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));
   2130        1.1   dyoung 		DELAY(atw_writewep_delay);
   2131        1.1   dyoung 	}
   2132        1.1   dyoung 	ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */
   2133        1.1   dyoung 
   2134        1.1   dyoung 	if (sc->sc_if.if_flags & IFF_DEBUG) {
   2135        1.1   dyoung 		int n_octets = 0;
   2136        1.1   dyoung 		printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n",
   2137        1.1   dyoung 		    sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl);
   2138        1.1   dyoung 		for (i = 0; i < buflen; i++) {
   2139        1.1   dyoung 			printf(" %02x", ptr[i]);
   2140        1.1   dyoung 			if (++n_octets % 24 == 0)
   2141        1.1   dyoung 				printf("\n");
   2142        1.1   dyoung 		}
   2143        1.1   dyoung 		if (n_octets % 24 != 0)
   2144        1.1   dyoung 			printf("\n");
   2145        1.1   dyoung 	}
   2146        1.1   dyoung }
   2147        1.1   dyoung 
   2148       1.85   dyoung static int
   2149       1.85   dyoung atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
   2150       1.85   dyoung {
   2151       1.85   dyoung 	struct atw_softc *sc = ic->ic_ifp->if_softc;
   2152       1.85   dyoung 	u_int keyix = k->wk_keyix;
   2153       1.85   dyoung 
   2154       1.85   dyoung 	DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix));
   2155       1.85   dyoung 
   2156       1.85   dyoung 	if (keyix >= IEEE80211_WEP_NKID)
   2157       1.85   dyoung 		return 0;
   2158       1.85   dyoung 	if (k->wk_keylen != 0)
   2159       1.85   dyoung 		sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
   2160       1.85   dyoung 
   2161       1.85   dyoung 	return 1;
   2162       1.85   dyoung }
   2163       1.85   dyoung 
   2164       1.85   dyoung static int
   2165       1.85   dyoung atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
   2166       1.85   dyoung 	const u_int8_t mac[IEEE80211_ADDR_LEN])
   2167       1.85   dyoung {
   2168       1.85   dyoung 	struct atw_softc *sc = ic->ic_ifp->if_softc;
   2169       1.85   dyoung 
   2170       1.85   dyoung 	DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix));
   2171       1.85   dyoung 
   2172       1.85   dyoung 	if (k->wk_keyix >= IEEE80211_WEP_NKID)
   2173       1.85   dyoung 		return 0;
   2174       1.85   dyoung 
   2175       1.85   dyoung 	sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
   2176       1.85   dyoung 
   2177       1.85   dyoung 	return 1;
   2178       1.85   dyoung }
   2179       1.85   dyoung 
   2180       1.85   dyoung static void
   2181       1.85   dyoung atw_key_update_begin(struct ieee80211com *ic)
   2182       1.85   dyoung {
   2183       1.85   dyoung #ifdef ATW_DEBUG
   2184       1.85   dyoung 	struct ifnet *ifp = ic->ic_ifp;
   2185       1.85   dyoung 	struct atw_softc *sc = ifp->if_softc;
   2186       1.85   dyoung #endif
   2187       1.85   dyoung 
   2188       1.85   dyoung 	DPRINTF(sc, ("%s:\n", __func__));
   2189       1.85   dyoung }
   2190       1.85   dyoung 
   2191       1.85   dyoung static void
   2192       1.85   dyoung atw_key_update_end(struct ieee80211com *ic)
   2193       1.85   dyoung {
   2194       1.85   dyoung 	struct ifnet *ifp = ic->ic_ifp;
   2195       1.85   dyoung 	struct atw_softc *sc = ifp->if_softc;
   2196       1.85   dyoung 
   2197       1.85   dyoung 	DPRINTF(sc, ("%s:\n", __func__));
   2198       1.85   dyoung 
   2199       1.85   dyoung 	if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0)
   2200       1.85   dyoung 		return;
   2201       1.89   dyoung 	if (ATW_IS_ENABLED(sc) == 0)
   2202       1.89   dyoung 		return;
   2203       1.89   dyoung 	atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST);
   2204       1.85   dyoung 	atw_write_wep(sc);
   2205       1.89   dyoung 	ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
   2206      1.101   dyoung 	DELAY(atw_nar_delay);
   2207      1.101   dyoung 	ATW_WRITE(sc, ATW_RDR, 0x1);
   2208       1.85   dyoung }
   2209       1.85   dyoung 
   2210        1.1   dyoung /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */
   2211        1.1   dyoung static void
   2212       1.23   dyoung atw_write_wep(struct atw_softc *sc)
   2213        1.1   dyoung {
   2214  1.105.6.1   simonb #if 0
   2215        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2216  1.105.6.1   simonb 	u_int32_t reg;
   2217  1.105.6.1   simonb 	int i;
   2218  1.105.6.1   simonb #endif
   2219        1.1   dyoung 	/* SRAM shared-key record format: key0 flags key1 ... key12 */
   2220        1.1   dyoung 	u_int8_t buf[IEEE80211_WEP_NKID]
   2221        1.1   dyoung 	            [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */];
   2222        1.1   dyoung 
   2223        1.1   dyoung 	sc->sc_wepctl = 0;
   2224        1.1   dyoung 	ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl);
   2225        1.1   dyoung 
   2226        1.1   dyoung 	memset(&buf[0][0], 0, sizeof(buf));
   2227        1.1   dyoung 
   2228  1.105.6.1   simonb #if 0
   2229        1.1   dyoung 	for (i = 0; i < IEEE80211_WEP_NKID; i++) {
   2230       1.85   dyoung 		if (ic->ic_nw_keys[i].wk_keylen > 5) {
   2231        1.1   dyoung 			buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT;
   2232       1.85   dyoung 		} else if (ic->ic_nw_keys[i].wk_keylen != 0) {
   2233        1.1   dyoung 			buf[i][1] = ATW_WEP_ENABLED;
   2234        1.1   dyoung 		} else {
   2235        1.1   dyoung 			buf[i][1] = 0;
   2236        1.1   dyoung 			continue;
   2237        1.1   dyoung 		}
   2238        1.1   dyoung 		buf[i][0] = ic->ic_nw_keys[i].wk_key[0];
   2239        1.1   dyoung 		memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1],
   2240       1.85   dyoung 		    ic->ic_nw_keys[i].wk_keylen - 1);
   2241        1.1   dyoung 	}
   2242        1.1   dyoung 
   2243        1.1   dyoung 	reg = ATW_READ(sc, ATW_MACTEST);
   2244        1.1   dyoung 	reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
   2245        1.1   dyoung 	reg &= ~ATW_MACTEST_KEYID_MASK;
   2246  1.105.6.1   simonb 	reg |= SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK);
   2247        1.1   dyoung 	ATW_WRITE(sc, ATW_MACTEST, reg);
   2248        1.1   dyoung 
   2249       1.85   dyoung 	if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0)
   2250       1.85   dyoung 		sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE;
   2251       1.69   dyoung 
   2252       1.69   dyoung 	switch (sc->sc_rev) {
   2253       1.69   dyoung 	case ATW_REVISION_AB:
   2254       1.69   dyoung 	case ATW_REVISION_AF:
   2255       1.69   dyoung 		/* Bypass WEP on Rx. */
   2256       1.69   dyoung 		sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP;
   2257       1.69   dyoung 		break;
   2258       1.69   dyoung 	default:
   2259       1.69   dyoung 		break;
   2260       1.69   dyoung 	}
   2261  1.105.6.1   simonb #endif
   2262        1.1   dyoung 
   2263        1.1   dyoung 	atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0],
   2264        1.1   dyoung 	    sizeof(buf));
   2265       1.85   dyoung 
   2266       1.85   dyoung 	sc->sc_flags |= ATWF_WEP_SRAM_VALID;
   2267        1.1   dyoung }
   2268        1.1   dyoung 
   2269        1.3   dyoung static void
   2270        1.3   dyoung atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
   2271        1.3   dyoung     struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp)
   2272        1.3   dyoung {
   2273       1.85   dyoung 	struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc;
   2274        1.3   dyoung 
   2275       1.78   dyoung 	/* The ADM8211A answers probe requests. TBD ADM8211B/C. */
   2276       1.78   dyoung 	if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ)
   2277       1.78   dyoung 		return;
   2278       1.78   dyoung 
   2279       1.78   dyoung 	(*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp);
   2280       1.78   dyoung 
   2281        1.3   dyoung 	switch (subtype) {
   2282        1.3   dyoung 	case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
   2283        1.3   dyoung 	case IEEE80211_FC0_SUBTYPE_BEACON:
   2284       1.97   dyoung 		if (ic->ic_opmode == IEEE80211_M_IBSS &&
   2285       1.97   dyoung 		    ic->ic_state == IEEE80211_S_RUN) {
   2286       1.97   dyoung 			if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc))
   2287       1.97   dyoung 				(void)ieee80211_ibss_merge(ni);
   2288       1.97   dyoung 		}
   2289        1.3   dyoung 		break;
   2290        1.3   dyoung 	default:
   2291        1.3   dyoung 		break;
   2292        1.3   dyoung 	}
   2293        1.3   dyoung 	return;
   2294        1.3   dyoung }
   2295        1.3   dyoung 
   2296        1.1   dyoung /* Write the SSID in the ieee80211com to the SRAM on the ADM8211.
   2297        1.1   dyoung  * In ad hoc mode, the SSID is written to the beacons sent by the
   2298        1.1   dyoung  * ADM8211. In both ad hoc and infrastructure mode, beacons received
   2299        1.1   dyoung  * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF
   2300        1.1   dyoung  * indications.
   2301        1.1   dyoung  */
   2302        1.1   dyoung static void
   2303       1.23   dyoung atw_write_ssid(struct atw_softc *sc)
   2304        1.1   dyoung {
   2305        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2306       1.53   dyoung 	/* 34 bytes are reserved in ADM8211 SRAM for the SSID, but
   2307       1.53   dyoung 	 * it only expects the element length, not its ID.
   2308       1.53   dyoung 	 */
   2309       1.18   dyoung 	u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)];
   2310        1.1   dyoung 
   2311        1.1   dyoung 	memset(buf, 0, sizeof(buf));
   2312        1.3   dyoung 	buf[0] = ic->ic_bss->ni_esslen;
   2313        1.3   dyoung 	memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen);
   2314        1.1   dyoung 
   2315       1.53   dyoung 	atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf,
   2316       1.53   dyoung 	    roundup(1 + ic->ic_bss->ni_esslen, 2));
   2317        1.1   dyoung }
   2318        1.1   dyoung 
   2319        1.1   dyoung /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211.
   2320        1.1   dyoung  * In ad hoc mode, the supported rates are written to beacons sent by the
   2321        1.1   dyoung  * ADM8211.
   2322        1.1   dyoung  */
   2323        1.1   dyoung static void
   2324       1.23   dyoung atw_write_sup_rates(struct atw_softc *sc)
   2325        1.1   dyoung {
   2326        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2327        1.1   dyoung 	/* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for
   2328        1.1   dyoung 	 * supported rates
   2329        1.1   dyoung 	 */
   2330       1.18   dyoung 	u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)];
   2331        1.1   dyoung 
   2332        1.1   dyoung 	memset(buf, 0, sizeof(buf));
   2333        1.1   dyoung 
   2334        1.3   dyoung 	buf[0] = ic->ic_bss->ni_rates.rs_nrates;
   2335        1.1   dyoung 
   2336        1.3   dyoung 	memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates,
   2337        1.3   dyoung 	    ic->ic_bss->ni_rates.rs_nrates);
   2338        1.1   dyoung 
   2339        1.1   dyoung 	atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf));
   2340        1.1   dyoung }
   2341        1.1   dyoung 
   2342        1.1   dyoung /* Start/stop sending beacons. */
   2343        1.1   dyoung void
   2344        1.1   dyoung atw_start_beacon(struct atw_softc *sc, int start)
   2345        1.1   dyoung {
   2346        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2347       1.55   dyoung 	uint16_t chan;
   2348       1.55   dyoung 	uint32_t bcnt, bpli, cap0, cap1, capinfo;
   2349       1.55   dyoung 	size_t len;
   2350        1.1   dyoung 
   2351        1.1   dyoung 	if (ATW_IS_ENABLED(sc) == 0)
   2352        1.1   dyoung 		return;
   2353        1.1   dyoung 
   2354        1.1   dyoung 	/* start beacons */
   2355        1.1   dyoung 	len = sizeof(struct ieee80211_frame) +
   2356        1.1   dyoung 	    8 /* timestamp */ + 2 /* beacon interval */ +
   2357        1.1   dyoung 	    2 /* capability info */ +
   2358        1.3   dyoung 	    2 + ic->ic_bss->ni_esslen /* SSID element */ +
   2359        1.3   dyoung 	    2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ +
   2360        1.1   dyoung 	    3 /* DS parameters */ +
   2361        1.1   dyoung 	    IEEE80211_CRC_LEN;
   2362        1.1   dyoung 
   2363       1.55   dyoung 	bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK;
   2364       1.55   dyoung 	cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK;
   2365       1.55   dyoung 	cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK;
   2366        1.1   dyoung 
   2367       1.55   dyoung 	ATW_WRITE(sc, ATW_BCNT, bcnt);
   2368       1.55   dyoung 	ATW_WRITE(sc, ATW_CAP1, cap1);
   2369        1.1   dyoung 
   2370        1.1   dyoung 	if (!start)
   2371        1.1   dyoung 		return;
   2372        1.1   dyoung 
   2373        1.1   dyoung 	/* TBD use ni_capinfo */
   2374        1.1   dyoung 
   2375       1.55   dyoung 	capinfo = 0;
   2376        1.1   dyoung 	if (sc->sc_flags & ATWF_SHORT_PREAMBLE)
   2377        1.1   dyoung 		capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE;
   2378       1.71  mycroft 	if (ic->ic_flags & IEEE80211_F_PRIVACY)
   2379        1.1   dyoung 		capinfo |= IEEE80211_CAPINFO_PRIVACY;
   2380        1.1   dyoung 
   2381        1.1   dyoung 	switch (ic->ic_opmode) {
   2382        1.1   dyoung 	case IEEE80211_M_IBSS:
   2383        1.1   dyoung 		len += 4; /* IBSS parameters */
   2384        1.1   dyoung 		capinfo |= IEEE80211_CAPINFO_IBSS;
   2385        1.1   dyoung 		break;
   2386        1.1   dyoung 	case IEEE80211_M_HOSTAP:
   2387        1.1   dyoung 		/* XXX 6-byte minimum TIM */
   2388        1.1   dyoung 		len += atw_beacon_len_adjust;
   2389        1.1   dyoung 		capinfo |= IEEE80211_CAPINFO_ESS;
   2390        1.1   dyoung 		break;
   2391        1.1   dyoung 	default:
   2392        1.1   dyoung 		return;
   2393        1.1   dyoung 	}
   2394        1.1   dyoung 
   2395       1.55   dyoung 	/* set listen interval
   2396       1.55   dyoung 	 * XXX do software units agree w/ hardware?
   2397       1.55   dyoung 	 */
   2398  1.105.6.1   simonb 	bpli = SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
   2399  1.105.6.1   simonb 	    SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);
   2400       1.55   dyoung 
   2401       1.90    skrll 	chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
   2402        1.1   dyoung 
   2403  1.105.6.1   simonb 	bcnt |= SHIFTIN(len, ATW_BCNT_BCNT_MASK);
   2404  1.105.6.1   simonb 	cap0 |= SHIFTIN(chan, ATW_CAP0_CHN_MASK);
   2405  1.105.6.1   simonb 	cap1 |= SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK);
   2406       1.55   dyoung 
   2407       1.55   dyoung 	ATW_WRITE(sc, ATW_BCNT, bcnt);
   2408       1.55   dyoung 	ATW_WRITE(sc, ATW_BPLI, bpli);
   2409       1.55   dyoung 	ATW_WRITE(sc, ATW_CAP0, cap0);
   2410       1.55   dyoung 	ATW_WRITE(sc, ATW_CAP1, cap1);
   2411        1.1   dyoung 
   2412        1.1   dyoung 	DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n",
   2413       1.55   dyoung 	    sc->sc_dev.dv_xname, bcnt));
   2414        1.1   dyoung 
   2415        1.1   dyoung 	DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n",
   2416       1.55   dyoung 	    sc->sc_dev.dv_xname, cap1));
   2417        1.1   dyoung }
   2418        1.1   dyoung 
   2419       1.56   dyoung /* Return the 32 lsb of the last TSFT divisible by ival. */
   2420       1.92    perry static inline uint32_t
   2421       1.56   dyoung atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival)
   2422       1.56   dyoung {
   2423       1.56   dyoung 	/* Following the reference driver's lead, I compute
   2424       1.84    perry 	 *
   2425       1.56   dyoung 	 *   (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival)
   2426       1.56   dyoung 	 *
   2427       1.56   dyoung 	 * without using 64-bit arithmetic, using the following
   2428       1.56   dyoung 	 * relationship:
   2429       1.56   dyoung 	 *
   2430       1.56   dyoung 	 *     (0x100000000 * H + L) % m
   2431       1.56   dyoung 	 *   = ((0x100000000 % m) * H + L) % m
   2432       1.56   dyoung 	 *   = (((0xffffffff + 1) % m) * H + L) % m
   2433       1.56   dyoung 	 *   = ((0xffffffff % m + 1 % m) * H + L) % m
   2434       1.56   dyoung 	 *   = ((0xffffffff % m + 1) * H + L) % m
   2435       1.56   dyoung 	 */
   2436       1.56   dyoung 	return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival;
   2437       1.56   dyoung }
   2438       1.56   dyoung 
   2439       1.78   dyoung static uint64_t
   2440       1.78   dyoung atw_get_tsft(struct atw_softc *sc)
   2441       1.76   dyoung {
   2442       1.76   dyoung 	int i;
   2443       1.78   dyoung 	uint32_t tsfth, tsftl;
   2444       1.76   dyoung 	for (i = 0; i < 2; i++) {
   2445       1.78   dyoung 		tsfth = ATW_READ(sc, ATW_TSFTH);
   2446       1.78   dyoung 		tsftl = ATW_READ(sc, ATW_TSFTL);
   2447       1.78   dyoung 		if (ATW_READ(sc, ATW_TSFTH) == tsfth)
   2448       1.76   dyoung 			break;
   2449       1.76   dyoung 	}
   2450       1.78   dyoung 	return ((uint64_t)tsfth << 32) | tsftl;
   2451       1.76   dyoung }
   2452       1.76   dyoung 
   2453        1.1   dyoung /* If we've created an IBSS, write the TSF time in the ADM8211 to
   2454        1.1   dyoung  * the ieee80211com.
   2455        1.1   dyoung  *
   2456        1.1   dyoung  * Predict the next target beacon transmission time (TBTT) and
   2457        1.1   dyoung  * write it to the ADM8211.
   2458        1.1   dyoung  */
   2459        1.1   dyoung static void
   2460       1.76   dyoung atw_predict_beacon(struct atw_softc *sc)
   2461        1.1   dyoung {
   2462        1.1   dyoung #define TBTTOFS 20 /* TU */
   2463        1.1   dyoung 
   2464        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2465       1.78   dyoung 	uint64_t tsft;
   2466       1.56   dyoung 	uint32_t ival, past_even, tbtt, tsfth, tsftl;
   2467       1.56   dyoung 	union {
   2468       1.78   dyoung 		uint64_t	word;
   2469       1.56   dyoung 		uint8_t		tstamp[8];
   2470       1.56   dyoung 	} u;
   2471        1.1   dyoung 
   2472        1.1   dyoung 	if ((ic->ic_opmode == IEEE80211_M_HOSTAP) ||
   2473        1.1   dyoung 	    ((ic->ic_opmode == IEEE80211_M_IBSS) &&
   2474        1.1   dyoung 	     (ic->ic_flags & IEEE80211_F_SIBSS))) {
   2475       1.78   dyoung 		tsft = atw_get_tsft(sc);
   2476       1.78   dyoung 		u.word = htole64(tsft);
   2477       1.85   dyoung 		(void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0],
   2478       1.56   dyoung 		    sizeof(ic->ic_bss->ni_tstamp));
   2479       1.85   dyoung 	} else
   2480       1.85   dyoung 		tsft = le64toh(ic->ic_bss->ni_tstamp.tsf);
   2481       1.56   dyoung 
   2482       1.56   dyoung 	ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU;
   2483       1.56   dyoung 
   2484       1.78   dyoung 	tsftl = tsft & 0xFFFFFFFF;
   2485       1.78   dyoung 	tsfth = tsft >> 32;
   2486       1.78   dyoung 
   2487       1.56   dyoung 	/* We sent/received the last beacon `past' microseconds
   2488       1.56   dyoung 	 * after the interval divided the TSF timer.
   2489        1.1   dyoung 	 */
   2490       1.56   dyoung 	past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival);
   2491        1.1   dyoung 
   2492       1.56   dyoung 	/* Skip ten beacons so that the TBTT cannot pass before
   2493       1.56   dyoung 	 * we've programmed it.  Ten is an arbitrary number.
   2494       1.56   dyoung 	 */
   2495       1.56   dyoung 	tbtt = past_even + ival * 10;
   2496        1.1   dyoung 
   2497        1.1   dyoung 	ATW_WRITE(sc, ATW_TOFS1,
   2498  1.105.6.1   simonb 	    SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) |
   2499  1.105.6.1   simonb 	    SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |
   2500  1.105.6.1   simonb 	    SHIFTIN(SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
   2501       1.56   dyoung 	        ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK));
   2502        1.1   dyoung #undef TBTTOFS
   2503        1.1   dyoung }
   2504        1.1   dyoung 
   2505        1.3   dyoung static void
   2506        1.3   dyoung atw_next_scan(void *arg)
   2507        1.3   dyoung {
   2508        1.3   dyoung 	struct atw_softc *sc = arg;
   2509        1.3   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2510        1.3   dyoung 	int s;
   2511        1.3   dyoung 
   2512        1.3   dyoung 	/* don't call atw_start w/o network interrupts blocked */
   2513        1.3   dyoung 	s = splnet();
   2514        1.3   dyoung 	if (ic->ic_state == IEEE80211_S_SCAN)
   2515       1.73  mycroft 		ieee80211_next_scan(ic);
   2516        1.3   dyoung 	splx(s);
   2517        1.3   dyoung }
   2518        1.3   dyoung 
   2519        1.1   dyoung /* Synchronize the hardware state with the software state. */
   2520        1.1   dyoung static int
   2521        1.3   dyoung atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
   2522        1.1   dyoung {
   2523       1.85   dyoung 	struct ifnet *ifp = ic->ic_ifp;
   2524        1.3   dyoung 	struct atw_softc *sc = ifp->if_softc;
   2525        1.1   dyoung 	enum ieee80211_state ostate;
   2526       1.90    skrll 	int error = 0;
   2527        1.1   dyoung 
   2528        1.1   dyoung 	ostate = ic->ic_state;
   2529       1.90    skrll 	callout_stop(&sc->sc_scan_ch);
   2530        1.3   dyoung 
   2531        1.1   dyoung 	switch (nstate) {
   2532       1.98   dyoung 	case IEEE80211_S_AUTH:
   2533        1.3   dyoung 	case IEEE80211_S_ASSOC:
   2534  1.105.6.1   simonb 		atw_write_bssid(sc);
   2535       1.90    skrll 		error = atw_tune(sc);
   2536        1.3   dyoung 		break;
   2537        1.1   dyoung 	case IEEE80211_S_INIT:
   2538       1.90    skrll 		callout_stop(&sc->sc_scan_ch);
   2539       1.90    skrll 		sc->sc_cur_chan = IEEE80211_CHAN_ANY;
   2540       1.98   dyoung 		atw_start_beacon(sc, 0);
   2541        1.1   dyoung 		break;
   2542        1.1   dyoung 	case IEEE80211_S_SCAN:
   2543       1.90    skrll 		error = atw_tune(sc);
   2544        1.3   dyoung 		callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000,
   2545        1.3   dyoung 		    atw_next_scan, sc);
   2546       1.90    skrll 		break;
   2547        1.1   dyoung 	case IEEE80211_S_RUN:
   2548       1.90    skrll 		error = atw_tune(sc);
   2549        1.1   dyoung 		atw_write_bssid(sc);
   2550        1.1   dyoung 		atw_write_ssid(sc);
   2551        1.1   dyoung 		atw_write_sup_rates(sc);
   2552        1.1   dyoung 
   2553        1.3   dyoung 		if (ic->ic_opmode == IEEE80211_M_AHDEMO ||
   2554        1.3   dyoung 		    ic->ic_opmode == IEEE80211_M_MONITOR)
   2555        1.3   dyoung 			break;
   2556        1.1   dyoung 
   2557        1.3   dyoung 		/* set listen interval
   2558        1.3   dyoung 		 * XXX do software units agree w/ hardware?
   2559        1.3   dyoung 		 */
   2560        1.3   dyoung 		ATW_WRITE(sc, ATW_BPLI,
   2561  1.105.6.1   simonb 		    SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
   2562  1.105.6.1   simonb 		    SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval,
   2563        1.3   dyoung 			   ATW_BPLI_LI_MASK));
   2564        1.1   dyoung 
   2565       1.98   dyoung 		DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname,
   2566       1.98   dyoung 		    ATW_READ(sc, ATW_BPLI)));
   2567        1.1   dyoung 
   2568       1.76   dyoung 		atw_predict_beacon(sc);
   2569       1.98   dyoung 
   2570       1.98   dyoung 		switch (ic->ic_opmode) {
   2571       1.98   dyoung 		case IEEE80211_M_AHDEMO:
   2572       1.98   dyoung 		case IEEE80211_M_HOSTAP:
   2573       1.98   dyoung 		case IEEE80211_M_IBSS:
   2574       1.98   dyoung 			atw_start_beacon(sc, 1);
   2575       1.98   dyoung 			break;
   2576       1.98   dyoung 		case IEEE80211_M_MONITOR:
   2577       1.98   dyoung 		case IEEE80211_M_STA:
   2578       1.98   dyoung 			break;
   2579       1.98   dyoung 		}
   2580       1.98   dyoung 
   2581        1.1   dyoung 		break;
   2582        1.1   dyoung 	}
   2583       1.90    skrll 	return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg);
   2584        1.1   dyoung }
   2585        1.1   dyoung 
   2586        1.1   dyoung /*
   2587        1.1   dyoung  * atw_add_rxbuf:
   2588        1.1   dyoung  *
   2589        1.1   dyoung  *	Add a receive buffer to the indicated descriptor.
   2590        1.1   dyoung  */
   2591        1.1   dyoung int
   2592       1.23   dyoung atw_add_rxbuf(struct atw_softc *sc, int idx)
   2593        1.1   dyoung {
   2594        1.1   dyoung 	struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx];
   2595        1.1   dyoung 	struct mbuf *m;
   2596        1.1   dyoung 	int error;
   2597        1.1   dyoung 
   2598        1.1   dyoung 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   2599        1.1   dyoung 	if (m == NULL)
   2600        1.1   dyoung 		return (ENOBUFS);
   2601        1.1   dyoung 
   2602        1.1   dyoung 	MCLGET(m, M_DONTWAIT);
   2603        1.1   dyoung 	if ((m->m_flags & M_EXT) == 0) {
   2604        1.1   dyoung 		m_freem(m);
   2605        1.1   dyoung 		return (ENOBUFS);
   2606        1.1   dyoung 	}
   2607        1.1   dyoung 
   2608        1.1   dyoung 	if (rxs->rxs_mbuf != NULL)
   2609        1.1   dyoung 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2610        1.1   dyoung 
   2611        1.1   dyoung 	rxs->rxs_mbuf = m;
   2612        1.1   dyoung 
   2613        1.1   dyoung 	error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
   2614        1.1   dyoung 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
   2615        1.1   dyoung 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   2616        1.1   dyoung 	if (error) {
   2617        1.1   dyoung 		printf("%s: can't load rx DMA map %d, error = %d\n",
   2618        1.1   dyoung 		    sc->sc_dev.dv_xname, idx, error);
   2619        1.1   dyoung 		panic("atw_add_rxbuf");	/* XXX */
   2620        1.1   dyoung 	}
   2621        1.1   dyoung 
   2622        1.1   dyoung 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2623        1.1   dyoung 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   2624        1.1   dyoung 
   2625        1.1   dyoung 	ATW_INIT_RXDESC(sc, idx);
   2626        1.1   dyoung 
   2627        1.1   dyoung 	return (0);
   2628        1.1   dyoung }
   2629        1.1   dyoung 
   2630        1.1   dyoung /*
   2631       1.36   dyoung  * Release any queued transmit buffers.
   2632       1.36   dyoung  */
   2633       1.36   dyoung void
   2634       1.36   dyoung atw_txdrain(struct atw_softc *sc)
   2635       1.36   dyoung {
   2636       1.36   dyoung 	struct atw_txsoft *txs;
   2637       1.36   dyoung 
   2638       1.36   dyoung 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
   2639       1.36   dyoung 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
   2640       1.36   dyoung 		if (txs->txs_mbuf != NULL) {
   2641       1.36   dyoung 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   2642       1.36   dyoung 			m_freem(txs->txs_mbuf);
   2643       1.36   dyoung 			txs->txs_mbuf = NULL;
   2644       1.36   dyoung 		}
   2645       1.36   dyoung 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
   2646       1.91   dyoung 		sc->sc_txfree += txs->txs_ndescs;
   2647       1.36   dyoung 	}
   2648      1.102   dyoung 
   2649      1.102   dyoung 	KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 ||
   2650      1.102   dyoung 	        !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) ||
   2651      1.102   dyoung 		  sc->sc_txfree != ATW_NTXDESC));
   2652       1.91   dyoung 	sc->sc_if.if_flags &= ~IFF_OACTIVE;
   2653       1.36   dyoung 	sc->sc_tx_timer = 0;
   2654       1.36   dyoung }
   2655       1.36   dyoung 
   2656       1.36   dyoung /*
   2657        1.1   dyoung  * atw_stop:		[ ifnet interface function ]
   2658        1.1   dyoung  *
   2659        1.1   dyoung  *	Stop transmission on the interface.
   2660        1.1   dyoung  */
   2661        1.1   dyoung void
   2662       1.23   dyoung atw_stop(struct ifnet *ifp, int disable)
   2663        1.1   dyoung {
   2664        1.1   dyoung 	struct atw_softc *sc = ifp->if_softc;
   2665        1.3   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   2666        1.1   dyoung 
   2667        1.3   dyoung 	ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
   2668        1.1   dyoung 
   2669        1.1   dyoung 	/* Disable interrupts. */
   2670        1.1   dyoung 	ATW_WRITE(sc, ATW_IER, 0);
   2671        1.1   dyoung 
   2672        1.1   dyoung 	/* Stop the transmit and receive processes. */
   2673        1.1   dyoung 	sc->sc_opmode = 0;
   2674        1.1   dyoung 	ATW_WRITE(sc, ATW_NAR, 0);
   2675       1.70   dyoung 	DELAY(atw_nar_delay);
   2676        1.1   dyoung 	ATW_WRITE(sc, ATW_TDBD, 0);
   2677        1.1   dyoung 	ATW_WRITE(sc, ATW_TDBP, 0);
   2678        1.1   dyoung 	ATW_WRITE(sc, ATW_RDB, 0);
   2679        1.1   dyoung 
   2680       1.36   dyoung 	atw_txdrain(sc);
   2681        1.1   dyoung 
   2682        1.1   dyoung 	if (disable) {
   2683        1.1   dyoung 		atw_rxdrain(sc);
   2684        1.1   dyoung 		atw_disable(sc);
   2685        1.1   dyoung 	}
   2686        1.1   dyoung 
   2687        1.1   dyoung 	/*
   2688        1.1   dyoung 	 * Mark the interface down and cancel the watchdog timer.
   2689        1.1   dyoung 	 */
   2690        1.1   dyoung 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   2691       1.91   dyoung 	sc->sc_tx_timer = 0;
   2692        1.1   dyoung 	ifp->if_timer = 0;
   2693        1.1   dyoung 
   2694       1.36   dyoung 	if (!disable)
   2695       1.36   dyoung 		atw_reset(sc);
   2696        1.1   dyoung }
   2697        1.1   dyoung 
   2698        1.1   dyoung /*
   2699        1.1   dyoung  * atw_rxdrain:
   2700        1.1   dyoung  *
   2701        1.1   dyoung  *	Drain the receive queue.
   2702        1.1   dyoung  */
   2703        1.1   dyoung void
   2704       1.23   dyoung atw_rxdrain(struct atw_softc *sc)
   2705        1.1   dyoung {
   2706        1.1   dyoung 	struct atw_rxsoft *rxs;
   2707        1.1   dyoung 	int i;
   2708        1.1   dyoung 
   2709        1.1   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
   2710        1.1   dyoung 		rxs = &sc->sc_rxsoft[i];
   2711        1.1   dyoung 		if (rxs->rxs_mbuf == NULL)
   2712        1.1   dyoung 			continue;
   2713        1.1   dyoung 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2714        1.1   dyoung 		m_freem(rxs->rxs_mbuf);
   2715        1.1   dyoung 		rxs->rxs_mbuf = NULL;
   2716        1.1   dyoung 	}
   2717        1.1   dyoung }
   2718        1.1   dyoung 
   2719        1.1   dyoung /*
   2720        1.1   dyoung  * atw_detach:
   2721        1.1   dyoung  *
   2722        1.1   dyoung  *	Detach an ADM8211 interface.
   2723        1.1   dyoung  */
   2724        1.1   dyoung int
   2725       1.23   dyoung atw_detach(struct atw_softc *sc)
   2726        1.1   dyoung {
   2727       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   2728        1.1   dyoung 	struct atw_rxsoft *rxs;
   2729        1.1   dyoung 	struct atw_txsoft *txs;
   2730        1.1   dyoung 	int i;
   2731        1.1   dyoung 
   2732        1.1   dyoung 	/*
   2733        1.1   dyoung 	 * Succeed now if there isn't any work to do.
   2734        1.1   dyoung 	 */
   2735        1.1   dyoung 	if ((sc->sc_flags & ATWF_ATTACHED) == 0)
   2736        1.1   dyoung 		return (0);
   2737        1.1   dyoung 
   2738       1.77   dyoung 	callout_stop(&sc->sc_scan_ch);
   2739       1.77   dyoung 
   2740       1.85   dyoung 	ieee80211_ifdetach(&sc->sc_ic);
   2741        1.1   dyoung 	if_detach(ifp);
   2742        1.1   dyoung 
   2743        1.1   dyoung 	for (i = 0; i < ATW_NRXDESC; i++) {
   2744        1.1   dyoung 		rxs = &sc->sc_rxsoft[i];
   2745        1.1   dyoung 		if (rxs->rxs_mbuf != NULL) {
   2746        1.1   dyoung 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2747        1.1   dyoung 			m_freem(rxs->rxs_mbuf);
   2748        1.1   dyoung 			rxs->rxs_mbuf = NULL;
   2749        1.1   dyoung 		}
   2750        1.1   dyoung 		bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap);
   2751        1.1   dyoung 	}
   2752        1.1   dyoung 	for (i = 0; i < ATW_TXQUEUELEN; i++) {
   2753        1.1   dyoung 		txs = &sc->sc_txsoft[i];
   2754        1.1   dyoung 		if (txs->txs_mbuf != NULL) {
   2755        1.1   dyoung 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   2756        1.1   dyoung 			m_freem(txs->txs_mbuf);
   2757        1.1   dyoung 			txs->txs_mbuf = NULL;
   2758        1.1   dyoung 		}
   2759        1.1   dyoung 		bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap);
   2760        1.1   dyoung 	}
   2761        1.1   dyoung 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
   2762        1.1   dyoung 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
   2763        1.1   dyoung 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
   2764        1.1   dyoung 	    sizeof(struct atw_control_data));
   2765        1.1   dyoung 	bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
   2766        1.1   dyoung 
   2767        1.1   dyoung 	shutdownhook_disestablish(sc->sc_sdhook);
   2768        1.1   dyoung 	powerhook_disestablish(sc->sc_powerhook);
   2769        1.1   dyoung 
   2770        1.1   dyoung 	if (sc->sc_srom)
   2771        1.1   dyoung 		free(sc->sc_srom, M_DEVBUF);
   2772        1.1   dyoung 
   2773        1.1   dyoung 	return (0);
   2774        1.1   dyoung }
   2775        1.1   dyoung 
   2776        1.1   dyoung /* atw_shutdown: make sure the interface is stopped at reboot time. */
   2777        1.1   dyoung void
   2778       1.23   dyoung atw_shutdown(void *arg)
   2779        1.1   dyoung {
   2780        1.1   dyoung 	struct atw_softc *sc = arg;
   2781        1.1   dyoung 
   2782       1.85   dyoung 	atw_stop(&sc->sc_if, 1);
   2783        1.1   dyoung }
   2784        1.1   dyoung 
   2785        1.1   dyoung int
   2786       1.23   dyoung atw_intr(void *arg)
   2787        1.1   dyoung {
   2788        1.1   dyoung 	struct atw_softc *sc = arg;
   2789       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   2790        1.1   dyoung 	u_int32_t status, rxstatus, txstatus, linkstatus;
   2791        1.1   dyoung 	int handled = 0, txthresh;
   2792        1.1   dyoung 
   2793        1.1   dyoung #ifdef DEBUG
   2794        1.1   dyoung 	if (ATW_IS_ENABLED(sc) == 0)
   2795        1.1   dyoung 		panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname);
   2796        1.1   dyoung #endif
   2797        1.1   dyoung 
   2798        1.1   dyoung 	/*
   2799        1.1   dyoung 	 * If the interface isn't running, the interrupt couldn't
   2800        1.1   dyoung 	 * possibly have come from us.
   2801        1.1   dyoung 	 */
   2802        1.1   dyoung 	if ((ifp->if_flags & IFF_RUNNING) == 0 ||
   2803  1.105.6.1   simonb 	    !device_is_active(&sc->sc_dev))
   2804        1.1   dyoung 		return (0);
   2805        1.1   dyoung 
   2806        1.1   dyoung 	for (;;) {
   2807        1.1   dyoung 		status = ATW_READ(sc, ATW_STSR);
   2808        1.1   dyoung 
   2809        1.1   dyoung 		if (status)
   2810        1.1   dyoung 			ATW_WRITE(sc, ATW_STSR, status);
   2811        1.1   dyoung 
   2812        1.1   dyoung #ifdef ATW_DEBUG
   2813        1.1   dyoung #define PRINTINTR(flag) do { \
   2814        1.1   dyoung 	if ((status & flag) != 0) { \
   2815        1.1   dyoung 		printf("%s" #flag, delim); \
   2816        1.1   dyoung 		delim = ","; \
   2817        1.1   dyoung 	} \
   2818        1.1   dyoung } while (0)
   2819        1.1   dyoung 
   2820        1.1   dyoung 		if (atw_debug > 1 && status) {
   2821        1.1   dyoung 			const char *delim = "<";
   2822        1.1   dyoung 
   2823        1.1   dyoung 			printf("%s: reg[STSR] = %x",
   2824        1.1   dyoung 			    sc->sc_dev.dv_xname, status);
   2825        1.1   dyoung 
   2826        1.1   dyoung 			PRINTINTR(ATW_INTR_FBE);
   2827        1.1   dyoung 			PRINTINTR(ATW_INTR_LINKOFF);
   2828        1.1   dyoung 			PRINTINTR(ATW_INTR_LINKON);
   2829        1.1   dyoung 			PRINTINTR(ATW_INTR_RCI);
   2830        1.1   dyoung 			PRINTINTR(ATW_INTR_RDU);
   2831       1.15   dyoung 			PRINTINTR(ATW_INTR_REIS);
   2832        1.1   dyoung 			PRINTINTR(ATW_INTR_RPS);
   2833        1.1   dyoung 			PRINTINTR(ATW_INTR_TCI);
   2834        1.1   dyoung 			PRINTINTR(ATW_INTR_TDU);
   2835        1.1   dyoung 			PRINTINTR(ATW_INTR_TLT);
   2836        1.1   dyoung 			PRINTINTR(ATW_INTR_TPS);
   2837        1.1   dyoung 			PRINTINTR(ATW_INTR_TRT);
   2838        1.1   dyoung 			PRINTINTR(ATW_INTR_TUF);
   2839        1.1   dyoung 			PRINTINTR(ATW_INTR_BCNTC);
   2840        1.1   dyoung 			PRINTINTR(ATW_INTR_ATIME);
   2841        1.1   dyoung 			PRINTINTR(ATW_INTR_TBTT);
   2842        1.1   dyoung 			PRINTINTR(ATW_INTR_TSCZ);
   2843        1.1   dyoung 			PRINTINTR(ATW_INTR_TSFTF);
   2844        1.1   dyoung 			printf(">\n");
   2845        1.1   dyoung 		}
   2846        1.1   dyoung #undef PRINTINTR
   2847        1.1   dyoung #endif /* ATW_DEBUG */
   2848        1.1   dyoung 
   2849        1.1   dyoung 		if ((status & sc->sc_inten) == 0)
   2850        1.1   dyoung 			break;
   2851        1.1   dyoung 
   2852        1.1   dyoung 		handled = 1;
   2853        1.1   dyoung 
   2854        1.1   dyoung 		rxstatus = status & sc->sc_rxint_mask;
   2855        1.1   dyoung 		txstatus = status & sc->sc_txint_mask;
   2856        1.1   dyoung 		linkstatus = status & sc->sc_linkint_mask;
   2857        1.1   dyoung 
   2858        1.1   dyoung 		if (linkstatus) {
   2859        1.1   dyoung 			atw_linkintr(sc, linkstatus);
   2860        1.1   dyoung 		}
   2861        1.1   dyoung 
   2862        1.1   dyoung 		if (rxstatus) {
   2863        1.1   dyoung 			/* Grab any new packets. */
   2864        1.1   dyoung 			atw_rxintr(sc);
   2865        1.1   dyoung 
   2866        1.1   dyoung 			if (rxstatus & ATW_INTR_RDU) {
   2867        1.1   dyoung 				printf("%s: receive ring overrun\n",
   2868        1.1   dyoung 				    sc->sc_dev.dv_xname);
   2869        1.1   dyoung 				/* Get the receive process going again. */
   2870        1.1   dyoung 				ATW_WRITE(sc, ATW_RDR, 0x1);
   2871        1.1   dyoung 				break;
   2872        1.1   dyoung 			}
   2873        1.1   dyoung 		}
   2874        1.1   dyoung 
   2875        1.1   dyoung 		if (txstatus) {
   2876        1.1   dyoung 			/* Sweep up transmit descriptors. */
   2877        1.1   dyoung 			atw_txintr(sc);
   2878        1.1   dyoung 
   2879        1.1   dyoung 			if (txstatus & ATW_INTR_TLT)
   2880        1.1   dyoung 				DPRINTF(sc, ("%s: tx lifetime exceeded\n",
   2881        1.1   dyoung 				    sc->sc_dev.dv_xname));
   2882        1.1   dyoung 
   2883        1.1   dyoung 			if (txstatus & ATW_INTR_TRT)
   2884        1.1   dyoung 				DPRINTF(sc, ("%s: tx retry limit exceeded\n",
   2885        1.1   dyoung 				    sc->sc_dev.dv_xname));
   2886        1.1   dyoung 
   2887        1.1   dyoung 			/* If Tx under-run, increase our transmit threshold
   2888        1.1   dyoung 			 * if another is available.
   2889        1.1   dyoung 			 */
   2890        1.1   dyoung 			txthresh = sc->sc_txthresh + 1;
   2891        1.1   dyoung 			if ((txstatus & ATW_INTR_TUF) &&
   2892        1.1   dyoung 			    sc->sc_txth[txthresh].txth_name != NULL) {
   2893        1.1   dyoung 				/* Idle the transmit process. */
   2894        1.1   dyoung 				atw_idle(sc, ATW_NAR_ST);
   2895        1.1   dyoung 
   2896        1.1   dyoung 				sc->sc_txthresh = txthresh;
   2897        1.1   dyoung 				sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF);
   2898        1.1   dyoung 				sc->sc_opmode |=
   2899        1.1   dyoung 				    sc->sc_txth[txthresh].txth_opmode;
   2900        1.1   dyoung 				printf("%s: transmit underrun; new "
   2901        1.1   dyoung 				    "threshold: %s\n", sc->sc_dev.dv_xname,
   2902        1.1   dyoung 				    sc->sc_txth[txthresh].txth_name);
   2903        1.1   dyoung 
   2904        1.1   dyoung 				/* Set the new threshold and restart
   2905        1.1   dyoung 				 * the transmit process.
   2906        1.1   dyoung 				 */
   2907        1.1   dyoung 				ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
   2908       1.70   dyoung 				DELAY(atw_nar_delay);
   2909       1.49   dyoung 				ATW_WRITE(sc, ATW_RDR, 0x1);
   2910        1.1   dyoung 				/* XXX Log every Nth underrun from
   2911        1.1   dyoung 				 * XXX now on?
   2912        1.1   dyoung 				 */
   2913        1.1   dyoung 			}
   2914        1.1   dyoung 		}
   2915        1.1   dyoung 
   2916        1.1   dyoung 		if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) {
   2917        1.1   dyoung 			if (status & ATW_INTR_TPS)
   2918        1.1   dyoung 				printf("%s: transmit process stopped\n",
   2919        1.1   dyoung 				    sc->sc_dev.dv_xname);
   2920        1.1   dyoung 			if (status & ATW_INTR_RPS)
   2921        1.1   dyoung 				printf("%s: receive process stopped\n",
   2922        1.1   dyoung 				    sc->sc_dev.dv_xname);
   2923        1.1   dyoung 			(void)atw_init(ifp);
   2924        1.1   dyoung 			break;
   2925        1.1   dyoung 		}
   2926        1.1   dyoung 
   2927        1.1   dyoung 		if (status & ATW_INTR_FBE) {
   2928        1.1   dyoung 			printf("%s: fatal bus error\n", sc->sc_dev.dv_xname);
   2929        1.1   dyoung 			(void)atw_init(ifp);
   2930        1.1   dyoung 			break;
   2931        1.1   dyoung 		}
   2932        1.1   dyoung 
   2933        1.1   dyoung 		/*
   2934        1.1   dyoung 		 * Not handled:
   2935        1.1   dyoung 		 *
   2936        1.1   dyoung 		 *	Transmit buffer unavailable -- normal
   2937        1.1   dyoung 		 *	condition, nothing to do, really.
   2938        1.1   dyoung 		 *
   2939        1.1   dyoung 		 *	Early receive interrupt -- not available on
   2940        1.1   dyoung 		 *	all chips, we just use RI.  We also only
   2941        1.1   dyoung 		 *	use single-segment receive DMA, so this
   2942        1.1   dyoung 		 *	is mostly useless.
   2943        1.1   dyoung 		 *
   2944        1.1   dyoung 		 *      TBD others
   2945        1.1   dyoung 		 */
   2946        1.1   dyoung 	}
   2947        1.1   dyoung 
   2948        1.1   dyoung 	/* Try to get more packets going. */
   2949        1.1   dyoung 	atw_start(ifp);
   2950        1.1   dyoung 
   2951        1.1   dyoung 	return (handled);
   2952        1.1   dyoung }
   2953        1.1   dyoung 
   2954        1.1   dyoung /*
   2955        1.1   dyoung  * atw_idle:
   2956        1.1   dyoung  *
   2957        1.1   dyoung  *	Cause the transmit and/or receive processes to go idle.
   2958        1.1   dyoung  *
   2959        1.1   dyoung  *      XXX It seems that the ADM8211 will not signal the end of the Rx/Tx
   2960        1.1   dyoung  *	process in STSR if I clear SR or ST after the process has already
   2961        1.1   dyoung  *	ceased. Fair enough. But the Rx process status bits in ATW_TEST0
   2962        1.1   dyoung  *      do not seem to be too reliable. Perhaps I have the sense of the
   2963        1.1   dyoung  *	Rx bits switched with the Tx bits?
   2964        1.1   dyoung  */
   2965        1.1   dyoung void
   2966       1.23   dyoung atw_idle(struct atw_softc *sc, u_int32_t bits)
   2967        1.1   dyoung {
   2968        1.1   dyoung 	u_int32_t ackmask = 0, opmode, stsr, test0;
   2969        1.1   dyoung 	int i, s;
   2970        1.1   dyoung 
   2971       1.84    perry 	s = splnet();
   2972        1.1   dyoung 
   2973        1.1   dyoung 	opmode = sc->sc_opmode & ~bits;
   2974        1.1   dyoung 
   2975        1.1   dyoung 	if (bits & ATW_NAR_SR)
   2976        1.1   dyoung 		ackmask |= ATW_INTR_RPS;
   2977        1.1   dyoung 
   2978        1.1   dyoung 	if (bits & ATW_NAR_ST) {
   2979        1.1   dyoung 		ackmask |= ATW_INTR_TPS;
   2980        1.1   dyoung 		/* set ATW_NAR_HF to flush TX FIFO. */
   2981        1.1   dyoung 		opmode |= ATW_NAR_HF;
   2982        1.1   dyoung 	}
   2983        1.1   dyoung 
   2984        1.1   dyoung 	ATW_WRITE(sc, ATW_NAR, opmode);
   2985       1.70   dyoung 	DELAY(atw_nar_delay);
   2986        1.1   dyoung 
   2987       1.70   dyoung 	for (i = 0; i < 1000; i++) {
   2988        1.1   dyoung 		stsr = ATW_READ(sc, ATW_STSR);
   2989        1.1   dyoung 		if ((stsr & ackmask) == ackmask)
   2990        1.1   dyoung 			break;
   2991       1.70   dyoung 		DELAY(10);
   2992        1.1   dyoung 	}
   2993        1.1   dyoung 
   2994        1.1   dyoung 	ATW_WRITE(sc, ATW_STSR, stsr & ackmask);
   2995        1.1   dyoung 
   2996        1.1   dyoung 	if ((stsr & ackmask) == ackmask)
   2997        1.1   dyoung 		goto out;
   2998        1.1   dyoung 
   2999        1.1   dyoung 	test0 = ATW_READ(sc, ATW_TEST0);
   3000        1.1   dyoung 
   3001        1.1   dyoung 	if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 &&
   3002        1.1   dyoung 	    (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) {
   3003        1.1   dyoung 		printf("%s: transmit process not idle [%s]\n",
   3004        1.1   dyoung 		    sc->sc_dev.dv_xname,
   3005  1.105.6.1   simonb 		    atw_tx_state[SHIFTOUT(test0, ATW_TEST0_TS_MASK)]);
   3006        1.1   dyoung 		printf("%s: bits %08x test0 %08x stsr %08x\n",
   3007        1.1   dyoung 		    sc->sc_dev.dv_xname, bits, test0, stsr);
   3008        1.1   dyoung 	}
   3009        1.1   dyoung 
   3010        1.1   dyoung 	if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 &&
   3011        1.1   dyoung 	    (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) {
   3012        1.1   dyoung 		DPRINTF2(sc, ("%s: receive process not idle [%s]\n",
   3013        1.1   dyoung 		    sc->sc_dev.dv_xname,
   3014  1.105.6.1   simonb 		    atw_rx_state[SHIFTOUT(test0, ATW_TEST0_RS_MASK)]));
   3015        1.1   dyoung 		DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n",
   3016        1.1   dyoung 		    sc->sc_dev.dv_xname, bits, test0, stsr));
   3017        1.1   dyoung 	}
   3018        1.1   dyoung out:
   3019       1.37   dyoung 	if ((bits & ATW_NAR_ST) != 0)
   3020       1.37   dyoung 		atw_txdrain(sc);
   3021        1.1   dyoung 	splx(s);
   3022        1.1   dyoung 	return;
   3023        1.1   dyoung }
   3024        1.1   dyoung 
   3025        1.1   dyoung /*
   3026        1.1   dyoung  * atw_linkintr:
   3027        1.1   dyoung  *
   3028        1.1   dyoung  *	Helper; handle link-status interrupts.
   3029        1.1   dyoung  */
   3030        1.1   dyoung void
   3031       1.23   dyoung atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus)
   3032        1.1   dyoung {
   3033        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   3034        1.1   dyoung 
   3035        1.1   dyoung 	if (ic->ic_state != IEEE80211_S_RUN)
   3036        1.1   dyoung 		return;
   3037        1.1   dyoung 
   3038        1.1   dyoung 	if (linkstatus & ATW_INTR_LINKON) {
   3039        1.1   dyoung 		DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname));
   3040        1.1   dyoung 		sc->sc_rescan_timer = 0;
   3041        1.1   dyoung 	} else if (linkstatus & ATW_INTR_LINKOFF) {
   3042        1.1   dyoung 		DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname));
   3043       1.32   dyoung 		if (ic->ic_opmode != IEEE80211_M_STA)
   3044       1.16   dyoung 			return;
   3045       1.32   dyoung 		sc->sc_rescan_timer = 3;
   3046       1.85   dyoung 		sc->sc_if.if_timer = 1;
   3047        1.1   dyoung 	}
   3048        1.1   dyoung }
   3049        1.1   dyoung 
   3050       1.92    perry static inline int
   3051       1.85   dyoung atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh)
   3052       1.69   dyoung {
   3053       1.72  mycroft 	if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
   3054       1.69   dyoung 		return 0;
   3055       1.69   dyoung 	if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0)
   3056       1.69   dyoung 		return 0;
   3057       1.69   dyoung 	return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0;
   3058       1.69   dyoung }
   3059       1.69   dyoung 
   3060        1.1   dyoung /*
   3061        1.1   dyoung  * atw_rxintr:
   3062        1.1   dyoung  *
   3063        1.1   dyoung  *	Helper; handle receive interrupts.
   3064        1.1   dyoung  */
   3065        1.1   dyoung void
   3066       1.23   dyoung atw_rxintr(struct atw_softc *sc)
   3067        1.1   dyoung {
   3068        1.1   dyoung 	static int rate_tbl[] = {2, 4, 11, 22, 44};
   3069        1.3   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   3070        1.3   dyoung 	struct ieee80211_node *ni;
   3071       1.85   dyoung 	struct ieee80211_frame_min *wh;
   3072       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   3073        1.1   dyoung 	struct atw_rxsoft *rxs;
   3074        1.1   dyoung 	struct mbuf *m;
   3075        1.1   dyoung 	u_int32_t rxstat;
   3076       1.20   dyoung 	int i, len, rate, rate0;
   3077       1.66   dyoung 	u_int32_t rssi, rssi0;
   3078        1.1   dyoung 
   3079        1.1   dyoung 	for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) {
   3080        1.1   dyoung 		rxs = &sc->sc_rxsoft[i];
   3081        1.1   dyoung 
   3082        1.1   dyoung 		ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   3083        1.1   dyoung 
   3084        1.1   dyoung 		rxstat = le32toh(sc->sc_rxdescs[i].ar_stat);
   3085       1.66   dyoung 		rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi);
   3086  1.105.6.1   simonb 		rate0 = SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK);
   3087        1.1   dyoung 
   3088        1.4   dyoung 		if (rxstat & ATW_RXSTAT_OWN)
   3089        1.4   dyoung 			break; /* We have processed all receive buffers. */
   3090        1.1   dyoung 
   3091       1.14   dyoung 		DPRINTF3(sc,
   3092       1.66   dyoung 		    ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n",
   3093       1.14   dyoung 		    sc->sc_dev.dv_xname,
   3094       1.66   dyoung 		    rxstat, rssi0,
   3095       1.45   dyoung 		    le32toh(sc->sc_rxdescs[i].ar_buf1),
   3096       1.45   dyoung 		    le32toh(sc->sc_rxdescs[i].ar_buf2)));
   3097        1.1   dyoung 
   3098        1.1   dyoung 		/*
   3099       1.29   dyoung 		 * Make sure the packet fits in one buffer.  This should
   3100        1.1   dyoung 		 * always be the case.
   3101        1.1   dyoung 		 */
   3102        1.1   dyoung 		if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) !=
   3103        1.1   dyoung 		    (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) {
   3104        1.1   dyoung 			printf("%s: incoming packet spilled, resetting\n",
   3105        1.1   dyoung 			    sc->sc_dev.dv_xname);
   3106        1.1   dyoung 			(void)atw_init(ifp);
   3107        1.1   dyoung 			return;
   3108        1.1   dyoung 		}
   3109        1.1   dyoung 
   3110        1.1   dyoung 		/*
   3111        1.1   dyoung 		 * If an error occurred, update stats, clear the status
   3112        1.1   dyoung 		 * word, and leave the packet buffer in place.  It will
   3113        1.1   dyoung 		 * simply be reused the next time the ring comes around.
   3114        1.1   dyoung 	 	 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long
   3115        1.1   dyoung 		 * error.
   3116        1.1   dyoung 		 */
   3117        1.1   dyoung 
   3118        1.1   dyoung 		if ((rxstat & ATW_RXSTAT_ES) != 0 &&
   3119       1.85   dyoung 		    ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 ||
   3120        1.1   dyoung 		     (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE |
   3121        1.1   dyoung 		                ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E |
   3122        1.1   dyoung 				ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E |
   3123        1.1   dyoung 				ATW_RXSTAT_ICVE)) != 0)) {
   3124        1.1   dyoung #define	PRINTERR(bit, str)						\
   3125        1.1   dyoung 			if (rxstat & (bit))				\
   3126        1.1   dyoung 				printf("%s: receive error: %s\n",	\
   3127        1.1   dyoung 				    sc->sc_dev.dv_xname, str)
   3128        1.1   dyoung 			ifp->if_ierrors++;
   3129        1.1   dyoung 			PRINTERR(ATW_RXSTAT_DE, "descriptor error");
   3130        1.1   dyoung 			PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error");
   3131        1.1   dyoung 			PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error");
   3132        1.1   dyoung 			PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error");
   3133        1.1   dyoung 			PRINTERR(ATW_RXSTAT_RXTOE, "time-out");
   3134        1.1   dyoung 			PRINTERR(ATW_RXSTAT_CRC32E, "FCS error");
   3135        1.1   dyoung 			PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error");
   3136        1.1   dyoung #undef PRINTERR
   3137        1.1   dyoung 			ATW_INIT_RXDESC(sc, i);
   3138        1.1   dyoung 			continue;
   3139        1.1   dyoung 		}
   3140        1.1   dyoung 
   3141        1.1   dyoung 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   3142        1.1   dyoung 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   3143        1.1   dyoung 
   3144        1.1   dyoung 		/*
   3145        1.1   dyoung 		 * No errors; receive the packet.  Note the ADM8211
   3146        1.1   dyoung 		 * includes the CRC in promiscuous mode.
   3147        1.1   dyoung 		 */
   3148  1.105.6.1   simonb 		len = SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK);
   3149        1.1   dyoung 
   3150        1.1   dyoung 		/*
   3151        1.1   dyoung 		 * Allocate a new mbuf cluster.  If that fails, we are
   3152        1.1   dyoung 		 * out of memory, and must drop the packet and recycle
   3153        1.1   dyoung 		 * the buffer that's already attached to this descriptor.
   3154        1.1   dyoung 		 */
   3155        1.1   dyoung 		m = rxs->rxs_mbuf;
   3156        1.1   dyoung 		if (atw_add_rxbuf(sc, i) != 0) {
   3157        1.1   dyoung 			ifp->if_ierrors++;
   3158        1.1   dyoung 			ATW_INIT_RXDESC(sc, i);
   3159        1.1   dyoung 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   3160        1.1   dyoung 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   3161        1.1   dyoung 			continue;
   3162        1.1   dyoung 		}
   3163        1.1   dyoung 
   3164        1.1   dyoung 		ifp->if_ipackets++;
   3165        1.1   dyoung 		if (sc->sc_opmode & ATW_NAR_PR)
   3166       1.83  thorpej 			len -= IEEE80211_CRC_LEN;
   3167        1.1   dyoung 		m->m_pkthdr.rcvif = ifp;
   3168       1.46   dyoung 		m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len);
   3169        1.1   dyoung 
   3170        1.1   dyoung 		if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0]))
   3171        1.1   dyoung 			rate = 0;
   3172        1.1   dyoung 		else
   3173        1.1   dyoung 			rate = rate_tbl[rate0];
   3174        1.1   dyoung 
   3175       1.66   dyoung 		/* The RSSI comes straight from a register in the
   3176       1.66   dyoung 		 * baseband processor.  I know that for the RF3000,
   3177       1.66   dyoung 		 * the RSSI register also contains the antenna-selection
   3178       1.66   dyoung 		 * bits.  Mask those off.
   3179       1.66   dyoung 		 *
   3180       1.66   dyoung 		 * TBD Treat other basebands.
   3181       1.66   dyoung 		 */
   3182       1.66   dyoung 		if (sc->sc_bbptype == ATW_BBPTYPE_RFMD)
   3183       1.66   dyoung 			rssi = rssi0 & RF3000_RSSI_MASK;
   3184       1.66   dyoung 		else
   3185       1.66   dyoung 			rssi = rssi0;
   3186       1.66   dyoung 
   3187       1.12   dyoung  #if NBPFILTER > 0
   3188       1.12   dyoung 		/* Pass this up to any BPF listeners. */
   3189       1.12   dyoung 		if (sc->sc_radiobpf != NULL) {
   3190       1.12   dyoung 			struct atw_rx_radiotap_header *tap = &sc->sc_rxtap;
   3191       1.12   dyoung 
   3192       1.12   dyoung 			tap->ar_rate = rate;
   3193  1.105.6.1   simonb 			tap->ar_chan_freq = htole16(ic->ic_curchan->ic_freq);
   3194  1.105.6.1   simonb 			tap->ar_chan_flags = htole16(ic->ic_curchan->ic_flags);
   3195       1.12   dyoung 
   3196       1.12   dyoung 			/* TBD verify units are dB */
   3197       1.20   dyoung 			tap->ar_antsignal = (int)rssi;
   3198       1.12   dyoung 			/* TBD tap->ar_flags */
   3199       1.12   dyoung 
   3200       1.25   dyoung 			bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap,
   3201       1.25   dyoung 			    tap->ar_ihdr.it_len, m);
   3202       1.12   dyoung  		}
   3203       1.12   dyoung  #endif /* NPBFILTER > 0 */
   3204        1.1   dyoung 
   3205       1.85   dyoung 		wh = mtod(m, struct ieee80211_frame_min *);
   3206        1.8   dyoung 		ni = ieee80211_find_rxnode(ic, wh);
   3207  1.105.6.1   simonb #if 0
   3208       1.85   dyoung 		if (atw_hw_decrypted(sc, wh)) {
   3209       1.69   dyoung 			wh->i_fc[1] &= ~IEEE80211_FC1_WEP;
   3210       1.85   dyoung 			DPRINTF(sc, ("%s: hw decrypted\n", __func__));
   3211       1.85   dyoung 		}
   3212  1.105.6.1   simonb #endif
   3213       1.85   dyoung 		ieee80211_input(ic, m, ni, (int)rssi, 0);
   3214       1.85   dyoung 		ieee80211_free_node(ni);
   3215        1.1   dyoung 	}
   3216        1.1   dyoung 
   3217        1.1   dyoung 	/* Update the receive pointer. */
   3218        1.1   dyoung 	sc->sc_rxptr = i;
   3219        1.1   dyoung }
   3220        1.1   dyoung 
   3221        1.1   dyoung /*
   3222        1.1   dyoung  * atw_txintr:
   3223        1.1   dyoung  *
   3224        1.1   dyoung  *	Helper; handle transmit interrupts.
   3225        1.1   dyoung  */
   3226        1.1   dyoung void
   3227       1.23   dyoung atw_txintr(struct atw_softc *sc)
   3228        1.1   dyoung {
   3229        1.1   dyoung #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \
   3230        1.1   dyoung     ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR)
   3231        1.1   dyoung #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \
   3232        1.1   dyoung     "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT"
   3233        1.1   dyoung 
   3234        1.1   dyoung 	static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)];
   3235       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   3236        1.1   dyoung 	struct atw_txsoft *txs;
   3237        1.1   dyoung 	u_int32_t txstat;
   3238        1.1   dyoung 
   3239        1.1   dyoung 	DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n",
   3240        1.1   dyoung 	    sc->sc_dev.dv_xname, sc->sc_flags));
   3241        1.1   dyoung 
   3242        1.1   dyoung 	/*
   3243        1.1   dyoung 	 * Go through our Tx list and free mbufs for those
   3244        1.1   dyoung 	 * frames that have been transmitted.
   3245        1.1   dyoung 	 */
   3246        1.1   dyoung 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
   3247       1.48   dyoung 		ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1,
   3248        1.1   dyoung 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   3249        1.1   dyoung 
   3250        1.1   dyoung #ifdef ATW_DEBUG
   3251        1.1   dyoung 		if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
   3252        1.1   dyoung 			int i;
   3253        1.1   dyoung 			printf("    txsoft %p transmit chain:\n", txs);
   3254       1.48   dyoung 			ATW_CDTXSYNC(sc, txs->txs_firstdesc,
   3255       1.48   dyoung 			    txs->txs_ndescs - 1,
   3256       1.48   dyoung 			    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   3257        1.1   dyoung 			for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) {
   3258        1.1   dyoung 				printf("     descriptor %d:\n", i);
   3259        1.1   dyoung 				printf("       at_status:   0x%08x\n",
   3260        1.1   dyoung 				    le32toh(sc->sc_txdescs[i].at_stat));
   3261        1.1   dyoung 				printf("       at_flags:      0x%08x\n",
   3262        1.1   dyoung 				    le32toh(sc->sc_txdescs[i].at_flags));
   3263        1.1   dyoung 				printf("       at_buf1: 0x%08x\n",
   3264        1.1   dyoung 				    le32toh(sc->sc_txdescs[i].at_buf1));
   3265        1.1   dyoung 				printf("       at_buf2: 0x%08x\n",
   3266        1.1   dyoung 				    le32toh(sc->sc_txdescs[i].at_buf2));
   3267        1.1   dyoung 				if (i == txs->txs_lastdesc)
   3268        1.1   dyoung 					break;
   3269        1.1   dyoung 			}
   3270        1.1   dyoung 		}
   3271        1.1   dyoung #endif
   3272        1.1   dyoung 
   3273        1.1   dyoung 		txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat);
   3274        1.1   dyoung 		if (txstat & ATW_TXSTAT_OWN)
   3275        1.1   dyoung 			break;
   3276        1.1   dyoung 
   3277        1.1   dyoung 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
   3278        1.1   dyoung 
   3279        1.1   dyoung 		sc->sc_txfree += txs->txs_ndescs;
   3280        1.1   dyoung 
   3281        1.1   dyoung 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   3282        1.1   dyoung 		    0, txs->txs_dmamap->dm_mapsize,
   3283        1.1   dyoung 		    BUS_DMASYNC_POSTWRITE);
   3284        1.1   dyoung 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   3285        1.1   dyoung 		m_freem(txs->txs_mbuf);
   3286        1.1   dyoung 		txs->txs_mbuf = NULL;
   3287        1.1   dyoung 
   3288        1.1   dyoung 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
   3289        1.1   dyoung 
   3290      1.102   dyoung 		KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) ||
   3291      1.102   dyoung 		        sc->sc_txfree == 0));
   3292       1.91   dyoung 		ifp->if_flags &= ~IFF_OACTIVE;
   3293       1.91   dyoung 
   3294        1.1   dyoung 		if ((ifp->if_flags & IFF_DEBUG) != 0 &&
   3295        1.1   dyoung 		    (txstat & TXSTAT_ERRMASK) != 0) {
   3296        1.1   dyoung 			bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT,
   3297        1.1   dyoung 			    txstat_buf, sizeof(txstat_buf));
   3298        1.1   dyoung 			printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname,
   3299        1.1   dyoung 			    txstat_buf,
   3300  1.105.6.1   simonb 			    SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK));
   3301        1.1   dyoung 		}
   3302        1.1   dyoung 
   3303        1.1   dyoung 		/*
   3304        1.1   dyoung 		 * Check for errors and collisions.
   3305        1.1   dyoung 		 */
   3306        1.1   dyoung 		if (txstat & ATW_TXSTAT_TUF)
   3307        1.1   dyoung 			sc->sc_stats.ts_tx_tuf++;
   3308        1.1   dyoung 		if (txstat & ATW_TXSTAT_TLT)
   3309        1.1   dyoung 			sc->sc_stats.ts_tx_tlt++;
   3310        1.1   dyoung 		if (txstat & ATW_TXSTAT_TRT)
   3311        1.1   dyoung 			sc->sc_stats.ts_tx_trt++;
   3312        1.1   dyoung 		if (txstat & ATW_TXSTAT_TRO)
   3313        1.1   dyoung 			sc->sc_stats.ts_tx_tro++;
   3314        1.1   dyoung 		if (txstat & ATW_TXSTAT_SOFBR) {
   3315        1.1   dyoung 			sc->sc_stats.ts_tx_sofbr++;
   3316        1.1   dyoung 		}
   3317        1.1   dyoung 
   3318        1.1   dyoung 		if ((txstat & ATW_TXSTAT_ES) == 0)
   3319        1.1   dyoung 			ifp->if_collisions +=
   3320  1.105.6.1   simonb 			    SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK);
   3321        1.1   dyoung 		else
   3322        1.1   dyoung 			ifp->if_oerrors++;
   3323        1.1   dyoung 
   3324        1.1   dyoung 		ifp->if_opackets++;
   3325        1.1   dyoung 	}
   3326        1.1   dyoung 
   3327        1.1   dyoung 	/*
   3328        1.1   dyoung 	 * If there are no more pending transmissions, cancel the watchdog
   3329        1.1   dyoung 	 * timer.
   3330        1.1   dyoung 	 */
   3331      1.102   dyoung 	if (txs == NULL) {
   3332      1.102   dyoung 		KASSERT((ifp->if_flags & IFF_OACTIVE) == 0);
   3333        1.1   dyoung 		sc->sc_tx_timer = 0;
   3334      1.102   dyoung 	}
   3335        1.1   dyoung #undef TXSTAT_ERRMASK
   3336        1.1   dyoung #undef TXSTAT_FMT
   3337        1.1   dyoung }
   3338        1.1   dyoung 
   3339        1.1   dyoung /*
   3340        1.1   dyoung  * atw_watchdog:	[ifnet interface function]
   3341        1.1   dyoung  *
   3342        1.1   dyoung  *	Watchdog timer handler.
   3343        1.1   dyoung  */
   3344        1.1   dyoung void
   3345       1.23   dyoung atw_watchdog(struct ifnet *ifp)
   3346        1.1   dyoung {
   3347        1.1   dyoung 	struct atw_softc *sc = ifp->if_softc;
   3348        1.3   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   3349        1.1   dyoung 
   3350        1.1   dyoung 	ifp->if_timer = 0;
   3351        1.1   dyoung 	if (ATW_IS_ENABLED(sc) == 0)
   3352        1.1   dyoung 		return;
   3353        1.1   dyoung 
   3354        1.1   dyoung 	if (sc->sc_rescan_timer) {
   3355        1.1   dyoung 		if (--sc->sc_rescan_timer == 0)
   3356        1.3   dyoung 			(void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
   3357        1.1   dyoung 	}
   3358        1.1   dyoung 	if (sc->sc_tx_timer) {
   3359        1.1   dyoung 		if (--sc->sc_tx_timer == 0 &&
   3360        1.1   dyoung 		    !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) {
   3361        1.1   dyoung 			printf("%s: transmit timeout\n", ifp->if_xname);
   3362        1.1   dyoung 			ifp->if_oerrors++;
   3363        1.1   dyoung 			(void)atw_init(ifp);
   3364        1.1   dyoung 			atw_start(ifp);
   3365        1.1   dyoung 		}
   3366        1.1   dyoung 	}
   3367        1.1   dyoung 	if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0)
   3368        1.1   dyoung 		ifp->if_timer = 1;
   3369       1.85   dyoung 	ieee80211_watchdog(ic);
   3370        1.1   dyoung }
   3371        1.1   dyoung 
   3372        1.1   dyoung #ifdef ATW_DEBUG
   3373        1.1   dyoung static void
   3374        1.1   dyoung atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0)
   3375        1.1   dyoung {
   3376        1.1   dyoung 	struct atw_softc *sc = ifp->if_softc;
   3377        1.1   dyoung 	struct mbuf *m;
   3378        1.1   dyoung 	int i, noctets = 0;
   3379        1.1   dyoung 
   3380        1.1   dyoung 	printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname,
   3381        1.1   dyoung 	    m0->m_pkthdr.len);
   3382        1.1   dyoung 
   3383        1.1   dyoung 	for (m = m0; m; m = m->m_next) {
   3384        1.1   dyoung 		if (m->m_len == 0)
   3385        1.1   dyoung 			continue;
   3386        1.1   dyoung 		for (i = 0; i < m->m_len; i++) {
   3387        1.1   dyoung 			printf(" %02x", ((u_int8_t*)m->m_data)[i]);
   3388        1.1   dyoung 			if (++noctets % 24 == 0)
   3389        1.1   dyoung 				printf("\n");
   3390        1.1   dyoung 		}
   3391        1.1   dyoung 	}
   3392        1.1   dyoung 	printf("%s%s: %d bytes emitted\n",
   3393        1.1   dyoung 	    (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets);
   3394        1.1   dyoung }
   3395        1.1   dyoung #endif /* ATW_DEBUG */
   3396        1.1   dyoung 
   3397        1.1   dyoung /*
   3398        1.1   dyoung  * atw_start:		[ifnet interface function]
   3399        1.1   dyoung  *
   3400        1.1   dyoung  *	Start packet transmission on the interface.
   3401        1.1   dyoung  */
   3402        1.1   dyoung void
   3403       1.23   dyoung atw_start(struct ifnet *ifp)
   3404        1.1   dyoung {
   3405        1.1   dyoung 	struct atw_softc *sc = ifp->if_softc;
   3406       1.93   dyoung 	struct ieee80211_key *k;
   3407        1.1   dyoung 	struct ieee80211com *ic = &sc->sc_ic;
   3408        1.3   dyoung 	struct ieee80211_node *ni;
   3409       1.93   dyoung 	struct ieee80211_frame_min *whm;
   3410        1.3   dyoung 	struct ieee80211_frame *wh;
   3411        1.1   dyoung 	struct atw_frame *hh;
   3412        1.3   dyoung 	struct mbuf *m0, *m;
   3413        1.1   dyoung 	struct atw_txsoft *txs, *last_txs;
   3414        1.1   dyoung 	struct atw_txdesc *txd;
   3415  1.105.6.1   simonb 	int npkt, rate;
   3416        1.1   dyoung 	bus_dmamap_t dmamap;
   3417  1.105.6.1   simonb 	int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg;
   3418        1.1   dyoung 
   3419        1.1   dyoung 	DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n",
   3420        1.1   dyoung 	    sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags));
   3421        1.1   dyoung 
   3422        1.1   dyoung 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
   3423        1.1   dyoung 		return;
   3424        1.1   dyoung 
   3425        1.1   dyoung 	/*
   3426        1.1   dyoung 	 * Remember the previous number of free descriptors and
   3427        1.1   dyoung 	 * the first descriptor we'll use.
   3428        1.1   dyoung 	 */
   3429        1.1   dyoung 	ofree = sc->sc_txfree;
   3430  1.105.6.1   simonb 	firsttx = lasttx = sc->sc_txnext;
   3431        1.1   dyoung 
   3432        1.1   dyoung 	DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n",
   3433        1.1   dyoung 	    sc->sc_dev.dv_xname, ofree, firsttx));
   3434        1.1   dyoung 
   3435        1.1   dyoung 	/*
   3436        1.1   dyoung 	 * Loop through the send queue, setting up transmit descriptors
   3437        1.1   dyoung 	 * until we drain the queue, or use up all available transmit
   3438        1.1   dyoung 	 * descriptors.
   3439        1.1   dyoung 	 */
   3440        1.1   dyoung 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
   3441        1.1   dyoung 	       sc->sc_txfree != 0) {
   3442        1.1   dyoung 
   3443        1.1   dyoung 		/*
   3444        1.1   dyoung 		 * Grab a packet off the management queue, if it
   3445        1.1   dyoung 		 * is not empty. Otherwise, from the data queue.
   3446        1.1   dyoung 		 */
   3447        1.3   dyoung 		IF_DEQUEUE(&ic->ic_mgtq, m0);
   3448        1.3   dyoung 		if (m0 != NULL) {
   3449        1.3   dyoung 			ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif;
   3450        1.3   dyoung 			m0->m_pkthdr.rcvif = NULL;
   3451       1.99   dyoung 		} else if (ic->ic_state != IEEE80211_S_RUN)
   3452       1.99   dyoung 			break; /* send no data until associated */
   3453       1.99   dyoung 		else {
   3454        1.3   dyoung 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   3455        1.1   dyoung 			if (m0 == NULL)
   3456        1.1   dyoung 				break;
   3457        1.1   dyoung #if NBPFILTER > 0
   3458        1.1   dyoung 			if (ifp->if_bpf != NULL)
   3459        1.1   dyoung 				bpf_mtap(ifp->if_bpf, m0);
   3460        1.1   dyoung #endif /* NBPFILTER > 0 */
   3461       1.85   dyoung 			ni = ieee80211_find_txnode(ic,
   3462       1.85   dyoung 			    mtod(m0, struct ether_header *)->ether_dhost);
   3463       1.85   dyoung 			if (ni == NULL) {
   3464       1.85   dyoung 				ifp->if_oerrors++;
   3465       1.85   dyoung 				break;
   3466       1.85   dyoung 			}
   3467       1.85   dyoung 			if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) {
   3468       1.85   dyoung 				ieee80211_free_node(ni);
   3469        1.1   dyoung 				ifp->if_oerrors++;
   3470        1.3   dyoung 				break;
   3471        1.1   dyoung 			}
   3472        1.1   dyoung 		}
   3473        1.1   dyoung 
   3474  1.105.6.1   simonb 		rate = MAX(ieee80211_get_rate(ni), 2);
   3475       1.12   dyoung 
   3476       1.93   dyoung 		whm = mtod(m0, struct ieee80211_frame_min *);
   3477       1.93   dyoung 
   3478  1.105.6.1   simonb 		if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0)
   3479       1.93   dyoung 			k = NULL;
   3480  1.105.6.1   simonb 		else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
   3481  1.105.6.1   simonb 			m_freem(m0);
   3482  1.105.6.1   simonb 			ieee80211_free_node(ni);
   3483  1.105.6.1   simonb 			ifp->if_oerrors++;
   3484  1.105.6.1   simonb 			break;
   3485  1.105.6.1   simonb 		}
   3486       1.93   dyoung 
   3487       1.93   dyoung 		if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len,
   3488       1.93   dyoung 		    ic->ic_flags, ic->ic_fragthreshold, rate,
   3489       1.93   dyoung 		    &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) {
   3490       1.93   dyoung 			DPRINTF2(sc, ("%s: fail compute duration\n", __func__));
   3491       1.93   dyoung 			m_freem(m0);
   3492       1.93   dyoung 			break;
   3493       1.93   dyoung 		}
   3494       1.93   dyoung 
   3495       1.93   dyoung 		/* XXX Misleading if fragmentation is enabled.  Better
   3496       1.93   dyoung 		 * to fragment in software?
   3497       1.93   dyoung 		 */
   3498       1.93   dyoung 		*(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur);
   3499       1.93   dyoung 
   3500        1.1   dyoung #if NBPFILTER > 0
   3501        1.1   dyoung 		/*
   3502        1.1   dyoung 		 * Pass the packet to any BPF listeners.
   3503        1.1   dyoung 		 */
   3504        1.1   dyoung 		if (ic->ic_rawbpf != NULL)
   3505        1.1   dyoung 			bpf_mtap((caddr_t)ic->ic_rawbpf, m0);
   3506       1.12   dyoung 
   3507       1.12   dyoung 		if (sc->sc_radiobpf != NULL) {
   3508       1.12   dyoung 			struct atw_tx_radiotap_header *tap = &sc->sc_txtap;
   3509       1.12   dyoung 
   3510       1.12   dyoung 			tap->at_rate = rate;
   3511  1.105.6.1   simonb 			tap->at_chan_freq = htole16(ic->ic_curchan->ic_freq);
   3512  1.105.6.1   simonb 			tap->at_chan_flags = htole16(ic->ic_curchan->ic_flags);
   3513       1.12   dyoung 
   3514       1.12   dyoung 			/* TBD tap->at_flags */
   3515       1.12   dyoung 
   3516       1.25   dyoung 			bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap,
   3517       1.25   dyoung 			    tap->at_ihdr.it_len, m0);
   3518       1.12   dyoung 		}
   3519        1.1   dyoung #endif /* NBPFILTER > 0 */
   3520        1.1   dyoung 
   3521        1.1   dyoung 		M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT);
   3522        1.1   dyoung 
   3523       1.79   dyoung 		if (ni != NULL)
   3524       1.85   dyoung 			ieee80211_free_node(ni);
   3525        1.3   dyoung 
   3526        1.1   dyoung 		if (m0 == NULL) {
   3527        1.1   dyoung 			ifp->if_oerrors++;
   3528        1.3   dyoung 			break;
   3529        1.1   dyoung 		}
   3530        1.1   dyoung 
   3531        1.1   dyoung 		/* just to make sure. */
   3532        1.1   dyoung 		m0 = m_pullup(m0, sizeof(struct atw_frame));
   3533        1.1   dyoung 
   3534        1.1   dyoung 		if (m0 == NULL) {
   3535        1.1   dyoung 			ifp->if_oerrors++;
   3536        1.3   dyoung 			break;
   3537        1.1   dyoung 		}
   3538        1.1   dyoung 
   3539        1.1   dyoung 		hh = mtod(m0, struct atw_frame *);
   3540        1.1   dyoung 		wh = &hh->atw_ihdr;
   3541        1.1   dyoung 
   3542        1.1   dyoung 		/* Copy everything we need from the 802.11 header:
   3543        1.1   dyoung 		 * Frame Control; address 1, address 3, or addresses
   3544        1.1   dyoung 		 * 3 and 4. NIC fills in BSSID, SA.
   3545        1.1   dyoung 		 */
   3546        1.1   dyoung 		if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) {
   3547        1.3   dyoung 			if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS)
   3548        1.3   dyoung 				panic("%s: illegal WDS frame",
   3549        1.3   dyoung 				    sc->sc_dev.dv_xname);
   3550        1.1   dyoung 			memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN);
   3551        1.1   dyoung 		} else
   3552        1.1   dyoung 			memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN);
   3553        1.1   dyoung 
   3554        1.1   dyoung 		*(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc;
   3555        1.1   dyoung 
   3556        1.3   dyoung 		/* initialize remaining Tx parameters */
   3557        1.3   dyoung 		memset(&hh->u, 0, sizeof(hh->u));
   3558        1.1   dyoung 
   3559        1.1   dyoung 		hh->atw_rate = rate * 5;
   3560        1.1   dyoung 		/* XXX this could be incorrect if M_FCS. _encap should
   3561        1.1   dyoung 		 * probably strip FCS just in case it sticks around in
   3562        1.1   dyoung 		 * bridged packets.
   3563        1.1   dyoung 		 */
   3564       1.81  mycroft 		hh->atw_service = 0x00; /* XXX guess */
   3565        1.1   dyoung 		hh->atw_paylen = htole16(m0->m_pkthdr.len -
   3566        1.1   dyoung 		    sizeof(struct atw_frame));
   3567        1.1   dyoung 
   3568       1.95   dyoung 		hh->atw_fragthr = htole16(ic->ic_fragthreshold);
   3569        1.1   dyoung 		hh->atw_rtylmt = 3;
   3570        1.1   dyoung 		hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1);
   3571  1.105.6.1   simonb #if 0
   3572        1.1   dyoung 		if (do_encrypt) {
   3573        1.1   dyoung 			hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP);
   3574       1.85   dyoung 			hh->atw_keyid = ic->ic_def_txkey;
   3575        1.1   dyoung 		}
   3576  1.105.6.1   simonb #endif
   3577        1.1   dyoung 
   3578       1.93   dyoung 		hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len);
   3579       1.93   dyoung 		hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len);
   3580       1.93   dyoung 		if (txs->txs_d0.d_residue)
   3581       1.93   dyoung 			hh->atw_head_plcplen |= htole16(0x8000);
   3582       1.93   dyoung 		if (txs->txs_dn.d_residue)
   3583       1.93   dyoung 			hh->atw_tail_plcplen |= htole16(0x8000);
   3584       1.93   dyoung 		hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur);
   3585       1.93   dyoung 		hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur);
   3586        1.1   dyoung 
   3587        1.1   dyoung 		/* never fragment multicast frames */
   3588        1.1   dyoung 		if (IEEE80211_IS_MULTICAST(hh->atw_dst)) {
   3589       1.95   dyoung 			hh->atw_fragthr = htole16(ic->ic_fragthreshold);
   3590        1.1   dyoung 		} else if (sc->sc_flags & ATWF_RTSCTS) {
   3591        1.1   dyoung 			hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS);
   3592        1.1   dyoung 		}
   3593        1.1   dyoung 
   3594        1.1   dyoung #ifdef ATW_DEBUG
   3595        1.1   dyoung 		hh->atw_fragnum = 0;
   3596        1.1   dyoung 
   3597        1.1   dyoung 		if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
   3598        1.1   dyoung 			printf("%s: dst = %s, rate = 0x%02x, "
   3599        1.1   dyoung 			    "service = 0x%02x, paylen = 0x%04x\n",
   3600        1.1   dyoung 			    sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst),
   3601        1.1   dyoung 			    hh->atw_rate, hh->atw_service, hh->atw_paylen);
   3602        1.1   dyoung 
   3603        1.1   dyoung 			printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, "
   3604        1.1   dyoung 			    "dur1 = 0x%04x, dur2 = 0x%04x, "
   3605        1.1   dyoung 			    "dur3 = 0x%04x, rts_dur = 0x%04x\n",
   3606        1.1   dyoung 			    sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1],
   3607        1.1   dyoung 			    hh->atw_tail_plcplen, hh->atw_head_plcplen,
   3608        1.1   dyoung 			    hh->atw_tail_dur, hh->atw_head_dur);
   3609        1.1   dyoung 
   3610        1.1   dyoung 			printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, "
   3611        1.1   dyoung 			    "fragnum = 0x%02x, rtylmt = 0x%04x\n",
   3612        1.1   dyoung 			    sc->sc_dev.dv_xname, hh->atw_hdrctl,
   3613        1.1   dyoung 			    hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt);
   3614        1.1   dyoung 
   3615        1.1   dyoung 			printf("%s: keyid = %d\n",
   3616        1.1   dyoung 			    sc->sc_dev.dv_xname, hh->atw_keyid);
   3617        1.1   dyoung 
   3618        1.1   dyoung 			atw_dump_pkt(ifp, m0);
   3619        1.1   dyoung 		}
   3620        1.1   dyoung #endif /* ATW_DEBUG */
   3621        1.1   dyoung 
   3622        1.1   dyoung 		dmamap = txs->txs_dmamap;
   3623        1.1   dyoung 
   3624        1.1   dyoung 		/*
   3625        1.3   dyoung 		 * Load the DMA map.  Copy and try (once) again if the packet
   3626        1.3   dyoung 		 * didn't fit in the alloted number of segments.
   3627        1.1   dyoung 		 */
   3628        1.3   dyoung 		for (first = 1;
   3629        1.3   dyoung 		     (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   3630        1.3   dyoung 		                  BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first;
   3631        1.3   dyoung 		     first = 0) {
   3632        1.1   dyoung 			MGETHDR(m, M_DONTWAIT, MT_DATA);
   3633        1.1   dyoung 			if (m == NULL) {
   3634        1.1   dyoung 				printf("%s: unable to allocate Tx mbuf\n",
   3635        1.1   dyoung 				    sc->sc_dev.dv_xname);
   3636        1.1   dyoung 				break;
   3637        1.1   dyoung 			}
   3638        1.1   dyoung 			if (m0->m_pkthdr.len > MHLEN) {
   3639        1.1   dyoung 				MCLGET(m, M_DONTWAIT);
   3640        1.1   dyoung 				if ((m->m_flags & M_EXT) == 0) {
   3641        1.1   dyoung 					printf("%s: unable to allocate Tx "
   3642        1.1   dyoung 					    "cluster\n", sc->sc_dev.dv_xname);
   3643        1.1   dyoung 					m_freem(m);
   3644        1.1   dyoung 					break;
   3645        1.1   dyoung 				}
   3646        1.1   dyoung 			}
   3647        1.1   dyoung 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
   3648        1.1   dyoung 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
   3649        1.3   dyoung 			m_freem(m0);
   3650        1.3   dyoung 			m0 = m;
   3651        1.3   dyoung 			m = NULL;
   3652        1.3   dyoung 		}
   3653        1.3   dyoung 		if (error != 0) {
   3654        1.3   dyoung 			printf("%s: unable to load Tx buffer, "
   3655        1.3   dyoung 			    "error = %d\n", sc->sc_dev.dv_xname, error);
   3656        1.3   dyoung 			m_freem(m0);
   3657        1.3   dyoung 			break;
   3658        1.1   dyoung 		}
   3659        1.1   dyoung 
   3660        1.1   dyoung 		/*
   3661        1.1   dyoung 		 * Ensure we have enough descriptors free to describe
   3662        1.1   dyoung 		 * the packet.
   3663        1.1   dyoung 		 */
   3664        1.1   dyoung 		if (dmamap->dm_nsegs > sc->sc_txfree) {
   3665        1.1   dyoung 			/*
   3666        1.3   dyoung 			 * Not enough free descriptors to transmit
   3667        1.3   dyoung 			 * this packet.  Unload the DMA map and
   3668        1.3   dyoung 			 * drop the packet.  Notify the upper layer
   3669        1.3   dyoung 			 * that there are no more slots left.
   3670        1.1   dyoung 			 *
   3671        1.1   dyoung 			 * XXX We could allocate an mbuf and copy, but
   3672        1.1   dyoung 			 * XXX it is worth it?
   3673        1.1   dyoung 			 */
   3674        1.1   dyoung 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   3675        1.3   dyoung 			m_freem(m0);
   3676        1.1   dyoung 			break;
   3677        1.1   dyoung 		}
   3678        1.1   dyoung 
   3679        1.1   dyoung 		/*
   3680        1.1   dyoung 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   3681        1.1   dyoung 		 */
   3682        1.1   dyoung 
   3683        1.1   dyoung 		/* Sync the DMA map. */
   3684        1.1   dyoung 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   3685        1.1   dyoung 		    BUS_DMASYNC_PREWRITE);
   3686        1.1   dyoung 
   3687        1.1   dyoung 		/* XXX arbitrary retry limit; 8 because I have seen it in
   3688        1.1   dyoung 		 * use already and maybe 0 means "no tries" !
   3689        1.1   dyoung 		 */
   3690  1.105.6.1   simonb 		ctl = htole32(SHIFTIN(8, ATW_TXCTL_TL_MASK));
   3691        1.1   dyoung 
   3692        1.1   dyoung 		DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n",
   3693        1.1   dyoung 		    sc->sc_dev.dv_xname, rate * 5));
   3694  1.105.6.1   simonb 		ctl |= htole32(SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
   3695        1.1   dyoung 
   3696        1.1   dyoung 		/*
   3697        1.1   dyoung 		 * Initialize the transmit descriptors.
   3698        1.1   dyoung 		 */
   3699        1.1   dyoung 		for (nexttx = sc->sc_txnext, seg = 0;
   3700        1.1   dyoung 		     seg < dmamap->dm_nsegs;
   3701        1.1   dyoung 		     seg++, nexttx = ATW_NEXTTX(nexttx)) {
   3702        1.1   dyoung 			/*
   3703        1.1   dyoung 			 * If this is the first descriptor we're
   3704        1.1   dyoung 			 * enqueueing, don't set the OWN bit just
   3705        1.1   dyoung 			 * yet.  That could cause a race condition.
   3706        1.1   dyoung 			 * We'll do it below.
   3707        1.1   dyoung 			 */
   3708        1.1   dyoung 			txd = &sc->sc_txdescs[nexttx];
   3709        1.1   dyoung 			txd->at_ctl = ctl |
   3710        1.1   dyoung 			    ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN));
   3711       1.84    perry 
   3712        1.1   dyoung 			txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr);
   3713        1.1   dyoung 			txd->at_flags =
   3714  1.105.6.1   simonb 			    htole32(SHIFTIN(dmamap->dm_segs[seg].ds_len,
   3715        1.1   dyoung 			                   ATW_TXFLAG_TBS1_MASK)) |
   3716        1.1   dyoung 			    ((nexttx == (ATW_NTXDESC - 1))
   3717        1.1   dyoung 			        ? htole32(ATW_TXFLAG_TER) : 0);
   3718        1.1   dyoung 			lasttx = nexttx;
   3719        1.1   dyoung 		}
   3720        1.1   dyoung 
   3721        1.1   dyoung 		/* Set `first segment' and `last segment' appropriately. */
   3722        1.1   dyoung 		sc->sc_txdescs[sc->sc_txnext].at_flags |=
   3723        1.1   dyoung 		    htole32(ATW_TXFLAG_FS);
   3724        1.1   dyoung 		sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS);
   3725        1.1   dyoung 
   3726        1.1   dyoung #ifdef ATW_DEBUG
   3727        1.1   dyoung 		if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
   3728        1.1   dyoung 			printf("     txsoft %p transmit chain:\n", txs);
   3729        1.1   dyoung 			for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) {
   3730        1.1   dyoung 				printf("     descriptor %d:\n", seg);
   3731        1.1   dyoung 				printf("       at_ctl:   0x%08x\n",
   3732        1.1   dyoung 				    le32toh(sc->sc_txdescs[seg].at_ctl));
   3733        1.1   dyoung 				printf("       at_flags:      0x%08x\n",
   3734        1.1   dyoung 				    le32toh(sc->sc_txdescs[seg].at_flags));
   3735        1.1   dyoung 				printf("       at_buf1: 0x%08x\n",
   3736        1.1   dyoung 				    le32toh(sc->sc_txdescs[seg].at_buf1));
   3737        1.1   dyoung 				printf("       at_buf2: 0x%08x\n",
   3738        1.1   dyoung 				    le32toh(sc->sc_txdescs[seg].at_buf2));
   3739        1.1   dyoung 				if (seg == lasttx)
   3740        1.1   dyoung 					break;
   3741        1.1   dyoung 			}
   3742        1.1   dyoung 		}
   3743        1.1   dyoung #endif
   3744        1.1   dyoung 
   3745        1.1   dyoung 		/* Sync the descriptors we're using. */
   3746        1.1   dyoung 		ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
   3747        1.1   dyoung 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   3748        1.1   dyoung 
   3749        1.1   dyoung 		/*
   3750        1.1   dyoung 		 * Store a pointer to the packet so we can free it later,
   3751        1.1   dyoung 		 * and remember what txdirty will be once the packet is
   3752        1.1   dyoung 		 * done.
   3753        1.1   dyoung 		 */
   3754        1.1   dyoung 		txs->txs_mbuf = m0;
   3755        1.1   dyoung 		txs->txs_firstdesc = sc->sc_txnext;
   3756        1.1   dyoung 		txs->txs_lastdesc = lasttx;
   3757        1.1   dyoung 		txs->txs_ndescs = dmamap->dm_nsegs;
   3758        1.1   dyoung 
   3759        1.1   dyoung 		/* Advance the tx pointer. */
   3760        1.1   dyoung 		sc->sc_txfree -= dmamap->dm_nsegs;
   3761        1.1   dyoung 		sc->sc_txnext = nexttx;
   3762        1.1   dyoung 
   3763        1.1   dyoung 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
   3764        1.1   dyoung 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
   3765        1.1   dyoung 
   3766        1.1   dyoung 		last_txs = txs;
   3767        1.1   dyoung 	}
   3768        1.1   dyoung 
   3769        1.1   dyoung 	if (sc->sc_txfree != ofree) {
   3770        1.1   dyoung 		DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
   3771        1.1   dyoung 		    sc->sc_dev.dv_xname, lasttx, firsttx));
   3772        1.1   dyoung 		/*
   3773        1.1   dyoung 		 * Cause a transmit interrupt to happen on the
   3774        1.1   dyoung 		 * last packet we enqueued.
   3775        1.1   dyoung 		 */
   3776        1.1   dyoung 		sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC);
   3777        1.1   dyoung 		ATW_CDTXSYNC(sc, lasttx, 1,
   3778        1.1   dyoung 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   3779        1.1   dyoung 
   3780        1.1   dyoung 		/*
   3781        1.1   dyoung 		 * The entire packet chain is set up.  Give the
   3782        1.1   dyoung 		 * first descriptor to the chip now.
   3783        1.1   dyoung 		 */
   3784        1.1   dyoung 		sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN);
   3785        1.1   dyoung 		ATW_CDTXSYNC(sc, firsttx, 1,
   3786        1.1   dyoung 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   3787        1.1   dyoung 
   3788        1.1   dyoung 		/* Wake up the transmitter. */
   3789        1.1   dyoung 		ATW_WRITE(sc, ATW_TDR, 0x1);
   3790        1.1   dyoung 
   3791      1.103   dyoung 		if (txs == NULL || sc->sc_txfree == 0)
   3792      1.103   dyoung 			ifp->if_flags |= IFF_OACTIVE;
   3793      1.103   dyoung 
   3794        1.1   dyoung 		/* Set a watchdog timer in case the chip flakes out. */
   3795        1.1   dyoung 		sc->sc_tx_timer = 5;
   3796        1.1   dyoung 		ifp->if_timer = 1;
   3797        1.1   dyoung 	}
   3798        1.1   dyoung }
   3799        1.1   dyoung 
   3800        1.1   dyoung /*
   3801        1.1   dyoung  * atw_power:
   3802        1.1   dyoung  *
   3803        1.1   dyoung  *	Power management (suspend/resume) hook.
   3804        1.1   dyoung  */
   3805        1.1   dyoung void
   3806       1.23   dyoung atw_power(int why, void *arg)
   3807        1.1   dyoung {
   3808        1.1   dyoung 	struct atw_softc *sc = arg;
   3809       1.85   dyoung 	struct ifnet *ifp = &sc->sc_if;
   3810        1.1   dyoung 	int s;
   3811        1.1   dyoung 
   3812        1.1   dyoung 	DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why));
   3813        1.1   dyoung 
   3814        1.1   dyoung 	s = splnet();
   3815        1.1   dyoung 	switch (why) {
   3816        1.1   dyoung 	case PWR_STANDBY:
   3817        1.1   dyoung 		/* XXX do nothing. */
   3818        1.1   dyoung 		break;
   3819        1.1   dyoung 	case PWR_SUSPEND:
   3820        1.1   dyoung 		atw_stop(ifp, 0);
   3821        1.1   dyoung 		if (sc->sc_power != NULL)
   3822        1.1   dyoung 			(*sc->sc_power)(sc, why);
   3823        1.1   dyoung 		break;
   3824        1.1   dyoung 	case PWR_RESUME:
   3825        1.1   dyoung 		if (ifp->if_flags & IFF_UP) {
   3826        1.1   dyoung 			if (sc->sc_power != NULL)
   3827        1.1   dyoung 				(*sc->sc_power)(sc, why);
   3828        1.1   dyoung 			atw_init(ifp);
   3829        1.1   dyoung 		}
   3830        1.1   dyoung 		break;
   3831        1.1   dyoung 	case PWR_SOFTSUSPEND:
   3832        1.1   dyoung 	case PWR_SOFTSTANDBY:
   3833        1.1   dyoung 	case PWR_SOFTRESUME:
   3834        1.1   dyoung 		break;
   3835        1.1   dyoung 	}
   3836        1.1   dyoung 	splx(s);
   3837        1.1   dyoung }
   3838        1.1   dyoung 
   3839        1.1   dyoung /*
   3840        1.1   dyoung  * atw_ioctl:		[ifnet interface function]
   3841        1.1   dyoung  *
   3842        1.1   dyoung  *	Handle control requests from the operator.
   3843        1.1   dyoung  */
   3844        1.1   dyoung int
   3845       1.23   dyoung atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
   3846        1.1   dyoung {
   3847        1.1   dyoung 	struct atw_softc *sc = ifp->if_softc;
   3848        1.1   dyoung 	struct ifreq *ifr = (struct ifreq *)data;
   3849        1.1   dyoung 	int s, error = 0;
   3850        1.1   dyoung 
   3851        1.1   dyoung 	/* XXX monkey see, monkey do. comes from wi_ioctl. */
   3852  1.105.6.1   simonb 	if (!device_is_active(&sc->sc_dev))
   3853        1.1   dyoung 		return ENXIO;
   3854        1.1   dyoung 
   3855        1.1   dyoung 	s = splnet();
   3856        1.1   dyoung 
   3857        1.1   dyoung 	switch (cmd) {
   3858        1.1   dyoung 	case SIOCSIFFLAGS:
   3859        1.1   dyoung 		if (ifp->if_flags & IFF_UP) {
   3860        1.1   dyoung 			if (ATW_IS_ENABLED(sc)) {
   3861        1.1   dyoung 				/*
   3862        1.1   dyoung 				 * To avoid rescanning another access point,
   3863        1.1   dyoung 				 * do not call atw_init() here.  Instead,
   3864        1.1   dyoung 				 * only reflect media settings.
   3865        1.1   dyoung 				 */
   3866        1.1   dyoung 				atw_filter_setup(sc);
   3867        1.1   dyoung 			} else
   3868        1.1   dyoung 				error = atw_init(ifp);
   3869        1.1   dyoung 		} else if (ATW_IS_ENABLED(sc))
   3870        1.1   dyoung 			atw_stop(ifp, 1);
   3871        1.1   dyoung 		break;
   3872        1.1   dyoung 	case SIOCADDMULTI:
   3873        1.1   dyoung 	case SIOCDELMULTI:
   3874        1.1   dyoung 		error = (cmd == SIOCADDMULTI) ?
   3875       1.85   dyoung 		    ether_addmulti(ifr, &sc->sc_ec) :
   3876       1.85   dyoung 		    ether_delmulti(ifr, &sc->sc_ec);
   3877        1.1   dyoung 		if (error == ENETRESET) {
   3878       1.80  thorpej 			if (ifp->if_flags & IFF_RUNNING)
   3879        1.1   dyoung 				atw_filter_setup(sc); /* do not rescan */
   3880        1.1   dyoung 			error = 0;
   3881        1.1   dyoung 		}
   3882        1.1   dyoung 		break;
   3883        1.1   dyoung 	default:
   3884       1.85   dyoung 		error = ieee80211_ioctl(&sc->sc_ic, cmd, data);
   3885      1.104   dyoung 		if (error == ENETRESET || error == ERESTART) {
   3886      1.104   dyoung 			if (is_running(ifp))
   3887        1.1   dyoung 				error = atw_init(ifp);
   3888        1.1   dyoung 			else
   3889        1.1   dyoung 				error = 0;
   3890        1.1   dyoung 		}
   3891        1.1   dyoung 		break;
   3892        1.1   dyoung 	}
   3893        1.1   dyoung 
   3894        1.1   dyoung 	/* Try to get more packets going. */
   3895        1.1   dyoung 	if (ATW_IS_ENABLED(sc))
   3896        1.1   dyoung 		atw_start(ifp);
   3897        1.1   dyoung 
   3898        1.1   dyoung 	splx(s);
   3899        1.1   dyoung 	return (error);
   3900        1.3   dyoung }
   3901        1.3   dyoung 
   3902        1.3   dyoung static int
   3903        1.3   dyoung atw_media_change(struct ifnet *ifp)
   3904        1.3   dyoung {
   3905        1.3   dyoung 	int error;
   3906        1.3   dyoung 
   3907        1.3   dyoung 	error = ieee80211_media_change(ifp);
   3908        1.3   dyoung 	if (error == ENETRESET) {
   3909      1.104   dyoung 		if (is_running(ifp))
   3910      1.104   dyoung 			error = atw_init(ifp);
   3911      1.104   dyoung 		else
   3912      1.104   dyoung 			error = 0;
   3913        1.3   dyoung 	}
   3914        1.3   dyoung 	return error;
   3915        1.1   dyoung }
   3916