atw.c revision 1.78.2.8
1 1.78.2.8 skrll /* $NetBSD: atw.c,v 1.78.2.8 2005/02/04 11:45:24 skrll Exp $ */ 2 1.78.2.2 skrll 3 1.78.2.2 skrll /*- 4 1.78.2.2 skrll * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 1.78.2.2 skrll * All rights reserved. 6 1.78.2.2 skrll * 7 1.78.2.2 skrll * This code is derived from software contributed to The NetBSD Foundation 8 1.78.2.2 skrll * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 1.78.2.2 skrll * 10 1.78.2.2 skrll * Redistribution and use in source and binary forms, with or without 11 1.78.2.2 skrll * modification, are permitted provided that the following conditions 12 1.78.2.2 skrll * are met: 13 1.78.2.2 skrll * 1. Redistributions of source code must retain the above copyright 14 1.78.2.2 skrll * notice, this list of conditions and the following disclaimer. 15 1.78.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 16 1.78.2.2 skrll * notice, this list of conditions and the following disclaimer in the 17 1.78.2.2 skrll * documentation and/or other materials provided with the distribution. 18 1.78.2.2 skrll * 3. All advertising materials mentioning features or use of this software 19 1.78.2.2 skrll * must display the following acknowledgement: 20 1.78.2.2 skrll * This product includes software developed by the NetBSD 21 1.78.2.2 skrll * Foundation, Inc. and its contributors. 22 1.78.2.2 skrll * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.78.2.2 skrll * contributors may be used to endorse or promote products derived 24 1.78.2.2 skrll * from this software without specific prior written permission. 25 1.78.2.2 skrll * 26 1.78.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.78.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.78.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.78.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.78.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.78.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.78.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.78.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.78.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.78.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.78.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 37 1.78.2.2 skrll */ 38 1.78.2.2 skrll 39 1.78.2.2 skrll /* 40 1.78.2.2 skrll * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 1.78.2.2 skrll */ 42 1.78.2.2 skrll 43 1.78.2.2 skrll #include <sys/cdefs.h> 44 1.78.2.8 skrll __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.78.2.8 2005/02/04 11:45:24 skrll Exp $"); 45 1.78.2.2 skrll 46 1.78.2.2 skrll #include "bpfilter.h" 47 1.78.2.2 skrll 48 1.78.2.2 skrll #include <sys/param.h> 49 1.78.2.2 skrll #include <sys/systm.h> 50 1.78.2.2 skrll #include <sys/callout.h> 51 1.78.2.2 skrll #include <sys/mbuf.h> 52 1.78.2.2 skrll #include <sys/malloc.h> 53 1.78.2.2 skrll #include <sys/kernel.h> 54 1.78.2.2 skrll #include <sys/socket.h> 55 1.78.2.2 skrll #include <sys/ioctl.h> 56 1.78.2.2 skrll #include <sys/errno.h> 57 1.78.2.2 skrll #include <sys/device.h> 58 1.78.2.2 skrll #include <sys/time.h> 59 1.78.2.2 skrll 60 1.78.2.2 skrll #include <machine/endian.h> 61 1.78.2.2 skrll 62 1.78.2.2 skrll #include <uvm/uvm_extern.h> 63 1.78.2.2 skrll 64 1.78.2.2 skrll #include <net/if.h> 65 1.78.2.2 skrll #include <net/if_dl.h> 66 1.78.2.2 skrll #include <net/if_media.h> 67 1.78.2.2 skrll #include <net/if_ether.h> 68 1.78.2.2 skrll 69 1.78.2.2 skrll #include <net80211/ieee80211_var.h> 70 1.78.2.2 skrll #include <net80211/ieee80211_compat.h> 71 1.78.2.2 skrll #include <net80211/ieee80211_radiotap.h> 72 1.78.2.2 skrll 73 1.78.2.2 skrll #if NBPFILTER > 0 74 1.78.2.2 skrll #include <net/bpf.h> 75 1.78.2.2 skrll #endif 76 1.78.2.2 skrll 77 1.78.2.2 skrll #include <machine/bus.h> 78 1.78.2.2 skrll #include <machine/intr.h> 79 1.78.2.2 skrll 80 1.78.2.2 skrll #include <dev/ic/atwreg.h> 81 1.78.2.2 skrll #include <dev/ic/rf3000reg.h> 82 1.78.2.2 skrll #include <dev/ic/si4136reg.h> 83 1.78.2.2 skrll #include <dev/ic/atwvar.h> 84 1.78.2.2 skrll #include <dev/ic/smc93cx6var.h> 85 1.78.2.2 skrll 86 1.78.2.2 skrll /* XXX TBD open questions 87 1.78.2.2 skrll * 88 1.78.2.2 skrll * 89 1.78.2.2 skrll * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 1.78.2.2 skrll * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 1.78.2.2 skrll * handle this for me? 92 1.78.2.2 skrll * 93 1.78.2.2 skrll */ 94 1.78.2.2 skrll /* device attachment 95 1.78.2.2 skrll * 96 1.78.2.2 skrll * print TOFS[012] 97 1.78.2.2 skrll * 98 1.78.2.2 skrll * device initialization 99 1.78.2.2 skrll * 100 1.78.2.2 skrll * clear ATW_FRCTL_MAXPSP to disable max power saving 101 1.78.2.2 skrll * set ATW_TXBR_ALCUPDATE to enable ALC 102 1.78.2.2 skrll * set TOFS[012]? (hope not) 103 1.78.2.2 skrll * disable rx/tx 104 1.78.2.2 skrll * set ATW_PAR_SWR (software reset) 105 1.78.2.2 skrll * wait for ATW_PAR_SWR clear 106 1.78.2.2 skrll * disable interrupts 107 1.78.2.2 skrll * ack status register 108 1.78.2.2 skrll * enable interrupts 109 1.78.2.2 skrll * 110 1.78.2.2 skrll * rx/tx initialization 111 1.78.2.2 skrll * 112 1.78.2.2 skrll * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 1.78.2.2 skrll * allocate and init descriptor rings 114 1.78.2.2 skrll * write ATW_PAR_DSL (descriptor skip length) 115 1.78.2.2 skrll * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 1.78.2.2 skrll * write ATW_NAR_SQ for one/both transmit descriptor rings 117 1.78.2.2 skrll * write ATW_NAR_SQ for one/both transmit descriptor rings 118 1.78.2.2 skrll * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 1.78.2.2 skrll * 120 1.78.2.2 skrll * rx/tx end 121 1.78.2.2 skrll * 122 1.78.2.2 skrll * stop DMA 123 1.78.2.2 skrll * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 1.78.2.2 skrll * flush tx w/ ATW_NAR_HF 125 1.78.2.2 skrll * 126 1.78.2.2 skrll * scan 127 1.78.2.2 skrll * 128 1.78.2.2 skrll * initialize rx/tx 129 1.78.2.2 skrll * 130 1.78.2.2 skrll * BSS join: (re)association response 131 1.78.2.2 skrll * 132 1.78.2.2 skrll * set ATW_FRCTL_AID 133 1.78.2.2 skrll * 134 1.78.2.2 skrll * optimizations ??? 135 1.78.2.2 skrll * 136 1.78.2.2 skrll */ 137 1.78.2.2 skrll 138 1.78.2.2 skrll #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 1.78.2.2 skrll 140 1.78.2.2 skrll #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 1.78.2.2 skrll #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 1.78.2.2 skrll int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 1.78.2.2 skrll 144 1.78.2.2 skrll int atw_pseudo_milli = 1; 145 1.78.2.2 skrll int atw_magic_delay1 = 100 * 1000; 146 1.78.2.2 skrll int atw_magic_delay2 = 100 * 1000; 147 1.78.2.2 skrll /* more magic multi-millisecond delays (units: microseconds) */ 148 1.78.2.2 skrll int atw_nar_delay = 20 * 1000; 149 1.78.2.2 skrll int atw_magic_delay4 = 10 * 1000; 150 1.78.2.2 skrll int atw_rf_delay1 = 10 * 1000; 151 1.78.2.2 skrll int atw_rf_delay2 = 5 * 1000; 152 1.78.2.2 skrll int atw_plcphd_delay = 2 * 1000; 153 1.78.2.2 skrll int atw_bbp_io_enable_delay = 20 * 1000; 154 1.78.2.2 skrll int atw_bbp_io_disable_delay = 2 * 1000; 155 1.78.2.2 skrll int atw_writewep_delay = 1000; 156 1.78.2.2 skrll int atw_beacon_len_adjust = 4; 157 1.78.2.2 skrll int atw_dwelltime = 200; 158 1.78.2.2 skrll int atw_xindiv2 = 0; 159 1.78.2.2 skrll 160 1.78.2.2 skrll #ifdef ATW_DEBUG 161 1.78.2.2 skrll int atw_debug = 0; 162 1.78.2.2 skrll 163 1.78.2.2 skrll #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 1.78.2.2 skrll #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 1.78.2.2 skrll #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 1.78.2.2 skrll #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 167 1.78.2.2 skrll #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 1.78.2.2 skrll #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 1.78.2.2 skrll 170 1.78.2.2 skrll static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 1.78.2.2 skrll static void atw_print_regs(struct atw_softc *, const char *); 172 1.78.2.2 skrll 173 1.78.2.2 skrll /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 1.78.2.2 skrll # ifdef ATW_BBPDEBUG 175 1.78.2.2 skrll static void atw_rf3000_print(struct atw_softc *); 176 1.78.2.2 skrll static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 1.78.2.2 skrll # endif /* ATW_BBPDEBUG */ 178 1.78.2.2 skrll 179 1.78.2.2 skrll # ifdef ATW_SYNDEBUG 180 1.78.2.2 skrll static void atw_si4126_print(struct atw_softc *); 181 1.78.2.2 skrll static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 1.78.2.2 skrll # endif /* ATW_SYNDEBUG */ 183 1.78.2.2 skrll 184 1.78.2.2 skrll #else 185 1.78.2.2 skrll #define ATW_DPRINTF(x) 186 1.78.2.2 skrll #define ATW_DPRINTF2(x) 187 1.78.2.2 skrll #define ATW_DPRINTF3(x) 188 1.78.2.2 skrll #define DPRINTF(sc, x) /* nothing */ 189 1.78.2.2 skrll #define DPRINTF2(sc, x) /* nothing */ 190 1.78.2.2 skrll #define DPRINTF3(sc, x) /* nothing */ 191 1.78.2.2 skrll #endif 192 1.78.2.2 skrll 193 1.78.2.2 skrll /* ifnet methods */ 194 1.78.2.2 skrll int atw_init(struct ifnet *); 195 1.78.2.2 skrll int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 1.78.2.2 skrll void atw_start(struct ifnet *); 197 1.78.2.2 skrll void atw_stop(struct ifnet *, int); 198 1.78.2.2 skrll void atw_watchdog(struct ifnet *); 199 1.78.2.2 skrll 200 1.78.2.2 skrll /* Device attachment */ 201 1.78.2.2 skrll void atw_attach(struct atw_softc *); 202 1.78.2.2 skrll int atw_detach(struct atw_softc *); 203 1.78.2.2 skrll 204 1.78.2.2 skrll /* Rx/Tx process */ 205 1.78.2.2 skrll int atw_add_rxbuf(struct atw_softc *, int); 206 1.78.2.2 skrll void atw_idle(struct atw_softc *, u_int32_t); 207 1.78.2.2 skrll void atw_rxdrain(struct atw_softc *); 208 1.78.2.2 skrll void atw_txdrain(struct atw_softc *); 209 1.78.2.2 skrll 210 1.78.2.2 skrll /* Device (de)activation and power state */ 211 1.78.2.2 skrll void atw_disable(struct atw_softc *); 212 1.78.2.2 skrll int atw_enable(struct atw_softc *); 213 1.78.2.2 skrll void atw_power(int, void *); 214 1.78.2.2 skrll void atw_reset(struct atw_softc *); 215 1.78.2.2 skrll void atw_shutdown(void *); 216 1.78.2.2 skrll 217 1.78.2.2 skrll /* Interrupt handlers */ 218 1.78.2.2 skrll void atw_linkintr(struct atw_softc *, u_int32_t); 219 1.78.2.2 skrll void atw_rxintr(struct atw_softc *); 220 1.78.2.2 skrll void atw_txintr(struct atw_softc *); 221 1.78.2.2 skrll 222 1.78.2.2 skrll /* 802.11 state machine */ 223 1.78.2.2 skrll static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 1.78.2.2 skrll static void atw_next_scan(void *); 225 1.78.2.2 skrll static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 1.78.2.2 skrll struct ieee80211_node *, int, int, u_int32_t); 227 1.78.2.2 skrll static int atw_tune(struct atw_softc *); 228 1.78.2.2 skrll 229 1.78.2.2 skrll /* Device initialization */ 230 1.78.2.2 skrll static void atw_bbp_io_init(struct atw_softc *); 231 1.78.2.2 skrll static void atw_cfp_init(struct atw_softc *); 232 1.78.2.2 skrll static void atw_cmdr_init(struct atw_softc *); 233 1.78.2.2 skrll static void atw_ifs_init(struct atw_softc *); 234 1.78.2.2 skrll static void atw_nar_init(struct atw_softc *); 235 1.78.2.2 skrll static void atw_response_times_init(struct atw_softc *); 236 1.78.2.2 skrll static void atw_rf_reset(struct atw_softc *); 237 1.78.2.2 skrll static void atw_test1_init(struct atw_softc *); 238 1.78.2.2 skrll static void atw_tofs0_init(struct atw_softc *); 239 1.78.2.2 skrll static void atw_tofs2_init(struct atw_softc *); 240 1.78.2.2 skrll static void atw_txlmt_init(struct atw_softc *); 241 1.78.2.2 skrll static void atw_wcsr_init(struct atw_softc *); 242 1.78.2.2 skrll 243 1.78.2.2 skrll /* RAM/ROM utilities */ 244 1.78.2.2 skrll static void atw_clear_sram(struct atw_softc *); 245 1.78.2.2 skrll static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 246 1.78.2.2 skrll static int atw_read_srom(struct atw_softc *); 247 1.78.2.2 skrll 248 1.78.2.2 skrll /* BSS setup */ 249 1.78.2.2 skrll static void atw_predict_beacon(struct atw_softc *); 250 1.78.2.2 skrll static void atw_start_beacon(struct atw_softc *, int); 251 1.78.2.2 skrll static void atw_write_bssid(struct atw_softc *); 252 1.78.2.2 skrll static void atw_write_ssid(struct atw_softc *); 253 1.78.2.2 skrll static void atw_write_sup_rates(struct atw_softc *); 254 1.78.2.2 skrll static void atw_write_wep(struct atw_softc *); 255 1.78.2.2 skrll 256 1.78.2.2 skrll /* Media */ 257 1.78.2.2 skrll static int atw_media_change(struct ifnet *); 258 1.78.2.2 skrll static void atw_media_status(struct ifnet *, struct ifmediareq *); 259 1.78.2.2 skrll 260 1.78.2.2 skrll static void atw_filter_setup(struct atw_softc *); 261 1.78.2.2 skrll 262 1.78.2.2 skrll /* 802.11 utilities */ 263 1.78.2.2 skrll static void atw_frame_setdurs(struct atw_softc *, 264 1.78.2.2 skrll struct atw_frame *, int, int); 265 1.78.2.2 skrll static uint64_t atw_get_tsft(struct atw_softc *); 266 1.78.2.2 skrll static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 267 1.78.2.2 skrll uint32_t); 268 1.78.2.2 skrll static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 269 1.78.2.2 skrll static void atw_node_free(struct ieee80211com *, 270 1.78.2.2 skrll struct ieee80211_node *); 271 1.78.2.2 skrll static void atw_change_ibss(struct atw_softc *); 272 1.78.2.2 skrll 273 1.78.2.2 skrll /* 274 1.78.2.2 skrll * Tuner/transceiver/modem 275 1.78.2.2 skrll */ 276 1.78.2.2 skrll static void atw_bbp_io_enable(struct atw_softc *, int); 277 1.78.2.2 skrll 278 1.78.2.2 skrll /* RFMD RF3000 Baseband Processor */ 279 1.78.2.2 skrll static int atw_rf3000_init(struct atw_softc *); 280 1.78.2.2 skrll static int atw_rf3000_tune(struct atw_softc *, u_int); 281 1.78.2.2 skrll static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 282 1.78.2.2 skrll 283 1.78.2.2 skrll /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 284 1.78.2.2 skrll static void atw_si4126_tune(struct atw_softc *, u_int); 285 1.78.2.2 skrll static void atw_si4126_write(struct atw_softc *, u_int, u_int); 286 1.78.2.2 skrll 287 1.78.2.2 skrll const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 288 1.78.2.2 skrll const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 289 1.78.2.2 skrll 290 1.78.2.2 skrll const char *atw_tx_state[] = { 291 1.78.2.2 skrll "STOPPED", 292 1.78.2.2 skrll "RUNNING - read descriptor", 293 1.78.2.2 skrll "RUNNING - transmitting", 294 1.78.2.2 skrll "RUNNING - filling fifo", /* XXX */ 295 1.78.2.2 skrll "SUSPENDED", 296 1.78.2.2 skrll "RUNNING -- write descriptor", 297 1.78.2.2 skrll "RUNNING -- write last descriptor", 298 1.78.2.2 skrll "RUNNING - fifo full" 299 1.78.2.2 skrll }; 300 1.78.2.2 skrll 301 1.78.2.2 skrll const char *atw_rx_state[] = { 302 1.78.2.2 skrll "STOPPED", 303 1.78.2.2 skrll "RUNNING - read descriptor", 304 1.78.2.2 skrll "RUNNING - check this packet, pre-fetch next", 305 1.78.2.2 skrll "RUNNING - wait for reception", 306 1.78.2.2 skrll "SUSPENDED", 307 1.78.2.2 skrll "RUNNING - write descriptor", 308 1.78.2.2 skrll "RUNNING - flush fifo", 309 1.78.2.2 skrll "RUNNING - fifo drain" 310 1.78.2.2 skrll }; 311 1.78.2.2 skrll 312 1.78.2.2 skrll int 313 1.78.2.2 skrll atw_activate(struct device *self, enum devact act) 314 1.78.2.2 skrll { 315 1.78.2.2 skrll struct atw_softc *sc = (struct atw_softc *)self; 316 1.78.2.2 skrll int rv = 0, s; 317 1.78.2.2 skrll 318 1.78.2.2 skrll s = splnet(); 319 1.78.2.2 skrll switch (act) { 320 1.78.2.2 skrll case DVACT_ACTIVATE: 321 1.78.2.2 skrll rv = EOPNOTSUPP; 322 1.78.2.2 skrll break; 323 1.78.2.2 skrll 324 1.78.2.2 skrll case DVACT_DEACTIVATE: 325 1.78.2.2 skrll if_deactivate(&sc->sc_ic.ic_if); 326 1.78.2.2 skrll break; 327 1.78.2.2 skrll } 328 1.78.2.2 skrll splx(s); 329 1.78.2.2 skrll return rv; 330 1.78.2.2 skrll } 331 1.78.2.2 skrll 332 1.78.2.2 skrll /* 333 1.78.2.2 skrll * atw_enable: 334 1.78.2.2 skrll * 335 1.78.2.2 skrll * Enable the ADM8211 chip. 336 1.78.2.2 skrll */ 337 1.78.2.2 skrll int 338 1.78.2.2 skrll atw_enable(struct atw_softc *sc) 339 1.78.2.2 skrll { 340 1.78.2.2 skrll 341 1.78.2.2 skrll if (ATW_IS_ENABLED(sc) == 0) { 342 1.78.2.2 skrll if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 343 1.78.2.2 skrll printf("%s: device enable failed\n", 344 1.78.2.2 skrll sc->sc_dev.dv_xname); 345 1.78.2.2 skrll return (EIO); 346 1.78.2.2 skrll } 347 1.78.2.2 skrll sc->sc_flags |= ATWF_ENABLED; 348 1.78.2.2 skrll } 349 1.78.2.2 skrll return (0); 350 1.78.2.2 skrll } 351 1.78.2.2 skrll 352 1.78.2.2 skrll /* 353 1.78.2.2 skrll * atw_disable: 354 1.78.2.2 skrll * 355 1.78.2.2 skrll * Disable the ADM8211 chip. 356 1.78.2.2 skrll */ 357 1.78.2.2 skrll void 358 1.78.2.2 skrll atw_disable(struct atw_softc *sc) 359 1.78.2.2 skrll { 360 1.78.2.2 skrll if (!ATW_IS_ENABLED(sc)) 361 1.78.2.2 skrll return; 362 1.78.2.2 skrll if (sc->sc_disable != NULL) 363 1.78.2.2 skrll (*sc->sc_disable)(sc); 364 1.78.2.2 skrll sc->sc_flags &= ~ATWF_ENABLED; 365 1.78.2.2 skrll } 366 1.78.2.2 skrll 367 1.78.2.2 skrll /* Returns -1 on failure. */ 368 1.78.2.2 skrll static int 369 1.78.2.2 skrll atw_read_srom(struct atw_softc *sc) 370 1.78.2.2 skrll { 371 1.78.2.2 skrll struct seeprom_descriptor sd; 372 1.78.2.2 skrll uint32_t test0, fail_bits; 373 1.78.2.2 skrll 374 1.78.2.2 skrll (void)memset(&sd, 0, sizeof(sd)); 375 1.78.2.2 skrll 376 1.78.2.2 skrll test0 = ATW_READ(sc, ATW_TEST0); 377 1.78.2.2 skrll 378 1.78.2.2 skrll switch (sc->sc_rev) { 379 1.78.2.2 skrll case ATW_REVISION_BA: 380 1.78.2.2 skrll case ATW_REVISION_CA: 381 1.78.2.2 skrll fail_bits = ATW_TEST0_EPNE; 382 1.78.2.2 skrll break; 383 1.78.2.2 skrll default: 384 1.78.2.2 skrll fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 385 1.78.2.2 skrll break; 386 1.78.2.2 skrll } 387 1.78.2.2 skrll if ((test0 & fail_bits) != 0) { 388 1.78.2.2 skrll printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 389 1.78.2.2 skrll return -1; 390 1.78.2.2 skrll } 391 1.78.2.2 skrll 392 1.78.2.2 skrll switch (test0 & ATW_TEST0_EPTYP_MASK) { 393 1.78.2.2 skrll case ATW_TEST0_EPTYP_93c66: 394 1.78.2.2 skrll ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 395 1.78.2.2 skrll sc->sc_sromsz = 512; 396 1.78.2.2 skrll sd.sd_chip = C56_66; 397 1.78.2.2 skrll break; 398 1.78.2.2 skrll case ATW_TEST0_EPTYP_93c46: 399 1.78.2.2 skrll ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 400 1.78.2.2 skrll sc->sc_sromsz = 128; 401 1.78.2.2 skrll sd.sd_chip = C46; 402 1.78.2.2 skrll break; 403 1.78.2.2 skrll default: 404 1.78.2.2 skrll printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 405 1.78.2.2 skrll MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 406 1.78.2.2 skrll return -1; 407 1.78.2.2 skrll } 408 1.78.2.2 skrll 409 1.78.2.2 skrll sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 410 1.78.2.2 skrll 411 1.78.2.2 skrll if (sc->sc_srom == NULL) { 412 1.78.2.2 skrll printf("%s: unable to allocate SROM buffer\n", 413 1.78.2.2 skrll sc->sc_dev.dv_xname); 414 1.78.2.2 skrll return -1; 415 1.78.2.2 skrll } 416 1.78.2.2 skrll 417 1.78.2.2 skrll (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 418 1.78.2.2 skrll 419 1.78.2.2 skrll /* ADM8211 has a single 32-bit register for controlling the 420 1.78.2.2 skrll * 93cx6 SROM. Bit SRS enables the serial port. There is no 421 1.78.2.2 skrll * "ready" bit. The ADM8211 input/output sense is the reverse 422 1.78.2.2 skrll * of read_seeprom's. 423 1.78.2.2 skrll */ 424 1.78.2.2 skrll sd.sd_tag = sc->sc_st; 425 1.78.2.2 skrll sd.sd_bsh = sc->sc_sh; 426 1.78.2.2 skrll sd.sd_regsize = 4; 427 1.78.2.2 skrll sd.sd_control_offset = ATW_SPR; 428 1.78.2.2 skrll sd.sd_status_offset = ATW_SPR; 429 1.78.2.2 skrll sd.sd_dataout_offset = ATW_SPR; 430 1.78.2.2 skrll sd.sd_CK = ATW_SPR_SCLK; 431 1.78.2.2 skrll sd.sd_CS = ATW_SPR_SCS; 432 1.78.2.2 skrll sd.sd_DI = ATW_SPR_SDO; 433 1.78.2.2 skrll sd.sd_DO = ATW_SPR_SDI; 434 1.78.2.2 skrll sd.sd_MS = ATW_SPR_SRS; 435 1.78.2.2 skrll sd.sd_RDY = 0; 436 1.78.2.2 skrll 437 1.78.2.2 skrll if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 438 1.78.2.2 skrll printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 439 1.78.2.2 skrll free(sc->sc_srom, M_DEVBUF); 440 1.78.2.2 skrll return -1; 441 1.78.2.2 skrll } 442 1.78.2.2 skrll #ifdef ATW_DEBUG 443 1.78.2.2 skrll { 444 1.78.2.2 skrll int i; 445 1.78.2.2 skrll ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 446 1.78.2.2 skrll for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 447 1.78.2.2 skrll if (((i % 8) == 0) && (i != 0)) { 448 1.78.2.2 skrll ATW_DPRINTF(("\n\t")); 449 1.78.2.2 skrll } 450 1.78.2.2 skrll ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 451 1.78.2.2 skrll } 452 1.78.2.2 skrll ATW_DPRINTF(("\n")); 453 1.78.2.2 skrll } 454 1.78.2.2 skrll #endif /* ATW_DEBUG */ 455 1.78.2.2 skrll return 0; 456 1.78.2.2 skrll } 457 1.78.2.2 skrll 458 1.78.2.2 skrll #ifdef ATW_DEBUG 459 1.78.2.2 skrll static void 460 1.78.2.2 skrll atw_print_regs(struct atw_softc *sc, const char *where) 461 1.78.2.2 skrll { 462 1.78.2.2 skrll #define PRINTREG(sc, reg) \ 463 1.78.2.2 skrll ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 464 1.78.2.2 skrll sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 465 1.78.2.2 skrll 466 1.78.2.2 skrll ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 467 1.78.2.2 skrll 468 1.78.2.2 skrll PRINTREG(sc, ATW_PAR); 469 1.78.2.2 skrll PRINTREG(sc, ATW_FRCTL); 470 1.78.2.2 skrll PRINTREG(sc, ATW_TDR); 471 1.78.2.2 skrll PRINTREG(sc, ATW_WTDP); 472 1.78.2.2 skrll PRINTREG(sc, ATW_RDR); 473 1.78.2.2 skrll PRINTREG(sc, ATW_WRDP); 474 1.78.2.2 skrll PRINTREG(sc, ATW_RDB); 475 1.78.2.2 skrll PRINTREG(sc, ATW_CSR3A); 476 1.78.2.2 skrll PRINTREG(sc, ATW_TDBD); 477 1.78.2.2 skrll PRINTREG(sc, ATW_TDBP); 478 1.78.2.2 skrll PRINTREG(sc, ATW_STSR); 479 1.78.2.2 skrll PRINTREG(sc, ATW_CSR5A); 480 1.78.2.2 skrll PRINTREG(sc, ATW_NAR); 481 1.78.2.2 skrll PRINTREG(sc, ATW_CSR6A); 482 1.78.2.2 skrll PRINTREG(sc, ATW_IER); 483 1.78.2.2 skrll PRINTREG(sc, ATW_CSR7A); 484 1.78.2.2 skrll PRINTREG(sc, ATW_LPC); 485 1.78.2.2 skrll PRINTREG(sc, ATW_TEST1); 486 1.78.2.2 skrll PRINTREG(sc, ATW_SPR); 487 1.78.2.2 skrll PRINTREG(sc, ATW_TEST0); 488 1.78.2.2 skrll PRINTREG(sc, ATW_WCSR); 489 1.78.2.2 skrll PRINTREG(sc, ATW_WPDR); 490 1.78.2.2 skrll PRINTREG(sc, ATW_GPTMR); 491 1.78.2.2 skrll PRINTREG(sc, ATW_GPIO); 492 1.78.2.2 skrll PRINTREG(sc, ATW_BBPCTL); 493 1.78.2.2 skrll PRINTREG(sc, ATW_SYNCTL); 494 1.78.2.2 skrll PRINTREG(sc, ATW_PLCPHD); 495 1.78.2.2 skrll PRINTREG(sc, ATW_MMIWADDR); 496 1.78.2.2 skrll PRINTREG(sc, ATW_MMIRADDR1); 497 1.78.2.2 skrll PRINTREG(sc, ATW_MMIRADDR2); 498 1.78.2.2 skrll PRINTREG(sc, ATW_TXBR); 499 1.78.2.2 skrll PRINTREG(sc, ATW_CSR15A); 500 1.78.2.2 skrll PRINTREG(sc, ATW_ALCSTAT); 501 1.78.2.2 skrll PRINTREG(sc, ATW_TOFS2); 502 1.78.2.2 skrll PRINTREG(sc, ATW_CMDR); 503 1.78.2.2 skrll PRINTREG(sc, ATW_PCIC); 504 1.78.2.2 skrll PRINTREG(sc, ATW_PMCSR); 505 1.78.2.2 skrll PRINTREG(sc, ATW_PAR0); 506 1.78.2.2 skrll PRINTREG(sc, ATW_PAR1); 507 1.78.2.2 skrll PRINTREG(sc, ATW_MAR0); 508 1.78.2.2 skrll PRINTREG(sc, ATW_MAR1); 509 1.78.2.2 skrll PRINTREG(sc, ATW_ATIMDA0); 510 1.78.2.2 skrll PRINTREG(sc, ATW_ABDA1); 511 1.78.2.2 skrll PRINTREG(sc, ATW_BSSID0); 512 1.78.2.2 skrll PRINTREG(sc, ATW_TXLMT); 513 1.78.2.2 skrll PRINTREG(sc, ATW_MIBCNT); 514 1.78.2.2 skrll PRINTREG(sc, ATW_BCNT); 515 1.78.2.2 skrll PRINTREG(sc, ATW_TSFTH); 516 1.78.2.2 skrll PRINTREG(sc, ATW_TSC); 517 1.78.2.2 skrll PRINTREG(sc, ATW_SYNRF); 518 1.78.2.2 skrll PRINTREG(sc, ATW_BPLI); 519 1.78.2.2 skrll PRINTREG(sc, ATW_CAP0); 520 1.78.2.2 skrll PRINTREG(sc, ATW_CAP1); 521 1.78.2.2 skrll PRINTREG(sc, ATW_RMD); 522 1.78.2.2 skrll PRINTREG(sc, ATW_CFPP); 523 1.78.2.2 skrll PRINTREG(sc, ATW_TOFS0); 524 1.78.2.2 skrll PRINTREG(sc, ATW_TOFS1); 525 1.78.2.2 skrll PRINTREG(sc, ATW_IFST); 526 1.78.2.2 skrll PRINTREG(sc, ATW_RSPT); 527 1.78.2.2 skrll PRINTREG(sc, ATW_TSFTL); 528 1.78.2.2 skrll PRINTREG(sc, ATW_WEPCTL); 529 1.78.2.2 skrll PRINTREG(sc, ATW_WESK); 530 1.78.2.2 skrll PRINTREG(sc, ATW_WEPCNT); 531 1.78.2.2 skrll PRINTREG(sc, ATW_MACTEST); 532 1.78.2.2 skrll PRINTREG(sc, ATW_FER); 533 1.78.2.2 skrll PRINTREG(sc, ATW_FEMR); 534 1.78.2.2 skrll PRINTREG(sc, ATW_FPSR); 535 1.78.2.2 skrll PRINTREG(sc, ATW_FFER); 536 1.78.2.2 skrll #undef PRINTREG 537 1.78.2.2 skrll } 538 1.78.2.2 skrll #endif /* ATW_DEBUG */ 539 1.78.2.2 skrll 540 1.78.2.2 skrll /* 541 1.78.2.2 skrll * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 542 1.78.2.2 skrll */ 543 1.78.2.2 skrll void 544 1.78.2.2 skrll atw_attach(struct atw_softc *sc) 545 1.78.2.2 skrll { 546 1.78.2.2 skrll static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 547 1.78.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 548 1.78.2.2 skrll }; 549 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 550 1.78.2.2 skrll struct ifnet *ifp = &ic->ic_if; 551 1.78.2.2 skrll int country_code, error, i, nrate, srom_major; 552 1.78.2.2 skrll u_int32_t reg; 553 1.78.2.2 skrll static const char *type_strings[] = {"Intersil (not supported)", 554 1.78.2.2 skrll "RFMD", "Marvel (not supported)"}; 555 1.78.2.2 skrll 556 1.78.2.2 skrll sc->sc_txth = atw_txthresh_tab_lo; 557 1.78.2.2 skrll 558 1.78.2.2 skrll SIMPLEQ_INIT(&sc->sc_txfreeq); 559 1.78.2.2 skrll SIMPLEQ_INIT(&sc->sc_txdirtyq); 560 1.78.2.2 skrll 561 1.78.2.2 skrll #ifdef ATW_DEBUG 562 1.78.2.2 skrll atw_print_regs(sc, "atw_attach"); 563 1.78.2.2 skrll #endif /* ATW_DEBUG */ 564 1.78.2.2 skrll 565 1.78.2.2 skrll /* 566 1.78.2.2 skrll * Allocate the control data structures, and create and load the 567 1.78.2.2 skrll * DMA map for it. 568 1.78.2.2 skrll */ 569 1.78.2.2 skrll if ((error = bus_dmamem_alloc(sc->sc_dmat, 570 1.78.2.2 skrll sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 571 1.78.2.2 skrll 1, &sc->sc_cdnseg, 0)) != 0) { 572 1.78.2.2 skrll printf("%s: unable to allocate control data, error = %d\n", 573 1.78.2.2 skrll sc->sc_dev.dv_xname, error); 574 1.78.2.2 skrll goto fail_0; 575 1.78.2.2 skrll } 576 1.78.2.2 skrll 577 1.78.2.2 skrll if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 578 1.78.2.2 skrll sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 579 1.78.2.2 skrll BUS_DMA_COHERENT)) != 0) { 580 1.78.2.2 skrll printf("%s: unable to map control data, error = %d\n", 581 1.78.2.2 skrll sc->sc_dev.dv_xname, error); 582 1.78.2.2 skrll goto fail_1; 583 1.78.2.2 skrll } 584 1.78.2.2 skrll 585 1.78.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, 586 1.78.2.2 skrll sizeof(struct atw_control_data), 1, 587 1.78.2.2 skrll sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 588 1.78.2.2 skrll printf("%s: unable to create control data DMA map, " 589 1.78.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 590 1.78.2.2 skrll goto fail_2; 591 1.78.2.2 skrll } 592 1.78.2.2 skrll 593 1.78.2.2 skrll if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 594 1.78.2.2 skrll sc->sc_control_data, sizeof(struct atw_control_data), NULL, 595 1.78.2.2 skrll 0)) != 0) { 596 1.78.2.2 skrll printf("%s: unable to load control data DMA map, error = %d\n", 597 1.78.2.2 skrll sc->sc_dev.dv_xname, error); 598 1.78.2.2 skrll goto fail_3; 599 1.78.2.2 skrll } 600 1.78.2.2 skrll 601 1.78.2.2 skrll /* 602 1.78.2.2 skrll * Create the transmit buffer DMA maps. 603 1.78.2.2 skrll */ 604 1.78.2.2 skrll sc->sc_ntxsegs = ATW_NTXSEGS; 605 1.78.2.2 skrll for (i = 0; i < ATW_TXQUEUELEN; i++) { 606 1.78.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 607 1.78.2.2 skrll sc->sc_ntxsegs, MCLBYTES, 0, 0, 608 1.78.2.2 skrll &sc->sc_txsoft[i].txs_dmamap)) != 0) { 609 1.78.2.2 skrll printf("%s: unable to create tx DMA map %d, " 610 1.78.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, i, error); 611 1.78.2.2 skrll goto fail_4; 612 1.78.2.2 skrll } 613 1.78.2.2 skrll } 614 1.78.2.2 skrll 615 1.78.2.2 skrll /* 616 1.78.2.2 skrll * Create the receive buffer DMA maps. 617 1.78.2.2 skrll */ 618 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 619 1.78.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 620 1.78.2.2 skrll MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 621 1.78.2.2 skrll printf("%s: unable to create rx DMA map %d, " 622 1.78.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, i, error); 623 1.78.2.2 skrll goto fail_5; 624 1.78.2.2 skrll } 625 1.78.2.2 skrll } 626 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 627 1.78.2.2 skrll sc->sc_rxsoft[i].rxs_mbuf = NULL; 628 1.78.2.2 skrll } 629 1.78.2.2 skrll 630 1.78.2.2 skrll switch (sc->sc_rev) { 631 1.78.2.2 skrll case ATW_REVISION_AB: 632 1.78.2.2 skrll case ATW_REVISION_AF: 633 1.78.2.2 skrll sc->sc_sramlen = ATW_SRAM_A_SIZE; 634 1.78.2.2 skrll break; 635 1.78.2.2 skrll case ATW_REVISION_BA: 636 1.78.2.2 skrll case ATW_REVISION_CA: 637 1.78.2.2 skrll sc->sc_sramlen = ATW_SRAM_B_SIZE; 638 1.78.2.2 skrll break; 639 1.78.2.2 skrll } 640 1.78.2.2 skrll 641 1.78.2.2 skrll /* Reset the chip to a known state. */ 642 1.78.2.2 skrll atw_reset(sc); 643 1.78.2.2 skrll 644 1.78.2.2 skrll if (atw_read_srom(sc) == -1) 645 1.78.2.2 skrll return; 646 1.78.2.2 skrll 647 1.78.2.2 skrll sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 648 1.78.2.2 skrll ATW_SR_RFTYPE_MASK); 649 1.78.2.2 skrll 650 1.78.2.2 skrll sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 651 1.78.2.2 skrll ATW_SR_BBPTYPE_MASK); 652 1.78.2.2 skrll 653 1.78.2.2 skrll if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 654 1.78.2.2 skrll printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 655 1.78.2.2 skrll return; 656 1.78.2.2 skrll } 657 1.78.2.2 skrll if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 658 1.78.2.2 skrll printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 659 1.78.2.2 skrll return; 660 1.78.2.2 skrll } 661 1.78.2.2 skrll 662 1.78.2.2 skrll printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 663 1.78.2.2 skrll type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 664 1.78.2.2 skrll 665 1.78.2.2 skrll /* XXX There exists a Linux driver which seems to use RFType = 0 for 666 1.78.2.2 skrll * MARVEL. My bug, or theirs? 667 1.78.2.2 skrll */ 668 1.78.2.2 skrll 669 1.78.2.2 skrll reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 670 1.78.2.2 skrll 671 1.78.2.2 skrll switch (sc->sc_rftype) { 672 1.78.2.2 skrll case ATW_RFTYPE_INTERSIL: 673 1.78.2.2 skrll reg |= ATW_SYNCTL_CS1; 674 1.78.2.2 skrll break; 675 1.78.2.2 skrll case ATW_RFTYPE_RFMD: 676 1.78.2.2 skrll reg |= ATW_SYNCTL_CS0; 677 1.78.2.2 skrll break; 678 1.78.2.2 skrll case ATW_RFTYPE_MARVEL: 679 1.78.2.2 skrll break; 680 1.78.2.2 skrll } 681 1.78.2.2 skrll 682 1.78.2.2 skrll sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 683 1.78.2.2 skrll sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 684 1.78.2.2 skrll 685 1.78.2.2 skrll reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 686 1.78.2.2 skrll 687 1.78.2.2 skrll switch (sc->sc_bbptype) { 688 1.78.2.2 skrll case ATW_BBPTYPE_INTERSIL: 689 1.78.2.2 skrll reg |= ATW_BBPCTL_TWI; 690 1.78.2.2 skrll break; 691 1.78.2.2 skrll case ATW_BBPTYPE_RFMD: 692 1.78.2.2 skrll reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 693 1.78.2.2 skrll ATW_BBPCTL_CCA_ACTLO; 694 1.78.2.2 skrll break; 695 1.78.2.2 skrll case ATW_BBPTYPE_MARVEL: 696 1.78.2.2 skrll break; 697 1.78.2.2 skrll case ATW_C_BBPTYPE_RFMD: 698 1.78.2.2 skrll printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 699 1.78.2.2 skrll sc->sc_dev.dv_xname); 700 1.78.2.2 skrll break; 701 1.78.2.2 skrll } 702 1.78.2.2 skrll 703 1.78.2.2 skrll sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 704 1.78.2.2 skrll sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 705 1.78.2.2 skrll 706 1.78.2.2 skrll /* 707 1.78.2.2 skrll * From this point forward, the attachment cannot fail. A failure 708 1.78.2.2 skrll * before this point releases all resources that may have been 709 1.78.2.2 skrll * allocated. 710 1.78.2.2 skrll */ 711 1.78.2.2 skrll sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 712 1.78.2.2 skrll 713 1.78.2.2 skrll ATW_DPRINTF((" SROM MAC %04x%04x%04x", 714 1.78.2.2 skrll htole16(sc->sc_srom[ATW_SR_MAC00]), 715 1.78.2.2 skrll htole16(sc->sc_srom[ATW_SR_MAC01]), 716 1.78.2.2 skrll htole16(sc->sc_srom[ATW_SR_MAC10]))); 717 1.78.2.2 skrll 718 1.78.2.2 skrll srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 719 1.78.2.2 skrll ATW_SR_MAJOR_MASK); 720 1.78.2.2 skrll 721 1.78.2.2 skrll if (srom_major < 2) 722 1.78.2.2 skrll sc->sc_rf3000_options1 = 0; 723 1.78.2.2 skrll else if (sc->sc_rev == ATW_REVISION_BA) { 724 1.78.2.2 skrll sc->sc_rf3000_options1 = 725 1.78.2.2 skrll MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 726 1.78.2.2 skrll ATW_SR_CR28_MASK); 727 1.78.2.2 skrll } else 728 1.78.2.2 skrll sc->sc_rf3000_options1 = 0; 729 1.78.2.2 skrll 730 1.78.2.2 skrll sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 731 1.78.2.2 skrll ATW_SR_CR29_MASK); 732 1.78.2.2 skrll 733 1.78.2.2 skrll country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 734 1.78.2.2 skrll ATW_SR_CTRY_MASK); 735 1.78.2.2 skrll 736 1.78.2.2 skrll #define ADD_CHANNEL(_ic, _chan) do { \ 737 1.78.2.2 skrll _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 738 1.78.2.2 skrll _ic->ic_channels[_chan].ic_freq = \ 739 1.78.2.2 skrll ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 740 1.78.2.2 skrll } while (0) 741 1.78.2.2 skrll 742 1.78.2.2 skrll /* Find available channels */ 743 1.78.2.2 skrll switch (country_code) { 744 1.78.2.2 skrll case COUNTRY_MMK2: /* 1-14 */ 745 1.78.2.2 skrll ADD_CHANNEL(ic, 14); 746 1.78.2.2 skrll /*FALLTHROUGH*/ 747 1.78.2.2 skrll case COUNTRY_ETSI: /* 1-13 */ 748 1.78.2.2 skrll for (i = 1; i <= 13; i++) 749 1.78.2.2 skrll ADD_CHANNEL(ic, i); 750 1.78.2.2 skrll break; 751 1.78.2.2 skrll case COUNTRY_FCC: /* 1-11 */ 752 1.78.2.2 skrll case COUNTRY_IC: /* 1-11 */ 753 1.78.2.2 skrll for (i = 1; i <= 11; i++) 754 1.78.2.2 skrll ADD_CHANNEL(ic, i); 755 1.78.2.2 skrll break; 756 1.78.2.2 skrll case COUNTRY_MMK: /* 14 */ 757 1.78.2.2 skrll ADD_CHANNEL(ic, 14); 758 1.78.2.2 skrll break; 759 1.78.2.2 skrll case COUNTRY_FRANCE: /* 10-13 */ 760 1.78.2.2 skrll for (i = 10; i <= 13; i++) 761 1.78.2.2 skrll ADD_CHANNEL(ic, i); 762 1.78.2.2 skrll break; 763 1.78.2.2 skrll default: /* assume channels 10-11 */ 764 1.78.2.2 skrll case COUNTRY_SPAIN: /* 10-11 */ 765 1.78.2.2 skrll for (i = 10; i <= 11; i++) 766 1.78.2.2 skrll ADD_CHANNEL(ic, i); 767 1.78.2.2 skrll break; 768 1.78.2.2 skrll } 769 1.78.2.2 skrll 770 1.78.2.2 skrll /* Read the MAC address. */ 771 1.78.2.2 skrll reg = ATW_READ(sc, ATW_PAR0); 772 1.78.2.2 skrll ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 773 1.78.2.2 skrll ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 774 1.78.2.2 skrll ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 775 1.78.2.2 skrll ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 776 1.78.2.2 skrll reg = ATW_READ(sc, ATW_PAR1); 777 1.78.2.2 skrll ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 778 1.78.2.2 skrll ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 779 1.78.2.2 skrll 780 1.78.2.2 skrll if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 781 1.78.2.2 skrll printf(" could not get mac address, attach failed\n"); 782 1.78.2.2 skrll return; 783 1.78.2.2 skrll } 784 1.78.2.2 skrll 785 1.78.2.2 skrll printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 786 1.78.2.2 skrll 787 1.78.2.2 skrll memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 788 1.78.2.2 skrll ifp->if_softc = sc; 789 1.78.2.2 skrll ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 790 1.78.2.2 skrll IFF_NOTRAILERS; 791 1.78.2.2 skrll ifp->if_ioctl = atw_ioctl; 792 1.78.2.2 skrll ifp->if_start = atw_start; 793 1.78.2.2 skrll ifp->if_watchdog = atw_watchdog; 794 1.78.2.2 skrll ifp->if_init = atw_init; 795 1.78.2.2 skrll ifp->if_stop = atw_stop; 796 1.78.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 797 1.78.2.2 skrll 798 1.78.2.2 skrll ic->ic_phytype = IEEE80211_T_DS; 799 1.78.2.2 skrll ic->ic_opmode = IEEE80211_M_STA; 800 1.78.2.2 skrll ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 801 1.78.2.2 skrll IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 802 1.78.2.2 skrll 803 1.78.2.2 skrll nrate = 0; 804 1.78.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 805 1.78.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 806 1.78.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 807 1.78.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 808 1.78.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 809 1.78.2.2 skrll 810 1.78.2.2 skrll /* 811 1.78.2.2 skrll * Call MI attach routines. 812 1.78.2.2 skrll */ 813 1.78.2.2 skrll 814 1.78.2.2 skrll if_attach(ifp); 815 1.78.2.2 skrll ieee80211_ifattach(ifp); 816 1.78.2.2 skrll 817 1.78.2.2 skrll sc->sc_newstate = ic->ic_newstate; 818 1.78.2.2 skrll ic->ic_newstate = atw_newstate; 819 1.78.2.2 skrll 820 1.78.2.2 skrll sc->sc_recv_mgmt = ic->ic_recv_mgmt; 821 1.78.2.2 skrll ic->ic_recv_mgmt = atw_recv_mgmt; 822 1.78.2.2 skrll 823 1.78.2.2 skrll sc->sc_node_free = ic->ic_node_free; 824 1.78.2.2 skrll ic->ic_node_free = atw_node_free; 825 1.78.2.2 skrll 826 1.78.2.2 skrll sc->sc_node_alloc = ic->ic_node_alloc; 827 1.78.2.2 skrll ic->ic_node_alloc = atw_node_alloc; 828 1.78.2.2 skrll 829 1.78.2.2 skrll /* possibly we should fill in our own sc_send_prresp, since 830 1.78.2.2 skrll * the ADM8211 is probably sending probe responses in ad hoc 831 1.78.2.2 skrll * mode. 832 1.78.2.2 skrll */ 833 1.78.2.2 skrll 834 1.78.2.2 skrll /* complete initialization */ 835 1.78.2.2 skrll ieee80211_media_init(ifp, atw_media_change, atw_media_status); 836 1.78.2.2 skrll callout_init(&sc->sc_scan_ch); 837 1.78.2.2 skrll 838 1.78.2.2 skrll #if NBPFILTER > 0 839 1.78.2.2 skrll bpfattach2(ifp, DLT_IEEE802_11_RADIO, 840 1.78.2.2 skrll sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 841 1.78.2.2 skrll #endif 842 1.78.2.2 skrll 843 1.78.2.2 skrll /* 844 1.78.2.2 skrll * Make sure the interface is shutdown during reboot. 845 1.78.2.2 skrll */ 846 1.78.2.2 skrll sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 847 1.78.2.2 skrll if (sc->sc_sdhook == NULL) 848 1.78.2.2 skrll printf("%s: WARNING: unable to establish shutdown hook\n", 849 1.78.2.2 skrll sc->sc_dev.dv_xname); 850 1.78.2.2 skrll 851 1.78.2.2 skrll /* 852 1.78.2.2 skrll * Add a suspend hook to make sure we come back up after a 853 1.78.2.2 skrll * resume. 854 1.78.2.2 skrll */ 855 1.78.2.2 skrll sc->sc_powerhook = powerhook_establish(atw_power, sc); 856 1.78.2.2 skrll if (sc->sc_powerhook == NULL) 857 1.78.2.2 skrll printf("%s: WARNING: unable to establish power hook\n", 858 1.78.2.2 skrll sc->sc_dev.dv_xname); 859 1.78.2.2 skrll 860 1.78.2.2 skrll memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 861 1.78.2.2 skrll sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 862 1.78.2.2 skrll sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 863 1.78.2.2 skrll 864 1.78.2.2 skrll memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 865 1.78.2.2 skrll sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 866 1.78.2.2 skrll sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 867 1.78.2.2 skrll 868 1.78.2.2 skrll return; 869 1.78.2.2 skrll 870 1.78.2.2 skrll /* 871 1.78.2.2 skrll * Free any resources we've allocated during the failed attach 872 1.78.2.2 skrll * attempt. Do this in reverse order and fall through. 873 1.78.2.2 skrll */ 874 1.78.2.2 skrll fail_5: 875 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 876 1.78.2.2 skrll if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 877 1.78.2.2 skrll continue; 878 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 879 1.78.2.2 skrll } 880 1.78.2.2 skrll fail_4: 881 1.78.2.2 skrll for (i = 0; i < ATW_TXQUEUELEN; i++) { 882 1.78.2.2 skrll if (sc->sc_txsoft[i].txs_dmamap == NULL) 883 1.78.2.2 skrll continue; 884 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 885 1.78.2.2 skrll } 886 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 887 1.78.2.2 skrll fail_3: 888 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 889 1.78.2.2 skrll fail_2: 890 1.78.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 891 1.78.2.2 skrll sizeof(struct atw_control_data)); 892 1.78.2.2 skrll fail_1: 893 1.78.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 894 1.78.2.2 skrll fail_0: 895 1.78.2.2 skrll return; 896 1.78.2.2 skrll } 897 1.78.2.2 skrll 898 1.78.2.2 skrll static struct ieee80211_node * 899 1.78.2.2 skrll atw_node_alloc(struct ieee80211com *ic) 900 1.78.2.2 skrll { 901 1.78.2.2 skrll struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 902 1.78.2.2 skrll struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 903 1.78.2.2 skrll 904 1.78.2.2 skrll DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 905 1.78.2.2 skrll return ni; 906 1.78.2.2 skrll } 907 1.78.2.2 skrll 908 1.78.2.2 skrll static void 909 1.78.2.2 skrll atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 910 1.78.2.2 skrll { 911 1.78.2.2 skrll struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 912 1.78.2.2 skrll 913 1.78.2.2 skrll DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 914 1.78.2.2 skrll ether_sprintf(ni->ni_bssid))); 915 1.78.2.2 skrll (*sc->sc_node_free)(ic, ni); 916 1.78.2.2 skrll } 917 1.78.2.2 skrll 918 1.78.2.2 skrll 919 1.78.2.2 skrll static void 920 1.78.2.2 skrll atw_test1_reset(struct atw_softc *sc) 921 1.78.2.2 skrll { 922 1.78.2.2 skrll switch (sc->sc_rev) { 923 1.78.2.2 skrll case ATW_REVISION_BA: 924 1.78.2.2 skrll if (1 /* XXX condition on transceiver type */) { 925 1.78.2.2 skrll ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 926 1.78.2.2 skrll } 927 1.78.2.2 skrll break; 928 1.78.2.2 skrll case ATW_REVISION_CA: 929 1.78.2.2 skrll ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 930 1.78.2.2 skrll break; 931 1.78.2.2 skrll default: 932 1.78.2.2 skrll break; 933 1.78.2.2 skrll } 934 1.78.2.2 skrll } 935 1.78.2.2 skrll 936 1.78.2.2 skrll /* 937 1.78.2.2 skrll * atw_reset: 938 1.78.2.2 skrll * 939 1.78.2.2 skrll * Perform a soft reset on the ADM8211. 940 1.78.2.2 skrll */ 941 1.78.2.2 skrll void 942 1.78.2.2 skrll atw_reset(struct atw_softc *sc) 943 1.78.2.2 skrll { 944 1.78.2.2 skrll int i; 945 1.78.2.2 skrll uint32_t lpc; 946 1.78.2.2 skrll 947 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, 0x0); 948 1.78.2.2 skrll DELAY(atw_nar_delay); 949 1.78.2.2 skrll 950 1.78.2.2 skrll /* Reference driver has a cryptic remark indicating that this might 951 1.78.2.2 skrll * power-on the chip. I know that it turns off power-saving.... 952 1.78.2.2 skrll */ 953 1.78.2.2 skrll ATW_WRITE(sc, ATW_FRCTL, 0x0); 954 1.78.2.2 skrll 955 1.78.2.2 skrll ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 956 1.78.2.2 skrll 957 1.78.2.2 skrll for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 958 1.78.2.2 skrll if (ATW_READ(sc, ATW_PAR) == 0) 959 1.78.2.2 skrll break; 960 1.78.2.2 skrll DELAY(atw_pseudo_milli); 961 1.78.2.2 skrll } 962 1.78.2.2 skrll 963 1.78.2.2 skrll /* ... and then pause 100ms longer for good measure. */ 964 1.78.2.2 skrll DELAY(atw_magic_delay1); 965 1.78.2.2 skrll 966 1.78.2.2 skrll DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 967 1.78.2.2 skrll 968 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 969 1.78.2.2 skrll printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 970 1.78.2.2 skrll 971 1.78.2.2 skrll atw_test1_reset(sc); 972 1.78.2.2 skrll /* 973 1.78.2.2 skrll * Initialize the PCI Access Register. 974 1.78.2.2 skrll */ 975 1.78.2.2 skrll sc->sc_busmode = ATW_PAR_PBL_8DW; 976 1.78.2.2 skrll 977 1.78.2.2 skrll ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 978 1.78.2.2 skrll DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 979 1.78.2.2 skrll ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 980 1.78.2.2 skrll 981 1.78.2.2 skrll /* Turn off maximum power saving, etc. 982 1.78.2.2 skrll * 983 1.78.2.2 skrll * XXX Following example of reference driver, should I set 984 1.78.2.2 skrll * an AID of 1? It didn't seem to help.... 985 1.78.2.2 skrll */ 986 1.78.2.2 skrll ATW_WRITE(sc, ATW_FRCTL, 0x0); 987 1.78.2.2 skrll 988 1.78.2.2 skrll DELAY(atw_magic_delay2); 989 1.78.2.2 skrll 990 1.78.2.2 skrll /* Recall EEPROM. */ 991 1.78.2.2 skrll ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 992 1.78.2.2 skrll 993 1.78.2.2 skrll DELAY(atw_magic_delay4); 994 1.78.2.2 skrll 995 1.78.2.2 skrll lpc = ATW_READ(sc, ATW_LPC); 996 1.78.2.2 skrll 997 1.78.2.2 skrll DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 998 1.78.2.2 skrll 999 1.78.2.2 skrll /* A reset seems to affect the SRAM contents, so put them into 1000 1.78.2.2 skrll * a known state. 1001 1.78.2.2 skrll */ 1002 1.78.2.2 skrll atw_clear_sram(sc); 1003 1.78.2.2 skrll 1004 1.78.2.2 skrll memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1005 1.78.2.2 skrll } 1006 1.78.2.2 skrll 1007 1.78.2.2 skrll static void 1008 1.78.2.2 skrll atw_clear_sram(struct atw_softc *sc) 1009 1.78.2.2 skrll { 1010 1.78.2.2 skrll memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1011 1.78.2.2 skrll /* XXX not for revision 0x20. */ 1012 1.78.2.2 skrll atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1013 1.78.2.2 skrll } 1014 1.78.2.2 skrll 1015 1.78.2.2 skrll /* TBD atw_init 1016 1.78.2.2 skrll * 1017 1.78.2.2 skrll * set MAC based on ic->ic_bss->myaddr 1018 1.78.2.2 skrll * write WEP keys 1019 1.78.2.2 skrll * set TX rate 1020 1.78.2.2 skrll */ 1021 1.78.2.2 skrll 1022 1.78.2.2 skrll /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1023 1.78.2.2 skrll * without receiving a beacon with the preferred BSSID & SSID. 1024 1.78.2.2 skrll * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1025 1.78.2.2 skrll */ 1026 1.78.2.2 skrll static void 1027 1.78.2.2 skrll atw_wcsr_init(struct atw_softc *sc) 1028 1.78.2.2 skrll { 1029 1.78.2.2 skrll uint32_t wcsr; 1030 1.78.2.2 skrll 1031 1.78.2.2 skrll wcsr = ATW_READ(sc, ATW_WCSR); 1032 1.78.2.2 skrll wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1033 1.78.2.2 skrll wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1034 1.78.2.2 skrll ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1035 1.78.2.2 skrll 1036 1.78.2.2 skrll DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1037 1.78.2.2 skrll sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1038 1.78.2.2 skrll } 1039 1.78.2.2 skrll 1040 1.78.2.2 skrll /* Turn off power management. Set Rx store-and-forward mode. */ 1041 1.78.2.2 skrll static void 1042 1.78.2.2 skrll atw_cmdr_init(struct atw_softc *sc) 1043 1.78.2.2 skrll { 1044 1.78.2.2 skrll uint32_t cmdr; 1045 1.78.2.2 skrll cmdr = ATW_READ(sc, ATW_CMDR); 1046 1.78.2.2 skrll cmdr &= ~ATW_CMDR_APM; 1047 1.78.2.2 skrll cmdr |= ATW_CMDR_RTE; 1048 1.78.2.2 skrll cmdr &= ~ATW_CMDR_DRT_MASK; 1049 1.78.2.2 skrll cmdr |= ATW_CMDR_DRT_SF; 1050 1.78.2.2 skrll 1051 1.78.2.2 skrll ATW_WRITE(sc, ATW_CMDR, cmdr); 1052 1.78.2.2 skrll } 1053 1.78.2.2 skrll 1054 1.78.2.2 skrll static void 1055 1.78.2.2 skrll atw_tofs2_init(struct atw_softc *sc) 1056 1.78.2.2 skrll { 1057 1.78.2.2 skrll uint32_t tofs2; 1058 1.78.2.2 skrll /* XXX this magic can probably be figured out from the RFMD docs */ 1059 1.78.2.2 skrll #ifndef ATW_REFSLAVE 1060 1.78.2.2 skrll tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1061 1.78.2.2 skrll LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1062 1.78.2.2 skrll LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1063 1.78.2.2 skrll LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1064 1.78.2.2 skrll LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1065 1.78.2.2 skrll LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1066 1.78.2.2 skrll LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1067 1.78.2.2 skrll LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1068 1.78.2.2 skrll #else 1069 1.78.2.2 skrll /* XXX new magic from reference driver source */ 1070 1.78.2.2 skrll tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1071 1.78.2.2 skrll LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1072 1.78.2.2 skrll LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1073 1.78.2.2 skrll LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1074 1.78.2.2 skrll LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1075 1.78.2.2 skrll LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1076 1.78.2.2 skrll LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1077 1.78.2.2 skrll LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1078 1.78.2.2 skrll #endif 1079 1.78.2.2 skrll ATW_WRITE(sc, ATW_TOFS2, tofs2); 1080 1.78.2.2 skrll } 1081 1.78.2.2 skrll 1082 1.78.2.2 skrll static void 1083 1.78.2.2 skrll atw_nar_init(struct atw_softc *sc) 1084 1.78.2.2 skrll { 1085 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1086 1.78.2.2 skrll } 1087 1.78.2.2 skrll 1088 1.78.2.2 skrll static void 1089 1.78.2.2 skrll atw_txlmt_init(struct atw_softc *sc) 1090 1.78.2.2 skrll { 1091 1.78.2.2 skrll ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1092 1.78.2.2 skrll LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1093 1.78.2.2 skrll } 1094 1.78.2.2 skrll 1095 1.78.2.2 skrll static void 1096 1.78.2.2 skrll atw_test1_init(struct atw_softc *sc) 1097 1.78.2.2 skrll { 1098 1.78.2.2 skrll uint32_t test1; 1099 1.78.2.2 skrll 1100 1.78.2.2 skrll test1 = ATW_READ(sc, ATW_TEST1); 1101 1.78.2.2 skrll test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1102 1.78.2.2 skrll /* XXX magic 0x1 */ 1103 1.78.2.2 skrll test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1104 1.78.2.2 skrll ATW_WRITE(sc, ATW_TEST1, test1); 1105 1.78.2.2 skrll } 1106 1.78.2.2 skrll 1107 1.78.2.2 skrll static void 1108 1.78.2.2 skrll atw_rf_reset(struct atw_softc *sc) 1109 1.78.2.2 skrll { 1110 1.78.2.2 skrll /* XXX this resets an Intersil RF front-end? */ 1111 1.78.2.2 skrll /* TBD condition on Intersil RFType? */ 1112 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1113 1.78.2.2 skrll DELAY(atw_rf_delay1); 1114 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, 0); 1115 1.78.2.2 skrll DELAY(atw_rf_delay2); 1116 1.78.2.2 skrll } 1117 1.78.2.2 skrll 1118 1.78.2.2 skrll /* Set 16 TU max duration for the contention-free period (CFP). */ 1119 1.78.2.2 skrll static void 1120 1.78.2.2 skrll atw_cfp_init(struct atw_softc *sc) 1121 1.78.2.2 skrll { 1122 1.78.2.2 skrll uint32_t cfpp; 1123 1.78.2.2 skrll 1124 1.78.2.2 skrll cfpp = ATW_READ(sc, ATW_CFPP); 1125 1.78.2.2 skrll cfpp &= ~ATW_CFPP_CFPMD; 1126 1.78.2.2 skrll cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1127 1.78.2.2 skrll ATW_WRITE(sc, ATW_CFPP, cfpp); 1128 1.78.2.2 skrll } 1129 1.78.2.2 skrll 1130 1.78.2.2 skrll static void 1131 1.78.2.2 skrll atw_tofs0_init(struct atw_softc *sc) 1132 1.78.2.2 skrll { 1133 1.78.2.2 skrll /* XXX I guess that the Cardbus clock is 22MHz? 1134 1.78.2.2 skrll * I am assuming that the role of ATW_TOFS0_USCNT is 1135 1.78.2.2 skrll * to divide the bus clock to get a 1MHz clock---the datasheet is not 1136 1.78.2.2 skrll * very clear on this point. It says in the datasheet that it is 1137 1.78.2.2 skrll * possible for the ADM8211 to accomodate bus speeds between 22MHz 1138 1.78.2.2 skrll * and 33MHz; maybe this is the way? I see a binary-only driver write 1139 1.78.2.2 skrll * these values. These values are also the power-on default. 1140 1.78.2.2 skrll */ 1141 1.78.2.2 skrll ATW_WRITE(sc, ATW_TOFS0, 1142 1.78.2.2 skrll LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1143 1.78.2.2 skrll ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1144 1.78.2.2 skrll } 1145 1.78.2.2 skrll 1146 1.78.2.2 skrll /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1147 1.78.2.2 skrll static void 1148 1.78.2.2 skrll atw_ifs_init(struct atw_softc *sc) 1149 1.78.2.2 skrll { 1150 1.78.2.2 skrll uint32_t ifst; 1151 1.78.2.2 skrll /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1152 1.78.2.2 skrll * Go figure. 1153 1.78.2.2 skrll */ 1154 1.78.2.2 skrll ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1155 1.78.2.2 skrll LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1156 1.78.2.2 skrll ATW_IFST_SIFS_MASK) | 1157 1.78.2.2 skrll LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1158 1.78.2.2 skrll LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1159 1.78.2.2 skrll 1160 1.78.2.2 skrll ATW_WRITE(sc, ATW_IFST, ifst); 1161 1.78.2.2 skrll } 1162 1.78.2.2 skrll 1163 1.78.2.2 skrll static void 1164 1.78.2.2 skrll atw_response_times_init(struct atw_softc *sc) 1165 1.78.2.2 skrll { 1166 1.78.2.2 skrll /* XXX More magic. Relates to ACK timing? The datasheet seems to 1167 1.78.2.2 skrll * indicate that the MAC expects at least SIFS + MIRT microseconds 1168 1.78.2.2 skrll * to pass after it transmits a frame that requires a response; 1169 1.78.2.2 skrll * it waits at most SIFS + MART microseconds for the response. 1170 1.78.2.2 skrll * Surely this is not the ACK timeout? 1171 1.78.2.2 skrll */ 1172 1.78.2.2 skrll ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1173 1.78.2.2 skrll LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1174 1.78.2.2 skrll } 1175 1.78.2.2 skrll 1176 1.78.2.2 skrll /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1177 1.78.2.2 skrll * engines read and write baseband registers after Rx and before 1178 1.78.2.2 skrll * Tx, respectively. 1179 1.78.2.2 skrll */ 1180 1.78.2.2 skrll static void 1181 1.78.2.2 skrll atw_bbp_io_init(struct atw_softc *sc) 1182 1.78.2.2 skrll { 1183 1.78.2.2 skrll uint32_t mmiraddr2; 1184 1.78.2.2 skrll 1185 1.78.2.2 skrll /* XXX The reference driver does this, but is it *really* 1186 1.78.2.2 skrll * necessary? 1187 1.78.2.2 skrll */ 1188 1.78.2.2 skrll switch (sc->sc_rev) { 1189 1.78.2.2 skrll case ATW_REVISION_AB: 1190 1.78.2.2 skrll case ATW_REVISION_AF: 1191 1.78.2.2 skrll mmiraddr2 = 0x0; 1192 1.78.2.2 skrll break; 1193 1.78.2.2 skrll default: 1194 1.78.2.2 skrll mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1195 1.78.2.2 skrll mmiraddr2 &= 1196 1.78.2.2 skrll ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1197 1.78.2.2 skrll break; 1198 1.78.2.2 skrll } 1199 1.78.2.2 skrll 1200 1.78.2.2 skrll switch (sc->sc_bbptype) { 1201 1.78.2.2 skrll case ATW_BBPTYPE_INTERSIL: 1202 1.78.2.2 skrll ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1203 1.78.2.2 skrll ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1204 1.78.2.2 skrll mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1205 1.78.2.2 skrll break; 1206 1.78.2.2 skrll case ATW_BBPTYPE_MARVEL: 1207 1.78.2.2 skrll /* TBD find out the Marvel settings. */ 1208 1.78.2.2 skrll break; 1209 1.78.2.2 skrll case ATW_BBPTYPE_RFMD: 1210 1.78.2.2 skrll default: 1211 1.78.2.2 skrll ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1212 1.78.2.2 skrll ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1213 1.78.2.2 skrll mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1214 1.78.2.2 skrll break; 1215 1.78.2.2 skrll } 1216 1.78.2.2 skrll ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1217 1.78.2.2 skrll ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1218 1.78.2.2 skrll } 1219 1.78.2.2 skrll 1220 1.78.2.2 skrll /* 1221 1.78.2.2 skrll * atw_init: [ ifnet interface function ] 1222 1.78.2.2 skrll * 1223 1.78.2.2 skrll * Initialize the interface. Must be called at splnet(). 1224 1.78.2.2 skrll */ 1225 1.78.2.2 skrll int 1226 1.78.2.2 skrll atw_init(struct ifnet *ifp) 1227 1.78.2.2 skrll { 1228 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 1229 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1230 1.78.2.2 skrll struct atw_txsoft *txs; 1231 1.78.2.2 skrll struct atw_rxsoft *rxs; 1232 1.78.2.2 skrll int i, error = 0; 1233 1.78.2.2 skrll 1234 1.78.2.2 skrll if ((error = atw_enable(sc)) != 0) 1235 1.78.2.2 skrll goto out; 1236 1.78.2.2 skrll 1237 1.78.2.2 skrll /* 1238 1.78.2.2 skrll * Cancel any pending I/O. This also resets. 1239 1.78.2.2 skrll */ 1240 1.78.2.2 skrll atw_stop(ifp, 0); 1241 1.78.2.2 skrll 1242 1.78.2.2 skrll ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1243 1.78.2.2 skrll DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1244 1.78.2.2 skrll __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1245 1.78.2.2 skrll ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1246 1.78.2.2 skrll 1247 1.78.2.2 skrll atw_wcsr_init(sc); 1248 1.78.2.2 skrll 1249 1.78.2.2 skrll atw_cmdr_init(sc); 1250 1.78.2.2 skrll 1251 1.78.2.2 skrll /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1252 1.78.2.2 skrll * 1253 1.78.2.2 skrll * XXX Set transmit power for ATIM, RTS, Beacon. 1254 1.78.2.2 skrll */ 1255 1.78.2.2 skrll ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1256 1.78.2.2 skrll LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1257 1.78.2.2 skrll 1258 1.78.2.2 skrll atw_tofs2_init(sc); 1259 1.78.2.2 skrll 1260 1.78.2.2 skrll atw_nar_init(sc); 1261 1.78.2.2 skrll 1262 1.78.2.2 skrll atw_txlmt_init(sc); 1263 1.78.2.2 skrll 1264 1.78.2.2 skrll atw_test1_init(sc); 1265 1.78.2.2 skrll 1266 1.78.2.2 skrll atw_rf_reset(sc); 1267 1.78.2.2 skrll 1268 1.78.2.2 skrll atw_cfp_init(sc); 1269 1.78.2.2 skrll 1270 1.78.2.2 skrll atw_tofs0_init(sc); 1271 1.78.2.2 skrll 1272 1.78.2.2 skrll atw_ifs_init(sc); 1273 1.78.2.2 skrll 1274 1.78.2.2 skrll /* XXX Fall asleep after one second of inactivity. 1275 1.78.2.2 skrll * XXX A frame may only dribble in for 65536us. 1276 1.78.2.2 skrll */ 1277 1.78.2.2 skrll ATW_WRITE(sc, ATW_RMD, 1278 1.78.2.2 skrll LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1279 1.78.2.2 skrll 1280 1.78.2.2 skrll atw_response_times_init(sc); 1281 1.78.2.2 skrll 1282 1.78.2.2 skrll atw_bbp_io_init(sc); 1283 1.78.2.2 skrll 1284 1.78.2.2 skrll ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1285 1.78.2.2 skrll 1286 1.78.2.2 skrll if ((error = atw_rf3000_init(sc)) != 0) 1287 1.78.2.2 skrll goto out; 1288 1.78.2.2 skrll 1289 1.78.2.2 skrll ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1290 1.78.2.2 skrll DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1291 1.78.2.2 skrll ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1292 1.78.2.2 skrll 1293 1.78.2.2 skrll /* 1294 1.78.2.2 skrll * Initialize the transmit descriptor ring. 1295 1.78.2.2 skrll */ 1296 1.78.2.2 skrll memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1297 1.78.2.2 skrll for (i = 0; i < ATW_NTXDESC; i++) { 1298 1.78.2.2 skrll sc->sc_txdescs[i].at_ctl = 0; 1299 1.78.2.2 skrll /* no transmit chaining */ 1300 1.78.2.2 skrll sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1301 1.78.2.2 skrll sc->sc_txdescs[i].at_buf2 = 1302 1.78.2.2 skrll htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1303 1.78.2.2 skrll } 1304 1.78.2.2 skrll /* use ring mode */ 1305 1.78.2.2 skrll sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1306 1.78.2.2 skrll ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1307 1.78.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1308 1.78.2.2 skrll sc->sc_txfree = ATW_NTXDESC; 1309 1.78.2.2 skrll sc->sc_txnext = 0; 1310 1.78.2.2 skrll 1311 1.78.2.2 skrll /* 1312 1.78.2.2 skrll * Initialize the transmit job descriptors. 1313 1.78.2.2 skrll */ 1314 1.78.2.2 skrll SIMPLEQ_INIT(&sc->sc_txfreeq); 1315 1.78.2.2 skrll SIMPLEQ_INIT(&sc->sc_txdirtyq); 1316 1.78.2.2 skrll for (i = 0; i < ATW_TXQUEUELEN; i++) { 1317 1.78.2.2 skrll txs = &sc->sc_txsoft[i]; 1318 1.78.2.2 skrll txs->txs_mbuf = NULL; 1319 1.78.2.2 skrll SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1320 1.78.2.2 skrll } 1321 1.78.2.2 skrll 1322 1.78.2.2 skrll /* 1323 1.78.2.2 skrll * Initialize the receive descriptor and receive job 1324 1.78.2.2 skrll * descriptor rings. 1325 1.78.2.2 skrll */ 1326 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 1327 1.78.2.2 skrll rxs = &sc->sc_rxsoft[i]; 1328 1.78.2.2 skrll if (rxs->rxs_mbuf == NULL) { 1329 1.78.2.2 skrll if ((error = atw_add_rxbuf(sc, i)) != 0) { 1330 1.78.2.2 skrll printf("%s: unable to allocate or map rx " 1331 1.78.2.2 skrll "buffer %d, error = %d\n", 1332 1.78.2.2 skrll sc->sc_dev.dv_xname, i, error); 1333 1.78.2.2 skrll /* 1334 1.78.2.2 skrll * XXX Should attempt to run with fewer receive 1335 1.78.2.2 skrll * XXX buffers instead of just failing. 1336 1.78.2.2 skrll */ 1337 1.78.2.2 skrll atw_rxdrain(sc); 1338 1.78.2.2 skrll goto out; 1339 1.78.2.2 skrll } 1340 1.78.2.2 skrll } else 1341 1.78.2.2 skrll ATW_INIT_RXDESC(sc, i); 1342 1.78.2.2 skrll } 1343 1.78.2.2 skrll sc->sc_rxptr = 0; 1344 1.78.2.2 skrll 1345 1.78.2.2 skrll /* 1346 1.78.2.2 skrll * Initialize the interrupt mask and enable interrupts. 1347 1.78.2.2 skrll */ 1348 1.78.2.2 skrll /* normal interrupts */ 1349 1.78.2.2 skrll sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1350 1.78.2.2 skrll ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1351 1.78.2.2 skrll 1352 1.78.2.2 skrll /* abnormal interrupts */ 1353 1.78.2.2 skrll sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1354 1.78.2.2 skrll ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1355 1.78.2.2 skrll ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1356 1.78.2.2 skrll 1357 1.78.2.2 skrll sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1358 1.78.2.2 skrll ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1359 1.78.2.2 skrll sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1360 1.78.2.2 skrll sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1361 1.78.2.2 skrll ATW_INTR_TRT; 1362 1.78.2.2 skrll 1363 1.78.2.2 skrll sc->sc_linkint_mask &= sc->sc_inten; 1364 1.78.2.2 skrll sc->sc_rxint_mask &= sc->sc_inten; 1365 1.78.2.2 skrll sc->sc_txint_mask &= sc->sc_inten; 1366 1.78.2.2 skrll 1367 1.78.2.2 skrll ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1368 1.78.2.2 skrll ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1369 1.78.2.2 skrll 1370 1.78.2.2 skrll DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1371 1.78.2.2 skrll sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1372 1.78.2.2 skrll 1373 1.78.2.2 skrll /* 1374 1.78.2.2 skrll * Give the transmit and receive rings to the ADM8211. 1375 1.78.2.2 skrll */ 1376 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1377 1.78.2.2 skrll ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1378 1.78.2.2 skrll 1379 1.78.2.2 skrll sc->sc_txthresh = 0; 1380 1.78.2.2 skrll sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1381 1.78.2.2 skrll sc->sc_txth[sc->sc_txthresh].txth_opmode; 1382 1.78.2.2 skrll 1383 1.78.2.2 skrll /* common 802.11 configuration */ 1384 1.78.2.2 skrll ic->ic_flags &= ~IEEE80211_F_IBSSON; 1385 1.78.2.2 skrll switch (ic->ic_opmode) { 1386 1.78.2.2 skrll case IEEE80211_M_STA: 1387 1.78.2.2 skrll break; 1388 1.78.2.2 skrll case IEEE80211_M_AHDEMO: /* XXX */ 1389 1.78.2.2 skrll case IEEE80211_M_IBSS: 1390 1.78.2.2 skrll ic->ic_flags |= IEEE80211_F_IBSSON; 1391 1.78.2.2 skrll /*FALLTHROUGH*/ 1392 1.78.2.2 skrll case IEEE80211_M_HOSTAP: /* XXX */ 1393 1.78.2.2 skrll break; 1394 1.78.2.2 skrll case IEEE80211_M_MONITOR: /* XXX */ 1395 1.78.2.2 skrll break; 1396 1.78.2.2 skrll } 1397 1.78.2.2 skrll 1398 1.78.2.2 skrll switch (ic->ic_opmode) { 1399 1.78.2.2 skrll case IEEE80211_M_AHDEMO: 1400 1.78.2.2 skrll case IEEE80211_M_HOSTAP: 1401 1.78.2.2 skrll ic->ic_bss->ni_intval = ic->ic_lintval; 1402 1.78.2.2 skrll ic->ic_bss->ni_rssi = 0; 1403 1.78.2.2 skrll ic->ic_bss->ni_rstamp = 0; 1404 1.78.2.2 skrll break; 1405 1.78.2.2 skrll default: /* XXX */ 1406 1.78.2.2 skrll break; 1407 1.78.2.2 skrll } 1408 1.78.2.2 skrll 1409 1.78.2.2 skrll sc->sc_wepctl = 0; 1410 1.78.2.2 skrll 1411 1.78.2.2 skrll atw_write_ssid(sc); 1412 1.78.2.2 skrll atw_write_sup_rates(sc); 1413 1.78.2.2 skrll if (ic->ic_caps & IEEE80211_C_WEP) 1414 1.78.2.2 skrll atw_write_wep(sc); 1415 1.78.2.2 skrll 1416 1.78.2.2 skrll ic->ic_state = IEEE80211_S_INIT; 1417 1.78.2.2 skrll 1418 1.78.2.2 skrll /* 1419 1.78.2.2 skrll * Set the receive filter. This will start the transmit and 1420 1.78.2.2 skrll * receive processes. 1421 1.78.2.2 skrll */ 1422 1.78.2.2 skrll atw_filter_setup(sc); 1423 1.78.2.2 skrll 1424 1.78.2.2 skrll /* 1425 1.78.2.2 skrll * Start the receive process. 1426 1.78.2.2 skrll */ 1427 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDR, 0x1); 1428 1.78.2.2 skrll 1429 1.78.2.2 skrll /* 1430 1.78.2.2 skrll * Note that the interface is now running. 1431 1.78.2.2 skrll */ 1432 1.78.2.2 skrll ifp->if_flags |= IFF_RUNNING; 1433 1.78.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1434 1.78.2.2 skrll 1435 1.78.2.2 skrll /* send no beacons, yet. */ 1436 1.78.2.2 skrll atw_start_beacon(sc, 0); 1437 1.78.2.2 skrll 1438 1.78.2.2 skrll if (ic->ic_opmode == IEEE80211_M_MONITOR) 1439 1.78.2.2 skrll error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1440 1.78.2.2 skrll else 1441 1.78.2.2 skrll error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1442 1.78.2.2 skrll out: 1443 1.78.2.2 skrll if (error) { 1444 1.78.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1445 1.78.2.2 skrll ifp->if_timer = 0; 1446 1.78.2.2 skrll printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1447 1.78.2.2 skrll } 1448 1.78.2.2 skrll #ifdef ATW_DEBUG 1449 1.78.2.2 skrll atw_print_regs(sc, "end of init"); 1450 1.78.2.2 skrll #endif /* ATW_DEBUG */ 1451 1.78.2.2 skrll 1452 1.78.2.2 skrll return (error); 1453 1.78.2.2 skrll } 1454 1.78.2.2 skrll 1455 1.78.2.2 skrll /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1456 1.78.2.2 skrll * 0: MAC control of RF3000/Si4126. 1457 1.78.2.2 skrll * 1458 1.78.2.2 skrll * Applies power, or selects RF front-end? Sets reset condition. 1459 1.78.2.2 skrll * 1460 1.78.2.2 skrll * TBD support non-RFMD BBP, non-SiLabs synth. 1461 1.78.2.2 skrll */ 1462 1.78.2.2 skrll static void 1463 1.78.2.2 skrll atw_bbp_io_enable(struct atw_softc *sc, int enable) 1464 1.78.2.2 skrll { 1465 1.78.2.2 skrll if (enable) { 1466 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, 1467 1.78.2.2 skrll ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1468 1.78.2.2 skrll DELAY(atw_bbp_io_enable_delay); 1469 1.78.2.2 skrll } else { 1470 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, 0); 1471 1.78.2.2 skrll DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1472 1.78.2.2 skrll } 1473 1.78.2.2 skrll } 1474 1.78.2.2 skrll 1475 1.78.2.2 skrll static int 1476 1.78.2.2 skrll atw_tune(struct atw_softc *sc) 1477 1.78.2.2 skrll { 1478 1.78.2.2 skrll int rc; 1479 1.78.2.2 skrll u_int chan; 1480 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1481 1.78.2.2 skrll 1482 1.78.2.2 skrll chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1483 1.78.2.2 skrll if (chan == IEEE80211_CHAN_ANY) 1484 1.78.2.2 skrll panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1485 1.78.2.2 skrll 1486 1.78.2.2 skrll if (chan == sc->sc_cur_chan) 1487 1.78.2.2 skrll return 0; 1488 1.78.2.2 skrll 1489 1.78.2.2 skrll DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1490 1.78.2.2 skrll sc->sc_cur_chan, chan)); 1491 1.78.2.2 skrll 1492 1.78.2.2 skrll atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1493 1.78.2.2 skrll 1494 1.78.2.2 skrll atw_si4126_tune(sc, chan); 1495 1.78.2.2 skrll if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1496 1.78.2.2 skrll printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1497 1.78.2.2 skrll chan); 1498 1.78.2.2 skrll 1499 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1500 1.78.2.2 skrll DELAY(atw_nar_delay); 1501 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDR, 0x1); 1502 1.78.2.2 skrll 1503 1.78.2.2 skrll if (rc == 0) 1504 1.78.2.2 skrll sc->sc_cur_chan = chan; 1505 1.78.2.2 skrll 1506 1.78.2.2 skrll return rc; 1507 1.78.2.2 skrll } 1508 1.78.2.2 skrll 1509 1.78.2.2 skrll #ifdef ATW_SYNDEBUG 1510 1.78.2.2 skrll static void 1511 1.78.2.2 skrll atw_si4126_print(struct atw_softc *sc) 1512 1.78.2.2 skrll { 1513 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 1514 1.78.2.2 skrll u_int addr, val; 1515 1.78.2.2 skrll 1516 1.78.2.2 skrll if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1517 1.78.2.2 skrll return; 1518 1.78.2.2 skrll 1519 1.78.2.2 skrll for (addr = 0; addr <= 8; addr++) { 1520 1.78.2.2 skrll printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1521 1.78.2.2 skrll if (atw_si4126_read(sc, addr, &val) == 0) { 1522 1.78.2.2 skrll printf("<unknown> (quitting print-out)\n"); 1523 1.78.2.2 skrll break; 1524 1.78.2.2 skrll } 1525 1.78.2.2 skrll printf("%05x\n", val); 1526 1.78.2.2 skrll } 1527 1.78.2.2 skrll } 1528 1.78.2.2 skrll #endif /* ATW_SYNDEBUG */ 1529 1.78.2.2 skrll 1530 1.78.2.2 skrll /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1531 1.78.2.2 skrll * 1532 1.78.2.2 skrll * The RF/IF synthesizer produces two reference frequencies for 1533 1.78.2.2 skrll * the RF2948B transceiver. The first frequency the RF2948B requires 1534 1.78.2.2 skrll * is two times the so-called "intermediate frequency" (IF). Since 1535 1.78.2.2 skrll * a SAW filter on the radio fixes the IF at 374MHz, I program the 1536 1.78.2.2 skrll * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1537 1.78.2.2 skrll * frequency required by the transceiver is the radio frequency 1538 1.78.2.2 skrll * (RF). This is a superheterodyne transceiver; for f(chan) the 1539 1.78.2.2 skrll * center frequency of the channel we are tuning, RF = f(chan) - 1540 1.78.2.2 skrll * IF. 1541 1.78.2.2 skrll * 1542 1.78.2.2 skrll * XXX I am told by SiLabs that the Si4126 will accept a broader range 1543 1.78.2.2 skrll * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1544 1.78.2.2 skrll * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1545 1.78.2.2 skrll * works, but I have still programmed for XINDIV2 = 1 to be safe. 1546 1.78.2.2 skrll */ 1547 1.78.2.2 skrll static void 1548 1.78.2.2 skrll atw_si4126_tune(struct atw_softc *sc, u_int chan) 1549 1.78.2.2 skrll { 1550 1.78.2.2 skrll u_int mhz; 1551 1.78.2.2 skrll u_int R; 1552 1.78.2.2 skrll u_int32_t gpio; 1553 1.78.2.2 skrll u_int16_t gain; 1554 1.78.2.2 skrll 1555 1.78.2.2 skrll #ifdef ATW_SYNDEBUG 1556 1.78.2.2 skrll atw_si4126_print(sc); 1557 1.78.2.2 skrll #endif /* ATW_SYNDEBUG */ 1558 1.78.2.2 skrll 1559 1.78.2.2 skrll if (chan == 14) 1560 1.78.2.2 skrll mhz = 2484; 1561 1.78.2.2 skrll else 1562 1.78.2.2 skrll mhz = 2412 + 5 * (chan - 1); 1563 1.78.2.2 skrll 1564 1.78.2.2 skrll /* Tune IF to 748MHz to suit the IF LO input of the 1565 1.78.2.2 skrll * RF2494B, which is 2 x IF. No need to set an IF divider 1566 1.78.2.2 skrll * because an IF in 526MHz - 952MHz is allowed. 1567 1.78.2.2 skrll * 1568 1.78.2.2 skrll * XIN is 44.000MHz, so divide it by two to get allowable 1569 1.78.2.2 skrll * range of 2-25MHz. SiLabs tells me that this is not 1570 1.78.2.2 skrll * strictly necessary. 1571 1.78.2.2 skrll */ 1572 1.78.2.2 skrll 1573 1.78.2.2 skrll if (atw_xindiv2) 1574 1.78.2.2 skrll R = 44; 1575 1.78.2.2 skrll else 1576 1.78.2.2 skrll R = 88; 1577 1.78.2.2 skrll 1578 1.78.2.2 skrll /* Power-up RF, IF synthesizers. */ 1579 1.78.2.2 skrll atw_si4126_write(sc, SI4126_POWER, 1580 1.78.2.2 skrll SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1581 1.78.2.2 skrll 1582 1.78.2.2 skrll /* set LPWR, too? */ 1583 1.78.2.2 skrll atw_si4126_write(sc, SI4126_MAIN, 1584 1.78.2.2 skrll (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1585 1.78.2.2 skrll 1586 1.78.2.2 skrll /* Set the phase-locked loop gain. If RF2 N > 2047, then 1587 1.78.2.2 skrll * set KP2 to 1. 1588 1.78.2.2 skrll * 1589 1.78.2.2 skrll * REFDIF This is different from the reference driver, which 1590 1.78.2.2 skrll * always sets SI4126_GAIN to 0. 1591 1.78.2.2 skrll */ 1592 1.78.2.2 skrll gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1593 1.78.2.2 skrll 1594 1.78.2.2 skrll atw_si4126_write(sc, SI4126_GAIN, gain); 1595 1.78.2.2 skrll 1596 1.78.2.2 skrll /* XIN = 44MHz. 1597 1.78.2.2 skrll * 1598 1.78.2.2 skrll * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1599 1.78.2.2 skrll * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1600 1.78.2.2 skrll * 1601 1.78.2.2 skrll * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1602 1.78.2.2 skrll * so that 1496/88 * 44MHz = 748MHz. 1603 1.78.2.2 skrll */ 1604 1.78.2.2 skrll atw_si4126_write(sc, SI4126_IFN, 1496); 1605 1.78.2.2 skrll 1606 1.78.2.2 skrll atw_si4126_write(sc, SI4126_IFR, R); 1607 1.78.2.2 skrll 1608 1.78.2.2 skrll #ifndef ATW_REFSLAVE 1609 1.78.2.2 skrll /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1610 1.78.2.2 skrll * then RF1 becomes the active RF synthesizer, even on the Si4126, 1611 1.78.2.2 skrll * which has no RF1! 1612 1.78.2.2 skrll */ 1613 1.78.2.2 skrll atw_si4126_write(sc, SI4126_RF1R, R); 1614 1.78.2.2 skrll 1615 1.78.2.2 skrll atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1616 1.78.2.2 skrll #endif 1617 1.78.2.2 skrll 1618 1.78.2.2 skrll /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1619 1.78.2.2 skrll * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1620 1.78.2.2 skrll * Now let's multiply it to mhz. So mhz - IF = N. 1621 1.78.2.2 skrll */ 1622 1.78.2.2 skrll atw_si4126_write(sc, SI4126_RF2R, R); 1623 1.78.2.2 skrll 1624 1.78.2.2 skrll atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1625 1.78.2.2 skrll 1626 1.78.2.2 skrll /* wait 100us from power-up for RF, IF to settle */ 1627 1.78.2.2 skrll DELAY(100); 1628 1.78.2.2 skrll 1629 1.78.2.2 skrll gpio = ATW_READ(sc, ATW_GPIO); 1630 1.78.2.2 skrll gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1631 1.78.2.2 skrll gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1632 1.78.2.2 skrll 1633 1.78.2.2 skrll if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1634 1.78.2.2 skrll /* Set a Prism RF front-end to a special mode for channel 14? 1635 1.78.2.2 skrll * 1636 1.78.2.2 skrll * Apparently the SMC2635W needs this, although I don't think 1637 1.78.2.2 skrll * it has a Prism RF. 1638 1.78.2.2 skrll */ 1639 1.78.2.2 skrll gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1640 1.78.2.2 skrll } 1641 1.78.2.2 skrll ATW_WRITE(sc, ATW_GPIO, gpio); 1642 1.78.2.2 skrll 1643 1.78.2.2 skrll #ifdef ATW_SYNDEBUG 1644 1.78.2.2 skrll atw_si4126_print(sc); 1645 1.78.2.2 skrll #endif /* ATW_SYNDEBUG */ 1646 1.78.2.2 skrll } 1647 1.78.2.2 skrll 1648 1.78.2.2 skrll /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1649 1.78.2.2 skrll * diversity. 1650 1.78.2.2 skrll * 1651 1.78.2.2 skrll * !!! 1652 1.78.2.2 skrll * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1653 1.78.2.2 skrll * !!! 1654 1.78.2.2 skrll */ 1655 1.78.2.2 skrll static int 1656 1.78.2.2 skrll atw_rf3000_init(struct atw_softc *sc) 1657 1.78.2.2 skrll { 1658 1.78.2.2 skrll int rc = 0; 1659 1.78.2.2 skrll 1660 1.78.2.2 skrll atw_bbp_io_enable(sc, 1); 1661 1.78.2.2 skrll 1662 1.78.2.2 skrll /* CCA is acquisition sensitive */ 1663 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_CCACTL, 1664 1.78.2.2 skrll LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1665 1.78.2.2 skrll 1666 1.78.2.2 skrll if (rc != 0) 1667 1.78.2.2 skrll goto out; 1668 1.78.2.2 skrll 1669 1.78.2.2 skrll /* enable diversity */ 1670 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1671 1.78.2.2 skrll 1672 1.78.2.2 skrll if (rc != 0) 1673 1.78.2.2 skrll goto out; 1674 1.78.2.2 skrll 1675 1.78.2.2 skrll /* sensible setting from a binary-only driver */ 1676 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1677 1.78.2.2 skrll LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1678 1.78.2.2 skrll 1679 1.78.2.2 skrll if (rc != 0) 1680 1.78.2.2 skrll goto out; 1681 1.78.2.2 skrll 1682 1.78.2.2 skrll /* magic from a binary-only driver */ 1683 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1684 1.78.2.2 skrll LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1685 1.78.2.2 skrll 1686 1.78.2.2 skrll if (rc != 0) 1687 1.78.2.2 skrll goto out; 1688 1.78.2.2 skrll 1689 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1690 1.78.2.2 skrll 1691 1.78.2.2 skrll if (rc != 0) 1692 1.78.2.2 skrll goto out; 1693 1.78.2.2 skrll 1694 1.78.2.2 skrll /* XXX Reference driver remarks that Abocom sets this to 50. 1695 1.78.2.2 skrll * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1696 1.78.2.2 skrll * in the "reserved" area of register RF3000_OPTIONS1. 1697 1.78.2.2 skrll */ 1698 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1699 1.78.2.2 skrll 1700 1.78.2.2 skrll if (rc != 0) 1701 1.78.2.2 skrll goto out; 1702 1.78.2.2 skrll 1703 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1704 1.78.2.2 skrll 1705 1.78.2.2 skrll if (rc != 0) 1706 1.78.2.2 skrll goto out; 1707 1.78.2.2 skrll 1708 1.78.2.2 skrll out: 1709 1.78.2.2 skrll atw_bbp_io_enable(sc, 0); 1710 1.78.2.2 skrll return rc; 1711 1.78.2.2 skrll } 1712 1.78.2.2 skrll 1713 1.78.2.2 skrll #ifdef ATW_BBPDEBUG 1714 1.78.2.2 skrll static void 1715 1.78.2.2 skrll atw_rf3000_print(struct atw_softc *sc) 1716 1.78.2.2 skrll { 1717 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 1718 1.78.2.2 skrll u_int addr, val; 1719 1.78.2.2 skrll 1720 1.78.2.2 skrll if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1721 1.78.2.2 skrll return; 1722 1.78.2.2 skrll 1723 1.78.2.2 skrll for (addr = 0x01; addr <= 0x15; addr++) { 1724 1.78.2.2 skrll printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1725 1.78.2.2 skrll if (atw_rf3000_read(sc, addr, &val) != 0) { 1726 1.78.2.2 skrll printf("<unknown> (quitting print-out)\n"); 1727 1.78.2.2 skrll break; 1728 1.78.2.2 skrll } 1729 1.78.2.2 skrll printf("%08x\n", val); 1730 1.78.2.2 skrll } 1731 1.78.2.2 skrll } 1732 1.78.2.2 skrll #endif /* ATW_BBPDEBUG */ 1733 1.78.2.2 skrll 1734 1.78.2.2 skrll /* Set the power settings on the BBP for channel `chan'. */ 1735 1.78.2.2 skrll static int 1736 1.78.2.2 skrll atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1737 1.78.2.2 skrll { 1738 1.78.2.2 skrll int rc = 0; 1739 1.78.2.2 skrll u_int32_t reg; 1740 1.78.2.2 skrll u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1741 1.78.2.2 skrll 1742 1.78.2.2 skrll txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1743 1.78.2.2 skrll lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1744 1.78.2.2 skrll lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1745 1.78.2.2 skrll 1746 1.78.2.2 skrll /* odd channels: LSB, even channels: MSB */ 1747 1.78.2.2 skrll if (chan % 2 == 1) { 1748 1.78.2.2 skrll txpower &= 0xFF; 1749 1.78.2.2 skrll lpf_cutoff &= 0xFF; 1750 1.78.2.2 skrll lna_gs_thresh &= 0xFF; 1751 1.78.2.2 skrll } else { 1752 1.78.2.2 skrll txpower >>= 8; 1753 1.78.2.2 skrll lpf_cutoff >>= 8; 1754 1.78.2.2 skrll lna_gs_thresh >>= 8; 1755 1.78.2.2 skrll } 1756 1.78.2.2 skrll 1757 1.78.2.2 skrll #ifdef ATW_BBPDEBUG 1758 1.78.2.2 skrll atw_rf3000_print(sc); 1759 1.78.2.2 skrll #endif /* ATW_BBPDEBUG */ 1760 1.78.2.2 skrll 1761 1.78.2.2 skrll DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1762 1.78.2.2 skrll "lna_gs_thresh %02x\n", 1763 1.78.2.2 skrll sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1764 1.78.2.2 skrll 1765 1.78.2.2 skrll atw_bbp_io_enable(sc, 1); 1766 1.78.2.2 skrll 1767 1.78.2.2 skrll if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1768 1.78.2.2 skrll LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1769 1.78.2.2 skrll goto out; 1770 1.78.2.2 skrll 1771 1.78.2.2 skrll if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1772 1.78.2.2 skrll goto out; 1773 1.78.2.2 skrll 1774 1.78.2.2 skrll if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1775 1.78.2.2 skrll goto out; 1776 1.78.2.2 skrll 1777 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1778 1.78.2.2 skrll 1779 1.78.2.2 skrll if (rc != 0) 1780 1.78.2.2 skrll goto out; 1781 1.78.2.2 skrll 1782 1.78.2.2 skrll rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1783 1.78.2.2 skrll 1784 1.78.2.2 skrll if (rc != 0) 1785 1.78.2.2 skrll goto out; 1786 1.78.2.2 skrll 1787 1.78.2.2 skrll #ifdef ATW_BBPDEBUG 1788 1.78.2.2 skrll atw_rf3000_print(sc); 1789 1.78.2.2 skrll #endif /* ATW_BBPDEBUG */ 1790 1.78.2.2 skrll 1791 1.78.2.2 skrll out: 1792 1.78.2.2 skrll atw_bbp_io_enable(sc, 0); 1793 1.78.2.2 skrll 1794 1.78.2.2 skrll /* set beacon, rts, atim transmit power */ 1795 1.78.2.2 skrll reg = ATW_READ(sc, ATW_PLCPHD); 1796 1.78.2.2 skrll reg &= ~ATW_PLCPHD_SERVICE_MASK; 1797 1.78.2.2 skrll reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1798 1.78.2.2 skrll ATW_PLCPHD_SERVICE_MASK); 1799 1.78.2.2 skrll ATW_WRITE(sc, ATW_PLCPHD, reg); 1800 1.78.2.2 skrll DELAY(atw_plcphd_delay); 1801 1.78.2.2 skrll 1802 1.78.2.2 skrll return rc; 1803 1.78.2.2 skrll } 1804 1.78.2.2 skrll 1805 1.78.2.2 skrll /* Write a register on the RF3000 baseband processor using the 1806 1.78.2.2 skrll * registers provided by the ADM8211 for this purpose. 1807 1.78.2.2 skrll * 1808 1.78.2.2 skrll * Return 0 on success. 1809 1.78.2.2 skrll */ 1810 1.78.2.2 skrll static int 1811 1.78.2.2 skrll atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1812 1.78.2.2 skrll { 1813 1.78.2.2 skrll u_int32_t reg; 1814 1.78.2.2 skrll int i; 1815 1.78.2.2 skrll 1816 1.78.2.2 skrll reg = sc->sc_bbpctl_wr | 1817 1.78.2.2 skrll LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1818 1.78.2.2 skrll LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1819 1.78.2.2 skrll 1820 1.78.2.2 skrll for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1821 1.78.2.2 skrll ATW_WRITE(sc, ATW_BBPCTL, reg); 1822 1.78.2.2 skrll DELAY(2 * atw_pseudo_milli); 1823 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1824 1.78.2.2 skrll break; 1825 1.78.2.2 skrll } 1826 1.78.2.2 skrll 1827 1.78.2.2 skrll if (i < 0) { 1828 1.78.2.2 skrll printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1829 1.78.2.2 skrll return ETIMEDOUT; 1830 1.78.2.2 skrll } 1831 1.78.2.2 skrll return 0; 1832 1.78.2.2 skrll } 1833 1.78.2.2 skrll 1834 1.78.2.2 skrll /* Read a register on the RF3000 baseband processor using the registers 1835 1.78.2.2 skrll * the ADM8211 provides for this purpose. 1836 1.78.2.2 skrll * 1837 1.78.2.2 skrll * The 7-bit register address is addr. Record the 8-bit data in the register 1838 1.78.2.2 skrll * in *val. 1839 1.78.2.2 skrll * 1840 1.78.2.2 skrll * Return 0 on success. 1841 1.78.2.2 skrll * 1842 1.78.2.2 skrll * XXX This does not seem to work. The ADM8211 must require more or 1843 1.78.2.2 skrll * different magic to read the chip than to write it. Possibly some 1844 1.78.2.2 skrll * of the magic I have derived from a binary-only driver concerns 1845 1.78.2.2 skrll * the "chip address" (see the RF3000 manual). 1846 1.78.2.2 skrll */ 1847 1.78.2.2 skrll #ifdef ATW_BBPDEBUG 1848 1.78.2.2 skrll static int 1849 1.78.2.2 skrll atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1850 1.78.2.2 skrll { 1851 1.78.2.2 skrll u_int32_t reg; 1852 1.78.2.2 skrll int i; 1853 1.78.2.2 skrll 1854 1.78.2.2 skrll for (i = 1000; --i >= 0; ) { 1855 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1856 1.78.2.2 skrll break; 1857 1.78.2.2 skrll DELAY(100); 1858 1.78.2.2 skrll } 1859 1.78.2.2 skrll 1860 1.78.2.2 skrll if (i < 0) { 1861 1.78.2.2 skrll printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1862 1.78.2.2 skrll sc->sc_dev.dv_xname); 1863 1.78.2.2 skrll return ETIMEDOUT; 1864 1.78.2.2 skrll } 1865 1.78.2.2 skrll 1866 1.78.2.2 skrll reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1867 1.78.2.2 skrll 1868 1.78.2.2 skrll ATW_WRITE(sc, ATW_BBPCTL, reg); 1869 1.78.2.2 skrll 1870 1.78.2.2 skrll for (i = 1000; --i >= 0; ) { 1871 1.78.2.2 skrll DELAY(100); 1872 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1873 1.78.2.2 skrll break; 1874 1.78.2.2 skrll } 1875 1.78.2.2 skrll 1876 1.78.2.2 skrll ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1877 1.78.2.2 skrll 1878 1.78.2.2 skrll if (i < 0) { 1879 1.78.2.2 skrll printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1880 1.78.2.2 skrll sc->sc_dev.dv_xname, reg); 1881 1.78.2.2 skrll return ETIMEDOUT; 1882 1.78.2.2 skrll } 1883 1.78.2.2 skrll if (val != NULL) 1884 1.78.2.2 skrll *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1885 1.78.2.2 skrll return 0; 1886 1.78.2.2 skrll } 1887 1.78.2.2 skrll #endif /* ATW_BBPDEBUG */ 1888 1.78.2.2 skrll 1889 1.78.2.2 skrll /* Write a register on the Si4126 RF/IF synthesizer using the registers 1890 1.78.2.2 skrll * provided by the ADM8211 for that purpose. 1891 1.78.2.2 skrll * 1892 1.78.2.2 skrll * val is 18 bits of data, and val is the 4-bit address of the register. 1893 1.78.2.2 skrll * 1894 1.78.2.2 skrll * Return 0 on success. 1895 1.78.2.2 skrll */ 1896 1.78.2.2 skrll static void 1897 1.78.2.2 skrll atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1898 1.78.2.2 skrll { 1899 1.78.2.2 skrll uint32_t bits, mask, reg; 1900 1.78.2.2 skrll const int nbits = 22; 1901 1.78.2.2 skrll 1902 1.78.2.2 skrll KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1903 1.78.2.2 skrll KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1904 1.78.2.2 skrll 1905 1.78.2.2 skrll bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1906 1.78.2.2 skrll LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1907 1.78.2.2 skrll 1908 1.78.2.2 skrll reg = ATW_SYNRF_SELSYN; 1909 1.78.2.2 skrll /* reference driver: reset Si4126 serial bus to initial 1910 1.78.2.2 skrll * conditions? 1911 1.78.2.2 skrll */ 1912 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1913 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg); 1914 1.78.2.2 skrll 1915 1.78.2.2 skrll for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1916 1.78.2.2 skrll if ((bits & mask) != 0) 1917 1.78.2.2 skrll reg |= ATW_SYNRF_SYNDATA; 1918 1.78.2.2 skrll else 1919 1.78.2.2 skrll reg &= ~ATW_SYNRF_SYNDATA; 1920 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg); 1921 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1922 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg); 1923 1.78.2.2 skrll } 1924 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1925 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNRF, 0x0); 1926 1.78.2.2 skrll } 1927 1.78.2.2 skrll 1928 1.78.2.2 skrll /* Read 18-bit data from the 4-bit address addr in Si4126 1929 1.78.2.2 skrll * RF synthesizer and write the data to *val. Return 0 on success. 1930 1.78.2.2 skrll * 1931 1.78.2.2 skrll * XXX This does not seem to work. The ADM8211 must require more or 1932 1.78.2.2 skrll * different magic to read the chip than to write it. 1933 1.78.2.2 skrll */ 1934 1.78.2.2 skrll #ifdef ATW_SYNDEBUG 1935 1.78.2.2 skrll static int 1936 1.78.2.2 skrll atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1937 1.78.2.2 skrll { 1938 1.78.2.2 skrll u_int32_t reg; 1939 1.78.2.2 skrll int i; 1940 1.78.2.2 skrll 1941 1.78.2.2 skrll KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1942 1.78.2.2 skrll 1943 1.78.2.2 skrll for (i = 1000; --i >= 0; ) { 1944 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1945 1.78.2.2 skrll break; 1946 1.78.2.2 skrll DELAY(100); 1947 1.78.2.2 skrll } 1948 1.78.2.2 skrll 1949 1.78.2.2 skrll if (i < 0) { 1950 1.78.2.2 skrll printf("%s: start atw_si4126_read, SYNCTL busy\n", 1951 1.78.2.2 skrll sc->sc_dev.dv_xname); 1952 1.78.2.2 skrll return ETIMEDOUT; 1953 1.78.2.2 skrll } 1954 1.78.2.2 skrll 1955 1.78.2.2 skrll reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1956 1.78.2.2 skrll 1957 1.78.2.2 skrll ATW_WRITE(sc, ATW_SYNCTL, reg); 1958 1.78.2.2 skrll 1959 1.78.2.2 skrll for (i = 1000; --i >= 0; ) { 1960 1.78.2.2 skrll DELAY(100); 1961 1.78.2.2 skrll if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1962 1.78.2.2 skrll break; 1963 1.78.2.2 skrll } 1964 1.78.2.2 skrll 1965 1.78.2.2 skrll ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1966 1.78.2.2 skrll 1967 1.78.2.2 skrll if (i < 0) { 1968 1.78.2.2 skrll printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1969 1.78.2.2 skrll sc->sc_dev.dv_xname, reg); 1970 1.78.2.2 skrll return ETIMEDOUT; 1971 1.78.2.2 skrll } 1972 1.78.2.2 skrll if (val != NULL) 1973 1.78.2.2 skrll *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1974 1.78.2.2 skrll ATW_SYNCTL_DATA_MASK); 1975 1.78.2.2 skrll return 0; 1976 1.78.2.2 skrll } 1977 1.78.2.2 skrll #endif /* ATW_SYNDEBUG */ 1978 1.78.2.2 skrll 1979 1.78.2.2 skrll /* XXX is the endianness correct? test. */ 1980 1.78.2.2 skrll #define atw_calchash(addr) \ 1981 1.78.2.2 skrll (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1982 1.78.2.2 skrll 1983 1.78.2.2 skrll /* 1984 1.78.2.2 skrll * atw_filter_setup: 1985 1.78.2.2 skrll * 1986 1.78.2.2 skrll * Set the ADM8211's receive filter. 1987 1.78.2.2 skrll */ 1988 1.78.2.2 skrll static void 1989 1.78.2.2 skrll atw_filter_setup(struct atw_softc *sc) 1990 1.78.2.2 skrll { 1991 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1992 1.78.2.2 skrll struct ethercom *ec = &ic->ic_ec; 1993 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 1994 1.78.2.2 skrll int hash; 1995 1.78.2.2 skrll u_int32_t hashes[2]; 1996 1.78.2.2 skrll struct ether_multi *enm; 1997 1.78.2.2 skrll struct ether_multistep step; 1998 1.78.2.2 skrll 1999 1.78.2.2 skrll /* According to comments in tlp_al981_filter_setup 2000 1.78.2.2 skrll * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2001 1.78.2.2 skrll * multicast filter to be set while it is running. Hopefully 2002 1.78.2.2 skrll * the ADM8211 is not the same! 2003 1.78.2.2 skrll */ 2004 1.78.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) != 0) 2005 1.78.2.2 skrll atw_idle(sc, ATW_NAR_SR); 2006 1.78.2.2 skrll 2007 1.78.2.2 skrll sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2008 1.78.2.2 skrll 2009 1.78.2.2 skrll /* XXX in scan mode, do not filter packets. Maybe this is 2010 1.78.2.2 skrll * unnecessary. 2011 1.78.2.2 skrll */ 2012 1.78.2.2 skrll if (ic->ic_state == IEEE80211_S_SCAN || 2013 1.78.2.2 skrll (ifp->if_flags & IFF_PROMISC) != 0) { 2014 1.78.2.2 skrll sc->sc_opmode |= ATW_NAR_PR; 2015 1.78.2.2 skrll goto allmulti; 2016 1.78.2.2 skrll } 2017 1.78.2.2 skrll 2018 1.78.2.2 skrll hashes[0] = hashes[1] = 0x0; 2019 1.78.2.2 skrll 2020 1.78.2.2 skrll /* 2021 1.78.2.2 skrll * Program the 64-bit multicast hash filter. 2022 1.78.2.2 skrll */ 2023 1.78.2.2 skrll ETHER_FIRST_MULTI(step, ec, enm); 2024 1.78.2.2 skrll while (enm != NULL) { 2025 1.78.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2026 1.78.2.2 skrll ETHER_ADDR_LEN) != 0) 2027 1.78.2.2 skrll goto allmulti; 2028 1.78.2.2 skrll 2029 1.78.2.2 skrll hash = atw_calchash(enm->enm_addrlo); 2030 1.78.2.2 skrll hashes[hash >> 5] |= 1 << (hash & 0x1f); 2031 1.78.2.2 skrll ETHER_NEXT_MULTI(step, enm); 2032 1.78.2.2 skrll sc->sc_opmode |= ATW_NAR_MM; 2033 1.78.2.2 skrll } 2034 1.78.2.2 skrll ifp->if_flags &= ~IFF_ALLMULTI; 2035 1.78.2.2 skrll goto setit; 2036 1.78.2.2 skrll 2037 1.78.2.2 skrll allmulti: 2038 1.78.2.2 skrll sc->sc_opmode |= ATW_NAR_MM; 2039 1.78.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 2040 1.78.2.2 skrll hashes[0] = hashes[1] = 0xffffffff; 2041 1.78.2.2 skrll 2042 1.78.2.2 skrll setit: 2043 1.78.2.2 skrll ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2044 1.78.2.2 skrll ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2045 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2046 1.78.2.2 skrll DELAY(atw_nar_delay); 2047 1.78.2.2 skrll 2048 1.78.2.2 skrll DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2049 1.78.2.2 skrll ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2050 1.78.2.2 skrll } 2051 1.78.2.2 skrll 2052 1.78.2.2 skrll /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2053 1.78.2.2 skrll * a beacon's BSSID and SSID against the preferred BSSID and SSID 2054 1.78.2.2 skrll * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2055 1.78.2.2 skrll * no beacon with the preferred BSSID and SSID in the number of 2056 1.78.2.2 skrll * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2057 1.78.2.2 skrll */ 2058 1.78.2.2 skrll static void 2059 1.78.2.2 skrll atw_write_bssid(struct atw_softc *sc) 2060 1.78.2.2 skrll { 2061 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2062 1.78.2.2 skrll u_int8_t *bssid; 2063 1.78.2.2 skrll 2064 1.78.2.2 skrll bssid = ic->ic_bss->ni_bssid; 2065 1.78.2.2 skrll 2066 1.78.2.2 skrll ATW_WRITE(sc, ATW_BSSID0, 2067 1.78.2.2 skrll LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2068 1.78.2.2 skrll LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2069 1.78.2.2 skrll LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2070 1.78.2.2 skrll LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2071 1.78.2.2 skrll 2072 1.78.2.2 skrll ATW_WRITE(sc, ATW_ABDA1, 2073 1.78.2.2 skrll (ATW_READ(sc, ATW_ABDA1) & 2074 1.78.2.2 skrll ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2075 1.78.2.2 skrll LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2076 1.78.2.2 skrll LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2077 1.78.2.2 skrll 2078 1.78.2.2 skrll DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2079 1.78.2.2 skrll ether_sprintf(sc->sc_bssid))); 2080 1.78.2.2 skrll DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2081 1.78.2.2 skrll 2082 1.78.2.2 skrll memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2083 1.78.2.2 skrll } 2084 1.78.2.2 skrll 2085 1.78.2.2 skrll /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2086 1.78.2.2 skrll * 16-bit word. 2087 1.78.2.2 skrll */ 2088 1.78.2.2 skrll static void 2089 1.78.2.2 skrll atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2090 1.78.2.2 skrll { 2091 1.78.2.2 skrll u_int i; 2092 1.78.2.2 skrll u_int8_t *ptr; 2093 1.78.2.2 skrll 2094 1.78.2.2 skrll memcpy(&sc->sc_sram[ofs], buf, buflen); 2095 1.78.2.2 skrll 2096 1.78.2.2 skrll KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2097 1.78.2.2 skrll 2098 1.78.2.2 skrll KASSERT(buflen + ofs <= sc->sc_sramlen); 2099 1.78.2.2 skrll 2100 1.78.2.2 skrll ptr = &sc->sc_sram[ofs]; 2101 1.78.2.2 skrll 2102 1.78.2.2 skrll for (i = 0; i < buflen; i += 2) { 2103 1.78.2.2 skrll ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2104 1.78.2.2 skrll LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2105 1.78.2.2 skrll DELAY(atw_writewep_delay); 2106 1.78.2.2 skrll 2107 1.78.2.2 skrll ATW_WRITE(sc, ATW_WESK, 2108 1.78.2.2 skrll LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2109 1.78.2.2 skrll DELAY(atw_writewep_delay); 2110 1.78.2.2 skrll } 2111 1.78.2.2 skrll ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2112 1.78.2.2 skrll 2113 1.78.2.2 skrll if (sc->sc_if.if_flags & IFF_DEBUG) { 2114 1.78.2.2 skrll int n_octets = 0; 2115 1.78.2.2 skrll printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2116 1.78.2.2 skrll sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2117 1.78.2.2 skrll for (i = 0; i < buflen; i++) { 2118 1.78.2.2 skrll printf(" %02x", ptr[i]); 2119 1.78.2.2 skrll if (++n_octets % 24 == 0) 2120 1.78.2.2 skrll printf("\n"); 2121 1.78.2.2 skrll } 2122 1.78.2.2 skrll if (n_octets % 24 != 0) 2123 1.78.2.2 skrll printf("\n"); 2124 1.78.2.2 skrll } 2125 1.78.2.2 skrll } 2126 1.78.2.2 skrll 2127 1.78.2.2 skrll /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2128 1.78.2.2 skrll static void 2129 1.78.2.2 skrll atw_write_wep(struct atw_softc *sc) 2130 1.78.2.2 skrll { 2131 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2132 1.78.2.2 skrll /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2133 1.78.2.2 skrll u_int8_t buf[IEEE80211_WEP_NKID] 2134 1.78.2.2 skrll [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2135 1.78.2.2 skrll u_int32_t reg; 2136 1.78.2.2 skrll int i; 2137 1.78.2.2 skrll 2138 1.78.2.2 skrll sc->sc_wepctl = 0; 2139 1.78.2.2 skrll ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2140 1.78.2.2 skrll 2141 1.78.2.2 skrll if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0) 2142 1.78.2.2 skrll return; 2143 1.78.2.2 skrll 2144 1.78.2.2 skrll memset(&buf[0][0], 0, sizeof(buf)); 2145 1.78.2.2 skrll 2146 1.78.2.2 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2147 1.78.2.2 skrll if (ic->ic_nw_keys[i].wk_len > 5) { 2148 1.78.2.2 skrll buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2149 1.78.2.2 skrll } else if (ic->ic_nw_keys[i].wk_len != 0) { 2150 1.78.2.2 skrll buf[i][1] = ATW_WEP_ENABLED; 2151 1.78.2.2 skrll } else { 2152 1.78.2.2 skrll buf[i][1] = 0; 2153 1.78.2.2 skrll continue; 2154 1.78.2.2 skrll } 2155 1.78.2.2 skrll buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2156 1.78.2.2 skrll memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2157 1.78.2.2 skrll ic->ic_nw_keys[i].wk_len - 1); 2158 1.78.2.2 skrll } 2159 1.78.2.2 skrll 2160 1.78.2.2 skrll reg = ATW_READ(sc, ATW_MACTEST); 2161 1.78.2.2 skrll reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2162 1.78.2.2 skrll reg &= ~ATW_MACTEST_KEYID_MASK; 2163 1.78.2.2 skrll reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2164 1.78.2.2 skrll ATW_WRITE(sc, ATW_MACTEST, reg); 2165 1.78.2.2 skrll 2166 1.78.2.2 skrll sc->sc_wepctl = ATW_WEPCTL_WEPENABLE; 2167 1.78.2.2 skrll 2168 1.78.2.2 skrll switch (sc->sc_rev) { 2169 1.78.2.2 skrll case ATW_REVISION_AB: 2170 1.78.2.2 skrll case ATW_REVISION_AF: 2171 1.78.2.2 skrll /* Bypass WEP on Rx. */ 2172 1.78.2.2 skrll sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2173 1.78.2.2 skrll break; 2174 1.78.2.2 skrll default: 2175 1.78.2.2 skrll break; 2176 1.78.2.2 skrll } 2177 1.78.2.2 skrll 2178 1.78.2.2 skrll atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2179 1.78.2.2 skrll sizeof(buf)); 2180 1.78.2.2 skrll } 2181 1.78.2.2 skrll 2182 1.78.2.2 skrll static void 2183 1.78.2.2 skrll atw_change_ibss(struct atw_softc *sc) 2184 1.78.2.2 skrll { 2185 1.78.2.2 skrll atw_predict_beacon(sc); 2186 1.78.2.2 skrll atw_write_bssid(sc); 2187 1.78.2.2 skrll atw_start_beacon(sc, 1); 2188 1.78.2.2 skrll } 2189 1.78.2.2 skrll 2190 1.78.2.2 skrll static void 2191 1.78.2.2 skrll atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2192 1.78.2.2 skrll struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2193 1.78.2.2 skrll { 2194 1.78.2.2 skrll struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2195 1.78.2.2 skrll 2196 1.78.2.2 skrll /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2197 1.78.2.2 skrll if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2198 1.78.2.2 skrll return; 2199 1.78.2.2 skrll 2200 1.78.2.2 skrll (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2201 1.78.2.2 skrll 2202 1.78.2.2 skrll switch (subtype) { 2203 1.78.2.2 skrll case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2204 1.78.2.2 skrll case IEEE80211_FC0_SUBTYPE_BEACON: 2205 1.78.2.2 skrll if (ic->ic_opmode != IEEE80211_M_IBSS || 2206 1.78.2.2 skrll ic->ic_state != IEEE80211_S_RUN) 2207 1.78.2.2 skrll break; 2208 1.78.2.7 skrll if (le64toh(ni->ni_tsf) >= atw_get_tsft(sc) && 2209 1.78.2.7 skrll ieee80211_ibss_merge(ic, ni) == ENETRESET) 2210 1.78.2.2 skrll atw_change_ibss(sc); 2211 1.78.2.2 skrll break; 2212 1.78.2.2 skrll default: 2213 1.78.2.2 skrll break; 2214 1.78.2.2 skrll } 2215 1.78.2.2 skrll return; 2216 1.78.2.2 skrll } 2217 1.78.2.2 skrll 2218 1.78.2.2 skrll /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2219 1.78.2.2 skrll * In ad hoc mode, the SSID is written to the beacons sent by the 2220 1.78.2.2 skrll * ADM8211. In both ad hoc and infrastructure mode, beacons received 2221 1.78.2.2 skrll * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2222 1.78.2.2 skrll * indications. 2223 1.78.2.2 skrll */ 2224 1.78.2.2 skrll static void 2225 1.78.2.2 skrll atw_write_ssid(struct atw_softc *sc) 2226 1.78.2.2 skrll { 2227 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2228 1.78.2.2 skrll /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2229 1.78.2.2 skrll * it only expects the element length, not its ID. 2230 1.78.2.2 skrll */ 2231 1.78.2.2 skrll u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2232 1.78.2.2 skrll 2233 1.78.2.2 skrll memset(buf, 0, sizeof(buf)); 2234 1.78.2.2 skrll buf[0] = ic->ic_bss->ni_esslen; 2235 1.78.2.2 skrll memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2236 1.78.2.2 skrll 2237 1.78.2.2 skrll atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2238 1.78.2.2 skrll roundup(1 + ic->ic_bss->ni_esslen, 2)); 2239 1.78.2.2 skrll } 2240 1.78.2.2 skrll 2241 1.78.2.2 skrll /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2242 1.78.2.2 skrll * In ad hoc mode, the supported rates are written to beacons sent by the 2243 1.78.2.2 skrll * ADM8211. 2244 1.78.2.2 skrll */ 2245 1.78.2.2 skrll static void 2246 1.78.2.2 skrll atw_write_sup_rates(struct atw_softc *sc) 2247 1.78.2.2 skrll { 2248 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2249 1.78.2.2 skrll /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2250 1.78.2.2 skrll * supported rates 2251 1.78.2.2 skrll */ 2252 1.78.2.2 skrll u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2253 1.78.2.2 skrll 2254 1.78.2.2 skrll memset(buf, 0, sizeof(buf)); 2255 1.78.2.2 skrll 2256 1.78.2.2 skrll buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2257 1.78.2.2 skrll 2258 1.78.2.2 skrll memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2259 1.78.2.2 skrll ic->ic_bss->ni_rates.rs_nrates); 2260 1.78.2.2 skrll 2261 1.78.2.2 skrll atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2262 1.78.2.2 skrll } 2263 1.78.2.2 skrll 2264 1.78.2.2 skrll /* Start/stop sending beacons. */ 2265 1.78.2.2 skrll void 2266 1.78.2.2 skrll atw_start_beacon(struct atw_softc *sc, int start) 2267 1.78.2.2 skrll { 2268 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2269 1.78.2.2 skrll uint16_t chan; 2270 1.78.2.2 skrll uint32_t bcnt, bpli, cap0, cap1, capinfo; 2271 1.78.2.2 skrll size_t len; 2272 1.78.2.2 skrll 2273 1.78.2.2 skrll if (ATW_IS_ENABLED(sc) == 0) 2274 1.78.2.2 skrll return; 2275 1.78.2.2 skrll 2276 1.78.2.2 skrll /* start beacons */ 2277 1.78.2.2 skrll len = sizeof(struct ieee80211_frame) + 2278 1.78.2.2 skrll 8 /* timestamp */ + 2 /* beacon interval */ + 2279 1.78.2.2 skrll 2 /* capability info */ + 2280 1.78.2.2 skrll 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2281 1.78.2.2 skrll 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2282 1.78.2.2 skrll 3 /* DS parameters */ + 2283 1.78.2.2 skrll IEEE80211_CRC_LEN; 2284 1.78.2.2 skrll 2285 1.78.2.2 skrll bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2286 1.78.2.2 skrll cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2287 1.78.2.2 skrll cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2288 1.78.2.2 skrll 2289 1.78.2.2 skrll ATW_WRITE(sc, ATW_BCNT, bcnt); 2290 1.78.2.2 skrll ATW_WRITE(sc, ATW_CAP1, cap1); 2291 1.78.2.2 skrll 2292 1.78.2.2 skrll if (!start) 2293 1.78.2.2 skrll return; 2294 1.78.2.2 skrll 2295 1.78.2.2 skrll /* TBD use ni_capinfo */ 2296 1.78.2.2 skrll 2297 1.78.2.2 skrll capinfo = 0; 2298 1.78.2.2 skrll if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2299 1.78.2.2 skrll capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2300 1.78.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) 2301 1.78.2.2 skrll capinfo |= IEEE80211_CAPINFO_PRIVACY; 2302 1.78.2.2 skrll 2303 1.78.2.2 skrll switch (ic->ic_opmode) { 2304 1.78.2.2 skrll case IEEE80211_M_IBSS: 2305 1.78.2.2 skrll len += 4; /* IBSS parameters */ 2306 1.78.2.2 skrll capinfo |= IEEE80211_CAPINFO_IBSS; 2307 1.78.2.2 skrll break; 2308 1.78.2.2 skrll case IEEE80211_M_HOSTAP: 2309 1.78.2.2 skrll /* XXX 6-byte minimum TIM */ 2310 1.78.2.2 skrll len += atw_beacon_len_adjust; 2311 1.78.2.2 skrll capinfo |= IEEE80211_CAPINFO_ESS; 2312 1.78.2.2 skrll break; 2313 1.78.2.2 skrll default: 2314 1.78.2.2 skrll return; 2315 1.78.2.2 skrll } 2316 1.78.2.2 skrll 2317 1.78.2.2 skrll /* set listen interval 2318 1.78.2.2 skrll * XXX do software units agree w/ hardware? 2319 1.78.2.2 skrll */ 2320 1.78.2.2 skrll bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2321 1.78.2.2 skrll LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2322 1.78.2.2 skrll 2323 1.78.2.2 skrll chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2324 1.78.2.2 skrll 2325 1.78.2.2 skrll bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2326 1.78.2.2 skrll cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2327 1.78.2.2 skrll cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2328 1.78.2.2 skrll 2329 1.78.2.2 skrll ATW_WRITE(sc, ATW_BCNT, bcnt); 2330 1.78.2.2 skrll ATW_WRITE(sc, ATW_BPLI, bpli); 2331 1.78.2.2 skrll ATW_WRITE(sc, ATW_CAP0, cap0); 2332 1.78.2.2 skrll ATW_WRITE(sc, ATW_CAP1, cap1); 2333 1.78.2.2 skrll 2334 1.78.2.2 skrll DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2335 1.78.2.2 skrll sc->sc_dev.dv_xname, bcnt)); 2336 1.78.2.2 skrll 2337 1.78.2.2 skrll DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2338 1.78.2.2 skrll sc->sc_dev.dv_xname, cap1)); 2339 1.78.2.2 skrll } 2340 1.78.2.2 skrll 2341 1.78.2.2 skrll /* Return the 32 lsb of the last TSFT divisible by ival. */ 2342 1.78.2.2 skrll static __inline uint32_t 2343 1.78.2.2 skrll atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2344 1.78.2.2 skrll { 2345 1.78.2.2 skrll /* Following the reference driver's lead, I compute 2346 1.78.2.2 skrll * 2347 1.78.2.2 skrll * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2348 1.78.2.2 skrll * 2349 1.78.2.2 skrll * without using 64-bit arithmetic, using the following 2350 1.78.2.2 skrll * relationship: 2351 1.78.2.2 skrll * 2352 1.78.2.2 skrll * (0x100000000 * H + L) % m 2353 1.78.2.2 skrll * = ((0x100000000 % m) * H + L) % m 2354 1.78.2.2 skrll * = (((0xffffffff + 1) % m) * H + L) % m 2355 1.78.2.2 skrll * = ((0xffffffff % m + 1 % m) * H + L) % m 2356 1.78.2.2 skrll * = ((0xffffffff % m + 1) * H + L) % m 2357 1.78.2.2 skrll */ 2358 1.78.2.2 skrll return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2359 1.78.2.2 skrll } 2360 1.78.2.2 skrll 2361 1.78.2.2 skrll static uint64_t 2362 1.78.2.2 skrll atw_get_tsft(struct atw_softc *sc) 2363 1.78.2.2 skrll { 2364 1.78.2.2 skrll int i; 2365 1.78.2.2 skrll uint32_t tsfth, tsftl; 2366 1.78.2.2 skrll for (i = 0; i < 2; i++) { 2367 1.78.2.2 skrll tsfth = ATW_READ(sc, ATW_TSFTH); 2368 1.78.2.2 skrll tsftl = ATW_READ(sc, ATW_TSFTL); 2369 1.78.2.2 skrll if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2370 1.78.2.2 skrll break; 2371 1.78.2.2 skrll } 2372 1.78.2.2 skrll return ((uint64_t)tsfth << 32) | tsftl; 2373 1.78.2.2 skrll } 2374 1.78.2.2 skrll 2375 1.78.2.2 skrll /* If we've created an IBSS, write the TSF time in the ADM8211 to 2376 1.78.2.2 skrll * the ieee80211com. 2377 1.78.2.2 skrll * 2378 1.78.2.2 skrll * Predict the next target beacon transmission time (TBTT) and 2379 1.78.2.2 skrll * write it to the ADM8211. 2380 1.78.2.2 skrll */ 2381 1.78.2.2 skrll static void 2382 1.78.2.2 skrll atw_predict_beacon(struct atw_softc *sc) 2383 1.78.2.2 skrll { 2384 1.78.2.2 skrll #define TBTTOFS 20 /* TU */ 2385 1.78.2.2 skrll 2386 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2387 1.78.2.2 skrll uint64_t tsft; 2388 1.78.2.2 skrll uint32_t ival, past_even, tbtt, tsfth, tsftl; 2389 1.78.2.2 skrll union { 2390 1.78.2.2 skrll uint64_t word; 2391 1.78.2.2 skrll uint8_t tstamp[8]; 2392 1.78.2.2 skrll } u; 2393 1.78.2.2 skrll 2394 1.78.2.2 skrll if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2395 1.78.2.2 skrll ((ic->ic_opmode == IEEE80211_M_IBSS) && 2396 1.78.2.2 skrll (ic->ic_flags & IEEE80211_F_SIBSS))) { 2397 1.78.2.2 skrll tsft = atw_get_tsft(sc); 2398 1.78.2.2 skrll u.word = htole64(tsft); 2399 1.78.2.2 skrll (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u.tstamp[0], 2400 1.78.2.2 skrll sizeof(ic->ic_bss->ni_tstamp)); 2401 1.78.2.2 skrll } else { 2402 1.78.2.2 skrll (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2403 1.78.2.2 skrll tsft = le64toh(u.word); 2404 1.78.2.2 skrll } 2405 1.78.2.2 skrll 2406 1.78.2.2 skrll ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2407 1.78.2.2 skrll 2408 1.78.2.2 skrll tsftl = tsft & 0xFFFFFFFF; 2409 1.78.2.2 skrll tsfth = tsft >> 32; 2410 1.78.2.2 skrll 2411 1.78.2.2 skrll /* We sent/received the last beacon `past' microseconds 2412 1.78.2.2 skrll * after the interval divided the TSF timer. 2413 1.78.2.2 skrll */ 2414 1.78.2.2 skrll past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2415 1.78.2.2 skrll 2416 1.78.2.2 skrll /* Skip ten beacons so that the TBTT cannot pass before 2417 1.78.2.2 skrll * we've programmed it. Ten is an arbitrary number. 2418 1.78.2.2 skrll */ 2419 1.78.2.2 skrll tbtt = past_even + ival * 10; 2420 1.78.2.2 skrll 2421 1.78.2.2 skrll ATW_WRITE(sc, ATW_TOFS1, 2422 1.78.2.2 skrll LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2423 1.78.2.2 skrll LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2424 1.78.2.2 skrll LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2425 1.78.2.2 skrll ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2426 1.78.2.2 skrll #undef TBTTOFS 2427 1.78.2.2 skrll } 2428 1.78.2.2 skrll 2429 1.78.2.2 skrll static void 2430 1.78.2.2 skrll atw_next_scan(void *arg) 2431 1.78.2.2 skrll { 2432 1.78.2.2 skrll struct atw_softc *sc = arg; 2433 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2434 1.78.2.2 skrll int s; 2435 1.78.2.2 skrll 2436 1.78.2.2 skrll /* don't call atw_start w/o network interrupts blocked */ 2437 1.78.2.2 skrll s = splnet(); 2438 1.78.2.2 skrll if (ic->ic_state == IEEE80211_S_SCAN) 2439 1.78.2.2 skrll ieee80211_next_scan(ic); 2440 1.78.2.2 skrll splx(s); 2441 1.78.2.2 skrll } 2442 1.78.2.2 skrll 2443 1.78.2.2 skrll /* Synchronize the hardware state with the software state. */ 2444 1.78.2.2 skrll static int 2445 1.78.2.2 skrll atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2446 1.78.2.2 skrll { 2447 1.78.2.2 skrll struct ifnet *ifp = &ic->ic_if; 2448 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 2449 1.78.2.2 skrll enum ieee80211_state ostate; 2450 1.78.2.2 skrll int error; 2451 1.78.2.2 skrll 2452 1.78.2.2 skrll ostate = ic->ic_state; 2453 1.78.2.2 skrll 2454 1.78.2.2 skrll if (nstate == IEEE80211_S_INIT) { 2455 1.78.2.2 skrll callout_stop(&sc->sc_scan_ch); 2456 1.78.2.2 skrll sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2457 1.78.2.2 skrll atw_start_beacon(sc, 0); 2458 1.78.2.2 skrll return (*sc->sc_newstate)(ic, nstate, arg); 2459 1.78.2.2 skrll } 2460 1.78.2.2 skrll 2461 1.78.2.2 skrll if ((error = atw_tune(sc)) != 0) 2462 1.78.2.2 skrll return error; 2463 1.78.2.2 skrll 2464 1.78.2.2 skrll switch (nstate) { 2465 1.78.2.2 skrll case IEEE80211_S_ASSOC: 2466 1.78.2.2 skrll break; 2467 1.78.2.2 skrll case IEEE80211_S_INIT: 2468 1.78.2.2 skrll panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2469 1.78.2.2 skrll break; 2470 1.78.2.2 skrll case IEEE80211_S_SCAN: 2471 1.78.2.2 skrll callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2472 1.78.2.2 skrll atw_next_scan, sc); 2473 1.78.2.2 skrll 2474 1.78.2.2 skrll break; 2475 1.78.2.2 skrll case IEEE80211_S_RUN: 2476 1.78.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA) 2477 1.78.2.2 skrll break; 2478 1.78.2.2 skrll /*FALLTHROUGH*/ 2479 1.78.2.2 skrll case IEEE80211_S_AUTH: 2480 1.78.2.2 skrll atw_write_bssid(sc); 2481 1.78.2.2 skrll atw_write_ssid(sc); 2482 1.78.2.2 skrll atw_write_sup_rates(sc); 2483 1.78.2.2 skrll 2484 1.78.2.2 skrll if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2485 1.78.2.2 skrll ic->ic_opmode == IEEE80211_M_MONITOR) 2486 1.78.2.2 skrll break; 2487 1.78.2.2 skrll 2488 1.78.2.2 skrll /* set listen interval 2489 1.78.2.2 skrll * XXX do software units agree w/ hardware? 2490 1.78.2.2 skrll */ 2491 1.78.2.2 skrll ATW_WRITE(sc, ATW_BPLI, 2492 1.78.2.2 skrll LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2493 1.78.2.2 skrll LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2494 1.78.2.2 skrll ATW_BPLI_LI_MASK)); 2495 1.78.2.2 skrll 2496 1.78.2.2 skrll DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2497 1.78.2.2 skrll sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2498 1.78.2.2 skrll 2499 1.78.2.2 skrll atw_predict_beacon(sc); 2500 1.78.2.2 skrll break; 2501 1.78.2.2 skrll } 2502 1.78.2.2 skrll 2503 1.78.2.2 skrll if (nstate != IEEE80211_S_SCAN) 2504 1.78.2.2 skrll callout_stop(&sc->sc_scan_ch); 2505 1.78.2.2 skrll 2506 1.78.2.2 skrll if (nstate == IEEE80211_S_RUN && 2507 1.78.2.2 skrll (ic->ic_opmode == IEEE80211_M_HOSTAP || 2508 1.78.2.2 skrll ic->ic_opmode == IEEE80211_M_IBSS)) 2509 1.78.2.2 skrll atw_start_beacon(sc, 1); 2510 1.78.2.2 skrll else 2511 1.78.2.2 skrll atw_start_beacon(sc, 0); 2512 1.78.2.2 skrll 2513 1.78.2.2 skrll error = (*sc->sc_newstate)(ic, nstate, arg); 2514 1.78.2.2 skrll 2515 1.78.2.2 skrll if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2516 1.78.2.2 skrll atw_write_bssid(sc); 2517 1.78.2.2 skrll 2518 1.78.2.2 skrll return error; 2519 1.78.2.2 skrll } 2520 1.78.2.2 skrll 2521 1.78.2.2 skrll /* 2522 1.78.2.2 skrll * atw_add_rxbuf: 2523 1.78.2.2 skrll * 2524 1.78.2.2 skrll * Add a receive buffer to the indicated descriptor. 2525 1.78.2.2 skrll */ 2526 1.78.2.2 skrll int 2527 1.78.2.2 skrll atw_add_rxbuf(struct atw_softc *sc, int idx) 2528 1.78.2.2 skrll { 2529 1.78.2.2 skrll struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2530 1.78.2.2 skrll struct mbuf *m; 2531 1.78.2.2 skrll int error; 2532 1.78.2.2 skrll 2533 1.78.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 2534 1.78.2.2 skrll if (m == NULL) 2535 1.78.2.2 skrll return (ENOBUFS); 2536 1.78.2.2 skrll 2537 1.78.2.2 skrll MCLGET(m, M_DONTWAIT); 2538 1.78.2.2 skrll if ((m->m_flags & M_EXT) == 0) { 2539 1.78.2.2 skrll m_freem(m); 2540 1.78.2.2 skrll return (ENOBUFS); 2541 1.78.2.2 skrll } 2542 1.78.2.2 skrll 2543 1.78.2.2 skrll if (rxs->rxs_mbuf != NULL) 2544 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2545 1.78.2.2 skrll 2546 1.78.2.2 skrll rxs->rxs_mbuf = m; 2547 1.78.2.2 skrll 2548 1.78.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2549 1.78.2.2 skrll m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2550 1.78.2.2 skrll BUS_DMA_READ|BUS_DMA_NOWAIT); 2551 1.78.2.2 skrll if (error) { 2552 1.78.2.2 skrll printf("%s: can't load rx DMA map %d, error = %d\n", 2553 1.78.2.2 skrll sc->sc_dev.dv_xname, idx, error); 2554 1.78.2.2 skrll panic("atw_add_rxbuf"); /* XXX */ 2555 1.78.2.2 skrll } 2556 1.78.2.2 skrll 2557 1.78.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2558 1.78.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2559 1.78.2.2 skrll 2560 1.78.2.2 skrll ATW_INIT_RXDESC(sc, idx); 2561 1.78.2.2 skrll 2562 1.78.2.2 skrll return (0); 2563 1.78.2.2 skrll } 2564 1.78.2.2 skrll 2565 1.78.2.2 skrll /* 2566 1.78.2.2 skrll * Release any queued transmit buffers. 2567 1.78.2.2 skrll */ 2568 1.78.2.2 skrll void 2569 1.78.2.2 skrll atw_txdrain(struct atw_softc *sc) 2570 1.78.2.2 skrll { 2571 1.78.2.2 skrll struct atw_txsoft *txs; 2572 1.78.2.2 skrll 2573 1.78.2.2 skrll while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2574 1.78.2.2 skrll SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2575 1.78.2.2 skrll if (txs->txs_mbuf != NULL) { 2576 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2577 1.78.2.2 skrll m_freem(txs->txs_mbuf); 2578 1.78.2.2 skrll txs->txs_mbuf = NULL; 2579 1.78.2.2 skrll } 2580 1.78.2.2 skrll SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2581 1.78.2.2 skrll } 2582 1.78.2.2 skrll sc->sc_tx_timer = 0; 2583 1.78.2.2 skrll } 2584 1.78.2.2 skrll 2585 1.78.2.2 skrll /* 2586 1.78.2.2 skrll * atw_stop: [ ifnet interface function ] 2587 1.78.2.2 skrll * 2588 1.78.2.2 skrll * Stop transmission on the interface. 2589 1.78.2.2 skrll */ 2590 1.78.2.2 skrll void 2591 1.78.2.2 skrll atw_stop(struct ifnet *ifp, int disable) 2592 1.78.2.2 skrll { 2593 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 2594 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2595 1.78.2.2 skrll 2596 1.78.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2597 1.78.2.2 skrll 2598 1.78.2.2 skrll /* Disable interrupts. */ 2599 1.78.2.2 skrll ATW_WRITE(sc, ATW_IER, 0); 2600 1.78.2.2 skrll 2601 1.78.2.2 skrll /* Stop the transmit and receive processes. */ 2602 1.78.2.2 skrll sc->sc_opmode = 0; 2603 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, 0); 2604 1.78.2.2 skrll DELAY(atw_nar_delay); 2605 1.78.2.2 skrll ATW_WRITE(sc, ATW_TDBD, 0); 2606 1.78.2.2 skrll ATW_WRITE(sc, ATW_TDBP, 0); 2607 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDB, 0); 2608 1.78.2.2 skrll 2609 1.78.2.2 skrll atw_txdrain(sc); 2610 1.78.2.2 skrll 2611 1.78.2.2 skrll if (disable) { 2612 1.78.2.2 skrll atw_rxdrain(sc); 2613 1.78.2.2 skrll atw_disable(sc); 2614 1.78.2.2 skrll } 2615 1.78.2.2 skrll 2616 1.78.2.2 skrll /* 2617 1.78.2.2 skrll * Mark the interface down and cancel the watchdog timer. 2618 1.78.2.2 skrll */ 2619 1.78.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2620 1.78.2.2 skrll ifp->if_timer = 0; 2621 1.78.2.2 skrll 2622 1.78.2.2 skrll if (!disable) 2623 1.78.2.2 skrll atw_reset(sc); 2624 1.78.2.2 skrll } 2625 1.78.2.2 skrll 2626 1.78.2.2 skrll /* 2627 1.78.2.2 skrll * atw_rxdrain: 2628 1.78.2.2 skrll * 2629 1.78.2.2 skrll * Drain the receive queue. 2630 1.78.2.2 skrll */ 2631 1.78.2.2 skrll void 2632 1.78.2.2 skrll atw_rxdrain(struct atw_softc *sc) 2633 1.78.2.2 skrll { 2634 1.78.2.2 skrll struct atw_rxsoft *rxs; 2635 1.78.2.2 skrll int i; 2636 1.78.2.2 skrll 2637 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 2638 1.78.2.2 skrll rxs = &sc->sc_rxsoft[i]; 2639 1.78.2.2 skrll if (rxs->rxs_mbuf == NULL) 2640 1.78.2.2 skrll continue; 2641 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2642 1.78.2.2 skrll m_freem(rxs->rxs_mbuf); 2643 1.78.2.2 skrll rxs->rxs_mbuf = NULL; 2644 1.78.2.2 skrll } 2645 1.78.2.2 skrll } 2646 1.78.2.2 skrll 2647 1.78.2.2 skrll /* 2648 1.78.2.2 skrll * atw_detach: 2649 1.78.2.2 skrll * 2650 1.78.2.2 skrll * Detach an ADM8211 interface. 2651 1.78.2.2 skrll */ 2652 1.78.2.2 skrll int 2653 1.78.2.2 skrll atw_detach(struct atw_softc *sc) 2654 1.78.2.2 skrll { 2655 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 2656 1.78.2.2 skrll struct atw_rxsoft *rxs; 2657 1.78.2.2 skrll struct atw_txsoft *txs; 2658 1.78.2.2 skrll int i; 2659 1.78.2.2 skrll 2660 1.78.2.2 skrll /* 2661 1.78.2.2 skrll * Succeed now if there isn't any work to do. 2662 1.78.2.2 skrll */ 2663 1.78.2.2 skrll if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2664 1.78.2.2 skrll return (0); 2665 1.78.2.2 skrll 2666 1.78.2.2 skrll callout_stop(&sc->sc_scan_ch); 2667 1.78.2.2 skrll 2668 1.78.2.2 skrll ieee80211_ifdetach(ifp); 2669 1.78.2.2 skrll if_detach(ifp); 2670 1.78.2.2 skrll 2671 1.78.2.2 skrll for (i = 0; i < ATW_NRXDESC; i++) { 2672 1.78.2.2 skrll rxs = &sc->sc_rxsoft[i]; 2673 1.78.2.2 skrll if (rxs->rxs_mbuf != NULL) { 2674 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2675 1.78.2.2 skrll m_freem(rxs->rxs_mbuf); 2676 1.78.2.2 skrll rxs->rxs_mbuf = NULL; 2677 1.78.2.2 skrll } 2678 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2679 1.78.2.2 skrll } 2680 1.78.2.2 skrll for (i = 0; i < ATW_TXQUEUELEN; i++) { 2681 1.78.2.2 skrll txs = &sc->sc_txsoft[i]; 2682 1.78.2.2 skrll if (txs->txs_mbuf != NULL) { 2683 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2684 1.78.2.2 skrll m_freem(txs->txs_mbuf); 2685 1.78.2.2 skrll txs->txs_mbuf = NULL; 2686 1.78.2.2 skrll } 2687 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2688 1.78.2.2 skrll } 2689 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2690 1.78.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2691 1.78.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2692 1.78.2.2 skrll sizeof(struct atw_control_data)); 2693 1.78.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2694 1.78.2.2 skrll 2695 1.78.2.2 skrll shutdownhook_disestablish(sc->sc_sdhook); 2696 1.78.2.2 skrll powerhook_disestablish(sc->sc_powerhook); 2697 1.78.2.2 skrll 2698 1.78.2.2 skrll if (sc->sc_srom) 2699 1.78.2.2 skrll free(sc->sc_srom, M_DEVBUF); 2700 1.78.2.2 skrll 2701 1.78.2.2 skrll return (0); 2702 1.78.2.2 skrll } 2703 1.78.2.2 skrll 2704 1.78.2.2 skrll /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2705 1.78.2.2 skrll void 2706 1.78.2.2 skrll atw_shutdown(void *arg) 2707 1.78.2.2 skrll { 2708 1.78.2.2 skrll struct atw_softc *sc = arg; 2709 1.78.2.2 skrll 2710 1.78.2.2 skrll atw_stop(&sc->sc_ic.ic_if, 1); 2711 1.78.2.2 skrll } 2712 1.78.2.2 skrll 2713 1.78.2.2 skrll int 2714 1.78.2.2 skrll atw_intr(void *arg) 2715 1.78.2.2 skrll { 2716 1.78.2.2 skrll struct atw_softc *sc = arg; 2717 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 2718 1.78.2.2 skrll u_int32_t status, rxstatus, txstatus, linkstatus; 2719 1.78.2.2 skrll int handled = 0, txthresh; 2720 1.78.2.2 skrll 2721 1.78.2.2 skrll #ifdef DEBUG 2722 1.78.2.2 skrll if (ATW_IS_ENABLED(sc) == 0) 2723 1.78.2.2 skrll panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2724 1.78.2.2 skrll #endif 2725 1.78.2.2 skrll 2726 1.78.2.2 skrll /* 2727 1.78.2.2 skrll * If the interface isn't running, the interrupt couldn't 2728 1.78.2.2 skrll * possibly have come from us. 2729 1.78.2.2 skrll */ 2730 1.78.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0 || 2731 1.78.2.2 skrll (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2732 1.78.2.2 skrll return (0); 2733 1.78.2.2 skrll 2734 1.78.2.2 skrll for (;;) { 2735 1.78.2.2 skrll status = ATW_READ(sc, ATW_STSR); 2736 1.78.2.2 skrll 2737 1.78.2.2 skrll if (status) 2738 1.78.2.2 skrll ATW_WRITE(sc, ATW_STSR, status); 2739 1.78.2.2 skrll 2740 1.78.2.2 skrll #ifdef ATW_DEBUG 2741 1.78.2.2 skrll #define PRINTINTR(flag) do { \ 2742 1.78.2.2 skrll if ((status & flag) != 0) { \ 2743 1.78.2.2 skrll printf("%s" #flag, delim); \ 2744 1.78.2.2 skrll delim = ","; \ 2745 1.78.2.2 skrll } \ 2746 1.78.2.2 skrll } while (0) 2747 1.78.2.2 skrll 2748 1.78.2.2 skrll if (atw_debug > 1 && status) { 2749 1.78.2.2 skrll const char *delim = "<"; 2750 1.78.2.2 skrll 2751 1.78.2.2 skrll printf("%s: reg[STSR] = %x", 2752 1.78.2.2 skrll sc->sc_dev.dv_xname, status); 2753 1.78.2.2 skrll 2754 1.78.2.2 skrll PRINTINTR(ATW_INTR_FBE); 2755 1.78.2.2 skrll PRINTINTR(ATW_INTR_LINKOFF); 2756 1.78.2.2 skrll PRINTINTR(ATW_INTR_LINKON); 2757 1.78.2.2 skrll PRINTINTR(ATW_INTR_RCI); 2758 1.78.2.2 skrll PRINTINTR(ATW_INTR_RDU); 2759 1.78.2.2 skrll PRINTINTR(ATW_INTR_REIS); 2760 1.78.2.2 skrll PRINTINTR(ATW_INTR_RPS); 2761 1.78.2.2 skrll PRINTINTR(ATW_INTR_TCI); 2762 1.78.2.2 skrll PRINTINTR(ATW_INTR_TDU); 2763 1.78.2.2 skrll PRINTINTR(ATW_INTR_TLT); 2764 1.78.2.2 skrll PRINTINTR(ATW_INTR_TPS); 2765 1.78.2.2 skrll PRINTINTR(ATW_INTR_TRT); 2766 1.78.2.2 skrll PRINTINTR(ATW_INTR_TUF); 2767 1.78.2.2 skrll PRINTINTR(ATW_INTR_BCNTC); 2768 1.78.2.2 skrll PRINTINTR(ATW_INTR_ATIME); 2769 1.78.2.2 skrll PRINTINTR(ATW_INTR_TBTT); 2770 1.78.2.2 skrll PRINTINTR(ATW_INTR_TSCZ); 2771 1.78.2.2 skrll PRINTINTR(ATW_INTR_TSFTF); 2772 1.78.2.2 skrll printf(">\n"); 2773 1.78.2.2 skrll } 2774 1.78.2.2 skrll #undef PRINTINTR 2775 1.78.2.2 skrll #endif /* ATW_DEBUG */ 2776 1.78.2.2 skrll 2777 1.78.2.2 skrll if ((status & sc->sc_inten) == 0) 2778 1.78.2.2 skrll break; 2779 1.78.2.2 skrll 2780 1.78.2.2 skrll handled = 1; 2781 1.78.2.2 skrll 2782 1.78.2.2 skrll rxstatus = status & sc->sc_rxint_mask; 2783 1.78.2.2 skrll txstatus = status & sc->sc_txint_mask; 2784 1.78.2.2 skrll linkstatus = status & sc->sc_linkint_mask; 2785 1.78.2.2 skrll 2786 1.78.2.2 skrll if (linkstatus) { 2787 1.78.2.2 skrll atw_linkintr(sc, linkstatus); 2788 1.78.2.2 skrll } 2789 1.78.2.2 skrll 2790 1.78.2.2 skrll if (rxstatus) { 2791 1.78.2.2 skrll /* Grab any new packets. */ 2792 1.78.2.2 skrll atw_rxintr(sc); 2793 1.78.2.2 skrll 2794 1.78.2.2 skrll if (rxstatus & ATW_INTR_RDU) { 2795 1.78.2.2 skrll printf("%s: receive ring overrun\n", 2796 1.78.2.2 skrll sc->sc_dev.dv_xname); 2797 1.78.2.2 skrll /* Get the receive process going again. */ 2798 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDR, 0x1); 2799 1.78.2.2 skrll break; 2800 1.78.2.2 skrll } 2801 1.78.2.2 skrll } 2802 1.78.2.2 skrll 2803 1.78.2.2 skrll if (txstatus) { 2804 1.78.2.2 skrll /* Sweep up transmit descriptors. */ 2805 1.78.2.2 skrll atw_txintr(sc); 2806 1.78.2.2 skrll 2807 1.78.2.2 skrll if (txstatus & ATW_INTR_TLT) 2808 1.78.2.2 skrll DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2809 1.78.2.2 skrll sc->sc_dev.dv_xname)); 2810 1.78.2.2 skrll 2811 1.78.2.2 skrll if (txstatus & ATW_INTR_TRT) 2812 1.78.2.2 skrll DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2813 1.78.2.2 skrll sc->sc_dev.dv_xname)); 2814 1.78.2.2 skrll 2815 1.78.2.2 skrll /* If Tx under-run, increase our transmit threshold 2816 1.78.2.2 skrll * if another is available. 2817 1.78.2.2 skrll */ 2818 1.78.2.2 skrll txthresh = sc->sc_txthresh + 1; 2819 1.78.2.2 skrll if ((txstatus & ATW_INTR_TUF) && 2820 1.78.2.2 skrll sc->sc_txth[txthresh].txth_name != NULL) { 2821 1.78.2.2 skrll /* Idle the transmit process. */ 2822 1.78.2.2 skrll atw_idle(sc, ATW_NAR_ST); 2823 1.78.2.2 skrll 2824 1.78.2.2 skrll sc->sc_txthresh = txthresh; 2825 1.78.2.2 skrll sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2826 1.78.2.2 skrll sc->sc_opmode |= 2827 1.78.2.2 skrll sc->sc_txth[txthresh].txth_opmode; 2828 1.78.2.2 skrll printf("%s: transmit underrun; new " 2829 1.78.2.2 skrll "threshold: %s\n", sc->sc_dev.dv_xname, 2830 1.78.2.2 skrll sc->sc_txth[txthresh].txth_name); 2831 1.78.2.2 skrll 2832 1.78.2.2 skrll /* Set the new threshold and restart 2833 1.78.2.2 skrll * the transmit process. 2834 1.78.2.2 skrll */ 2835 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2836 1.78.2.2 skrll DELAY(atw_nar_delay); 2837 1.78.2.2 skrll ATW_WRITE(sc, ATW_RDR, 0x1); 2838 1.78.2.2 skrll /* XXX Log every Nth underrun from 2839 1.78.2.2 skrll * XXX now on? 2840 1.78.2.2 skrll */ 2841 1.78.2.2 skrll } 2842 1.78.2.2 skrll } 2843 1.78.2.2 skrll 2844 1.78.2.2 skrll if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2845 1.78.2.2 skrll if (status & ATW_INTR_TPS) 2846 1.78.2.2 skrll printf("%s: transmit process stopped\n", 2847 1.78.2.2 skrll sc->sc_dev.dv_xname); 2848 1.78.2.2 skrll if (status & ATW_INTR_RPS) 2849 1.78.2.2 skrll printf("%s: receive process stopped\n", 2850 1.78.2.2 skrll sc->sc_dev.dv_xname); 2851 1.78.2.2 skrll (void)atw_init(ifp); 2852 1.78.2.2 skrll break; 2853 1.78.2.2 skrll } 2854 1.78.2.2 skrll 2855 1.78.2.2 skrll if (status & ATW_INTR_FBE) { 2856 1.78.2.2 skrll printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2857 1.78.2.2 skrll (void)atw_init(ifp); 2858 1.78.2.2 skrll break; 2859 1.78.2.2 skrll } 2860 1.78.2.2 skrll 2861 1.78.2.2 skrll /* 2862 1.78.2.2 skrll * Not handled: 2863 1.78.2.2 skrll * 2864 1.78.2.2 skrll * Transmit buffer unavailable -- normal 2865 1.78.2.2 skrll * condition, nothing to do, really. 2866 1.78.2.2 skrll * 2867 1.78.2.2 skrll * Early receive interrupt -- not available on 2868 1.78.2.2 skrll * all chips, we just use RI. We also only 2869 1.78.2.2 skrll * use single-segment receive DMA, so this 2870 1.78.2.2 skrll * is mostly useless. 2871 1.78.2.2 skrll * 2872 1.78.2.2 skrll * TBD others 2873 1.78.2.2 skrll */ 2874 1.78.2.2 skrll } 2875 1.78.2.2 skrll 2876 1.78.2.2 skrll /* Try to get more packets going. */ 2877 1.78.2.2 skrll atw_start(ifp); 2878 1.78.2.2 skrll 2879 1.78.2.2 skrll return (handled); 2880 1.78.2.2 skrll } 2881 1.78.2.2 skrll 2882 1.78.2.2 skrll /* 2883 1.78.2.2 skrll * atw_idle: 2884 1.78.2.2 skrll * 2885 1.78.2.2 skrll * Cause the transmit and/or receive processes to go idle. 2886 1.78.2.2 skrll * 2887 1.78.2.2 skrll * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2888 1.78.2.2 skrll * process in STSR if I clear SR or ST after the process has already 2889 1.78.2.2 skrll * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2890 1.78.2.2 skrll * do not seem to be too reliable. Perhaps I have the sense of the 2891 1.78.2.2 skrll * Rx bits switched with the Tx bits? 2892 1.78.2.2 skrll */ 2893 1.78.2.2 skrll void 2894 1.78.2.2 skrll atw_idle(struct atw_softc *sc, u_int32_t bits) 2895 1.78.2.2 skrll { 2896 1.78.2.2 skrll u_int32_t ackmask = 0, opmode, stsr, test0; 2897 1.78.2.2 skrll int i, s; 2898 1.78.2.2 skrll 2899 1.78.2.2 skrll s = splnet(); 2900 1.78.2.2 skrll 2901 1.78.2.2 skrll opmode = sc->sc_opmode & ~bits; 2902 1.78.2.2 skrll 2903 1.78.2.2 skrll if (bits & ATW_NAR_SR) 2904 1.78.2.2 skrll ackmask |= ATW_INTR_RPS; 2905 1.78.2.2 skrll 2906 1.78.2.2 skrll if (bits & ATW_NAR_ST) { 2907 1.78.2.2 skrll ackmask |= ATW_INTR_TPS; 2908 1.78.2.2 skrll /* set ATW_NAR_HF to flush TX FIFO. */ 2909 1.78.2.2 skrll opmode |= ATW_NAR_HF; 2910 1.78.2.2 skrll } 2911 1.78.2.2 skrll 2912 1.78.2.2 skrll ATW_WRITE(sc, ATW_NAR, opmode); 2913 1.78.2.2 skrll DELAY(atw_nar_delay); 2914 1.78.2.2 skrll 2915 1.78.2.2 skrll for (i = 0; i < 1000; i++) { 2916 1.78.2.2 skrll stsr = ATW_READ(sc, ATW_STSR); 2917 1.78.2.2 skrll if ((stsr & ackmask) == ackmask) 2918 1.78.2.2 skrll break; 2919 1.78.2.2 skrll DELAY(10); 2920 1.78.2.2 skrll } 2921 1.78.2.2 skrll 2922 1.78.2.2 skrll ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2923 1.78.2.2 skrll 2924 1.78.2.2 skrll if ((stsr & ackmask) == ackmask) 2925 1.78.2.2 skrll goto out; 2926 1.78.2.2 skrll 2927 1.78.2.2 skrll test0 = ATW_READ(sc, ATW_TEST0); 2928 1.78.2.2 skrll 2929 1.78.2.2 skrll if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2930 1.78.2.2 skrll (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2931 1.78.2.2 skrll printf("%s: transmit process not idle [%s]\n", 2932 1.78.2.2 skrll sc->sc_dev.dv_xname, 2933 1.78.2.2 skrll atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2934 1.78.2.2 skrll printf("%s: bits %08x test0 %08x stsr %08x\n", 2935 1.78.2.2 skrll sc->sc_dev.dv_xname, bits, test0, stsr); 2936 1.78.2.2 skrll } 2937 1.78.2.2 skrll 2938 1.78.2.2 skrll if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2939 1.78.2.2 skrll (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2940 1.78.2.2 skrll DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2941 1.78.2.2 skrll sc->sc_dev.dv_xname, 2942 1.78.2.2 skrll atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2943 1.78.2.2 skrll DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2944 1.78.2.2 skrll sc->sc_dev.dv_xname, bits, test0, stsr)); 2945 1.78.2.2 skrll } 2946 1.78.2.2 skrll out: 2947 1.78.2.2 skrll if ((bits & ATW_NAR_ST) != 0) 2948 1.78.2.2 skrll atw_txdrain(sc); 2949 1.78.2.2 skrll splx(s); 2950 1.78.2.2 skrll return; 2951 1.78.2.2 skrll } 2952 1.78.2.2 skrll 2953 1.78.2.2 skrll /* 2954 1.78.2.2 skrll * atw_linkintr: 2955 1.78.2.2 skrll * 2956 1.78.2.2 skrll * Helper; handle link-status interrupts. 2957 1.78.2.2 skrll */ 2958 1.78.2.2 skrll void 2959 1.78.2.2 skrll atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2960 1.78.2.2 skrll { 2961 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2962 1.78.2.2 skrll 2963 1.78.2.2 skrll if (ic->ic_state != IEEE80211_S_RUN) 2964 1.78.2.2 skrll return; 2965 1.78.2.2 skrll 2966 1.78.2.2 skrll if (linkstatus & ATW_INTR_LINKON) { 2967 1.78.2.2 skrll DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2968 1.78.2.2 skrll sc->sc_rescan_timer = 0; 2969 1.78.2.2 skrll } else if (linkstatus & ATW_INTR_LINKOFF) { 2970 1.78.2.2 skrll DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2971 1.78.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) 2972 1.78.2.2 skrll return; 2973 1.78.2.2 skrll sc->sc_rescan_timer = 3; 2974 1.78.2.2 skrll ic->ic_if.if_timer = 1; 2975 1.78.2.2 skrll } 2976 1.78.2.2 skrll } 2977 1.78.2.2 skrll 2978 1.78.2.2 skrll static __inline int 2979 1.78.2.2 skrll atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame *wh) 2980 1.78.2.2 skrll { 2981 1.78.2.2 skrll if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 2982 1.78.2.2 skrll return 0; 2983 1.78.2.2 skrll if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 2984 1.78.2.2 skrll return 0; 2985 1.78.2.2 skrll return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 2986 1.78.2.2 skrll } 2987 1.78.2.2 skrll 2988 1.78.2.2 skrll /* 2989 1.78.2.2 skrll * atw_rxintr: 2990 1.78.2.2 skrll * 2991 1.78.2.2 skrll * Helper; handle receive interrupts. 2992 1.78.2.2 skrll */ 2993 1.78.2.2 skrll void 2994 1.78.2.2 skrll atw_rxintr(struct atw_softc *sc) 2995 1.78.2.2 skrll { 2996 1.78.2.2 skrll static int rate_tbl[] = {2, 4, 11, 22, 44}; 2997 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2998 1.78.2.2 skrll struct ieee80211_node *ni; 2999 1.78.2.2 skrll struct ieee80211_frame *wh; 3000 1.78.2.2 skrll struct ifnet *ifp = &ic->ic_if; 3001 1.78.2.2 skrll struct atw_rxsoft *rxs; 3002 1.78.2.2 skrll struct mbuf *m; 3003 1.78.2.2 skrll u_int32_t rxstat; 3004 1.78.2.2 skrll int i, len, rate, rate0; 3005 1.78.2.2 skrll u_int32_t rssi, rssi0; 3006 1.78.2.2 skrll 3007 1.78.2.2 skrll for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3008 1.78.2.2 skrll rxs = &sc->sc_rxsoft[i]; 3009 1.78.2.2 skrll 3010 1.78.2.2 skrll ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3011 1.78.2.2 skrll 3012 1.78.2.2 skrll rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3013 1.78.2.2 skrll rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3014 1.78.2.2 skrll rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3015 1.78.2.2 skrll 3016 1.78.2.2 skrll if (rxstat & ATW_RXSTAT_OWN) 3017 1.78.2.2 skrll break; /* We have processed all receive buffers. */ 3018 1.78.2.2 skrll 3019 1.78.2.2 skrll DPRINTF3(sc, 3020 1.78.2.2 skrll ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3021 1.78.2.2 skrll sc->sc_dev.dv_xname, 3022 1.78.2.2 skrll rxstat, rssi0, 3023 1.78.2.2 skrll le32toh(sc->sc_rxdescs[i].ar_buf1), 3024 1.78.2.2 skrll le32toh(sc->sc_rxdescs[i].ar_buf2))); 3025 1.78.2.2 skrll 3026 1.78.2.2 skrll /* 3027 1.78.2.2 skrll * Make sure the packet fits in one buffer. This should 3028 1.78.2.2 skrll * always be the case. 3029 1.78.2.2 skrll */ 3030 1.78.2.2 skrll if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3031 1.78.2.2 skrll (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3032 1.78.2.2 skrll printf("%s: incoming packet spilled, resetting\n", 3033 1.78.2.2 skrll sc->sc_dev.dv_xname); 3034 1.78.2.2 skrll (void)atw_init(ifp); 3035 1.78.2.2 skrll return; 3036 1.78.2.2 skrll } 3037 1.78.2.2 skrll 3038 1.78.2.2 skrll /* 3039 1.78.2.2 skrll * If an error occurred, update stats, clear the status 3040 1.78.2.2 skrll * word, and leave the packet buffer in place. It will 3041 1.78.2.2 skrll * simply be reused the next time the ring comes around. 3042 1.78.2.2 skrll * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3043 1.78.2.2 skrll * error. 3044 1.78.2.2 skrll */ 3045 1.78.2.2 skrll 3046 1.78.2.2 skrll if ((rxstat & ATW_RXSTAT_ES) != 0 && 3047 1.78.2.2 skrll ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3048 1.78.2.2 skrll (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3049 1.78.2.2 skrll ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3050 1.78.2.2 skrll ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3051 1.78.2.2 skrll ATW_RXSTAT_ICVE)) != 0)) { 3052 1.78.2.2 skrll #define PRINTERR(bit, str) \ 3053 1.78.2.2 skrll if (rxstat & (bit)) \ 3054 1.78.2.2 skrll printf("%s: receive error: %s\n", \ 3055 1.78.2.2 skrll sc->sc_dev.dv_xname, str) 3056 1.78.2.2 skrll ifp->if_ierrors++; 3057 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3058 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3059 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3060 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3061 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3062 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3063 1.78.2.2 skrll PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3064 1.78.2.2 skrll #undef PRINTERR 3065 1.78.2.2 skrll ATW_INIT_RXDESC(sc, i); 3066 1.78.2.2 skrll continue; 3067 1.78.2.2 skrll } 3068 1.78.2.2 skrll 3069 1.78.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3070 1.78.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3071 1.78.2.2 skrll 3072 1.78.2.2 skrll /* 3073 1.78.2.2 skrll * No errors; receive the packet. Note the ADM8211 3074 1.78.2.2 skrll * includes the CRC in promiscuous mode. 3075 1.78.2.2 skrll */ 3076 1.78.2.2 skrll len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3077 1.78.2.2 skrll 3078 1.78.2.2 skrll /* 3079 1.78.2.2 skrll * Allocate a new mbuf cluster. If that fails, we are 3080 1.78.2.2 skrll * out of memory, and must drop the packet and recycle 3081 1.78.2.2 skrll * the buffer that's already attached to this descriptor. 3082 1.78.2.2 skrll */ 3083 1.78.2.2 skrll m = rxs->rxs_mbuf; 3084 1.78.2.2 skrll if (atw_add_rxbuf(sc, i) != 0) { 3085 1.78.2.2 skrll ifp->if_ierrors++; 3086 1.78.2.2 skrll ATW_INIT_RXDESC(sc, i); 3087 1.78.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3088 1.78.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3089 1.78.2.2 skrll continue; 3090 1.78.2.2 skrll } 3091 1.78.2.2 skrll 3092 1.78.2.2 skrll ifp->if_ipackets++; 3093 1.78.2.2 skrll if (sc->sc_opmode & ATW_NAR_PR) 3094 1.78.2.8 skrll len -= IEEE80211_CRC_LEN; 3095 1.78.2.2 skrll m->m_pkthdr.rcvif = ifp; 3096 1.78.2.2 skrll m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3097 1.78.2.2 skrll 3098 1.78.2.2 skrll if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3099 1.78.2.2 skrll rate = 0; 3100 1.78.2.2 skrll else 3101 1.78.2.2 skrll rate = rate_tbl[rate0]; 3102 1.78.2.2 skrll 3103 1.78.2.2 skrll /* The RSSI comes straight from a register in the 3104 1.78.2.2 skrll * baseband processor. I know that for the RF3000, 3105 1.78.2.2 skrll * the RSSI register also contains the antenna-selection 3106 1.78.2.2 skrll * bits. Mask those off. 3107 1.78.2.2 skrll * 3108 1.78.2.2 skrll * TBD Treat other basebands. 3109 1.78.2.2 skrll */ 3110 1.78.2.2 skrll if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3111 1.78.2.2 skrll rssi = rssi0 & RF3000_RSSI_MASK; 3112 1.78.2.2 skrll else 3113 1.78.2.2 skrll rssi = rssi0; 3114 1.78.2.2 skrll 3115 1.78.2.2 skrll #if NBPFILTER > 0 3116 1.78.2.2 skrll /* Pass this up to any BPF listeners. */ 3117 1.78.2.2 skrll if (sc->sc_radiobpf != NULL) { 3118 1.78.2.2 skrll struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3119 1.78.2.2 skrll 3120 1.78.2.2 skrll tap->ar_rate = rate; 3121 1.78.2.2 skrll tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3122 1.78.2.2 skrll tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3123 1.78.2.2 skrll 3124 1.78.2.2 skrll /* TBD verify units are dB */ 3125 1.78.2.2 skrll tap->ar_antsignal = (int)rssi; 3126 1.78.2.2 skrll /* TBD tap->ar_flags */ 3127 1.78.2.2 skrll 3128 1.78.2.2 skrll bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3129 1.78.2.2 skrll tap->ar_ihdr.it_len, m); 3130 1.78.2.2 skrll } 3131 1.78.2.2 skrll #endif /* NPBFILTER > 0 */ 3132 1.78.2.2 skrll 3133 1.78.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 3134 1.78.2.2 skrll ni = ieee80211_find_rxnode(ic, wh); 3135 1.78.2.2 skrll if (atw_hw_decrypted(sc, wh)) 3136 1.78.2.2 skrll wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3137 1.78.2.2 skrll ieee80211_input(ifp, m, ni, (int)rssi, 0); 3138 1.78.2.2 skrll /* 3139 1.78.2.2 skrll * The frame may have caused the node to be marked for 3140 1.78.2.2 skrll * reclamation (e.g. in response to a DEAUTH message) 3141 1.78.2.3 skrll * so use release_node here instead of unref_node. 3142 1.78.2.2 skrll */ 3143 1.78.2.3 skrll ieee80211_release_node(ic, ni); 3144 1.78.2.2 skrll } 3145 1.78.2.2 skrll 3146 1.78.2.2 skrll /* Update the receive pointer. */ 3147 1.78.2.2 skrll sc->sc_rxptr = i; 3148 1.78.2.2 skrll } 3149 1.78.2.2 skrll 3150 1.78.2.2 skrll /* 3151 1.78.2.2 skrll * atw_txintr: 3152 1.78.2.2 skrll * 3153 1.78.2.2 skrll * Helper; handle transmit interrupts. 3154 1.78.2.2 skrll */ 3155 1.78.2.2 skrll void 3156 1.78.2.2 skrll atw_txintr(struct atw_softc *sc) 3157 1.78.2.2 skrll { 3158 1.78.2.2 skrll #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3159 1.78.2.2 skrll ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3160 1.78.2.2 skrll #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3161 1.78.2.2 skrll "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3162 1.78.2.2 skrll 3163 1.78.2.2 skrll static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3164 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 3165 1.78.2.2 skrll struct atw_txsoft *txs; 3166 1.78.2.2 skrll u_int32_t txstat; 3167 1.78.2.2 skrll 3168 1.78.2.2 skrll DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3169 1.78.2.2 skrll sc->sc_dev.dv_xname, sc->sc_flags)); 3170 1.78.2.2 skrll 3171 1.78.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 3172 1.78.2.2 skrll 3173 1.78.2.2 skrll /* 3174 1.78.2.2 skrll * Go through our Tx list and free mbufs for those 3175 1.78.2.2 skrll * frames that have been transmitted. 3176 1.78.2.2 skrll */ 3177 1.78.2.2 skrll while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3178 1.78.2.2 skrll ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3179 1.78.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3180 1.78.2.2 skrll 3181 1.78.2.2 skrll #ifdef ATW_DEBUG 3182 1.78.2.2 skrll if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3183 1.78.2.2 skrll int i; 3184 1.78.2.2 skrll printf(" txsoft %p transmit chain:\n", txs); 3185 1.78.2.2 skrll ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3186 1.78.2.2 skrll txs->txs_ndescs - 1, 3187 1.78.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3188 1.78.2.2 skrll for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3189 1.78.2.2 skrll printf(" descriptor %d:\n", i); 3190 1.78.2.2 skrll printf(" at_status: 0x%08x\n", 3191 1.78.2.2 skrll le32toh(sc->sc_txdescs[i].at_stat)); 3192 1.78.2.2 skrll printf(" at_flags: 0x%08x\n", 3193 1.78.2.2 skrll le32toh(sc->sc_txdescs[i].at_flags)); 3194 1.78.2.2 skrll printf(" at_buf1: 0x%08x\n", 3195 1.78.2.2 skrll le32toh(sc->sc_txdescs[i].at_buf1)); 3196 1.78.2.2 skrll printf(" at_buf2: 0x%08x\n", 3197 1.78.2.2 skrll le32toh(sc->sc_txdescs[i].at_buf2)); 3198 1.78.2.2 skrll if (i == txs->txs_lastdesc) 3199 1.78.2.2 skrll break; 3200 1.78.2.2 skrll } 3201 1.78.2.2 skrll } 3202 1.78.2.2 skrll #endif 3203 1.78.2.2 skrll 3204 1.78.2.2 skrll txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3205 1.78.2.2 skrll if (txstat & ATW_TXSTAT_OWN) 3206 1.78.2.2 skrll break; 3207 1.78.2.2 skrll 3208 1.78.2.2 skrll SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3209 1.78.2.2 skrll 3210 1.78.2.2 skrll sc->sc_txfree += txs->txs_ndescs; 3211 1.78.2.2 skrll 3212 1.78.2.2 skrll bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3213 1.78.2.2 skrll 0, txs->txs_dmamap->dm_mapsize, 3214 1.78.2.2 skrll BUS_DMASYNC_POSTWRITE); 3215 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3216 1.78.2.2 skrll m_freem(txs->txs_mbuf); 3217 1.78.2.2 skrll txs->txs_mbuf = NULL; 3218 1.78.2.2 skrll 3219 1.78.2.2 skrll SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3220 1.78.2.2 skrll 3221 1.78.2.2 skrll if ((ifp->if_flags & IFF_DEBUG) != 0 && 3222 1.78.2.2 skrll (txstat & TXSTAT_ERRMASK) != 0) { 3223 1.78.2.2 skrll bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3224 1.78.2.2 skrll txstat_buf, sizeof(txstat_buf)); 3225 1.78.2.2 skrll printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3226 1.78.2.2 skrll txstat_buf, 3227 1.78.2.2 skrll MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3228 1.78.2.2 skrll } 3229 1.78.2.2 skrll 3230 1.78.2.2 skrll /* 3231 1.78.2.2 skrll * Check for errors and collisions. 3232 1.78.2.2 skrll */ 3233 1.78.2.2 skrll if (txstat & ATW_TXSTAT_TUF) 3234 1.78.2.2 skrll sc->sc_stats.ts_tx_tuf++; 3235 1.78.2.2 skrll if (txstat & ATW_TXSTAT_TLT) 3236 1.78.2.2 skrll sc->sc_stats.ts_tx_tlt++; 3237 1.78.2.2 skrll if (txstat & ATW_TXSTAT_TRT) 3238 1.78.2.2 skrll sc->sc_stats.ts_tx_trt++; 3239 1.78.2.2 skrll if (txstat & ATW_TXSTAT_TRO) 3240 1.78.2.2 skrll sc->sc_stats.ts_tx_tro++; 3241 1.78.2.2 skrll if (txstat & ATW_TXSTAT_SOFBR) { 3242 1.78.2.2 skrll sc->sc_stats.ts_tx_sofbr++; 3243 1.78.2.2 skrll } 3244 1.78.2.2 skrll 3245 1.78.2.2 skrll if ((txstat & ATW_TXSTAT_ES) == 0) 3246 1.78.2.2 skrll ifp->if_collisions += 3247 1.78.2.2 skrll MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3248 1.78.2.2 skrll else 3249 1.78.2.2 skrll ifp->if_oerrors++; 3250 1.78.2.2 skrll 3251 1.78.2.2 skrll ifp->if_opackets++; 3252 1.78.2.2 skrll } 3253 1.78.2.2 skrll 3254 1.78.2.2 skrll /* 3255 1.78.2.2 skrll * If there are no more pending transmissions, cancel the watchdog 3256 1.78.2.2 skrll * timer. 3257 1.78.2.2 skrll */ 3258 1.78.2.2 skrll if (txs == NULL) 3259 1.78.2.2 skrll sc->sc_tx_timer = 0; 3260 1.78.2.2 skrll #undef TXSTAT_ERRMASK 3261 1.78.2.2 skrll #undef TXSTAT_FMT 3262 1.78.2.2 skrll } 3263 1.78.2.2 skrll 3264 1.78.2.2 skrll /* 3265 1.78.2.2 skrll * atw_watchdog: [ifnet interface function] 3266 1.78.2.2 skrll * 3267 1.78.2.2 skrll * Watchdog timer handler. 3268 1.78.2.2 skrll */ 3269 1.78.2.2 skrll void 3270 1.78.2.2 skrll atw_watchdog(struct ifnet *ifp) 3271 1.78.2.2 skrll { 3272 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 3273 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3274 1.78.2.2 skrll 3275 1.78.2.2 skrll ifp->if_timer = 0; 3276 1.78.2.2 skrll if (ATW_IS_ENABLED(sc) == 0) 3277 1.78.2.2 skrll return; 3278 1.78.2.2 skrll 3279 1.78.2.2 skrll if (sc->sc_rescan_timer) { 3280 1.78.2.2 skrll if (--sc->sc_rescan_timer == 0) 3281 1.78.2.2 skrll (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3282 1.78.2.2 skrll } 3283 1.78.2.2 skrll if (sc->sc_tx_timer) { 3284 1.78.2.2 skrll if (--sc->sc_tx_timer == 0 && 3285 1.78.2.2 skrll !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3286 1.78.2.2 skrll printf("%s: transmit timeout\n", ifp->if_xname); 3287 1.78.2.2 skrll ifp->if_oerrors++; 3288 1.78.2.2 skrll (void)atw_init(ifp); 3289 1.78.2.2 skrll atw_start(ifp); 3290 1.78.2.2 skrll } 3291 1.78.2.2 skrll } 3292 1.78.2.2 skrll if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3293 1.78.2.2 skrll ifp->if_timer = 1; 3294 1.78.2.2 skrll ieee80211_watchdog(ifp); 3295 1.78.2.2 skrll } 3296 1.78.2.2 skrll 3297 1.78.2.2 skrll /* Compute the 802.11 Duration field and the PLCP Length fields for 3298 1.78.2.2 skrll * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3299 1.78.2.2 skrll * Write the fields to the ADM8211 Tx header, frm. 3300 1.78.2.2 skrll * 3301 1.78.2.2 skrll * TBD use the fragmentation threshold to find the right duration for 3302 1.78.2.2 skrll * the first & last fragments. 3303 1.78.2.2 skrll * 3304 1.78.2.2 skrll * TBD make certain of the duration fields applied by the ADM8211 to each 3305 1.78.2.2 skrll * fragment. I think that the ADM8211 knows how to subtract the CTS 3306 1.78.2.2 skrll * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3307 1.78.2.2 skrll * I also think that the ADM8211 does *some* arithmetic for us, because 3308 1.78.2.2 skrll * otherwise I think we would have to set a first duration for CTS/first 3309 1.78.2.2 skrll * fragment, a second duration for fragments between the first and the 3310 1.78.2.2 skrll * last, and a third duration for the last fragment. 3311 1.78.2.2 skrll * 3312 1.78.2.2 skrll * TBD make certain that duration fields reflect addition of FCS/WEP 3313 1.78.2.2 skrll * and correct duration arithmetic as necessary. 3314 1.78.2.2 skrll */ 3315 1.78.2.2 skrll static void 3316 1.78.2.2 skrll atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3317 1.78.2.2 skrll int len) 3318 1.78.2.2 skrll { 3319 1.78.2.2 skrll int remainder; 3320 1.78.2.2 skrll 3321 1.78.2.2 skrll /* deal also with encrypted fragments */ 3322 1.78.2.2 skrll if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3323 1.78.2.2 skrll DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3324 1.78.2.2 skrll sc->sc_dev.dv_xname)); 3325 1.78.2.2 skrll len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3326 1.78.2.2 skrll IEEE80211_WEP_CRCLEN; 3327 1.78.2.2 skrll } 3328 1.78.2.2 skrll 3329 1.78.2.2 skrll /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3330 1.78.2.2 skrll * duration (XXX added by MAC?). 3331 1.78.2.2 skrll */ 3332 1.78.2.2 skrll frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3333 1.78.2.2 skrll remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3334 1.78.2.2 skrll 3335 1.78.2.2 skrll if (rate <= 4) 3336 1.78.2.2 skrll /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3337 1.78.2.2 skrll frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3338 1.78.2.2 skrll IEEE80211_DUR_DS_SHORT_PREAMBLE + 3339 1.78.2.2 skrll IEEE80211_DUR_DS_FAST_PLCPHDR) + 3340 1.78.2.2 skrll IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3341 1.78.2.2 skrll else 3342 1.78.2.2 skrll /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3343 1.78.2.2 skrll frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3344 1.78.2.2 skrll IEEE80211_DUR_DS_SHORT_PREAMBLE + 3345 1.78.2.2 skrll IEEE80211_DUR_DS_FAST_PLCPHDR) + 3346 1.78.2.2 skrll IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3347 1.78.2.2 skrll 3348 1.78.2.2 skrll /* lengthen duration if long preamble */ 3349 1.78.2.2 skrll if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3350 1.78.2.2 skrll frm->atw_head_dur += 3351 1.78.2.2 skrll 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3352 1.78.2.2 skrll IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3353 1.78.2.2 skrll 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3354 1.78.2.2 skrll IEEE80211_DUR_DS_FAST_PLCPHDR); 3355 1.78.2.2 skrll 3356 1.78.2.2 skrll if (remainder != 0) 3357 1.78.2.2 skrll frm->atw_head_dur++; 3358 1.78.2.2 skrll 3359 1.78.2.2 skrll if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3360 1.78.2.2 skrll (rate == 2 || rate == 4)) { 3361 1.78.2.2 skrll /* derived from Linux: how could this be right? */ 3362 1.78.2.2 skrll frm->atw_head_plcplen = frm->atw_head_dur; 3363 1.78.2.2 skrll } else { 3364 1.78.2.2 skrll frm->atw_head_plcplen = (16 * len) / rate; 3365 1.78.2.2 skrll remainder = (80 * len) % (rate * 5); 3366 1.78.2.2 skrll 3367 1.78.2.2 skrll if (remainder != 0) { 3368 1.78.2.2 skrll frm->atw_head_plcplen++; 3369 1.78.2.2 skrll 3370 1.78.2.2 skrll /* XXX magic */ 3371 1.78.2.2 skrll if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3372 1.78.2.2 skrll rate == 22 && remainder <= 30) 3373 1.78.2.2 skrll frm->atw_head_plcplen |= 0x8000; 3374 1.78.2.2 skrll } 3375 1.78.2.2 skrll } 3376 1.78.2.2 skrll frm->atw_tail_plcplen = frm->atw_head_plcplen = 3377 1.78.2.2 skrll htole16(frm->atw_head_plcplen); 3378 1.78.2.2 skrll frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3379 1.78.2.2 skrll } 3380 1.78.2.2 skrll 3381 1.78.2.2 skrll #ifdef ATW_DEBUG 3382 1.78.2.2 skrll static void 3383 1.78.2.2 skrll atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3384 1.78.2.2 skrll { 3385 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 3386 1.78.2.2 skrll struct mbuf *m; 3387 1.78.2.2 skrll int i, noctets = 0; 3388 1.78.2.2 skrll 3389 1.78.2.2 skrll printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3390 1.78.2.2 skrll m0->m_pkthdr.len); 3391 1.78.2.2 skrll 3392 1.78.2.2 skrll for (m = m0; m; m = m->m_next) { 3393 1.78.2.2 skrll if (m->m_len == 0) 3394 1.78.2.2 skrll continue; 3395 1.78.2.2 skrll for (i = 0; i < m->m_len; i++) { 3396 1.78.2.2 skrll printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3397 1.78.2.2 skrll if (++noctets % 24 == 0) 3398 1.78.2.2 skrll printf("\n"); 3399 1.78.2.2 skrll } 3400 1.78.2.2 skrll } 3401 1.78.2.2 skrll printf("%s%s: %d bytes emitted\n", 3402 1.78.2.2 skrll (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3403 1.78.2.2 skrll } 3404 1.78.2.2 skrll #endif /* ATW_DEBUG */ 3405 1.78.2.2 skrll 3406 1.78.2.2 skrll /* 3407 1.78.2.2 skrll * atw_start: [ifnet interface function] 3408 1.78.2.2 skrll * 3409 1.78.2.2 skrll * Start packet transmission on the interface. 3410 1.78.2.2 skrll */ 3411 1.78.2.2 skrll void 3412 1.78.2.2 skrll atw_start(struct ifnet *ifp) 3413 1.78.2.2 skrll { 3414 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 3415 1.78.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3416 1.78.2.2 skrll struct ieee80211_node *ni; 3417 1.78.2.2 skrll struct ieee80211_frame *wh; 3418 1.78.2.2 skrll struct atw_frame *hh; 3419 1.78.2.2 skrll struct mbuf *m0, *m; 3420 1.78.2.2 skrll struct atw_txsoft *txs, *last_txs; 3421 1.78.2.2 skrll struct atw_txdesc *txd; 3422 1.78.2.2 skrll int do_encrypt, rate; 3423 1.78.2.2 skrll bus_dmamap_t dmamap; 3424 1.78.2.2 skrll int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3425 1.78.2.2 skrll 3426 1.78.2.2 skrll DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3427 1.78.2.2 skrll sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3428 1.78.2.2 skrll 3429 1.78.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3430 1.78.2.2 skrll return; 3431 1.78.2.2 skrll 3432 1.78.2.2 skrll /* 3433 1.78.2.2 skrll * Remember the previous number of free descriptors and 3434 1.78.2.2 skrll * the first descriptor we'll use. 3435 1.78.2.2 skrll */ 3436 1.78.2.2 skrll ofree = sc->sc_txfree; 3437 1.78.2.2 skrll firsttx = sc->sc_txnext; 3438 1.78.2.2 skrll 3439 1.78.2.2 skrll DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3440 1.78.2.2 skrll sc->sc_dev.dv_xname, ofree, firsttx)); 3441 1.78.2.2 skrll 3442 1.78.2.2 skrll /* 3443 1.78.2.2 skrll * Loop through the send queue, setting up transmit descriptors 3444 1.78.2.2 skrll * until we drain the queue, or use up all available transmit 3445 1.78.2.2 skrll * descriptors. 3446 1.78.2.2 skrll */ 3447 1.78.2.2 skrll while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3448 1.78.2.2 skrll sc->sc_txfree != 0) { 3449 1.78.2.2 skrll 3450 1.78.2.2 skrll /* 3451 1.78.2.2 skrll * Grab a packet off the management queue, if it 3452 1.78.2.2 skrll * is not empty. Otherwise, from the data queue. 3453 1.78.2.2 skrll */ 3454 1.78.2.2 skrll IF_DEQUEUE(&ic->ic_mgtq, m0); 3455 1.78.2.2 skrll if (m0 != NULL) { 3456 1.78.2.2 skrll ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3457 1.78.2.2 skrll m0->m_pkthdr.rcvif = NULL; 3458 1.78.2.2 skrll } else { 3459 1.78.2.2 skrll /* send no data packets until we are associated */ 3460 1.78.2.2 skrll if (ic->ic_state != IEEE80211_S_RUN) 3461 1.78.2.2 skrll break; 3462 1.78.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m0); 3463 1.78.2.2 skrll if (m0 == NULL) 3464 1.78.2.2 skrll break; 3465 1.78.2.2 skrll #if NBPFILTER > 0 3466 1.78.2.2 skrll if (ifp->if_bpf != NULL) 3467 1.78.2.2 skrll bpf_mtap(ifp->if_bpf, m0); 3468 1.78.2.2 skrll #endif /* NBPFILTER > 0 */ 3469 1.78.2.2 skrll if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3470 1.78.2.2 skrll ifp->if_oerrors++; 3471 1.78.2.2 skrll break; 3472 1.78.2.2 skrll } 3473 1.78.2.2 skrll } 3474 1.78.2.2 skrll 3475 1.78.2.2 skrll rate = MAX(ieee80211_get_rate(ic), 2); 3476 1.78.2.2 skrll 3477 1.78.2.2 skrll #if NBPFILTER > 0 3478 1.78.2.2 skrll /* 3479 1.78.2.2 skrll * Pass the packet to any BPF listeners. 3480 1.78.2.2 skrll */ 3481 1.78.2.2 skrll if (ic->ic_rawbpf != NULL) 3482 1.78.2.2 skrll bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3483 1.78.2.2 skrll 3484 1.78.2.2 skrll if (sc->sc_radiobpf != NULL) { 3485 1.78.2.2 skrll struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3486 1.78.2.2 skrll 3487 1.78.2.2 skrll tap->at_rate = rate; 3488 1.78.2.2 skrll tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3489 1.78.2.2 skrll tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3490 1.78.2.2 skrll 3491 1.78.2.2 skrll /* TBD tap->at_flags */ 3492 1.78.2.2 skrll 3493 1.78.2.2 skrll bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3494 1.78.2.2 skrll tap->at_ihdr.it_len, m0); 3495 1.78.2.2 skrll } 3496 1.78.2.2 skrll #endif /* NBPFILTER > 0 */ 3497 1.78.2.2 skrll 3498 1.78.2.2 skrll M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3499 1.78.2.2 skrll 3500 1.78.2.3 skrll if (ni != NULL) 3501 1.78.2.3 skrll ieee80211_release_node(ic, ni); 3502 1.78.2.2 skrll 3503 1.78.2.2 skrll if (m0 == NULL) { 3504 1.78.2.2 skrll ifp->if_oerrors++; 3505 1.78.2.2 skrll break; 3506 1.78.2.2 skrll } 3507 1.78.2.2 skrll 3508 1.78.2.2 skrll /* just to make sure. */ 3509 1.78.2.2 skrll m0 = m_pullup(m0, sizeof(struct atw_frame)); 3510 1.78.2.2 skrll 3511 1.78.2.2 skrll if (m0 == NULL) { 3512 1.78.2.2 skrll ifp->if_oerrors++; 3513 1.78.2.2 skrll break; 3514 1.78.2.2 skrll } 3515 1.78.2.2 skrll 3516 1.78.2.2 skrll hh = mtod(m0, struct atw_frame *); 3517 1.78.2.2 skrll wh = &hh->atw_ihdr; 3518 1.78.2.2 skrll 3519 1.78.2.2 skrll do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3520 1.78.2.2 skrll 3521 1.78.2.2 skrll /* Copy everything we need from the 802.11 header: 3522 1.78.2.2 skrll * Frame Control; address 1, address 3, or addresses 3523 1.78.2.2 skrll * 3 and 4. NIC fills in BSSID, SA. 3524 1.78.2.2 skrll */ 3525 1.78.2.2 skrll if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3526 1.78.2.2 skrll if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3527 1.78.2.2 skrll panic("%s: illegal WDS frame", 3528 1.78.2.2 skrll sc->sc_dev.dv_xname); 3529 1.78.2.2 skrll memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3530 1.78.2.2 skrll } else 3531 1.78.2.2 skrll memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3532 1.78.2.2 skrll 3533 1.78.2.2 skrll *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3534 1.78.2.2 skrll 3535 1.78.2.2 skrll /* initialize remaining Tx parameters */ 3536 1.78.2.2 skrll memset(&hh->u, 0, sizeof(hh->u)); 3537 1.78.2.2 skrll 3538 1.78.2.2 skrll hh->atw_rate = rate * 5; 3539 1.78.2.2 skrll /* XXX this could be incorrect if M_FCS. _encap should 3540 1.78.2.2 skrll * probably strip FCS just in case it sticks around in 3541 1.78.2.2 skrll * bridged packets. 3542 1.78.2.2 skrll */ 3543 1.78.2.7 skrll hh->atw_service = 0x00; /* XXX guess */ 3544 1.78.2.2 skrll hh->atw_paylen = htole16(m0->m_pkthdr.len - 3545 1.78.2.2 skrll sizeof(struct atw_frame)); 3546 1.78.2.2 skrll 3547 1.78.2.2 skrll hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3548 1.78.2.2 skrll hh->atw_rtylmt = 3; 3549 1.78.2.2 skrll hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3550 1.78.2.2 skrll if (do_encrypt) { 3551 1.78.2.2 skrll hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3552 1.78.2.2 skrll hh->atw_keyid = ic->ic_wep_txkey; 3553 1.78.2.2 skrll } 3554 1.78.2.2 skrll 3555 1.78.2.2 skrll /* TBD 4-addr frames */ 3556 1.78.2.2 skrll atw_frame_setdurs(sc, hh, rate, 3557 1.78.2.2 skrll m0->m_pkthdr.len - sizeof(struct atw_frame) + 3558 1.78.2.2 skrll sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3559 1.78.2.2 skrll 3560 1.78.2.2 skrll /* never fragment multicast frames */ 3561 1.78.2.2 skrll if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3562 1.78.2.2 skrll hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3563 1.78.2.2 skrll } else if (sc->sc_flags & ATWF_RTSCTS) { 3564 1.78.2.2 skrll hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3565 1.78.2.2 skrll } 3566 1.78.2.2 skrll 3567 1.78.2.2 skrll #ifdef ATW_DEBUG 3568 1.78.2.2 skrll hh->atw_fragnum = 0; 3569 1.78.2.2 skrll 3570 1.78.2.2 skrll if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3571 1.78.2.2 skrll printf("%s: dst = %s, rate = 0x%02x, " 3572 1.78.2.2 skrll "service = 0x%02x, paylen = 0x%04x\n", 3573 1.78.2.2 skrll sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3574 1.78.2.2 skrll hh->atw_rate, hh->atw_service, hh->atw_paylen); 3575 1.78.2.2 skrll 3576 1.78.2.2 skrll printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3577 1.78.2.2 skrll "dur1 = 0x%04x, dur2 = 0x%04x, " 3578 1.78.2.2 skrll "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3579 1.78.2.2 skrll sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3580 1.78.2.2 skrll hh->atw_tail_plcplen, hh->atw_head_plcplen, 3581 1.78.2.2 skrll hh->atw_tail_dur, hh->atw_head_dur); 3582 1.78.2.2 skrll 3583 1.78.2.2 skrll printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3584 1.78.2.2 skrll "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3585 1.78.2.2 skrll sc->sc_dev.dv_xname, hh->atw_hdrctl, 3586 1.78.2.2 skrll hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3587 1.78.2.2 skrll 3588 1.78.2.2 skrll printf("%s: keyid = %d\n", 3589 1.78.2.2 skrll sc->sc_dev.dv_xname, hh->atw_keyid); 3590 1.78.2.2 skrll 3591 1.78.2.2 skrll atw_dump_pkt(ifp, m0); 3592 1.78.2.2 skrll } 3593 1.78.2.2 skrll #endif /* ATW_DEBUG */ 3594 1.78.2.2 skrll 3595 1.78.2.2 skrll dmamap = txs->txs_dmamap; 3596 1.78.2.2 skrll 3597 1.78.2.2 skrll /* 3598 1.78.2.2 skrll * Load the DMA map. Copy and try (once) again if the packet 3599 1.78.2.2 skrll * didn't fit in the alloted number of segments. 3600 1.78.2.2 skrll */ 3601 1.78.2.2 skrll for (first = 1; 3602 1.78.2.2 skrll (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3603 1.78.2.2 skrll BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3604 1.78.2.2 skrll first = 0) { 3605 1.78.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 3606 1.78.2.2 skrll if (m == NULL) { 3607 1.78.2.2 skrll printf("%s: unable to allocate Tx mbuf\n", 3608 1.78.2.2 skrll sc->sc_dev.dv_xname); 3609 1.78.2.2 skrll break; 3610 1.78.2.2 skrll } 3611 1.78.2.2 skrll if (m0->m_pkthdr.len > MHLEN) { 3612 1.78.2.2 skrll MCLGET(m, M_DONTWAIT); 3613 1.78.2.2 skrll if ((m->m_flags & M_EXT) == 0) { 3614 1.78.2.2 skrll printf("%s: unable to allocate Tx " 3615 1.78.2.2 skrll "cluster\n", sc->sc_dev.dv_xname); 3616 1.78.2.2 skrll m_freem(m); 3617 1.78.2.2 skrll break; 3618 1.78.2.2 skrll } 3619 1.78.2.2 skrll } 3620 1.78.2.2 skrll m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3621 1.78.2.2 skrll m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3622 1.78.2.2 skrll m_freem(m0); 3623 1.78.2.2 skrll m0 = m; 3624 1.78.2.2 skrll m = NULL; 3625 1.78.2.2 skrll } 3626 1.78.2.2 skrll if (error != 0) { 3627 1.78.2.2 skrll printf("%s: unable to load Tx buffer, " 3628 1.78.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 3629 1.78.2.2 skrll m_freem(m0); 3630 1.78.2.2 skrll break; 3631 1.78.2.2 skrll } 3632 1.78.2.2 skrll 3633 1.78.2.2 skrll /* 3634 1.78.2.2 skrll * Ensure we have enough descriptors free to describe 3635 1.78.2.2 skrll * the packet. 3636 1.78.2.2 skrll */ 3637 1.78.2.2 skrll if (dmamap->dm_nsegs > sc->sc_txfree) { 3638 1.78.2.2 skrll /* 3639 1.78.2.2 skrll * Not enough free descriptors to transmit 3640 1.78.2.2 skrll * this packet. Unload the DMA map and 3641 1.78.2.2 skrll * drop the packet. Notify the upper layer 3642 1.78.2.2 skrll * that there are no more slots left. 3643 1.78.2.2 skrll * 3644 1.78.2.2 skrll * XXX We could allocate an mbuf and copy, but 3645 1.78.2.2 skrll * XXX it is worth it? 3646 1.78.2.2 skrll */ 3647 1.78.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 3648 1.78.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dmamap); 3649 1.78.2.2 skrll m_freem(m0); 3650 1.78.2.2 skrll break; 3651 1.78.2.2 skrll } 3652 1.78.2.2 skrll 3653 1.78.2.2 skrll /* 3654 1.78.2.2 skrll * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3655 1.78.2.2 skrll */ 3656 1.78.2.2 skrll 3657 1.78.2.2 skrll /* Sync the DMA map. */ 3658 1.78.2.2 skrll bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3659 1.78.2.2 skrll BUS_DMASYNC_PREWRITE); 3660 1.78.2.2 skrll 3661 1.78.2.2 skrll /* XXX arbitrary retry limit; 8 because I have seen it in 3662 1.78.2.2 skrll * use already and maybe 0 means "no tries" ! 3663 1.78.2.2 skrll */ 3664 1.78.2.2 skrll ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3665 1.78.2.2 skrll 3666 1.78.2.2 skrll DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3667 1.78.2.2 skrll sc->sc_dev.dv_xname, rate * 5)); 3668 1.78.2.2 skrll ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3669 1.78.2.2 skrll 3670 1.78.2.2 skrll /* 3671 1.78.2.2 skrll * Initialize the transmit descriptors. 3672 1.78.2.2 skrll */ 3673 1.78.2.2 skrll for (nexttx = sc->sc_txnext, seg = 0; 3674 1.78.2.2 skrll seg < dmamap->dm_nsegs; 3675 1.78.2.2 skrll seg++, nexttx = ATW_NEXTTX(nexttx)) { 3676 1.78.2.2 skrll /* 3677 1.78.2.2 skrll * If this is the first descriptor we're 3678 1.78.2.2 skrll * enqueueing, don't set the OWN bit just 3679 1.78.2.2 skrll * yet. That could cause a race condition. 3680 1.78.2.2 skrll * We'll do it below. 3681 1.78.2.2 skrll */ 3682 1.78.2.2 skrll txd = &sc->sc_txdescs[nexttx]; 3683 1.78.2.2 skrll txd->at_ctl = ctl | 3684 1.78.2.2 skrll ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3685 1.78.2.2 skrll 3686 1.78.2.2 skrll txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3687 1.78.2.2 skrll txd->at_flags = 3688 1.78.2.2 skrll htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3689 1.78.2.2 skrll ATW_TXFLAG_TBS1_MASK)) | 3690 1.78.2.2 skrll ((nexttx == (ATW_NTXDESC - 1)) 3691 1.78.2.2 skrll ? htole32(ATW_TXFLAG_TER) : 0); 3692 1.78.2.2 skrll lasttx = nexttx; 3693 1.78.2.2 skrll } 3694 1.78.2.2 skrll 3695 1.78.2.2 skrll IASSERT(lasttx != -1, ("bad lastx")); 3696 1.78.2.2 skrll /* Set `first segment' and `last segment' appropriately. */ 3697 1.78.2.2 skrll sc->sc_txdescs[sc->sc_txnext].at_flags |= 3698 1.78.2.2 skrll htole32(ATW_TXFLAG_FS); 3699 1.78.2.2 skrll sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3700 1.78.2.2 skrll 3701 1.78.2.2 skrll #ifdef ATW_DEBUG 3702 1.78.2.2 skrll if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3703 1.78.2.2 skrll printf(" txsoft %p transmit chain:\n", txs); 3704 1.78.2.2 skrll for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3705 1.78.2.2 skrll printf(" descriptor %d:\n", seg); 3706 1.78.2.2 skrll printf(" at_ctl: 0x%08x\n", 3707 1.78.2.2 skrll le32toh(sc->sc_txdescs[seg].at_ctl)); 3708 1.78.2.2 skrll printf(" at_flags: 0x%08x\n", 3709 1.78.2.2 skrll le32toh(sc->sc_txdescs[seg].at_flags)); 3710 1.78.2.2 skrll printf(" at_buf1: 0x%08x\n", 3711 1.78.2.2 skrll le32toh(sc->sc_txdescs[seg].at_buf1)); 3712 1.78.2.2 skrll printf(" at_buf2: 0x%08x\n", 3713 1.78.2.2 skrll le32toh(sc->sc_txdescs[seg].at_buf2)); 3714 1.78.2.2 skrll if (seg == lasttx) 3715 1.78.2.2 skrll break; 3716 1.78.2.2 skrll } 3717 1.78.2.2 skrll } 3718 1.78.2.2 skrll #endif 3719 1.78.2.2 skrll 3720 1.78.2.2 skrll /* Sync the descriptors we're using. */ 3721 1.78.2.2 skrll ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3722 1.78.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3723 1.78.2.2 skrll 3724 1.78.2.2 skrll /* 3725 1.78.2.2 skrll * Store a pointer to the packet so we can free it later, 3726 1.78.2.2 skrll * and remember what txdirty will be once the packet is 3727 1.78.2.2 skrll * done. 3728 1.78.2.2 skrll */ 3729 1.78.2.2 skrll txs->txs_mbuf = m0; 3730 1.78.2.2 skrll txs->txs_firstdesc = sc->sc_txnext; 3731 1.78.2.2 skrll txs->txs_lastdesc = lasttx; 3732 1.78.2.2 skrll txs->txs_ndescs = dmamap->dm_nsegs; 3733 1.78.2.2 skrll 3734 1.78.2.2 skrll /* Advance the tx pointer. */ 3735 1.78.2.2 skrll sc->sc_txfree -= dmamap->dm_nsegs; 3736 1.78.2.2 skrll sc->sc_txnext = nexttx; 3737 1.78.2.2 skrll 3738 1.78.2.2 skrll SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3739 1.78.2.2 skrll SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3740 1.78.2.2 skrll 3741 1.78.2.2 skrll last_txs = txs; 3742 1.78.2.2 skrll } 3743 1.78.2.2 skrll 3744 1.78.2.2 skrll if (txs == NULL || sc->sc_txfree == 0) { 3745 1.78.2.2 skrll /* No more slots left; notify upper layer. */ 3746 1.78.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 3747 1.78.2.2 skrll } 3748 1.78.2.2 skrll 3749 1.78.2.2 skrll if (sc->sc_txfree != ofree) { 3750 1.78.2.2 skrll DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3751 1.78.2.2 skrll sc->sc_dev.dv_xname, lasttx, firsttx)); 3752 1.78.2.2 skrll /* 3753 1.78.2.2 skrll * Cause a transmit interrupt to happen on the 3754 1.78.2.2 skrll * last packet we enqueued. 3755 1.78.2.2 skrll */ 3756 1.78.2.2 skrll sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3757 1.78.2.2 skrll ATW_CDTXSYNC(sc, lasttx, 1, 3758 1.78.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3759 1.78.2.2 skrll 3760 1.78.2.2 skrll /* 3761 1.78.2.2 skrll * The entire packet chain is set up. Give the 3762 1.78.2.2 skrll * first descriptor to the chip now. 3763 1.78.2.2 skrll */ 3764 1.78.2.2 skrll sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3765 1.78.2.2 skrll ATW_CDTXSYNC(sc, firsttx, 1, 3766 1.78.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3767 1.78.2.2 skrll 3768 1.78.2.2 skrll /* Wake up the transmitter. */ 3769 1.78.2.2 skrll ATW_WRITE(sc, ATW_TDR, 0x1); 3770 1.78.2.2 skrll 3771 1.78.2.2 skrll /* Set a watchdog timer in case the chip flakes out. */ 3772 1.78.2.2 skrll sc->sc_tx_timer = 5; 3773 1.78.2.2 skrll ifp->if_timer = 1; 3774 1.78.2.2 skrll } 3775 1.78.2.2 skrll } 3776 1.78.2.2 skrll 3777 1.78.2.2 skrll /* 3778 1.78.2.2 skrll * atw_power: 3779 1.78.2.2 skrll * 3780 1.78.2.2 skrll * Power management (suspend/resume) hook. 3781 1.78.2.2 skrll */ 3782 1.78.2.2 skrll void 3783 1.78.2.2 skrll atw_power(int why, void *arg) 3784 1.78.2.2 skrll { 3785 1.78.2.2 skrll struct atw_softc *sc = arg; 3786 1.78.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 3787 1.78.2.2 skrll int s; 3788 1.78.2.2 skrll 3789 1.78.2.2 skrll DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3790 1.78.2.2 skrll 3791 1.78.2.2 skrll s = splnet(); 3792 1.78.2.2 skrll switch (why) { 3793 1.78.2.2 skrll case PWR_STANDBY: 3794 1.78.2.2 skrll /* XXX do nothing. */ 3795 1.78.2.2 skrll break; 3796 1.78.2.2 skrll case PWR_SUSPEND: 3797 1.78.2.2 skrll atw_stop(ifp, 0); 3798 1.78.2.2 skrll if (sc->sc_power != NULL) 3799 1.78.2.2 skrll (*sc->sc_power)(sc, why); 3800 1.78.2.2 skrll break; 3801 1.78.2.2 skrll case PWR_RESUME: 3802 1.78.2.2 skrll if (ifp->if_flags & IFF_UP) { 3803 1.78.2.2 skrll if (sc->sc_power != NULL) 3804 1.78.2.2 skrll (*sc->sc_power)(sc, why); 3805 1.78.2.2 skrll atw_init(ifp); 3806 1.78.2.2 skrll } 3807 1.78.2.2 skrll break; 3808 1.78.2.2 skrll case PWR_SOFTSUSPEND: 3809 1.78.2.2 skrll case PWR_SOFTSTANDBY: 3810 1.78.2.2 skrll case PWR_SOFTRESUME: 3811 1.78.2.2 skrll break; 3812 1.78.2.2 skrll } 3813 1.78.2.2 skrll splx(s); 3814 1.78.2.2 skrll } 3815 1.78.2.2 skrll 3816 1.78.2.2 skrll /* 3817 1.78.2.2 skrll * atw_ioctl: [ifnet interface function] 3818 1.78.2.2 skrll * 3819 1.78.2.2 skrll * Handle control requests from the operator. 3820 1.78.2.2 skrll */ 3821 1.78.2.2 skrll int 3822 1.78.2.2 skrll atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3823 1.78.2.2 skrll { 3824 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 3825 1.78.2.2 skrll struct ifreq *ifr = (struct ifreq *)data; 3826 1.78.2.2 skrll int s, error = 0; 3827 1.78.2.2 skrll 3828 1.78.2.2 skrll /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3829 1.78.2.2 skrll if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3830 1.78.2.2 skrll return ENXIO; 3831 1.78.2.2 skrll 3832 1.78.2.2 skrll s = splnet(); 3833 1.78.2.2 skrll 3834 1.78.2.2 skrll switch (cmd) { 3835 1.78.2.2 skrll case SIOCSIFFLAGS: 3836 1.78.2.2 skrll if (ifp->if_flags & IFF_UP) { 3837 1.78.2.2 skrll if (ATW_IS_ENABLED(sc)) { 3838 1.78.2.2 skrll /* 3839 1.78.2.2 skrll * To avoid rescanning another access point, 3840 1.78.2.2 skrll * do not call atw_init() here. Instead, 3841 1.78.2.2 skrll * only reflect media settings. 3842 1.78.2.2 skrll */ 3843 1.78.2.2 skrll atw_filter_setup(sc); 3844 1.78.2.2 skrll } else 3845 1.78.2.2 skrll error = atw_init(ifp); 3846 1.78.2.2 skrll } else if (ATW_IS_ENABLED(sc)) 3847 1.78.2.2 skrll atw_stop(ifp, 1); 3848 1.78.2.2 skrll break; 3849 1.78.2.2 skrll case SIOCADDMULTI: 3850 1.78.2.2 skrll case SIOCDELMULTI: 3851 1.78.2.2 skrll error = (cmd == SIOCADDMULTI) ? 3852 1.78.2.2 skrll ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3853 1.78.2.2 skrll ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3854 1.78.2.2 skrll if (error == ENETRESET) { 3855 1.78.2.6 skrll if (ifp->if_flags & IFF_RUNNING) 3856 1.78.2.2 skrll atw_filter_setup(sc); /* do not rescan */ 3857 1.78.2.2 skrll error = 0; 3858 1.78.2.2 skrll } 3859 1.78.2.2 skrll break; 3860 1.78.2.2 skrll default: 3861 1.78.2.2 skrll error = ieee80211_ioctl(ifp, cmd, data); 3862 1.78.2.2 skrll if (error == ENETRESET) { 3863 1.78.2.2 skrll if (ATW_IS_ENABLED(sc)) 3864 1.78.2.2 skrll error = atw_init(ifp); 3865 1.78.2.2 skrll else 3866 1.78.2.2 skrll error = 0; 3867 1.78.2.2 skrll } 3868 1.78.2.2 skrll break; 3869 1.78.2.2 skrll } 3870 1.78.2.2 skrll 3871 1.78.2.2 skrll /* Try to get more packets going. */ 3872 1.78.2.2 skrll if (ATW_IS_ENABLED(sc)) 3873 1.78.2.2 skrll atw_start(ifp); 3874 1.78.2.2 skrll 3875 1.78.2.2 skrll splx(s); 3876 1.78.2.2 skrll return (error); 3877 1.78.2.2 skrll } 3878 1.78.2.2 skrll 3879 1.78.2.2 skrll static int 3880 1.78.2.2 skrll atw_media_change(struct ifnet *ifp) 3881 1.78.2.2 skrll { 3882 1.78.2.2 skrll int error; 3883 1.78.2.2 skrll 3884 1.78.2.2 skrll error = ieee80211_media_change(ifp); 3885 1.78.2.2 skrll if (error == ENETRESET) { 3886 1.78.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3887 1.78.2.2 skrll (IFF_RUNNING|IFF_UP)) 3888 1.78.2.2 skrll atw_init(ifp); /* XXX lose error */ 3889 1.78.2.2 skrll error = 0; 3890 1.78.2.2 skrll } 3891 1.78.2.2 skrll return error; 3892 1.78.2.2 skrll } 3893 1.78.2.2 skrll 3894 1.78.2.2 skrll static void 3895 1.78.2.2 skrll atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3896 1.78.2.2 skrll { 3897 1.78.2.2 skrll struct atw_softc *sc = ifp->if_softc; 3898 1.78.2.2 skrll 3899 1.78.2.2 skrll if (ATW_IS_ENABLED(sc) == 0) { 3900 1.78.2.2 skrll imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3901 1.78.2.2 skrll imr->ifm_status = 0; 3902 1.78.2.2 skrll return; 3903 1.78.2.2 skrll } 3904 1.78.2.2 skrll ieee80211_media_status(ifp, imr); 3905 1.78.2.2 skrll } 3906
Indexes created Mon Oct 20 10:10:01 GMT 2025