atw.c revision 1.1
1 /* $NetBSD: atw.c,v 1.1 2003/07/06 22:58:08 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.1 2003/07/06 22:58:08 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 #include <net/if_ieee80211.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/ic/atwreg.h> 78 #include <dev/ic/atwvar.h> 79 #include <dev/ic/smc93cx6var.h> 80 81 /* XXX TBD open questions 82 * 83 * 84 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 85 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 86 * handle this for me? 87 * 88 */ 89 /* device attachment 90 * 91 * print TOFS[012] 92 * 93 * device initialization 94 * 95 * clear ATW_FRCTL_MAXPSP to disable max power saving 96 * set ATW_TXBR_ALCUPDATE to enable ALC 97 * set TOFS[012]? (hope not) 98 * disable rx/tx 99 * set ATW_PAR_SWR (software reset) 100 * wait for ATW_PAR_SWR clear 101 * disable interrupts 102 * ack status register 103 * enable interrupts 104 * 105 * rx/tx initialization 106 * 107 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 108 * allocate and init descriptor rings 109 * write ATW_PAR_DSL (descriptor skip length) 110 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 111 * write ATW_NAR_SQ for one/both transmit descriptor rings 112 * write ATW_NAR_SQ for one/both transmit descriptor rings 113 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * 115 * rx/tx end 116 * 117 * stop DMA 118 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * flush tx w/ ATW_NAR_HF 120 * 121 * scan 122 * 123 * initialize rx/tx 124 * 125 * IBSS join/create 126 * 127 * set ATW_NAR_EA (is set by ASIC?) 128 * 129 * BSS join: (re)association response 130 * 131 * set ATW_FRCTL_AID 132 * 133 * optimizations ??? 134 * 135 */ 136 137 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 138 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 139 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 140 141 int atw_rfio_enable_delay = 20 * 1000; 142 int atw_rfio_disable_delay = 2 * 1000; 143 int atw_writewep_delay = 5; 144 int atw_beacon_len_adjust = 4; 145 146 #ifdef ATW_DEBUG 147 int atw_xhdrctl = 0; 148 int atw_xrtylmt = ~0; 149 int atw_xservice = IEEE80211_PLCP_SERVICE; 150 int atw_xpaylen = 0; 151 152 int atw_debug = 0; 153 154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 157 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 158 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 159 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 160 static void atw_print_regs(struct atw_softc *, const char *); 161 static void atw_rf3000_print(struct atw_softc *); 162 static void atw_si4126_print(struct atw_softc *); 163 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 164 #else 165 #define ATW_DPRINTF(x) 166 #define ATW_DPRINTF2(x) 167 #define ATW_DPRINTF3(x) 168 #define DPRINTF(sc, x) /* nothing */ 169 #define DPRINTF2(sc, x) /* nothing */ 170 #define DPRINTF3(sc, x) /* nothing */ 171 #endif 172 173 #ifdef ATW_STATS 174 void atw_print_stats __P((struct atw_softc *)); 175 #endif 176 177 void atw_start __P((struct ifnet *)); 178 void atw_watchdog __P((struct ifnet *)); 179 int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 int atw_init __P((struct ifnet *)); 181 void atw_stop __P((struct ifnet *, int)); 182 183 void atw_reset __P((struct atw_softc *)); 184 int atw_read_srom __P((struct atw_softc *)); 185 186 void atw_shutdown __P((void *)); 187 188 void atw_rxdrain __P((struct atw_softc *)); 189 int atw_add_rxbuf __P((struct atw_softc *, int)); 190 void atw_idle __P((struct atw_softc *, u_int32_t)); 191 192 int atw_enable __P((struct atw_softc *)); 193 void atw_disable __P((struct atw_softc *)); 194 void atw_power __P((int, void *)); 195 196 void atw_rxintr __P((struct atw_softc *)); 197 void atw_txintr __P((struct atw_softc *)); 198 void atw_linkintr __P((struct atw_softc *, u_int32_t)); 199 200 static int atw_newstate(void *, enum ieee80211_state); 201 static void atw_tsf(struct atw_softc *); 202 static void atw_start_beacon(struct atw_softc *, int); 203 static void atw_write_wep(struct atw_softc *); 204 static void atw_write_bssid(struct atw_softc *); 205 static void atw_write_bcn_thresh(struct atw_softc *); 206 static void atw_write_ssid(struct atw_softc *); 207 static void atw_write_sup_rates(struct atw_softc *); 208 static void atw_clear_sram(struct atw_softc *); 209 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 210 static void atw_media_status(struct ifnet *, struct ifmediareq *); 211 static void atw_filter_setup(struct atw_softc *); 212 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 213 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 214 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, int, 215 u_int32_t); 216 217 static int atw_tune(struct atw_softc *); 218 219 static void atw_rfio_enable(struct atw_softc *, int); 220 221 /* RFMD RF3000 Baseband Processor */ 222 static int atw_rf3000_init(struct atw_softc *); 223 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 224 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 225 #ifdef ATW_DEBUG 226 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 227 #endif /* ATW_DEBUG */ 228 229 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 230 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 231 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 232 #ifdef ATW_DEBUG 233 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 234 #endif /* ATW_DEBUG */ 235 236 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 237 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 238 239 const char *atw_tx_state[] = { 240 "STOPPED", 241 "RUNNING - FETCH", 242 "RUNNING - WAIT", 243 "RUNNING - READING", 244 "-- RESERVED1 --", 245 "-- RESERVED2 --", 246 "SUSPENDED", 247 "RUNNING - CLOSE" 248 }; 249 250 const char *atw_rx_state[] = { 251 "STOPPED", 252 "RUNNING - FETCH", 253 "RUNNING - CHECK", 254 "RUNNING - WAIT", 255 "SUSPENDED", 256 "RUNNING - CLOSE", 257 "RUNNING - FLUSH", 258 "RUNNING - QUEUE" 259 }; 260 261 int 262 atw_activate(struct device *self, enum devact act) 263 { 264 struct atw_softc *sc = (struct atw_softc *)self; 265 int rv = 0, s; 266 267 s = splnet(); 268 switch (act) { 269 case DVACT_ACTIVATE: 270 rv = EOPNOTSUPP; 271 break; 272 273 case DVACT_DEACTIVATE: 274 if_deactivate(&sc->sc_ic.ic_if); 275 break; 276 } 277 splx(s); 278 return rv; 279 } 280 281 /* 282 * atw_enable: 283 * 284 * Enable the ADM8211 chip. 285 */ 286 int 287 atw_enable(sc) 288 struct atw_softc *sc; 289 { 290 291 if (ATW_IS_ENABLED(sc) == 0) { 292 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 293 printf("%s: device enable failed\n", 294 sc->sc_dev.dv_xname); 295 return (EIO); 296 } 297 sc->sc_flags |= ATWF_ENABLED; 298 } 299 return (0); 300 } 301 302 /* 303 * atw_disable: 304 * 305 * Disable the ADM8211 chip. 306 */ 307 void 308 atw_disable(sc) 309 struct atw_softc *sc; 310 { 311 if (!ATW_IS_ENABLED(sc)) 312 return; 313 if (sc->sc_disable != NULL) 314 (*sc->sc_disable)(sc); 315 sc->sc_flags &= ~ATWF_ENABLED; 316 } 317 318 /* Returns -1 on failure. */ 319 int 320 atw_read_srom(struct atw_softc *sc) 321 { 322 struct seeprom_descriptor sd; 323 u_int32_t reg; 324 325 (void)memset(&sd, 0, sizeof(sd)); 326 327 reg = ATW_READ(sc, ATW_TEST0); 328 329 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 330 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 331 return -1; 332 } 333 334 switch (reg & ATW_TEST0_EPTYP_MASK) { 335 case ATW_TEST0_EPTYP_93c66: 336 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 337 sc->sc_sromsz = 512; 338 sd.sd_chip = C56_66; 339 break; 340 case ATW_TEST0_EPTYP_93c46: 341 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 342 sc->sc_sromsz = 128; 343 sd.sd_chip = C46; 344 break; 345 default: 346 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 347 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 348 return -1; 349 } 350 351 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 352 353 if (sc->sc_srom == NULL) { 354 printf("%s: unable to allocate SROM buffer\n", 355 sc->sc_dev.dv_xname); 356 return -1; 357 } 358 359 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 360 361 /* ADM8211 has a single 32-bit register for controlling the 362 * 93cx6 SROM. Bit SRS enables the serial port. There is no 363 * "ready" bit. The ADM8211 input/output sense is the reverse 364 * of read_seeprom's. 365 */ 366 sd.sd_tag = sc->sc_st; 367 sd.sd_bsh = sc->sc_sh; 368 sd.sd_regsize = 4; 369 sd.sd_control_offset = ATW_SPR; 370 sd.sd_status_offset = ATW_SPR; 371 sd.sd_dataout_offset = ATW_SPR; 372 sd.sd_CK = ATW_SPR_SCLK; 373 sd.sd_CS = ATW_SPR_SCS; 374 sd.sd_DI = ATW_SPR_SDO; 375 sd.sd_DO = ATW_SPR_SDI; 376 sd.sd_MS = ATW_SPR_SRS; 377 sd.sd_RDY = 0; 378 379 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 380 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 381 free(sc->sc_srom, M_DEVBUF); 382 return -1; 383 } 384 #ifdef ATW_DEBUG 385 { 386 int i; 387 ATW_DPRINTF2(("\nSerial EEPROM:\n\t")); 388 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 389 if (((i % 8) == 0) && (i != 0)) { 390 ATW_DPRINTF2(("\n\t")); 391 } 392 ATW_DPRINTF2((" 0x%x", sc->sc_srom[i])); 393 } 394 ATW_DPRINTF2(("\n")); 395 } 396 #endif /* ATW_DEBUG */ 397 return 0; 398 } 399 400 #ifdef ATW_DEBUG 401 static void 402 atw_print_regs(struct atw_softc *sc, const char *where) 403 { 404 #define PRINTREG(sc, reg) \ 405 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 406 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 407 408 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 409 410 PRINTREG(sc, ATW_PAR); 411 PRINTREG(sc, ATW_FRCTL); 412 PRINTREG(sc, ATW_TDR); 413 PRINTREG(sc, ATW_WTDP); 414 PRINTREG(sc, ATW_RDR); 415 PRINTREG(sc, ATW_WRDP); 416 PRINTREG(sc, ATW_RDB); 417 PRINTREG(sc, ATW_CSR3A); 418 PRINTREG(sc, ATW_TDBD); 419 PRINTREG(sc, ATW_TDBP); 420 PRINTREG(sc, ATW_STSR); 421 PRINTREG(sc, ATW_CSR5A); 422 PRINTREG(sc, ATW_NAR); 423 PRINTREG(sc, ATW_CSR6A); 424 PRINTREG(sc, ATW_IER); 425 PRINTREG(sc, ATW_CSR7A); 426 PRINTREG(sc, ATW_LPC); 427 PRINTREG(sc, ATW_TEST1); 428 PRINTREG(sc, ATW_SPR); 429 PRINTREG(sc, ATW_TEST0); 430 PRINTREG(sc, ATW_WCSR); 431 PRINTREG(sc, ATW_WPDR); 432 PRINTREG(sc, ATW_GPTMR); 433 PRINTREG(sc, ATW_GPIO); 434 PRINTREG(sc, ATW_BBPCTL); 435 PRINTREG(sc, ATW_SYNCTL); 436 PRINTREG(sc, ATW_PLCPHD); 437 PRINTREG(sc, ATW_MMIWADDR); 438 PRINTREG(sc, ATW_MMIRADDR1); 439 PRINTREG(sc, ATW_MMIRADDR2); 440 PRINTREG(sc, ATW_TXBR); 441 PRINTREG(sc, ATW_CSR15A); 442 PRINTREG(sc, ATW_ALCSTAT); 443 PRINTREG(sc, ATW_TOFS2); 444 PRINTREG(sc, ATW_CMDR); 445 PRINTREG(sc, ATW_PCIC); 446 PRINTREG(sc, ATW_PMCSR); 447 PRINTREG(sc, ATW_PAR0); 448 PRINTREG(sc, ATW_PAR1); 449 PRINTREG(sc, ATW_MAR0); 450 PRINTREG(sc, ATW_MAR1); 451 PRINTREG(sc, ATW_ATIMDA0); 452 PRINTREG(sc, ATW_ABDA1); 453 PRINTREG(sc, ATW_BSSID0); 454 PRINTREG(sc, ATW_TXLMT); 455 PRINTREG(sc, ATW_MIBCNT); 456 PRINTREG(sc, ATW_BCNT); 457 PRINTREG(sc, ATW_TSFTH); 458 PRINTREG(sc, ATW_TSC); 459 PRINTREG(sc, ATW_SYNRF); 460 PRINTREG(sc, ATW_BPLI); 461 PRINTREG(sc, ATW_CAP0); 462 PRINTREG(sc, ATW_CAP1); 463 PRINTREG(sc, ATW_RMD); 464 PRINTREG(sc, ATW_CFPP); 465 PRINTREG(sc, ATW_TOFS0); 466 PRINTREG(sc, ATW_TOFS1); 467 PRINTREG(sc, ATW_IFST); 468 PRINTREG(sc, ATW_RSPT); 469 PRINTREG(sc, ATW_TSFTL); 470 PRINTREG(sc, ATW_WEPCTL); 471 PRINTREG(sc, ATW_WESK); 472 PRINTREG(sc, ATW_WEPCNT); 473 PRINTREG(sc, ATW_MACTEST); 474 PRINTREG(sc, ATW_FER); 475 PRINTREG(sc, ATW_FEMR); 476 PRINTREG(sc, ATW_FPSR); 477 PRINTREG(sc, ATW_FFER); 478 #undef PRINTREG 479 } 480 #endif /* ATW_DEBUG */ 481 482 /* 483 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 484 */ 485 void 486 atw_attach(struct atw_softc *sc) 487 { 488 struct ieee80211com *ic = &sc->sc_ic; 489 struct ifnet *ifp = &ic->ic_if; 490 int country_code, error, i, nrate; 491 u_int32_t reg; 492 static const char *type_strings[] = {"Intersil (not supported)", 493 "RFMD", "Marvel (not supported)"}; 494 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 496 }; 497 498 sc->sc_txth = atw_txthresh_tab_lo; 499 500 SIMPLEQ_INIT(&sc->sc_txfreeq); 501 SIMPLEQ_INIT(&sc->sc_txdirtyq); 502 503 #ifdef ATW_DEBUG 504 atw_print_regs(sc, "atw_attach"); 505 #endif /* ATW_DEBUG */ 506 507 /* 508 * Allocate the control data structures, and create and load the 509 * DMA map for it. 510 */ 511 if ((error = bus_dmamem_alloc(sc->sc_dmat, 512 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 513 1, &sc->sc_cdnseg, 0)) != 0) { 514 printf("%s: unable to allocate control data, error = %d\n", 515 sc->sc_dev.dv_xname, error); 516 goto fail_0; 517 } 518 519 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 520 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 521 BUS_DMA_COHERENT)) != 0) { 522 printf("%s: unable to map control data, error = %d\n", 523 sc->sc_dev.dv_xname, error); 524 goto fail_1; 525 } 526 527 if ((error = bus_dmamap_create(sc->sc_dmat, 528 sizeof(struct atw_control_data), 1, 529 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 530 printf("%s: unable to create control data DMA map, " 531 "error = %d\n", sc->sc_dev.dv_xname, error); 532 goto fail_2; 533 } 534 535 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 536 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 537 0)) != 0) { 538 printf("%s: unable to load control data DMA map, error = %d\n", 539 sc->sc_dev.dv_xname, error); 540 goto fail_3; 541 } 542 543 /* 544 * Create the transmit buffer DMA maps. 545 */ 546 sc->sc_ntxsegs = ATW_NTXSEGS; 547 for (i = 0; i < ATW_TXQUEUELEN; i++) { 548 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 549 sc->sc_ntxsegs, MCLBYTES, 0, 0, 550 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 551 printf("%s: unable to create tx DMA map %d, " 552 "error = %d\n", sc->sc_dev.dv_xname, i, error); 553 goto fail_4; 554 } 555 } 556 557 /* 558 * Create the receive buffer DMA maps. 559 */ 560 for (i = 0; i < ATW_NRXDESC; i++) { 561 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 562 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 563 printf("%s: unable to create rx DMA map %d, " 564 "error = %d\n", sc->sc_dev.dv_xname, i, error); 565 goto fail_5; 566 } 567 sc->sc_rxsoft[i].rxs_mbuf = NULL; 568 } 569 570 /* Reset the chip to a known state. */ 571 atw_reset(sc); 572 573 if (atw_read_srom(sc) == -1) 574 return; 575 576 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 577 ATW_SR_RFTYPE_MASK); 578 579 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 580 ATW_SR_BBPTYPE_MASK); 581 582 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 583 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 584 return; 585 } 586 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 587 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 588 return; 589 } 590 591 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 592 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 593 594 /* XXX There exists a Linux driver which seems to use RFType = 0 for 595 * MARVEL. My bug, or theirs? 596 */ 597 598 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 599 600 switch (sc->sc_rftype) { 601 case ATW_RFTYPE_INTERSIL: 602 reg |= ATW_SYNCTL_CS1; 603 break; 604 case ATW_RFTYPE_RFMD: 605 reg |= ATW_SYNCTL_CS0; 606 break; 607 case ATW_RFTYPE_MARVEL: 608 break; 609 } 610 611 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 612 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 613 614 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 615 616 switch (sc->sc_bbptype) { 617 case ATW_RFTYPE_INTERSIL: 618 reg |= ATW_BBPCTL_TWI; 619 break; 620 case ATW_RFTYPE_RFMD: 621 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 622 ATW_BBPCTL_CCA_ACTLO; 623 break; 624 case ATW_RFTYPE_MARVEL: 625 break; 626 } 627 628 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 629 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 630 631 /* 632 * From this point forward, the attachment cannot fail. A failure 633 * before this point releases all resources that may have been 634 * allocated. 635 */ 636 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 637 638 ATW_DPRINTF2((" SROM MAC %04x%04x%04x", 639 htole16(sc->sc_srom[ATW_SR_MAC00]), 640 htole16(sc->sc_srom[ATW_SR_MAC01]), 641 htole16(sc->sc_srom[ATW_SR_MAC10]))); 642 643 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 644 ATW_SR_CTRY_MASK); 645 646 /* Find available channels */ 647 switch (country_code) { 648 case COUNTRY_MMK2: /* 1-14 */ 649 setbit(ic->ic_chan_avail, 14); 650 break; 651 case COUNTRY_ETSI: /* 1-13 */ 652 for (i = 1; i <= 13; i++) 653 setbit(ic->ic_chan_avail, i); 654 break; 655 case COUNTRY_FCC: /* 1-11 */ 656 case COUNTRY_IC: /* 1-11 */ 657 for (i = 1; i <= 11; i++) 658 setbit(ic->ic_chan_avail, i); 659 break; 660 case COUNTRY_MMK: /* 14 */ 661 setbit(ic->ic_chan_avail, 14); 662 break; 663 case COUNTRY_FRANCE: /* 10-13 */ 664 for (i = 10; i <= 13; i++) 665 setbit(ic->ic_chan_avail, i); 666 break; 667 default: /* assume channels 10-11 */ 668 case COUNTRY_SPAIN: /* 10-11 */ 669 for (i = 10; i <= 11; i++) 670 setbit(ic->ic_chan_avail, i); 671 break; 672 } 673 674 /* Read the MAC address. */ 675 reg = ATW_READ(sc, ATW_PAR0); 676 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 677 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 678 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 679 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 680 reg = ATW_READ(sc, ATW_PAR1); 681 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 682 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 683 684 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 685 printf(" could not get mac address, attach failed\n"); 686 return; 687 } 688 689 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 690 691 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 692 ifp->if_softc = sc; 693 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 694 IFF_NOTRAILERS; 695 ifp->if_ioctl = atw_ioctl; 696 ifp->if_start = atw_start; 697 ifp->if_watchdog = atw_watchdog; 698 ifp->if_init = atw_init; 699 ifp->if_stop = atw_stop; 700 IFQ_SET_READY(&ifp->if_snd); 701 702 ic->ic_phytype = IEEE80211_T_DS; 703 ic->ic_opmode = IEEE80211_M_STA; 704 ic->ic_flags = IEEE80211_F_HASPMGT | IEEE80211_F_HASIBSS | 705 IEEE80211_F_HASHOSTAP | IEEE80211_F_HASWEP; 706 ic->ic_state = IEEE80211_S_INIT; 707 ic->ic_newstate = atw_newstate; 708 709 #if 0 710 ic->ic_pfxlen = offsetof(struct atw_frame, atw_ihdr); 711 #endif 712 ic->ic_hdrlen = sizeof(struct ieee80211_frame_addr4); 713 714 nrate = 0; 715 ic->ic_sup_rates[nrate++] = 2; 716 ic->ic_sup_rates[nrate++] = 4; 717 ic->ic_sup_rates[nrate++] = 11; 718 ic->ic_sup_rates[nrate++] = 22; 719 720 /* 721 * Call MI attach routines. 722 */ 723 724 if_attach(ifp); 725 ieee80211_ifattach(ifp); 726 727 callout_init(&sc->sc_scan_timer); 728 729 /* hardware answers probe request */ 730 ic->ic_recv_mgmt[IEEE80211_FC0_SUBTYPE_PROBE_REQ 731 >> IEEE80211_FC0_SUBTYPE_SHIFT] = NULL; 732 733 /* NB: override default setting */ 734 ic->ic_media.ifm_status = atw_media_status; 735 736 /* possibly we should fill in our own sc_send_prresp, since 737 * the ADM8211 is probably sending probe responses in ad hoc 738 * mode. 739 */ 740 741 sc->sc_recv_beacon = 742 ic->ic_recv_mgmt[IEEE80211_FC0_SUBTYPE_BEACON >> 743 IEEE80211_FC0_SUBTYPE_SHIFT]; 744 sc->sc_recv_prresp = 745 ic->ic_recv_mgmt[IEEE80211_FC0_SUBTYPE_PROBE_RESP >> 746 IEEE80211_FC0_SUBTYPE_SHIFT]; 747 748 ic->ic_recv_mgmt[IEEE80211_FC0_SUBTYPE_BEACON 749 >> IEEE80211_FC0_SUBTYPE_SHIFT] = atw_recv_beacon; 750 ic->ic_recv_mgmt[IEEE80211_FC0_SUBTYPE_PROBE_RESP 751 >> IEEE80211_FC0_SUBTYPE_SHIFT] = atw_recv_beacon; 752 #if 0 753 #if NBPFILTER > 0 754 bpfattach2(ifp, DLT_IEEE802_11_RADIO, /* ??? */, 755 &sc->sc_radiobpf); 756 #endif 757 #endif 758 759 /* 760 * Make sure the interface is shutdown during reboot. 761 */ 762 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 763 if (sc->sc_sdhook == NULL) 764 printf("%s: WARNING: unable to establish shutdown hook\n", 765 sc->sc_dev.dv_xname); 766 767 /* 768 * Add a suspend hook to make sure we come back up after a 769 * resume. 770 */ 771 sc->sc_powerhook = powerhook_establish(atw_power, sc); 772 if (sc->sc_powerhook == NULL) 773 printf("%s: WARNING: unable to establish power hook\n", 774 sc->sc_dev.dv_xname); 775 776 return; 777 778 /* 779 * Free any resources we've allocated during the failed attach 780 * attempt. Do this in reverse order and fall through. 781 */ 782 fail_5: 783 for (i = 0; i < ATW_NRXDESC; i++) { 784 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 785 continue; 786 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 787 } 788 fail_4: 789 for (i = 0; i < ATW_TXQUEUELEN; i++) { 790 if (sc->sc_txsoft[i].txs_dmamap == NULL) 791 continue; 792 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 793 } 794 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 795 fail_3: 796 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 797 fail_2: 798 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 799 sizeof(struct atw_control_data)); 800 fail_1: 801 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 802 fail_0: 803 return; 804 } 805 806 /* 807 * atw_reset: 808 * 809 * Perform a soft reset on the ADM8211. 810 */ 811 void 812 atw_reset(sc) 813 struct atw_softc *sc; 814 { 815 int i; 816 817 if (ATW_IS_ENABLED(sc) == 0) 818 return; 819 820 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 821 822 for (i = 0; i < 10000; i++) { 823 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 824 break; 825 DELAY(1); 826 } 827 828 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 829 830 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 831 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 832 833 /* Turn off maximum power saving. */ 834 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 835 836 /* Recall EEPROM. */ 837 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 838 839 DELAY(10 * 1000); 840 841 /* A reset seems to affect the SRAM contents, so put them into 842 * a known state. 843 */ 844 atw_clear_sram(sc); 845 846 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 847 848 sc->sc_lost_bcn_thresh = 0; 849 } 850 851 static void 852 atw_clear_sram(sc) 853 struct atw_softc *sc; 854 { 855 #if 0 856 for (addr = 0; addr < 448; addr++) { 857 ATW_WRITE(sc, ATW_WEPCTL, 858 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 859 DELAY(1000); 860 ATW_WRITE(sc, ATW_WESK, 0); 861 DELAY(1000); /* paranoia */ 862 } 863 return; 864 #endif 865 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 866 /* XXX not for revision 0x20. */ 867 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 868 } 869 870 /* TBD atw_init 871 * 872 * set MAC based on ic->ic_bss.myaddr 873 * write WEP keys 874 * set TX rate 875 */ 876 877 /* 878 * atw_init: [ ifnet interface function ] 879 * 880 * Initialize the interface. Must be called at splnet(). 881 */ 882 int 883 atw_init(ifp) 884 struct ifnet *ifp; 885 { 886 struct atw_softc *sc = ifp->if_softc; 887 struct ieee80211com *ic = &sc->sc_ic; 888 struct atw_txsoft *txs; 889 struct atw_rxsoft *rxs; 890 u_int32_t reg; 891 int i, error = 0; 892 893 if ((error = atw_enable(sc)) != 0) 894 goto out; 895 896 /* 897 * Cancel any pending I/O. This also resets. 898 */ 899 atw_stop(ifp, 0); 900 901 /* Turn off APM??? (A binary-only driver does this.) 902 * 903 * Set Rx store-and-forward mode. 904 */ 905 reg = ATW_READ(sc, ATW_CMDR); 906 reg &= ~ATW_CMDR_APM; 907 reg &= ~ATW_CMDR_DRT_MASK; 908 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 909 910 ATW_WRITE(sc, ATW_CMDR, reg); 911 912 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 913 * 914 * XXX a binary-only driver sets a different service field than 915 * 0. why? 916 */ 917 reg = ATW_READ(sc, ATW_PLCPHD); 918 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 919 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 920 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 921 ATW_WRITE(sc, ATW_PLCPHD, reg); 922 923 /* XXX */ 924 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 925 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 926 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 927 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 928 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 929 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 930 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 931 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 932 ATW_WRITE(sc, ATW_TOFS2, reg); 933 934 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 935 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 936 937 /* XXX this resets an Intersil RF front-end? */ 938 /* TBD condition on Intersil RFType? */ 939 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 940 DELAY(10 * 1000); 941 ATW_WRITE(sc, ATW_SYNRF, 0); 942 DELAY(5 * 1000); 943 944 /* 16 TU max duration for contention-free period */ 945 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 946 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 947 948 /* XXX I guess that the Cardbus clock is 22MHz? 949 * I am assuming that the role of ATW_TOFS0_USCNT is 950 * to divide the bus clock to get a 1MHz clock---the datasheet is not 951 * very clear on this point. It says in the datasheet that it is 952 * possible for the ADM8211 to accomodate bus speeds between 22MHz 953 * and 33MHz; maybe this is the way? I see a binary-only driver write 954 * these values. These values are also the power-on default. 955 */ 956 ATW_WRITE(sc, ATW_TOFS0, 957 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 958 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 959 960 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 961 * driver. go figure. 962 */ 963 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 964 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 965 ATW_IFST_SIFS_MASK) | 966 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 967 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 968 969 ATW_WRITE(sc, ATW_IFST, reg); 970 971 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 972 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 973 974 /* Set up the MMI read/write addresses for the BBP. 975 * 976 * TBD find out the Marvel settings. 977 */ 978 switch (sc->sc_bbptype) { 979 case ATW_BBPTYPE_INTERSIL: 980 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 981 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 982 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 983 break; 984 case ATW_BBPTYPE_MARVEL: 985 break; 986 case ATW_BBPTYPE_RFMD: 987 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 988 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 989 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 990 default: 991 break; 992 } 993 994 sc->sc_wepctl = 0; 995 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 996 997 if ((error = atw_rf3000_init(sc)) != 0) 998 goto out; 999 1000 /* 1001 * Initialize the PCI Access Register. 1002 */ 1003 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1004 1005 /* 1006 * If we're allowed to do so, use Memory Read Line 1007 * and Memory Read Multiple. 1008 * 1009 * XXX Should we use Memory Write and Invalidate? 1010 */ 1011 if (sc->sc_flags & ATWF_MRL) 1012 sc->sc_busmode |= ATW_PAR_MRLE; 1013 if (sc->sc_flags & ATWF_MRM) 1014 sc->sc_busmode |= ATW_PAR_MRME; 1015 if (sc->sc_flags & ATWF_MWI) 1016 sc->sc_busmode |= ATW_PAR_MWIE; 1017 if (sc->sc_maxburst == 0) 1018 sc->sc_maxburst = 8; /* ADM8211 default */ 1019 1020 switch (sc->sc_cacheline) { 1021 default: 1022 /* Use burst length. */ 1023 break; 1024 case 8: 1025 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1026 break; 1027 case 16: 1028 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1029 break; 1030 case 32: 1031 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1032 break; 1033 } 1034 switch (sc->sc_maxburst) { 1035 case 1: 1036 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1037 break; 1038 case 2: 1039 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1040 break; 1041 case 4: 1042 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1043 break; 1044 case 8: 1045 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1046 break; 1047 case 16: 1048 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1049 break; 1050 case 32: 1051 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1052 break; 1053 default: 1054 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1055 break; 1056 } 1057 1058 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1059 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1060 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1061 1062 /* 1063 * Initialize the OPMODE register. We don't write it until 1064 * we're ready to begin the transmit and receive processes. 1065 */ 1066 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1067 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1068 1069 /* 1070 * Initialize the transmit descriptor ring. 1071 */ 1072 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1073 for (i = 0; i < ATW_NTXDESC; i++) { 1074 /* no transmit chaining */ 1075 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1076 sc->sc_txdescs[i].at_buf2 = 1077 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1078 } 1079 /* use ring mode */ 1080 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1081 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1082 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1083 sc->sc_txfree = ATW_NTXDESC; 1084 sc->sc_txnext = 0; 1085 1086 /* 1087 * Initialize the transmit job descriptors. 1088 */ 1089 SIMPLEQ_INIT(&sc->sc_txfreeq); 1090 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1091 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1092 txs = &sc->sc_txsoft[i]; 1093 txs->txs_mbuf = NULL; 1094 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1095 } 1096 1097 /* 1098 * Initialize the receive descriptor and receive job 1099 * descriptor rings. 1100 */ 1101 for (i = 0; i < ATW_NRXDESC; i++) { 1102 rxs = &sc->sc_rxsoft[i]; 1103 if (rxs->rxs_mbuf == NULL) { 1104 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1105 printf("%s: unable to allocate or map rx " 1106 "buffer %d, error = %d\n", 1107 sc->sc_dev.dv_xname, i, error); 1108 /* 1109 * XXX Should attempt to run with fewer receive 1110 * XXX buffers instead of just failing. 1111 */ 1112 atw_rxdrain(sc); 1113 goto out; 1114 } 1115 } else 1116 ATW_INIT_RXDESC(sc, i); 1117 } 1118 sc->sc_rxptr = 0; 1119 1120 /* disable all wake-up events */ 1121 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1122 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1123 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1124 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1125 1126 /* ack all wake-up events */ 1127 ATW_SET(sc, ATW_WCSR, 0); 1128 1129 /* 1130 * Initialize the interrupt mask and enable interrupts. 1131 */ 1132 /* normal interrupts */ 1133 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1134 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1135 1136 /* abnormal interrupts */ 1137 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1138 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1139 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1140 1141 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1142 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1143 1144 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1145 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1146 ATW_INTR_TRT; 1147 1148 sc->sc_linkint_mask &= sc->sc_inten; 1149 sc->sc_rxint_mask &= sc->sc_inten; 1150 sc->sc_txint_mask &= sc->sc_inten; 1151 1152 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1153 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1154 if (sc->sc_intr_ack != NULL) 1155 (*sc->sc_intr_ack)(sc); 1156 1157 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1158 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1159 1160 /* 1161 * Give the transmit and receive rings to the ADM8211. 1162 */ 1163 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1164 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1165 1166 /* common 802.11 configuration */ 1167 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1168 switch (ic->ic_opmode) { 1169 case IEEE80211_M_HOSTAP: /* XXX */ 1170 case IEEE80211_M_STA: 1171 sc->sc_opmode &= ~ATW_NAR_EA; 1172 break; 1173 case IEEE80211_M_AHDEMO: /* XXX */ 1174 case IEEE80211_M_IBSS: 1175 /* EA bit seems important for ad hoc reception. */ 1176 sc->sc_opmode |= ATW_NAR_EA; 1177 ic->ic_flags |= IEEE80211_F_IBSSON; 1178 break; 1179 case IEEE80211_M_MONITOR: /* XXX */ 1180 break; 1181 } 1182 1183 atw_start_beacon(sc, 0); 1184 1185 switch (ic->ic_opmode) { 1186 case IEEE80211_M_IBSS: 1187 case IEEE80211_M_STA: 1188 error = ieee80211_new_state(ifp, IEEE80211_S_SCAN, -1); 1189 if (error) 1190 goto out; 1191 break; 1192 case IEEE80211_M_AHDEMO: 1193 case IEEE80211_M_HOSTAP: 1194 ic->ic_bss.ni_chan = ic->ic_ibss_chan; 1195 ic->ic_bss.ni_intval = ic->ic_lintval; 1196 ic->ic_bss.ni_rssi = 0; 1197 ic->ic_bss.ni_rstamp = 0; 1198 ic->ic_state = IEEE80211_S_SCAN; /*XXX*/ 1199 1200 error = ieee80211_new_state(&ic->ic_if, IEEE80211_S_RUN, -1); 1201 if (error) 1202 goto out; 1203 break; 1204 case IEEE80211_M_MONITOR: /* XXX */ 1205 break; 1206 } 1207 1208 atw_write_ssid(sc); 1209 atw_write_sup_rates(sc); 1210 if (ic->ic_flags & IEEE80211_F_HASWEP) 1211 atw_write_wep(sc); 1212 1213 /* 1214 * Set the receive filter. This will start the transmit and 1215 * receive processes. 1216 */ 1217 atw_filter_setup(sc); 1218 1219 /* 1220 * Start the receive process. 1221 */ 1222 ATW_WRITE(sc, ATW_RDR, 0x1); 1223 1224 /* 1225 * Note that the interface is now running. 1226 */ 1227 ifp->if_flags |= IFF_RUNNING; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 1230 out: 1231 if (error) { 1232 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1233 ifp->if_timer = 0; 1234 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1235 } 1236 #ifdef ATW_DEBUG 1237 atw_print_regs(sc, "end of init"); 1238 #endif /* ATW_DEBUG */ 1239 1240 return (error); 1241 } 1242 1243 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1244 * 0: MAC control of RF3000/Si4126. 1245 * 1246 * Applies power, or selects RF front-end? Sets reset condition. 1247 * 1248 * TBD support non-RFMD BBP, non-SiLabs synth. 1249 */ 1250 static void 1251 atw_rfio_enable(struct atw_softc *sc, int enable) 1252 { 1253 if (enable) { 1254 ATW_WRITE(sc, ATW_SYNRF, 1255 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1256 DELAY(atw_rfio_enable_delay); 1257 } else { 1258 ATW_WRITE(sc, ATW_SYNRF, 0); 1259 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1260 } 1261 } 1262 1263 static int 1264 atw_tune(sc) 1265 struct atw_softc *sc; 1266 { 1267 int rc; 1268 u_int32_t reg; 1269 u_int8_t chan; 1270 struct ieee80211com *ic = &sc->sc_ic; 1271 1272 chan = ic->ic_bss.ni_chan; 1273 1274 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1275 sc->sc_cur_chan, chan)); 1276 1277 if (chan == sc->sc_cur_chan) 1278 return 0; 1279 1280 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1281 1282 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1283 (rc = atw_rf3000_tune(sc, chan)) != 0) 1284 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1285 chan); 1286 1287 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1288 ATW_WRITE(sc, ATW_CAP0, 1289 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1290 1291 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1292 1293 if (rc == 0) 1294 sc->sc_cur_chan = chan; 1295 1296 return rc; 1297 } 1298 1299 #ifdef ATW_DEBUG 1300 static void 1301 atw_si4126_print(sc) 1302 struct atw_softc *sc; 1303 { 1304 struct ifnet *ifp = &sc->sc_ic.ic_if; 1305 u_int addr, val; 1306 1307 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1308 return; 1309 1310 for (addr = 0; addr <= 8; addr++) { 1311 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1312 if (atw_si4126_read(sc, addr, &val) == 0) { 1313 printf("<unknown> (quitting print-out)\n"); 1314 break; 1315 } 1316 printf("%05x\n", val); 1317 } 1318 } 1319 #endif /* ATW_DEBUG */ 1320 1321 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1322 * 1323 * The RF/IF synthesizer produces two reference frequencies for 1324 * the RF2948B transceiver. The first frequency the RF2948B requires 1325 * is two times the so-called "intermediate frequency" (IF). Since 1326 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1327 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1328 * frequency required by the transceiver is the radio frequency 1329 * (RF). This is a superheterodyne transceiver; for f(chan) the 1330 * center frequency of the channel we are tuning, RF = f(chan) - 1331 * IF. 1332 * 1333 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1334 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1335 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1336 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1337 */ 1338 static int 1339 atw_si4126_tune(sc, chan) 1340 struct atw_softc *sc; 1341 u_int8_t chan; 1342 { 1343 int rc = 0; 1344 u_int mhz; 1345 u_int R; 1346 u_int32_t reg; 1347 u_int16_t gain; 1348 1349 #ifdef ATW_DEBUG 1350 atw_si4126_print(sc); 1351 #endif /* ATW_DEBUG */ 1352 1353 if (chan == 14) 1354 mhz = 2484; 1355 else 1356 mhz = 2412 + 5 * (chan - 1); 1357 1358 /* Tune IF to 748MHz to suit the IF LO input of the 1359 * RF2494B, which is 2 x IF. No need to set an IF divider 1360 * because an IF in 526MHz - 952MHz is allowed. 1361 * 1362 * XIN is 44.000MHz, so divide it by two to get allowable 1363 * range of 2-25MHz. SiLabs tells me that this is not 1364 * strictly necessary. 1365 */ 1366 1367 R = 44; 1368 1369 atw_rfio_enable(sc, 1); 1370 1371 /* Power-up RF, IF synthesizers. */ 1372 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1373 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1374 goto out; 1375 1376 /* If RF2 N > 2047, then set KP2 to 1. */ 1377 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1378 1379 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1380 goto out; 1381 1382 /* set LPWR, too? */ 1383 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1384 SI4126_MAIN_XINDIV2)) != 0) 1385 goto out; 1386 1387 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1388 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1389 */ 1390 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1391 goto out; 1392 1393 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1394 goto out; 1395 1396 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1397 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1398 * which has no RF1! 1399 */ 1400 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1401 goto out; 1402 1403 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1404 goto out; 1405 1406 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1407 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1408 * Now let's multiply it to mhz. So mhz - IF = N. 1409 */ 1410 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1411 goto out; 1412 1413 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1414 goto out; 1415 1416 /* wait 100us from power-up for RF, IF to settle */ 1417 DELAY(100); 1418 1419 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1420 /* XXX there is a binary driver which sends 1421 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1422 * that this enables the Si4126 by raising its PWDN#, but I 1423 * think that it actually sets the Prism RF front-end 1424 * to a special mode for channel 14. 1425 */ 1426 reg = ATW_READ(sc, ATW_GPIO); 1427 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1428 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1429 ATW_WRITE(sc, ATW_GPIO, reg); 1430 } 1431 1432 #ifdef ATW_DEBUG 1433 atw_si4126_print(sc); 1434 #endif /* ATW_DEBUG */ 1435 1436 out: 1437 atw_rfio_enable(sc, 0); 1438 1439 return rc; 1440 } 1441 1442 /* Baseline initialization of RF3000 BBP: set CCA mode, enable antenna 1443 * diversity, and write some magic. 1444 * 1445 * Call this w/ Tx/Rx suspended. 1446 */ 1447 static int 1448 atw_rf3000_init(sc) 1449 struct atw_softc *sc; 1450 { 1451 int rc = 0; 1452 1453 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1454 1455 atw_rfio_enable(sc, 1); 1456 1457 /* enable diversity */ 1458 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1459 1460 if (rc != 0) 1461 goto out; 1462 1463 /* sensible setting from a binary-only driver */ 1464 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1465 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1466 1467 if (rc != 0) 1468 goto out; 1469 1470 /* magic from a binary-only driver */ 1471 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1472 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1473 1474 if (rc != 0) 1475 goto out; 1476 1477 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1478 1479 if (rc != 0) 1480 goto out; 1481 1482 /* magic derived from binary-only driver */ 1483 rc = atw_rf3000_write(sc, RF3000_MAGIC0, RF3000_MAGIC0_VAL); 1484 1485 if (rc != 0) 1486 goto out; 1487 1488 rc = atw_rf3000_write(sc, RF3000_MAGIC1, RF3000_MAGIC1_VAL); 1489 1490 if (rc != 0) 1491 goto out; 1492 1493 /* CCA is acquisition sensitive */ 1494 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1495 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1496 1497 if (rc != 0) 1498 goto out; 1499 1500 out: 1501 atw_rfio_enable(sc, 0); 1502 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1503 return rc; 1504 } 1505 1506 #ifdef ATW_DEBUG 1507 static void 1508 atw_rf3000_print(sc) 1509 struct atw_softc *sc; 1510 { 1511 struct ifnet *ifp = &sc->sc_ic.ic_if; 1512 u_int addr, val; 1513 1514 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1515 return; 1516 1517 for (addr = 0x01; addr <= 0x15; addr++) { 1518 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1519 if (atw_rf3000_read(sc, addr, &val) != 0) { 1520 printf("<unknown> (quitting print-out)\n"); 1521 break; 1522 } 1523 printf("%08x\n", val); 1524 } 1525 } 1526 #endif /* ATW_DEBUG */ 1527 1528 /* Set the power settings on the BBP for channel `chan'. */ 1529 static int 1530 atw_rf3000_tune(sc, chan) 1531 struct atw_softc *sc; 1532 u_int8_t chan; 1533 { 1534 int rc = 0; 1535 u_int32_t reg; 1536 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1537 1538 atw_rfio_enable(sc, 1); 1539 1540 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1541 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1542 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1543 1544 /* odd channels: LSB, even channels: MSB */ 1545 if (chan % 2 == 1) { 1546 txpower &= 0xFF; 1547 lpf_cutoff &= 0xFF; 1548 lna_gs_thresh &= 0xFF; 1549 } else { 1550 txpower >>= 8; 1551 lpf_cutoff >>= 8; 1552 lna_gs_thresh >>= 8; 1553 } 1554 1555 #ifdef ATW_DEBUG 1556 atw_rf3000_print(sc); 1557 #endif /* ATW_DEBUG */ 1558 1559 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1560 "lna_gs_thresh %02x\n", 1561 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1562 1563 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1564 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1565 goto out; 1566 1567 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1568 goto out; 1569 1570 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1571 goto out; 1572 1573 /* from a binary-only driver. */ 1574 reg = ATW_READ(sc, ATW_PLCPHD); 1575 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1576 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1577 ATW_WRITE(sc, ATW_PLCPHD, reg); 1578 1579 #ifdef ATW_DEBUG 1580 atw_rf3000_print(sc); 1581 #endif /* ATW_DEBUG */ 1582 1583 out: 1584 atw_rfio_enable(sc, 0); 1585 1586 return rc; 1587 } 1588 1589 /* Write a register on the RF3000 baseband processor using the 1590 * registers provided by the ADM8211 for this purpose. 1591 * 1592 * Return 0 on success. 1593 */ 1594 static int 1595 atw_rf3000_write(sc, addr, val) 1596 struct atw_softc *sc; 1597 u_int addr, val; 1598 { 1599 u_int32_t reg; 1600 int i; 1601 1602 for (i = 1000; --i >= 0; ) { 1603 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1604 break; 1605 DELAY(100); 1606 } 1607 1608 if (i < 0) { 1609 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1610 return ETIMEDOUT; 1611 } 1612 1613 reg = sc->sc_bbpctl_wr | 1614 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1615 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1616 1617 ATW_WRITE(sc, ATW_BBPCTL, reg); 1618 1619 for (i = 1000; --i >= 0; ) { 1620 DELAY(100); 1621 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1622 break; 1623 } 1624 1625 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1626 1627 if (i < 0) { 1628 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1629 return ETIMEDOUT; 1630 } 1631 return 0; 1632 } 1633 1634 /* Read a register on the RF3000 baseband processor using the registers 1635 * the ADM8211 provides for this purpose. 1636 * 1637 * The 7-bit register address is addr. Record the 8-bit data in the register 1638 * in *val. 1639 * 1640 * Return 0 on success. 1641 * 1642 * XXX This does not seem to work. The ADM8211 must require more or 1643 * different magic to read the chip than to write it. Possibly some 1644 * of the magic I have derived from a binary-only driver concerns 1645 * the "chip address" (see the RF3000 manual). 1646 */ 1647 #ifdef ATW_DEBUG 1648 static int 1649 atw_rf3000_read(sc, addr, val) 1650 struct atw_softc *sc; 1651 u_int addr, *val; 1652 { 1653 u_int32_t reg; 1654 int i; 1655 1656 for (i = 1000; --i >= 0; ) { 1657 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1658 break; 1659 DELAY(100); 1660 } 1661 1662 if (i < 0) { 1663 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1664 sc->sc_dev.dv_xname); 1665 return ETIMEDOUT; 1666 } 1667 1668 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1669 1670 ATW_WRITE(sc, ATW_BBPCTL, reg); 1671 1672 for (i = 1000; --i >= 0; ) { 1673 DELAY(100); 1674 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1675 break; 1676 } 1677 1678 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1679 1680 if (i < 0) { 1681 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1682 sc->sc_dev.dv_xname, reg); 1683 return ETIMEDOUT; 1684 } 1685 if (val != NULL) 1686 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1687 return 0; 1688 } 1689 #endif /* ATW_DEBUG */ 1690 1691 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1692 * provided by the ADM8211 for that purpose. 1693 * 1694 * val is 18 bits of data, and val is the 4-bit address of the register. 1695 * 1696 * Return 0 on success. 1697 */ 1698 static int 1699 atw_si4126_write(sc, addr, val) 1700 struct atw_softc *sc; 1701 u_int addr, val; 1702 { 1703 u_int32_t reg; 1704 int i; 1705 1706 for (i = 1000; --i >= 0; ) { 1707 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1708 break; 1709 DELAY(100); 1710 } 1711 1712 if (i < 0) { 1713 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1714 sc->sc_dev.dv_xname); 1715 return ETIMEDOUT; 1716 } 1717 1718 reg = sc->sc_synctl_wr | 1719 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1720 1721 ATW_WRITE(sc, ATW_SYNCTL, reg); 1722 1723 for (i = 1000; --i >= 0; ) { 1724 DELAY(100); 1725 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1726 break; 1727 } 1728 1729 /* restore to acceptable starting condition */ 1730 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1731 1732 if (i < 0) { 1733 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1734 sc->sc_dev.dv_xname, reg); 1735 return ETIMEDOUT; 1736 } 1737 return 0; 1738 } 1739 1740 /* Read 18-bit data from the 4-bit address addr in Si4126 1741 * RF synthesizer and write the data to *val. Return 0 on success. 1742 * 1743 * XXX This does not seem to work. The ADM8211 must require more or 1744 * different magic to read the chip than to write it. 1745 */ 1746 #ifdef ATW_DEBUG 1747 static int 1748 atw_si4126_read(sc, addr, val) 1749 struct atw_softc *sc; 1750 u_int addr; 1751 u_int *val; 1752 { 1753 u_int32_t reg; 1754 int i; 1755 1756 for (i = 1000; --i >= 0; ) { 1757 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1758 break; 1759 DELAY(100); 1760 } 1761 1762 if (i < 0) { 1763 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1764 sc->sc_dev.dv_xname); 1765 return ETIMEDOUT; 1766 } 1767 1768 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1769 1770 ATW_WRITE(sc, ATW_SYNCTL, reg); 1771 1772 for (i = 1000; --i >= 0; ) { 1773 DELAY(100); 1774 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1775 break; 1776 } 1777 1778 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1779 1780 if (i < 0) { 1781 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1782 sc->sc_dev.dv_xname, reg); 1783 return ETIMEDOUT; 1784 } 1785 if (val != NULL) 1786 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1787 ATW_SYNCTL_DATA_MASK); 1788 return 0; 1789 } 1790 #endif /* ATW_DEBUG */ 1791 1792 /* XXX is the endianness correct? test. */ 1793 #define atw_calchash(addr) \ 1794 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1795 1796 /* 1797 * atw_filter_setup: 1798 * 1799 * Set the ADM8211's receive filter. 1800 */ 1801 static void 1802 atw_filter_setup(sc) 1803 struct atw_softc *sc; 1804 { 1805 struct ieee80211com *ic = &sc->sc_ic; 1806 struct ethercom *ec = &ic->ic_ec; 1807 struct ifnet *ifp = &sc->sc_ic.ic_if; 1808 int hash; 1809 u_int32_t hashes[2] = { 0, 0 }; 1810 struct ether_multi *enm; 1811 struct ether_multistep step; 1812 1813 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1814 sc->sc_dev.dv_xname, sc->sc_flags)); 1815 1816 /* 1817 * If we're running, idle the receive engine. If we're NOT running, 1818 * we're being called from atw_init(), and our writing ATW_NAR will 1819 * start the transmit and receive processes in motion. 1820 */ 1821 if (ifp->if_flags & IFF_RUNNING) 1822 atw_idle(sc, ATW_NAR_SR); 1823 1824 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1825 1826 ifp->if_flags &= ~IFF_ALLMULTI; 1827 1828 if (ifp->if_flags & IFF_PROMISC) { 1829 sc->sc_opmode |= ATW_NAR_PR; 1830 allmulti: 1831 ifp->if_flags |= IFF_ALLMULTI; 1832 goto setit; 1833 } 1834 1835 /* 1836 * Program the 64-bit multicast hash filter. 1837 */ 1838 ETHER_FIRST_MULTI(step, ec, enm); 1839 while (enm != NULL) { 1840 /* XXX */ 1841 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1842 ETHER_ADDR_LEN) != 0) 1843 goto allmulti; 1844 1845 hash = atw_calchash(enm->enm_addrlo); 1846 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1847 ETHER_NEXT_MULTI(step, enm); 1848 } 1849 1850 if (ifp->if_flags & IFF_BROADCAST) { 1851 hash = atw_calchash(etherbroadcastaddr); 1852 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1853 } 1854 1855 /* all bits set => hash is useless */ 1856 if (~(hashes[0] & hashes[1]) == 0) 1857 goto allmulti; 1858 1859 setit: 1860 if (ifp->if_flags & IFF_ALLMULTI) 1861 sc->sc_opmode |= ATW_NAR_MM; 1862 1863 /* XXX in scan mode, do not filter packets. maybe this is 1864 * unnecessary. 1865 */ 1866 if (ic->ic_state == IEEE80211_S_SCAN) 1867 sc->sc_opmode |= ATW_NAR_PR; 1868 1869 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1870 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1871 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1872 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1873 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1874 1875 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1876 } 1877 1878 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1879 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1880 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1881 * no beacon with the preferred BSSID and SSID in the number of 1882 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1883 */ 1884 static void 1885 atw_write_bssid(sc) 1886 struct atw_softc *sc; 1887 { 1888 struct ieee80211com *ic = &sc->sc_ic; 1889 u_int8_t *bssid; 1890 1891 bssid = ic->ic_bss.ni_bssid; 1892 1893 ATW_WRITE(sc, ATW_ABDA1, 1894 (ATW_READ(sc, ATW_ABDA1) & 1895 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1896 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1897 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1898 1899 ATW_WRITE(sc, ATW_BSSID0, 1900 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1901 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1902 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1903 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1904 1905 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1906 ether_sprintf(sc->sc_bssid))); 1907 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1908 1909 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1910 } 1911 1912 /* Tell the ADM8211 how many beacon intervals must pass without 1913 * receiving a beacon with the preferred BSSID & SSID set by 1914 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1915 * raised. 1916 */ 1917 static void 1918 atw_write_bcn_thresh(sc) 1919 struct atw_softc *sc; 1920 { 1921 struct ieee80211com *ic = &sc->sc_ic; 1922 int lost_bcn_thresh; 1923 1924 /* Lose link after one second or 7 beacons, whichever comes 1925 * first, but do not lose link before 2 beacons are lost. 1926 * 1927 * In host AP mode, set the lost-beacon threshold to 0. 1928 */ 1929 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1930 lost_bcn_thresh = 0; 1931 else 1932 lost_bcn_thresh = MAX(2, 1933 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss.ni_intval), 7)); 1934 1935 /* XXX resets wake-up status bits */ 1936 ATW_WRITE(sc, ATW_WCSR, 1937 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1938 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1939 1940 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1941 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1942 1943 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1944 1945 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1946 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1947 } 1948 1949 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1950 * 16-bit word. 1951 */ 1952 static void 1953 atw_write_sram(sc, ofs, buf, buflen) 1954 struct atw_softc *sc; 1955 u_int ofs; 1956 u_int8_t *buf; 1957 u_int buflen; 1958 { 1959 u_int i; 1960 u_int8_t *ptr; 1961 1962 memcpy(&sc->sc_sram[ofs], buf, buflen); 1963 1964 if (ofs % 2 != 0) { 1965 ofs--; 1966 buflen++; 1967 } 1968 1969 if (buflen % 2 != 0) 1970 buflen++; 1971 1972 assert(buflen + ofs <= ATW_SRAM_SIZE); 1973 1974 ptr = &sc->sc_sram[ofs]; 1975 1976 for (i = 0; i < buflen; i += 2) { 1977 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1978 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1979 DELAY(atw_writewep_delay); 1980 1981 ATW_WRITE(sc, ATW_WESK, 1982 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1983 DELAY(atw_writewep_delay); 1984 } 1985 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1986 1987 if (sc->sc_if.if_flags & IFF_DEBUG) { 1988 int n_octets = 0; 1989 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1990 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1991 for (i = 0; i < buflen; i++) { 1992 printf(" %02x", ptr[i]); 1993 if (++n_octets % 24 == 0) 1994 printf("\n"); 1995 } 1996 if (n_octets % 24 != 0) 1997 printf("\n"); 1998 } 1999 } 2000 2001 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2002 static void 2003 atw_write_wep(sc) 2004 struct atw_softc *sc; 2005 { 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2008 u_int8_t buf[IEEE80211_WEP_NKID] 2009 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2010 u_int32_t reg; 2011 int i; 2012 2013 sc->sc_wepctl = 0; 2014 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2015 2016 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2017 return; 2018 2019 memset(&buf[0][0], 0, sizeof(buf)); 2020 2021 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2022 if (ic->ic_nw_keys[i].wk_len > 5) { 2023 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2024 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2025 buf[i][1] = ATW_WEP_ENABLED; 2026 } else { 2027 buf[i][1] = 0; 2028 continue; 2029 } 2030 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2031 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2032 ic->ic_nw_keys[i].wk_len - 1); 2033 } 2034 2035 reg = ATW_READ(sc, ATW_MACTEST); 2036 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2037 reg &= ~ATW_MACTEST_KEYID_MASK; 2038 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2039 ATW_WRITE(sc, ATW_MACTEST, reg); 2040 2041 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2042 * throughout.) 2043 */ 2044 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2045 if (sc->sc_if.if_flags & IFF_LINK2) 2046 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2047 2048 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2049 sizeof(buf)); 2050 } 2051 2052 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2053 2054 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2055 * of IBSSs with like SSID/channel but different BSSID. It joins the 2056 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2057 * convention. Possibly the ADMtek chip does this for us; I will have 2058 * to test to find out. 2059 * 2060 * XXX we should add the duration field of the received beacon to 2061 * the TSF time it contains before comparing it with the ADM8211's 2062 * TSF. 2063 */ 2064 static void 2065 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, int rssi, 2066 u_int32_t rstamp) 2067 { 2068 struct atw_softc *sc; 2069 struct ieee80211_frame *wh; 2070 struct ieee80211_node *ni, tmp_ni; 2071 u_int64_t tsft, bcn_tsft; 2072 u_int32_t tsftl, tsfth; 2073 int do_print = 0; 2074 void *p; 2075 2076 sc = (struct atw_softc*)ic->ic_if.if_softc; 2077 2078 if (ic->ic_if.if_flags & IFF_DEBUG) 2079 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2080 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2081 2082 wh = mtod(m0, struct ieee80211_frame *); 2083 2084 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 2085 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2086 (*sc->sc_recv_prresp)(ic, m0, rssi, rstamp); 2087 else 2088 (*sc->sc_recv_beacon)(ic, m0, rssi, rstamp); 2089 2090 if (ic->ic_state != IEEE80211_S_RUN) { 2091 if (do_print) 2092 printf("%s: atw_recv_beacon: not running\n", 2093 sc->sc_dev.dv_xname); 2094 return; 2095 } 2096 2097 if ((ni = ieee80211_find_node(ic, wh->i_addr2)) == NULL) { 2098 if (do_print) 2099 printf("%s: atw_recv_beacon: no node %s\n", 2100 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2101 return; 2102 } 2103 2104 if (ieee80211_match_bss(ic, ni) != 0) { 2105 if (do_print) 2106 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2107 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2108 return; 2109 } 2110 2111 if (memcmp(ni->ni_bssid, ic->ic_bss.ni_bssid, IEEE80211_ADDR_LEN) == 0) 2112 return; 2113 2114 if (do_print) 2115 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2116 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2117 2118 if (sc->sc_opmode != IEEE80211_M_IBSS) 2119 return; 2120 2121 /* If we read TSFTL right before rollover, we read a TSF timer 2122 * that is too high rather than too low. This prevents a spurious 2123 * synchronization down the line, however, our IBSS could suffer 2124 * from a creeping TSF.... 2125 */ 2126 tsftl = ATW_READ(sc, ATW_TSFTL); 2127 tsfth = ATW_READ(sc, ATW_TSFTH); 2128 2129 tsft = (u_int64_t)tsfth << 32 | tsftl; 2130 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2131 2132 if (do_print) 2133 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2134 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2135 2136 /* we are faster, let the other guy catch up */ 2137 if (bcn_tsft < tsft) 2138 return; 2139 2140 if (do_print) 2141 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2142 ether_sprintf(wh->i_addr2)); 2143 2144 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2145 2146 #if 0 2147 atw_tsf(sc); 2148 #endif 2149 2150 tmp_ni = *ni; 2151 /* negotiate rates with new IBSS */ 2152 ieee80211_fix_rate(ic, &tmp_ni, IEEE80211_F_DOFRATE | 2153 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2154 if (tmp_ni.ni_nrate == 0) { 2155 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2156 ether_sprintf(ni->ni_bssid)); 2157 return; 2158 } 2159 2160 if (do_print) { 2161 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2162 ether_sprintf(ic->ic_bss.ni_bssid)); 2163 printf("%s ", ether_sprintf(ni->ni_bssid)); 2164 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2165 } 2166 2167 p = ic->ic_bss.ni_private; 2168 ic->ic_bss = *ni; 2169 ic->ic_bss.ni_private = p; 2170 if (p != NULL && ic->ic_node_privlen) 2171 memcpy(p, ni->ni_private, ic->ic_node_privlen); 2172 2173 atw_write_bssid(sc); 2174 if (atw_tune(sc) != 0) 2175 printf("%s: could not sync channel\n", sc->sc_dev.dv_xname); 2176 atw_write_bcn_thresh(sc); 2177 atw_start_beacon(sc, 1); 2178 } 2179 2180 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2181 * In ad hoc mode, the SSID is written to the beacons sent by the 2182 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2183 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2184 * indications. 2185 */ 2186 static void 2187 atw_write_ssid(sc) 2188 struct atw_softc *sc; 2189 { 2190 struct ieee80211com *ic = &sc->sc_ic; 2191 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2192 u_int8_t buf[1 /* length */ + IEEE80211_NWID_LEN + 2193 1 /* for a round number */]; 2194 2195 memset(buf, 0, sizeof(buf)); 2196 buf[0] = ic->ic_bss.ni_esslen; 2197 memcpy(&buf[1], ic->ic_bss.ni_essid, ic->ic_bss.ni_esslen); 2198 2199 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2200 } 2201 2202 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2203 * In ad hoc mode, the supported rates are written to beacons sent by the 2204 * ADM8211. 2205 */ 2206 static void 2207 atw_write_sup_rates(sc) 2208 struct atw_softc *sc; 2209 { 2210 struct ieee80211com *ic = &sc->sc_ic; 2211 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2212 * supported rates 2213 */ 2214 u_int8_t buf[1 /* length */ + IEEE80211_RATE_SIZE + 2215 1 /* for a round number */]; 2216 2217 memset(buf, 0, sizeof(buf)); 2218 2219 buf[0] = ic->ic_bss.ni_nrate; 2220 2221 memcpy(&buf[1], ic->ic_bss.ni_rates, ic->ic_bss.ni_nrate); 2222 2223 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2224 } 2225 2226 /* Start/stop sending beacons. */ 2227 void 2228 atw_start_beacon(struct atw_softc *sc, int start) 2229 { 2230 struct ieee80211com *ic = &sc->sc_ic; 2231 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2232 2233 if (ATW_IS_ENABLED(sc) == 0) 2234 return; 2235 2236 len = capinfo = 0; 2237 2238 /* start beacons */ 2239 len = sizeof(struct ieee80211_frame) + 2240 8 /* timestamp */ + 2 /* beacon interval */ + 2241 2 /* capability info */ + 2242 2 + ic->ic_bss.ni_esslen /* SSID element */ + 2243 2 + ic->ic_bss.ni_nrate /* rates element */ + 2244 3 /* DS parameters */ + 2245 IEEE80211_CRC_LEN; 2246 2247 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2248 2249 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2250 2251 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2252 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2253 2254 if (!start) 2255 return; 2256 2257 /* TBD use ni_capinfo */ 2258 2259 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2260 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2261 if (ic->ic_flags & IEEE80211_F_WEPON) 2262 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2263 2264 switch (ic->ic_opmode) { 2265 case IEEE80211_M_IBSS: 2266 len += 4; /* IBSS parameters */ 2267 capinfo |= IEEE80211_CAPINFO_IBSS; 2268 break; 2269 case IEEE80211_M_HOSTAP: 2270 /* XXX 6-byte minimum TIM */ 2271 len += atw_beacon_len_adjust; 2272 capinfo |= IEEE80211_CAPINFO_ESS; 2273 break; 2274 default: 2275 return; 2276 } 2277 2278 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2279 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2280 2281 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2282 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2283 2284 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2285 sc->sc_dev.dv_xname, reg_bcnt)); 2286 2287 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2288 sc->sc_dev.dv_xname, reg_cap1)); 2289 } 2290 2291 /* First beacon was sent at time 0 microseconds, current time is 2292 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2293 * microseconds. Return the expected time in microseconds for the 2294 * beacon after next. 2295 */ 2296 static __inline u_int64_t 2297 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2298 { 2299 return tsft + (tbtt - tsft % tbtt); 2300 } 2301 2302 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2303 * the ieee80211com. 2304 * 2305 * Predict the next target beacon transmission time (TBTT) and 2306 * write it to the ADM8211. 2307 */ 2308 static void 2309 atw_tsf(struct atw_softc *sc) 2310 { 2311 #define TBTTOFS 20 /* TU */ 2312 2313 struct ieee80211com *ic = &sc->sc_ic; 2314 u_int64_t tsft, tbtt; 2315 2316 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2317 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2318 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2319 tsft = ATW_READ(sc, ATW_TSFTH); 2320 tsft <<= 32; 2321 tsft |= ATW_READ(sc, ATW_TSFTL); 2322 *(u_int64_t*)&ic->ic_bss.ni_tstamp[0] = htole64(tsft); 2323 } else 2324 tsft = le64toh(*(u_int64_t*)&ic->ic_bss.ni_tstamp[0]); 2325 2326 tbtt = atw_predict_beacon(tsft, 2327 ic->ic_bss.ni_intval * IEEE80211_DUR_TU); 2328 2329 /* skip one more beacon so that the TBTT cannot pass before 2330 * we've programmed it, and also so that we can subtract a 2331 * few TU so that we wake a little before TBTT. 2332 */ 2333 tbtt += ic->ic_bss.ni_intval * IEEE80211_DUR_TU; 2334 2335 /* wake up a little early */ 2336 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2337 2338 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2339 sc->sc_dev.dv_xname, tsft, tbtt)); 2340 2341 ATW_WRITE(sc, ATW_TOFS1, 2342 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2343 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2344 LSHIFT( 2345 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2346 ATW_TOFS1_TBTTPRE_MASK)); 2347 #undef TBTTOFS 2348 } 2349 2350 /* Synchronize the hardware state with the software state. */ 2351 static int 2352 atw_newstate(void *arg, enum ieee80211_state nstate) 2353 { 2354 enum ieee80211_state ostate; 2355 int error, scan_timo, start_beacon = 0; 2356 struct atw_softc *sc = arg; 2357 struct ieee80211com *ic = &sc->sc_ic; 2358 2359 ostate = ic->ic_state; 2360 2361 switch (nstate) { 2362 case IEEE80211_S_INIT: 2363 break; 2364 case IEEE80211_S_SCAN: 2365 if (ic->ic_flags & IEEE80211_F_ASCAN) 2366 scan_timo = 100 + 54 /* overhead */; 2367 else 2368 scan_timo = 200 + 54 /* overhead */; 2369 2370 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2371 atw_write_bssid(sc); 2372 2373 callout_reset(&sc->sc_scan_timer, scan_timo * hz / 1000, 2374 (void(*)(void*))ieee80211_next_scan, (void*)&ic->ic_if); 2375 2376 error = atw_tune(sc); 2377 if (error != 0) 2378 return error; 2379 2380 break; 2381 case IEEE80211_S_RUN: 2382 if (ic->ic_opmode == IEEE80211_M_STA) 2383 break; 2384 /*FALLTHROUGH*/ 2385 case IEEE80211_S_AUTH: 2386 atw_write_bssid(sc); 2387 atw_write_bcn_thresh(sc); 2388 atw_write_ssid(sc); 2389 atw_write_sup_rates(sc); 2390 2391 switch (ic->ic_opmode) { 2392 case IEEE80211_M_HOSTAP: 2393 case IEEE80211_M_IBSS: 2394 start_beacon = 1; 2395 /* FALL THROUGH */ 2396 case IEEE80211_M_STA: 2397 /* set listen interval 2398 * XXX do software units agree w/ hardware? 2399 */ 2400 ATW_WRITE(sc, ATW_BPLI, 2401 LSHIFT(ic->ic_bss.ni_intval, ATW_BPLI_BP_MASK) | 2402 LSHIFT(ic->ic_lintval / ic->ic_bss.ni_intval, 2403 ATW_BPLI_LI_MASK)); 2404 2405 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2406 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2407 2408 atw_tsf(sc); 2409 break; 2410 2411 case IEEE80211_M_AHDEMO: 2412 case IEEE80211_M_MONITOR: 2413 /* TBD */ 2414 break; 2415 } 2416 error = atw_tune(sc); 2417 if (error != 0) 2418 return error; 2419 2420 break; 2421 default: 2422 break; 2423 } 2424 2425 switch (ostate) { 2426 case IEEE80211_S_SCAN: 2427 if (nstate != IEEE80211_S_SCAN) 2428 callout_stop(&sc->sc_scan_timer); 2429 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2430 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2431 break; 2432 case IEEE80211_S_INIT: 2433 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2434 break; 2435 default: 2436 break; 2437 } 2438 2439 atw_start_beacon(sc, start_beacon); 2440 2441 return 0; 2442 } 2443 2444 /* 2445 * atw_add_rxbuf: 2446 * 2447 * Add a receive buffer to the indicated descriptor. 2448 */ 2449 int 2450 atw_add_rxbuf(sc, idx) 2451 struct atw_softc *sc; 2452 int idx; 2453 { 2454 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2455 struct mbuf *m; 2456 int error; 2457 2458 MGETHDR(m, M_DONTWAIT, MT_DATA); 2459 if (m == NULL) 2460 return (ENOBUFS); 2461 2462 MCLGET(m, M_DONTWAIT); 2463 if ((m->m_flags & M_EXT) == 0) { 2464 m_freem(m); 2465 return (ENOBUFS); 2466 } 2467 2468 if (rxs->rxs_mbuf != NULL) 2469 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2470 2471 rxs->rxs_mbuf = m; 2472 2473 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2474 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2475 BUS_DMA_READ|BUS_DMA_NOWAIT); 2476 if (error) { 2477 printf("%s: can't load rx DMA map %d, error = %d\n", 2478 sc->sc_dev.dv_xname, idx, error); 2479 panic("atw_add_rxbuf"); /* XXX */ 2480 } 2481 2482 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2483 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2484 2485 ATW_INIT_RXDESC(sc, idx); 2486 2487 return (0); 2488 } 2489 2490 /* 2491 * atw_stop: [ ifnet interface function ] 2492 * 2493 * Stop transmission on the interface. 2494 */ 2495 void 2496 atw_stop(ifp, disable) 2497 struct ifnet *ifp; 2498 int disable; 2499 { 2500 struct atw_softc *sc = ifp->if_softc; 2501 struct atw_txsoft *txs; 2502 2503 ieee80211_new_state(ifp, IEEE80211_S_INIT, -1); 2504 2505 /* Disable interrupts. */ 2506 ATW_WRITE(sc, ATW_IER, 0); 2507 2508 /* Stop the transmit and receive processes. */ 2509 sc->sc_opmode = 0; 2510 ATW_WRITE(sc, ATW_NAR, 0); 2511 ATW_WRITE(sc, ATW_TDBD, 0); 2512 ATW_WRITE(sc, ATW_TDBP, 0); 2513 ATW_WRITE(sc, ATW_RDB, 0); 2514 2515 /* 2516 * Release any queued transmit buffers. 2517 */ 2518 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2519 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2520 if (txs->txs_mbuf != NULL) { 2521 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2522 m_freem(txs->txs_mbuf); 2523 txs->txs_mbuf = NULL; 2524 } 2525 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2526 } 2527 2528 if (disable) { 2529 atw_rxdrain(sc); 2530 atw_disable(sc); 2531 } 2532 2533 /* 2534 * Mark the interface down and cancel the watchdog timer. 2535 */ 2536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2537 ifp->if_timer = 0; 2538 2539 /* XXX */ 2540 atw_reset(sc); 2541 } 2542 2543 /* 2544 * atw_rxdrain: 2545 * 2546 * Drain the receive queue. 2547 */ 2548 void 2549 atw_rxdrain(sc) 2550 struct atw_softc *sc; 2551 { 2552 struct atw_rxsoft *rxs; 2553 int i; 2554 2555 for (i = 0; i < ATW_NRXDESC; i++) { 2556 rxs = &sc->sc_rxsoft[i]; 2557 if (rxs->rxs_mbuf == NULL) 2558 continue; 2559 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2560 m_freem(rxs->rxs_mbuf); 2561 rxs->rxs_mbuf = NULL; 2562 } 2563 } 2564 2565 /* 2566 * atw_detach: 2567 * 2568 * Detach an ADM8211 interface. 2569 */ 2570 int 2571 atw_detach(sc) 2572 struct atw_softc *sc; 2573 { 2574 struct ifnet *ifp = &sc->sc_ic.ic_if; 2575 struct atw_rxsoft *rxs; 2576 struct atw_txsoft *txs; 2577 int i; 2578 2579 /* 2580 * Succeed now if there isn't any work to do. 2581 */ 2582 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2583 return (0); 2584 2585 ieee80211_ifdetach(ifp); 2586 if_detach(ifp); 2587 2588 for (i = 0; i < ATW_NRXDESC; i++) { 2589 rxs = &sc->sc_rxsoft[i]; 2590 if (rxs->rxs_mbuf != NULL) { 2591 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2592 m_freem(rxs->rxs_mbuf); 2593 rxs->rxs_mbuf = NULL; 2594 } 2595 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2596 } 2597 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2598 txs = &sc->sc_txsoft[i]; 2599 if (txs->txs_mbuf != NULL) { 2600 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2601 m_freem(txs->txs_mbuf); 2602 txs->txs_mbuf = NULL; 2603 } 2604 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2605 } 2606 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2607 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2608 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2609 sizeof(struct atw_control_data)); 2610 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2611 2612 shutdownhook_disestablish(sc->sc_sdhook); 2613 powerhook_disestablish(sc->sc_powerhook); 2614 2615 if (sc->sc_srom) 2616 free(sc->sc_srom, M_DEVBUF); 2617 2618 return (0); 2619 } 2620 2621 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2622 void 2623 atw_shutdown(arg) 2624 void *arg; 2625 { 2626 struct atw_softc *sc = arg; 2627 2628 atw_stop(&sc->sc_ic.ic_if, 1); 2629 } 2630 2631 int 2632 atw_intr(arg) 2633 void *arg; 2634 { 2635 struct atw_softc *sc = arg; 2636 struct ifnet *ifp = &sc->sc_ic.ic_if; 2637 u_int32_t status, rxstatus, txstatus, linkstatus; 2638 int handled = 0, txthresh; 2639 2640 #ifdef DEBUG 2641 if (ATW_IS_ENABLED(sc) == 0) 2642 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2643 #endif 2644 2645 /* 2646 * If the interface isn't running, the interrupt couldn't 2647 * possibly have come from us. 2648 */ 2649 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2650 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2651 return (0); 2652 2653 for (;;) { 2654 status = ATW_READ(sc, ATW_STSR); 2655 2656 if (status) 2657 ATW_WRITE(sc, ATW_STSR, status); 2658 2659 if (sc->sc_intr_ack != NULL) 2660 (*sc->sc_intr_ack)(sc); 2661 2662 #ifdef ATW_DEBUG 2663 #define PRINTINTR(flag) do { \ 2664 if ((status & flag) != 0) { \ 2665 printf("%s" #flag, delim); \ 2666 delim = ","; \ 2667 } \ 2668 } while (0) 2669 2670 if (atw_debug > 1 && status) { 2671 const char *delim = "<"; 2672 2673 printf("%s: reg[STSR] = %x", 2674 sc->sc_dev.dv_xname, status); 2675 2676 PRINTINTR(ATW_INTR_FBE); 2677 PRINTINTR(ATW_INTR_LINKOFF); 2678 PRINTINTR(ATW_INTR_LINKON); 2679 PRINTINTR(ATW_INTR_RCI); 2680 PRINTINTR(ATW_INTR_RDU); 2681 PRINTINTR(ATW_INTR_RPS); 2682 PRINTINTR(ATW_INTR_TCI); 2683 PRINTINTR(ATW_INTR_TDU); 2684 PRINTINTR(ATW_INTR_TLT); 2685 PRINTINTR(ATW_INTR_TPS); 2686 PRINTINTR(ATW_INTR_TRT); 2687 PRINTINTR(ATW_INTR_TUF); 2688 PRINTINTR(ATW_INTR_BCNTC); 2689 PRINTINTR(ATW_INTR_ATIME); 2690 PRINTINTR(ATW_INTR_TBTT); 2691 PRINTINTR(ATW_INTR_TSCZ); 2692 PRINTINTR(ATW_INTR_TSFTF); 2693 printf(">\n"); 2694 } 2695 #undef PRINTINTR 2696 #endif /* ATW_DEBUG */ 2697 2698 if ((status & sc->sc_inten) == 0) 2699 break; 2700 2701 handled = 1; 2702 2703 rxstatus = status & sc->sc_rxint_mask; 2704 txstatus = status & sc->sc_txint_mask; 2705 linkstatus = status & sc->sc_linkint_mask; 2706 2707 if (linkstatus) { 2708 atw_linkintr(sc, linkstatus); 2709 } 2710 2711 if (rxstatus) { 2712 /* Grab any new packets. */ 2713 atw_rxintr(sc); 2714 2715 if (rxstatus & ATW_INTR_RDU) { 2716 printf("%s: receive ring overrun\n", 2717 sc->sc_dev.dv_xname); 2718 /* Get the receive process going again. */ 2719 ATW_WRITE(sc, ATW_RDR, 0x1); 2720 break; 2721 } 2722 } 2723 2724 if (txstatus) { 2725 /* Sweep up transmit descriptors. */ 2726 atw_txintr(sc); 2727 2728 if (txstatus & ATW_INTR_TLT) 2729 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2730 sc->sc_dev.dv_xname)); 2731 2732 if (txstatus & ATW_INTR_TRT) 2733 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2734 sc->sc_dev.dv_xname)); 2735 2736 /* If Tx under-run, increase our transmit threshold 2737 * if another is available. 2738 */ 2739 txthresh = sc->sc_txthresh + 1; 2740 if ((txstatus & ATW_INTR_TUF) && 2741 sc->sc_txth[txthresh].txth_name != NULL) { 2742 /* Idle the transmit process. */ 2743 atw_idle(sc, ATW_NAR_ST); 2744 2745 sc->sc_txthresh = txthresh; 2746 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2747 sc->sc_opmode |= 2748 sc->sc_txth[txthresh].txth_opmode; 2749 printf("%s: transmit underrun; new " 2750 "threshold: %s\n", sc->sc_dev.dv_xname, 2751 sc->sc_txth[txthresh].txth_name); 2752 2753 /* Set the new threshold and restart 2754 * the transmit process. 2755 */ 2756 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2757 /* XXX Log every Nth underrun from 2758 * XXX now on? 2759 */ 2760 } 2761 } 2762 2763 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2764 if (status & ATW_INTR_TPS) 2765 printf("%s: transmit process stopped\n", 2766 sc->sc_dev.dv_xname); 2767 if (status & ATW_INTR_RPS) 2768 printf("%s: receive process stopped\n", 2769 sc->sc_dev.dv_xname); 2770 (void)atw_init(ifp); 2771 break; 2772 } 2773 2774 if (status & ATW_INTR_FBE) { 2775 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2776 (void)atw_init(ifp); 2777 break; 2778 } 2779 2780 /* 2781 * Not handled: 2782 * 2783 * Transmit buffer unavailable -- normal 2784 * condition, nothing to do, really. 2785 * 2786 * Early receive interrupt -- not available on 2787 * all chips, we just use RI. We also only 2788 * use single-segment receive DMA, so this 2789 * is mostly useless. 2790 * 2791 * TBD others 2792 */ 2793 } 2794 2795 /* Try to get more packets going. */ 2796 atw_start(ifp); 2797 2798 return (handled); 2799 } 2800 2801 /* 2802 * atw_idle: 2803 * 2804 * Cause the transmit and/or receive processes to go idle. 2805 * 2806 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2807 * process in STSR if I clear SR or ST after the process has already 2808 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2809 * do not seem to be too reliable. Perhaps I have the sense of the 2810 * Rx bits switched with the Tx bits? 2811 */ 2812 void 2813 atw_idle(sc, bits) 2814 struct atw_softc *sc; 2815 u_int32_t bits; 2816 { 2817 u_int32_t ackmask = 0, opmode, stsr, test0; 2818 int i, s; 2819 2820 /* without this, somehow we run concurrently w/ interrupt handler */ 2821 s = splnet(); 2822 2823 opmode = sc->sc_opmode & ~bits; 2824 2825 if (bits & ATW_NAR_SR) 2826 ackmask |= ATW_INTR_RPS; 2827 2828 if (bits & ATW_NAR_ST) { 2829 ackmask |= ATW_INTR_TPS; 2830 /* set ATW_NAR_HF to flush TX FIFO. */ 2831 opmode |= ATW_NAR_HF; 2832 } 2833 2834 ATW_WRITE(sc, ATW_NAR, opmode); 2835 2836 for (i = 0; i < 1000; i++) { 2837 stsr = ATW_READ(sc, ATW_STSR); 2838 if ((stsr & ackmask) == ackmask) 2839 break; 2840 DELAY(10); 2841 } 2842 2843 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2844 2845 if ((stsr & ackmask) == ackmask) 2846 goto out; 2847 2848 test0 = ATW_READ(sc, ATW_TEST0); 2849 2850 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2851 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2852 printf("%s: transmit process not idle [%s]\n", 2853 sc->sc_dev.dv_xname, 2854 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2855 printf("%s: bits %08x test0 %08x stsr %08x\n", 2856 sc->sc_dev.dv_xname, bits, test0, stsr); 2857 } 2858 2859 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2860 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2861 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2862 sc->sc_dev.dv_xname, 2863 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2864 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2865 sc->sc_dev.dv_xname, bits, test0, stsr)); 2866 } 2867 out: 2868 splx(s); 2869 return; 2870 } 2871 2872 /* 2873 * atw_linkintr: 2874 * 2875 * Helper; handle link-status interrupts. 2876 */ 2877 void 2878 atw_linkintr(sc, linkstatus) 2879 struct atw_softc *sc; 2880 u_int32_t linkstatus; 2881 { 2882 struct ieee80211com *ic = &sc->sc_ic; 2883 2884 if (ic->ic_state != IEEE80211_S_RUN) 2885 return; 2886 2887 if (linkstatus & ATW_INTR_LINKON) { 2888 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2889 sc->sc_rescan_timer = 0; 2890 } else if (linkstatus & ATW_INTR_LINKOFF) { 2891 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2892 switch (ic->ic_opmode) { 2893 case IEEE80211_M_IBSS: 2894 if (ic->ic_flags & IEEE80211_F_SIBSS) 2895 return; 2896 /* FALL THROUGH */ 2897 case IEEE80211_M_STA: 2898 sc->sc_rescan_timer = 3; 2899 ic->ic_if.if_timer = 1; 2900 break; 2901 default: 2902 break; 2903 } 2904 } 2905 } 2906 2907 /* 2908 * atw_rxintr: 2909 * 2910 * Helper; handle receive interrupts. 2911 */ 2912 void 2913 atw_rxintr(sc) 2914 struct atw_softc *sc; 2915 { 2916 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2917 struct ifnet *ifp = &sc->sc_ic.ic_if; 2918 struct atw_rxsoft *rxs; 2919 struct mbuf *m; 2920 u_int32_t rxstat; 2921 int i, len, rate, rate0, rssi; 2922 2923 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2924 rxs = &sc->sc_rxsoft[i]; 2925 2926 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2927 2928 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2929 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2930 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2931 2932 if (rxstat & ATW_RXSTAT_OWN) { 2933 /* 2934 * We have processed all of the receive buffers. 2935 */ 2936 break; 2937 } 2938 2939 ATW_DPRINTF3(("%s: rssi %d\n", sc->sc_dev.dv_xname, rssi)); 2940 2941 /* 2942 * Make sure the packet fit in one buffer. This should 2943 * always be the case. 2944 */ 2945 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2946 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2947 printf("%s: incoming packet spilled, resetting\n", 2948 sc->sc_dev.dv_xname); 2949 (void)atw_init(ifp); 2950 return; 2951 } 2952 2953 /* 2954 * If an error occurred, update stats, clear the status 2955 * word, and leave the packet buffer in place. It will 2956 * simply be reused the next time the ring comes around. 2957 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2958 * error. 2959 */ 2960 2961 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2962 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2963 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2964 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2965 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2966 ATW_RXSTAT_ICVE)) != 0)) { 2967 #define PRINTERR(bit, str) \ 2968 if (rxstat & (bit)) \ 2969 printf("%s: receive error: %s\n", \ 2970 sc->sc_dev.dv_xname, str) 2971 ifp->if_ierrors++; 2972 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2973 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2974 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2975 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2976 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2977 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2978 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2979 #undef PRINTERR 2980 ATW_INIT_RXDESC(sc, i); 2981 continue; 2982 } 2983 2984 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2985 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2986 2987 /* 2988 * No errors; receive the packet. Note the ADM8211 2989 * includes the CRC in promiscuous mode. 2990 */ 2991 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2992 2993 /* 2994 * Allocate a new mbuf cluster. If that fails, we are 2995 * out of memory, and must drop the packet and recycle 2996 * the buffer that's already attached to this descriptor. 2997 */ 2998 m = rxs->rxs_mbuf; 2999 if (atw_add_rxbuf(sc, i) != 0) { 3000 ifp->if_ierrors++; 3001 ATW_INIT_RXDESC(sc, i); 3002 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3003 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3004 continue; 3005 } 3006 3007 ifp->if_ipackets++; 3008 if (sc->sc_opmode & ATW_NAR_PR) 3009 m->m_flags |= M_HASFCS; 3010 m->m_pkthdr.rcvif = ifp; 3011 m->m_pkthdr.len = m->m_len = len; 3012 3013 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3014 rate = 0; 3015 else 3016 rate = rate_tbl[rate0]; 3017 3018 #if NBPFILTER > 0 3019 /* 3020 * Pass this up to any BPF listeners, but only 3021 * pass it up the stack if it's for us. 3022 */ 3023 if (sc->sc_radiobpf) { 3024 /* TBD capture DLT_IEEE802_11_RADIO */ 3025 } 3026 #endif /* NPBFILTER > 0 */ 3027 3028 /* Pass it on. */ 3029 ieee80211_input(ifp, m, rssi, 0); 3030 } 3031 3032 /* Update the receive pointer. */ 3033 sc->sc_rxptr = i; 3034 } 3035 3036 /* 3037 * atw_txintr: 3038 * 3039 * Helper; handle transmit interrupts. 3040 */ 3041 void 3042 atw_txintr(sc) 3043 struct atw_softc *sc; 3044 { 3045 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3046 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3047 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3048 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3049 3050 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3051 struct ifnet *ifp = &sc->sc_ic.ic_if; 3052 struct atw_txsoft *txs; 3053 u_int32_t txstat; 3054 3055 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3056 sc->sc_dev.dv_xname, sc->sc_flags)); 3057 3058 ifp->if_flags &= ~IFF_OACTIVE; 3059 3060 /* 3061 * Go through our Tx list and free mbufs for those 3062 * frames that have been transmitted. 3063 */ 3064 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3065 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3066 txs->txs_ndescs, 3067 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3068 3069 #ifdef ATW_DEBUG 3070 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3071 int i; 3072 printf(" txsoft %p transmit chain:\n", txs); 3073 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3074 printf(" descriptor %d:\n", i); 3075 printf(" at_status: 0x%08x\n", 3076 le32toh(sc->sc_txdescs[i].at_stat)); 3077 printf(" at_flags: 0x%08x\n", 3078 le32toh(sc->sc_txdescs[i].at_flags)); 3079 printf(" at_buf1: 0x%08x\n", 3080 le32toh(sc->sc_txdescs[i].at_buf1)); 3081 printf(" at_buf2: 0x%08x\n", 3082 le32toh(sc->sc_txdescs[i].at_buf2)); 3083 if (i == txs->txs_lastdesc) 3084 break; 3085 } 3086 } 3087 #endif 3088 3089 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3090 if (txstat & ATW_TXSTAT_OWN) 3091 break; 3092 3093 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3094 3095 sc->sc_txfree += txs->txs_ndescs; 3096 3097 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3098 0, txs->txs_dmamap->dm_mapsize, 3099 BUS_DMASYNC_POSTWRITE); 3100 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3101 m_freem(txs->txs_mbuf); 3102 txs->txs_mbuf = NULL; 3103 3104 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3105 3106 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3107 (txstat & TXSTAT_ERRMASK) != 0) { 3108 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3109 txstat_buf, sizeof(txstat_buf)); 3110 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3111 txstat_buf, 3112 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3113 } 3114 3115 /* 3116 * Check for errors and collisions. 3117 */ 3118 if (txstat & ATW_TXSTAT_TUF) 3119 sc->sc_stats.ts_tx_tuf++; 3120 if (txstat & ATW_TXSTAT_TLT) 3121 sc->sc_stats.ts_tx_tlt++; 3122 if (txstat & ATW_TXSTAT_TRT) 3123 sc->sc_stats.ts_tx_trt++; 3124 if (txstat & ATW_TXSTAT_TRO) 3125 sc->sc_stats.ts_tx_tro++; 3126 if (txstat & ATW_TXSTAT_SOFBR) { 3127 sc->sc_stats.ts_tx_sofbr++; 3128 } 3129 3130 if ((txstat & ATW_TXSTAT_ES) == 0) 3131 ifp->if_collisions += 3132 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3133 else 3134 ifp->if_oerrors++; 3135 3136 ifp->if_opackets++; 3137 } 3138 3139 /* 3140 * If there are no more pending transmissions, cancel the watchdog 3141 * timer. 3142 */ 3143 if (txs == NULL) 3144 sc->sc_tx_timer = 0; 3145 #undef TXSTAT_ERRMASK 3146 #undef TXSTAT_FMT 3147 } 3148 3149 /* 3150 * atw_watchdog: [ifnet interface function] 3151 * 3152 * Watchdog timer handler. 3153 */ 3154 void 3155 atw_watchdog(ifp) 3156 struct ifnet *ifp; 3157 { 3158 struct atw_softc *sc = ifp->if_softc; 3159 3160 ifp->if_timer = 0; 3161 if (ATW_IS_ENABLED(sc) == 0) 3162 return; 3163 3164 if (sc->sc_rescan_timer) { 3165 if (--sc->sc_rescan_timer == 0) 3166 (void)ieee80211_new_state(ifp, IEEE80211_S_SCAN, -1); 3167 } 3168 if (sc->sc_tx_timer) { 3169 if (--sc->sc_tx_timer == 0 && 3170 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3171 printf("%s: transmit timeout\n", ifp->if_xname); 3172 ifp->if_oerrors++; 3173 (void)atw_init(ifp); 3174 atw_start(ifp); 3175 } 3176 } 3177 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3178 ifp->if_timer = 1; 3179 ieee80211_watchdog(ifp); 3180 } 3181 3182 /* Compute the 802.11 Duration field and the PLCP Length fields for 3183 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3184 * Write the fields to the ADM8211 Tx header, frm. 3185 * 3186 * TBD use the fragmentation threshold to find the right duration for 3187 * the first & last fragments. 3188 * 3189 * TBD make certain of the duration fields applied by the ADM8211 to each 3190 * fragment. I think that the ADM8211 knows how to subtract the CTS 3191 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3192 * I also think that the ADM8211 does *some* arithmetic for us, because 3193 * otherwise I think we would have to set a first duration for CTS/first 3194 * fragment, a second duration for fragments between the first and the 3195 * last, and a third duration for the last fragment. 3196 * 3197 * TBD make certain that duration fields reflect addition of FCS/WEP 3198 * and correct duration arithmetic as necessary. 3199 */ 3200 static void 3201 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3202 int len) 3203 { 3204 int remainder; 3205 3206 /* deal also with encrypted fragments */ 3207 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3208 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3209 sc->sc_dev.dv_xname)); 3210 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3211 IEEE80211_WEP_CRCLEN; 3212 } 3213 3214 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3215 * duration (XXX added by MAC?). 3216 */ 3217 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3218 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3219 3220 if (rate <= 4) 3221 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3222 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3223 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3224 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3225 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3226 else 3227 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3228 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3229 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3230 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3231 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3232 3233 /* lengthen duration if long preamble */ 3234 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3235 frm->atw_head_dur += 3236 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3237 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3238 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3239 IEEE80211_DUR_DS_FAST_PLCPHDR); 3240 3241 if (remainder != 0) 3242 frm->atw_head_dur++; 3243 3244 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3245 (rate == 2 || rate == 4)) { 3246 /* derived from Linux: how could this be right? */ 3247 frm->atw_head_plcplen = frm->atw_head_dur; 3248 } else { 3249 frm->atw_head_plcplen = (16 * len) / rate; 3250 remainder = (80 * len) % (rate * 5); 3251 3252 if (remainder != 0) { 3253 frm->atw_head_plcplen++; 3254 3255 /* XXX magic */ 3256 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3257 rate == 22 && remainder <= 30) 3258 frm->atw_head_plcplen |= 0x8000; 3259 } 3260 } 3261 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3262 htole16(frm->atw_head_plcplen); 3263 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3264 } 3265 3266 #ifdef ATW_DEBUG 3267 static void 3268 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3269 { 3270 struct atw_softc *sc = ifp->if_softc; 3271 struct mbuf *m; 3272 int i, noctets = 0; 3273 3274 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3275 m0->m_pkthdr.len); 3276 3277 for (m = m0; m; m = m->m_next) { 3278 if (m->m_len == 0) 3279 continue; 3280 for (i = 0; i < m->m_len; i++) { 3281 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3282 if (++noctets % 24 == 0) 3283 printf("\n"); 3284 } 3285 } 3286 printf("%s%s: %d bytes emitted\n", 3287 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3288 } 3289 #endif /* ATW_DEBUG */ 3290 3291 /* 3292 * atw_start: [ifnet interface function] 3293 * 3294 * Start packet transmission on the interface. 3295 */ 3296 void 3297 atw_start(ifp) 3298 struct ifnet *ifp; 3299 { 3300 struct atw_softc *sc = ifp->if_softc; 3301 struct ieee80211com *ic = &sc->sc_ic; 3302 struct ieee80211_frame_addr4 *wh; 3303 struct atw_frame *hh; 3304 struct mbuf *m0, *m, *mh; 3305 struct atw_txsoft *txs, *last_txs; 3306 struct atw_txdesc *txd; 3307 int do_encrypt, is_mgt, rate; 3308 bus_dmamap_t dmamap; 3309 int ctl, error, firsttx, nexttx, lasttx, ofree, seg; 3310 3311 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3312 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3313 3314 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3315 return; 3316 3317 #if 0 /* TBD ??? */ 3318 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3319 return; 3320 #endif 3321 3322 /* 3323 * Remember the previous number of free descriptors and 3324 * the first descriptor we'll use. 3325 */ 3326 ofree = sc->sc_txfree; 3327 firsttx = sc->sc_txnext; 3328 3329 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3330 sc->sc_dev.dv_xname, ofree, firsttx)); 3331 3332 /* 3333 * Loop through the send queue, setting up transmit descriptors 3334 * until we drain the queue, or use up all available transmit 3335 * descriptors. 3336 */ 3337 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3338 sc->sc_txfree != 0) { 3339 3340 do_encrypt = 0; 3341 is_mgt = 1; 3342 3343 /* 3344 * Grab a packet off the management queue, if it 3345 * is not empty. Otherwise, from the data queue. 3346 */ 3347 IF_POLL(&ic->ic_mgtq, m0); 3348 if (m0 == NULL) { 3349 is_mgt = 0; 3350 IFQ_POLL(&ifp->if_snd, m0); 3351 if (m0 == NULL) 3352 break; 3353 #if NBPFILTER > 0 3354 if (ifp->if_bpf != NULL) 3355 bpf_mtap(ifp->if_bpf, m0); 3356 #endif /* NBPFILTER > 0 */ 3357 if ((m0 = ieee80211_encap(ifp, m0)) == NULL) { 3358 ifp->if_oerrors++; 3359 continue; 3360 } 3361 } 3362 m = NULL; 3363 3364 #if NBPFILTER > 0 3365 /* 3366 * Pass the packet to any BPF listeners. 3367 */ 3368 if (ic->ic_rawbpf != NULL) 3369 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3370 if (sc->sc_radiobpf != NULL) 3371 ; /* TBD tap w/ radio header */ 3372 #endif /* NBPFILTER > 0 */ 3373 3374 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3375 3376 if (m0 == NULL) { 3377 ifp->if_oerrors++; 3378 continue; 3379 } 3380 3381 /* just to make sure. */ 3382 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3383 3384 if (m0 == NULL) { 3385 ifp->if_oerrors++; 3386 continue; 3387 } 3388 3389 hh = mtod(m0, struct atw_frame *); 3390 wh = &hh->atw_ihdr; 3391 3392 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3393 3394 /* Copy everything we need from the 802.11 header: 3395 * Frame Control; address 1, address 3, or addresses 3396 * 3 and 4. NIC fills in BSSID, SA. 3397 */ 3398 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3399 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3400 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3401 memcpy(hh->atw_addr4, wh->i_addr4, 3402 IEEE80211_ADDR_LEN); 3403 } else 3404 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3405 3406 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3407 3408 /* zero 802.11 header before we fill it w/ Tx parameters */ 3409 memset(&hh->atw_ihdr, 0, sizeof(hh->atw_ihdr)); 3410 3411 rate = MAX(ieee80211_get_rate(ic), 2); 3412 3413 hh->atw_rate = rate * 5; 3414 /* XXX this could be incorrect if M_FCS. _encap should 3415 * probably strip FCS just in case it sticks around in 3416 * bridged packets. 3417 */ 3418 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3419 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3420 sizeof(struct atw_frame)); 3421 3422 #if 0 3423 /* this virtually guaranteed that WEP-encrypted frames 3424 * are fragmented. oops. 3425 */ 3426 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3427 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3428 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3429 #else 3430 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3431 #endif 3432 3433 hh->atw_rtylmt = 3; 3434 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3435 if (do_encrypt) { 3436 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3437 hh->atw_keyid = ic->ic_wep_txkey; 3438 } 3439 3440 /* TBD 4-addr frames */ 3441 atw_frame_setdurs(sc, hh, rate, 3442 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3443 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3444 3445 /* never fragment multicast frames */ 3446 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3447 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3448 } else if (sc->sc_flags & ATWF_RTSCTS) { 3449 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3450 } 3451 3452 #ifdef ATW_DEBUG 3453 /* experimental stuff */ 3454 if (atw_xrtylmt != ~0) 3455 hh->atw_rtylmt = atw_xrtylmt; 3456 if (atw_xhdrctl != 0) 3457 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3458 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3459 hh->atw_service = atw_xservice; 3460 if (atw_xpaylen != 0) 3461 hh->atw_paylen = htole16(atw_xpaylen); 3462 memset(hh->atw_addr4, 0, IEEE80211_ADDR_LEN); 3463 hh->atw_fragnum = 0; 3464 3465 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3466 printf("%s: dst = %s, rate = 0x%02x, " 3467 "service = 0x%02x, paylen = 0x%04x\n", 3468 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3469 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3470 3471 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3472 "dur1 = 0x%04x, dur2 = 0x%04x, " 3473 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3474 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3475 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3476 hh->atw_tail_dur, hh->atw_head_dur); 3477 3478 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3479 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3480 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3481 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3482 3483 printf("%s: keyid = %d\n", 3484 sc->sc_dev.dv_xname, hh->atw_keyid); 3485 3486 atw_dump_pkt(ifp, m0); 3487 } 3488 #endif /* ATW_DEBUG */ 3489 3490 dmamap = txs->txs_dmamap; 3491 3492 /* 3493 * Load the DMA map. If this fails, the packet either 3494 * didn't fit in the alloted number of segments, or we were 3495 * short on resources. In this case, we'll copy and try 3496 * again. 3497 */ 3498 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3499 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 3500 MGETHDR(m, M_DONTWAIT, MT_DATA); 3501 if (m == NULL) { 3502 printf("%s: unable to allocate Tx mbuf\n", 3503 sc->sc_dev.dv_xname); 3504 break; 3505 } 3506 if (m0->m_pkthdr.len > MHLEN) { 3507 MCLGET(m, M_DONTWAIT); 3508 if ((m->m_flags & M_EXT) == 0) { 3509 printf("%s: unable to allocate Tx " 3510 "cluster\n", sc->sc_dev.dv_xname); 3511 m_freem(m); 3512 break; 3513 } 3514 } 3515 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3516 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3517 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 3518 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 3519 if (error) { 3520 printf("%s: unable to load Tx buffer, " 3521 "error = %d\n", sc->sc_dev.dv_xname, error); 3522 if (m != NULL) 3523 m_freem(m); 3524 break; 3525 } 3526 } 3527 3528 /* 3529 * Ensure we have enough descriptors free to describe 3530 * the packet. 3531 */ 3532 if (dmamap->dm_nsegs > sc->sc_txfree) { 3533 /* 3534 * Not enough free descriptors to transmit this 3535 * packet. We haven't committed to anything yet, 3536 * so just unload the DMA map, put the packet 3537 * back on the queue, and punt. Notify the upper 3538 * layer that there are no more slots left. 3539 * 3540 * XXX We could allocate an mbuf and copy, but 3541 * XXX it is worth it? 3542 */ 3543 ifp->if_flags |= IFF_OACTIVE; 3544 bus_dmamap_unload(sc->sc_dmat, dmamap); 3545 if (m != NULL) 3546 m_freem(m); 3547 break; 3548 } 3549 3550 if (is_mgt) { 3551 IF_DEQUEUE(&ic->ic_mgtq, mh); 3552 } else { 3553 IFQ_DEQUEUE(&ifp->if_snd, mh); 3554 } 3555 3556 if (m != NULL) { 3557 m_freem(m0); 3558 m0 = m; 3559 } 3560 3561 /* 3562 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3563 */ 3564 3565 /* Sync the DMA map. */ 3566 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3567 BUS_DMASYNC_PREWRITE); 3568 3569 /* XXX arbitrary retry limit; 8 because I have seen it in 3570 * use already and maybe 0 means "no tries" ! 3571 */ 3572 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3573 3574 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3575 sc->sc_dev.dv_xname, rate * 5)); 3576 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3577 3578 /* 3579 * Initialize the transmit descriptors. 3580 */ 3581 for (nexttx = sc->sc_txnext, seg = 0; 3582 seg < dmamap->dm_nsegs; 3583 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3584 /* 3585 * If this is the first descriptor we're 3586 * enqueueing, don't set the OWN bit just 3587 * yet. That could cause a race condition. 3588 * We'll do it below. 3589 */ 3590 txd = &sc->sc_txdescs[nexttx]; 3591 txd->at_ctl = ctl | 3592 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3593 3594 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3595 txd->at_flags = 3596 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3597 ATW_TXFLAG_TBS1_MASK)) | 3598 ((nexttx == (ATW_NTXDESC - 1)) 3599 ? htole32(ATW_TXFLAG_TER) : 0); 3600 lasttx = nexttx; 3601 } 3602 3603 /* Set `first segment' and `last segment' appropriately. */ 3604 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3605 htole32(ATW_TXFLAG_FS); 3606 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3607 3608 #ifdef ATW_DEBUG 3609 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3610 printf(" txsoft %p transmit chain:\n", txs); 3611 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3612 printf(" descriptor %d:\n", seg); 3613 printf(" at_ctl: 0x%08x\n", 3614 le32toh(sc->sc_txdescs[seg].at_ctl)); 3615 printf(" at_flags: 0x%08x\n", 3616 le32toh(sc->sc_txdescs[seg].at_flags)); 3617 printf(" at_buf1: 0x%08x\n", 3618 le32toh(sc->sc_txdescs[seg].at_buf1)); 3619 printf(" at_buf2: 0x%08x\n", 3620 le32toh(sc->sc_txdescs[seg].at_buf2)); 3621 if (seg == lasttx) 3622 break; 3623 } 3624 } 3625 #endif 3626 3627 /* Sync the descriptors we're using. */ 3628 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3629 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3630 3631 /* 3632 * Store a pointer to the packet so we can free it later, 3633 * and remember what txdirty will be once the packet is 3634 * done. 3635 */ 3636 txs->txs_mbuf = m0; 3637 txs->txs_firstdesc = sc->sc_txnext; 3638 txs->txs_lastdesc = lasttx; 3639 txs->txs_ndescs = dmamap->dm_nsegs; 3640 3641 /* Advance the tx pointer. */ 3642 sc->sc_txfree -= dmamap->dm_nsegs; 3643 sc->sc_txnext = nexttx; 3644 3645 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3646 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3647 3648 last_txs = txs; 3649 } 3650 3651 if (txs == NULL || sc->sc_txfree == 0) { 3652 /* No more slots left; notify upper layer. */ 3653 ifp->if_flags |= IFF_OACTIVE; 3654 } 3655 3656 if (sc->sc_txfree != ofree) { 3657 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3658 sc->sc_dev.dv_xname, lasttx, firsttx)); 3659 /* 3660 * Cause a transmit interrupt to happen on the 3661 * last packet we enqueued. 3662 */ 3663 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3664 ATW_CDTXSYNC(sc, lasttx, 1, 3665 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3666 3667 /* 3668 * The entire packet chain is set up. Give the 3669 * first descriptor to the chip now. 3670 */ 3671 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3672 ATW_CDTXSYNC(sc, firsttx, 1, 3673 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3674 3675 /* Wake up the transmitter. */ 3676 /* XXX USE AUTOPOLLING? */ 3677 ATW_WRITE(sc, ATW_TDR, 0x1); 3678 3679 /* Set a watchdog timer in case the chip flakes out. */ 3680 sc->sc_tx_timer = 5; 3681 ifp->if_timer = 1; 3682 } 3683 } 3684 3685 /* 3686 * atw_power: 3687 * 3688 * Power management (suspend/resume) hook. 3689 */ 3690 void 3691 atw_power(why, arg) 3692 int why; 3693 void *arg; 3694 { 3695 struct atw_softc *sc = arg; 3696 struct ifnet *ifp = &sc->sc_ic.ic_if; 3697 int s; 3698 3699 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3700 3701 s = splnet(); 3702 switch (why) { 3703 case PWR_STANDBY: 3704 /* XXX do nothing. */ 3705 break; 3706 case PWR_SUSPEND: 3707 atw_stop(ifp, 0); 3708 if (sc->sc_power != NULL) 3709 (*sc->sc_power)(sc, why); 3710 break; 3711 case PWR_RESUME: 3712 if (ifp->if_flags & IFF_UP) { 3713 if (sc->sc_power != NULL) 3714 (*sc->sc_power)(sc, why); 3715 atw_init(ifp); 3716 } 3717 break; 3718 case PWR_SOFTSUSPEND: 3719 case PWR_SOFTSTANDBY: 3720 case PWR_SOFTRESUME: 3721 break; 3722 } 3723 splx(s); 3724 } 3725 3726 /* 3727 * atw_ioctl: [ifnet interface function] 3728 * 3729 * Handle control requests from the operator. 3730 */ 3731 int 3732 atw_ioctl(ifp, cmd, data) 3733 struct ifnet *ifp; 3734 u_long cmd; 3735 caddr_t data; 3736 { 3737 struct atw_softc *sc = ifp->if_softc; 3738 struct ifreq *ifr = (struct ifreq *)data; 3739 int s, error = 0; 3740 3741 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3742 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3743 return ENXIO; 3744 3745 s = splnet(); 3746 3747 switch (cmd) { 3748 case SIOCSIFFLAGS: 3749 if (ifp->if_flags & IFF_UP) { 3750 if (ATW_IS_ENABLED(sc)) { 3751 /* 3752 * To avoid rescanning another access point, 3753 * do not call atw_init() here. Instead, 3754 * only reflect media settings. 3755 */ 3756 atw_filter_setup(sc); 3757 } else 3758 error = atw_init(ifp); 3759 } else if (ATW_IS_ENABLED(sc)) 3760 atw_stop(ifp, 1); 3761 break; 3762 case SIOCADDMULTI: 3763 case SIOCDELMULTI: 3764 error = (cmd == SIOCADDMULTI) ? 3765 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3766 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3767 if (error == ENETRESET) { 3768 if (ATW_IS_ENABLED(sc)) 3769 atw_filter_setup(sc); /* do not rescan */ 3770 error = 0; 3771 } 3772 break; 3773 default: 3774 error = ieee80211_ioctl(ifp, cmd, data); 3775 if (error == ENETRESET) { 3776 if (ATW_IS_ENABLED(sc)) 3777 error = atw_init(ifp); 3778 else 3779 error = 0; 3780 } 3781 break; 3782 } 3783 3784 /* Try to get more packets going. */ 3785 if (ATW_IS_ENABLED(sc)) 3786 atw_start(ifp); 3787 3788 splx(s); 3789 return (error); 3790 } 3791 3792 static void 3793 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3794 { 3795 struct atw_softc *sc = ifp->if_softc; 3796 3797 if (ATW_IS_ENABLED(sc) == 0) { 3798 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3799 imr->ifm_status = 0; 3800 return; 3801 } 3802 ieee80211_media_status(ifp, imr); 3803 } 3804
Indexes created Fri Sep 26 20:09:58 GMT 2025