atw.c revision 1.10
1 /* $NetBSD: atw.c,v 1.10 2003/11/02 02:05:15 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.10 2003/11/02 02:05:15 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/ic/atwreg.h> 80 #include <dev/ic/atwvar.h> 81 #include <dev/ic/smc93cx6var.h> 82 83 /* XXX TBD open questions 84 * 85 * 86 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 87 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 88 * handle this for me? 89 * 90 */ 91 /* device attachment 92 * 93 * print TOFS[012] 94 * 95 * device initialization 96 * 97 * clear ATW_FRCTL_MAXPSP to disable max power saving 98 * set ATW_TXBR_ALCUPDATE to enable ALC 99 * set TOFS[012]? (hope not) 100 * disable rx/tx 101 * set ATW_PAR_SWR (software reset) 102 * wait for ATW_PAR_SWR clear 103 * disable interrupts 104 * ack status register 105 * enable interrupts 106 * 107 * rx/tx initialization 108 * 109 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 110 * allocate and init descriptor rings 111 * write ATW_PAR_DSL (descriptor skip length) 112 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 113 * write ATW_NAR_SQ for one/both transmit descriptor rings 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * 117 * rx/tx end 118 * 119 * stop DMA 120 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 121 * flush tx w/ ATW_NAR_HF 122 * 123 * scan 124 * 125 * initialize rx/tx 126 * 127 * IBSS join/create 128 * 129 * set ATW_NAR_EA (is set by ASIC?) 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 140 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 141 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 142 143 int atw_rfio_enable_delay = 20 * 1000; 144 int atw_rfio_disable_delay = 2 * 1000; 145 int atw_writewep_delay = 5; 146 int atw_beacon_len_adjust = 4; 147 int atw_dwelltime = 200; 148 149 #ifdef ATW_DEBUG 150 int atw_xhdrctl = 0; 151 int atw_xrtylmt = ~0; 152 int atw_xservice = IEEE80211_PLCP_SERVICE; 153 int atw_xpaylen = 0; 154 155 int atw_debug = 0; 156 157 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 158 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 159 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 160 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 161 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 162 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 163 static void atw_print_regs(struct atw_softc *, const char *); 164 static void atw_rf3000_print(struct atw_softc *); 165 static void atw_si4126_print(struct atw_softc *); 166 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 167 #else 168 #define ATW_DPRINTF(x) 169 #define ATW_DPRINTF2(x) 170 #define ATW_DPRINTF3(x) 171 #define DPRINTF(sc, x) /* nothing */ 172 #define DPRINTF2(sc, x) /* nothing */ 173 #define DPRINTF3(sc, x) /* nothing */ 174 #endif 175 176 #ifdef ATW_STATS 177 void atw_print_stats __P((struct atw_softc *)); 178 #endif 179 180 void atw_start __P((struct ifnet *)); 181 void atw_watchdog __P((struct ifnet *)); 182 int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 183 int atw_init __P((struct ifnet *)); 184 void atw_stop __P((struct ifnet *, int)); 185 186 void atw_reset __P((struct atw_softc *)); 187 int atw_read_srom __P((struct atw_softc *)); 188 189 void atw_shutdown __P((void *)); 190 191 void atw_rxdrain __P((struct atw_softc *)); 192 int atw_add_rxbuf __P((struct atw_softc *, int)); 193 void atw_idle __P((struct atw_softc *, u_int32_t)); 194 195 int atw_enable __P((struct atw_softc *)); 196 void atw_disable __P((struct atw_softc *)); 197 void atw_power __P((int, void *)); 198 199 void atw_rxintr __P((struct atw_softc *)); 200 void atw_txintr __P((struct atw_softc *)); 201 void atw_linkintr __P((struct atw_softc *, u_int32_t)); 202 203 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 204 static void atw_tsf(struct atw_softc *); 205 static void atw_start_beacon(struct atw_softc *, int); 206 static void atw_write_wep(struct atw_softc *); 207 static void atw_write_bssid(struct atw_softc *); 208 static void atw_write_bcn_thresh(struct atw_softc *); 209 static void atw_write_ssid(struct atw_softc *); 210 static void atw_write_sup_rates(struct atw_softc *); 211 static void atw_clear_sram(struct atw_softc *); 212 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 213 static int atw_media_change(struct ifnet *); 214 static void atw_media_status(struct ifnet *, struct ifmediareq *); 215 static void atw_filter_setup(struct atw_softc *); 216 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 217 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 218 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 219 struct ieee80211_node *, int, int, u_int32_t); 220 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 221 struct ieee80211_node *, int, int, u_int32_t); 222 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 223 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 224 225 static int atw_tune(struct atw_softc *); 226 227 static void atw_rfio_enable(struct atw_softc *, int); 228 229 /* RFMD RF3000 Baseband Processor */ 230 static int atw_rf3000_init(struct atw_softc *); 231 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 232 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 233 #ifdef ATW_DEBUG 234 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 235 #endif /* ATW_DEBUG */ 236 237 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 238 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 239 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 240 #ifdef ATW_DEBUG 241 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 242 #endif /* ATW_DEBUG */ 243 244 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 245 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 246 247 const char *atw_tx_state[] = { 248 "STOPPED", 249 "RUNNING - FETCH", 250 "RUNNING - WAIT", 251 "RUNNING - READING", 252 "-- RESERVED1 --", 253 "-- RESERVED2 --", 254 "SUSPENDED", 255 "RUNNING - CLOSE" 256 }; 257 258 const char *atw_rx_state[] = { 259 "STOPPED", 260 "RUNNING - FETCH", 261 "RUNNING - CHECK", 262 "RUNNING - WAIT", 263 "SUSPENDED", 264 "RUNNING - CLOSE", 265 "RUNNING - FLUSH", 266 "RUNNING - QUEUE" 267 }; 268 269 int 270 atw_activate(struct device *self, enum devact act) 271 { 272 struct atw_softc *sc = (struct atw_softc *)self; 273 int rv = 0, s; 274 275 s = splnet(); 276 switch (act) { 277 case DVACT_ACTIVATE: 278 rv = EOPNOTSUPP; 279 break; 280 281 case DVACT_DEACTIVATE: 282 if_deactivate(&sc->sc_ic.ic_if); 283 break; 284 } 285 splx(s); 286 return rv; 287 } 288 289 /* 290 * atw_enable: 291 * 292 * Enable the ADM8211 chip. 293 */ 294 int 295 atw_enable(sc) 296 struct atw_softc *sc; 297 { 298 299 if (ATW_IS_ENABLED(sc) == 0) { 300 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 301 printf("%s: device enable failed\n", 302 sc->sc_dev.dv_xname); 303 return (EIO); 304 } 305 sc->sc_flags |= ATWF_ENABLED; 306 } 307 return (0); 308 } 309 310 /* 311 * atw_disable: 312 * 313 * Disable the ADM8211 chip. 314 */ 315 void 316 atw_disable(sc) 317 struct atw_softc *sc; 318 { 319 if (!ATW_IS_ENABLED(sc)) 320 return; 321 if (sc->sc_disable != NULL) 322 (*sc->sc_disable)(sc); 323 sc->sc_flags &= ~ATWF_ENABLED; 324 } 325 326 /* Returns -1 on failure. */ 327 int 328 atw_read_srom(struct atw_softc *sc) 329 { 330 struct seeprom_descriptor sd; 331 u_int32_t reg; 332 333 (void)memset(&sd, 0, sizeof(sd)); 334 335 reg = ATW_READ(sc, ATW_TEST0); 336 337 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 338 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 339 return -1; 340 } 341 342 switch (reg & ATW_TEST0_EPTYP_MASK) { 343 case ATW_TEST0_EPTYP_93c66: 344 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 345 sc->sc_sromsz = 512; 346 sd.sd_chip = C56_66; 347 break; 348 case ATW_TEST0_EPTYP_93c46: 349 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 350 sc->sc_sromsz = 128; 351 sd.sd_chip = C46; 352 break; 353 default: 354 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 355 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 356 return -1; 357 } 358 359 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 360 361 if (sc->sc_srom == NULL) { 362 printf("%s: unable to allocate SROM buffer\n", 363 sc->sc_dev.dv_xname); 364 return -1; 365 } 366 367 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 368 369 /* ADM8211 has a single 32-bit register for controlling the 370 * 93cx6 SROM. Bit SRS enables the serial port. There is no 371 * "ready" bit. The ADM8211 input/output sense is the reverse 372 * of read_seeprom's. 373 */ 374 sd.sd_tag = sc->sc_st; 375 sd.sd_bsh = sc->sc_sh; 376 sd.sd_regsize = 4; 377 sd.sd_control_offset = ATW_SPR; 378 sd.sd_status_offset = ATW_SPR; 379 sd.sd_dataout_offset = ATW_SPR; 380 sd.sd_CK = ATW_SPR_SCLK; 381 sd.sd_CS = ATW_SPR_SCS; 382 sd.sd_DI = ATW_SPR_SDO; 383 sd.sd_DO = ATW_SPR_SDI; 384 sd.sd_MS = ATW_SPR_SRS; 385 sd.sd_RDY = 0; 386 387 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 388 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 389 free(sc->sc_srom, M_DEVBUF); 390 return -1; 391 } 392 #ifdef ATW_DEBUG 393 { 394 int i; 395 ATW_DPRINTF2(("\nSerial EEPROM:\n\t")); 396 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 397 if (((i % 8) == 0) && (i != 0)) { 398 ATW_DPRINTF2(("\n\t")); 399 } 400 ATW_DPRINTF2((" 0x%x", sc->sc_srom[i])); 401 } 402 ATW_DPRINTF2(("\n")); 403 } 404 #endif /* ATW_DEBUG */ 405 return 0; 406 } 407 408 #ifdef ATW_DEBUG 409 static void 410 atw_print_regs(struct atw_softc *sc, const char *where) 411 { 412 #define PRINTREG(sc, reg) \ 413 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 414 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 415 416 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 417 418 PRINTREG(sc, ATW_PAR); 419 PRINTREG(sc, ATW_FRCTL); 420 PRINTREG(sc, ATW_TDR); 421 PRINTREG(sc, ATW_WTDP); 422 PRINTREG(sc, ATW_RDR); 423 PRINTREG(sc, ATW_WRDP); 424 PRINTREG(sc, ATW_RDB); 425 PRINTREG(sc, ATW_CSR3A); 426 PRINTREG(sc, ATW_TDBD); 427 PRINTREG(sc, ATW_TDBP); 428 PRINTREG(sc, ATW_STSR); 429 PRINTREG(sc, ATW_CSR5A); 430 PRINTREG(sc, ATW_NAR); 431 PRINTREG(sc, ATW_CSR6A); 432 PRINTREG(sc, ATW_IER); 433 PRINTREG(sc, ATW_CSR7A); 434 PRINTREG(sc, ATW_LPC); 435 PRINTREG(sc, ATW_TEST1); 436 PRINTREG(sc, ATW_SPR); 437 PRINTREG(sc, ATW_TEST0); 438 PRINTREG(sc, ATW_WCSR); 439 PRINTREG(sc, ATW_WPDR); 440 PRINTREG(sc, ATW_GPTMR); 441 PRINTREG(sc, ATW_GPIO); 442 PRINTREG(sc, ATW_BBPCTL); 443 PRINTREG(sc, ATW_SYNCTL); 444 PRINTREG(sc, ATW_PLCPHD); 445 PRINTREG(sc, ATW_MMIWADDR); 446 PRINTREG(sc, ATW_MMIRADDR1); 447 PRINTREG(sc, ATW_MMIRADDR2); 448 PRINTREG(sc, ATW_TXBR); 449 PRINTREG(sc, ATW_CSR15A); 450 PRINTREG(sc, ATW_ALCSTAT); 451 PRINTREG(sc, ATW_TOFS2); 452 PRINTREG(sc, ATW_CMDR); 453 PRINTREG(sc, ATW_PCIC); 454 PRINTREG(sc, ATW_PMCSR); 455 PRINTREG(sc, ATW_PAR0); 456 PRINTREG(sc, ATW_PAR1); 457 PRINTREG(sc, ATW_MAR0); 458 PRINTREG(sc, ATW_MAR1); 459 PRINTREG(sc, ATW_ATIMDA0); 460 PRINTREG(sc, ATW_ABDA1); 461 PRINTREG(sc, ATW_BSSID0); 462 PRINTREG(sc, ATW_TXLMT); 463 PRINTREG(sc, ATW_MIBCNT); 464 PRINTREG(sc, ATW_BCNT); 465 PRINTREG(sc, ATW_TSFTH); 466 PRINTREG(sc, ATW_TSC); 467 PRINTREG(sc, ATW_SYNRF); 468 PRINTREG(sc, ATW_BPLI); 469 PRINTREG(sc, ATW_CAP0); 470 PRINTREG(sc, ATW_CAP1); 471 PRINTREG(sc, ATW_RMD); 472 PRINTREG(sc, ATW_CFPP); 473 PRINTREG(sc, ATW_TOFS0); 474 PRINTREG(sc, ATW_TOFS1); 475 PRINTREG(sc, ATW_IFST); 476 PRINTREG(sc, ATW_RSPT); 477 PRINTREG(sc, ATW_TSFTL); 478 PRINTREG(sc, ATW_WEPCTL); 479 PRINTREG(sc, ATW_WESK); 480 PRINTREG(sc, ATW_WEPCNT); 481 PRINTREG(sc, ATW_MACTEST); 482 PRINTREG(sc, ATW_FER); 483 PRINTREG(sc, ATW_FEMR); 484 PRINTREG(sc, ATW_FPSR); 485 PRINTREG(sc, ATW_FFER); 486 #undef PRINTREG 487 } 488 #endif /* ATW_DEBUG */ 489 490 /* 491 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 492 */ 493 void 494 atw_attach(struct atw_softc *sc) 495 { 496 struct ieee80211com *ic = &sc->sc_ic; 497 struct ifnet *ifp = &ic->ic_if; 498 int country_code, error, i, nrate; 499 u_int32_t reg; 500 static const char *type_strings[] = {"Intersil (not supported)", 501 "RFMD", "Marvel (not supported)"}; 502 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 503 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 504 }; 505 506 sc->sc_txth = atw_txthresh_tab_lo; 507 508 SIMPLEQ_INIT(&sc->sc_txfreeq); 509 SIMPLEQ_INIT(&sc->sc_txdirtyq); 510 511 #ifdef ATW_DEBUG 512 atw_print_regs(sc, "atw_attach"); 513 #endif /* ATW_DEBUG */ 514 515 /* 516 * Allocate the control data structures, and create and load the 517 * DMA map for it. 518 */ 519 if ((error = bus_dmamem_alloc(sc->sc_dmat, 520 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 521 1, &sc->sc_cdnseg, 0)) != 0) { 522 printf("%s: unable to allocate control data, error = %d\n", 523 sc->sc_dev.dv_xname, error); 524 goto fail_0; 525 } 526 527 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 528 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 529 BUS_DMA_COHERENT)) != 0) { 530 printf("%s: unable to map control data, error = %d\n", 531 sc->sc_dev.dv_xname, error); 532 goto fail_1; 533 } 534 535 if ((error = bus_dmamap_create(sc->sc_dmat, 536 sizeof(struct atw_control_data), 1, 537 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 538 printf("%s: unable to create control data DMA map, " 539 "error = %d\n", sc->sc_dev.dv_xname, error); 540 goto fail_2; 541 } 542 543 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 544 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 545 0)) != 0) { 546 printf("%s: unable to load control data DMA map, error = %d\n", 547 sc->sc_dev.dv_xname, error); 548 goto fail_3; 549 } 550 551 /* 552 * Create the transmit buffer DMA maps. 553 */ 554 sc->sc_ntxsegs = ATW_NTXSEGS; 555 for (i = 0; i < ATW_TXQUEUELEN; i++) { 556 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 557 sc->sc_ntxsegs, MCLBYTES, 0, 0, 558 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 559 printf("%s: unable to create tx DMA map %d, " 560 "error = %d\n", sc->sc_dev.dv_xname, i, error); 561 goto fail_4; 562 } 563 } 564 565 /* 566 * Create the receive buffer DMA maps. 567 */ 568 for (i = 0; i < ATW_NRXDESC; i++) { 569 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 570 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 571 printf("%s: unable to create rx DMA map %d, " 572 "error = %d\n", sc->sc_dev.dv_xname, i, error); 573 goto fail_5; 574 } 575 sc->sc_rxsoft[i].rxs_mbuf = NULL; 576 } 577 578 /* Reset the chip to a known state. */ 579 atw_reset(sc); 580 581 if (atw_read_srom(sc) == -1) 582 return; 583 584 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 585 ATW_SR_RFTYPE_MASK); 586 587 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_BBPTYPE_MASK); 589 590 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 591 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 592 return; 593 } 594 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 595 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 596 return; 597 } 598 599 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 600 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 601 602 /* XXX There exists a Linux driver which seems to use RFType = 0 for 603 * MARVEL. My bug, or theirs? 604 */ 605 606 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 607 608 switch (sc->sc_rftype) { 609 case ATW_RFTYPE_INTERSIL: 610 reg |= ATW_SYNCTL_CS1; 611 break; 612 case ATW_RFTYPE_RFMD: 613 reg |= ATW_SYNCTL_CS0; 614 break; 615 case ATW_RFTYPE_MARVEL: 616 break; 617 } 618 619 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 620 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 621 622 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 623 624 switch (sc->sc_bbptype) { 625 case ATW_RFTYPE_INTERSIL: 626 reg |= ATW_BBPCTL_TWI; 627 break; 628 case ATW_RFTYPE_RFMD: 629 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 630 ATW_BBPCTL_CCA_ACTLO; 631 break; 632 case ATW_RFTYPE_MARVEL: 633 break; 634 } 635 636 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 637 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 638 639 /* 640 * From this point forward, the attachment cannot fail. A failure 641 * before this point releases all resources that may have been 642 * allocated. 643 */ 644 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 645 646 ATW_DPRINTF2((" SROM MAC %04x%04x%04x", 647 htole16(sc->sc_srom[ATW_SR_MAC00]), 648 htole16(sc->sc_srom[ATW_SR_MAC01]), 649 htole16(sc->sc_srom[ATW_SR_MAC10]))); 650 651 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 652 ATW_SR_CTRY_MASK); 653 654 #define ADD_CHANNEL(_ic, _chan) do { \ 655 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 656 _ic->ic_channels[_chan].ic_freq = \ 657 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 658 } while (0) 659 660 /* Find available channels */ 661 switch (country_code) { 662 case COUNTRY_MMK2: /* 1-14 */ 663 ADD_CHANNEL(ic, 14); 664 /*FALLTHROUGH*/ 665 case COUNTRY_ETSI: /* 1-13 */ 666 for (i = 1; i <= 13; i++) 667 ADD_CHANNEL(ic, i); 668 break; 669 case COUNTRY_FCC: /* 1-11 */ 670 case COUNTRY_IC: /* 1-11 */ 671 for (i = 1; i <= 11; i++) 672 ADD_CHANNEL(ic, i); 673 break; 674 case COUNTRY_MMK: /* 14 */ 675 ADD_CHANNEL(ic, 14); 676 break; 677 case COUNTRY_FRANCE: /* 10-13 */ 678 for (i = 10; i <= 13; i++) 679 ADD_CHANNEL(ic, i); 680 break; 681 default: /* assume channels 10-11 */ 682 case COUNTRY_SPAIN: /* 10-11 */ 683 for (i = 10; i <= 11; i++) 684 ADD_CHANNEL(ic, i); 685 break; 686 } 687 688 /* Read the MAC address. */ 689 reg = ATW_READ(sc, ATW_PAR0); 690 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 691 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 692 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 693 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 694 reg = ATW_READ(sc, ATW_PAR1); 695 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 696 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 697 698 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 699 printf(" could not get mac address, attach failed\n"); 700 return; 701 } 702 703 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 704 705 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 706 ifp->if_softc = sc; 707 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 708 IFF_NOTRAILERS; 709 ifp->if_ioctl = atw_ioctl; 710 ifp->if_start = atw_start; 711 ifp->if_watchdog = atw_watchdog; 712 ifp->if_init = atw_init; 713 ifp->if_stop = atw_stop; 714 IFQ_SET_READY(&ifp->if_snd); 715 716 ic->ic_phytype = IEEE80211_T_DS; 717 ic->ic_opmode = IEEE80211_M_STA; 718 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 719 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 720 721 nrate = 0; 722 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 723 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 724 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 727 728 /* 729 * Call MI attach routines. 730 */ 731 732 if_attach(ifp); 733 ieee80211_ifattach(ifp); 734 735 sc->sc_newstate = ic->ic_newstate; 736 ic->ic_newstate = atw_newstate; 737 738 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 739 ic->ic_recv_mgmt = atw_recv_mgmt; 740 741 sc->sc_node_free = ic->ic_node_free; 742 ic->ic_node_free = atw_node_free; 743 744 sc->sc_node_alloc = ic->ic_node_alloc; 745 ic->ic_node_alloc = atw_node_alloc; 746 747 /* possibly we should fill in our own sc_send_prresp, since 748 * the ADM8211 is probably sending probe responses in ad hoc 749 * mode. 750 */ 751 752 /* complete initialization */ 753 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 754 callout_init(&sc->sc_scan_ch); 755 756 #if 0 757 #if NBPFILTER > 0 758 bpfattach2(ifp, DLT_IEEE802_11_RADIO, /* ??? */, 759 &sc->sc_radiobpf); 760 #endif 761 #endif 762 763 /* 764 * Make sure the interface is shutdown during reboot. 765 */ 766 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 767 if (sc->sc_sdhook == NULL) 768 printf("%s: WARNING: unable to establish shutdown hook\n", 769 sc->sc_dev.dv_xname); 770 771 /* 772 * Add a suspend hook to make sure we come back up after a 773 * resume. 774 */ 775 sc->sc_powerhook = powerhook_establish(atw_power, sc); 776 if (sc->sc_powerhook == NULL) 777 printf("%s: WARNING: unable to establish power hook\n", 778 sc->sc_dev.dv_xname); 779 780 return; 781 782 /* 783 * Free any resources we've allocated during the failed attach 784 * attempt. Do this in reverse order and fall through. 785 */ 786 fail_5: 787 for (i = 0; i < ATW_NRXDESC; i++) { 788 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 789 continue; 790 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 791 } 792 fail_4: 793 for (i = 0; i < ATW_TXQUEUELEN; i++) { 794 if (sc->sc_txsoft[i].txs_dmamap == NULL) 795 continue; 796 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 797 } 798 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 799 fail_3: 800 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 801 fail_2: 802 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 803 sizeof(struct atw_control_data)); 804 fail_1: 805 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 806 fail_0: 807 return; 808 } 809 810 static struct ieee80211_node * 811 atw_node_alloc(struct ieee80211com *ic) 812 { 813 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 814 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 815 816 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 817 return ni; 818 } 819 820 static void 821 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 822 { 823 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 824 825 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 826 ether_sprintf(ni->ni_bssid))); 827 (*sc->sc_node_free)(ic, ni); 828 } 829 830 /* 831 * atw_reset: 832 * 833 * Perform a soft reset on the ADM8211. 834 */ 835 void 836 atw_reset(sc) 837 struct atw_softc *sc; 838 { 839 int i; 840 841 if (ATW_IS_ENABLED(sc) == 0) 842 return; 843 844 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 845 846 for (i = 0; i < 10000; i++) { 847 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 848 break; 849 DELAY(1); 850 } 851 852 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 853 854 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 855 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 856 857 /* Turn off maximum power saving. */ 858 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 859 860 /* Recall EEPROM. */ 861 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 862 863 DELAY(10 * 1000); 864 865 /* A reset seems to affect the SRAM contents, so put them into 866 * a known state. 867 */ 868 atw_clear_sram(sc); 869 870 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 871 872 sc->sc_lost_bcn_thresh = 0; 873 } 874 875 static void 876 atw_clear_sram(sc) 877 struct atw_softc *sc; 878 { 879 #if 0 880 for (addr = 0; addr < 448; addr++) { 881 ATW_WRITE(sc, ATW_WEPCTL, 882 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 883 DELAY(1000); 884 ATW_WRITE(sc, ATW_WESK, 0); 885 DELAY(1000); /* paranoia */ 886 } 887 return; 888 #endif 889 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 890 /* XXX not for revision 0x20. */ 891 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 892 } 893 894 /* TBD atw_init 895 * 896 * set MAC based on ic->ic_bss->myaddr 897 * write WEP keys 898 * set TX rate 899 */ 900 901 /* 902 * atw_init: [ ifnet interface function ] 903 * 904 * Initialize the interface. Must be called at splnet(). 905 */ 906 int 907 atw_init(ifp) 908 struct ifnet *ifp; 909 { 910 struct atw_softc *sc = ifp->if_softc; 911 struct ieee80211com *ic = &sc->sc_ic; 912 struct atw_txsoft *txs; 913 struct atw_rxsoft *rxs; 914 u_int32_t reg; 915 int i, error = 0; 916 917 if ((error = atw_enable(sc)) != 0) 918 goto out; 919 920 /* 921 * Cancel any pending I/O. This also resets. 922 */ 923 atw_stop(ifp, 0); 924 925 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 926 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 927 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 928 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 929 930 /* Turn off APM??? (A binary-only driver does this.) 931 * 932 * Set Rx store-and-forward mode. 933 */ 934 reg = ATW_READ(sc, ATW_CMDR); 935 reg &= ~ATW_CMDR_APM; 936 reg &= ~ATW_CMDR_DRT_MASK; 937 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 938 939 ATW_WRITE(sc, ATW_CMDR, reg); 940 941 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 942 * 943 * XXX a binary-only driver sets a different service field than 944 * 0. why? 945 */ 946 reg = ATW_READ(sc, ATW_PLCPHD); 947 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 948 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 949 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 950 ATW_WRITE(sc, ATW_PLCPHD, reg); 951 952 /* XXX */ 953 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 954 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 955 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 956 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 957 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 958 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 959 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 960 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 961 ATW_WRITE(sc, ATW_TOFS2, reg); 962 963 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 964 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 965 966 /* XXX this resets an Intersil RF front-end? */ 967 /* TBD condition on Intersil RFType? */ 968 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 969 DELAY(10 * 1000); 970 ATW_WRITE(sc, ATW_SYNRF, 0); 971 DELAY(5 * 1000); 972 973 /* 16 TU max duration for contention-free period */ 974 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 975 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 976 977 /* XXX I guess that the Cardbus clock is 22MHz? 978 * I am assuming that the role of ATW_TOFS0_USCNT is 979 * to divide the bus clock to get a 1MHz clock---the datasheet is not 980 * very clear on this point. It says in the datasheet that it is 981 * possible for the ADM8211 to accomodate bus speeds between 22MHz 982 * and 33MHz; maybe this is the way? I see a binary-only driver write 983 * these values. These values are also the power-on default. 984 */ 985 ATW_WRITE(sc, ATW_TOFS0, 986 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 987 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 988 989 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 990 * driver. go figure. 991 */ 992 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 993 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 994 ATW_IFST_SIFS_MASK) | 995 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 996 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 997 998 ATW_WRITE(sc, ATW_IFST, reg); 999 1000 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1001 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1002 1003 /* Set up the MMI read/write addresses for the BBP. 1004 * 1005 * TBD find out the Marvel settings. 1006 */ 1007 switch (sc->sc_bbptype) { 1008 case ATW_BBPTYPE_INTERSIL: 1009 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1010 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1011 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1012 break; 1013 case ATW_BBPTYPE_MARVEL: 1014 break; 1015 case ATW_BBPTYPE_RFMD: 1016 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1017 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1018 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1019 default: 1020 break; 1021 } 1022 1023 sc->sc_wepctl = 0; 1024 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1025 1026 if ((error = atw_rf3000_init(sc)) != 0) 1027 goto out; 1028 1029 /* 1030 * Initialize the PCI Access Register. 1031 */ 1032 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1033 1034 /* 1035 * If we're allowed to do so, use Memory Read Line 1036 * and Memory Read Multiple. 1037 * 1038 * XXX Should we use Memory Write and Invalidate? 1039 */ 1040 if (sc->sc_flags & ATWF_MRL) 1041 sc->sc_busmode |= ATW_PAR_MRLE; 1042 if (sc->sc_flags & ATWF_MRM) 1043 sc->sc_busmode |= ATW_PAR_MRME; 1044 if (sc->sc_flags & ATWF_MWI) 1045 sc->sc_busmode |= ATW_PAR_MWIE; 1046 if (sc->sc_maxburst == 0) 1047 sc->sc_maxburst = 8; /* ADM8211 default */ 1048 1049 switch (sc->sc_cacheline) { 1050 default: 1051 /* Use burst length. */ 1052 break; 1053 case 8: 1054 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1055 break; 1056 case 16: 1057 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1058 break; 1059 case 32: 1060 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1061 break; 1062 } 1063 switch (sc->sc_maxburst) { 1064 case 1: 1065 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1066 break; 1067 case 2: 1068 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1069 break; 1070 case 4: 1071 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1072 break; 1073 case 8: 1074 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1075 break; 1076 case 16: 1077 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1078 break; 1079 case 32: 1080 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1081 break; 1082 default: 1083 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1084 break; 1085 } 1086 1087 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1088 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1089 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1090 1091 /* 1092 * Initialize the OPMODE register. We don't write it until 1093 * we're ready to begin the transmit and receive processes. 1094 */ 1095 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1096 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1097 1098 /* 1099 * Initialize the transmit descriptor ring. 1100 */ 1101 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1102 for (i = 0; i < ATW_NTXDESC; i++) { 1103 /* no transmit chaining */ 1104 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1105 sc->sc_txdescs[i].at_buf2 = 1106 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1107 } 1108 /* use ring mode */ 1109 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1110 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1111 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1112 sc->sc_txfree = ATW_NTXDESC; 1113 sc->sc_txnext = 0; 1114 1115 /* 1116 * Initialize the transmit job descriptors. 1117 */ 1118 SIMPLEQ_INIT(&sc->sc_txfreeq); 1119 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1120 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1121 txs = &sc->sc_txsoft[i]; 1122 txs->txs_mbuf = NULL; 1123 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1124 } 1125 1126 /* 1127 * Initialize the receive descriptor and receive job 1128 * descriptor rings. 1129 */ 1130 for (i = 0; i < ATW_NRXDESC; i++) { 1131 rxs = &sc->sc_rxsoft[i]; 1132 if (rxs->rxs_mbuf == NULL) { 1133 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1134 printf("%s: unable to allocate or map rx " 1135 "buffer %d, error = %d\n", 1136 sc->sc_dev.dv_xname, i, error); 1137 /* 1138 * XXX Should attempt to run with fewer receive 1139 * XXX buffers instead of just failing. 1140 */ 1141 atw_rxdrain(sc); 1142 goto out; 1143 } 1144 } else 1145 ATW_INIT_RXDESC(sc, i); 1146 } 1147 sc->sc_rxptr = 0; 1148 1149 /* disable all wake-up events */ 1150 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1151 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1152 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1153 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1154 1155 /* ack all wake-up events */ 1156 ATW_SET(sc, ATW_WCSR, 0); 1157 1158 /* 1159 * Initialize the interrupt mask and enable interrupts. 1160 */ 1161 /* normal interrupts */ 1162 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1163 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1164 1165 /* abnormal interrupts */ 1166 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1167 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1168 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1169 1170 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1171 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1172 1173 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1174 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1175 ATW_INTR_TRT; 1176 1177 sc->sc_linkint_mask &= sc->sc_inten; 1178 sc->sc_rxint_mask &= sc->sc_inten; 1179 sc->sc_txint_mask &= sc->sc_inten; 1180 1181 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1182 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1183 if (sc->sc_intr_ack != NULL) 1184 (*sc->sc_intr_ack)(sc); 1185 1186 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1187 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1188 1189 /* 1190 * Give the transmit and receive rings to the ADM8211. 1191 */ 1192 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1193 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1194 1195 /* common 802.11 configuration */ 1196 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1197 switch (ic->ic_opmode) { 1198 case IEEE80211_M_HOSTAP: /* XXX */ 1199 case IEEE80211_M_STA: 1200 sc->sc_opmode &= ~ATW_NAR_EA; 1201 break; 1202 case IEEE80211_M_AHDEMO: /* XXX */ 1203 case IEEE80211_M_IBSS: 1204 /* EA bit seems important for ad hoc reception. */ 1205 sc->sc_opmode |= ATW_NAR_EA; 1206 ic->ic_flags |= IEEE80211_F_IBSSON; 1207 break; 1208 case IEEE80211_M_MONITOR: /* XXX */ 1209 break; 1210 } 1211 1212 atw_start_beacon(sc, 0); 1213 1214 switch (ic->ic_opmode) { 1215 case IEEE80211_M_AHDEMO: 1216 case IEEE80211_M_HOSTAP: 1217 ic->ic_bss->ni_intval = ic->ic_lintval; 1218 ic->ic_bss->ni_rssi = 0; 1219 ic->ic_bss->ni_rstamp = 0; 1220 break; 1221 default: /* XXX */ 1222 break; 1223 } 1224 1225 atw_write_ssid(sc); 1226 atw_write_sup_rates(sc); 1227 if (ic->ic_caps & IEEE80211_C_WEP) 1228 atw_write_wep(sc); 1229 1230 /* 1231 * Set the receive filter. This will start the transmit and 1232 * receive processes. 1233 */ 1234 atw_filter_setup(sc); 1235 1236 /* 1237 * Start the receive process. 1238 */ 1239 ATW_WRITE(sc, ATW_RDR, 0x1); 1240 1241 /* 1242 * Note that the interface is now running. 1243 */ 1244 ifp->if_flags |= IFF_RUNNING; 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 ic->ic_state = IEEE80211_S_INIT; 1247 1248 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1249 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1250 else 1251 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1252 out: 1253 if (error) { 1254 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1255 ifp->if_timer = 0; 1256 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1257 } 1258 #ifdef ATW_DEBUG 1259 atw_print_regs(sc, "end of init"); 1260 #endif /* ATW_DEBUG */ 1261 1262 return (error); 1263 } 1264 1265 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1266 * 0: MAC control of RF3000/Si4126. 1267 * 1268 * Applies power, or selects RF front-end? Sets reset condition. 1269 * 1270 * TBD support non-RFMD BBP, non-SiLabs synth. 1271 */ 1272 static void 1273 atw_rfio_enable(struct atw_softc *sc, int enable) 1274 { 1275 if (enable) { 1276 ATW_WRITE(sc, ATW_SYNRF, 1277 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1278 DELAY(atw_rfio_enable_delay); 1279 } else { 1280 ATW_WRITE(sc, ATW_SYNRF, 0); 1281 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1282 } 1283 } 1284 1285 static int 1286 atw_tune(sc) 1287 struct atw_softc *sc; 1288 { 1289 int rc; 1290 u_int32_t reg; 1291 int chan; 1292 struct ieee80211com *ic = &sc->sc_ic; 1293 1294 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1295 if (chan == IEEE80211_CHAN_ANY) 1296 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1297 1298 if (chan == sc->sc_cur_chan) 1299 return 0; 1300 1301 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1302 sc->sc_cur_chan, chan)); 1303 1304 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1305 1306 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1307 (rc = atw_rf3000_tune(sc, chan)) != 0) 1308 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1309 chan); 1310 1311 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1312 ATW_WRITE(sc, ATW_CAP0, 1313 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1314 1315 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1316 1317 if (rc == 0) 1318 sc->sc_cur_chan = chan; 1319 1320 return rc; 1321 } 1322 1323 #ifdef ATW_DEBUG 1324 static void 1325 atw_si4126_print(sc) 1326 struct atw_softc *sc; 1327 { 1328 struct ifnet *ifp = &sc->sc_ic.ic_if; 1329 u_int addr, val; 1330 1331 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1332 return; 1333 1334 for (addr = 0; addr <= 8; addr++) { 1335 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1336 if (atw_si4126_read(sc, addr, &val) == 0) { 1337 printf("<unknown> (quitting print-out)\n"); 1338 break; 1339 } 1340 printf("%05x\n", val); 1341 } 1342 } 1343 #endif /* ATW_DEBUG */ 1344 1345 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1346 * 1347 * The RF/IF synthesizer produces two reference frequencies for 1348 * the RF2948B transceiver. The first frequency the RF2948B requires 1349 * is two times the so-called "intermediate frequency" (IF). Since 1350 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1351 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1352 * frequency required by the transceiver is the radio frequency 1353 * (RF). This is a superheterodyne transceiver; for f(chan) the 1354 * center frequency of the channel we are tuning, RF = f(chan) - 1355 * IF. 1356 * 1357 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1358 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1359 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1360 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1361 */ 1362 static int 1363 atw_si4126_tune(sc, chan) 1364 struct atw_softc *sc; 1365 u_int8_t chan; 1366 { 1367 int rc = 0; 1368 u_int mhz; 1369 u_int R; 1370 u_int32_t reg; 1371 u_int16_t gain; 1372 1373 #ifdef ATW_DEBUG 1374 atw_si4126_print(sc); 1375 #endif /* ATW_DEBUG */ 1376 1377 if (chan == 14) 1378 mhz = 2484; 1379 else 1380 mhz = 2412 + 5 * (chan - 1); 1381 1382 /* Tune IF to 748MHz to suit the IF LO input of the 1383 * RF2494B, which is 2 x IF. No need to set an IF divider 1384 * because an IF in 526MHz - 952MHz is allowed. 1385 * 1386 * XIN is 44.000MHz, so divide it by two to get allowable 1387 * range of 2-25MHz. SiLabs tells me that this is not 1388 * strictly necessary. 1389 */ 1390 1391 R = 44; 1392 1393 atw_rfio_enable(sc, 1); 1394 1395 /* Power-up RF, IF synthesizers. */ 1396 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1397 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1398 goto out; 1399 1400 /* If RF2 N > 2047, then set KP2 to 1. */ 1401 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1402 1403 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1404 goto out; 1405 1406 /* set LPWR, too? */ 1407 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1408 SI4126_MAIN_XINDIV2)) != 0) 1409 goto out; 1410 1411 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1412 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1413 */ 1414 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1415 goto out; 1416 1417 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1418 goto out; 1419 1420 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1421 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1422 * which has no RF1! 1423 */ 1424 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1425 goto out; 1426 1427 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1428 goto out; 1429 1430 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1431 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1432 * Now let's multiply it to mhz. So mhz - IF = N. 1433 */ 1434 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1435 goto out; 1436 1437 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1438 goto out; 1439 1440 /* wait 100us from power-up for RF, IF to settle */ 1441 DELAY(100); 1442 1443 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1444 /* XXX there is a binary driver which sends 1445 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1446 * that this enables the Si4126 by raising its PWDN#, but I 1447 * think that it actually sets the Prism RF front-end 1448 * to a special mode for channel 14. 1449 */ 1450 reg = ATW_READ(sc, ATW_GPIO); 1451 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1452 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1453 ATW_WRITE(sc, ATW_GPIO, reg); 1454 } 1455 1456 #ifdef ATW_DEBUG 1457 atw_si4126_print(sc); 1458 #endif /* ATW_DEBUG */ 1459 1460 out: 1461 atw_rfio_enable(sc, 0); 1462 1463 return rc; 1464 } 1465 1466 /* Baseline initialization of RF3000 BBP: set CCA mode, enable antenna 1467 * diversity, and write some magic. 1468 * 1469 * Call this w/ Tx/Rx suspended. 1470 */ 1471 static int 1472 atw_rf3000_init(sc) 1473 struct atw_softc *sc; 1474 { 1475 int rc = 0; 1476 1477 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1478 1479 atw_rfio_enable(sc, 1); 1480 1481 /* enable diversity */ 1482 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1483 1484 if (rc != 0) 1485 goto out; 1486 1487 /* sensible setting from a binary-only driver */ 1488 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1489 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1490 1491 if (rc != 0) 1492 goto out; 1493 1494 /* magic from a binary-only driver */ 1495 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1496 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1502 1503 if (rc != 0) 1504 goto out; 1505 1506 /* magic derived from binary-only driver */ 1507 rc = atw_rf3000_write(sc, RF3000_MAGIC0, RF3000_MAGIC0_VAL); 1508 1509 if (rc != 0) 1510 goto out; 1511 1512 rc = atw_rf3000_write(sc, RF3000_MAGIC1, RF3000_MAGIC1_VAL); 1513 1514 if (rc != 0) 1515 goto out; 1516 1517 /* CCA is acquisition sensitive */ 1518 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1519 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1520 1521 if (rc != 0) 1522 goto out; 1523 1524 out: 1525 atw_rfio_enable(sc, 0); 1526 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1527 return rc; 1528 } 1529 1530 #ifdef ATW_DEBUG 1531 static void 1532 atw_rf3000_print(sc) 1533 struct atw_softc *sc; 1534 { 1535 struct ifnet *ifp = &sc->sc_ic.ic_if; 1536 u_int addr, val; 1537 1538 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1539 return; 1540 1541 for (addr = 0x01; addr <= 0x15; addr++) { 1542 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1543 if (atw_rf3000_read(sc, addr, &val) != 0) { 1544 printf("<unknown> (quitting print-out)\n"); 1545 break; 1546 } 1547 printf("%08x\n", val); 1548 } 1549 } 1550 #endif /* ATW_DEBUG */ 1551 1552 /* Set the power settings on the BBP for channel `chan'. */ 1553 static int 1554 atw_rf3000_tune(sc, chan) 1555 struct atw_softc *sc; 1556 u_int8_t chan; 1557 { 1558 int rc = 0; 1559 u_int32_t reg; 1560 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1561 1562 atw_rfio_enable(sc, 1); 1563 1564 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1565 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1566 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1567 1568 /* odd channels: LSB, even channels: MSB */ 1569 if (chan % 2 == 1) { 1570 txpower &= 0xFF; 1571 lpf_cutoff &= 0xFF; 1572 lna_gs_thresh &= 0xFF; 1573 } else { 1574 txpower >>= 8; 1575 lpf_cutoff >>= 8; 1576 lna_gs_thresh >>= 8; 1577 } 1578 1579 #ifdef ATW_DEBUG 1580 atw_rf3000_print(sc); 1581 #endif /* ATW_DEBUG */ 1582 1583 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1584 "lna_gs_thresh %02x\n", 1585 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1586 1587 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1588 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1589 goto out; 1590 1591 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1592 goto out; 1593 1594 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1595 goto out; 1596 1597 /* from a binary-only driver. */ 1598 reg = ATW_READ(sc, ATW_PLCPHD); 1599 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1600 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1601 ATW_WRITE(sc, ATW_PLCPHD, reg); 1602 1603 #ifdef ATW_DEBUG 1604 atw_rf3000_print(sc); 1605 #endif /* ATW_DEBUG */ 1606 1607 out: 1608 atw_rfio_enable(sc, 0); 1609 1610 return rc; 1611 } 1612 1613 /* Write a register on the RF3000 baseband processor using the 1614 * registers provided by the ADM8211 for this purpose. 1615 * 1616 * Return 0 on success. 1617 */ 1618 static int 1619 atw_rf3000_write(sc, addr, val) 1620 struct atw_softc *sc; 1621 u_int addr, val; 1622 { 1623 u_int32_t reg; 1624 int i; 1625 1626 for (i = 1000; --i >= 0; ) { 1627 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1628 break; 1629 DELAY(100); 1630 } 1631 1632 if (i < 0) { 1633 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1634 return ETIMEDOUT; 1635 } 1636 1637 reg = sc->sc_bbpctl_wr | 1638 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1639 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1640 1641 ATW_WRITE(sc, ATW_BBPCTL, reg); 1642 1643 for (i = 1000; --i >= 0; ) { 1644 DELAY(100); 1645 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1646 break; 1647 } 1648 1649 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1650 1651 if (i < 0) { 1652 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1653 return ETIMEDOUT; 1654 } 1655 return 0; 1656 } 1657 1658 /* Read a register on the RF3000 baseband processor using the registers 1659 * the ADM8211 provides for this purpose. 1660 * 1661 * The 7-bit register address is addr. Record the 8-bit data in the register 1662 * in *val. 1663 * 1664 * Return 0 on success. 1665 * 1666 * XXX This does not seem to work. The ADM8211 must require more or 1667 * different magic to read the chip than to write it. Possibly some 1668 * of the magic I have derived from a binary-only driver concerns 1669 * the "chip address" (see the RF3000 manual). 1670 */ 1671 #ifdef ATW_DEBUG 1672 static int 1673 atw_rf3000_read(sc, addr, val) 1674 struct atw_softc *sc; 1675 u_int addr, *val; 1676 { 1677 u_int32_t reg; 1678 int i; 1679 1680 for (i = 1000; --i >= 0; ) { 1681 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1682 break; 1683 DELAY(100); 1684 } 1685 1686 if (i < 0) { 1687 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1688 sc->sc_dev.dv_xname); 1689 return ETIMEDOUT; 1690 } 1691 1692 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1693 1694 ATW_WRITE(sc, ATW_BBPCTL, reg); 1695 1696 for (i = 1000; --i >= 0; ) { 1697 DELAY(100); 1698 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1699 break; 1700 } 1701 1702 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1703 1704 if (i < 0) { 1705 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1706 sc->sc_dev.dv_xname, reg); 1707 return ETIMEDOUT; 1708 } 1709 if (val != NULL) 1710 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1711 return 0; 1712 } 1713 #endif /* ATW_DEBUG */ 1714 1715 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1716 * provided by the ADM8211 for that purpose. 1717 * 1718 * val is 18 bits of data, and val is the 4-bit address of the register. 1719 * 1720 * Return 0 on success. 1721 */ 1722 static int 1723 atw_si4126_write(sc, addr, val) 1724 struct atw_softc *sc; 1725 u_int addr, val; 1726 { 1727 u_int32_t reg; 1728 int i; 1729 1730 for (i = 1000; --i >= 0; ) { 1731 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1732 break; 1733 DELAY(100); 1734 } 1735 1736 if (i < 0) { 1737 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1738 sc->sc_dev.dv_xname); 1739 return ETIMEDOUT; 1740 } 1741 1742 reg = sc->sc_synctl_wr | 1743 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1744 1745 ATW_WRITE(sc, ATW_SYNCTL, reg); 1746 1747 for (i = 1000; --i >= 0; ) { 1748 DELAY(100); 1749 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1750 break; 1751 } 1752 1753 /* restore to acceptable starting condition */ 1754 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1755 1756 if (i < 0) { 1757 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1758 sc->sc_dev.dv_xname, reg); 1759 return ETIMEDOUT; 1760 } 1761 return 0; 1762 } 1763 1764 /* Read 18-bit data from the 4-bit address addr in Si4126 1765 * RF synthesizer and write the data to *val. Return 0 on success. 1766 * 1767 * XXX This does not seem to work. The ADM8211 must require more or 1768 * different magic to read the chip than to write it. 1769 */ 1770 #ifdef ATW_DEBUG 1771 static int 1772 atw_si4126_read(sc, addr, val) 1773 struct atw_softc *sc; 1774 u_int addr; 1775 u_int *val; 1776 { 1777 u_int32_t reg; 1778 int i; 1779 1780 for (i = 1000; --i >= 0; ) { 1781 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1782 break; 1783 DELAY(100); 1784 } 1785 1786 if (i < 0) { 1787 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1788 sc->sc_dev.dv_xname); 1789 return ETIMEDOUT; 1790 } 1791 1792 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1793 1794 ATW_WRITE(sc, ATW_SYNCTL, reg); 1795 1796 for (i = 1000; --i >= 0; ) { 1797 DELAY(100); 1798 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1799 break; 1800 } 1801 1802 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1803 1804 if (i < 0) { 1805 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1806 sc->sc_dev.dv_xname, reg); 1807 return ETIMEDOUT; 1808 } 1809 if (val != NULL) 1810 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1811 ATW_SYNCTL_DATA_MASK); 1812 return 0; 1813 } 1814 #endif /* ATW_DEBUG */ 1815 1816 /* XXX is the endianness correct? test. */ 1817 #define atw_calchash(addr) \ 1818 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1819 1820 /* 1821 * atw_filter_setup: 1822 * 1823 * Set the ADM8211's receive filter. 1824 */ 1825 static void 1826 atw_filter_setup(sc) 1827 struct atw_softc *sc; 1828 { 1829 struct ieee80211com *ic = &sc->sc_ic; 1830 struct ethercom *ec = &ic->ic_ec; 1831 struct ifnet *ifp = &sc->sc_ic.ic_if; 1832 int hash; 1833 u_int32_t hashes[2] = { 0, 0 }; 1834 struct ether_multi *enm; 1835 struct ether_multistep step; 1836 1837 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1838 sc->sc_dev.dv_xname, sc->sc_flags)); 1839 1840 /* 1841 * If we're running, idle the receive engine. If we're NOT running, 1842 * we're being called from atw_init(), and our writing ATW_NAR will 1843 * start the transmit and receive processes in motion. 1844 */ 1845 if (ifp->if_flags & IFF_RUNNING) 1846 atw_idle(sc, ATW_NAR_SR); 1847 1848 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1849 1850 ifp->if_flags &= ~IFF_ALLMULTI; 1851 1852 if (ifp->if_flags & IFF_PROMISC) { 1853 sc->sc_opmode |= ATW_NAR_PR; 1854 allmulti: 1855 ifp->if_flags |= IFF_ALLMULTI; 1856 goto setit; 1857 } 1858 1859 /* 1860 * Program the 64-bit multicast hash filter. 1861 */ 1862 ETHER_FIRST_MULTI(step, ec, enm); 1863 while (enm != NULL) { 1864 /* XXX */ 1865 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1866 ETHER_ADDR_LEN) != 0) 1867 goto allmulti; 1868 1869 hash = atw_calchash(enm->enm_addrlo); 1870 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1871 ETHER_NEXT_MULTI(step, enm); 1872 } 1873 1874 if (ifp->if_flags & IFF_BROADCAST) { 1875 hash = atw_calchash(etherbroadcastaddr); 1876 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1877 } 1878 1879 /* all bits set => hash is useless */ 1880 if (~(hashes[0] & hashes[1]) == 0) 1881 goto allmulti; 1882 1883 setit: 1884 if (ifp->if_flags & IFF_ALLMULTI) 1885 sc->sc_opmode |= ATW_NAR_MM; 1886 1887 /* XXX in scan mode, do not filter packets. maybe this is 1888 * unnecessary. 1889 */ 1890 if (ic->ic_state == IEEE80211_S_SCAN) 1891 sc->sc_opmode |= ATW_NAR_PR; 1892 1893 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1894 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1895 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1896 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1897 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1898 1899 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1900 } 1901 1902 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1903 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1904 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1905 * no beacon with the preferred BSSID and SSID in the number of 1906 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1907 */ 1908 static void 1909 atw_write_bssid(sc) 1910 struct atw_softc *sc; 1911 { 1912 struct ieee80211com *ic = &sc->sc_ic; 1913 u_int8_t *bssid; 1914 1915 bssid = ic->ic_bss->ni_bssid; 1916 1917 ATW_WRITE(sc, ATW_ABDA1, 1918 (ATW_READ(sc, ATW_ABDA1) & 1919 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1920 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1921 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1922 1923 ATW_WRITE(sc, ATW_BSSID0, 1924 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1925 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1926 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1927 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1928 1929 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1930 ether_sprintf(sc->sc_bssid))); 1931 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1932 1933 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1934 } 1935 1936 /* Tell the ADM8211 how many beacon intervals must pass without 1937 * receiving a beacon with the preferred BSSID & SSID set by 1938 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1939 * raised. 1940 */ 1941 static void 1942 atw_write_bcn_thresh(sc) 1943 struct atw_softc *sc; 1944 { 1945 struct ieee80211com *ic = &sc->sc_ic; 1946 int lost_bcn_thresh; 1947 1948 /* Lose link after one second or 7 beacons, whichever comes 1949 * first, but do not lose link before 2 beacons are lost. 1950 * 1951 * In host AP mode, set the lost-beacon threshold to 0. 1952 */ 1953 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1954 lost_bcn_thresh = 0; 1955 else 1956 lost_bcn_thresh = MAX(2, 1957 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss->ni_intval), 7)); 1958 1959 /* XXX resets wake-up status bits */ 1960 ATW_WRITE(sc, ATW_WCSR, 1961 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1962 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1963 1964 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1965 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1966 1967 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1968 1969 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1970 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1971 } 1972 1973 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1974 * 16-bit word. 1975 */ 1976 static void 1977 atw_write_sram(sc, ofs, buf, buflen) 1978 struct atw_softc *sc; 1979 u_int ofs; 1980 u_int8_t *buf; 1981 u_int buflen; 1982 { 1983 u_int i; 1984 u_int8_t *ptr; 1985 1986 memcpy(&sc->sc_sram[ofs], buf, buflen); 1987 1988 if (ofs % 2 != 0) { 1989 ofs--; 1990 buflen++; 1991 } 1992 1993 if (buflen % 2 != 0) 1994 buflen++; 1995 1996 assert(buflen + ofs <= ATW_SRAM_SIZE); 1997 1998 ptr = &sc->sc_sram[ofs]; 1999 2000 for (i = 0; i < buflen; i += 2) { 2001 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2002 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2003 DELAY(atw_writewep_delay); 2004 2005 ATW_WRITE(sc, ATW_WESK, 2006 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2007 DELAY(atw_writewep_delay); 2008 } 2009 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2010 2011 if (sc->sc_if.if_flags & IFF_DEBUG) { 2012 int n_octets = 0; 2013 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2014 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2015 for (i = 0; i < buflen; i++) { 2016 printf(" %02x", ptr[i]); 2017 if (++n_octets % 24 == 0) 2018 printf("\n"); 2019 } 2020 if (n_octets % 24 != 0) 2021 printf("\n"); 2022 } 2023 } 2024 2025 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2026 static void 2027 atw_write_wep(sc) 2028 struct atw_softc *sc; 2029 { 2030 struct ieee80211com *ic = &sc->sc_ic; 2031 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2032 u_int8_t buf[IEEE80211_WEP_NKID] 2033 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2034 u_int32_t reg; 2035 int i; 2036 2037 sc->sc_wepctl = 0; 2038 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2039 2040 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2041 return; 2042 2043 memset(&buf[0][0], 0, sizeof(buf)); 2044 2045 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2046 if (ic->ic_nw_keys[i].wk_len > 5) { 2047 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2048 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2049 buf[i][1] = ATW_WEP_ENABLED; 2050 } else { 2051 buf[i][1] = 0; 2052 continue; 2053 } 2054 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2055 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2056 ic->ic_nw_keys[i].wk_len - 1); 2057 } 2058 2059 reg = ATW_READ(sc, ATW_MACTEST); 2060 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2061 reg &= ~ATW_MACTEST_KEYID_MASK; 2062 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2063 ATW_WRITE(sc, ATW_MACTEST, reg); 2064 2065 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2066 * throughout.) 2067 */ 2068 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2069 if (sc->sc_if.if_flags & IFF_LINK2) 2070 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2071 2072 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2073 sizeof(buf)); 2074 } 2075 2076 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2077 2078 static void 2079 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2080 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2081 { 2082 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2083 2084 switch (subtype) { 2085 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2086 /* do nothing: hardware answers probe request */ 2087 break; 2088 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2089 case IEEE80211_FC0_SUBTYPE_BEACON: 2090 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2091 break; 2092 default: 2093 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2094 break; 2095 } 2096 return; 2097 } 2098 2099 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2100 * of IBSSs with like SSID/channel but different BSSID. It joins the 2101 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2102 * convention. Possibly the ADMtek chip does this for us; I will have 2103 * to test to find out. 2104 * 2105 * XXX we should add the duration field of the received beacon to 2106 * the TSF time it contains before comparing it with the ADM8211's 2107 * TSF. 2108 */ 2109 static void 2110 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2111 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2112 { 2113 struct atw_softc *sc; 2114 struct ieee80211_frame *wh; 2115 u_int64_t tsft, bcn_tsft; 2116 u_int32_t tsftl, tsfth; 2117 int do_print = 0; 2118 2119 sc = (struct atw_softc*)ic->ic_if.if_softc; 2120 2121 if (ic->ic_if.if_flags & IFF_DEBUG) 2122 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2123 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2124 2125 wh = mtod(m0, struct ieee80211_frame *); 2126 2127 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2128 2129 if (ic->ic_state != IEEE80211_S_RUN) { 2130 if (do_print) 2131 printf("%s: atw_recv_beacon: not running\n", 2132 sc->sc_dev.dv_xname); 2133 return; 2134 } 2135 2136 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2137 ic->ic_bss->ni_chan)) == NULL) { 2138 if (do_print) 2139 printf("%s: atw_recv_beacon: no node %s\n", 2140 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2141 return; 2142 } 2143 2144 if (ieee80211_match_bss(ic, ni) != 0) { 2145 if (do_print) 2146 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2147 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2148 return; 2149 } 2150 2151 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2152 return; 2153 2154 if (do_print) 2155 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2156 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2157 2158 if (ic->ic_opmode != IEEE80211_M_IBSS) 2159 return; 2160 2161 /* If we read TSFTL right before rollover, we read a TSF timer 2162 * that is too high rather than too low. This prevents a spurious 2163 * synchronization down the line, however, our IBSS could suffer 2164 * from a creeping TSF.... 2165 */ 2166 tsftl = ATW_READ(sc, ATW_TSFTL); 2167 tsfth = ATW_READ(sc, ATW_TSFTH); 2168 2169 tsft = (u_int64_t)tsfth << 32 | tsftl; 2170 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2171 2172 if (do_print) 2173 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2174 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2175 2176 /* we are faster, let the other guy catch up */ 2177 if (bcn_tsft < tsft) 2178 return; 2179 2180 if (do_print) 2181 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2182 ether_sprintf(wh->i_addr2)); 2183 2184 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2185 2186 #if 0 2187 atw_tsf(sc); 2188 #endif 2189 2190 /* negotiate rates with new IBSS */ 2191 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2192 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2193 if (ni->ni_rates.rs_nrates == 0) { 2194 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2195 ether_sprintf(ni->ni_bssid)); 2196 return; 2197 } 2198 2199 if (do_print) { 2200 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2201 ether_sprintf(ic->ic_bss->ni_bssid)); 2202 printf("%s ", ether_sprintf(ni->ni_bssid)); 2203 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2204 } 2205 2206 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2207 2208 atw_write_bssid(sc); 2209 atw_write_bcn_thresh(sc); 2210 atw_start_beacon(sc, 1); 2211 } 2212 2213 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2214 * In ad hoc mode, the SSID is written to the beacons sent by the 2215 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2216 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2217 * indications. 2218 */ 2219 static void 2220 atw_write_ssid(sc) 2221 struct atw_softc *sc; 2222 { 2223 struct ieee80211com *ic = &sc->sc_ic; 2224 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2225 u_int8_t buf[1 /* length */ + IEEE80211_NWID_LEN + 2226 1 /* for a round number */]; 2227 2228 memset(buf, 0, sizeof(buf)); 2229 buf[0] = ic->ic_bss->ni_esslen; 2230 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2231 2232 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2233 } 2234 2235 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2236 * In ad hoc mode, the supported rates are written to beacons sent by the 2237 * ADM8211. 2238 */ 2239 static void 2240 atw_write_sup_rates(sc) 2241 struct atw_softc *sc; 2242 { 2243 struct ieee80211com *ic = &sc->sc_ic; 2244 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2245 * supported rates 2246 */ 2247 u_int8_t buf[1 /* length */ + IEEE80211_RATE_SIZE + 2248 1 /* for a round number */]; 2249 2250 memset(buf, 0, sizeof(buf)); 2251 2252 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2253 2254 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2255 ic->ic_bss->ni_rates.rs_nrates); 2256 2257 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2258 } 2259 2260 /* Start/stop sending beacons. */ 2261 void 2262 atw_start_beacon(struct atw_softc *sc, int start) 2263 { 2264 struct ieee80211com *ic = &sc->sc_ic; 2265 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2266 2267 if (ATW_IS_ENABLED(sc) == 0) 2268 return; 2269 2270 len = capinfo = 0; 2271 2272 /* start beacons */ 2273 len = sizeof(struct ieee80211_frame) + 2274 8 /* timestamp */ + 2 /* beacon interval */ + 2275 2 /* capability info */ + 2276 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2277 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2278 3 /* DS parameters */ + 2279 IEEE80211_CRC_LEN; 2280 2281 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2282 2283 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2284 2285 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2286 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2287 2288 if (!start) 2289 return; 2290 2291 /* TBD use ni_capinfo */ 2292 2293 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2294 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2295 if (ic->ic_flags & IEEE80211_F_WEPON) 2296 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2297 2298 switch (ic->ic_opmode) { 2299 case IEEE80211_M_IBSS: 2300 len += 4; /* IBSS parameters */ 2301 capinfo |= IEEE80211_CAPINFO_IBSS; 2302 break; 2303 case IEEE80211_M_HOSTAP: 2304 /* XXX 6-byte minimum TIM */ 2305 len += atw_beacon_len_adjust; 2306 capinfo |= IEEE80211_CAPINFO_ESS; 2307 break; 2308 default: 2309 return; 2310 } 2311 2312 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2313 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2314 2315 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2316 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2317 2318 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2319 sc->sc_dev.dv_xname, reg_bcnt)); 2320 2321 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2322 sc->sc_dev.dv_xname, reg_cap1)); 2323 } 2324 2325 /* First beacon was sent at time 0 microseconds, current time is 2326 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2327 * microseconds. Return the expected time in microseconds for the 2328 * beacon after next. 2329 */ 2330 static __inline u_int64_t 2331 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2332 { 2333 return tsft + (tbtt - tsft % tbtt); 2334 } 2335 2336 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2337 * the ieee80211com. 2338 * 2339 * Predict the next target beacon transmission time (TBTT) and 2340 * write it to the ADM8211. 2341 */ 2342 static void 2343 atw_tsf(struct atw_softc *sc) 2344 { 2345 #define TBTTOFS 20 /* TU */ 2346 2347 struct ieee80211com *ic = &sc->sc_ic; 2348 u_int64_t tsft, tbtt; 2349 2350 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2351 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2352 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2353 tsft = ATW_READ(sc, ATW_TSFTH); 2354 tsft <<= 32; 2355 tsft |= ATW_READ(sc, ATW_TSFTL); 2356 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2357 } else 2358 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2359 2360 tbtt = atw_predict_beacon(tsft, 2361 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2362 2363 /* skip one more beacon so that the TBTT cannot pass before 2364 * we've programmed it, and also so that we can subtract a 2365 * few TU so that we wake a little before TBTT. 2366 */ 2367 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2368 2369 /* wake up a little early */ 2370 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2371 2372 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2373 sc->sc_dev.dv_xname, tsft, tbtt)); 2374 2375 ATW_WRITE(sc, ATW_TOFS1, 2376 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2377 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2378 LSHIFT( 2379 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2380 ATW_TOFS1_TBTTPRE_MASK)); 2381 #undef TBTTOFS 2382 } 2383 2384 static void 2385 atw_next_scan(void *arg) 2386 { 2387 struct atw_softc *sc = arg; 2388 struct ieee80211com *ic = &sc->sc_ic; 2389 struct ifnet *ifp = &ic->ic_if; 2390 int s; 2391 2392 /* don't call atw_start w/o network interrupts blocked */ 2393 s = splnet(); 2394 if (ic->ic_state == IEEE80211_S_SCAN) 2395 ieee80211_next_scan(ifp); 2396 splx(s); 2397 } 2398 2399 /* Synchronize the hardware state with the software state. */ 2400 static int 2401 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2402 { 2403 struct ifnet *ifp = &ic->ic_if; 2404 struct atw_softc *sc = ifp->if_softc; 2405 enum ieee80211_state ostate; 2406 int error; 2407 2408 ostate = ic->ic_state; 2409 2410 if (nstate == IEEE80211_S_INIT) { 2411 callout_stop(&sc->sc_scan_ch); 2412 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2413 atw_start_beacon(sc, 0); 2414 return (*sc->sc_newstate)(ic, nstate, arg); 2415 } 2416 2417 if ((error = atw_tune(sc)) != 0) 2418 return error; 2419 2420 switch (nstate) { 2421 case IEEE80211_S_ASSOC: 2422 break; 2423 case IEEE80211_S_INIT: 2424 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2425 break; 2426 case IEEE80211_S_SCAN: 2427 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2428 atw_write_bssid(sc); 2429 2430 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2431 atw_next_scan, sc); 2432 2433 break; 2434 case IEEE80211_S_RUN: 2435 if (ic->ic_opmode == IEEE80211_M_STA) 2436 break; 2437 /*FALLTHROUGH*/ 2438 case IEEE80211_S_AUTH: 2439 atw_write_bssid(sc); 2440 atw_write_bcn_thresh(sc); 2441 atw_write_ssid(sc); 2442 atw_write_sup_rates(sc); 2443 2444 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2445 ic->ic_opmode == IEEE80211_M_MONITOR) 2446 break; 2447 2448 /* set listen interval 2449 * XXX do software units agree w/ hardware? 2450 */ 2451 ATW_WRITE(sc, ATW_BPLI, 2452 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2453 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2454 ATW_BPLI_LI_MASK)); 2455 2456 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2457 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2458 2459 atw_tsf(sc); 2460 break; 2461 } 2462 2463 if (ostate == IEEE80211_S_SCAN && nstate != IEEE80211_S_SCAN) 2464 callout_stop(&sc->sc_scan_ch); 2465 2466 if (nstate == IEEE80211_S_RUN && 2467 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2468 ic->ic_opmode == IEEE80211_M_IBSS)) 2469 atw_start_beacon(sc, 1); 2470 else 2471 atw_start_beacon(sc, 0); 2472 2473 return (*sc->sc_newstate)(ic, nstate, arg); 2474 } 2475 2476 /* 2477 * atw_add_rxbuf: 2478 * 2479 * Add a receive buffer to the indicated descriptor. 2480 */ 2481 int 2482 atw_add_rxbuf(sc, idx) 2483 struct atw_softc *sc; 2484 int idx; 2485 { 2486 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2487 struct mbuf *m; 2488 int error; 2489 2490 MGETHDR(m, M_DONTWAIT, MT_DATA); 2491 if (m == NULL) 2492 return (ENOBUFS); 2493 2494 MCLGET(m, M_DONTWAIT); 2495 if ((m->m_flags & M_EXT) == 0) { 2496 m_freem(m); 2497 return (ENOBUFS); 2498 } 2499 2500 if (rxs->rxs_mbuf != NULL) 2501 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2502 2503 rxs->rxs_mbuf = m; 2504 2505 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2506 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2507 BUS_DMA_READ|BUS_DMA_NOWAIT); 2508 if (error) { 2509 printf("%s: can't load rx DMA map %d, error = %d\n", 2510 sc->sc_dev.dv_xname, idx, error); 2511 panic("atw_add_rxbuf"); /* XXX */ 2512 } 2513 2514 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2515 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2516 2517 ATW_INIT_RXDESC(sc, idx); 2518 2519 return (0); 2520 } 2521 2522 /* 2523 * atw_stop: [ ifnet interface function ] 2524 * 2525 * Stop transmission on the interface. 2526 */ 2527 void 2528 atw_stop(ifp, disable) 2529 struct ifnet *ifp; 2530 int disable; 2531 { 2532 struct atw_softc *sc = ifp->if_softc; 2533 struct ieee80211com *ic = &sc->sc_ic; 2534 struct atw_txsoft *txs; 2535 2536 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2537 2538 /* Disable interrupts. */ 2539 ATW_WRITE(sc, ATW_IER, 0); 2540 2541 /* Stop the transmit and receive processes. */ 2542 sc->sc_opmode = 0; 2543 ATW_WRITE(sc, ATW_NAR, 0); 2544 ATW_WRITE(sc, ATW_TDBD, 0); 2545 ATW_WRITE(sc, ATW_TDBP, 0); 2546 ATW_WRITE(sc, ATW_RDB, 0); 2547 2548 /* 2549 * Release any queued transmit buffers. 2550 */ 2551 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2552 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2553 if (txs->txs_mbuf != NULL) { 2554 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2555 m_freem(txs->txs_mbuf); 2556 txs->txs_mbuf = NULL; 2557 } 2558 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2559 } 2560 2561 if (disable) { 2562 atw_rxdrain(sc); 2563 atw_disable(sc); 2564 } 2565 2566 /* 2567 * Mark the interface down and cancel the watchdog timer. 2568 */ 2569 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2570 ifp->if_timer = 0; 2571 2572 /* XXX */ 2573 atw_reset(sc); 2574 } 2575 2576 /* 2577 * atw_rxdrain: 2578 * 2579 * Drain the receive queue. 2580 */ 2581 void 2582 atw_rxdrain(sc) 2583 struct atw_softc *sc; 2584 { 2585 struct atw_rxsoft *rxs; 2586 int i; 2587 2588 for (i = 0; i < ATW_NRXDESC; i++) { 2589 rxs = &sc->sc_rxsoft[i]; 2590 if (rxs->rxs_mbuf == NULL) 2591 continue; 2592 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2593 m_freem(rxs->rxs_mbuf); 2594 rxs->rxs_mbuf = NULL; 2595 } 2596 } 2597 2598 /* 2599 * atw_detach: 2600 * 2601 * Detach an ADM8211 interface. 2602 */ 2603 int 2604 atw_detach(sc) 2605 struct atw_softc *sc; 2606 { 2607 struct ifnet *ifp = &sc->sc_ic.ic_if; 2608 struct atw_rxsoft *rxs; 2609 struct atw_txsoft *txs; 2610 int i; 2611 2612 /* 2613 * Succeed now if there isn't any work to do. 2614 */ 2615 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2616 return (0); 2617 2618 ieee80211_ifdetach(ifp); 2619 if_detach(ifp); 2620 2621 for (i = 0; i < ATW_NRXDESC; i++) { 2622 rxs = &sc->sc_rxsoft[i]; 2623 if (rxs->rxs_mbuf != NULL) { 2624 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2625 m_freem(rxs->rxs_mbuf); 2626 rxs->rxs_mbuf = NULL; 2627 } 2628 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2629 } 2630 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2631 txs = &sc->sc_txsoft[i]; 2632 if (txs->txs_mbuf != NULL) { 2633 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2634 m_freem(txs->txs_mbuf); 2635 txs->txs_mbuf = NULL; 2636 } 2637 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2638 } 2639 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2640 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2641 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2642 sizeof(struct atw_control_data)); 2643 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2644 2645 shutdownhook_disestablish(sc->sc_sdhook); 2646 powerhook_disestablish(sc->sc_powerhook); 2647 2648 if (sc->sc_srom) 2649 free(sc->sc_srom, M_DEVBUF); 2650 2651 return (0); 2652 } 2653 2654 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2655 void 2656 atw_shutdown(arg) 2657 void *arg; 2658 { 2659 struct atw_softc *sc = arg; 2660 2661 atw_stop(&sc->sc_ic.ic_if, 1); 2662 } 2663 2664 int 2665 atw_intr(arg) 2666 void *arg; 2667 { 2668 struct atw_softc *sc = arg; 2669 struct ifnet *ifp = &sc->sc_ic.ic_if; 2670 u_int32_t status, rxstatus, txstatus, linkstatus; 2671 int handled = 0, txthresh; 2672 2673 #ifdef DEBUG 2674 if (ATW_IS_ENABLED(sc) == 0) 2675 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2676 #endif 2677 2678 /* 2679 * If the interface isn't running, the interrupt couldn't 2680 * possibly have come from us. 2681 */ 2682 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2683 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2684 return (0); 2685 2686 for (;;) { 2687 status = ATW_READ(sc, ATW_STSR); 2688 2689 if (status) 2690 ATW_WRITE(sc, ATW_STSR, status); 2691 2692 if (sc->sc_intr_ack != NULL) 2693 (*sc->sc_intr_ack)(sc); 2694 2695 #ifdef ATW_DEBUG 2696 #define PRINTINTR(flag) do { \ 2697 if ((status & flag) != 0) { \ 2698 printf("%s" #flag, delim); \ 2699 delim = ","; \ 2700 } \ 2701 } while (0) 2702 2703 if (atw_debug > 1 && status) { 2704 const char *delim = "<"; 2705 2706 printf("%s: reg[STSR] = %x", 2707 sc->sc_dev.dv_xname, status); 2708 2709 PRINTINTR(ATW_INTR_FBE); 2710 PRINTINTR(ATW_INTR_LINKOFF); 2711 PRINTINTR(ATW_INTR_LINKON); 2712 PRINTINTR(ATW_INTR_RCI); 2713 PRINTINTR(ATW_INTR_RDU); 2714 PRINTINTR(ATW_INTR_RPS); 2715 PRINTINTR(ATW_INTR_TCI); 2716 PRINTINTR(ATW_INTR_TDU); 2717 PRINTINTR(ATW_INTR_TLT); 2718 PRINTINTR(ATW_INTR_TPS); 2719 PRINTINTR(ATW_INTR_TRT); 2720 PRINTINTR(ATW_INTR_TUF); 2721 PRINTINTR(ATW_INTR_BCNTC); 2722 PRINTINTR(ATW_INTR_ATIME); 2723 PRINTINTR(ATW_INTR_TBTT); 2724 PRINTINTR(ATW_INTR_TSCZ); 2725 PRINTINTR(ATW_INTR_TSFTF); 2726 printf(">\n"); 2727 } 2728 #undef PRINTINTR 2729 #endif /* ATW_DEBUG */ 2730 2731 if ((status & sc->sc_inten) == 0) 2732 break; 2733 2734 handled = 1; 2735 2736 rxstatus = status & sc->sc_rxint_mask; 2737 txstatus = status & sc->sc_txint_mask; 2738 linkstatus = status & sc->sc_linkint_mask; 2739 2740 if (linkstatus) { 2741 atw_linkintr(sc, linkstatus); 2742 } 2743 2744 if (rxstatus) { 2745 /* Grab any new packets. */ 2746 atw_rxintr(sc); 2747 2748 if (rxstatus & ATW_INTR_RDU) { 2749 printf("%s: receive ring overrun\n", 2750 sc->sc_dev.dv_xname); 2751 /* Get the receive process going again. */ 2752 ATW_WRITE(sc, ATW_RDR, 0x1); 2753 break; 2754 } 2755 } 2756 2757 if (txstatus) { 2758 /* Sweep up transmit descriptors. */ 2759 atw_txintr(sc); 2760 2761 if (txstatus & ATW_INTR_TLT) 2762 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2763 sc->sc_dev.dv_xname)); 2764 2765 if (txstatus & ATW_INTR_TRT) 2766 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2767 sc->sc_dev.dv_xname)); 2768 2769 /* If Tx under-run, increase our transmit threshold 2770 * if another is available. 2771 */ 2772 txthresh = sc->sc_txthresh + 1; 2773 if ((txstatus & ATW_INTR_TUF) && 2774 sc->sc_txth[txthresh].txth_name != NULL) { 2775 /* Idle the transmit process. */ 2776 atw_idle(sc, ATW_NAR_ST); 2777 2778 sc->sc_txthresh = txthresh; 2779 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2780 sc->sc_opmode |= 2781 sc->sc_txth[txthresh].txth_opmode; 2782 printf("%s: transmit underrun; new " 2783 "threshold: %s\n", sc->sc_dev.dv_xname, 2784 sc->sc_txth[txthresh].txth_name); 2785 2786 /* Set the new threshold and restart 2787 * the transmit process. 2788 */ 2789 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2790 /* XXX Log every Nth underrun from 2791 * XXX now on? 2792 */ 2793 } 2794 } 2795 2796 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2797 if (status & ATW_INTR_TPS) 2798 printf("%s: transmit process stopped\n", 2799 sc->sc_dev.dv_xname); 2800 if (status & ATW_INTR_RPS) 2801 printf("%s: receive process stopped\n", 2802 sc->sc_dev.dv_xname); 2803 (void)atw_init(ifp); 2804 break; 2805 } 2806 2807 if (status & ATW_INTR_FBE) { 2808 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2809 (void)atw_init(ifp); 2810 break; 2811 } 2812 2813 /* 2814 * Not handled: 2815 * 2816 * Transmit buffer unavailable -- normal 2817 * condition, nothing to do, really. 2818 * 2819 * Early receive interrupt -- not available on 2820 * all chips, we just use RI. We also only 2821 * use single-segment receive DMA, so this 2822 * is mostly useless. 2823 * 2824 * TBD others 2825 */ 2826 } 2827 2828 /* Try to get more packets going. */ 2829 atw_start(ifp); 2830 2831 return (handled); 2832 } 2833 2834 /* 2835 * atw_idle: 2836 * 2837 * Cause the transmit and/or receive processes to go idle. 2838 * 2839 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2840 * process in STSR if I clear SR or ST after the process has already 2841 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2842 * do not seem to be too reliable. Perhaps I have the sense of the 2843 * Rx bits switched with the Tx bits? 2844 */ 2845 void 2846 atw_idle(sc, bits) 2847 struct atw_softc *sc; 2848 u_int32_t bits; 2849 { 2850 u_int32_t ackmask = 0, opmode, stsr, test0; 2851 int i, s; 2852 2853 /* without this, somehow we run concurrently w/ interrupt handler */ 2854 s = splnet(); 2855 2856 opmode = sc->sc_opmode & ~bits; 2857 2858 if (bits & ATW_NAR_SR) 2859 ackmask |= ATW_INTR_RPS; 2860 2861 if (bits & ATW_NAR_ST) { 2862 ackmask |= ATW_INTR_TPS; 2863 /* set ATW_NAR_HF to flush TX FIFO. */ 2864 opmode |= ATW_NAR_HF; 2865 } 2866 2867 ATW_WRITE(sc, ATW_NAR, opmode); 2868 2869 for (i = 0; i < 1000; i++) { 2870 stsr = ATW_READ(sc, ATW_STSR); 2871 if ((stsr & ackmask) == ackmask) 2872 break; 2873 DELAY(10); 2874 } 2875 2876 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2877 2878 if ((stsr & ackmask) == ackmask) 2879 goto out; 2880 2881 test0 = ATW_READ(sc, ATW_TEST0); 2882 2883 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2884 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2885 printf("%s: transmit process not idle [%s]\n", 2886 sc->sc_dev.dv_xname, 2887 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2888 printf("%s: bits %08x test0 %08x stsr %08x\n", 2889 sc->sc_dev.dv_xname, bits, test0, stsr); 2890 } 2891 2892 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2893 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2894 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2895 sc->sc_dev.dv_xname, 2896 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2897 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2898 sc->sc_dev.dv_xname, bits, test0, stsr)); 2899 } 2900 out: 2901 splx(s); 2902 return; 2903 } 2904 2905 /* 2906 * atw_linkintr: 2907 * 2908 * Helper; handle link-status interrupts. 2909 */ 2910 void 2911 atw_linkintr(sc, linkstatus) 2912 struct atw_softc *sc; 2913 u_int32_t linkstatus; 2914 { 2915 struct ieee80211com *ic = &sc->sc_ic; 2916 2917 if (ic->ic_state != IEEE80211_S_RUN) 2918 return; 2919 2920 if (linkstatus & ATW_INTR_LINKON) { 2921 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2922 sc->sc_rescan_timer = 0; 2923 } else if (linkstatus & ATW_INTR_LINKOFF) { 2924 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2925 switch (ic->ic_opmode) { 2926 case IEEE80211_M_IBSS: 2927 if (ic->ic_flags & IEEE80211_F_SIBSS) 2928 return; 2929 /* FALL THROUGH */ 2930 case IEEE80211_M_STA: 2931 sc->sc_rescan_timer = 3; 2932 ic->ic_if.if_timer = 1; 2933 break; 2934 default: 2935 break; 2936 } 2937 } 2938 } 2939 2940 /* 2941 * atw_rxintr: 2942 * 2943 * Helper; handle receive interrupts. 2944 */ 2945 void 2946 atw_rxintr(sc) 2947 struct atw_softc *sc; 2948 { 2949 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2950 struct ieee80211com *ic = &sc->sc_ic; 2951 struct ieee80211_node *ni; 2952 struct ieee80211_frame *wh; 2953 struct ifnet *ifp = &ic->ic_if; 2954 struct atw_rxsoft *rxs; 2955 struct mbuf *m; 2956 u_int32_t rxstat; 2957 int i, len, rate, rate0, rssi; 2958 2959 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2960 rxs = &sc->sc_rxsoft[i]; 2961 2962 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2963 2964 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2965 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2966 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2967 2968 if (rxstat & ATW_RXSTAT_OWN) 2969 break; /* We have processed all receive buffers. */ 2970 2971 ATW_DPRINTF3(("%s: rssi %d\n", sc->sc_dev.dv_xname, rssi)); 2972 2973 /* 2974 * Make sure the packet fit in one buffer. This should 2975 * always be the case. 2976 */ 2977 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2978 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2979 printf("%s: incoming packet spilled, resetting\n", 2980 sc->sc_dev.dv_xname); 2981 (void)atw_init(ifp); 2982 return; 2983 } 2984 2985 /* 2986 * If an error occurred, update stats, clear the status 2987 * word, and leave the packet buffer in place. It will 2988 * simply be reused the next time the ring comes around. 2989 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2990 * error. 2991 */ 2992 2993 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2994 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2995 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2996 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2997 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2998 ATW_RXSTAT_ICVE)) != 0)) { 2999 #define PRINTERR(bit, str) \ 3000 if (rxstat & (bit)) \ 3001 printf("%s: receive error: %s\n", \ 3002 sc->sc_dev.dv_xname, str) 3003 ifp->if_ierrors++; 3004 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3005 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3006 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3007 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3008 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3009 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3010 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3011 #undef PRINTERR 3012 ATW_INIT_RXDESC(sc, i); 3013 continue; 3014 } 3015 3016 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3017 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3018 3019 /* 3020 * No errors; receive the packet. Note the ADM8211 3021 * includes the CRC in promiscuous mode. 3022 */ 3023 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3024 3025 /* 3026 * Allocate a new mbuf cluster. If that fails, we are 3027 * out of memory, and must drop the packet and recycle 3028 * the buffer that's already attached to this descriptor. 3029 */ 3030 m = rxs->rxs_mbuf; 3031 if (atw_add_rxbuf(sc, i) != 0) { 3032 ifp->if_ierrors++; 3033 ATW_INIT_RXDESC(sc, i); 3034 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3035 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3036 continue; 3037 } 3038 3039 ifp->if_ipackets++; 3040 if (sc->sc_opmode & ATW_NAR_PR) 3041 m->m_flags |= M_HASFCS; 3042 m->m_pkthdr.rcvif = ifp; 3043 m->m_pkthdr.len = m->m_len = len; 3044 3045 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3046 rate = 0; 3047 else 3048 rate = rate_tbl[rate0]; 3049 3050 #if NBPFILTER > 0 3051 /* 3052 * Pass this up to any BPF listeners, but only 3053 * pass it up the stack if it's for us. 3054 */ 3055 if (sc->sc_radiobpf) { 3056 /* TBD capture DLT_IEEE802_11_RADIO */ 3057 } 3058 #endif /* NPBFILTER > 0 */ 3059 3060 wh = mtod(m, struct ieee80211_frame *); 3061 ni = ieee80211_find_rxnode(ic, wh); 3062 ieee80211_input(ifp, m, ni, rssi, 0); 3063 /* 3064 * The frame may have caused the node to be marked for 3065 * reclamation (e.g. in response to a DEAUTH message) 3066 * so use free_node here instead of unref_node. 3067 */ 3068 if (ni == ic->ic_bss) 3069 ieee80211_unref_node(&ni); 3070 else 3071 ieee80211_free_node(ic, ni); 3072 } 3073 3074 /* Update the receive pointer. */ 3075 sc->sc_rxptr = i; 3076 } 3077 3078 /* 3079 * atw_txintr: 3080 * 3081 * Helper; handle transmit interrupts. 3082 */ 3083 void 3084 atw_txintr(sc) 3085 struct atw_softc *sc; 3086 { 3087 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3088 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3089 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3090 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3091 3092 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3093 struct ifnet *ifp = &sc->sc_ic.ic_if; 3094 struct atw_txsoft *txs; 3095 u_int32_t txstat; 3096 3097 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3098 sc->sc_dev.dv_xname, sc->sc_flags)); 3099 3100 ifp->if_flags &= ~IFF_OACTIVE; 3101 3102 /* 3103 * Go through our Tx list and free mbufs for those 3104 * frames that have been transmitted. 3105 */ 3106 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3107 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3108 txs->txs_ndescs, 3109 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3110 3111 #ifdef ATW_DEBUG 3112 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3113 int i; 3114 printf(" txsoft %p transmit chain:\n", txs); 3115 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3116 printf(" descriptor %d:\n", i); 3117 printf(" at_status: 0x%08x\n", 3118 le32toh(sc->sc_txdescs[i].at_stat)); 3119 printf(" at_flags: 0x%08x\n", 3120 le32toh(sc->sc_txdescs[i].at_flags)); 3121 printf(" at_buf1: 0x%08x\n", 3122 le32toh(sc->sc_txdescs[i].at_buf1)); 3123 printf(" at_buf2: 0x%08x\n", 3124 le32toh(sc->sc_txdescs[i].at_buf2)); 3125 if (i == txs->txs_lastdesc) 3126 break; 3127 } 3128 } 3129 #endif 3130 3131 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3132 if (txstat & ATW_TXSTAT_OWN) 3133 break; 3134 3135 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3136 3137 sc->sc_txfree += txs->txs_ndescs; 3138 3139 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3140 0, txs->txs_dmamap->dm_mapsize, 3141 BUS_DMASYNC_POSTWRITE); 3142 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3143 m_freem(txs->txs_mbuf); 3144 txs->txs_mbuf = NULL; 3145 3146 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3147 3148 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3149 (txstat & TXSTAT_ERRMASK) != 0) { 3150 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3151 txstat_buf, sizeof(txstat_buf)); 3152 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3153 txstat_buf, 3154 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3155 } 3156 3157 /* 3158 * Check for errors and collisions. 3159 */ 3160 if (txstat & ATW_TXSTAT_TUF) 3161 sc->sc_stats.ts_tx_tuf++; 3162 if (txstat & ATW_TXSTAT_TLT) 3163 sc->sc_stats.ts_tx_tlt++; 3164 if (txstat & ATW_TXSTAT_TRT) 3165 sc->sc_stats.ts_tx_trt++; 3166 if (txstat & ATW_TXSTAT_TRO) 3167 sc->sc_stats.ts_tx_tro++; 3168 if (txstat & ATW_TXSTAT_SOFBR) { 3169 sc->sc_stats.ts_tx_sofbr++; 3170 } 3171 3172 if ((txstat & ATW_TXSTAT_ES) == 0) 3173 ifp->if_collisions += 3174 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3175 else 3176 ifp->if_oerrors++; 3177 3178 ifp->if_opackets++; 3179 } 3180 3181 /* 3182 * If there are no more pending transmissions, cancel the watchdog 3183 * timer. 3184 */ 3185 if (txs == NULL) 3186 sc->sc_tx_timer = 0; 3187 #undef TXSTAT_ERRMASK 3188 #undef TXSTAT_FMT 3189 } 3190 3191 /* 3192 * atw_watchdog: [ifnet interface function] 3193 * 3194 * Watchdog timer handler. 3195 */ 3196 void 3197 atw_watchdog(ifp) 3198 struct ifnet *ifp; 3199 { 3200 struct atw_softc *sc = ifp->if_softc; 3201 struct ieee80211com *ic = &sc->sc_ic; 3202 3203 ifp->if_timer = 0; 3204 if (ATW_IS_ENABLED(sc) == 0) 3205 return; 3206 3207 if (sc->sc_rescan_timer) { 3208 if (--sc->sc_rescan_timer == 0) 3209 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3210 } 3211 if (sc->sc_tx_timer) { 3212 if (--sc->sc_tx_timer == 0 && 3213 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3214 printf("%s: transmit timeout\n", ifp->if_xname); 3215 ifp->if_oerrors++; 3216 (void)atw_init(ifp); 3217 atw_start(ifp); 3218 } 3219 } 3220 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3221 ifp->if_timer = 1; 3222 ieee80211_watchdog(ifp); 3223 } 3224 3225 /* Compute the 802.11 Duration field and the PLCP Length fields for 3226 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3227 * Write the fields to the ADM8211 Tx header, frm. 3228 * 3229 * TBD use the fragmentation threshold to find the right duration for 3230 * the first & last fragments. 3231 * 3232 * TBD make certain of the duration fields applied by the ADM8211 to each 3233 * fragment. I think that the ADM8211 knows how to subtract the CTS 3234 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3235 * I also think that the ADM8211 does *some* arithmetic for us, because 3236 * otherwise I think we would have to set a first duration for CTS/first 3237 * fragment, a second duration for fragments between the first and the 3238 * last, and a third duration for the last fragment. 3239 * 3240 * TBD make certain that duration fields reflect addition of FCS/WEP 3241 * and correct duration arithmetic as necessary. 3242 */ 3243 static void 3244 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3245 int len) 3246 { 3247 int remainder; 3248 3249 /* deal also with encrypted fragments */ 3250 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3251 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3252 sc->sc_dev.dv_xname)); 3253 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3254 IEEE80211_WEP_CRCLEN; 3255 } 3256 3257 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3258 * duration (XXX added by MAC?). 3259 */ 3260 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3261 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3262 3263 if (rate <= 4) 3264 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3265 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3266 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3267 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3268 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3269 else 3270 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3271 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3272 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3273 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3274 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3275 3276 /* lengthen duration if long preamble */ 3277 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3278 frm->atw_head_dur += 3279 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3280 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3281 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3282 IEEE80211_DUR_DS_FAST_PLCPHDR); 3283 3284 if (remainder != 0) 3285 frm->atw_head_dur++; 3286 3287 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3288 (rate == 2 || rate == 4)) { 3289 /* derived from Linux: how could this be right? */ 3290 frm->atw_head_plcplen = frm->atw_head_dur; 3291 } else { 3292 frm->atw_head_plcplen = (16 * len) / rate; 3293 remainder = (80 * len) % (rate * 5); 3294 3295 if (remainder != 0) { 3296 frm->atw_head_plcplen++; 3297 3298 /* XXX magic */ 3299 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3300 rate == 22 && remainder <= 30) 3301 frm->atw_head_plcplen |= 0x8000; 3302 } 3303 } 3304 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3305 htole16(frm->atw_head_plcplen); 3306 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3307 } 3308 3309 #ifdef ATW_DEBUG 3310 static void 3311 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3312 { 3313 struct atw_softc *sc = ifp->if_softc; 3314 struct mbuf *m; 3315 int i, noctets = 0; 3316 3317 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3318 m0->m_pkthdr.len); 3319 3320 for (m = m0; m; m = m->m_next) { 3321 if (m->m_len == 0) 3322 continue; 3323 for (i = 0; i < m->m_len; i++) { 3324 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3325 if (++noctets % 24 == 0) 3326 printf("\n"); 3327 } 3328 } 3329 printf("%s%s: %d bytes emitted\n", 3330 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3331 } 3332 #endif /* ATW_DEBUG */ 3333 3334 /* 3335 * atw_start: [ifnet interface function] 3336 * 3337 * Start packet transmission on the interface. 3338 */ 3339 void 3340 atw_start(ifp) 3341 struct ifnet *ifp; 3342 { 3343 struct atw_softc *sc = ifp->if_softc; 3344 struct ieee80211com *ic = &sc->sc_ic; 3345 struct ieee80211_node *ni; 3346 struct ieee80211_frame *wh; 3347 struct atw_frame *hh; 3348 struct mbuf *m0, *m; 3349 struct atw_txsoft *txs, *last_txs; 3350 struct atw_txdesc *txd; 3351 int do_encrypt, rate; 3352 bus_dmamap_t dmamap; 3353 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3354 3355 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3356 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3357 3358 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3359 return; 3360 3361 #if 0 /* TBD ??? */ 3362 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3363 return; 3364 #endif 3365 3366 /* 3367 * Remember the previous number of free descriptors and 3368 * the first descriptor we'll use. 3369 */ 3370 ofree = sc->sc_txfree; 3371 firsttx = sc->sc_txnext; 3372 3373 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3374 sc->sc_dev.dv_xname, ofree, firsttx)); 3375 3376 /* 3377 * Loop through the send queue, setting up transmit descriptors 3378 * until we drain the queue, or use up all available transmit 3379 * descriptors. 3380 */ 3381 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3382 sc->sc_txfree != 0) { 3383 3384 do_encrypt = 0; 3385 /* 3386 * Grab a packet off the management queue, if it 3387 * is not empty. Otherwise, from the data queue. 3388 */ 3389 IF_DEQUEUE(&ic->ic_mgtq, m0); 3390 if (m0 != NULL) { 3391 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3392 m0->m_pkthdr.rcvif = NULL; 3393 } else { 3394 IFQ_DEQUEUE(&ifp->if_snd, m0); 3395 if (m0 == NULL) 3396 break; 3397 #if NBPFILTER > 0 3398 if (ifp->if_bpf != NULL) 3399 bpf_mtap(ifp->if_bpf, m0); 3400 #endif /* NBPFILTER > 0 */ 3401 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3402 ifp->if_oerrors++; 3403 break; 3404 } 3405 } 3406 3407 #if NBPFILTER > 0 3408 /* 3409 * Pass the packet to any BPF listeners. 3410 */ 3411 if (ic->ic_rawbpf != NULL) 3412 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3413 if (sc->sc_radiobpf != NULL) 3414 ; /* TBD tap w/ radio header */ 3415 #endif /* NBPFILTER > 0 */ 3416 3417 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3418 3419 if (ni != NULL && ni != ic->ic_bss) 3420 ieee80211_free_node(ic, ni); 3421 3422 if (m0 == NULL) { 3423 ifp->if_oerrors++; 3424 break; 3425 } 3426 3427 /* just to make sure. */ 3428 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3429 3430 if (m0 == NULL) { 3431 ifp->if_oerrors++; 3432 break; 3433 } 3434 3435 hh = mtod(m0, struct atw_frame *); 3436 wh = &hh->atw_ihdr; 3437 3438 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3439 3440 /* Copy everything we need from the 802.11 header: 3441 * Frame Control; address 1, address 3, or addresses 3442 * 3 and 4. NIC fills in BSSID, SA. 3443 */ 3444 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3445 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3446 panic("%s: illegal WDS frame", 3447 sc->sc_dev.dv_xname); 3448 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3449 } else 3450 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3451 3452 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3453 3454 /* initialize remaining Tx parameters */ 3455 memset(&hh->u, 0, sizeof(hh->u)); 3456 3457 rate = MAX(ieee80211_get_rate(ic), 2); 3458 3459 hh->atw_rate = rate * 5; 3460 /* XXX this could be incorrect if M_FCS. _encap should 3461 * probably strip FCS just in case it sticks around in 3462 * bridged packets. 3463 */ 3464 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3465 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3466 sizeof(struct atw_frame)); 3467 3468 #if 0 3469 /* this virtually guaranteed that WEP-encrypted frames 3470 * are fragmented. oops. 3471 */ 3472 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3473 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3474 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3475 #else 3476 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3477 #endif 3478 3479 hh->atw_rtylmt = 3; 3480 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3481 if (do_encrypt) { 3482 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3483 hh->atw_keyid = ic->ic_wep_txkey; 3484 } 3485 3486 /* TBD 4-addr frames */ 3487 atw_frame_setdurs(sc, hh, rate, 3488 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3489 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3490 3491 /* never fragment multicast frames */ 3492 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3493 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3494 } else if (sc->sc_flags & ATWF_RTSCTS) { 3495 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3496 } 3497 3498 #ifdef ATW_DEBUG 3499 /* experimental stuff */ 3500 if (atw_xrtylmt != ~0) 3501 hh->atw_rtylmt = atw_xrtylmt; 3502 if (atw_xhdrctl != 0) 3503 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3504 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3505 hh->atw_service = atw_xservice; 3506 if (atw_xpaylen != 0) 3507 hh->atw_paylen = htole16(atw_xpaylen); 3508 hh->atw_fragnum = 0; 3509 3510 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3511 printf("%s: dst = %s, rate = 0x%02x, " 3512 "service = 0x%02x, paylen = 0x%04x\n", 3513 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3514 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3515 3516 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3517 "dur1 = 0x%04x, dur2 = 0x%04x, " 3518 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3519 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3520 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3521 hh->atw_tail_dur, hh->atw_head_dur); 3522 3523 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3524 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3525 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3526 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3527 3528 printf("%s: keyid = %d\n", 3529 sc->sc_dev.dv_xname, hh->atw_keyid); 3530 3531 atw_dump_pkt(ifp, m0); 3532 } 3533 #endif /* ATW_DEBUG */ 3534 3535 dmamap = txs->txs_dmamap; 3536 3537 /* 3538 * Load the DMA map. Copy and try (once) again if the packet 3539 * didn't fit in the alloted number of segments. 3540 */ 3541 for (first = 1; 3542 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3543 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3544 first = 0) { 3545 MGETHDR(m, M_DONTWAIT, MT_DATA); 3546 if (m == NULL) { 3547 printf("%s: unable to allocate Tx mbuf\n", 3548 sc->sc_dev.dv_xname); 3549 break; 3550 } 3551 if (m0->m_pkthdr.len > MHLEN) { 3552 MCLGET(m, M_DONTWAIT); 3553 if ((m->m_flags & M_EXT) == 0) { 3554 printf("%s: unable to allocate Tx " 3555 "cluster\n", sc->sc_dev.dv_xname); 3556 m_freem(m); 3557 break; 3558 } 3559 } 3560 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3561 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3562 m_freem(m0); 3563 m0 = m; 3564 m = NULL; 3565 } 3566 if (error != 0) { 3567 printf("%s: unable to load Tx buffer, " 3568 "error = %d\n", sc->sc_dev.dv_xname, error); 3569 m_freem(m0); 3570 break; 3571 } 3572 3573 /* 3574 * Ensure we have enough descriptors free to describe 3575 * the packet. 3576 */ 3577 if (dmamap->dm_nsegs > sc->sc_txfree) { 3578 /* 3579 * Not enough free descriptors to transmit 3580 * this packet. Unload the DMA map and 3581 * drop the packet. Notify the upper layer 3582 * that there are no more slots left. 3583 * 3584 * XXX We could allocate an mbuf and copy, but 3585 * XXX it is worth it? 3586 */ 3587 ifp->if_flags |= IFF_OACTIVE; 3588 bus_dmamap_unload(sc->sc_dmat, dmamap); 3589 m_freem(m0); 3590 break; 3591 } 3592 3593 /* 3594 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3595 */ 3596 3597 /* Sync the DMA map. */ 3598 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3599 BUS_DMASYNC_PREWRITE); 3600 3601 /* XXX arbitrary retry limit; 8 because I have seen it in 3602 * use already and maybe 0 means "no tries" ! 3603 */ 3604 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3605 3606 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3607 sc->sc_dev.dv_xname, rate * 5)); 3608 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3609 3610 /* 3611 * Initialize the transmit descriptors. 3612 */ 3613 for (nexttx = sc->sc_txnext, seg = 0; 3614 seg < dmamap->dm_nsegs; 3615 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3616 /* 3617 * If this is the first descriptor we're 3618 * enqueueing, don't set the OWN bit just 3619 * yet. That could cause a race condition. 3620 * We'll do it below. 3621 */ 3622 txd = &sc->sc_txdescs[nexttx]; 3623 txd->at_ctl = ctl | 3624 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3625 3626 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3627 txd->at_flags = 3628 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3629 ATW_TXFLAG_TBS1_MASK)) | 3630 ((nexttx == (ATW_NTXDESC - 1)) 3631 ? htole32(ATW_TXFLAG_TER) : 0); 3632 lasttx = nexttx; 3633 } 3634 3635 KASSERT(lasttx != -1, ("bad lastx")); 3636 /* Set `first segment' and `last segment' appropriately. */ 3637 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3638 htole32(ATW_TXFLAG_FS); 3639 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3640 3641 #ifdef ATW_DEBUG 3642 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3643 printf(" txsoft %p transmit chain:\n", txs); 3644 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3645 printf(" descriptor %d:\n", seg); 3646 printf(" at_ctl: 0x%08x\n", 3647 le32toh(sc->sc_txdescs[seg].at_ctl)); 3648 printf(" at_flags: 0x%08x\n", 3649 le32toh(sc->sc_txdescs[seg].at_flags)); 3650 printf(" at_buf1: 0x%08x\n", 3651 le32toh(sc->sc_txdescs[seg].at_buf1)); 3652 printf(" at_buf2: 0x%08x\n", 3653 le32toh(sc->sc_txdescs[seg].at_buf2)); 3654 if (seg == lasttx) 3655 break; 3656 } 3657 } 3658 #endif 3659 3660 /* Sync the descriptors we're using. */ 3661 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3662 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3663 3664 /* 3665 * Store a pointer to the packet so we can free it later, 3666 * and remember what txdirty will be once the packet is 3667 * done. 3668 */ 3669 txs->txs_mbuf = m0; 3670 txs->txs_firstdesc = sc->sc_txnext; 3671 txs->txs_lastdesc = lasttx; 3672 txs->txs_ndescs = dmamap->dm_nsegs; 3673 3674 /* Advance the tx pointer. */ 3675 sc->sc_txfree -= dmamap->dm_nsegs; 3676 sc->sc_txnext = nexttx; 3677 3678 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3679 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3680 3681 last_txs = txs; 3682 } 3683 3684 if (txs == NULL || sc->sc_txfree == 0) { 3685 /* No more slots left; notify upper layer. */ 3686 ifp->if_flags |= IFF_OACTIVE; 3687 } 3688 3689 if (sc->sc_txfree != ofree) { 3690 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3691 sc->sc_dev.dv_xname, lasttx, firsttx)); 3692 /* 3693 * Cause a transmit interrupt to happen on the 3694 * last packet we enqueued. 3695 */ 3696 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3697 ATW_CDTXSYNC(sc, lasttx, 1, 3698 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3699 3700 /* 3701 * The entire packet chain is set up. Give the 3702 * first descriptor to the chip now. 3703 */ 3704 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3705 ATW_CDTXSYNC(sc, firsttx, 1, 3706 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3707 3708 /* Wake up the transmitter. */ 3709 /* XXX USE AUTOPOLLING? */ 3710 ATW_WRITE(sc, ATW_TDR, 0x1); 3711 3712 /* Set a watchdog timer in case the chip flakes out. */ 3713 sc->sc_tx_timer = 5; 3714 ifp->if_timer = 1; 3715 } 3716 } 3717 3718 /* 3719 * atw_power: 3720 * 3721 * Power management (suspend/resume) hook. 3722 */ 3723 void 3724 atw_power(why, arg) 3725 int why; 3726 void *arg; 3727 { 3728 struct atw_softc *sc = arg; 3729 struct ifnet *ifp = &sc->sc_ic.ic_if; 3730 int s; 3731 3732 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3733 3734 s = splnet(); 3735 switch (why) { 3736 case PWR_STANDBY: 3737 /* XXX do nothing. */ 3738 break; 3739 case PWR_SUSPEND: 3740 atw_stop(ifp, 0); 3741 if (sc->sc_power != NULL) 3742 (*sc->sc_power)(sc, why); 3743 break; 3744 case PWR_RESUME: 3745 if (ifp->if_flags & IFF_UP) { 3746 if (sc->sc_power != NULL) 3747 (*sc->sc_power)(sc, why); 3748 atw_init(ifp); 3749 } 3750 break; 3751 case PWR_SOFTSUSPEND: 3752 case PWR_SOFTSTANDBY: 3753 case PWR_SOFTRESUME: 3754 break; 3755 } 3756 splx(s); 3757 } 3758 3759 /* 3760 * atw_ioctl: [ifnet interface function] 3761 * 3762 * Handle control requests from the operator. 3763 */ 3764 int 3765 atw_ioctl(ifp, cmd, data) 3766 struct ifnet *ifp; 3767 u_long cmd; 3768 caddr_t data; 3769 { 3770 struct atw_softc *sc = ifp->if_softc; 3771 struct ifreq *ifr = (struct ifreq *)data; 3772 int s, error = 0; 3773 3774 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3775 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3776 return ENXIO; 3777 3778 s = splnet(); 3779 3780 switch (cmd) { 3781 case SIOCSIFFLAGS: 3782 if (ifp->if_flags & IFF_UP) { 3783 if (ATW_IS_ENABLED(sc)) { 3784 /* 3785 * To avoid rescanning another access point, 3786 * do not call atw_init() here. Instead, 3787 * only reflect media settings. 3788 */ 3789 atw_filter_setup(sc); 3790 } else 3791 error = atw_init(ifp); 3792 } else if (ATW_IS_ENABLED(sc)) 3793 atw_stop(ifp, 1); 3794 break; 3795 case SIOCADDMULTI: 3796 case SIOCDELMULTI: 3797 error = (cmd == SIOCADDMULTI) ? 3798 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3799 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3800 if (error == ENETRESET) { 3801 if (ATW_IS_ENABLED(sc)) 3802 atw_filter_setup(sc); /* do not rescan */ 3803 error = 0; 3804 } 3805 break; 3806 default: 3807 error = ieee80211_ioctl(ifp, cmd, data); 3808 if (error == ENETRESET) { 3809 if (ATW_IS_ENABLED(sc)) 3810 error = atw_init(ifp); 3811 else 3812 error = 0; 3813 } 3814 break; 3815 } 3816 3817 /* Try to get more packets going. */ 3818 if (ATW_IS_ENABLED(sc)) 3819 atw_start(ifp); 3820 3821 splx(s); 3822 return (error); 3823 } 3824 3825 static int 3826 atw_media_change(struct ifnet *ifp) 3827 { 3828 int error; 3829 3830 error = ieee80211_media_change(ifp); 3831 if (error == ENETRESET) { 3832 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3833 (IFF_RUNNING|IFF_UP)) 3834 atw_init(ifp); /* XXX lose error */ 3835 error = 0; 3836 } 3837 return error; 3838 } 3839 3840 static void 3841 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3842 { 3843 struct atw_softc *sc = ifp->if_softc; 3844 3845 if (ATW_IS_ENABLED(sc) == 0) { 3846 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3847 imr->ifm_status = 0; 3848 return; 3849 } 3850 ieee80211_media_status(ifp, imr); 3851 } 3852
Indexes created Wed Sep 24 05:09:52 GMT 2025