atw.c revision 1.103
1 /* $NetBSD: atw.c,v 1.103 2005/12/29 22:01:43 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.103 2005/12/29 22:01:43 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 266 static void atw_filter_setup(struct atw_softc *); 267 268 /* 802.11 utilities */ 269 static uint64_t atw_get_tsft(struct atw_softc *); 270 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 271 uint32_t); 272 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 273 static void atw_node_free(struct ieee80211_node *); 274 static void atw_change_ibss(struct atw_softc *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 int 316 atw_activate(struct device *self, enum devact act) 317 { 318 struct atw_softc *sc = (struct atw_softc *)self; 319 int rv = 0, s; 320 321 s = splnet(); 322 switch (act) { 323 case DVACT_ACTIVATE: 324 rv = EOPNOTSUPP; 325 break; 326 327 case DVACT_DEACTIVATE: 328 if_deactivate(&sc->sc_if); 329 break; 330 } 331 splx(s); 332 return rv; 333 } 334 335 /* 336 * atw_enable: 337 * 338 * Enable the ADM8211 chip. 339 */ 340 int 341 atw_enable(struct atw_softc *sc) 342 { 343 344 if (ATW_IS_ENABLED(sc) == 0) { 345 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 346 printf("%s: device enable failed\n", 347 sc->sc_dev.dv_xname); 348 return (EIO); 349 } 350 sc->sc_flags |= ATWF_ENABLED; 351 } 352 return (0); 353 } 354 355 /* 356 * atw_disable: 357 * 358 * Disable the ADM8211 chip. 359 */ 360 void 361 atw_disable(struct atw_softc *sc) 362 { 363 if (!ATW_IS_ENABLED(sc)) 364 return; 365 if (sc->sc_disable != NULL) 366 (*sc->sc_disable)(sc); 367 sc->sc_flags &= ~ATWF_ENABLED; 368 } 369 370 /* Returns -1 on failure. */ 371 static int 372 atw_read_srom(struct atw_softc *sc) 373 { 374 struct seeprom_descriptor sd; 375 uint32_t test0, fail_bits; 376 377 (void)memset(&sd, 0, sizeof(sd)); 378 379 test0 = ATW_READ(sc, ATW_TEST0); 380 381 switch (sc->sc_rev) { 382 case ATW_REVISION_BA: 383 case ATW_REVISION_CA: 384 fail_bits = ATW_TEST0_EPNE; 385 break; 386 default: 387 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 388 break; 389 } 390 if ((test0 & fail_bits) != 0) { 391 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 392 return -1; 393 } 394 395 switch (test0 & ATW_TEST0_EPTYP_MASK) { 396 case ATW_TEST0_EPTYP_93c66: 397 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 398 sc->sc_sromsz = 512; 399 sd.sd_chip = C56_66; 400 break; 401 case ATW_TEST0_EPTYP_93c46: 402 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 403 sc->sc_sromsz = 128; 404 sd.sd_chip = C46; 405 break; 406 default: 407 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 408 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 409 return -1; 410 } 411 412 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 413 414 if (sc->sc_srom == NULL) { 415 printf("%s: unable to allocate SROM buffer\n", 416 sc->sc_dev.dv_xname); 417 return -1; 418 } 419 420 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 421 422 /* ADM8211 has a single 32-bit register for controlling the 423 * 93cx6 SROM. Bit SRS enables the serial port. There is no 424 * "ready" bit. The ADM8211 input/output sense is the reverse 425 * of read_seeprom's. 426 */ 427 sd.sd_tag = sc->sc_st; 428 sd.sd_bsh = sc->sc_sh; 429 sd.sd_regsize = 4; 430 sd.sd_control_offset = ATW_SPR; 431 sd.sd_status_offset = ATW_SPR; 432 sd.sd_dataout_offset = ATW_SPR; 433 sd.sd_CK = ATW_SPR_SCLK; 434 sd.sd_CS = ATW_SPR_SCS; 435 sd.sd_DI = ATW_SPR_SDO; 436 sd.sd_DO = ATW_SPR_SDI; 437 sd.sd_MS = ATW_SPR_SRS; 438 sd.sd_RDY = 0; 439 440 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 441 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 442 free(sc->sc_srom, M_DEVBUF); 443 return -1; 444 } 445 #ifdef ATW_DEBUG 446 { 447 int i; 448 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 449 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 450 if (((i % 8) == 0) && (i != 0)) { 451 ATW_DPRINTF(("\n\t")); 452 } 453 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 454 } 455 ATW_DPRINTF(("\n")); 456 } 457 #endif /* ATW_DEBUG */ 458 return 0; 459 } 460 461 #ifdef ATW_DEBUG 462 static void 463 atw_print_regs(struct atw_softc *sc, const char *where) 464 { 465 #define PRINTREG(sc, reg) \ 466 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 467 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 468 469 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 470 471 PRINTREG(sc, ATW_PAR); 472 PRINTREG(sc, ATW_FRCTL); 473 PRINTREG(sc, ATW_TDR); 474 PRINTREG(sc, ATW_WTDP); 475 PRINTREG(sc, ATW_RDR); 476 PRINTREG(sc, ATW_WRDP); 477 PRINTREG(sc, ATW_RDB); 478 PRINTREG(sc, ATW_CSR3A); 479 PRINTREG(sc, ATW_TDBD); 480 PRINTREG(sc, ATW_TDBP); 481 PRINTREG(sc, ATW_STSR); 482 PRINTREG(sc, ATW_CSR5A); 483 PRINTREG(sc, ATW_NAR); 484 PRINTREG(sc, ATW_CSR6A); 485 PRINTREG(sc, ATW_IER); 486 PRINTREG(sc, ATW_CSR7A); 487 PRINTREG(sc, ATW_LPC); 488 PRINTREG(sc, ATW_TEST1); 489 PRINTREG(sc, ATW_SPR); 490 PRINTREG(sc, ATW_TEST0); 491 PRINTREG(sc, ATW_WCSR); 492 PRINTREG(sc, ATW_WPDR); 493 PRINTREG(sc, ATW_GPTMR); 494 PRINTREG(sc, ATW_GPIO); 495 PRINTREG(sc, ATW_BBPCTL); 496 PRINTREG(sc, ATW_SYNCTL); 497 PRINTREG(sc, ATW_PLCPHD); 498 PRINTREG(sc, ATW_MMIWADDR); 499 PRINTREG(sc, ATW_MMIRADDR1); 500 PRINTREG(sc, ATW_MMIRADDR2); 501 PRINTREG(sc, ATW_TXBR); 502 PRINTREG(sc, ATW_CSR15A); 503 PRINTREG(sc, ATW_ALCSTAT); 504 PRINTREG(sc, ATW_TOFS2); 505 PRINTREG(sc, ATW_CMDR); 506 PRINTREG(sc, ATW_PCIC); 507 PRINTREG(sc, ATW_PMCSR); 508 PRINTREG(sc, ATW_PAR0); 509 PRINTREG(sc, ATW_PAR1); 510 PRINTREG(sc, ATW_MAR0); 511 PRINTREG(sc, ATW_MAR1); 512 PRINTREG(sc, ATW_ATIMDA0); 513 PRINTREG(sc, ATW_ABDA1); 514 PRINTREG(sc, ATW_BSSID0); 515 PRINTREG(sc, ATW_TXLMT); 516 PRINTREG(sc, ATW_MIBCNT); 517 PRINTREG(sc, ATW_BCNT); 518 PRINTREG(sc, ATW_TSFTH); 519 PRINTREG(sc, ATW_TSC); 520 PRINTREG(sc, ATW_SYNRF); 521 PRINTREG(sc, ATW_BPLI); 522 PRINTREG(sc, ATW_CAP0); 523 PRINTREG(sc, ATW_CAP1); 524 PRINTREG(sc, ATW_RMD); 525 PRINTREG(sc, ATW_CFPP); 526 PRINTREG(sc, ATW_TOFS0); 527 PRINTREG(sc, ATW_TOFS1); 528 PRINTREG(sc, ATW_IFST); 529 PRINTREG(sc, ATW_RSPT); 530 PRINTREG(sc, ATW_TSFTL); 531 PRINTREG(sc, ATW_WEPCTL); 532 PRINTREG(sc, ATW_WESK); 533 PRINTREG(sc, ATW_WEPCNT); 534 PRINTREG(sc, ATW_MACTEST); 535 PRINTREG(sc, ATW_FER); 536 PRINTREG(sc, ATW_FEMR); 537 PRINTREG(sc, ATW_FPSR); 538 PRINTREG(sc, ATW_FFER); 539 #undef PRINTREG 540 } 541 #endif /* ATW_DEBUG */ 542 543 /* 544 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 545 */ 546 void 547 atw_attach(struct atw_softc *sc) 548 { 549 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 551 }; 552 struct ieee80211com *ic = &sc->sc_ic; 553 struct ifnet *ifp = &sc->sc_if; 554 int country_code, error, i, nrate, srom_major; 555 u_int32_t reg; 556 static const char *type_strings[] = {"Intersil (not supported)", 557 "RFMD", "Marvel (not supported)"}; 558 559 sc->sc_txth = atw_txthresh_tab_lo; 560 561 SIMPLEQ_INIT(&sc->sc_txfreeq); 562 SIMPLEQ_INIT(&sc->sc_txdirtyq); 563 564 #ifdef ATW_DEBUG 565 atw_print_regs(sc, "atw_attach"); 566 #endif /* ATW_DEBUG */ 567 568 /* 569 * Allocate the control data structures, and create and load the 570 * DMA map for it. 571 */ 572 if ((error = bus_dmamem_alloc(sc->sc_dmat, 573 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 574 1, &sc->sc_cdnseg, 0)) != 0) { 575 printf("%s: unable to allocate control data, error = %d\n", 576 sc->sc_dev.dv_xname, error); 577 goto fail_0; 578 } 579 580 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 581 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 582 BUS_DMA_COHERENT)) != 0) { 583 printf("%s: unable to map control data, error = %d\n", 584 sc->sc_dev.dv_xname, error); 585 goto fail_1; 586 } 587 588 if ((error = bus_dmamap_create(sc->sc_dmat, 589 sizeof(struct atw_control_data), 1, 590 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 591 printf("%s: unable to create control data DMA map, " 592 "error = %d\n", sc->sc_dev.dv_xname, error); 593 goto fail_2; 594 } 595 596 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 597 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 598 0)) != 0) { 599 printf("%s: unable to load control data DMA map, error = %d\n", 600 sc->sc_dev.dv_xname, error); 601 goto fail_3; 602 } 603 604 /* 605 * Create the transmit buffer DMA maps. 606 */ 607 sc->sc_ntxsegs = ATW_NTXSEGS; 608 for (i = 0; i < ATW_TXQUEUELEN; i++) { 609 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 610 sc->sc_ntxsegs, MCLBYTES, 0, 0, 611 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 612 printf("%s: unable to create tx DMA map %d, " 613 "error = %d\n", sc->sc_dev.dv_xname, i, error); 614 goto fail_4; 615 } 616 } 617 618 /* 619 * Create the receive buffer DMA maps. 620 */ 621 for (i = 0; i < ATW_NRXDESC; i++) { 622 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 623 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 624 printf("%s: unable to create rx DMA map %d, " 625 "error = %d\n", sc->sc_dev.dv_xname, i, error); 626 goto fail_5; 627 } 628 } 629 for (i = 0; i < ATW_NRXDESC; i++) { 630 sc->sc_rxsoft[i].rxs_mbuf = NULL; 631 } 632 633 switch (sc->sc_rev) { 634 case ATW_REVISION_AB: 635 case ATW_REVISION_AF: 636 sc->sc_sramlen = ATW_SRAM_A_SIZE; 637 break; 638 case ATW_REVISION_BA: 639 case ATW_REVISION_CA: 640 sc->sc_sramlen = ATW_SRAM_B_SIZE; 641 break; 642 } 643 644 /* Reset the chip to a known state. */ 645 atw_reset(sc); 646 647 if (atw_read_srom(sc) == -1) 648 return; 649 650 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 651 ATW_SR_RFTYPE_MASK); 652 653 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 654 ATW_SR_BBPTYPE_MASK); 655 656 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 657 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 661 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 662 return; 663 } 664 665 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 666 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 667 668 /* XXX There exists a Linux driver which seems to use RFType = 0 for 669 * MARVEL. My bug, or theirs? 670 */ 671 672 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 673 674 switch (sc->sc_rftype) { 675 case ATW_RFTYPE_INTERSIL: 676 reg |= ATW_SYNCTL_CS1; 677 break; 678 case ATW_RFTYPE_RFMD: 679 reg |= ATW_SYNCTL_CS0; 680 break; 681 case ATW_RFTYPE_MARVEL: 682 break; 683 } 684 685 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 686 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 687 688 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 689 690 switch (sc->sc_bbptype) { 691 case ATW_BBPTYPE_INTERSIL: 692 reg |= ATW_BBPCTL_TWI; 693 break; 694 case ATW_BBPTYPE_RFMD: 695 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 696 ATW_BBPCTL_CCA_ACTLO; 697 break; 698 case ATW_BBPTYPE_MARVEL: 699 break; 700 case ATW_C_BBPTYPE_RFMD: 701 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 702 sc->sc_dev.dv_xname); 703 break; 704 } 705 706 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 707 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 708 709 /* 710 * From this point forward, the attachment cannot fail. A failure 711 * before this point releases all resources that may have been 712 * allocated. 713 */ 714 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 715 716 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 717 htole16(sc->sc_srom[ATW_SR_MAC00]), 718 htole16(sc->sc_srom[ATW_SR_MAC01]), 719 htole16(sc->sc_srom[ATW_SR_MAC10]))); 720 721 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 722 ATW_SR_MAJOR_MASK); 723 724 if (srom_major < 2) 725 sc->sc_rf3000_options1 = 0; 726 else if (sc->sc_rev == ATW_REVISION_BA) { 727 sc->sc_rf3000_options1 = 728 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 729 ATW_SR_CR28_MASK); 730 } else 731 sc->sc_rf3000_options1 = 0; 732 733 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 734 ATW_SR_CR29_MASK); 735 736 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 737 ATW_SR_CTRY_MASK); 738 739 #define ADD_CHANNEL(_ic, _chan) do { \ 740 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 741 _ic->ic_channels[_chan].ic_freq = \ 742 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 743 } while (0) 744 745 /* Find available channels */ 746 switch (country_code) { 747 case COUNTRY_MMK2: /* 1-14 */ 748 ADD_CHANNEL(ic, 14); 749 /*FALLTHROUGH*/ 750 case COUNTRY_ETSI: /* 1-13 */ 751 for (i = 1; i <= 13; i++) 752 ADD_CHANNEL(ic, i); 753 break; 754 case COUNTRY_FCC: /* 1-11 */ 755 case COUNTRY_IC: /* 1-11 */ 756 for (i = 1; i <= 11; i++) 757 ADD_CHANNEL(ic, i); 758 break; 759 case COUNTRY_MMK: /* 14 */ 760 ADD_CHANNEL(ic, 14); 761 break; 762 case COUNTRY_FRANCE: /* 10-13 */ 763 for (i = 10; i <= 13; i++) 764 ADD_CHANNEL(ic, i); 765 break; 766 default: /* assume channels 10-11 */ 767 case COUNTRY_SPAIN: /* 10-11 */ 768 for (i = 10; i <= 11; i++) 769 ADD_CHANNEL(ic, i); 770 break; 771 } 772 773 /* Read the MAC address. */ 774 reg = ATW_READ(sc, ATW_PAR0); 775 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 776 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 777 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 778 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 779 reg = ATW_READ(sc, ATW_PAR1); 780 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 781 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 782 783 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 784 printf(" could not get mac address, attach failed\n"); 785 return; 786 } 787 788 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 789 790 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 791 ifp->if_softc = sc; 792 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 793 IFF_NOTRAILERS; 794 ifp->if_ioctl = atw_ioctl; 795 ifp->if_start = atw_start; 796 ifp->if_watchdog = atw_watchdog; 797 ifp->if_init = atw_init; 798 ifp->if_stop = atw_stop; 799 IFQ_SET_READY(&ifp->if_snd); 800 801 ic->ic_ifp = ifp; 802 ic->ic_phytype = IEEE80211_T_DS; 803 ic->ic_opmode = IEEE80211_M_STA; 804 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 805 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 806 807 nrate = 0; 808 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 809 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 810 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 811 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 813 814 /* 815 * Call MI attach routines. 816 */ 817 818 if_attach(ifp); 819 ieee80211_ifattach(ic); 820 821 sc->sc_newstate = ic->ic_newstate; 822 ic->ic_newstate = atw_newstate; 823 824 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 825 ic->ic_recv_mgmt = atw_recv_mgmt; 826 827 sc->sc_node_free = ic->ic_node_free; 828 ic->ic_node_free = atw_node_free; 829 830 sc->sc_node_alloc = ic->ic_node_alloc; 831 ic->ic_node_alloc = atw_node_alloc; 832 833 ic->ic_crypto.cs_key_delete = atw_key_delete; 834 ic->ic_crypto.cs_key_set = atw_key_set; 835 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 836 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 837 838 /* possibly we should fill in our own sc_send_prresp, since 839 * the ADM8211 is probably sending probe responses in ad hoc 840 * mode. 841 */ 842 843 /* complete initialization */ 844 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 845 callout_init(&sc->sc_scan_ch); 846 847 #if NBPFILTER > 0 848 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 849 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 850 #endif 851 852 /* 853 * Make sure the interface is shutdown during reboot. 854 */ 855 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 856 if (sc->sc_sdhook == NULL) 857 printf("%s: WARNING: unable to establish shutdown hook\n", 858 sc->sc_dev.dv_xname); 859 860 /* 861 * Add a suspend hook to make sure we come back up after a 862 * resume. 863 */ 864 sc->sc_powerhook = powerhook_establish(atw_power, sc); 865 if (sc->sc_powerhook == NULL) 866 printf("%s: WARNING: unable to establish power hook\n", 867 sc->sc_dev.dv_xname); 868 869 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 870 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 871 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 872 873 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 874 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 875 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 876 877 ieee80211_announce(ic); 878 return; 879 880 /* 881 * Free any resources we've allocated during the failed attach 882 * attempt. Do this in reverse order and fall through. 883 */ 884 fail_5: 885 for (i = 0; i < ATW_NRXDESC; i++) { 886 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 887 continue; 888 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 889 } 890 fail_4: 891 for (i = 0; i < ATW_TXQUEUELEN; i++) { 892 if (sc->sc_txsoft[i].txs_dmamap == NULL) 893 continue; 894 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 895 } 896 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 897 fail_3: 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 899 fail_2: 900 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 901 sizeof(struct atw_control_data)); 902 fail_1: 903 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 904 fail_0: 905 return; 906 } 907 908 static struct ieee80211_node * 909 atw_node_alloc(struct ieee80211_node_table *nt) 910 { 911 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 912 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 913 914 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 915 return ni; 916 } 917 918 static void 919 atw_node_free(struct ieee80211_node *ni) 920 { 921 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 922 923 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 924 ether_sprintf(ni->ni_bssid))); 925 (*sc->sc_node_free)(ni); 926 } 927 928 929 static void 930 atw_test1_reset(struct atw_softc *sc) 931 { 932 switch (sc->sc_rev) { 933 case ATW_REVISION_BA: 934 if (1 /* XXX condition on transceiver type */) { 935 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 936 } 937 break; 938 case ATW_REVISION_CA: 939 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 940 break; 941 default: 942 break; 943 } 944 } 945 946 /* 947 * atw_reset: 948 * 949 * Perform a soft reset on the ADM8211. 950 */ 951 void 952 atw_reset(struct atw_softc *sc) 953 { 954 int i; 955 uint32_t lpc; 956 957 ATW_WRITE(sc, ATW_NAR, 0x0); 958 DELAY(atw_nar_delay); 959 960 /* Reference driver has a cryptic remark indicating that this might 961 * power-on the chip. I know that it turns off power-saving.... 962 */ 963 ATW_WRITE(sc, ATW_FRCTL, 0x0); 964 965 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 966 967 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 968 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 969 break; 970 DELAY(atw_pseudo_milli); 971 } 972 973 /* ... and then pause 100ms longer for good measure. */ 974 DELAY(atw_magic_delay1); 975 976 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 977 978 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 979 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 980 981 /* 982 * Initialize the PCI Access Register. 983 */ 984 sc->sc_busmode = ATW_PAR_PBL_8DW; 985 986 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 987 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 988 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 989 990 atw_test1_reset(sc); 991 992 /* Turn off maximum power saving, etc. */ 993 ATW_WRITE(sc, ATW_FRCTL, 0x0); 994 995 DELAY(atw_magic_delay2); 996 997 /* Recall EEPROM. */ 998 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 999 1000 DELAY(atw_magic_delay4); 1001 1002 lpc = ATW_READ(sc, ATW_LPC); 1003 1004 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1005 1006 /* A reset seems to affect the SRAM contents, so put them into 1007 * a known state. 1008 */ 1009 atw_clear_sram(sc); 1010 1011 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1012 } 1013 1014 static void 1015 atw_clear_sram(struct atw_softc *sc) 1016 { 1017 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1018 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1019 /* XXX not for revision 0x20. */ 1020 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1021 } 1022 1023 /* TBD atw_init 1024 * 1025 * set MAC based on ic->ic_bss->myaddr 1026 * write WEP keys 1027 * set TX rate 1028 */ 1029 1030 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1031 * without receiving a beacon with the preferred BSSID & SSID. 1032 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1033 */ 1034 static void 1035 atw_wcsr_init(struct atw_softc *sc) 1036 { 1037 uint32_t wcsr; 1038 1039 wcsr = ATW_READ(sc, ATW_WCSR); 1040 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1041 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1042 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1043 1044 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1045 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1046 } 1047 1048 /* Turn off power management. Set Rx store-and-forward mode. */ 1049 static void 1050 atw_cmdr_init(struct atw_softc *sc) 1051 { 1052 uint32_t cmdr; 1053 cmdr = ATW_READ(sc, ATW_CMDR); 1054 cmdr &= ~ATW_CMDR_APM; 1055 cmdr |= ATW_CMDR_RTE; 1056 cmdr &= ~ATW_CMDR_DRT_MASK; 1057 cmdr |= ATW_CMDR_DRT_SF; 1058 1059 ATW_WRITE(sc, ATW_CMDR, cmdr); 1060 } 1061 1062 static void 1063 atw_tofs2_init(struct atw_softc *sc) 1064 { 1065 uint32_t tofs2; 1066 /* XXX this magic can probably be figured out from the RFMD docs */ 1067 #ifndef ATW_REFSLAVE 1068 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1069 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1070 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1071 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1072 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1073 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1074 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1075 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1076 #else 1077 /* XXX new magic from reference driver source */ 1078 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1079 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1080 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1081 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1082 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1083 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1084 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1085 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1086 #endif 1087 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1088 } 1089 1090 static void 1091 atw_nar_init(struct atw_softc *sc) 1092 { 1093 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1094 } 1095 1096 static void 1097 atw_txlmt_init(struct atw_softc *sc) 1098 { 1099 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1100 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1101 } 1102 1103 static void 1104 atw_test1_init(struct atw_softc *sc) 1105 { 1106 uint32_t test1; 1107 1108 test1 = ATW_READ(sc, ATW_TEST1); 1109 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1110 /* XXX magic 0x1 */ 1111 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1112 ATW_WRITE(sc, ATW_TEST1, test1); 1113 } 1114 1115 static void 1116 atw_rf_reset(struct atw_softc *sc) 1117 { 1118 /* XXX this resets an Intersil RF front-end? */ 1119 /* TBD condition on Intersil RFType? */ 1120 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1121 DELAY(atw_rf_delay1); 1122 ATW_WRITE(sc, ATW_SYNRF, 0); 1123 DELAY(atw_rf_delay2); 1124 } 1125 1126 /* Set 16 TU max duration for the contention-free period (CFP). */ 1127 static void 1128 atw_cfp_init(struct atw_softc *sc) 1129 { 1130 uint32_t cfpp; 1131 1132 cfpp = ATW_READ(sc, ATW_CFPP); 1133 cfpp &= ~ATW_CFPP_CFPMD; 1134 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1135 ATW_WRITE(sc, ATW_CFPP, cfpp); 1136 } 1137 1138 static void 1139 atw_tofs0_init(struct atw_softc *sc) 1140 { 1141 /* XXX I guess that the Cardbus clock is 22MHz? 1142 * I am assuming that the role of ATW_TOFS0_USCNT is 1143 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1144 * very clear on this point. It says in the datasheet that it is 1145 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1146 * and 33MHz; maybe this is the way? I see a binary-only driver write 1147 * these values. These values are also the power-on default. 1148 */ 1149 ATW_WRITE(sc, ATW_TOFS0, 1150 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1151 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1152 } 1153 1154 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1155 static void 1156 atw_ifs_init(struct atw_softc *sc) 1157 { 1158 uint32_t ifst; 1159 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1160 * Go figure. 1161 */ 1162 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1163 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1164 ATW_IFST_SIFS_MASK) | 1165 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1166 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1167 1168 ATW_WRITE(sc, ATW_IFST, ifst); 1169 } 1170 1171 static void 1172 atw_response_times_init(struct atw_softc *sc) 1173 { 1174 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1175 * indicate that the MAC expects at least SIFS + MIRT microseconds 1176 * to pass after it transmits a frame that requires a response; 1177 * it waits at most SIFS + MART microseconds for the response. 1178 * Surely this is not the ACK timeout? 1179 */ 1180 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1181 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1182 } 1183 1184 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1185 * engines read and write baseband registers after Rx and before 1186 * Tx, respectively. 1187 */ 1188 static void 1189 atw_bbp_io_init(struct atw_softc *sc) 1190 { 1191 uint32_t mmiraddr2; 1192 1193 /* XXX The reference driver does this, but is it *really* 1194 * necessary? 1195 */ 1196 switch (sc->sc_rev) { 1197 case ATW_REVISION_AB: 1198 case ATW_REVISION_AF: 1199 mmiraddr2 = 0x0; 1200 break; 1201 default: 1202 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1203 mmiraddr2 &= 1204 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1205 break; 1206 } 1207 1208 switch (sc->sc_bbptype) { 1209 case ATW_BBPTYPE_INTERSIL: 1210 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1211 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1212 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1213 break; 1214 case ATW_BBPTYPE_MARVEL: 1215 /* TBD find out the Marvel settings. */ 1216 break; 1217 case ATW_BBPTYPE_RFMD: 1218 default: 1219 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1220 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1221 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1222 break; 1223 } 1224 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1225 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1226 } 1227 1228 /* 1229 * atw_init: [ ifnet interface function ] 1230 * 1231 * Initialize the interface. Must be called at splnet(). 1232 */ 1233 int 1234 atw_init(struct ifnet *ifp) 1235 { 1236 struct atw_softc *sc = ifp->if_softc; 1237 struct ieee80211com *ic = &sc->sc_ic; 1238 struct atw_txsoft *txs; 1239 struct atw_rxsoft *rxs; 1240 int i, error = 0; 1241 1242 if ((error = atw_enable(sc)) != 0) 1243 goto out; 1244 1245 /* 1246 * Cancel any pending I/O. This also resets. 1247 */ 1248 atw_stop(ifp, 0); 1249 1250 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1251 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1252 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1253 1254 atw_wcsr_init(sc); 1255 1256 atw_cmdr_init(sc); 1257 1258 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1259 * 1260 * XXX Set transmit power for ATIM, RTS, Beacon. 1261 */ 1262 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1263 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1264 1265 atw_tofs2_init(sc); 1266 1267 atw_nar_init(sc); 1268 1269 atw_txlmt_init(sc); 1270 1271 atw_test1_init(sc); 1272 1273 atw_rf_reset(sc); 1274 1275 atw_cfp_init(sc); 1276 1277 atw_tofs0_init(sc); 1278 1279 atw_ifs_init(sc); 1280 1281 /* XXX Fall asleep after one second of inactivity. 1282 * XXX A frame may only dribble in for 65536us. 1283 */ 1284 ATW_WRITE(sc, ATW_RMD, 1285 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1286 1287 atw_response_times_init(sc); 1288 1289 atw_bbp_io_init(sc); 1290 1291 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1292 1293 if ((error = atw_rf3000_init(sc)) != 0) 1294 goto out; 1295 1296 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1297 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1298 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1299 1300 /* 1301 * Initialize the transmit descriptor ring. 1302 */ 1303 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1304 for (i = 0; i < ATW_NTXDESC; i++) { 1305 sc->sc_txdescs[i].at_ctl = 0; 1306 /* no transmit chaining */ 1307 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1308 sc->sc_txdescs[i].at_buf2 = 1309 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1310 } 1311 /* use ring mode */ 1312 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1313 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1314 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1315 sc->sc_txfree = ATW_NTXDESC; 1316 sc->sc_txnext = 0; 1317 1318 /* 1319 * Initialize the transmit job descriptors. 1320 */ 1321 SIMPLEQ_INIT(&sc->sc_txfreeq); 1322 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1323 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1324 txs = &sc->sc_txsoft[i]; 1325 txs->txs_mbuf = NULL; 1326 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1327 } 1328 1329 /* 1330 * Initialize the receive descriptor and receive job 1331 * descriptor rings. 1332 */ 1333 for (i = 0; i < ATW_NRXDESC; i++) { 1334 rxs = &sc->sc_rxsoft[i]; 1335 if (rxs->rxs_mbuf == NULL) { 1336 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1337 printf("%s: unable to allocate or map rx " 1338 "buffer %d, error = %d\n", 1339 sc->sc_dev.dv_xname, i, error); 1340 /* 1341 * XXX Should attempt to run with fewer receive 1342 * XXX buffers instead of just failing. 1343 */ 1344 atw_rxdrain(sc); 1345 goto out; 1346 } 1347 } else 1348 ATW_INIT_RXDESC(sc, i); 1349 } 1350 sc->sc_rxptr = 0; 1351 1352 /* 1353 * Initialize the interrupt mask and enable interrupts. 1354 */ 1355 /* normal interrupts */ 1356 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1357 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1358 1359 /* abnormal interrupts */ 1360 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1361 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1362 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1363 1364 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1365 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1366 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1367 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1368 ATW_INTR_TRT; 1369 1370 sc->sc_linkint_mask &= sc->sc_inten; 1371 sc->sc_rxint_mask &= sc->sc_inten; 1372 sc->sc_txint_mask &= sc->sc_inten; 1373 1374 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1375 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1376 1377 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1378 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1379 1380 /* 1381 * Give the transmit and receive rings to the ADM8211. 1382 */ 1383 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1384 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1385 1386 sc->sc_txthresh = 0; 1387 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1388 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1389 1390 /* common 802.11 configuration */ 1391 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1392 switch (ic->ic_opmode) { 1393 case IEEE80211_M_STA: 1394 break; 1395 case IEEE80211_M_AHDEMO: /* XXX */ 1396 case IEEE80211_M_IBSS: 1397 ic->ic_flags |= IEEE80211_F_IBSSON; 1398 /*FALLTHROUGH*/ 1399 case IEEE80211_M_HOSTAP: /* XXX */ 1400 break; 1401 case IEEE80211_M_MONITOR: /* XXX */ 1402 break; 1403 } 1404 1405 switch (ic->ic_opmode) { 1406 case IEEE80211_M_AHDEMO: 1407 case IEEE80211_M_HOSTAP: 1408 #ifndef IEEE80211_NO_HOSTAP 1409 ic->ic_bss->ni_intval = ic->ic_lintval; 1410 ic->ic_bss->ni_rssi = 0; 1411 ic->ic_bss->ni_rstamp = 0; 1412 #endif /* !IEEE80211_NO_HOSTAP */ 1413 break; 1414 default: /* XXX */ 1415 break; 1416 } 1417 1418 sc->sc_wepctl = 0; 1419 1420 atw_write_ssid(sc); 1421 atw_write_sup_rates(sc); 1422 atw_write_wep(sc); 1423 1424 ic->ic_state = IEEE80211_S_INIT; 1425 1426 /* 1427 * Set the receive filter. This will start the transmit and 1428 * receive processes. 1429 */ 1430 atw_filter_setup(sc); 1431 1432 /* 1433 * Start the receive process. 1434 */ 1435 ATW_WRITE(sc, ATW_RDR, 0x1); 1436 1437 /* 1438 * Note that the interface is now running. 1439 */ 1440 ifp->if_flags |= IFF_RUNNING; 1441 ifp->if_flags &= ~IFF_OACTIVE; 1442 1443 /* send no beacons, yet. */ 1444 atw_start_beacon(sc, 0); 1445 1446 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1447 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1448 else 1449 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1450 out: 1451 if (error) { 1452 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1453 sc->sc_tx_timer = 0; 1454 ifp->if_timer = 0; 1455 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1456 } 1457 #ifdef ATW_DEBUG 1458 atw_print_regs(sc, "end of init"); 1459 #endif /* ATW_DEBUG */ 1460 1461 return (error); 1462 } 1463 1464 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1465 * 0: MAC control of RF3000/Si4126. 1466 * 1467 * Applies power, or selects RF front-end? Sets reset condition. 1468 * 1469 * TBD support non-RFMD BBP, non-SiLabs synth. 1470 */ 1471 static void 1472 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1473 { 1474 if (enable) { 1475 ATW_WRITE(sc, ATW_SYNRF, 1476 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1477 DELAY(atw_bbp_io_enable_delay); 1478 } else { 1479 ATW_WRITE(sc, ATW_SYNRF, 0); 1480 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1481 } 1482 } 1483 1484 static int 1485 atw_tune(struct atw_softc *sc) 1486 { 1487 int rc; 1488 u_int chan; 1489 struct ieee80211com *ic = &sc->sc_ic; 1490 1491 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1492 if (chan == IEEE80211_CHAN_ANY) 1493 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1494 1495 if (chan == sc->sc_cur_chan) 1496 return 0; 1497 1498 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1499 sc->sc_cur_chan, chan)); 1500 1501 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1502 1503 atw_si4126_tune(sc, chan); 1504 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1505 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1506 chan); 1507 1508 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1509 DELAY(atw_nar_delay); 1510 ATW_WRITE(sc, ATW_RDR, 0x1); 1511 1512 if (rc == 0) 1513 sc->sc_cur_chan = chan; 1514 1515 return rc; 1516 } 1517 1518 #ifdef ATW_SYNDEBUG 1519 static void 1520 atw_si4126_print(struct atw_softc *sc) 1521 { 1522 struct ifnet *ifp = &sc->sc_if; 1523 u_int addr, val; 1524 1525 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1526 return; 1527 1528 for (addr = 0; addr <= 8; addr++) { 1529 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1530 if (atw_si4126_read(sc, addr, &val) == 0) { 1531 printf("<unknown> (quitting print-out)\n"); 1532 break; 1533 } 1534 printf("%05x\n", val); 1535 } 1536 } 1537 #endif /* ATW_SYNDEBUG */ 1538 1539 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1540 * 1541 * The RF/IF synthesizer produces two reference frequencies for 1542 * the RF2948B transceiver. The first frequency the RF2948B requires 1543 * is two times the so-called "intermediate frequency" (IF). Since 1544 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1545 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1546 * frequency required by the transceiver is the radio frequency 1547 * (RF). This is a superheterodyne transceiver; for f(chan) the 1548 * center frequency of the channel we are tuning, RF = f(chan) - 1549 * IF. 1550 * 1551 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1552 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1553 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1554 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1555 */ 1556 static void 1557 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1558 { 1559 u_int mhz; 1560 u_int R; 1561 u_int32_t gpio; 1562 u_int16_t gain; 1563 1564 #ifdef ATW_SYNDEBUG 1565 atw_si4126_print(sc); 1566 #endif /* ATW_SYNDEBUG */ 1567 1568 if (chan == 14) 1569 mhz = 2484; 1570 else 1571 mhz = 2412 + 5 * (chan - 1); 1572 1573 /* Tune IF to 748MHz to suit the IF LO input of the 1574 * RF2494B, which is 2 x IF. No need to set an IF divider 1575 * because an IF in 526MHz - 952MHz is allowed. 1576 * 1577 * XIN is 44.000MHz, so divide it by two to get allowable 1578 * range of 2-25MHz. SiLabs tells me that this is not 1579 * strictly necessary. 1580 */ 1581 1582 if (atw_xindiv2) 1583 R = 44; 1584 else 1585 R = 88; 1586 1587 /* Power-up RF, IF synthesizers. */ 1588 atw_si4126_write(sc, SI4126_POWER, 1589 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1590 1591 /* set LPWR, too? */ 1592 atw_si4126_write(sc, SI4126_MAIN, 1593 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1594 1595 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1596 * set KP2 to 1. 1597 * 1598 * REFDIF This is different from the reference driver, which 1599 * always sets SI4126_GAIN to 0. 1600 */ 1601 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1602 1603 atw_si4126_write(sc, SI4126_GAIN, gain); 1604 1605 /* XIN = 44MHz. 1606 * 1607 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1608 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1609 * 1610 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1611 * so that 1496/88 * 44MHz = 748MHz. 1612 */ 1613 atw_si4126_write(sc, SI4126_IFN, 1496); 1614 1615 atw_si4126_write(sc, SI4126_IFR, R); 1616 1617 #ifndef ATW_REFSLAVE 1618 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1619 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1620 * which has no RF1! 1621 */ 1622 atw_si4126_write(sc, SI4126_RF1R, R); 1623 1624 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1625 #endif 1626 1627 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1628 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1629 * Now let's multiply it to mhz. So mhz - IF = N. 1630 */ 1631 atw_si4126_write(sc, SI4126_RF2R, R); 1632 1633 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1634 1635 /* wait 100us from power-up for RF, IF to settle */ 1636 DELAY(100); 1637 1638 gpio = ATW_READ(sc, ATW_GPIO); 1639 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1640 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1641 1642 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1643 /* Set a Prism RF front-end to a special mode for channel 14? 1644 * 1645 * Apparently the SMC2635W needs this, although I don't think 1646 * it has a Prism RF. 1647 */ 1648 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1649 } 1650 ATW_WRITE(sc, ATW_GPIO, gpio); 1651 1652 #ifdef ATW_SYNDEBUG 1653 atw_si4126_print(sc); 1654 #endif /* ATW_SYNDEBUG */ 1655 } 1656 1657 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1658 * diversity. 1659 * 1660 * !!! 1661 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1662 * !!! 1663 */ 1664 static int 1665 atw_rf3000_init(struct atw_softc *sc) 1666 { 1667 int rc = 0; 1668 1669 atw_bbp_io_enable(sc, 1); 1670 1671 /* CCA is acquisition sensitive */ 1672 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1673 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1674 1675 if (rc != 0) 1676 goto out; 1677 1678 /* enable diversity */ 1679 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1680 1681 if (rc != 0) 1682 goto out; 1683 1684 /* sensible setting from a binary-only driver */ 1685 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1686 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1687 1688 if (rc != 0) 1689 goto out; 1690 1691 /* magic from a binary-only driver */ 1692 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1693 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1694 1695 if (rc != 0) 1696 goto out; 1697 1698 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1699 1700 if (rc != 0) 1701 goto out; 1702 1703 /* XXX Reference driver remarks that Abocom sets this to 50. 1704 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1705 * in the "reserved" area of register RF3000_OPTIONS1. 1706 */ 1707 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1708 1709 if (rc != 0) 1710 goto out; 1711 1712 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1713 1714 if (rc != 0) 1715 goto out; 1716 1717 out: 1718 atw_bbp_io_enable(sc, 0); 1719 return rc; 1720 } 1721 1722 #ifdef ATW_BBPDEBUG 1723 static void 1724 atw_rf3000_print(struct atw_softc *sc) 1725 { 1726 struct ifnet *ifp = &sc->sc_if; 1727 u_int addr, val; 1728 1729 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1730 return; 1731 1732 for (addr = 0x01; addr <= 0x15; addr++) { 1733 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1734 if (atw_rf3000_read(sc, addr, &val) != 0) { 1735 printf("<unknown> (quitting print-out)\n"); 1736 break; 1737 } 1738 printf("%08x\n", val); 1739 } 1740 } 1741 #endif /* ATW_BBPDEBUG */ 1742 1743 /* Set the power settings on the BBP for channel `chan'. */ 1744 static int 1745 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1746 { 1747 int rc = 0; 1748 u_int32_t reg; 1749 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1750 1751 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1752 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1753 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1754 1755 /* odd channels: LSB, even channels: MSB */ 1756 if (chan % 2 == 1) { 1757 txpower &= 0xFF; 1758 lpf_cutoff &= 0xFF; 1759 lna_gs_thresh &= 0xFF; 1760 } else { 1761 txpower >>= 8; 1762 lpf_cutoff >>= 8; 1763 lna_gs_thresh >>= 8; 1764 } 1765 1766 #ifdef ATW_BBPDEBUG 1767 atw_rf3000_print(sc); 1768 #endif /* ATW_BBPDEBUG */ 1769 1770 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1771 "lna_gs_thresh %02x\n", 1772 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1773 1774 atw_bbp_io_enable(sc, 1); 1775 1776 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1777 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1778 goto out; 1779 1780 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1781 goto out; 1782 1783 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1784 goto out; 1785 1786 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1787 1788 if (rc != 0) 1789 goto out; 1790 1791 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1792 1793 if (rc != 0) 1794 goto out; 1795 1796 #ifdef ATW_BBPDEBUG 1797 atw_rf3000_print(sc); 1798 #endif /* ATW_BBPDEBUG */ 1799 1800 out: 1801 atw_bbp_io_enable(sc, 0); 1802 1803 /* set beacon, rts, atim transmit power */ 1804 reg = ATW_READ(sc, ATW_PLCPHD); 1805 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1806 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1807 ATW_PLCPHD_SERVICE_MASK); 1808 ATW_WRITE(sc, ATW_PLCPHD, reg); 1809 DELAY(atw_plcphd_delay); 1810 1811 return rc; 1812 } 1813 1814 /* Write a register on the RF3000 baseband processor using the 1815 * registers provided by the ADM8211 for this purpose. 1816 * 1817 * Return 0 on success. 1818 */ 1819 static int 1820 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1821 { 1822 u_int32_t reg; 1823 int i; 1824 1825 reg = sc->sc_bbpctl_wr | 1826 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1827 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1828 1829 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1830 ATW_WRITE(sc, ATW_BBPCTL, reg); 1831 DELAY(2 * atw_pseudo_milli); 1832 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1833 break; 1834 } 1835 1836 if (i < 0) { 1837 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1838 return ETIMEDOUT; 1839 } 1840 return 0; 1841 } 1842 1843 /* Read a register on the RF3000 baseband processor using the registers 1844 * the ADM8211 provides for this purpose. 1845 * 1846 * The 7-bit register address is addr. Record the 8-bit data in the register 1847 * in *val. 1848 * 1849 * Return 0 on success. 1850 * 1851 * XXX This does not seem to work. The ADM8211 must require more or 1852 * different magic to read the chip than to write it. Possibly some 1853 * of the magic I have derived from a binary-only driver concerns 1854 * the "chip address" (see the RF3000 manual). 1855 */ 1856 #ifdef ATW_BBPDEBUG 1857 static int 1858 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1859 { 1860 u_int32_t reg; 1861 int i; 1862 1863 for (i = 1000; --i >= 0; ) { 1864 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1865 break; 1866 DELAY(100); 1867 } 1868 1869 if (i < 0) { 1870 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1871 sc->sc_dev.dv_xname); 1872 return ETIMEDOUT; 1873 } 1874 1875 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1876 1877 ATW_WRITE(sc, ATW_BBPCTL, reg); 1878 1879 for (i = 1000; --i >= 0; ) { 1880 DELAY(100); 1881 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1882 break; 1883 } 1884 1885 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1886 1887 if (i < 0) { 1888 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1889 sc->sc_dev.dv_xname, reg); 1890 return ETIMEDOUT; 1891 } 1892 if (val != NULL) 1893 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1894 return 0; 1895 } 1896 #endif /* ATW_BBPDEBUG */ 1897 1898 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1899 * provided by the ADM8211 for that purpose. 1900 * 1901 * val is 18 bits of data, and val is the 4-bit address of the register. 1902 * 1903 * Return 0 on success. 1904 */ 1905 static void 1906 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1907 { 1908 uint32_t bits, mask, reg; 1909 const int nbits = 22; 1910 1911 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1912 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1913 1914 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1915 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1916 1917 reg = ATW_SYNRF_SELSYN; 1918 /* reference driver: reset Si4126 serial bus to initial 1919 * conditions? 1920 */ 1921 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1922 ATW_WRITE(sc, ATW_SYNRF, reg); 1923 1924 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1925 if ((bits & mask) != 0) 1926 reg |= ATW_SYNRF_SYNDATA; 1927 else 1928 reg &= ~ATW_SYNRF_SYNDATA; 1929 ATW_WRITE(sc, ATW_SYNRF, reg); 1930 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1931 ATW_WRITE(sc, ATW_SYNRF, reg); 1932 } 1933 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1934 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1935 } 1936 1937 /* Read 18-bit data from the 4-bit address addr in Si4126 1938 * RF synthesizer and write the data to *val. Return 0 on success. 1939 * 1940 * XXX This does not seem to work. The ADM8211 must require more or 1941 * different magic to read the chip than to write it. 1942 */ 1943 #ifdef ATW_SYNDEBUG 1944 static int 1945 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1946 { 1947 u_int32_t reg; 1948 int i; 1949 1950 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1951 1952 for (i = 1000; --i >= 0; ) { 1953 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1954 break; 1955 DELAY(100); 1956 } 1957 1958 if (i < 0) { 1959 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1960 sc->sc_dev.dv_xname); 1961 return ETIMEDOUT; 1962 } 1963 1964 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1965 1966 ATW_WRITE(sc, ATW_SYNCTL, reg); 1967 1968 for (i = 1000; --i >= 0; ) { 1969 DELAY(100); 1970 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1971 break; 1972 } 1973 1974 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1975 1976 if (i < 0) { 1977 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1978 sc->sc_dev.dv_xname, reg); 1979 return ETIMEDOUT; 1980 } 1981 if (val != NULL) 1982 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1983 ATW_SYNCTL_DATA_MASK); 1984 return 0; 1985 } 1986 #endif /* ATW_SYNDEBUG */ 1987 1988 /* XXX is the endianness correct? test. */ 1989 #define atw_calchash(addr) \ 1990 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1991 1992 /* 1993 * atw_filter_setup: 1994 * 1995 * Set the ADM8211's receive filter. 1996 */ 1997 static void 1998 atw_filter_setup(struct atw_softc *sc) 1999 { 2000 struct ieee80211com *ic = &sc->sc_ic; 2001 struct ethercom *ec = &sc->sc_ec; 2002 struct ifnet *ifp = &sc->sc_if; 2003 int hash; 2004 u_int32_t hashes[2]; 2005 struct ether_multi *enm; 2006 struct ether_multistep step; 2007 2008 /* According to comments in tlp_al981_filter_setup 2009 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2010 * multicast filter to be set while it is running. Hopefully 2011 * the ADM8211 is not the same! 2012 */ 2013 if ((ifp->if_flags & IFF_RUNNING) != 0) 2014 atw_idle(sc, ATW_NAR_SR); 2015 2016 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2017 ifp->if_flags &= ~IFF_ALLMULTI; 2018 2019 /* XXX in scan mode, do not filter packets. Maybe this is 2020 * unnecessary. 2021 */ 2022 if (ic->ic_state == IEEE80211_S_SCAN || 2023 (ifp->if_flags & IFF_PROMISC) != 0) { 2024 sc->sc_opmode |= ATW_NAR_PR; 2025 goto allmulti; 2026 } 2027 2028 hashes[0] = hashes[1] = 0x0; 2029 2030 /* 2031 * Program the 64-bit multicast hash filter. 2032 */ 2033 ETHER_FIRST_MULTI(step, ec, enm); 2034 while (enm != NULL) { 2035 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2036 ETHER_ADDR_LEN) != 0) 2037 goto allmulti; 2038 2039 hash = atw_calchash(enm->enm_addrlo); 2040 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2041 ETHER_NEXT_MULTI(step, enm); 2042 sc->sc_opmode |= ATW_NAR_MM; 2043 } 2044 ifp->if_flags &= ~IFF_ALLMULTI; 2045 goto setit; 2046 2047 allmulti: 2048 sc->sc_opmode |= ATW_NAR_MM; 2049 ifp->if_flags |= IFF_ALLMULTI; 2050 hashes[0] = hashes[1] = 0xffffffff; 2051 2052 setit: 2053 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2054 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2055 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2056 DELAY(atw_nar_delay); 2057 ATW_WRITE(sc, ATW_RDR, 0x1); 2058 2059 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2060 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2061 } 2062 2063 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2064 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2065 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2066 * no beacon with the preferred BSSID and SSID in the number of 2067 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2068 */ 2069 static void 2070 atw_write_bssid(struct atw_softc *sc) 2071 { 2072 struct ieee80211com *ic = &sc->sc_ic; 2073 u_int8_t *bssid; 2074 2075 bssid = ic->ic_bss->ni_bssid; 2076 2077 ATW_WRITE(sc, ATW_BSSID0, 2078 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2079 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2080 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2081 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2082 2083 ATW_WRITE(sc, ATW_ABDA1, 2084 (ATW_READ(sc, ATW_ABDA1) & 2085 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2086 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2087 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2088 2089 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2090 ether_sprintf(sc->sc_bssid))); 2091 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2092 2093 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2094 } 2095 2096 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2097 * 16-bit word. 2098 */ 2099 static void 2100 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2101 { 2102 u_int i; 2103 u_int8_t *ptr; 2104 2105 memcpy(&sc->sc_sram[ofs], buf, buflen); 2106 2107 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2108 2109 KASSERT(buflen + ofs <= sc->sc_sramlen); 2110 2111 ptr = &sc->sc_sram[ofs]; 2112 2113 for (i = 0; i < buflen; i += 2) { 2114 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2115 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2116 DELAY(atw_writewep_delay); 2117 2118 ATW_WRITE(sc, ATW_WESK, 2119 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2120 DELAY(atw_writewep_delay); 2121 } 2122 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2123 2124 if (sc->sc_if.if_flags & IFF_DEBUG) { 2125 int n_octets = 0; 2126 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2127 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2128 for (i = 0; i < buflen; i++) { 2129 printf(" %02x", ptr[i]); 2130 if (++n_octets % 24 == 0) 2131 printf("\n"); 2132 } 2133 if (n_octets % 24 != 0) 2134 printf("\n"); 2135 } 2136 } 2137 2138 static int 2139 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2140 { 2141 struct atw_softc *sc = ic->ic_ifp->if_softc; 2142 u_int keyix = k->wk_keyix; 2143 2144 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2145 2146 if (keyix >= IEEE80211_WEP_NKID) 2147 return 0; 2148 if (k->wk_keylen != 0) 2149 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2150 2151 return 1; 2152 } 2153 2154 static int 2155 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2156 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2157 { 2158 struct atw_softc *sc = ic->ic_ifp->if_softc; 2159 2160 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2161 2162 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2163 return 0; 2164 2165 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2166 2167 return 1; 2168 } 2169 2170 static void 2171 atw_key_update_begin(struct ieee80211com *ic) 2172 { 2173 #ifdef ATW_DEBUG 2174 struct ifnet *ifp = ic->ic_ifp; 2175 struct atw_softc *sc = ifp->if_softc; 2176 #endif 2177 2178 DPRINTF(sc, ("%s:\n", __func__)); 2179 } 2180 2181 static void 2182 atw_key_update_end(struct ieee80211com *ic) 2183 { 2184 struct ifnet *ifp = ic->ic_ifp; 2185 struct atw_softc *sc = ifp->if_softc; 2186 2187 DPRINTF(sc, ("%s:\n", __func__)); 2188 2189 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2190 return; 2191 if (ATW_IS_ENABLED(sc) == 0) 2192 return; 2193 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2194 atw_write_wep(sc); 2195 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2196 DELAY(atw_nar_delay); 2197 ATW_WRITE(sc, ATW_RDR, 0x1); 2198 } 2199 2200 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2201 static void 2202 atw_write_wep(struct atw_softc *sc) 2203 { 2204 struct ieee80211com *ic = &sc->sc_ic; 2205 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2206 u_int8_t buf[IEEE80211_WEP_NKID] 2207 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2208 u_int32_t reg; 2209 int i; 2210 2211 sc->sc_wepctl = 0; 2212 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2213 2214 memset(&buf[0][0], 0, sizeof(buf)); 2215 2216 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2217 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2218 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2219 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2220 buf[i][1] = ATW_WEP_ENABLED; 2221 } else { 2222 buf[i][1] = 0; 2223 continue; 2224 } 2225 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2226 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2227 ic->ic_nw_keys[i].wk_keylen - 1); 2228 } 2229 2230 reg = ATW_READ(sc, ATW_MACTEST); 2231 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2232 reg &= ~ATW_MACTEST_KEYID_MASK; 2233 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2234 ATW_WRITE(sc, ATW_MACTEST, reg); 2235 2236 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2237 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2238 2239 switch (sc->sc_rev) { 2240 case ATW_REVISION_AB: 2241 case ATW_REVISION_AF: 2242 /* Bypass WEP on Rx. */ 2243 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2244 break; 2245 default: 2246 break; 2247 } 2248 2249 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2250 sizeof(buf)); 2251 2252 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2253 } 2254 2255 static void 2256 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2257 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2258 { 2259 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2260 2261 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2262 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2263 return; 2264 2265 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2266 2267 switch (subtype) { 2268 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2269 case IEEE80211_FC0_SUBTYPE_BEACON: 2270 if (ic->ic_opmode == IEEE80211_M_IBSS && 2271 ic->ic_state == IEEE80211_S_RUN) { 2272 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2273 (void)ieee80211_ibss_merge(ni); 2274 } 2275 break; 2276 default: 2277 break; 2278 } 2279 return; 2280 } 2281 2282 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2283 * In ad hoc mode, the SSID is written to the beacons sent by the 2284 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2285 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2286 * indications. 2287 */ 2288 static void 2289 atw_write_ssid(struct atw_softc *sc) 2290 { 2291 struct ieee80211com *ic = &sc->sc_ic; 2292 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2293 * it only expects the element length, not its ID. 2294 */ 2295 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2296 2297 memset(buf, 0, sizeof(buf)); 2298 buf[0] = ic->ic_bss->ni_esslen; 2299 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2300 2301 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2302 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2303 } 2304 2305 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2306 * In ad hoc mode, the supported rates are written to beacons sent by the 2307 * ADM8211. 2308 */ 2309 static void 2310 atw_write_sup_rates(struct atw_softc *sc) 2311 { 2312 struct ieee80211com *ic = &sc->sc_ic; 2313 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2314 * supported rates 2315 */ 2316 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2317 2318 memset(buf, 0, sizeof(buf)); 2319 2320 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2321 2322 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2323 ic->ic_bss->ni_rates.rs_nrates); 2324 2325 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2326 } 2327 2328 /* Start/stop sending beacons. */ 2329 void 2330 atw_start_beacon(struct atw_softc *sc, int start) 2331 { 2332 struct ieee80211com *ic = &sc->sc_ic; 2333 uint16_t chan; 2334 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2335 size_t len; 2336 2337 if (ATW_IS_ENABLED(sc) == 0) 2338 return; 2339 2340 /* start beacons */ 2341 len = sizeof(struct ieee80211_frame) + 2342 8 /* timestamp */ + 2 /* beacon interval */ + 2343 2 /* capability info */ + 2344 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2345 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2346 3 /* DS parameters */ + 2347 IEEE80211_CRC_LEN; 2348 2349 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2350 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2351 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2352 2353 ATW_WRITE(sc, ATW_BCNT, bcnt); 2354 ATW_WRITE(sc, ATW_CAP1, cap1); 2355 2356 if (!start) 2357 return; 2358 2359 /* TBD use ni_capinfo */ 2360 2361 capinfo = 0; 2362 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2363 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2364 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2365 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2366 2367 switch (ic->ic_opmode) { 2368 case IEEE80211_M_IBSS: 2369 len += 4; /* IBSS parameters */ 2370 capinfo |= IEEE80211_CAPINFO_IBSS; 2371 break; 2372 case IEEE80211_M_HOSTAP: 2373 /* XXX 6-byte minimum TIM */ 2374 len += atw_beacon_len_adjust; 2375 capinfo |= IEEE80211_CAPINFO_ESS; 2376 break; 2377 default: 2378 return; 2379 } 2380 2381 /* set listen interval 2382 * XXX do software units agree w/ hardware? 2383 */ 2384 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2385 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2386 2387 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2388 2389 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2390 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2391 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2392 2393 ATW_WRITE(sc, ATW_BCNT, bcnt); 2394 ATW_WRITE(sc, ATW_BPLI, bpli); 2395 ATW_WRITE(sc, ATW_CAP0, cap0); 2396 ATW_WRITE(sc, ATW_CAP1, cap1); 2397 2398 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2399 sc->sc_dev.dv_xname, bcnt)); 2400 2401 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2402 sc->sc_dev.dv_xname, cap1)); 2403 } 2404 2405 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2406 static inline uint32_t 2407 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2408 { 2409 /* Following the reference driver's lead, I compute 2410 * 2411 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2412 * 2413 * without using 64-bit arithmetic, using the following 2414 * relationship: 2415 * 2416 * (0x100000000 * H + L) % m 2417 * = ((0x100000000 % m) * H + L) % m 2418 * = (((0xffffffff + 1) % m) * H + L) % m 2419 * = ((0xffffffff % m + 1 % m) * H + L) % m 2420 * = ((0xffffffff % m + 1) * H + L) % m 2421 */ 2422 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2423 } 2424 2425 static uint64_t 2426 atw_get_tsft(struct atw_softc *sc) 2427 { 2428 int i; 2429 uint32_t tsfth, tsftl; 2430 for (i = 0; i < 2; i++) { 2431 tsfth = ATW_READ(sc, ATW_TSFTH); 2432 tsftl = ATW_READ(sc, ATW_TSFTL); 2433 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2434 break; 2435 } 2436 return ((uint64_t)tsfth << 32) | tsftl; 2437 } 2438 2439 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2440 * the ieee80211com. 2441 * 2442 * Predict the next target beacon transmission time (TBTT) and 2443 * write it to the ADM8211. 2444 */ 2445 static void 2446 atw_predict_beacon(struct atw_softc *sc) 2447 { 2448 #define TBTTOFS 20 /* TU */ 2449 2450 struct ieee80211com *ic = &sc->sc_ic; 2451 uint64_t tsft; 2452 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2453 union { 2454 uint64_t word; 2455 uint8_t tstamp[8]; 2456 } u; 2457 2458 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2459 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2460 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2461 tsft = atw_get_tsft(sc); 2462 u.word = htole64(tsft); 2463 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2464 sizeof(ic->ic_bss->ni_tstamp)); 2465 } else 2466 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2467 2468 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2469 2470 tsftl = tsft & 0xFFFFFFFF; 2471 tsfth = tsft >> 32; 2472 2473 /* We sent/received the last beacon `past' microseconds 2474 * after the interval divided the TSF timer. 2475 */ 2476 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2477 2478 /* Skip ten beacons so that the TBTT cannot pass before 2479 * we've programmed it. Ten is an arbitrary number. 2480 */ 2481 tbtt = past_even + ival * 10; 2482 2483 ATW_WRITE(sc, ATW_TOFS1, 2484 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2485 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2486 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2487 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2488 #undef TBTTOFS 2489 } 2490 2491 static void 2492 atw_next_scan(void *arg) 2493 { 2494 struct atw_softc *sc = arg; 2495 struct ieee80211com *ic = &sc->sc_ic; 2496 int s; 2497 2498 /* don't call atw_start w/o network interrupts blocked */ 2499 s = splnet(); 2500 if (ic->ic_state == IEEE80211_S_SCAN) 2501 ieee80211_next_scan(ic); 2502 splx(s); 2503 } 2504 2505 /* Synchronize the hardware state with the software state. */ 2506 static int 2507 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2508 { 2509 struct ifnet *ifp = ic->ic_ifp; 2510 struct atw_softc *sc = ifp->if_softc; 2511 enum ieee80211_state ostate; 2512 int error = 0; 2513 2514 ostate = ic->ic_state; 2515 callout_stop(&sc->sc_scan_ch); 2516 2517 switch (nstate) { 2518 case IEEE80211_S_AUTH: 2519 case IEEE80211_S_ASSOC: 2520 error = atw_tune(sc); 2521 break; 2522 case IEEE80211_S_INIT: 2523 callout_stop(&sc->sc_scan_ch); 2524 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2525 atw_start_beacon(sc, 0); 2526 break; 2527 case IEEE80211_S_SCAN: 2528 error = atw_tune(sc); 2529 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2530 atw_next_scan, sc); 2531 break; 2532 case IEEE80211_S_RUN: 2533 error = atw_tune(sc); 2534 atw_write_bssid(sc); 2535 atw_write_ssid(sc); 2536 atw_write_sup_rates(sc); 2537 2538 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2539 ic->ic_opmode == IEEE80211_M_MONITOR) 2540 break; 2541 2542 /* set listen interval 2543 * XXX do software units agree w/ hardware? 2544 */ 2545 ATW_WRITE(sc, ATW_BPLI, 2546 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2547 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2548 ATW_BPLI_LI_MASK)); 2549 2550 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2551 ATW_READ(sc, ATW_BPLI))); 2552 2553 atw_predict_beacon(sc); 2554 2555 switch (ic->ic_opmode) { 2556 case IEEE80211_M_AHDEMO: 2557 case IEEE80211_M_HOSTAP: 2558 case IEEE80211_M_IBSS: 2559 atw_start_beacon(sc, 1); 2560 break; 2561 case IEEE80211_M_MONITOR: 2562 case IEEE80211_M_STA: 2563 break; 2564 } 2565 2566 break; 2567 } 2568 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2569 } 2570 2571 /* 2572 * atw_add_rxbuf: 2573 * 2574 * Add a receive buffer to the indicated descriptor. 2575 */ 2576 int 2577 atw_add_rxbuf(struct atw_softc *sc, int idx) 2578 { 2579 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2580 struct mbuf *m; 2581 int error; 2582 2583 MGETHDR(m, M_DONTWAIT, MT_DATA); 2584 if (m == NULL) 2585 return (ENOBUFS); 2586 2587 MCLGET(m, M_DONTWAIT); 2588 if ((m->m_flags & M_EXT) == 0) { 2589 m_freem(m); 2590 return (ENOBUFS); 2591 } 2592 2593 if (rxs->rxs_mbuf != NULL) 2594 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2595 2596 rxs->rxs_mbuf = m; 2597 2598 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2599 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2600 BUS_DMA_READ|BUS_DMA_NOWAIT); 2601 if (error) { 2602 printf("%s: can't load rx DMA map %d, error = %d\n", 2603 sc->sc_dev.dv_xname, idx, error); 2604 panic("atw_add_rxbuf"); /* XXX */ 2605 } 2606 2607 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2608 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2609 2610 ATW_INIT_RXDESC(sc, idx); 2611 2612 return (0); 2613 } 2614 2615 /* 2616 * Release any queued transmit buffers. 2617 */ 2618 void 2619 atw_txdrain(struct atw_softc *sc) 2620 { 2621 struct atw_txsoft *txs; 2622 2623 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2624 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2625 if (txs->txs_mbuf != NULL) { 2626 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2627 m_freem(txs->txs_mbuf); 2628 txs->txs_mbuf = NULL; 2629 } 2630 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2631 sc->sc_txfree += txs->txs_ndescs; 2632 } 2633 2634 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2635 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2636 sc->sc_txfree != ATW_NTXDESC)); 2637 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2638 sc->sc_tx_timer = 0; 2639 } 2640 2641 /* 2642 * atw_stop: [ ifnet interface function ] 2643 * 2644 * Stop transmission on the interface. 2645 */ 2646 void 2647 atw_stop(struct ifnet *ifp, int disable) 2648 { 2649 struct atw_softc *sc = ifp->if_softc; 2650 struct ieee80211com *ic = &sc->sc_ic; 2651 2652 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2653 2654 /* Disable interrupts. */ 2655 ATW_WRITE(sc, ATW_IER, 0); 2656 2657 /* Stop the transmit and receive processes. */ 2658 sc->sc_opmode = 0; 2659 ATW_WRITE(sc, ATW_NAR, 0); 2660 DELAY(atw_nar_delay); 2661 ATW_WRITE(sc, ATW_TDBD, 0); 2662 ATW_WRITE(sc, ATW_TDBP, 0); 2663 ATW_WRITE(sc, ATW_RDB, 0); 2664 2665 atw_txdrain(sc); 2666 2667 if (disable) { 2668 atw_rxdrain(sc); 2669 atw_disable(sc); 2670 } 2671 2672 /* 2673 * Mark the interface down and cancel the watchdog timer. 2674 */ 2675 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2676 sc->sc_tx_timer = 0; 2677 ifp->if_timer = 0; 2678 2679 if (!disable) 2680 atw_reset(sc); 2681 } 2682 2683 /* 2684 * atw_rxdrain: 2685 * 2686 * Drain the receive queue. 2687 */ 2688 void 2689 atw_rxdrain(struct atw_softc *sc) 2690 { 2691 struct atw_rxsoft *rxs; 2692 int i; 2693 2694 for (i = 0; i < ATW_NRXDESC; i++) { 2695 rxs = &sc->sc_rxsoft[i]; 2696 if (rxs->rxs_mbuf == NULL) 2697 continue; 2698 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2699 m_freem(rxs->rxs_mbuf); 2700 rxs->rxs_mbuf = NULL; 2701 } 2702 } 2703 2704 /* 2705 * atw_detach: 2706 * 2707 * Detach an ADM8211 interface. 2708 */ 2709 int 2710 atw_detach(struct atw_softc *sc) 2711 { 2712 struct ifnet *ifp = &sc->sc_if; 2713 struct atw_rxsoft *rxs; 2714 struct atw_txsoft *txs; 2715 int i; 2716 2717 /* 2718 * Succeed now if there isn't any work to do. 2719 */ 2720 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2721 return (0); 2722 2723 callout_stop(&sc->sc_scan_ch); 2724 2725 ieee80211_ifdetach(&sc->sc_ic); 2726 if_detach(ifp); 2727 2728 for (i = 0; i < ATW_NRXDESC; i++) { 2729 rxs = &sc->sc_rxsoft[i]; 2730 if (rxs->rxs_mbuf != NULL) { 2731 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2732 m_freem(rxs->rxs_mbuf); 2733 rxs->rxs_mbuf = NULL; 2734 } 2735 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2736 } 2737 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2738 txs = &sc->sc_txsoft[i]; 2739 if (txs->txs_mbuf != NULL) { 2740 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2741 m_freem(txs->txs_mbuf); 2742 txs->txs_mbuf = NULL; 2743 } 2744 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2745 } 2746 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2747 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2748 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2749 sizeof(struct atw_control_data)); 2750 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2751 2752 shutdownhook_disestablish(sc->sc_sdhook); 2753 powerhook_disestablish(sc->sc_powerhook); 2754 2755 if (sc->sc_srom) 2756 free(sc->sc_srom, M_DEVBUF); 2757 2758 return (0); 2759 } 2760 2761 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2762 void 2763 atw_shutdown(void *arg) 2764 { 2765 struct atw_softc *sc = arg; 2766 2767 atw_stop(&sc->sc_if, 1); 2768 } 2769 2770 int 2771 atw_intr(void *arg) 2772 { 2773 struct atw_softc *sc = arg; 2774 struct ifnet *ifp = &sc->sc_if; 2775 u_int32_t status, rxstatus, txstatus, linkstatus; 2776 int handled = 0, txthresh; 2777 2778 #ifdef DEBUG 2779 if (ATW_IS_ENABLED(sc) == 0) 2780 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2781 #endif 2782 2783 /* 2784 * If the interface isn't running, the interrupt couldn't 2785 * possibly have come from us. 2786 */ 2787 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2788 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2789 return (0); 2790 2791 for (;;) { 2792 status = ATW_READ(sc, ATW_STSR); 2793 2794 if (status) 2795 ATW_WRITE(sc, ATW_STSR, status); 2796 2797 #ifdef ATW_DEBUG 2798 #define PRINTINTR(flag) do { \ 2799 if ((status & flag) != 0) { \ 2800 printf("%s" #flag, delim); \ 2801 delim = ","; \ 2802 } \ 2803 } while (0) 2804 2805 if (atw_debug > 1 && status) { 2806 const char *delim = "<"; 2807 2808 printf("%s: reg[STSR] = %x", 2809 sc->sc_dev.dv_xname, status); 2810 2811 PRINTINTR(ATW_INTR_FBE); 2812 PRINTINTR(ATW_INTR_LINKOFF); 2813 PRINTINTR(ATW_INTR_LINKON); 2814 PRINTINTR(ATW_INTR_RCI); 2815 PRINTINTR(ATW_INTR_RDU); 2816 PRINTINTR(ATW_INTR_REIS); 2817 PRINTINTR(ATW_INTR_RPS); 2818 PRINTINTR(ATW_INTR_TCI); 2819 PRINTINTR(ATW_INTR_TDU); 2820 PRINTINTR(ATW_INTR_TLT); 2821 PRINTINTR(ATW_INTR_TPS); 2822 PRINTINTR(ATW_INTR_TRT); 2823 PRINTINTR(ATW_INTR_TUF); 2824 PRINTINTR(ATW_INTR_BCNTC); 2825 PRINTINTR(ATW_INTR_ATIME); 2826 PRINTINTR(ATW_INTR_TBTT); 2827 PRINTINTR(ATW_INTR_TSCZ); 2828 PRINTINTR(ATW_INTR_TSFTF); 2829 printf(">\n"); 2830 } 2831 #undef PRINTINTR 2832 #endif /* ATW_DEBUG */ 2833 2834 if ((status & sc->sc_inten) == 0) 2835 break; 2836 2837 handled = 1; 2838 2839 rxstatus = status & sc->sc_rxint_mask; 2840 txstatus = status & sc->sc_txint_mask; 2841 linkstatus = status & sc->sc_linkint_mask; 2842 2843 if (linkstatus) { 2844 atw_linkintr(sc, linkstatus); 2845 } 2846 2847 if (rxstatus) { 2848 /* Grab any new packets. */ 2849 atw_rxintr(sc); 2850 2851 if (rxstatus & ATW_INTR_RDU) { 2852 printf("%s: receive ring overrun\n", 2853 sc->sc_dev.dv_xname); 2854 /* Get the receive process going again. */ 2855 ATW_WRITE(sc, ATW_RDR, 0x1); 2856 break; 2857 } 2858 } 2859 2860 if (txstatus) { 2861 /* Sweep up transmit descriptors. */ 2862 atw_txintr(sc); 2863 2864 if (txstatus & ATW_INTR_TLT) 2865 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2866 sc->sc_dev.dv_xname)); 2867 2868 if (txstatus & ATW_INTR_TRT) 2869 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2870 sc->sc_dev.dv_xname)); 2871 2872 /* If Tx under-run, increase our transmit threshold 2873 * if another is available. 2874 */ 2875 txthresh = sc->sc_txthresh + 1; 2876 if ((txstatus & ATW_INTR_TUF) && 2877 sc->sc_txth[txthresh].txth_name != NULL) { 2878 /* Idle the transmit process. */ 2879 atw_idle(sc, ATW_NAR_ST); 2880 2881 sc->sc_txthresh = txthresh; 2882 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2883 sc->sc_opmode |= 2884 sc->sc_txth[txthresh].txth_opmode; 2885 printf("%s: transmit underrun; new " 2886 "threshold: %s\n", sc->sc_dev.dv_xname, 2887 sc->sc_txth[txthresh].txth_name); 2888 2889 /* Set the new threshold and restart 2890 * the transmit process. 2891 */ 2892 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2893 DELAY(atw_nar_delay); 2894 ATW_WRITE(sc, ATW_RDR, 0x1); 2895 /* XXX Log every Nth underrun from 2896 * XXX now on? 2897 */ 2898 } 2899 } 2900 2901 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2902 if (status & ATW_INTR_TPS) 2903 printf("%s: transmit process stopped\n", 2904 sc->sc_dev.dv_xname); 2905 if (status & ATW_INTR_RPS) 2906 printf("%s: receive process stopped\n", 2907 sc->sc_dev.dv_xname); 2908 (void)atw_init(ifp); 2909 break; 2910 } 2911 2912 if (status & ATW_INTR_FBE) { 2913 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2914 (void)atw_init(ifp); 2915 break; 2916 } 2917 2918 /* 2919 * Not handled: 2920 * 2921 * Transmit buffer unavailable -- normal 2922 * condition, nothing to do, really. 2923 * 2924 * Early receive interrupt -- not available on 2925 * all chips, we just use RI. We also only 2926 * use single-segment receive DMA, so this 2927 * is mostly useless. 2928 * 2929 * TBD others 2930 */ 2931 } 2932 2933 /* Try to get more packets going. */ 2934 atw_start(ifp); 2935 2936 return (handled); 2937 } 2938 2939 /* 2940 * atw_idle: 2941 * 2942 * Cause the transmit and/or receive processes to go idle. 2943 * 2944 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2945 * process in STSR if I clear SR or ST after the process has already 2946 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2947 * do not seem to be too reliable. Perhaps I have the sense of the 2948 * Rx bits switched with the Tx bits? 2949 */ 2950 void 2951 atw_idle(struct atw_softc *sc, u_int32_t bits) 2952 { 2953 u_int32_t ackmask = 0, opmode, stsr, test0; 2954 int i, s; 2955 2956 s = splnet(); 2957 2958 opmode = sc->sc_opmode & ~bits; 2959 2960 if (bits & ATW_NAR_SR) 2961 ackmask |= ATW_INTR_RPS; 2962 2963 if (bits & ATW_NAR_ST) { 2964 ackmask |= ATW_INTR_TPS; 2965 /* set ATW_NAR_HF to flush TX FIFO. */ 2966 opmode |= ATW_NAR_HF; 2967 } 2968 2969 ATW_WRITE(sc, ATW_NAR, opmode); 2970 DELAY(atw_nar_delay); 2971 2972 for (i = 0; i < 1000; i++) { 2973 stsr = ATW_READ(sc, ATW_STSR); 2974 if ((stsr & ackmask) == ackmask) 2975 break; 2976 DELAY(10); 2977 } 2978 2979 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2980 2981 if ((stsr & ackmask) == ackmask) 2982 goto out; 2983 2984 test0 = ATW_READ(sc, ATW_TEST0); 2985 2986 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2987 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2988 printf("%s: transmit process not idle [%s]\n", 2989 sc->sc_dev.dv_xname, 2990 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2991 printf("%s: bits %08x test0 %08x stsr %08x\n", 2992 sc->sc_dev.dv_xname, bits, test0, stsr); 2993 } 2994 2995 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2996 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2997 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2998 sc->sc_dev.dv_xname, 2999 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3000 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3001 sc->sc_dev.dv_xname, bits, test0, stsr)); 3002 } 3003 out: 3004 if ((bits & ATW_NAR_ST) != 0) 3005 atw_txdrain(sc); 3006 splx(s); 3007 return; 3008 } 3009 3010 /* 3011 * atw_linkintr: 3012 * 3013 * Helper; handle link-status interrupts. 3014 */ 3015 void 3016 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3017 { 3018 struct ieee80211com *ic = &sc->sc_ic; 3019 3020 if (ic->ic_state != IEEE80211_S_RUN) 3021 return; 3022 3023 if (linkstatus & ATW_INTR_LINKON) { 3024 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3025 sc->sc_rescan_timer = 0; 3026 } else if (linkstatus & ATW_INTR_LINKOFF) { 3027 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3028 if (ic->ic_opmode != IEEE80211_M_STA) 3029 return; 3030 sc->sc_rescan_timer = 3; 3031 sc->sc_if.if_timer = 1; 3032 } 3033 } 3034 3035 static inline int 3036 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3037 { 3038 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3039 return 0; 3040 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3041 return 0; 3042 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3043 } 3044 3045 /* 3046 * atw_rxintr: 3047 * 3048 * Helper; handle receive interrupts. 3049 */ 3050 void 3051 atw_rxintr(struct atw_softc *sc) 3052 { 3053 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3054 struct ieee80211com *ic = &sc->sc_ic; 3055 struct ieee80211_node *ni; 3056 struct ieee80211_frame_min *wh; 3057 struct ifnet *ifp = &sc->sc_if; 3058 struct atw_rxsoft *rxs; 3059 struct mbuf *m; 3060 u_int32_t rxstat; 3061 int i, len, rate, rate0; 3062 u_int32_t rssi, rssi0; 3063 3064 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3065 rxs = &sc->sc_rxsoft[i]; 3066 3067 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3068 3069 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3070 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3071 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3072 3073 if (rxstat & ATW_RXSTAT_OWN) 3074 break; /* We have processed all receive buffers. */ 3075 3076 DPRINTF3(sc, 3077 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3078 sc->sc_dev.dv_xname, 3079 rxstat, rssi0, 3080 le32toh(sc->sc_rxdescs[i].ar_buf1), 3081 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3082 3083 /* 3084 * Make sure the packet fits in one buffer. This should 3085 * always be the case. 3086 */ 3087 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3088 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3089 printf("%s: incoming packet spilled, resetting\n", 3090 sc->sc_dev.dv_xname); 3091 (void)atw_init(ifp); 3092 return; 3093 } 3094 3095 /* 3096 * If an error occurred, update stats, clear the status 3097 * word, and leave the packet buffer in place. It will 3098 * simply be reused the next time the ring comes around. 3099 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3100 * error. 3101 */ 3102 3103 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3104 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3105 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3106 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3107 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3108 ATW_RXSTAT_ICVE)) != 0)) { 3109 #define PRINTERR(bit, str) \ 3110 if (rxstat & (bit)) \ 3111 printf("%s: receive error: %s\n", \ 3112 sc->sc_dev.dv_xname, str) 3113 ifp->if_ierrors++; 3114 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3115 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3116 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3117 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3118 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3119 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3120 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3121 #undef PRINTERR 3122 ATW_INIT_RXDESC(sc, i); 3123 continue; 3124 } 3125 3126 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3127 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3128 3129 /* 3130 * No errors; receive the packet. Note the ADM8211 3131 * includes the CRC in promiscuous mode. 3132 */ 3133 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3134 3135 /* 3136 * Allocate a new mbuf cluster. If that fails, we are 3137 * out of memory, and must drop the packet and recycle 3138 * the buffer that's already attached to this descriptor. 3139 */ 3140 m = rxs->rxs_mbuf; 3141 if (atw_add_rxbuf(sc, i) != 0) { 3142 ifp->if_ierrors++; 3143 ATW_INIT_RXDESC(sc, i); 3144 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3145 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3146 continue; 3147 } 3148 3149 ifp->if_ipackets++; 3150 if (sc->sc_opmode & ATW_NAR_PR) 3151 len -= IEEE80211_CRC_LEN; 3152 m->m_pkthdr.rcvif = ifp; 3153 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3154 3155 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3156 rate = 0; 3157 else 3158 rate = rate_tbl[rate0]; 3159 3160 /* The RSSI comes straight from a register in the 3161 * baseband processor. I know that for the RF3000, 3162 * the RSSI register also contains the antenna-selection 3163 * bits. Mask those off. 3164 * 3165 * TBD Treat other basebands. 3166 */ 3167 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3168 rssi = rssi0 & RF3000_RSSI_MASK; 3169 else 3170 rssi = rssi0; 3171 3172 #if NBPFILTER > 0 3173 /* Pass this up to any BPF listeners. */ 3174 if (sc->sc_radiobpf != NULL) { 3175 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3176 3177 tap->ar_rate = rate; 3178 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3179 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3180 3181 /* TBD verify units are dB */ 3182 tap->ar_antsignal = (int)rssi; 3183 /* TBD tap->ar_flags */ 3184 3185 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3186 tap->ar_ihdr.it_len, m); 3187 } 3188 #endif /* NPBFILTER > 0 */ 3189 3190 wh = mtod(m, struct ieee80211_frame_min *); 3191 ni = ieee80211_find_rxnode(ic, wh); 3192 if (atw_hw_decrypted(sc, wh)) { 3193 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3194 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3195 } 3196 ieee80211_input(ic, m, ni, (int)rssi, 0); 3197 ieee80211_free_node(ni); 3198 } 3199 3200 /* Update the receive pointer. */ 3201 sc->sc_rxptr = i; 3202 } 3203 3204 /* 3205 * atw_txintr: 3206 * 3207 * Helper; handle transmit interrupts. 3208 */ 3209 void 3210 atw_txintr(struct atw_softc *sc) 3211 { 3212 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3213 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3214 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3215 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3216 3217 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3218 struct ifnet *ifp = &sc->sc_if; 3219 struct atw_txsoft *txs; 3220 u_int32_t txstat; 3221 3222 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3223 sc->sc_dev.dv_xname, sc->sc_flags)); 3224 3225 /* 3226 * Go through our Tx list and free mbufs for those 3227 * frames that have been transmitted. 3228 */ 3229 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3230 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3231 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3232 3233 #ifdef ATW_DEBUG 3234 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3235 int i; 3236 printf(" txsoft %p transmit chain:\n", txs); 3237 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3238 txs->txs_ndescs - 1, 3239 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3240 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3241 printf(" descriptor %d:\n", i); 3242 printf(" at_status: 0x%08x\n", 3243 le32toh(sc->sc_txdescs[i].at_stat)); 3244 printf(" at_flags: 0x%08x\n", 3245 le32toh(sc->sc_txdescs[i].at_flags)); 3246 printf(" at_buf1: 0x%08x\n", 3247 le32toh(sc->sc_txdescs[i].at_buf1)); 3248 printf(" at_buf2: 0x%08x\n", 3249 le32toh(sc->sc_txdescs[i].at_buf2)); 3250 if (i == txs->txs_lastdesc) 3251 break; 3252 } 3253 } 3254 #endif 3255 3256 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3257 if (txstat & ATW_TXSTAT_OWN) 3258 break; 3259 3260 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3261 3262 sc->sc_txfree += txs->txs_ndescs; 3263 3264 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3265 0, txs->txs_dmamap->dm_mapsize, 3266 BUS_DMASYNC_POSTWRITE); 3267 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3268 m_freem(txs->txs_mbuf); 3269 txs->txs_mbuf = NULL; 3270 3271 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3272 3273 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3274 sc->sc_txfree == 0)); 3275 ifp->if_flags &= ~IFF_OACTIVE; 3276 3277 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3278 (txstat & TXSTAT_ERRMASK) != 0) { 3279 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3280 txstat_buf, sizeof(txstat_buf)); 3281 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3282 txstat_buf, 3283 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3284 } 3285 3286 /* 3287 * Check for errors and collisions. 3288 */ 3289 if (txstat & ATW_TXSTAT_TUF) 3290 sc->sc_stats.ts_tx_tuf++; 3291 if (txstat & ATW_TXSTAT_TLT) 3292 sc->sc_stats.ts_tx_tlt++; 3293 if (txstat & ATW_TXSTAT_TRT) 3294 sc->sc_stats.ts_tx_trt++; 3295 if (txstat & ATW_TXSTAT_TRO) 3296 sc->sc_stats.ts_tx_tro++; 3297 if (txstat & ATW_TXSTAT_SOFBR) { 3298 sc->sc_stats.ts_tx_sofbr++; 3299 } 3300 3301 if ((txstat & ATW_TXSTAT_ES) == 0) 3302 ifp->if_collisions += 3303 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3304 else 3305 ifp->if_oerrors++; 3306 3307 ifp->if_opackets++; 3308 } 3309 3310 /* 3311 * If there are no more pending transmissions, cancel the watchdog 3312 * timer. 3313 */ 3314 if (txs == NULL) { 3315 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3316 sc->sc_tx_timer = 0; 3317 } 3318 #undef TXSTAT_ERRMASK 3319 #undef TXSTAT_FMT 3320 } 3321 3322 /* 3323 * atw_watchdog: [ifnet interface function] 3324 * 3325 * Watchdog timer handler. 3326 */ 3327 void 3328 atw_watchdog(struct ifnet *ifp) 3329 { 3330 struct atw_softc *sc = ifp->if_softc; 3331 struct ieee80211com *ic = &sc->sc_ic; 3332 3333 ifp->if_timer = 0; 3334 if (ATW_IS_ENABLED(sc) == 0) 3335 return; 3336 3337 if (sc->sc_rescan_timer) { 3338 if (--sc->sc_rescan_timer == 0) 3339 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3340 } 3341 if (sc->sc_tx_timer) { 3342 if (--sc->sc_tx_timer == 0 && 3343 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3344 printf("%s: transmit timeout\n", ifp->if_xname); 3345 ifp->if_oerrors++; 3346 (void)atw_init(ifp); 3347 atw_start(ifp); 3348 } 3349 } 3350 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3351 ifp->if_timer = 1; 3352 ieee80211_watchdog(ic); 3353 } 3354 3355 #ifdef ATW_DEBUG 3356 static void 3357 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3358 { 3359 struct atw_softc *sc = ifp->if_softc; 3360 struct mbuf *m; 3361 int i, noctets = 0; 3362 3363 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3364 m0->m_pkthdr.len); 3365 3366 for (m = m0; m; m = m->m_next) { 3367 if (m->m_len == 0) 3368 continue; 3369 for (i = 0; i < m->m_len; i++) { 3370 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3371 if (++noctets % 24 == 0) 3372 printf("\n"); 3373 } 3374 } 3375 printf("%s%s: %d bytes emitted\n", 3376 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3377 } 3378 #endif /* ATW_DEBUG */ 3379 3380 /* 3381 * atw_start: [ifnet interface function] 3382 * 3383 * Start packet transmission on the interface. 3384 */ 3385 void 3386 atw_start(struct ifnet *ifp) 3387 { 3388 struct atw_softc *sc = ifp->if_softc; 3389 struct ieee80211_key *k; 3390 struct ieee80211com *ic = &sc->sc_ic; 3391 struct ieee80211_node *ni; 3392 struct ieee80211_frame_min *whm; 3393 struct ieee80211_frame *wh; 3394 struct atw_frame *hh; 3395 struct mbuf *m0, *m; 3396 struct atw_txsoft *txs, *last_txs; 3397 struct atw_txdesc *txd; 3398 int do_encrypt, npkt, rate; 3399 bus_dmamap_t dmamap; 3400 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3401 3402 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3403 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3404 3405 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3406 return; 3407 3408 /* 3409 * Remember the previous number of free descriptors and 3410 * the first descriptor we'll use. 3411 */ 3412 ofree = sc->sc_txfree; 3413 firsttx = sc->sc_txnext; 3414 3415 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3416 sc->sc_dev.dv_xname, ofree, firsttx)); 3417 3418 /* 3419 * Loop through the send queue, setting up transmit descriptors 3420 * until we drain the queue, or use up all available transmit 3421 * descriptors. 3422 */ 3423 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3424 sc->sc_txfree != 0) { 3425 3426 /* 3427 * Grab a packet off the management queue, if it 3428 * is not empty. Otherwise, from the data queue. 3429 */ 3430 IF_DEQUEUE(&ic->ic_mgtq, m0); 3431 if (m0 != NULL) { 3432 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3433 m0->m_pkthdr.rcvif = NULL; 3434 } else if (ic->ic_state != IEEE80211_S_RUN) 3435 break; /* send no data until associated */ 3436 else { 3437 IFQ_DEQUEUE(&ifp->if_snd, m0); 3438 if (m0 == NULL) 3439 break; 3440 #if NBPFILTER > 0 3441 if (ifp->if_bpf != NULL) 3442 bpf_mtap(ifp->if_bpf, m0); 3443 #endif /* NBPFILTER > 0 */ 3444 ni = ieee80211_find_txnode(ic, 3445 mtod(m0, struct ether_header *)->ether_dhost); 3446 if (ni == NULL) { 3447 ifp->if_oerrors++; 3448 break; 3449 } 3450 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3451 ieee80211_free_node(ni); 3452 ifp->if_oerrors++; 3453 break; 3454 } 3455 } 3456 3457 rate = MAX(ieee80211_get_rate(ic), 2); 3458 3459 whm = mtod(m0, struct ieee80211_frame_min *); 3460 3461 do_encrypt = ((whm->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3462 if (do_encrypt) 3463 k = &ic->ic_nw_keys[ic->ic_def_txkey]; 3464 else 3465 k = NULL; 3466 3467 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3468 ic->ic_flags, ic->ic_fragthreshold, rate, 3469 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3470 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3471 m_freem(m0); 3472 break; 3473 } 3474 3475 /* XXX Misleading if fragmentation is enabled. Better 3476 * to fragment in software? 3477 */ 3478 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3479 3480 #if NBPFILTER > 0 3481 /* 3482 * Pass the packet to any BPF listeners. 3483 */ 3484 if (ic->ic_rawbpf != NULL) 3485 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3486 3487 if (sc->sc_radiobpf != NULL) { 3488 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3489 3490 tap->at_rate = rate; 3491 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3492 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3493 3494 /* TBD tap->at_flags */ 3495 3496 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3497 tap->at_ihdr.it_len, m0); 3498 } 3499 #endif /* NBPFILTER > 0 */ 3500 3501 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3502 3503 if (ni != NULL) 3504 ieee80211_free_node(ni); 3505 3506 if (m0 == NULL) { 3507 ifp->if_oerrors++; 3508 break; 3509 } 3510 3511 /* just to make sure. */ 3512 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3513 3514 if (m0 == NULL) { 3515 ifp->if_oerrors++; 3516 break; 3517 } 3518 3519 hh = mtod(m0, struct atw_frame *); 3520 wh = &hh->atw_ihdr; 3521 3522 /* Copy everything we need from the 802.11 header: 3523 * Frame Control; address 1, address 3, or addresses 3524 * 3 and 4. NIC fills in BSSID, SA. 3525 */ 3526 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3527 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3528 panic("%s: illegal WDS frame", 3529 sc->sc_dev.dv_xname); 3530 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3531 } else 3532 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3533 3534 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3535 3536 /* initialize remaining Tx parameters */ 3537 memset(&hh->u, 0, sizeof(hh->u)); 3538 3539 hh->atw_rate = rate * 5; 3540 /* XXX this could be incorrect if M_FCS. _encap should 3541 * probably strip FCS just in case it sticks around in 3542 * bridged packets. 3543 */ 3544 hh->atw_service = 0x00; /* XXX guess */ 3545 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3546 sizeof(struct atw_frame)); 3547 3548 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3549 hh->atw_rtylmt = 3; 3550 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3551 if (do_encrypt) { 3552 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3553 hh->atw_keyid = ic->ic_def_txkey; 3554 } 3555 3556 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3557 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3558 if (txs->txs_d0.d_residue) 3559 hh->atw_head_plcplen |= htole16(0x8000); 3560 if (txs->txs_dn.d_residue) 3561 hh->atw_tail_plcplen |= htole16(0x8000); 3562 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3563 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3564 3565 /* never fragment multicast frames */ 3566 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3567 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3568 } else if (sc->sc_flags & ATWF_RTSCTS) { 3569 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3570 } 3571 3572 #ifdef ATW_DEBUG 3573 hh->atw_fragnum = 0; 3574 3575 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3576 printf("%s: dst = %s, rate = 0x%02x, " 3577 "service = 0x%02x, paylen = 0x%04x\n", 3578 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3579 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3580 3581 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3582 "dur1 = 0x%04x, dur2 = 0x%04x, " 3583 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3584 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3585 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3586 hh->atw_tail_dur, hh->atw_head_dur); 3587 3588 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3589 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3590 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3591 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3592 3593 printf("%s: keyid = %d\n", 3594 sc->sc_dev.dv_xname, hh->atw_keyid); 3595 3596 atw_dump_pkt(ifp, m0); 3597 } 3598 #endif /* ATW_DEBUG */ 3599 3600 dmamap = txs->txs_dmamap; 3601 3602 /* 3603 * Load the DMA map. Copy and try (once) again if the packet 3604 * didn't fit in the alloted number of segments. 3605 */ 3606 for (first = 1; 3607 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3608 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3609 first = 0) { 3610 MGETHDR(m, M_DONTWAIT, MT_DATA); 3611 if (m == NULL) { 3612 printf("%s: unable to allocate Tx mbuf\n", 3613 sc->sc_dev.dv_xname); 3614 break; 3615 } 3616 if (m0->m_pkthdr.len > MHLEN) { 3617 MCLGET(m, M_DONTWAIT); 3618 if ((m->m_flags & M_EXT) == 0) { 3619 printf("%s: unable to allocate Tx " 3620 "cluster\n", sc->sc_dev.dv_xname); 3621 m_freem(m); 3622 break; 3623 } 3624 } 3625 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3626 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3627 m_freem(m0); 3628 m0 = m; 3629 m = NULL; 3630 } 3631 if (error != 0) { 3632 printf("%s: unable to load Tx buffer, " 3633 "error = %d\n", sc->sc_dev.dv_xname, error); 3634 m_freem(m0); 3635 break; 3636 } 3637 3638 /* 3639 * Ensure we have enough descriptors free to describe 3640 * the packet. 3641 */ 3642 if (dmamap->dm_nsegs > sc->sc_txfree) { 3643 /* 3644 * Not enough free descriptors to transmit 3645 * this packet. Unload the DMA map and 3646 * drop the packet. Notify the upper layer 3647 * that there are no more slots left. 3648 * 3649 * XXX We could allocate an mbuf and copy, but 3650 * XXX it is worth it? 3651 */ 3652 bus_dmamap_unload(sc->sc_dmat, dmamap); 3653 m_freem(m0); 3654 break; 3655 } 3656 3657 /* 3658 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3659 */ 3660 3661 /* Sync the DMA map. */ 3662 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3663 BUS_DMASYNC_PREWRITE); 3664 3665 /* XXX arbitrary retry limit; 8 because I have seen it in 3666 * use already and maybe 0 means "no tries" ! 3667 */ 3668 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3669 3670 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3671 sc->sc_dev.dv_xname, rate * 5)); 3672 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3673 3674 /* 3675 * Initialize the transmit descriptors. 3676 */ 3677 for (nexttx = sc->sc_txnext, seg = 0; 3678 seg < dmamap->dm_nsegs; 3679 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3680 /* 3681 * If this is the first descriptor we're 3682 * enqueueing, don't set the OWN bit just 3683 * yet. That could cause a race condition. 3684 * We'll do it below. 3685 */ 3686 txd = &sc->sc_txdescs[nexttx]; 3687 txd->at_ctl = ctl | 3688 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3689 3690 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3691 txd->at_flags = 3692 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3693 ATW_TXFLAG_TBS1_MASK)) | 3694 ((nexttx == (ATW_NTXDESC - 1)) 3695 ? htole32(ATW_TXFLAG_TER) : 0); 3696 lasttx = nexttx; 3697 } 3698 3699 IASSERT(lasttx != -1, ("bad lastx")); 3700 /* Set `first segment' and `last segment' appropriately. */ 3701 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3702 htole32(ATW_TXFLAG_FS); 3703 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3704 3705 #ifdef ATW_DEBUG 3706 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3707 printf(" txsoft %p transmit chain:\n", txs); 3708 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3709 printf(" descriptor %d:\n", seg); 3710 printf(" at_ctl: 0x%08x\n", 3711 le32toh(sc->sc_txdescs[seg].at_ctl)); 3712 printf(" at_flags: 0x%08x\n", 3713 le32toh(sc->sc_txdescs[seg].at_flags)); 3714 printf(" at_buf1: 0x%08x\n", 3715 le32toh(sc->sc_txdescs[seg].at_buf1)); 3716 printf(" at_buf2: 0x%08x\n", 3717 le32toh(sc->sc_txdescs[seg].at_buf2)); 3718 if (seg == lasttx) 3719 break; 3720 } 3721 } 3722 #endif 3723 3724 /* Sync the descriptors we're using. */ 3725 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3726 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3727 3728 /* 3729 * Store a pointer to the packet so we can free it later, 3730 * and remember what txdirty will be once the packet is 3731 * done. 3732 */ 3733 txs->txs_mbuf = m0; 3734 txs->txs_firstdesc = sc->sc_txnext; 3735 txs->txs_lastdesc = lasttx; 3736 txs->txs_ndescs = dmamap->dm_nsegs; 3737 3738 /* Advance the tx pointer. */ 3739 sc->sc_txfree -= dmamap->dm_nsegs; 3740 sc->sc_txnext = nexttx; 3741 3742 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3743 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3744 3745 last_txs = txs; 3746 } 3747 3748 if (sc->sc_txfree != ofree) { 3749 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3750 sc->sc_dev.dv_xname, lasttx, firsttx)); 3751 /* 3752 * Cause a transmit interrupt to happen on the 3753 * last packet we enqueued. 3754 */ 3755 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3756 ATW_CDTXSYNC(sc, lasttx, 1, 3757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3758 3759 /* 3760 * The entire packet chain is set up. Give the 3761 * first descriptor to the chip now. 3762 */ 3763 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3764 ATW_CDTXSYNC(sc, firsttx, 1, 3765 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3766 3767 /* Wake up the transmitter. */ 3768 ATW_WRITE(sc, ATW_TDR, 0x1); 3769 3770 if (txs == NULL || sc->sc_txfree == 0) 3771 ifp->if_flags |= IFF_OACTIVE; 3772 3773 /* Set a watchdog timer in case the chip flakes out. */ 3774 sc->sc_tx_timer = 5; 3775 ifp->if_timer = 1; 3776 } 3777 } 3778 3779 /* 3780 * atw_power: 3781 * 3782 * Power management (suspend/resume) hook. 3783 */ 3784 void 3785 atw_power(int why, void *arg) 3786 { 3787 struct atw_softc *sc = arg; 3788 struct ifnet *ifp = &sc->sc_if; 3789 int s; 3790 3791 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3792 3793 s = splnet(); 3794 switch (why) { 3795 case PWR_STANDBY: 3796 /* XXX do nothing. */ 3797 break; 3798 case PWR_SUSPEND: 3799 atw_stop(ifp, 0); 3800 if (sc->sc_power != NULL) 3801 (*sc->sc_power)(sc, why); 3802 break; 3803 case PWR_RESUME: 3804 if (ifp->if_flags & IFF_UP) { 3805 if (sc->sc_power != NULL) 3806 (*sc->sc_power)(sc, why); 3807 atw_init(ifp); 3808 } 3809 break; 3810 case PWR_SOFTSUSPEND: 3811 case PWR_SOFTSTANDBY: 3812 case PWR_SOFTRESUME: 3813 break; 3814 } 3815 splx(s); 3816 } 3817 3818 /* 3819 * atw_ioctl: [ifnet interface function] 3820 * 3821 * Handle control requests from the operator. 3822 */ 3823 int 3824 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3825 { 3826 struct atw_softc *sc = ifp->if_softc; 3827 struct ifreq *ifr = (struct ifreq *)data; 3828 int s, error = 0; 3829 3830 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3831 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3832 return ENXIO; 3833 3834 s = splnet(); 3835 3836 switch (cmd) { 3837 case SIOCSIFFLAGS: 3838 if (ifp->if_flags & IFF_UP) { 3839 if (ATW_IS_ENABLED(sc)) { 3840 /* 3841 * To avoid rescanning another access point, 3842 * do not call atw_init() here. Instead, 3843 * only reflect media settings. 3844 */ 3845 atw_filter_setup(sc); 3846 } else 3847 error = atw_init(ifp); 3848 } else if (ATW_IS_ENABLED(sc)) 3849 atw_stop(ifp, 1); 3850 break; 3851 case SIOCADDMULTI: 3852 case SIOCDELMULTI: 3853 error = (cmd == SIOCADDMULTI) ? 3854 ether_addmulti(ifr, &sc->sc_ec) : 3855 ether_delmulti(ifr, &sc->sc_ec); 3856 if (error == ENETRESET) { 3857 if (ifp->if_flags & IFF_RUNNING) 3858 atw_filter_setup(sc); /* do not rescan */ 3859 error = 0; 3860 } 3861 break; 3862 default: 3863 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3864 if (error == ENETRESET) { 3865 if (ATW_IS_ENABLED(sc)) 3866 error = atw_init(ifp); 3867 else 3868 error = 0; 3869 } 3870 break; 3871 } 3872 3873 /* Try to get more packets going. */ 3874 if (ATW_IS_ENABLED(sc)) 3875 atw_start(ifp); 3876 3877 splx(s); 3878 return (error); 3879 } 3880 3881 static int 3882 atw_media_change(struct ifnet *ifp) 3883 { 3884 int error; 3885 3886 error = ieee80211_media_change(ifp); 3887 if (error == ENETRESET) { 3888 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3889 (IFF_RUNNING|IFF_UP)) 3890 atw_init(ifp); /* XXX lose error */ 3891 error = 0; 3892 } 3893 return error; 3894 } 3895
Indexes created Mon Sep 22 21:09:42 GMT 2025