atw.c revision 1.104
1 /* $NetBSD: atw.c,v 1.104 2005/12/29 22:04:21 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.104 2005/12/29 22:04:21 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 266 static void atw_filter_setup(struct atw_softc *); 267 268 /* 802.11 utilities */ 269 static uint64_t atw_get_tsft(struct atw_softc *); 270 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 271 uint32_t); 272 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 273 static void atw_node_free(struct ieee80211_node *); 274 static void atw_change_ibss(struct atw_softc *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(struct device *self, enum devact act) 323 { 324 struct atw_softc *sc = (struct atw_softc *)self; 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 printf("%s: device enable failed\n", 353 sc->sc_dev.dv_xname); 354 return (EIO); 355 } 356 sc->sc_flags |= ATWF_ENABLED; 357 } 358 return (0); 359 } 360 361 /* 362 * atw_disable: 363 * 364 * Disable the ADM8211 chip. 365 */ 366 void 367 atw_disable(struct atw_softc *sc) 368 { 369 if (!ATW_IS_ENABLED(sc)) 370 return; 371 if (sc->sc_disable != NULL) 372 (*sc->sc_disable)(sc); 373 sc->sc_flags &= ~ATWF_ENABLED; 374 } 375 376 /* Returns -1 on failure. */ 377 static int 378 atw_read_srom(struct atw_softc *sc) 379 { 380 struct seeprom_descriptor sd; 381 uint32_t test0, fail_bits; 382 383 (void)memset(&sd, 0, sizeof(sd)); 384 385 test0 = ATW_READ(sc, ATW_TEST0); 386 387 switch (sc->sc_rev) { 388 case ATW_REVISION_BA: 389 case ATW_REVISION_CA: 390 fail_bits = ATW_TEST0_EPNE; 391 break; 392 default: 393 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 394 break; 395 } 396 if ((test0 & fail_bits) != 0) { 397 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 398 return -1; 399 } 400 401 switch (test0 & ATW_TEST0_EPTYP_MASK) { 402 case ATW_TEST0_EPTYP_93c66: 403 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 404 sc->sc_sromsz = 512; 405 sd.sd_chip = C56_66; 406 break; 407 case ATW_TEST0_EPTYP_93c46: 408 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 409 sc->sc_sromsz = 128; 410 sd.sd_chip = C46; 411 break; 412 default: 413 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 414 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 415 return -1; 416 } 417 418 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 419 420 if (sc->sc_srom == NULL) { 421 printf("%s: unable to allocate SROM buffer\n", 422 sc->sc_dev.dv_xname); 423 return -1; 424 } 425 426 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 427 428 /* ADM8211 has a single 32-bit register for controlling the 429 * 93cx6 SROM. Bit SRS enables the serial port. There is no 430 * "ready" bit. The ADM8211 input/output sense is the reverse 431 * of read_seeprom's. 432 */ 433 sd.sd_tag = sc->sc_st; 434 sd.sd_bsh = sc->sc_sh; 435 sd.sd_regsize = 4; 436 sd.sd_control_offset = ATW_SPR; 437 sd.sd_status_offset = ATW_SPR; 438 sd.sd_dataout_offset = ATW_SPR; 439 sd.sd_CK = ATW_SPR_SCLK; 440 sd.sd_CS = ATW_SPR_SCS; 441 sd.sd_DI = ATW_SPR_SDO; 442 sd.sd_DO = ATW_SPR_SDI; 443 sd.sd_MS = ATW_SPR_SRS; 444 sd.sd_RDY = 0; 445 446 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 447 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 448 free(sc->sc_srom, M_DEVBUF); 449 return -1; 450 } 451 #ifdef ATW_DEBUG 452 { 453 int i; 454 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 455 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 456 if (((i % 8) == 0) && (i != 0)) { 457 ATW_DPRINTF(("\n\t")); 458 } 459 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 460 } 461 ATW_DPRINTF(("\n")); 462 } 463 #endif /* ATW_DEBUG */ 464 return 0; 465 } 466 467 #ifdef ATW_DEBUG 468 static void 469 atw_print_regs(struct atw_softc *sc, const char *where) 470 { 471 #define PRINTREG(sc, reg) \ 472 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 473 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 474 475 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 476 477 PRINTREG(sc, ATW_PAR); 478 PRINTREG(sc, ATW_FRCTL); 479 PRINTREG(sc, ATW_TDR); 480 PRINTREG(sc, ATW_WTDP); 481 PRINTREG(sc, ATW_RDR); 482 PRINTREG(sc, ATW_WRDP); 483 PRINTREG(sc, ATW_RDB); 484 PRINTREG(sc, ATW_CSR3A); 485 PRINTREG(sc, ATW_TDBD); 486 PRINTREG(sc, ATW_TDBP); 487 PRINTREG(sc, ATW_STSR); 488 PRINTREG(sc, ATW_CSR5A); 489 PRINTREG(sc, ATW_NAR); 490 PRINTREG(sc, ATW_CSR6A); 491 PRINTREG(sc, ATW_IER); 492 PRINTREG(sc, ATW_CSR7A); 493 PRINTREG(sc, ATW_LPC); 494 PRINTREG(sc, ATW_TEST1); 495 PRINTREG(sc, ATW_SPR); 496 PRINTREG(sc, ATW_TEST0); 497 PRINTREG(sc, ATW_WCSR); 498 PRINTREG(sc, ATW_WPDR); 499 PRINTREG(sc, ATW_GPTMR); 500 PRINTREG(sc, ATW_GPIO); 501 PRINTREG(sc, ATW_BBPCTL); 502 PRINTREG(sc, ATW_SYNCTL); 503 PRINTREG(sc, ATW_PLCPHD); 504 PRINTREG(sc, ATW_MMIWADDR); 505 PRINTREG(sc, ATW_MMIRADDR1); 506 PRINTREG(sc, ATW_MMIRADDR2); 507 PRINTREG(sc, ATW_TXBR); 508 PRINTREG(sc, ATW_CSR15A); 509 PRINTREG(sc, ATW_ALCSTAT); 510 PRINTREG(sc, ATW_TOFS2); 511 PRINTREG(sc, ATW_CMDR); 512 PRINTREG(sc, ATW_PCIC); 513 PRINTREG(sc, ATW_PMCSR); 514 PRINTREG(sc, ATW_PAR0); 515 PRINTREG(sc, ATW_PAR1); 516 PRINTREG(sc, ATW_MAR0); 517 PRINTREG(sc, ATW_MAR1); 518 PRINTREG(sc, ATW_ATIMDA0); 519 PRINTREG(sc, ATW_ABDA1); 520 PRINTREG(sc, ATW_BSSID0); 521 PRINTREG(sc, ATW_TXLMT); 522 PRINTREG(sc, ATW_MIBCNT); 523 PRINTREG(sc, ATW_BCNT); 524 PRINTREG(sc, ATW_TSFTH); 525 PRINTREG(sc, ATW_TSC); 526 PRINTREG(sc, ATW_SYNRF); 527 PRINTREG(sc, ATW_BPLI); 528 PRINTREG(sc, ATW_CAP0); 529 PRINTREG(sc, ATW_CAP1); 530 PRINTREG(sc, ATW_RMD); 531 PRINTREG(sc, ATW_CFPP); 532 PRINTREG(sc, ATW_TOFS0); 533 PRINTREG(sc, ATW_TOFS1); 534 PRINTREG(sc, ATW_IFST); 535 PRINTREG(sc, ATW_RSPT); 536 PRINTREG(sc, ATW_TSFTL); 537 PRINTREG(sc, ATW_WEPCTL); 538 PRINTREG(sc, ATW_WESK); 539 PRINTREG(sc, ATW_WEPCNT); 540 PRINTREG(sc, ATW_MACTEST); 541 PRINTREG(sc, ATW_FER); 542 PRINTREG(sc, ATW_FEMR); 543 PRINTREG(sc, ATW_FPSR); 544 PRINTREG(sc, ATW_FFER); 545 #undef PRINTREG 546 } 547 #endif /* ATW_DEBUG */ 548 549 /* 550 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 551 */ 552 void 553 atw_attach(struct atw_softc *sc) 554 { 555 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 557 }; 558 struct ieee80211com *ic = &sc->sc_ic; 559 struct ifnet *ifp = &sc->sc_if; 560 int country_code, error, i, nrate, srom_major; 561 u_int32_t reg; 562 static const char *type_strings[] = {"Intersil (not supported)", 563 "RFMD", "Marvel (not supported)"}; 564 565 sc->sc_txth = atw_txthresh_tab_lo; 566 567 SIMPLEQ_INIT(&sc->sc_txfreeq); 568 SIMPLEQ_INIT(&sc->sc_txdirtyq); 569 570 #ifdef ATW_DEBUG 571 atw_print_regs(sc, "atw_attach"); 572 #endif /* ATW_DEBUG */ 573 574 /* 575 * Allocate the control data structures, and create and load the 576 * DMA map for it. 577 */ 578 if ((error = bus_dmamem_alloc(sc->sc_dmat, 579 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 580 1, &sc->sc_cdnseg, 0)) != 0) { 581 printf("%s: unable to allocate control data, error = %d\n", 582 sc->sc_dev.dv_xname, error); 583 goto fail_0; 584 } 585 586 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 587 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 588 BUS_DMA_COHERENT)) != 0) { 589 printf("%s: unable to map control data, error = %d\n", 590 sc->sc_dev.dv_xname, error); 591 goto fail_1; 592 } 593 594 if ((error = bus_dmamap_create(sc->sc_dmat, 595 sizeof(struct atw_control_data), 1, 596 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 597 printf("%s: unable to create control data DMA map, " 598 "error = %d\n", sc->sc_dev.dv_xname, error); 599 goto fail_2; 600 } 601 602 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 603 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 604 0)) != 0) { 605 printf("%s: unable to load control data DMA map, error = %d\n", 606 sc->sc_dev.dv_xname, error); 607 goto fail_3; 608 } 609 610 /* 611 * Create the transmit buffer DMA maps. 612 */ 613 sc->sc_ntxsegs = ATW_NTXSEGS; 614 for (i = 0; i < ATW_TXQUEUELEN; i++) { 615 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 616 sc->sc_ntxsegs, MCLBYTES, 0, 0, 617 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 618 printf("%s: unable to create tx DMA map %d, " 619 "error = %d\n", sc->sc_dev.dv_xname, i, error); 620 goto fail_4; 621 } 622 } 623 624 /* 625 * Create the receive buffer DMA maps. 626 */ 627 for (i = 0; i < ATW_NRXDESC; i++) { 628 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 629 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 630 printf("%s: unable to create rx DMA map %d, " 631 "error = %d\n", sc->sc_dev.dv_xname, i, error); 632 goto fail_5; 633 } 634 } 635 for (i = 0; i < ATW_NRXDESC; i++) { 636 sc->sc_rxsoft[i].rxs_mbuf = NULL; 637 } 638 639 switch (sc->sc_rev) { 640 case ATW_REVISION_AB: 641 case ATW_REVISION_AF: 642 sc->sc_sramlen = ATW_SRAM_A_SIZE; 643 break; 644 case ATW_REVISION_BA: 645 case ATW_REVISION_CA: 646 sc->sc_sramlen = ATW_SRAM_B_SIZE; 647 break; 648 } 649 650 /* Reset the chip to a known state. */ 651 atw_reset(sc); 652 653 if (atw_read_srom(sc) == -1) 654 return; 655 656 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 657 ATW_SR_RFTYPE_MASK); 658 659 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 660 ATW_SR_BBPTYPE_MASK); 661 662 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 663 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 664 return; 665 } 666 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 667 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 668 return; 669 } 670 671 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 672 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 673 674 /* XXX There exists a Linux driver which seems to use RFType = 0 for 675 * MARVEL. My bug, or theirs? 676 */ 677 678 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 679 680 switch (sc->sc_rftype) { 681 case ATW_RFTYPE_INTERSIL: 682 reg |= ATW_SYNCTL_CS1; 683 break; 684 case ATW_RFTYPE_RFMD: 685 reg |= ATW_SYNCTL_CS0; 686 break; 687 case ATW_RFTYPE_MARVEL: 688 break; 689 } 690 691 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 692 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 693 694 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 695 696 switch (sc->sc_bbptype) { 697 case ATW_BBPTYPE_INTERSIL: 698 reg |= ATW_BBPCTL_TWI; 699 break; 700 case ATW_BBPTYPE_RFMD: 701 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 702 ATW_BBPCTL_CCA_ACTLO; 703 break; 704 case ATW_BBPTYPE_MARVEL: 705 break; 706 case ATW_C_BBPTYPE_RFMD: 707 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 708 sc->sc_dev.dv_xname); 709 break; 710 } 711 712 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 713 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 714 715 /* 716 * From this point forward, the attachment cannot fail. A failure 717 * before this point releases all resources that may have been 718 * allocated. 719 */ 720 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 721 722 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 723 htole16(sc->sc_srom[ATW_SR_MAC00]), 724 htole16(sc->sc_srom[ATW_SR_MAC01]), 725 htole16(sc->sc_srom[ATW_SR_MAC10]))); 726 727 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 728 ATW_SR_MAJOR_MASK); 729 730 if (srom_major < 2) 731 sc->sc_rf3000_options1 = 0; 732 else if (sc->sc_rev == ATW_REVISION_BA) { 733 sc->sc_rf3000_options1 = 734 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 735 ATW_SR_CR28_MASK); 736 } else 737 sc->sc_rf3000_options1 = 0; 738 739 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 740 ATW_SR_CR29_MASK); 741 742 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 743 ATW_SR_CTRY_MASK); 744 745 #define ADD_CHANNEL(_ic, _chan) do { \ 746 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 747 _ic->ic_channels[_chan].ic_freq = \ 748 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 749 } while (0) 750 751 /* Find available channels */ 752 switch (country_code) { 753 case COUNTRY_MMK2: /* 1-14 */ 754 ADD_CHANNEL(ic, 14); 755 /*FALLTHROUGH*/ 756 case COUNTRY_ETSI: /* 1-13 */ 757 for (i = 1; i <= 13; i++) 758 ADD_CHANNEL(ic, i); 759 break; 760 case COUNTRY_FCC: /* 1-11 */ 761 case COUNTRY_IC: /* 1-11 */ 762 for (i = 1; i <= 11; i++) 763 ADD_CHANNEL(ic, i); 764 break; 765 case COUNTRY_MMK: /* 14 */ 766 ADD_CHANNEL(ic, 14); 767 break; 768 case COUNTRY_FRANCE: /* 10-13 */ 769 for (i = 10; i <= 13; i++) 770 ADD_CHANNEL(ic, i); 771 break; 772 default: /* assume channels 10-11 */ 773 case COUNTRY_SPAIN: /* 10-11 */ 774 for (i = 10; i <= 11; i++) 775 ADD_CHANNEL(ic, i); 776 break; 777 } 778 779 /* Read the MAC address. */ 780 reg = ATW_READ(sc, ATW_PAR0); 781 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 782 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 783 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 784 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 785 reg = ATW_READ(sc, ATW_PAR1); 786 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 787 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 788 789 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 790 printf(" could not get mac address, attach failed\n"); 791 return; 792 } 793 794 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 795 796 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 797 ifp->if_softc = sc; 798 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 799 IFF_NOTRAILERS; 800 ifp->if_ioctl = atw_ioctl; 801 ifp->if_start = atw_start; 802 ifp->if_watchdog = atw_watchdog; 803 ifp->if_init = atw_init; 804 ifp->if_stop = atw_stop; 805 IFQ_SET_READY(&ifp->if_snd); 806 807 ic->ic_ifp = ifp; 808 ic->ic_phytype = IEEE80211_T_DS; 809 ic->ic_opmode = IEEE80211_M_STA; 810 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 811 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 812 813 nrate = 0; 814 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 815 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 816 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 817 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 819 820 /* 821 * Call MI attach routines. 822 */ 823 824 if_attach(ifp); 825 ieee80211_ifattach(ic); 826 827 sc->sc_newstate = ic->ic_newstate; 828 ic->ic_newstate = atw_newstate; 829 830 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 831 ic->ic_recv_mgmt = atw_recv_mgmt; 832 833 sc->sc_node_free = ic->ic_node_free; 834 ic->ic_node_free = atw_node_free; 835 836 sc->sc_node_alloc = ic->ic_node_alloc; 837 ic->ic_node_alloc = atw_node_alloc; 838 839 ic->ic_crypto.cs_key_delete = atw_key_delete; 840 ic->ic_crypto.cs_key_set = atw_key_set; 841 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 842 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 843 844 /* possibly we should fill in our own sc_send_prresp, since 845 * the ADM8211 is probably sending probe responses in ad hoc 846 * mode. 847 */ 848 849 /* complete initialization */ 850 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 851 callout_init(&sc->sc_scan_ch); 852 853 #if NBPFILTER > 0 854 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 855 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 856 #endif 857 858 /* 859 * Make sure the interface is shutdown during reboot. 860 */ 861 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 862 if (sc->sc_sdhook == NULL) 863 printf("%s: WARNING: unable to establish shutdown hook\n", 864 sc->sc_dev.dv_xname); 865 866 /* 867 * Add a suspend hook to make sure we come back up after a 868 * resume. 869 */ 870 sc->sc_powerhook = powerhook_establish(atw_power, sc); 871 if (sc->sc_powerhook == NULL) 872 printf("%s: WARNING: unable to establish power hook\n", 873 sc->sc_dev.dv_xname); 874 875 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 876 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 877 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 878 879 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 880 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 881 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 882 883 ieee80211_announce(ic); 884 return; 885 886 /* 887 * Free any resources we've allocated during the failed attach 888 * attempt. Do this in reverse order and fall through. 889 */ 890 fail_5: 891 for (i = 0; i < ATW_NRXDESC; i++) { 892 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 893 continue; 894 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 895 } 896 fail_4: 897 for (i = 0; i < ATW_TXQUEUELEN; i++) { 898 if (sc->sc_txsoft[i].txs_dmamap == NULL) 899 continue; 900 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 901 } 902 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 903 fail_3: 904 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 905 fail_2: 906 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 907 sizeof(struct atw_control_data)); 908 fail_1: 909 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 910 fail_0: 911 return; 912 } 913 914 static struct ieee80211_node * 915 atw_node_alloc(struct ieee80211_node_table *nt) 916 { 917 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 918 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 919 920 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 921 return ni; 922 } 923 924 static void 925 atw_node_free(struct ieee80211_node *ni) 926 { 927 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 928 929 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 930 ether_sprintf(ni->ni_bssid))); 931 (*sc->sc_node_free)(ni); 932 } 933 934 935 static void 936 atw_test1_reset(struct atw_softc *sc) 937 { 938 switch (sc->sc_rev) { 939 case ATW_REVISION_BA: 940 if (1 /* XXX condition on transceiver type */) { 941 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 942 } 943 break; 944 case ATW_REVISION_CA: 945 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 946 break; 947 default: 948 break; 949 } 950 } 951 952 /* 953 * atw_reset: 954 * 955 * Perform a soft reset on the ADM8211. 956 */ 957 void 958 atw_reset(struct atw_softc *sc) 959 { 960 int i; 961 uint32_t lpc; 962 963 ATW_WRITE(sc, ATW_NAR, 0x0); 964 DELAY(atw_nar_delay); 965 966 /* Reference driver has a cryptic remark indicating that this might 967 * power-on the chip. I know that it turns off power-saving.... 968 */ 969 ATW_WRITE(sc, ATW_FRCTL, 0x0); 970 971 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 972 973 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 974 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 975 break; 976 DELAY(atw_pseudo_milli); 977 } 978 979 /* ... and then pause 100ms longer for good measure. */ 980 DELAY(atw_magic_delay1); 981 982 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 983 984 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 985 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 986 987 /* 988 * Initialize the PCI Access Register. 989 */ 990 sc->sc_busmode = ATW_PAR_PBL_8DW; 991 992 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 993 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 994 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 995 996 atw_test1_reset(sc); 997 998 /* Turn off maximum power saving, etc. */ 999 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1000 1001 DELAY(atw_magic_delay2); 1002 1003 /* Recall EEPROM. */ 1004 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1005 1006 DELAY(atw_magic_delay4); 1007 1008 lpc = ATW_READ(sc, ATW_LPC); 1009 1010 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1011 1012 /* A reset seems to affect the SRAM contents, so put them into 1013 * a known state. 1014 */ 1015 atw_clear_sram(sc); 1016 1017 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1018 } 1019 1020 static void 1021 atw_clear_sram(struct atw_softc *sc) 1022 { 1023 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1024 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1025 /* XXX not for revision 0x20. */ 1026 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1027 } 1028 1029 /* TBD atw_init 1030 * 1031 * set MAC based on ic->ic_bss->myaddr 1032 * write WEP keys 1033 * set TX rate 1034 */ 1035 1036 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1037 * without receiving a beacon with the preferred BSSID & SSID. 1038 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1039 */ 1040 static void 1041 atw_wcsr_init(struct atw_softc *sc) 1042 { 1043 uint32_t wcsr; 1044 1045 wcsr = ATW_READ(sc, ATW_WCSR); 1046 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1047 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1048 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1049 1050 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1051 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1052 } 1053 1054 /* Turn off power management. Set Rx store-and-forward mode. */ 1055 static void 1056 atw_cmdr_init(struct atw_softc *sc) 1057 { 1058 uint32_t cmdr; 1059 cmdr = ATW_READ(sc, ATW_CMDR); 1060 cmdr &= ~ATW_CMDR_APM; 1061 cmdr |= ATW_CMDR_RTE; 1062 cmdr &= ~ATW_CMDR_DRT_MASK; 1063 cmdr |= ATW_CMDR_DRT_SF; 1064 1065 ATW_WRITE(sc, ATW_CMDR, cmdr); 1066 } 1067 1068 static void 1069 atw_tofs2_init(struct atw_softc *sc) 1070 { 1071 uint32_t tofs2; 1072 /* XXX this magic can probably be figured out from the RFMD docs */ 1073 #ifndef ATW_REFSLAVE 1074 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1075 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1076 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1077 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1078 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1079 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1080 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1081 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1082 #else 1083 /* XXX new magic from reference driver source */ 1084 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1085 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1086 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1087 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1088 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1089 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1090 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1091 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1092 #endif 1093 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1094 } 1095 1096 static void 1097 atw_nar_init(struct atw_softc *sc) 1098 { 1099 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1100 } 1101 1102 static void 1103 atw_txlmt_init(struct atw_softc *sc) 1104 { 1105 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1106 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1107 } 1108 1109 static void 1110 atw_test1_init(struct atw_softc *sc) 1111 { 1112 uint32_t test1; 1113 1114 test1 = ATW_READ(sc, ATW_TEST1); 1115 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1116 /* XXX magic 0x1 */ 1117 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1118 ATW_WRITE(sc, ATW_TEST1, test1); 1119 } 1120 1121 static void 1122 atw_rf_reset(struct atw_softc *sc) 1123 { 1124 /* XXX this resets an Intersil RF front-end? */ 1125 /* TBD condition on Intersil RFType? */ 1126 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1127 DELAY(atw_rf_delay1); 1128 ATW_WRITE(sc, ATW_SYNRF, 0); 1129 DELAY(atw_rf_delay2); 1130 } 1131 1132 /* Set 16 TU max duration for the contention-free period (CFP). */ 1133 static void 1134 atw_cfp_init(struct atw_softc *sc) 1135 { 1136 uint32_t cfpp; 1137 1138 cfpp = ATW_READ(sc, ATW_CFPP); 1139 cfpp &= ~ATW_CFPP_CFPMD; 1140 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1141 ATW_WRITE(sc, ATW_CFPP, cfpp); 1142 } 1143 1144 static void 1145 atw_tofs0_init(struct atw_softc *sc) 1146 { 1147 /* XXX I guess that the Cardbus clock is 22MHz? 1148 * I am assuming that the role of ATW_TOFS0_USCNT is 1149 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1150 * very clear on this point. It says in the datasheet that it is 1151 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1152 * and 33MHz; maybe this is the way? I see a binary-only driver write 1153 * these values. These values are also the power-on default. 1154 */ 1155 ATW_WRITE(sc, ATW_TOFS0, 1156 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1157 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1158 } 1159 1160 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1161 static void 1162 atw_ifs_init(struct atw_softc *sc) 1163 { 1164 uint32_t ifst; 1165 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1166 * Go figure. 1167 */ 1168 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1169 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1170 ATW_IFST_SIFS_MASK) | 1171 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1172 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1173 1174 ATW_WRITE(sc, ATW_IFST, ifst); 1175 } 1176 1177 static void 1178 atw_response_times_init(struct atw_softc *sc) 1179 { 1180 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1181 * indicate that the MAC expects at least SIFS + MIRT microseconds 1182 * to pass after it transmits a frame that requires a response; 1183 * it waits at most SIFS + MART microseconds for the response. 1184 * Surely this is not the ACK timeout? 1185 */ 1186 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1187 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1188 } 1189 1190 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1191 * engines read and write baseband registers after Rx and before 1192 * Tx, respectively. 1193 */ 1194 static void 1195 atw_bbp_io_init(struct atw_softc *sc) 1196 { 1197 uint32_t mmiraddr2; 1198 1199 /* XXX The reference driver does this, but is it *really* 1200 * necessary? 1201 */ 1202 switch (sc->sc_rev) { 1203 case ATW_REVISION_AB: 1204 case ATW_REVISION_AF: 1205 mmiraddr2 = 0x0; 1206 break; 1207 default: 1208 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1209 mmiraddr2 &= 1210 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1211 break; 1212 } 1213 1214 switch (sc->sc_bbptype) { 1215 case ATW_BBPTYPE_INTERSIL: 1216 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1217 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1218 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1219 break; 1220 case ATW_BBPTYPE_MARVEL: 1221 /* TBD find out the Marvel settings. */ 1222 break; 1223 case ATW_BBPTYPE_RFMD: 1224 default: 1225 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1226 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1227 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1228 break; 1229 } 1230 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1231 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1232 } 1233 1234 /* 1235 * atw_init: [ ifnet interface function ] 1236 * 1237 * Initialize the interface. Must be called at splnet(). 1238 */ 1239 int 1240 atw_init(struct ifnet *ifp) 1241 { 1242 struct atw_softc *sc = ifp->if_softc; 1243 struct ieee80211com *ic = &sc->sc_ic; 1244 struct atw_txsoft *txs; 1245 struct atw_rxsoft *rxs; 1246 int i, error = 0; 1247 1248 if ((error = atw_enable(sc)) != 0) 1249 goto out; 1250 1251 /* 1252 * Cancel any pending I/O. This also resets. 1253 */ 1254 atw_stop(ifp, 0); 1255 1256 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1257 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1258 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1259 1260 atw_wcsr_init(sc); 1261 1262 atw_cmdr_init(sc); 1263 1264 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1265 * 1266 * XXX Set transmit power for ATIM, RTS, Beacon. 1267 */ 1268 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1269 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1270 1271 atw_tofs2_init(sc); 1272 1273 atw_nar_init(sc); 1274 1275 atw_txlmt_init(sc); 1276 1277 atw_test1_init(sc); 1278 1279 atw_rf_reset(sc); 1280 1281 atw_cfp_init(sc); 1282 1283 atw_tofs0_init(sc); 1284 1285 atw_ifs_init(sc); 1286 1287 /* XXX Fall asleep after one second of inactivity. 1288 * XXX A frame may only dribble in for 65536us. 1289 */ 1290 ATW_WRITE(sc, ATW_RMD, 1291 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1292 1293 atw_response_times_init(sc); 1294 1295 atw_bbp_io_init(sc); 1296 1297 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1298 1299 if ((error = atw_rf3000_init(sc)) != 0) 1300 goto out; 1301 1302 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1303 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1304 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1305 1306 /* 1307 * Initialize the transmit descriptor ring. 1308 */ 1309 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1310 for (i = 0; i < ATW_NTXDESC; i++) { 1311 sc->sc_txdescs[i].at_ctl = 0; 1312 /* no transmit chaining */ 1313 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1314 sc->sc_txdescs[i].at_buf2 = 1315 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1316 } 1317 /* use ring mode */ 1318 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1319 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1320 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1321 sc->sc_txfree = ATW_NTXDESC; 1322 sc->sc_txnext = 0; 1323 1324 /* 1325 * Initialize the transmit job descriptors. 1326 */ 1327 SIMPLEQ_INIT(&sc->sc_txfreeq); 1328 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1329 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1330 txs = &sc->sc_txsoft[i]; 1331 txs->txs_mbuf = NULL; 1332 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1333 } 1334 1335 /* 1336 * Initialize the receive descriptor and receive job 1337 * descriptor rings. 1338 */ 1339 for (i = 0; i < ATW_NRXDESC; i++) { 1340 rxs = &sc->sc_rxsoft[i]; 1341 if (rxs->rxs_mbuf == NULL) { 1342 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1343 printf("%s: unable to allocate or map rx " 1344 "buffer %d, error = %d\n", 1345 sc->sc_dev.dv_xname, i, error); 1346 /* 1347 * XXX Should attempt to run with fewer receive 1348 * XXX buffers instead of just failing. 1349 */ 1350 atw_rxdrain(sc); 1351 goto out; 1352 } 1353 } else 1354 ATW_INIT_RXDESC(sc, i); 1355 } 1356 sc->sc_rxptr = 0; 1357 1358 /* 1359 * Initialize the interrupt mask and enable interrupts. 1360 */ 1361 /* normal interrupts */ 1362 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1363 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1364 1365 /* abnormal interrupts */ 1366 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1367 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1368 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1369 1370 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1371 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1372 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1373 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1374 ATW_INTR_TRT; 1375 1376 sc->sc_linkint_mask &= sc->sc_inten; 1377 sc->sc_rxint_mask &= sc->sc_inten; 1378 sc->sc_txint_mask &= sc->sc_inten; 1379 1380 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1381 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1382 1383 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1384 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1385 1386 /* 1387 * Give the transmit and receive rings to the ADM8211. 1388 */ 1389 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1390 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1391 1392 sc->sc_txthresh = 0; 1393 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1394 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1395 1396 /* common 802.11 configuration */ 1397 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1398 switch (ic->ic_opmode) { 1399 case IEEE80211_M_STA: 1400 break; 1401 case IEEE80211_M_AHDEMO: /* XXX */ 1402 case IEEE80211_M_IBSS: 1403 ic->ic_flags |= IEEE80211_F_IBSSON; 1404 /*FALLTHROUGH*/ 1405 case IEEE80211_M_HOSTAP: /* XXX */ 1406 break; 1407 case IEEE80211_M_MONITOR: /* XXX */ 1408 break; 1409 } 1410 1411 switch (ic->ic_opmode) { 1412 case IEEE80211_M_AHDEMO: 1413 case IEEE80211_M_HOSTAP: 1414 #ifndef IEEE80211_NO_HOSTAP 1415 ic->ic_bss->ni_intval = ic->ic_lintval; 1416 ic->ic_bss->ni_rssi = 0; 1417 ic->ic_bss->ni_rstamp = 0; 1418 #endif /* !IEEE80211_NO_HOSTAP */ 1419 break; 1420 default: /* XXX */ 1421 break; 1422 } 1423 1424 sc->sc_wepctl = 0; 1425 1426 atw_write_ssid(sc); 1427 atw_write_sup_rates(sc); 1428 atw_write_wep(sc); 1429 1430 ic->ic_state = IEEE80211_S_INIT; 1431 1432 /* 1433 * Set the receive filter. This will start the transmit and 1434 * receive processes. 1435 */ 1436 atw_filter_setup(sc); 1437 1438 /* 1439 * Start the receive process. 1440 */ 1441 ATW_WRITE(sc, ATW_RDR, 0x1); 1442 1443 /* 1444 * Note that the interface is now running. 1445 */ 1446 ifp->if_flags |= IFF_RUNNING; 1447 ifp->if_flags &= ~IFF_OACTIVE; 1448 1449 /* send no beacons, yet. */ 1450 atw_start_beacon(sc, 0); 1451 1452 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1453 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1454 else 1455 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1456 out: 1457 if (error) { 1458 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1459 sc->sc_tx_timer = 0; 1460 ifp->if_timer = 0; 1461 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1462 } 1463 #ifdef ATW_DEBUG 1464 atw_print_regs(sc, "end of init"); 1465 #endif /* ATW_DEBUG */ 1466 1467 return (error); 1468 } 1469 1470 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1471 * 0: MAC control of RF3000/Si4126. 1472 * 1473 * Applies power, or selects RF front-end? Sets reset condition. 1474 * 1475 * TBD support non-RFMD BBP, non-SiLabs synth. 1476 */ 1477 static void 1478 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1479 { 1480 if (enable) { 1481 ATW_WRITE(sc, ATW_SYNRF, 1482 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1483 DELAY(atw_bbp_io_enable_delay); 1484 } else { 1485 ATW_WRITE(sc, ATW_SYNRF, 0); 1486 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1487 } 1488 } 1489 1490 static int 1491 atw_tune(struct atw_softc *sc) 1492 { 1493 int rc; 1494 u_int chan; 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 1497 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1498 if (chan == IEEE80211_CHAN_ANY) 1499 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1500 1501 if (chan == sc->sc_cur_chan) 1502 return 0; 1503 1504 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1505 sc->sc_cur_chan, chan)); 1506 1507 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1508 1509 atw_si4126_tune(sc, chan); 1510 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1511 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1512 chan); 1513 1514 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1515 DELAY(atw_nar_delay); 1516 ATW_WRITE(sc, ATW_RDR, 0x1); 1517 1518 if (rc == 0) 1519 sc->sc_cur_chan = chan; 1520 1521 return rc; 1522 } 1523 1524 #ifdef ATW_SYNDEBUG 1525 static void 1526 atw_si4126_print(struct atw_softc *sc) 1527 { 1528 struct ifnet *ifp = &sc->sc_if; 1529 u_int addr, val; 1530 1531 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1532 return; 1533 1534 for (addr = 0; addr <= 8; addr++) { 1535 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1536 if (atw_si4126_read(sc, addr, &val) == 0) { 1537 printf("<unknown> (quitting print-out)\n"); 1538 break; 1539 } 1540 printf("%05x\n", val); 1541 } 1542 } 1543 #endif /* ATW_SYNDEBUG */ 1544 1545 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1546 * 1547 * The RF/IF synthesizer produces two reference frequencies for 1548 * the RF2948B transceiver. The first frequency the RF2948B requires 1549 * is two times the so-called "intermediate frequency" (IF). Since 1550 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1551 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1552 * frequency required by the transceiver is the radio frequency 1553 * (RF). This is a superheterodyne transceiver; for f(chan) the 1554 * center frequency of the channel we are tuning, RF = f(chan) - 1555 * IF. 1556 * 1557 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1558 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1559 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1560 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1561 */ 1562 static void 1563 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1564 { 1565 u_int mhz; 1566 u_int R; 1567 u_int32_t gpio; 1568 u_int16_t gain; 1569 1570 #ifdef ATW_SYNDEBUG 1571 atw_si4126_print(sc); 1572 #endif /* ATW_SYNDEBUG */ 1573 1574 if (chan == 14) 1575 mhz = 2484; 1576 else 1577 mhz = 2412 + 5 * (chan - 1); 1578 1579 /* Tune IF to 748MHz to suit the IF LO input of the 1580 * RF2494B, which is 2 x IF. No need to set an IF divider 1581 * because an IF in 526MHz - 952MHz is allowed. 1582 * 1583 * XIN is 44.000MHz, so divide it by two to get allowable 1584 * range of 2-25MHz. SiLabs tells me that this is not 1585 * strictly necessary. 1586 */ 1587 1588 if (atw_xindiv2) 1589 R = 44; 1590 else 1591 R = 88; 1592 1593 /* Power-up RF, IF synthesizers. */ 1594 atw_si4126_write(sc, SI4126_POWER, 1595 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1596 1597 /* set LPWR, too? */ 1598 atw_si4126_write(sc, SI4126_MAIN, 1599 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1600 1601 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1602 * set KP2 to 1. 1603 * 1604 * REFDIF This is different from the reference driver, which 1605 * always sets SI4126_GAIN to 0. 1606 */ 1607 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1608 1609 atw_si4126_write(sc, SI4126_GAIN, gain); 1610 1611 /* XIN = 44MHz. 1612 * 1613 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1614 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1615 * 1616 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1617 * so that 1496/88 * 44MHz = 748MHz. 1618 */ 1619 atw_si4126_write(sc, SI4126_IFN, 1496); 1620 1621 atw_si4126_write(sc, SI4126_IFR, R); 1622 1623 #ifndef ATW_REFSLAVE 1624 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1625 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1626 * which has no RF1! 1627 */ 1628 atw_si4126_write(sc, SI4126_RF1R, R); 1629 1630 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1631 #endif 1632 1633 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1634 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1635 * Now let's multiply it to mhz. So mhz - IF = N. 1636 */ 1637 atw_si4126_write(sc, SI4126_RF2R, R); 1638 1639 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1640 1641 /* wait 100us from power-up for RF, IF to settle */ 1642 DELAY(100); 1643 1644 gpio = ATW_READ(sc, ATW_GPIO); 1645 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1646 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1647 1648 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1649 /* Set a Prism RF front-end to a special mode for channel 14? 1650 * 1651 * Apparently the SMC2635W needs this, although I don't think 1652 * it has a Prism RF. 1653 */ 1654 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1655 } 1656 ATW_WRITE(sc, ATW_GPIO, gpio); 1657 1658 #ifdef ATW_SYNDEBUG 1659 atw_si4126_print(sc); 1660 #endif /* ATW_SYNDEBUG */ 1661 } 1662 1663 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1664 * diversity. 1665 * 1666 * !!! 1667 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1668 * !!! 1669 */ 1670 static int 1671 atw_rf3000_init(struct atw_softc *sc) 1672 { 1673 int rc = 0; 1674 1675 atw_bbp_io_enable(sc, 1); 1676 1677 /* CCA is acquisition sensitive */ 1678 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1679 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1680 1681 if (rc != 0) 1682 goto out; 1683 1684 /* enable diversity */ 1685 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1686 1687 if (rc != 0) 1688 goto out; 1689 1690 /* sensible setting from a binary-only driver */ 1691 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1692 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 /* magic from a binary-only driver */ 1698 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1699 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1700 1701 if (rc != 0) 1702 goto out; 1703 1704 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1705 1706 if (rc != 0) 1707 goto out; 1708 1709 /* XXX Reference driver remarks that Abocom sets this to 50. 1710 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1711 * in the "reserved" area of register RF3000_OPTIONS1. 1712 */ 1713 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1714 1715 if (rc != 0) 1716 goto out; 1717 1718 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1719 1720 if (rc != 0) 1721 goto out; 1722 1723 out: 1724 atw_bbp_io_enable(sc, 0); 1725 return rc; 1726 } 1727 1728 #ifdef ATW_BBPDEBUG 1729 static void 1730 atw_rf3000_print(struct atw_softc *sc) 1731 { 1732 struct ifnet *ifp = &sc->sc_if; 1733 u_int addr, val; 1734 1735 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1736 return; 1737 1738 for (addr = 0x01; addr <= 0x15; addr++) { 1739 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1740 if (atw_rf3000_read(sc, addr, &val) != 0) { 1741 printf("<unknown> (quitting print-out)\n"); 1742 break; 1743 } 1744 printf("%08x\n", val); 1745 } 1746 } 1747 #endif /* ATW_BBPDEBUG */ 1748 1749 /* Set the power settings on the BBP for channel `chan'. */ 1750 static int 1751 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1752 { 1753 int rc = 0; 1754 u_int32_t reg; 1755 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1756 1757 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1758 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1759 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1760 1761 /* odd channels: LSB, even channels: MSB */ 1762 if (chan % 2 == 1) { 1763 txpower &= 0xFF; 1764 lpf_cutoff &= 0xFF; 1765 lna_gs_thresh &= 0xFF; 1766 } else { 1767 txpower >>= 8; 1768 lpf_cutoff >>= 8; 1769 lna_gs_thresh >>= 8; 1770 } 1771 1772 #ifdef ATW_BBPDEBUG 1773 atw_rf3000_print(sc); 1774 #endif /* ATW_BBPDEBUG */ 1775 1776 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1777 "lna_gs_thresh %02x\n", 1778 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1779 1780 atw_bbp_io_enable(sc, 1); 1781 1782 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1783 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1784 goto out; 1785 1786 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1787 goto out; 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1790 goto out; 1791 1792 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1793 1794 if (rc != 0) 1795 goto out; 1796 1797 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1798 1799 if (rc != 0) 1800 goto out; 1801 1802 #ifdef ATW_BBPDEBUG 1803 atw_rf3000_print(sc); 1804 #endif /* ATW_BBPDEBUG */ 1805 1806 out: 1807 atw_bbp_io_enable(sc, 0); 1808 1809 /* set beacon, rts, atim transmit power */ 1810 reg = ATW_READ(sc, ATW_PLCPHD); 1811 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1812 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1813 ATW_PLCPHD_SERVICE_MASK); 1814 ATW_WRITE(sc, ATW_PLCPHD, reg); 1815 DELAY(atw_plcphd_delay); 1816 1817 return rc; 1818 } 1819 1820 /* Write a register on the RF3000 baseband processor using the 1821 * registers provided by the ADM8211 for this purpose. 1822 * 1823 * Return 0 on success. 1824 */ 1825 static int 1826 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1827 { 1828 u_int32_t reg; 1829 int i; 1830 1831 reg = sc->sc_bbpctl_wr | 1832 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1833 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1834 1835 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1836 ATW_WRITE(sc, ATW_BBPCTL, reg); 1837 DELAY(2 * atw_pseudo_milli); 1838 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1839 break; 1840 } 1841 1842 if (i < 0) { 1843 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1844 return ETIMEDOUT; 1845 } 1846 return 0; 1847 } 1848 1849 /* Read a register on the RF3000 baseband processor using the registers 1850 * the ADM8211 provides for this purpose. 1851 * 1852 * The 7-bit register address is addr. Record the 8-bit data in the register 1853 * in *val. 1854 * 1855 * Return 0 on success. 1856 * 1857 * XXX This does not seem to work. The ADM8211 must require more or 1858 * different magic to read the chip than to write it. Possibly some 1859 * of the magic I have derived from a binary-only driver concerns 1860 * the "chip address" (see the RF3000 manual). 1861 */ 1862 #ifdef ATW_BBPDEBUG 1863 static int 1864 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1865 { 1866 u_int32_t reg; 1867 int i; 1868 1869 for (i = 1000; --i >= 0; ) { 1870 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1871 break; 1872 DELAY(100); 1873 } 1874 1875 if (i < 0) { 1876 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1877 sc->sc_dev.dv_xname); 1878 return ETIMEDOUT; 1879 } 1880 1881 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1882 1883 ATW_WRITE(sc, ATW_BBPCTL, reg); 1884 1885 for (i = 1000; --i >= 0; ) { 1886 DELAY(100); 1887 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1888 break; 1889 } 1890 1891 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1892 1893 if (i < 0) { 1894 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1895 sc->sc_dev.dv_xname, reg); 1896 return ETIMEDOUT; 1897 } 1898 if (val != NULL) 1899 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1900 return 0; 1901 } 1902 #endif /* ATW_BBPDEBUG */ 1903 1904 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1905 * provided by the ADM8211 for that purpose. 1906 * 1907 * val is 18 bits of data, and val is the 4-bit address of the register. 1908 * 1909 * Return 0 on success. 1910 */ 1911 static void 1912 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1913 { 1914 uint32_t bits, mask, reg; 1915 const int nbits = 22; 1916 1917 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1918 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1919 1920 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1921 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1922 1923 reg = ATW_SYNRF_SELSYN; 1924 /* reference driver: reset Si4126 serial bus to initial 1925 * conditions? 1926 */ 1927 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1928 ATW_WRITE(sc, ATW_SYNRF, reg); 1929 1930 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1931 if ((bits & mask) != 0) 1932 reg |= ATW_SYNRF_SYNDATA; 1933 else 1934 reg &= ~ATW_SYNRF_SYNDATA; 1935 ATW_WRITE(sc, ATW_SYNRF, reg); 1936 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1937 ATW_WRITE(sc, ATW_SYNRF, reg); 1938 } 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1940 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1941 } 1942 1943 /* Read 18-bit data from the 4-bit address addr in Si4126 1944 * RF synthesizer and write the data to *val. Return 0 on success. 1945 * 1946 * XXX This does not seem to work. The ADM8211 must require more or 1947 * different magic to read the chip than to write it. 1948 */ 1949 #ifdef ATW_SYNDEBUG 1950 static int 1951 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1952 { 1953 u_int32_t reg; 1954 int i; 1955 1956 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1957 1958 for (i = 1000; --i >= 0; ) { 1959 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1960 break; 1961 DELAY(100); 1962 } 1963 1964 if (i < 0) { 1965 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1966 sc->sc_dev.dv_xname); 1967 return ETIMEDOUT; 1968 } 1969 1970 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1971 1972 ATW_WRITE(sc, ATW_SYNCTL, reg); 1973 1974 for (i = 1000; --i >= 0; ) { 1975 DELAY(100); 1976 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1977 break; 1978 } 1979 1980 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1981 1982 if (i < 0) { 1983 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1984 sc->sc_dev.dv_xname, reg); 1985 return ETIMEDOUT; 1986 } 1987 if (val != NULL) 1988 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1989 ATW_SYNCTL_DATA_MASK); 1990 return 0; 1991 } 1992 #endif /* ATW_SYNDEBUG */ 1993 1994 /* XXX is the endianness correct? test. */ 1995 #define atw_calchash(addr) \ 1996 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1997 1998 /* 1999 * atw_filter_setup: 2000 * 2001 * Set the ADM8211's receive filter. 2002 */ 2003 static void 2004 atw_filter_setup(struct atw_softc *sc) 2005 { 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 struct ethercom *ec = &sc->sc_ec; 2008 struct ifnet *ifp = &sc->sc_if; 2009 int hash; 2010 u_int32_t hashes[2]; 2011 struct ether_multi *enm; 2012 struct ether_multistep step; 2013 2014 /* According to comments in tlp_al981_filter_setup 2015 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2016 * multicast filter to be set while it is running. Hopefully 2017 * the ADM8211 is not the same! 2018 */ 2019 if ((ifp->if_flags & IFF_RUNNING) != 0) 2020 atw_idle(sc, ATW_NAR_SR); 2021 2022 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2023 ifp->if_flags &= ~IFF_ALLMULTI; 2024 2025 /* XXX in scan mode, do not filter packets. Maybe this is 2026 * unnecessary. 2027 */ 2028 if (ic->ic_state == IEEE80211_S_SCAN || 2029 (ifp->if_flags & IFF_PROMISC) != 0) { 2030 sc->sc_opmode |= ATW_NAR_PR; 2031 goto allmulti; 2032 } 2033 2034 hashes[0] = hashes[1] = 0x0; 2035 2036 /* 2037 * Program the 64-bit multicast hash filter. 2038 */ 2039 ETHER_FIRST_MULTI(step, ec, enm); 2040 while (enm != NULL) { 2041 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2042 ETHER_ADDR_LEN) != 0) 2043 goto allmulti; 2044 2045 hash = atw_calchash(enm->enm_addrlo); 2046 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2047 ETHER_NEXT_MULTI(step, enm); 2048 sc->sc_opmode |= ATW_NAR_MM; 2049 } 2050 ifp->if_flags &= ~IFF_ALLMULTI; 2051 goto setit; 2052 2053 allmulti: 2054 sc->sc_opmode |= ATW_NAR_MM; 2055 ifp->if_flags |= IFF_ALLMULTI; 2056 hashes[0] = hashes[1] = 0xffffffff; 2057 2058 setit: 2059 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2060 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2061 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2062 DELAY(atw_nar_delay); 2063 ATW_WRITE(sc, ATW_RDR, 0x1); 2064 2065 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2066 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2067 } 2068 2069 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2070 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2071 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2072 * no beacon with the preferred BSSID and SSID in the number of 2073 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2074 */ 2075 static void 2076 atw_write_bssid(struct atw_softc *sc) 2077 { 2078 struct ieee80211com *ic = &sc->sc_ic; 2079 u_int8_t *bssid; 2080 2081 bssid = ic->ic_bss->ni_bssid; 2082 2083 ATW_WRITE(sc, ATW_BSSID0, 2084 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2085 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2086 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2087 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2088 2089 ATW_WRITE(sc, ATW_ABDA1, 2090 (ATW_READ(sc, ATW_ABDA1) & 2091 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2092 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2093 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2094 2095 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2096 ether_sprintf(sc->sc_bssid))); 2097 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2098 2099 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2100 } 2101 2102 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2103 * 16-bit word. 2104 */ 2105 static void 2106 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2107 { 2108 u_int i; 2109 u_int8_t *ptr; 2110 2111 memcpy(&sc->sc_sram[ofs], buf, buflen); 2112 2113 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2114 2115 KASSERT(buflen + ofs <= sc->sc_sramlen); 2116 2117 ptr = &sc->sc_sram[ofs]; 2118 2119 for (i = 0; i < buflen; i += 2) { 2120 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2121 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2122 DELAY(atw_writewep_delay); 2123 2124 ATW_WRITE(sc, ATW_WESK, 2125 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2126 DELAY(atw_writewep_delay); 2127 } 2128 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2129 2130 if (sc->sc_if.if_flags & IFF_DEBUG) { 2131 int n_octets = 0; 2132 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2133 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2134 for (i = 0; i < buflen; i++) { 2135 printf(" %02x", ptr[i]); 2136 if (++n_octets % 24 == 0) 2137 printf("\n"); 2138 } 2139 if (n_octets % 24 != 0) 2140 printf("\n"); 2141 } 2142 } 2143 2144 static int 2145 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2146 { 2147 struct atw_softc *sc = ic->ic_ifp->if_softc; 2148 u_int keyix = k->wk_keyix; 2149 2150 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2151 2152 if (keyix >= IEEE80211_WEP_NKID) 2153 return 0; 2154 if (k->wk_keylen != 0) 2155 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2156 2157 return 1; 2158 } 2159 2160 static int 2161 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2162 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2163 { 2164 struct atw_softc *sc = ic->ic_ifp->if_softc; 2165 2166 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2167 2168 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2169 return 0; 2170 2171 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2172 2173 return 1; 2174 } 2175 2176 static void 2177 atw_key_update_begin(struct ieee80211com *ic) 2178 { 2179 #ifdef ATW_DEBUG 2180 struct ifnet *ifp = ic->ic_ifp; 2181 struct atw_softc *sc = ifp->if_softc; 2182 #endif 2183 2184 DPRINTF(sc, ("%s:\n", __func__)); 2185 } 2186 2187 static void 2188 atw_key_update_end(struct ieee80211com *ic) 2189 { 2190 struct ifnet *ifp = ic->ic_ifp; 2191 struct atw_softc *sc = ifp->if_softc; 2192 2193 DPRINTF(sc, ("%s:\n", __func__)); 2194 2195 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2196 return; 2197 if (ATW_IS_ENABLED(sc) == 0) 2198 return; 2199 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2200 atw_write_wep(sc); 2201 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2202 DELAY(atw_nar_delay); 2203 ATW_WRITE(sc, ATW_RDR, 0x1); 2204 } 2205 2206 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2207 static void 2208 atw_write_wep(struct atw_softc *sc) 2209 { 2210 struct ieee80211com *ic = &sc->sc_ic; 2211 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2212 u_int8_t buf[IEEE80211_WEP_NKID] 2213 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2214 u_int32_t reg; 2215 int i; 2216 2217 sc->sc_wepctl = 0; 2218 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2219 2220 memset(&buf[0][0], 0, sizeof(buf)); 2221 2222 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2223 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2224 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2225 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2226 buf[i][1] = ATW_WEP_ENABLED; 2227 } else { 2228 buf[i][1] = 0; 2229 continue; 2230 } 2231 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2232 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2233 ic->ic_nw_keys[i].wk_keylen - 1); 2234 } 2235 2236 reg = ATW_READ(sc, ATW_MACTEST); 2237 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2238 reg &= ~ATW_MACTEST_KEYID_MASK; 2239 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2240 ATW_WRITE(sc, ATW_MACTEST, reg); 2241 2242 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2243 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2244 2245 switch (sc->sc_rev) { 2246 case ATW_REVISION_AB: 2247 case ATW_REVISION_AF: 2248 /* Bypass WEP on Rx. */ 2249 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2250 break; 2251 default: 2252 break; 2253 } 2254 2255 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2256 sizeof(buf)); 2257 2258 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2259 } 2260 2261 static void 2262 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2263 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2264 { 2265 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2266 2267 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2268 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2269 return; 2270 2271 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2272 2273 switch (subtype) { 2274 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2275 case IEEE80211_FC0_SUBTYPE_BEACON: 2276 if (ic->ic_opmode == IEEE80211_M_IBSS && 2277 ic->ic_state == IEEE80211_S_RUN) { 2278 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2279 (void)ieee80211_ibss_merge(ni); 2280 } 2281 break; 2282 default: 2283 break; 2284 } 2285 return; 2286 } 2287 2288 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2289 * In ad hoc mode, the SSID is written to the beacons sent by the 2290 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2291 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2292 * indications. 2293 */ 2294 static void 2295 atw_write_ssid(struct atw_softc *sc) 2296 { 2297 struct ieee80211com *ic = &sc->sc_ic; 2298 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2299 * it only expects the element length, not its ID. 2300 */ 2301 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2302 2303 memset(buf, 0, sizeof(buf)); 2304 buf[0] = ic->ic_bss->ni_esslen; 2305 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2306 2307 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2308 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2309 } 2310 2311 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2312 * In ad hoc mode, the supported rates are written to beacons sent by the 2313 * ADM8211. 2314 */ 2315 static void 2316 atw_write_sup_rates(struct atw_softc *sc) 2317 { 2318 struct ieee80211com *ic = &sc->sc_ic; 2319 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2320 * supported rates 2321 */ 2322 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2323 2324 memset(buf, 0, sizeof(buf)); 2325 2326 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2327 2328 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2329 ic->ic_bss->ni_rates.rs_nrates); 2330 2331 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2332 } 2333 2334 /* Start/stop sending beacons. */ 2335 void 2336 atw_start_beacon(struct atw_softc *sc, int start) 2337 { 2338 struct ieee80211com *ic = &sc->sc_ic; 2339 uint16_t chan; 2340 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2341 size_t len; 2342 2343 if (ATW_IS_ENABLED(sc) == 0) 2344 return; 2345 2346 /* start beacons */ 2347 len = sizeof(struct ieee80211_frame) + 2348 8 /* timestamp */ + 2 /* beacon interval */ + 2349 2 /* capability info */ + 2350 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2351 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2352 3 /* DS parameters */ + 2353 IEEE80211_CRC_LEN; 2354 2355 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2356 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2357 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2358 2359 ATW_WRITE(sc, ATW_BCNT, bcnt); 2360 ATW_WRITE(sc, ATW_CAP1, cap1); 2361 2362 if (!start) 2363 return; 2364 2365 /* TBD use ni_capinfo */ 2366 2367 capinfo = 0; 2368 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2369 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2370 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2371 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2372 2373 switch (ic->ic_opmode) { 2374 case IEEE80211_M_IBSS: 2375 len += 4; /* IBSS parameters */ 2376 capinfo |= IEEE80211_CAPINFO_IBSS; 2377 break; 2378 case IEEE80211_M_HOSTAP: 2379 /* XXX 6-byte minimum TIM */ 2380 len += atw_beacon_len_adjust; 2381 capinfo |= IEEE80211_CAPINFO_ESS; 2382 break; 2383 default: 2384 return; 2385 } 2386 2387 /* set listen interval 2388 * XXX do software units agree w/ hardware? 2389 */ 2390 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2391 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2392 2393 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2394 2395 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2396 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2397 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2398 2399 ATW_WRITE(sc, ATW_BCNT, bcnt); 2400 ATW_WRITE(sc, ATW_BPLI, bpli); 2401 ATW_WRITE(sc, ATW_CAP0, cap0); 2402 ATW_WRITE(sc, ATW_CAP1, cap1); 2403 2404 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2405 sc->sc_dev.dv_xname, bcnt)); 2406 2407 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2408 sc->sc_dev.dv_xname, cap1)); 2409 } 2410 2411 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2412 static inline uint32_t 2413 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2414 { 2415 /* Following the reference driver's lead, I compute 2416 * 2417 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2418 * 2419 * without using 64-bit arithmetic, using the following 2420 * relationship: 2421 * 2422 * (0x100000000 * H + L) % m 2423 * = ((0x100000000 % m) * H + L) % m 2424 * = (((0xffffffff + 1) % m) * H + L) % m 2425 * = ((0xffffffff % m + 1 % m) * H + L) % m 2426 * = ((0xffffffff % m + 1) * H + L) % m 2427 */ 2428 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2429 } 2430 2431 static uint64_t 2432 atw_get_tsft(struct atw_softc *sc) 2433 { 2434 int i; 2435 uint32_t tsfth, tsftl; 2436 for (i = 0; i < 2; i++) { 2437 tsfth = ATW_READ(sc, ATW_TSFTH); 2438 tsftl = ATW_READ(sc, ATW_TSFTL); 2439 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2440 break; 2441 } 2442 return ((uint64_t)tsfth << 32) | tsftl; 2443 } 2444 2445 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2446 * the ieee80211com. 2447 * 2448 * Predict the next target beacon transmission time (TBTT) and 2449 * write it to the ADM8211. 2450 */ 2451 static void 2452 atw_predict_beacon(struct atw_softc *sc) 2453 { 2454 #define TBTTOFS 20 /* TU */ 2455 2456 struct ieee80211com *ic = &sc->sc_ic; 2457 uint64_t tsft; 2458 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2459 union { 2460 uint64_t word; 2461 uint8_t tstamp[8]; 2462 } u; 2463 2464 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2465 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2466 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2467 tsft = atw_get_tsft(sc); 2468 u.word = htole64(tsft); 2469 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2470 sizeof(ic->ic_bss->ni_tstamp)); 2471 } else 2472 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2473 2474 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2475 2476 tsftl = tsft & 0xFFFFFFFF; 2477 tsfth = tsft >> 32; 2478 2479 /* We sent/received the last beacon `past' microseconds 2480 * after the interval divided the TSF timer. 2481 */ 2482 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2483 2484 /* Skip ten beacons so that the TBTT cannot pass before 2485 * we've programmed it. Ten is an arbitrary number. 2486 */ 2487 tbtt = past_even + ival * 10; 2488 2489 ATW_WRITE(sc, ATW_TOFS1, 2490 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2491 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2492 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2493 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2494 #undef TBTTOFS 2495 } 2496 2497 static void 2498 atw_next_scan(void *arg) 2499 { 2500 struct atw_softc *sc = arg; 2501 struct ieee80211com *ic = &sc->sc_ic; 2502 int s; 2503 2504 /* don't call atw_start w/o network interrupts blocked */ 2505 s = splnet(); 2506 if (ic->ic_state == IEEE80211_S_SCAN) 2507 ieee80211_next_scan(ic); 2508 splx(s); 2509 } 2510 2511 /* Synchronize the hardware state with the software state. */ 2512 static int 2513 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2514 { 2515 struct ifnet *ifp = ic->ic_ifp; 2516 struct atw_softc *sc = ifp->if_softc; 2517 enum ieee80211_state ostate; 2518 int error = 0; 2519 2520 ostate = ic->ic_state; 2521 callout_stop(&sc->sc_scan_ch); 2522 2523 switch (nstate) { 2524 case IEEE80211_S_AUTH: 2525 case IEEE80211_S_ASSOC: 2526 error = atw_tune(sc); 2527 break; 2528 case IEEE80211_S_INIT: 2529 callout_stop(&sc->sc_scan_ch); 2530 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2531 atw_start_beacon(sc, 0); 2532 break; 2533 case IEEE80211_S_SCAN: 2534 error = atw_tune(sc); 2535 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2536 atw_next_scan, sc); 2537 break; 2538 case IEEE80211_S_RUN: 2539 error = atw_tune(sc); 2540 atw_write_bssid(sc); 2541 atw_write_ssid(sc); 2542 atw_write_sup_rates(sc); 2543 2544 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2545 ic->ic_opmode == IEEE80211_M_MONITOR) 2546 break; 2547 2548 /* set listen interval 2549 * XXX do software units agree w/ hardware? 2550 */ 2551 ATW_WRITE(sc, ATW_BPLI, 2552 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2553 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2554 ATW_BPLI_LI_MASK)); 2555 2556 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2557 ATW_READ(sc, ATW_BPLI))); 2558 2559 atw_predict_beacon(sc); 2560 2561 switch (ic->ic_opmode) { 2562 case IEEE80211_M_AHDEMO: 2563 case IEEE80211_M_HOSTAP: 2564 case IEEE80211_M_IBSS: 2565 atw_start_beacon(sc, 1); 2566 break; 2567 case IEEE80211_M_MONITOR: 2568 case IEEE80211_M_STA: 2569 break; 2570 } 2571 2572 break; 2573 } 2574 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2575 } 2576 2577 /* 2578 * atw_add_rxbuf: 2579 * 2580 * Add a receive buffer to the indicated descriptor. 2581 */ 2582 int 2583 atw_add_rxbuf(struct atw_softc *sc, int idx) 2584 { 2585 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2586 struct mbuf *m; 2587 int error; 2588 2589 MGETHDR(m, M_DONTWAIT, MT_DATA); 2590 if (m == NULL) 2591 return (ENOBUFS); 2592 2593 MCLGET(m, M_DONTWAIT); 2594 if ((m->m_flags & M_EXT) == 0) { 2595 m_freem(m); 2596 return (ENOBUFS); 2597 } 2598 2599 if (rxs->rxs_mbuf != NULL) 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 2602 rxs->rxs_mbuf = m; 2603 2604 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2606 BUS_DMA_READ|BUS_DMA_NOWAIT); 2607 if (error) { 2608 printf("%s: can't load rx DMA map %d, error = %d\n", 2609 sc->sc_dev.dv_xname, idx, error); 2610 panic("atw_add_rxbuf"); /* XXX */ 2611 } 2612 2613 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2614 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2615 2616 ATW_INIT_RXDESC(sc, idx); 2617 2618 return (0); 2619 } 2620 2621 /* 2622 * Release any queued transmit buffers. 2623 */ 2624 void 2625 atw_txdrain(struct atw_softc *sc) 2626 { 2627 struct atw_txsoft *txs; 2628 2629 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2630 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2631 if (txs->txs_mbuf != NULL) { 2632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2633 m_freem(txs->txs_mbuf); 2634 txs->txs_mbuf = NULL; 2635 } 2636 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2637 sc->sc_txfree += txs->txs_ndescs; 2638 } 2639 2640 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2641 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2642 sc->sc_txfree != ATW_NTXDESC)); 2643 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2644 sc->sc_tx_timer = 0; 2645 } 2646 2647 /* 2648 * atw_stop: [ ifnet interface function ] 2649 * 2650 * Stop transmission on the interface. 2651 */ 2652 void 2653 atw_stop(struct ifnet *ifp, int disable) 2654 { 2655 struct atw_softc *sc = ifp->if_softc; 2656 struct ieee80211com *ic = &sc->sc_ic; 2657 2658 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2659 2660 /* Disable interrupts. */ 2661 ATW_WRITE(sc, ATW_IER, 0); 2662 2663 /* Stop the transmit and receive processes. */ 2664 sc->sc_opmode = 0; 2665 ATW_WRITE(sc, ATW_NAR, 0); 2666 DELAY(atw_nar_delay); 2667 ATW_WRITE(sc, ATW_TDBD, 0); 2668 ATW_WRITE(sc, ATW_TDBP, 0); 2669 ATW_WRITE(sc, ATW_RDB, 0); 2670 2671 atw_txdrain(sc); 2672 2673 if (disable) { 2674 atw_rxdrain(sc); 2675 atw_disable(sc); 2676 } 2677 2678 /* 2679 * Mark the interface down and cancel the watchdog timer. 2680 */ 2681 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2682 sc->sc_tx_timer = 0; 2683 ifp->if_timer = 0; 2684 2685 if (!disable) 2686 atw_reset(sc); 2687 } 2688 2689 /* 2690 * atw_rxdrain: 2691 * 2692 * Drain the receive queue. 2693 */ 2694 void 2695 atw_rxdrain(struct atw_softc *sc) 2696 { 2697 struct atw_rxsoft *rxs; 2698 int i; 2699 2700 for (i = 0; i < ATW_NRXDESC; i++) { 2701 rxs = &sc->sc_rxsoft[i]; 2702 if (rxs->rxs_mbuf == NULL) 2703 continue; 2704 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2705 m_freem(rxs->rxs_mbuf); 2706 rxs->rxs_mbuf = NULL; 2707 } 2708 } 2709 2710 /* 2711 * atw_detach: 2712 * 2713 * Detach an ADM8211 interface. 2714 */ 2715 int 2716 atw_detach(struct atw_softc *sc) 2717 { 2718 struct ifnet *ifp = &sc->sc_if; 2719 struct atw_rxsoft *rxs; 2720 struct atw_txsoft *txs; 2721 int i; 2722 2723 /* 2724 * Succeed now if there isn't any work to do. 2725 */ 2726 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2727 return (0); 2728 2729 callout_stop(&sc->sc_scan_ch); 2730 2731 ieee80211_ifdetach(&sc->sc_ic); 2732 if_detach(ifp); 2733 2734 for (i = 0; i < ATW_NRXDESC; i++) { 2735 rxs = &sc->sc_rxsoft[i]; 2736 if (rxs->rxs_mbuf != NULL) { 2737 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2738 m_freem(rxs->rxs_mbuf); 2739 rxs->rxs_mbuf = NULL; 2740 } 2741 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2742 } 2743 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2744 txs = &sc->sc_txsoft[i]; 2745 if (txs->txs_mbuf != NULL) { 2746 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2747 m_freem(txs->txs_mbuf); 2748 txs->txs_mbuf = NULL; 2749 } 2750 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2751 } 2752 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2753 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2754 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2755 sizeof(struct atw_control_data)); 2756 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2757 2758 shutdownhook_disestablish(sc->sc_sdhook); 2759 powerhook_disestablish(sc->sc_powerhook); 2760 2761 if (sc->sc_srom) 2762 free(sc->sc_srom, M_DEVBUF); 2763 2764 return (0); 2765 } 2766 2767 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2768 void 2769 atw_shutdown(void *arg) 2770 { 2771 struct atw_softc *sc = arg; 2772 2773 atw_stop(&sc->sc_if, 1); 2774 } 2775 2776 int 2777 atw_intr(void *arg) 2778 { 2779 struct atw_softc *sc = arg; 2780 struct ifnet *ifp = &sc->sc_if; 2781 u_int32_t status, rxstatus, txstatus, linkstatus; 2782 int handled = 0, txthresh; 2783 2784 #ifdef DEBUG 2785 if (ATW_IS_ENABLED(sc) == 0) 2786 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2787 #endif 2788 2789 /* 2790 * If the interface isn't running, the interrupt couldn't 2791 * possibly have come from us. 2792 */ 2793 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2794 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2795 return (0); 2796 2797 for (;;) { 2798 status = ATW_READ(sc, ATW_STSR); 2799 2800 if (status) 2801 ATW_WRITE(sc, ATW_STSR, status); 2802 2803 #ifdef ATW_DEBUG 2804 #define PRINTINTR(flag) do { \ 2805 if ((status & flag) != 0) { \ 2806 printf("%s" #flag, delim); \ 2807 delim = ","; \ 2808 } \ 2809 } while (0) 2810 2811 if (atw_debug > 1 && status) { 2812 const char *delim = "<"; 2813 2814 printf("%s: reg[STSR] = %x", 2815 sc->sc_dev.dv_xname, status); 2816 2817 PRINTINTR(ATW_INTR_FBE); 2818 PRINTINTR(ATW_INTR_LINKOFF); 2819 PRINTINTR(ATW_INTR_LINKON); 2820 PRINTINTR(ATW_INTR_RCI); 2821 PRINTINTR(ATW_INTR_RDU); 2822 PRINTINTR(ATW_INTR_REIS); 2823 PRINTINTR(ATW_INTR_RPS); 2824 PRINTINTR(ATW_INTR_TCI); 2825 PRINTINTR(ATW_INTR_TDU); 2826 PRINTINTR(ATW_INTR_TLT); 2827 PRINTINTR(ATW_INTR_TPS); 2828 PRINTINTR(ATW_INTR_TRT); 2829 PRINTINTR(ATW_INTR_TUF); 2830 PRINTINTR(ATW_INTR_BCNTC); 2831 PRINTINTR(ATW_INTR_ATIME); 2832 PRINTINTR(ATW_INTR_TBTT); 2833 PRINTINTR(ATW_INTR_TSCZ); 2834 PRINTINTR(ATW_INTR_TSFTF); 2835 printf(">\n"); 2836 } 2837 #undef PRINTINTR 2838 #endif /* ATW_DEBUG */ 2839 2840 if ((status & sc->sc_inten) == 0) 2841 break; 2842 2843 handled = 1; 2844 2845 rxstatus = status & sc->sc_rxint_mask; 2846 txstatus = status & sc->sc_txint_mask; 2847 linkstatus = status & sc->sc_linkint_mask; 2848 2849 if (linkstatus) { 2850 atw_linkintr(sc, linkstatus); 2851 } 2852 2853 if (rxstatus) { 2854 /* Grab any new packets. */ 2855 atw_rxintr(sc); 2856 2857 if (rxstatus & ATW_INTR_RDU) { 2858 printf("%s: receive ring overrun\n", 2859 sc->sc_dev.dv_xname); 2860 /* Get the receive process going again. */ 2861 ATW_WRITE(sc, ATW_RDR, 0x1); 2862 break; 2863 } 2864 } 2865 2866 if (txstatus) { 2867 /* Sweep up transmit descriptors. */ 2868 atw_txintr(sc); 2869 2870 if (txstatus & ATW_INTR_TLT) 2871 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2872 sc->sc_dev.dv_xname)); 2873 2874 if (txstatus & ATW_INTR_TRT) 2875 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2876 sc->sc_dev.dv_xname)); 2877 2878 /* If Tx under-run, increase our transmit threshold 2879 * if another is available. 2880 */ 2881 txthresh = sc->sc_txthresh + 1; 2882 if ((txstatus & ATW_INTR_TUF) && 2883 sc->sc_txth[txthresh].txth_name != NULL) { 2884 /* Idle the transmit process. */ 2885 atw_idle(sc, ATW_NAR_ST); 2886 2887 sc->sc_txthresh = txthresh; 2888 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2889 sc->sc_opmode |= 2890 sc->sc_txth[txthresh].txth_opmode; 2891 printf("%s: transmit underrun; new " 2892 "threshold: %s\n", sc->sc_dev.dv_xname, 2893 sc->sc_txth[txthresh].txth_name); 2894 2895 /* Set the new threshold and restart 2896 * the transmit process. 2897 */ 2898 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2899 DELAY(atw_nar_delay); 2900 ATW_WRITE(sc, ATW_RDR, 0x1); 2901 /* XXX Log every Nth underrun from 2902 * XXX now on? 2903 */ 2904 } 2905 } 2906 2907 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2908 if (status & ATW_INTR_TPS) 2909 printf("%s: transmit process stopped\n", 2910 sc->sc_dev.dv_xname); 2911 if (status & ATW_INTR_RPS) 2912 printf("%s: receive process stopped\n", 2913 sc->sc_dev.dv_xname); 2914 (void)atw_init(ifp); 2915 break; 2916 } 2917 2918 if (status & ATW_INTR_FBE) { 2919 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2920 (void)atw_init(ifp); 2921 break; 2922 } 2923 2924 /* 2925 * Not handled: 2926 * 2927 * Transmit buffer unavailable -- normal 2928 * condition, nothing to do, really. 2929 * 2930 * Early receive interrupt -- not available on 2931 * all chips, we just use RI. We also only 2932 * use single-segment receive DMA, so this 2933 * is mostly useless. 2934 * 2935 * TBD others 2936 */ 2937 } 2938 2939 /* Try to get more packets going. */ 2940 atw_start(ifp); 2941 2942 return (handled); 2943 } 2944 2945 /* 2946 * atw_idle: 2947 * 2948 * Cause the transmit and/or receive processes to go idle. 2949 * 2950 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2951 * process in STSR if I clear SR or ST after the process has already 2952 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2953 * do not seem to be too reliable. Perhaps I have the sense of the 2954 * Rx bits switched with the Tx bits? 2955 */ 2956 void 2957 atw_idle(struct atw_softc *sc, u_int32_t bits) 2958 { 2959 u_int32_t ackmask = 0, opmode, stsr, test0; 2960 int i, s; 2961 2962 s = splnet(); 2963 2964 opmode = sc->sc_opmode & ~bits; 2965 2966 if (bits & ATW_NAR_SR) 2967 ackmask |= ATW_INTR_RPS; 2968 2969 if (bits & ATW_NAR_ST) { 2970 ackmask |= ATW_INTR_TPS; 2971 /* set ATW_NAR_HF to flush TX FIFO. */ 2972 opmode |= ATW_NAR_HF; 2973 } 2974 2975 ATW_WRITE(sc, ATW_NAR, opmode); 2976 DELAY(atw_nar_delay); 2977 2978 for (i = 0; i < 1000; i++) { 2979 stsr = ATW_READ(sc, ATW_STSR); 2980 if ((stsr & ackmask) == ackmask) 2981 break; 2982 DELAY(10); 2983 } 2984 2985 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2986 2987 if ((stsr & ackmask) == ackmask) 2988 goto out; 2989 2990 test0 = ATW_READ(sc, ATW_TEST0); 2991 2992 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2993 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2994 printf("%s: transmit process not idle [%s]\n", 2995 sc->sc_dev.dv_xname, 2996 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2997 printf("%s: bits %08x test0 %08x stsr %08x\n", 2998 sc->sc_dev.dv_xname, bits, test0, stsr); 2999 } 3000 3001 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3002 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3003 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3004 sc->sc_dev.dv_xname, 3005 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3006 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3007 sc->sc_dev.dv_xname, bits, test0, stsr)); 3008 } 3009 out: 3010 if ((bits & ATW_NAR_ST) != 0) 3011 atw_txdrain(sc); 3012 splx(s); 3013 return; 3014 } 3015 3016 /* 3017 * atw_linkintr: 3018 * 3019 * Helper; handle link-status interrupts. 3020 */ 3021 void 3022 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3023 { 3024 struct ieee80211com *ic = &sc->sc_ic; 3025 3026 if (ic->ic_state != IEEE80211_S_RUN) 3027 return; 3028 3029 if (linkstatus & ATW_INTR_LINKON) { 3030 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3031 sc->sc_rescan_timer = 0; 3032 } else if (linkstatus & ATW_INTR_LINKOFF) { 3033 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3034 if (ic->ic_opmode != IEEE80211_M_STA) 3035 return; 3036 sc->sc_rescan_timer = 3; 3037 sc->sc_if.if_timer = 1; 3038 } 3039 } 3040 3041 static inline int 3042 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3043 { 3044 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3045 return 0; 3046 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3047 return 0; 3048 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3049 } 3050 3051 /* 3052 * atw_rxintr: 3053 * 3054 * Helper; handle receive interrupts. 3055 */ 3056 void 3057 atw_rxintr(struct atw_softc *sc) 3058 { 3059 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3060 struct ieee80211com *ic = &sc->sc_ic; 3061 struct ieee80211_node *ni; 3062 struct ieee80211_frame_min *wh; 3063 struct ifnet *ifp = &sc->sc_if; 3064 struct atw_rxsoft *rxs; 3065 struct mbuf *m; 3066 u_int32_t rxstat; 3067 int i, len, rate, rate0; 3068 u_int32_t rssi, rssi0; 3069 3070 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3071 rxs = &sc->sc_rxsoft[i]; 3072 3073 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3074 3075 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3076 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3077 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3078 3079 if (rxstat & ATW_RXSTAT_OWN) 3080 break; /* We have processed all receive buffers. */ 3081 3082 DPRINTF3(sc, 3083 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3084 sc->sc_dev.dv_xname, 3085 rxstat, rssi0, 3086 le32toh(sc->sc_rxdescs[i].ar_buf1), 3087 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3088 3089 /* 3090 * Make sure the packet fits in one buffer. This should 3091 * always be the case. 3092 */ 3093 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3094 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3095 printf("%s: incoming packet spilled, resetting\n", 3096 sc->sc_dev.dv_xname); 3097 (void)atw_init(ifp); 3098 return; 3099 } 3100 3101 /* 3102 * If an error occurred, update stats, clear the status 3103 * word, and leave the packet buffer in place. It will 3104 * simply be reused the next time the ring comes around. 3105 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3106 * error. 3107 */ 3108 3109 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3110 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3111 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3112 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3113 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3114 ATW_RXSTAT_ICVE)) != 0)) { 3115 #define PRINTERR(bit, str) \ 3116 if (rxstat & (bit)) \ 3117 printf("%s: receive error: %s\n", \ 3118 sc->sc_dev.dv_xname, str) 3119 ifp->if_ierrors++; 3120 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3121 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3122 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3123 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3124 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3125 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3126 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3127 #undef PRINTERR 3128 ATW_INIT_RXDESC(sc, i); 3129 continue; 3130 } 3131 3132 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3133 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3134 3135 /* 3136 * No errors; receive the packet. Note the ADM8211 3137 * includes the CRC in promiscuous mode. 3138 */ 3139 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3140 3141 /* 3142 * Allocate a new mbuf cluster. If that fails, we are 3143 * out of memory, and must drop the packet and recycle 3144 * the buffer that's already attached to this descriptor. 3145 */ 3146 m = rxs->rxs_mbuf; 3147 if (atw_add_rxbuf(sc, i) != 0) { 3148 ifp->if_ierrors++; 3149 ATW_INIT_RXDESC(sc, i); 3150 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3151 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3152 continue; 3153 } 3154 3155 ifp->if_ipackets++; 3156 if (sc->sc_opmode & ATW_NAR_PR) 3157 len -= IEEE80211_CRC_LEN; 3158 m->m_pkthdr.rcvif = ifp; 3159 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3160 3161 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3162 rate = 0; 3163 else 3164 rate = rate_tbl[rate0]; 3165 3166 /* The RSSI comes straight from a register in the 3167 * baseband processor. I know that for the RF3000, 3168 * the RSSI register also contains the antenna-selection 3169 * bits. Mask those off. 3170 * 3171 * TBD Treat other basebands. 3172 */ 3173 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3174 rssi = rssi0 & RF3000_RSSI_MASK; 3175 else 3176 rssi = rssi0; 3177 3178 #if NBPFILTER > 0 3179 /* Pass this up to any BPF listeners. */ 3180 if (sc->sc_radiobpf != NULL) { 3181 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3182 3183 tap->ar_rate = rate; 3184 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3185 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3186 3187 /* TBD verify units are dB */ 3188 tap->ar_antsignal = (int)rssi; 3189 /* TBD tap->ar_flags */ 3190 3191 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3192 tap->ar_ihdr.it_len, m); 3193 } 3194 #endif /* NPBFILTER > 0 */ 3195 3196 wh = mtod(m, struct ieee80211_frame_min *); 3197 ni = ieee80211_find_rxnode(ic, wh); 3198 if (atw_hw_decrypted(sc, wh)) { 3199 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3200 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3201 } 3202 ieee80211_input(ic, m, ni, (int)rssi, 0); 3203 ieee80211_free_node(ni); 3204 } 3205 3206 /* Update the receive pointer. */ 3207 sc->sc_rxptr = i; 3208 } 3209 3210 /* 3211 * atw_txintr: 3212 * 3213 * Helper; handle transmit interrupts. 3214 */ 3215 void 3216 atw_txintr(struct atw_softc *sc) 3217 { 3218 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3219 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3220 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3221 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3222 3223 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3224 struct ifnet *ifp = &sc->sc_if; 3225 struct atw_txsoft *txs; 3226 u_int32_t txstat; 3227 3228 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3229 sc->sc_dev.dv_xname, sc->sc_flags)); 3230 3231 /* 3232 * Go through our Tx list and free mbufs for those 3233 * frames that have been transmitted. 3234 */ 3235 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3236 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3237 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3238 3239 #ifdef ATW_DEBUG 3240 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3241 int i; 3242 printf(" txsoft %p transmit chain:\n", txs); 3243 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3244 txs->txs_ndescs - 1, 3245 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3246 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3247 printf(" descriptor %d:\n", i); 3248 printf(" at_status: 0x%08x\n", 3249 le32toh(sc->sc_txdescs[i].at_stat)); 3250 printf(" at_flags: 0x%08x\n", 3251 le32toh(sc->sc_txdescs[i].at_flags)); 3252 printf(" at_buf1: 0x%08x\n", 3253 le32toh(sc->sc_txdescs[i].at_buf1)); 3254 printf(" at_buf2: 0x%08x\n", 3255 le32toh(sc->sc_txdescs[i].at_buf2)); 3256 if (i == txs->txs_lastdesc) 3257 break; 3258 } 3259 } 3260 #endif 3261 3262 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3263 if (txstat & ATW_TXSTAT_OWN) 3264 break; 3265 3266 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3267 3268 sc->sc_txfree += txs->txs_ndescs; 3269 3270 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3271 0, txs->txs_dmamap->dm_mapsize, 3272 BUS_DMASYNC_POSTWRITE); 3273 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3274 m_freem(txs->txs_mbuf); 3275 txs->txs_mbuf = NULL; 3276 3277 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3278 3279 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3280 sc->sc_txfree == 0)); 3281 ifp->if_flags &= ~IFF_OACTIVE; 3282 3283 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3284 (txstat & TXSTAT_ERRMASK) != 0) { 3285 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3286 txstat_buf, sizeof(txstat_buf)); 3287 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3288 txstat_buf, 3289 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3290 } 3291 3292 /* 3293 * Check for errors and collisions. 3294 */ 3295 if (txstat & ATW_TXSTAT_TUF) 3296 sc->sc_stats.ts_tx_tuf++; 3297 if (txstat & ATW_TXSTAT_TLT) 3298 sc->sc_stats.ts_tx_tlt++; 3299 if (txstat & ATW_TXSTAT_TRT) 3300 sc->sc_stats.ts_tx_trt++; 3301 if (txstat & ATW_TXSTAT_TRO) 3302 sc->sc_stats.ts_tx_tro++; 3303 if (txstat & ATW_TXSTAT_SOFBR) { 3304 sc->sc_stats.ts_tx_sofbr++; 3305 } 3306 3307 if ((txstat & ATW_TXSTAT_ES) == 0) 3308 ifp->if_collisions += 3309 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3310 else 3311 ifp->if_oerrors++; 3312 3313 ifp->if_opackets++; 3314 } 3315 3316 /* 3317 * If there are no more pending transmissions, cancel the watchdog 3318 * timer. 3319 */ 3320 if (txs == NULL) { 3321 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3322 sc->sc_tx_timer = 0; 3323 } 3324 #undef TXSTAT_ERRMASK 3325 #undef TXSTAT_FMT 3326 } 3327 3328 /* 3329 * atw_watchdog: [ifnet interface function] 3330 * 3331 * Watchdog timer handler. 3332 */ 3333 void 3334 atw_watchdog(struct ifnet *ifp) 3335 { 3336 struct atw_softc *sc = ifp->if_softc; 3337 struct ieee80211com *ic = &sc->sc_ic; 3338 3339 ifp->if_timer = 0; 3340 if (ATW_IS_ENABLED(sc) == 0) 3341 return; 3342 3343 if (sc->sc_rescan_timer) { 3344 if (--sc->sc_rescan_timer == 0) 3345 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3346 } 3347 if (sc->sc_tx_timer) { 3348 if (--sc->sc_tx_timer == 0 && 3349 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3350 printf("%s: transmit timeout\n", ifp->if_xname); 3351 ifp->if_oerrors++; 3352 (void)atw_init(ifp); 3353 atw_start(ifp); 3354 } 3355 } 3356 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3357 ifp->if_timer = 1; 3358 ieee80211_watchdog(ic); 3359 } 3360 3361 #ifdef ATW_DEBUG 3362 static void 3363 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3364 { 3365 struct atw_softc *sc = ifp->if_softc; 3366 struct mbuf *m; 3367 int i, noctets = 0; 3368 3369 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3370 m0->m_pkthdr.len); 3371 3372 for (m = m0; m; m = m->m_next) { 3373 if (m->m_len == 0) 3374 continue; 3375 for (i = 0; i < m->m_len; i++) { 3376 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3377 if (++noctets % 24 == 0) 3378 printf("\n"); 3379 } 3380 } 3381 printf("%s%s: %d bytes emitted\n", 3382 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3383 } 3384 #endif /* ATW_DEBUG */ 3385 3386 /* 3387 * atw_start: [ifnet interface function] 3388 * 3389 * Start packet transmission on the interface. 3390 */ 3391 void 3392 atw_start(struct ifnet *ifp) 3393 { 3394 struct atw_softc *sc = ifp->if_softc; 3395 struct ieee80211_key *k; 3396 struct ieee80211com *ic = &sc->sc_ic; 3397 struct ieee80211_node *ni; 3398 struct ieee80211_frame_min *whm; 3399 struct ieee80211_frame *wh; 3400 struct atw_frame *hh; 3401 struct mbuf *m0, *m; 3402 struct atw_txsoft *txs, *last_txs; 3403 struct atw_txdesc *txd; 3404 int do_encrypt, npkt, rate; 3405 bus_dmamap_t dmamap; 3406 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3407 3408 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3409 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3410 3411 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3412 return; 3413 3414 /* 3415 * Remember the previous number of free descriptors and 3416 * the first descriptor we'll use. 3417 */ 3418 ofree = sc->sc_txfree; 3419 firsttx = sc->sc_txnext; 3420 3421 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3422 sc->sc_dev.dv_xname, ofree, firsttx)); 3423 3424 /* 3425 * Loop through the send queue, setting up transmit descriptors 3426 * until we drain the queue, or use up all available transmit 3427 * descriptors. 3428 */ 3429 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3430 sc->sc_txfree != 0) { 3431 3432 /* 3433 * Grab a packet off the management queue, if it 3434 * is not empty. Otherwise, from the data queue. 3435 */ 3436 IF_DEQUEUE(&ic->ic_mgtq, m0); 3437 if (m0 != NULL) { 3438 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3439 m0->m_pkthdr.rcvif = NULL; 3440 } else if (ic->ic_state != IEEE80211_S_RUN) 3441 break; /* send no data until associated */ 3442 else { 3443 IFQ_DEQUEUE(&ifp->if_snd, m0); 3444 if (m0 == NULL) 3445 break; 3446 #if NBPFILTER > 0 3447 if (ifp->if_bpf != NULL) 3448 bpf_mtap(ifp->if_bpf, m0); 3449 #endif /* NBPFILTER > 0 */ 3450 ni = ieee80211_find_txnode(ic, 3451 mtod(m0, struct ether_header *)->ether_dhost); 3452 if (ni == NULL) { 3453 ifp->if_oerrors++; 3454 break; 3455 } 3456 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3457 ieee80211_free_node(ni); 3458 ifp->if_oerrors++; 3459 break; 3460 } 3461 } 3462 3463 rate = MAX(ieee80211_get_rate(ic), 2); 3464 3465 whm = mtod(m0, struct ieee80211_frame_min *); 3466 3467 do_encrypt = ((whm->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3468 if (do_encrypt) 3469 k = &ic->ic_nw_keys[ic->ic_def_txkey]; 3470 else 3471 k = NULL; 3472 3473 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3474 ic->ic_flags, ic->ic_fragthreshold, rate, 3475 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3476 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3477 m_freem(m0); 3478 break; 3479 } 3480 3481 /* XXX Misleading if fragmentation is enabled. Better 3482 * to fragment in software? 3483 */ 3484 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3485 3486 #if NBPFILTER > 0 3487 /* 3488 * Pass the packet to any BPF listeners. 3489 */ 3490 if (ic->ic_rawbpf != NULL) 3491 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3492 3493 if (sc->sc_radiobpf != NULL) { 3494 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3495 3496 tap->at_rate = rate; 3497 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3498 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3499 3500 /* TBD tap->at_flags */ 3501 3502 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3503 tap->at_ihdr.it_len, m0); 3504 } 3505 #endif /* NBPFILTER > 0 */ 3506 3507 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3508 3509 if (ni != NULL) 3510 ieee80211_free_node(ni); 3511 3512 if (m0 == NULL) { 3513 ifp->if_oerrors++; 3514 break; 3515 } 3516 3517 /* just to make sure. */ 3518 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3519 3520 if (m0 == NULL) { 3521 ifp->if_oerrors++; 3522 break; 3523 } 3524 3525 hh = mtod(m0, struct atw_frame *); 3526 wh = &hh->atw_ihdr; 3527 3528 /* Copy everything we need from the 802.11 header: 3529 * Frame Control; address 1, address 3, or addresses 3530 * 3 and 4. NIC fills in BSSID, SA. 3531 */ 3532 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3533 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3534 panic("%s: illegal WDS frame", 3535 sc->sc_dev.dv_xname); 3536 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3537 } else 3538 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3539 3540 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3541 3542 /* initialize remaining Tx parameters */ 3543 memset(&hh->u, 0, sizeof(hh->u)); 3544 3545 hh->atw_rate = rate * 5; 3546 /* XXX this could be incorrect if M_FCS. _encap should 3547 * probably strip FCS just in case it sticks around in 3548 * bridged packets. 3549 */ 3550 hh->atw_service = 0x00; /* XXX guess */ 3551 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3552 sizeof(struct atw_frame)); 3553 3554 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3555 hh->atw_rtylmt = 3; 3556 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3557 if (do_encrypt) { 3558 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3559 hh->atw_keyid = ic->ic_def_txkey; 3560 } 3561 3562 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3563 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3564 if (txs->txs_d0.d_residue) 3565 hh->atw_head_plcplen |= htole16(0x8000); 3566 if (txs->txs_dn.d_residue) 3567 hh->atw_tail_plcplen |= htole16(0x8000); 3568 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3569 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3570 3571 /* never fragment multicast frames */ 3572 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3573 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3574 } else if (sc->sc_flags & ATWF_RTSCTS) { 3575 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3576 } 3577 3578 #ifdef ATW_DEBUG 3579 hh->atw_fragnum = 0; 3580 3581 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3582 printf("%s: dst = %s, rate = 0x%02x, " 3583 "service = 0x%02x, paylen = 0x%04x\n", 3584 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3585 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3586 3587 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3588 "dur1 = 0x%04x, dur2 = 0x%04x, " 3589 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3590 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3591 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3592 hh->atw_tail_dur, hh->atw_head_dur); 3593 3594 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3595 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3596 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3597 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3598 3599 printf("%s: keyid = %d\n", 3600 sc->sc_dev.dv_xname, hh->atw_keyid); 3601 3602 atw_dump_pkt(ifp, m0); 3603 } 3604 #endif /* ATW_DEBUG */ 3605 3606 dmamap = txs->txs_dmamap; 3607 3608 /* 3609 * Load the DMA map. Copy and try (once) again if the packet 3610 * didn't fit in the alloted number of segments. 3611 */ 3612 for (first = 1; 3613 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3614 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3615 first = 0) { 3616 MGETHDR(m, M_DONTWAIT, MT_DATA); 3617 if (m == NULL) { 3618 printf("%s: unable to allocate Tx mbuf\n", 3619 sc->sc_dev.dv_xname); 3620 break; 3621 } 3622 if (m0->m_pkthdr.len > MHLEN) { 3623 MCLGET(m, M_DONTWAIT); 3624 if ((m->m_flags & M_EXT) == 0) { 3625 printf("%s: unable to allocate Tx " 3626 "cluster\n", sc->sc_dev.dv_xname); 3627 m_freem(m); 3628 break; 3629 } 3630 } 3631 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3632 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3633 m_freem(m0); 3634 m0 = m; 3635 m = NULL; 3636 } 3637 if (error != 0) { 3638 printf("%s: unable to load Tx buffer, " 3639 "error = %d\n", sc->sc_dev.dv_xname, error); 3640 m_freem(m0); 3641 break; 3642 } 3643 3644 /* 3645 * Ensure we have enough descriptors free to describe 3646 * the packet. 3647 */ 3648 if (dmamap->dm_nsegs > sc->sc_txfree) { 3649 /* 3650 * Not enough free descriptors to transmit 3651 * this packet. Unload the DMA map and 3652 * drop the packet. Notify the upper layer 3653 * that there are no more slots left. 3654 * 3655 * XXX We could allocate an mbuf and copy, but 3656 * XXX it is worth it? 3657 */ 3658 bus_dmamap_unload(sc->sc_dmat, dmamap); 3659 m_freem(m0); 3660 break; 3661 } 3662 3663 /* 3664 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3665 */ 3666 3667 /* Sync the DMA map. */ 3668 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3669 BUS_DMASYNC_PREWRITE); 3670 3671 /* XXX arbitrary retry limit; 8 because I have seen it in 3672 * use already and maybe 0 means "no tries" ! 3673 */ 3674 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3675 3676 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3677 sc->sc_dev.dv_xname, rate * 5)); 3678 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3679 3680 /* 3681 * Initialize the transmit descriptors. 3682 */ 3683 for (nexttx = sc->sc_txnext, seg = 0; 3684 seg < dmamap->dm_nsegs; 3685 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3686 /* 3687 * If this is the first descriptor we're 3688 * enqueueing, don't set the OWN bit just 3689 * yet. That could cause a race condition. 3690 * We'll do it below. 3691 */ 3692 txd = &sc->sc_txdescs[nexttx]; 3693 txd->at_ctl = ctl | 3694 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3695 3696 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3697 txd->at_flags = 3698 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3699 ATW_TXFLAG_TBS1_MASK)) | 3700 ((nexttx == (ATW_NTXDESC - 1)) 3701 ? htole32(ATW_TXFLAG_TER) : 0); 3702 lasttx = nexttx; 3703 } 3704 3705 IASSERT(lasttx != -1, ("bad lastx")); 3706 /* Set `first segment' and `last segment' appropriately. */ 3707 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3708 htole32(ATW_TXFLAG_FS); 3709 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3710 3711 #ifdef ATW_DEBUG 3712 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3713 printf(" txsoft %p transmit chain:\n", txs); 3714 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3715 printf(" descriptor %d:\n", seg); 3716 printf(" at_ctl: 0x%08x\n", 3717 le32toh(sc->sc_txdescs[seg].at_ctl)); 3718 printf(" at_flags: 0x%08x\n", 3719 le32toh(sc->sc_txdescs[seg].at_flags)); 3720 printf(" at_buf1: 0x%08x\n", 3721 le32toh(sc->sc_txdescs[seg].at_buf1)); 3722 printf(" at_buf2: 0x%08x\n", 3723 le32toh(sc->sc_txdescs[seg].at_buf2)); 3724 if (seg == lasttx) 3725 break; 3726 } 3727 } 3728 #endif 3729 3730 /* Sync the descriptors we're using. */ 3731 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3732 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3733 3734 /* 3735 * Store a pointer to the packet so we can free it later, 3736 * and remember what txdirty will be once the packet is 3737 * done. 3738 */ 3739 txs->txs_mbuf = m0; 3740 txs->txs_firstdesc = sc->sc_txnext; 3741 txs->txs_lastdesc = lasttx; 3742 txs->txs_ndescs = dmamap->dm_nsegs; 3743 3744 /* Advance the tx pointer. */ 3745 sc->sc_txfree -= dmamap->dm_nsegs; 3746 sc->sc_txnext = nexttx; 3747 3748 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3749 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3750 3751 last_txs = txs; 3752 } 3753 3754 if (sc->sc_txfree != ofree) { 3755 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3756 sc->sc_dev.dv_xname, lasttx, firsttx)); 3757 /* 3758 * Cause a transmit interrupt to happen on the 3759 * last packet we enqueued. 3760 */ 3761 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3762 ATW_CDTXSYNC(sc, lasttx, 1, 3763 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3764 3765 /* 3766 * The entire packet chain is set up. Give the 3767 * first descriptor to the chip now. 3768 */ 3769 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3770 ATW_CDTXSYNC(sc, firsttx, 1, 3771 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3772 3773 /* Wake up the transmitter. */ 3774 ATW_WRITE(sc, ATW_TDR, 0x1); 3775 3776 if (txs == NULL || sc->sc_txfree == 0) 3777 ifp->if_flags |= IFF_OACTIVE; 3778 3779 /* Set a watchdog timer in case the chip flakes out. */ 3780 sc->sc_tx_timer = 5; 3781 ifp->if_timer = 1; 3782 } 3783 } 3784 3785 /* 3786 * atw_power: 3787 * 3788 * Power management (suspend/resume) hook. 3789 */ 3790 void 3791 atw_power(int why, void *arg) 3792 { 3793 struct atw_softc *sc = arg; 3794 struct ifnet *ifp = &sc->sc_if; 3795 int s; 3796 3797 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3798 3799 s = splnet(); 3800 switch (why) { 3801 case PWR_STANDBY: 3802 /* XXX do nothing. */ 3803 break; 3804 case PWR_SUSPEND: 3805 atw_stop(ifp, 0); 3806 if (sc->sc_power != NULL) 3807 (*sc->sc_power)(sc, why); 3808 break; 3809 case PWR_RESUME: 3810 if (ifp->if_flags & IFF_UP) { 3811 if (sc->sc_power != NULL) 3812 (*sc->sc_power)(sc, why); 3813 atw_init(ifp); 3814 } 3815 break; 3816 case PWR_SOFTSUSPEND: 3817 case PWR_SOFTSTANDBY: 3818 case PWR_SOFTRESUME: 3819 break; 3820 } 3821 splx(s); 3822 } 3823 3824 /* 3825 * atw_ioctl: [ifnet interface function] 3826 * 3827 * Handle control requests from the operator. 3828 */ 3829 int 3830 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3831 { 3832 struct atw_softc *sc = ifp->if_softc; 3833 struct ifreq *ifr = (struct ifreq *)data; 3834 int s, error = 0; 3835 3836 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3837 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3838 return ENXIO; 3839 3840 s = splnet(); 3841 3842 switch (cmd) { 3843 case SIOCSIFFLAGS: 3844 if (ifp->if_flags & IFF_UP) { 3845 if (ATW_IS_ENABLED(sc)) { 3846 /* 3847 * To avoid rescanning another access point, 3848 * do not call atw_init() here. Instead, 3849 * only reflect media settings. 3850 */ 3851 atw_filter_setup(sc); 3852 } else 3853 error = atw_init(ifp); 3854 } else if (ATW_IS_ENABLED(sc)) 3855 atw_stop(ifp, 1); 3856 break; 3857 case SIOCADDMULTI: 3858 case SIOCDELMULTI: 3859 error = (cmd == SIOCADDMULTI) ? 3860 ether_addmulti(ifr, &sc->sc_ec) : 3861 ether_delmulti(ifr, &sc->sc_ec); 3862 if (error == ENETRESET) { 3863 if (ifp->if_flags & IFF_RUNNING) 3864 atw_filter_setup(sc); /* do not rescan */ 3865 error = 0; 3866 } 3867 break; 3868 default: 3869 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3870 if (error == ENETRESET || error == ERESTART) { 3871 if (is_running(ifp)) 3872 error = atw_init(ifp); 3873 else 3874 error = 0; 3875 } 3876 break; 3877 } 3878 3879 /* Try to get more packets going. */ 3880 if (ATW_IS_ENABLED(sc)) 3881 atw_start(ifp); 3882 3883 splx(s); 3884 return (error); 3885 } 3886 3887 static int 3888 atw_media_change(struct ifnet *ifp) 3889 { 3890 int error; 3891 3892 error = ieee80211_media_change(ifp); 3893 if (error == ENETRESET) { 3894 if (is_running(ifp)) 3895 error = atw_init(ifp); 3896 else 3897 error = 0; 3898 } 3899 return error; 3900 } 3901
Indexes created Sat Sep 27 22:09:54 GMT 2025