atw.c revision 1.107
1 /* $NetBSD: atw.c,v 1.107 2006/02/18 22:12:01 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.107 2006/02/18 22:12:01 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 266 static void atw_filter_setup(struct atw_softc *); 267 268 /* 802.11 utilities */ 269 static uint64_t atw_get_tsft(struct atw_softc *); 270 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 271 uint32_t); 272 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 273 static void atw_node_free(struct ieee80211_node *); 274 275 /* 276 * Tuner/transceiver/modem 277 */ 278 static void atw_bbp_io_enable(struct atw_softc *, int); 279 280 /* RFMD RF3000 Baseband Processor */ 281 static int atw_rf3000_init(struct atw_softc *); 282 static int atw_rf3000_tune(struct atw_softc *, u_int); 283 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 284 285 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 286 static void atw_si4126_tune(struct atw_softc *, u_int); 287 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 288 289 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 290 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 291 292 const char *atw_tx_state[] = { 293 "STOPPED", 294 "RUNNING - read descriptor", 295 "RUNNING - transmitting", 296 "RUNNING - filling fifo", /* XXX */ 297 "SUSPENDED", 298 "RUNNING -- write descriptor", 299 "RUNNING -- write last descriptor", 300 "RUNNING - fifo full" 301 }; 302 303 const char *atw_rx_state[] = { 304 "STOPPED", 305 "RUNNING - read descriptor", 306 "RUNNING - check this packet, pre-fetch next", 307 "RUNNING - wait for reception", 308 "SUSPENDED", 309 "RUNNING - write descriptor", 310 "RUNNING - flush fifo", 311 "RUNNING - fifo drain" 312 }; 313 314 static inline int 315 is_running(struct ifnet *ifp) 316 { 317 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 318 } 319 320 int 321 atw_activate(struct device *self, enum devact act) 322 { 323 struct atw_softc *sc = (struct atw_softc *)self; 324 int rv = 0, s; 325 326 s = splnet(); 327 switch (act) { 328 case DVACT_ACTIVATE: 329 rv = EOPNOTSUPP; 330 break; 331 332 case DVACT_DEACTIVATE: 333 if_deactivate(&sc->sc_if); 334 break; 335 } 336 splx(s); 337 return rv; 338 } 339 340 /* 341 * atw_enable: 342 * 343 * Enable the ADM8211 chip. 344 */ 345 int 346 atw_enable(struct atw_softc *sc) 347 { 348 349 if (ATW_IS_ENABLED(sc) == 0) { 350 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 351 printf("%s: device enable failed\n", 352 sc->sc_dev.dv_xname); 353 return (EIO); 354 } 355 sc->sc_flags |= ATWF_ENABLED; 356 /* Power may have been removed, and WEP keys thus 357 * reset. 358 */ 359 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 360 } 361 return (0); 362 } 363 364 /* 365 * atw_disable: 366 * 367 * Disable the ADM8211 chip. 368 */ 369 void 370 atw_disable(struct atw_softc *sc) 371 { 372 if (!ATW_IS_ENABLED(sc)) 373 return; 374 if (sc->sc_disable != NULL) 375 (*sc->sc_disable)(sc); 376 sc->sc_flags &= ~ATWF_ENABLED; 377 } 378 379 /* Returns -1 on failure. */ 380 static int 381 atw_read_srom(struct atw_softc *sc) 382 { 383 struct seeprom_descriptor sd; 384 uint32_t test0, fail_bits; 385 386 (void)memset(&sd, 0, sizeof(sd)); 387 388 test0 = ATW_READ(sc, ATW_TEST0); 389 390 switch (sc->sc_rev) { 391 case ATW_REVISION_BA: 392 case ATW_REVISION_CA: 393 fail_bits = ATW_TEST0_EPNE; 394 break; 395 default: 396 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 397 break; 398 } 399 if ((test0 & fail_bits) != 0) { 400 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 401 return -1; 402 } 403 404 switch (test0 & ATW_TEST0_EPTYP_MASK) { 405 case ATW_TEST0_EPTYP_93c66: 406 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 407 sc->sc_sromsz = 512; 408 sd.sd_chip = C56_66; 409 break; 410 case ATW_TEST0_EPTYP_93c46: 411 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 412 sc->sc_sromsz = 128; 413 sd.sd_chip = C46; 414 break; 415 default: 416 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 417 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 418 return -1; 419 } 420 421 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 422 423 if (sc->sc_srom == NULL) { 424 printf("%s: unable to allocate SROM buffer\n", 425 sc->sc_dev.dv_xname); 426 return -1; 427 } 428 429 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 430 431 /* ADM8211 has a single 32-bit register for controlling the 432 * 93cx6 SROM. Bit SRS enables the serial port. There is no 433 * "ready" bit. The ADM8211 input/output sense is the reverse 434 * of read_seeprom's. 435 */ 436 sd.sd_tag = sc->sc_st; 437 sd.sd_bsh = sc->sc_sh; 438 sd.sd_regsize = 4; 439 sd.sd_control_offset = ATW_SPR; 440 sd.sd_status_offset = ATW_SPR; 441 sd.sd_dataout_offset = ATW_SPR; 442 sd.sd_CK = ATW_SPR_SCLK; 443 sd.sd_CS = ATW_SPR_SCS; 444 sd.sd_DI = ATW_SPR_SDO; 445 sd.sd_DO = ATW_SPR_SDI; 446 sd.sd_MS = ATW_SPR_SRS; 447 sd.sd_RDY = 0; 448 449 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 450 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 451 free(sc->sc_srom, M_DEVBUF); 452 return -1; 453 } 454 #ifdef ATW_DEBUG 455 { 456 int i; 457 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 458 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 459 if (((i % 8) == 0) && (i != 0)) { 460 ATW_DPRINTF(("\n\t")); 461 } 462 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 463 } 464 ATW_DPRINTF(("\n")); 465 } 466 #endif /* ATW_DEBUG */ 467 return 0; 468 } 469 470 #ifdef ATW_DEBUG 471 static void 472 atw_print_regs(struct atw_softc *sc, const char *where) 473 { 474 #define PRINTREG(sc, reg) \ 475 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 476 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 477 478 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 479 480 PRINTREG(sc, ATW_PAR); 481 PRINTREG(sc, ATW_FRCTL); 482 PRINTREG(sc, ATW_TDR); 483 PRINTREG(sc, ATW_WTDP); 484 PRINTREG(sc, ATW_RDR); 485 PRINTREG(sc, ATW_WRDP); 486 PRINTREG(sc, ATW_RDB); 487 PRINTREG(sc, ATW_CSR3A); 488 PRINTREG(sc, ATW_TDBD); 489 PRINTREG(sc, ATW_TDBP); 490 PRINTREG(sc, ATW_STSR); 491 PRINTREG(sc, ATW_CSR5A); 492 PRINTREG(sc, ATW_NAR); 493 PRINTREG(sc, ATW_CSR6A); 494 PRINTREG(sc, ATW_IER); 495 PRINTREG(sc, ATW_CSR7A); 496 PRINTREG(sc, ATW_LPC); 497 PRINTREG(sc, ATW_TEST1); 498 PRINTREG(sc, ATW_SPR); 499 PRINTREG(sc, ATW_TEST0); 500 PRINTREG(sc, ATW_WCSR); 501 PRINTREG(sc, ATW_WPDR); 502 PRINTREG(sc, ATW_GPTMR); 503 PRINTREG(sc, ATW_GPIO); 504 PRINTREG(sc, ATW_BBPCTL); 505 PRINTREG(sc, ATW_SYNCTL); 506 PRINTREG(sc, ATW_PLCPHD); 507 PRINTREG(sc, ATW_MMIWADDR); 508 PRINTREG(sc, ATW_MMIRADDR1); 509 PRINTREG(sc, ATW_MMIRADDR2); 510 PRINTREG(sc, ATW_TXBR); 511 PRINTREG(sc, ATW_CSR15A); 512 PRINTREG(sc, ATW_ALCSTAT); 513 PRINTREG(sc, ATW_TOFS2); 514 PRINTREG(sc, ATW_CMDR); 515 PRINTREG(sc, ATW_PCIC); 516 PRINTREG(sc, ATW_PMCSR); 517 PRINTREG(sc, ATW_PAR0); 518 PRINTREG(sc, ATW_PAR1); 519 PRINTREG(sc, ATW_MAR0); 520 PRINTREG(sc, ATW_MAR1); 521 PRINTREG(sc, ATW_ATIMDA0); 522 PRINTREG(sc, ATW_ABDA1); 523 PRINTREG(sc, ATW_BSSID0); 524 PRINTREG(sc, ATW_TXLMT); 525 PRINTREG(sc, ATW_MIBCNT); 526 PRINTREG(sc, ATW_BCNT); 527 PRINTREG(sc, ATW_TSFTH); 528 PRINTREG(sc, ATW_TSC); 529 PRINTREG(sc, ATW_SYNRF); 530 PRINTREG(sc, ATW_BPLI); 531 PRINTREG(sc, ATW_CAP0); 532 PRINTREG(sc, ATW_CAP1); 533 PRINTREG(sc, ATW_RMD); 534 PRINTREG(sc, ATW_CFPP); 535 PRINTREG(sc, ATW_TOFS0); 536 PRINTREG(sc, ATW_TOFS1); 537 PRINTREG(sc, ATW_IFST); 538 PRINTREG(sc, ATW_RSPT); 539 PRINTREG(sc, ATW_TSFTL); 540 PRINTREG(sc, ATW_WEPCTL); 541 PRINTREG(sc, ATW_WESK); 542 PRINTREG(sc, ATW_WEPCNT); 543 PRINTREG(sc, ATW_MACTEST); 544 PRINTREG(sc, ATW_FER); 545 PRINTREG(sc, ATW_FEMR); 546 PRINTREG(sc, ATW_FPSR); 547 PRINTREG(sc, ATW_FFER); 548 #undef PRINTREG 549 } 550 #endif /* ATW_DEBUG */ 551 552 /* 553 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 554 */ 555 void 556 atw_attach(struct atw_softc *sc) 557 { 558 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 560 }; 561 struct ieee80211com *ic = &sc->sc_ic; 562 struct ifnet *ifp = &sc->sc_if; 563 int country_code, error, i, nrate, srom_major; 564 u_int32_t reg; 565 static const char *type_strings[] = {"Intersil (not supported)", 566 "RFMD", "Marvel (not supported)"}; 567 568 sc->sc_txth = atw_txthresh_tab_lo; 569 570 SIMPLEQ_INIT(&sc->sc_txfreeq); 571 SIMPLEQ_INIT(&sc->sc_txdirtyq); 572 573 #ifdef ATW_DEBUG 574 atw_print_regs(sc, "atw_attach"); 575 #endif /* ATW_DEBUG */ 576 577 /* 578 * Allocate the control data structures, and create and load the 579 * DMA map for it. 580 */ 581 if ((error = bus_dmamem_alloc(sc->sc_dmat, 582 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 583 1, &sc->sc_cdnseg, 0)) != 0) { 584 printf("%s: unable to allocate control data, error = %d\n", 585 sc->sc_dev.dv_xname, error); 586 goto fail_0; 587 } 588 589 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 590 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 591 BUS_DMA_COHERENT)) != 0) { 592 printf("%s: unable to map control data, error = %d\n", 593 sc->sc_dev.dv_xname, error); 594 goto fail_1; 595 } 596 597 if ((error = bus_dmamap_create(sc->sc_dmat, 598 sizeof(struct atw_control_data), 1, 599 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 600 printf("%s: unable to create control data DMA map, " 601 "error = %d\n", sc->sc_dev.dv_xname, error); 602 goto fail_2; 603 } 604 605 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 606 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 607 0)) != 0) { 608 printf("%s: unable to load control data DMA map, error = %d\n", 609 sc->sc_dev.dv_xname, error); 610 goto fail_3; 611 } 612 613 /* 614 * Create the transmit buffer DMA maps. 615 */ 616 sc->sc_ntxsegs = ATW_NTXSEGS; 617 for (i = 0; i < ATW_TXQUEUELEN; i++) { 618 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 619 sc->sc_ntxsegs, MCLBYTES, 0, 0, 620 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 621 printf("%s: unable to create tx DMA map %d, " 622 "error = %d\n", sc->sc_dev.dv_xname, i, error); 623 goto fail_4; 624 } 625 } 626 627 /* 628 * Create the receive buffer DMA maps. 629 */ 630 for (i = 0; i < ATW_NRXDESC; i++) { 631 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 632 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 633 printf("%s: unable to create rx DMA map %d, " 634 "error = %d\n", sc->sc_dev.dv_xname, i, error); 635 goto fail_5; 636 } 637 } 638 for (i = 0; i < ATW_NRXDESC; i++) { 639 sc->sc_rxsoft[i].rxs_mbuf = NULL; 640 } 641 642 switch (sc->sc_rev) { 643 case ATW_REVISION_AB: 644 case ATW_REVISION_AF: 645 sc->sc_sramlen = ATW_SRAM_A_SIZE; 646 break; 647 case ATW_REVISION_BA: 648 case ATW_REVISION_CA: 649 sc->sc_sramlen = ATW_SRAM_B_SIZE; 650 break; 651 } 652 653 /* Reset the chip to a known state. */ 654 atw_reset(sc); 655 656 if (atw_read_srom(sc) == -1) 657 return; 658 659 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 660 ATW_SR_RFTYPE_MASK); 661 662 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 663 ATW_SR_BBPTYPE_MASK); 664 665 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 666 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 667 return; 668 } 669 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 670 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 671 return; 672 } 673 674 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 675 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 676 677 /* XXX There exists a Linux driver which seems to use RFType = 0 for 678 * MARVEL. My bug, or theirs? 679 */ 680 681 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 682 683 switch (sc->sc_rftype) { 684 case ATW_RFTYPE_INTERSIL: 685 reg |= ATW_SYNCTL_CS1; 686 break; 687 case ATW_RFTYPE_RFMD: 688 reg |= ATW_SYNCTL_CS0; 689 break; 690 case ATW_RFTYPE_MARVEL: 691 break; 692 } 693 694 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 695 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 696 697 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 698 699 switch (sc->sc_bbptype) { 700 case ATW_BBPTYPE_INTERSIL: 701 reg |= ATW_BBPCTL_TWI; 702 break; 703 case ATW_BBPTYPE_RFMD: 704 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 705 ATW_BBPCTL_CCA_ACTLO; 706 break; 707 case ATW_BBPTYPE_MARVEL: 708 break; 709 case ATW_C_BBPTYPE_RFMD: 710 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 711 sc->sc_dev.dv_xname); 712 break; 713 } 714 715 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 716 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 717 718 /* 719 * From this point forward, the attachment cannot fail. A failure 720 * before this point releases all resources that may have been 721 * allocated. 722 */ 723 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 724 725 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 726 htole16(sc->sc_srom[ATW_SR_MAC00]), 727 htole16(sc->sc_srom[ATW_SR_MAC01]), 728 htole16(sc->sc_srom[ATW_SR_MAC10]))); 729 730 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 731 ATW_SR_MAJOR_MASK); 732 733 if (srom_major < 2) 734 sc->sc_rf3000_options1 = 0; 735 else if (sc->sc_rev == ATW_REVISION_BA) { 736 sc->sc_rf3000_options1 = 737 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 738 ATW_SR_CR28_MASK); 739 } else 740 sc->sc_rf3000_options1 = 0; 741 742 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 743 ATW_SR_CR29_MASK); 744 745 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 746 ATW_SR_CTRY_MASK); 747 748 #define ADD_CHANNEL(_ic, _chan) do { \ 749 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 750 _ic->ic_channels[_chan].ic_freq = \ 751 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 752 } while (0) 753 754 /* Find available channels */ 755 switch (country_code) { 756 case COUNTRY_MMK2: /* 1-14 */ 757 ADD_CHANNEL(ic, 14); 758 /*FALLTHROUGH*/ 759 case COUNTRY_ETSI: /* 1-13 */ 760 for (i = 1; i <= 13; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 case COUNTRY_FCC: /* 1-11 */ 764 case COUNTRY_IC: /* 1-11 */ 765 for (i = 1; i <= 11; i++) 766 ADD_CHANNEL(ic, i); 767 break; 768 case COUNTRY_MMK: /* 14 */ 769 ADD_CHANNEL(ic, 14); 770 break; 771 case COUNTRY_FRANCE: /* 10-13 */ 772 for (i = 10; i <= 13; i++) 773 ADD_CHANNEL(ic, i); 774 break; 775 default: /* assume channels 10-11 */ 776 case COUNTRY_SPAIN: /* 10-11 */ 777 for (i = 10; i <= 11; i++) 778 ADD_CHANNEL(ic, i); 779 break; 780 } 781 782 /* Read the MAC address. */ 783 reg = ATW_READ(sc, ATW_PAR0); 784 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 785 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 786 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 787 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 788 reg = ATW_READ(sc, ATW_PAR1); 789 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 790 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 791 792 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 793 printf(" could not get mac address, attach failed\n"); 794 return; 795 } 796 797 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 798 799 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 800 ifp->if_softc = sc; 801 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 802 IFF_NOTRAILERS; 803 ifp->if_ioctl = atw_ioctl; 804 ifp->if_start = atw_start; 805 ifp->if_watchdog = atw_watchdog; 806 ifp->if_init = atw_init; 807 ifp->if_stop = atw_stop; 808 IFQ_SET_READY(&ifp->if_snd); 809 810 ic->ic_ifp = ifp; 811 ic->ic_phytype = IEEE80211_T_DS; 812 ic->ic_opmode = IEEE80211_M_STA; 813 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 814 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 815 816 nrate = 0; 817 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 822 823 /* 824 * Call MI attach routines. 825 */ 826 827 if_attach(ifp); 828 ieee80211_ifattach(ic); 829 830 sc->sc_newstate = ic->ic_newstate; 831 ic->ic_newstate = atw_newstate; 832 833 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 834 ic->ic_recv_mgmt = atw_recv_mgmt; 835 836 sc->sc_node_free = ic->ic_node_free; 837 ic->ic_node_free = atw_node_free; 838 839 sc->sc_node_alloc = ic->ic_node_alloc; 840 ic->ic_node_alloc = atw_node_alloc; 841 842 ic->ic_crypto.cs_key_delete = atw_key_delete; 843 ic->ic_crypto.cs_key_set = atw_key_set; 844 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 845 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 846 847 /* possibly we should fill in our own sc_send_prresp, since 848 * the ADM8211 is probably sending probe responses in ad hoc 849 * mode. 850 */ 851 852 /* complete initialization */ 853 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 854 callout_init(&sc->sc_scan_ch); 855 856 #if NBPFILTER > 0 857 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 858 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 859 #endif 860 861 /* 862 * Make sure the interface is shutdown during reboot. 863 */ 864 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 865 if (sc->sc_sdhook == NULL) 866 printf("%s: WARNING: unable to establish shutdown hook\n", 867 sc->sc_dev.dv_xname); 868 869 /* 870 * Add a suspend hook to make sure we come back up after a 871 * resume. 872 */ 873 sc->sc_powerhook = powerhook_establish(atw_power, sc); 874 if (sc->sc_powerhook == NULL) 875 printf("%s: WARNING: unable to establish power hook\n", 876 sc->sc_dev.dv_xname); 877 878 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 879 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 880 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 881 882 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 883 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 884 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 885 886 ieee80211_announce(ic); 887 return; 888 889 /* 890 * Free any resources we've allocated during the failed attach 891 * attempt. Do this in reverse order and fall through. 892 */ 893 fail_5: 894 for (i = 0; i < ATW_NRXDESC; i++) { 895 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 896 continue; 897 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 898 } 899 fail_4: 900 for (i = 0; i < ATW_TXQUEUELEN; i++) { 901 if (sc->sc_txsoft[i].txs_dmamap == NULL) 902 continue; 903 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 904 } 905 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 906 fail_3: 907 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 908 fail_2: 909 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 910 sizeof(struct atw_control_data)); 911 fail_1: 912 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 913 fail_0: 914 return; 915 } 916 917 static struct ieee80211_node * 918 atw_node_alloc(struct ieee80211_node_table *nt) 919 { 920 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 921 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 922 923 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 924 return ni; 925 } 926 927 static void 928 atw_node_free(struct ieee80211_node *ni) 929 { 930 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 931 932 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 933 ether_sprintf(ni->ni_bssid))); 934 (*sc->sc_node_free)(ni); 935 } 936 937 938 static void 939 atw_test1_reset(struct atw_softc *sc) 940 { 941 switch (sc->sc_rev) { 942 case ATW_REVISION_BA: 943 if (1 /* XXX condition on transceiver type */) { 944 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 945 } 946 break; 947 case ATW_REVISION_CA: 948 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 949 break; 950 default: 951 break; 952 } 953 } 954 955 /* 956 * atw_reset: 957 * 958 * Perform a soft reset on the ADM8211. 959 */ 960 void 961 atw_reset(struct atw_softc *sc) 962 { 963 int i; 964 uint32_t lpc; 965 966 ATW_WRITE(sc, ATW_NAR, 0x0); 967 DELAY(atw_nar_delay); 968 969 /* Reference driver has a cryptic remark indicating that this might 970 * power-on the chip. I know that it turns off power-saving.... 971 */ 972 ATW_WRITE(sc, ATW_FRCTL, 0x0); 973 974 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 975 976 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 977 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 978 break; 979 DELAY(atw_pseudo_milli); 980 } 981 982 /* ... and then pause 100ms longer for good measure. */ 983 DELAY(atw_magic_delay1); 984 985 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 986 987 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 988 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 989 990 /* 991 * Initialize the PCI Access Register. 992 */ 993 sc->sc_busmode = ATW_PAR_PBL_8DW; 994 995 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 996 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 997 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 998 999 atw_test1_reset(sc); 1000 1001 /* Turn off maximum power saving, etc. */ 1002 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1003 1004 DELAY(atw_magic_delay2); 1005 1006 /* Recall EEPROM. */ 1007 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1008 1009 DELAY(atw_magic_delay4); 1010 1011 lpc = ATW_READ(sc, ATW_LPC); 1012 1013 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1014 1015 /* A reset seems to affect the SRAM contents, so put them into 1016 * a known state. 1017 */ 1018 atw_clear_sram(sc); 1019 1020 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1021 } 1022 1023 static void 1024 atw_clear_sram(struct atw_softc *sc) 1025 { 1026 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1027 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1028 /* XXX not for revision 0x20. */ 1029 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1030 } 1031 1032 /* TBD atw_init 1033 * 1034 * set MAC based on ic->ic_bss->myaddr 1035 * write WEP keys 1036 * set TX rate 1037 */ 1038 1039 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1040 * without receiving a beacon with the preferred BSSID & SSID. 1041 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1042 */ 1043 static void 1044 atw_wcsr_init(struct atw_softc *sc) 1045 { 1046 uint32_t wcsr; 1047 1048 wcsr = ATW_READ(sc, ATW_WCSR); 1049 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1050 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1051 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1052 1053 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1054 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1055 } 1056 1057 /* Turn off power management. Set Rx store-and-forward mode. */ 1058 static void 1059 atw_cmdr_init(struct atw_softc *sc) 1060 { 1061 uint32_t cmdr; 1062 cmdr = ATW_READ(sc, ATW_CMDR); 1063 cmdr &= ~ATW_CMDR_APM; 1064 cmdr |= ATW_CMDR_RTE; 1065 cmdr &= ~ATW_CMDR_DRT_MASK; 1066 cmdr |= ATW_CMDR_DRT_SF; 1067 1068 ATW_WRITE(sc, ATW_CMDR, cmdr); 1069 } 1070 1071 static void 1072 atw_tofs2_init(struct atw_softc *sc) 1073 { 1074 uint32_t tofs2; 1075 /* XXX this magic can probably be figured out from the RFMD docs */ 1076 #ifndef ATW_REFSLAVE 1077 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1078 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1079 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1080 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1081 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1082 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1083 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1084 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1085 #else 1086 /* XXX new magic from reference driver source */ 1087 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1088 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1089 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1090 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1091 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1092 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1093 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1094 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1095 #endif 1096 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1097 } 1098 1099 static void 1100 atw_nar_init(struct atw_softc *sc) 1101 { 1102 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1103 } 1104 1105 static void 1106 atw_txlmt_init(struct atw_softc *sc) 1107 { 1108 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1109 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1110 } 1111 1112 static void 1113 atw_test1_init(struct atw_softc *sc) 1114 { 1115 uint32_t test1; 1116 1117 test1 = ATW_READ(sc, ATW_TEST1); 1118 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1119 /* XXX magic 0x1 */ 1120 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1121 ATW_WRITE(sc, ATW_TEST1, test1); 1122 } 1123 1124 static void 1125 atw_rf_reset(struct atw_softc *sc) 1126 { 1127 /* XXX this resets an Intersil RF front-end? */ 1128 /* TBD condition on Intersil RFType? */ 1129 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1130 DELAY(atw_rf_delay1); 1131 ATW_WRITE(sc, ATW_SYNRF, 0); 1132 DELAY(atw_rf_delay2); 1133 } 1134 1135 /* Set 16 TU max duration for the contention-free period (CFP). */ 1136 static void 1137 atw_cfp_init(struct atw_softc *sc) 1138 { 1139 uint32_t cfpp; 1140 1141 cfpp = ATW_READ(sc, ATW_CFPP); 1142 cfpp &= ~ATW_CFPP_CFPMD; 1143 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1144 ATW_WRITE(sc, ATW_CFPP, cfpp); 1145 } 1146 1147 static void 1148 atw_tofs0_init(struct atw_softc *sc) 1149 { 1150 /* XXX I guess that the Cardbus clock is 22MHz? 1151 * I am assuming that the role of ATW_TOFS0_USCNT is 1152 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1153 * very clear on this point. It says in the datasheet that it is 1154 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1155 * and 33MHz; maybe this is the way? I see a binary-only driver write 1156 * these values. These values are also the power-on default. 1157 */ 1158 ATW_WRITE(sc, ATW_TOFS0, 1159 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1160 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1161 } 1162 1163 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1164 static void 1165 atw_ifs_init(struct atw_softc *sc) 1166 { 1167 uint32_t ifst; 1168 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1169 * Go figure. 1170 */ 1171 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1172 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1173 ATW_IFST_SIFS_MASK) | 1174 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1175 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1176 1177 ATW_WRITE(sc, ATW_IFST, ifst); 1178 } 1179 1180 static void 1181 atw_response_times_init(struct atw_softc *sc) 1182 { 1183 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1184 * indicate that the MAC expects at least SIFS + MIRT microseconds 1185 * to pass after it transmits a frame that requires a response; 1186 * it waits at most SIFS + MART microseconds for the response. 1187 * Surely this is not the ACK timeout? 1188 */ 1189 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1190 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1191 } 1192 1193 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1194 * engines read and write baseband registers after Rx and before 1195 * Tx, respectively. 1196 */ 1197 static void 1198 atw_bbp_io_init(struct atw_softc *sc) 1199 { 1200 uint32_t mmiraddr2; 1201 1202 /* XXX The reference driver does this, but is it *really* 1203 * necessary? 1204 */ 1205 switch (sc->sc_rev) { 1206 case ATW_REVISION_AB: 1207 case ATW_REVISION_AF: 1208 mmiraddr2 = 0x0; 1209 break; 1210 default: 1211 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1212 mmiraddr2 &= 1213 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1214 break; 1215 } 1216 1217 switch (sc->sc_bbptype) { 1218 case ATW_BBPTYPE_INTERSIL: 1219 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1220 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1221 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1222 break; 1223 case ATW_BBPTYPE_MARVEL: 1224 /* TBD find out the Marvel settings. */ 1225 break; 1226 case ATW_BBPTYPE_RFMD: 1227 default: 1228 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1229 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1230 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1231 break; 1232 } 1233 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1234 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1235 } 1236 1237 /* 1238 * atw_init: [ ifnet interface function ] 1239 * 1240 * Initialize the interface. Must be called at splnet(). 1241 */ 1242 int 1243 atw_init(struct ifnet *ifp) 1244 { 1245 struct atw_softc *sc = ifp->if_softc; 1246 struct ieee80211com *ic = &sc->sc_ic; 1247 struct atw_txsoft *txs; 1248 struct atw_rxsoft *rxs; 1249 int i, error = 0; 1250 1251 if ((error = atw_enable(sc)) != 0) 1252 goto out; 1253 1254 /* 1255 * Cancel any pending I/O. This also resets. 1256 */ 1257 atw_stop(ifp, 0); 1258 1259 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1260 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1261 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1262 1263 atw_wcsr_init(sc); 1264 1265 atw_cmdr_init(sc); 1266 1267 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1268 * 1269 * XXX Set transmit power for ATIM, RTS, Beacon. 1270 */ 1271 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1272 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1273 1274 atw_tofs2_init(sc); 1275 1276 atw_nar_init(sc); 1277 1278 atw_txlmt_init(sc); 1279 1280 atw_test1_init(sc); 1281 1282 atw_rf_reset(sc); 1283 1284 atw_cfp_init(sc); 1285 1286 atw_tofs0_init(sc); 1287 1288 atw_ifs_init(sc); 1289 1290 /* XXX Fall asleep after one second of inactivity. 1291 * XXX A frame may only dribble in for 65536us. 1292 */ 1293 ATW_WRITE(sc, ATW_RMD, 1294 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1295 1296 atw_response_times_init(sc); 1297 1298 atw_bbp_io_init(sc); 1299 1300 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1301 1302 if ((error = atw_rf3000_init(sc)) != 0) 1303 goto out; 1304 1305 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1306 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1307 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1308 1309 /* 1310 * Initialize the transmit descriptor ring. 1311 */ 1312 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1313 for (i = 0; i < ATW_NTXDESC; i++) { 1314 sc->sc_txdescs[i].at_ctl = 0; 1315 /* no transmit chaining */ 1316 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1317 sc->sc_txdescs[i].at_buf2 = 1318 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1319 } 1320 /* use ring mode */ 1321 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1322 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1323 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1324 sc->sc_txfree = ATW_NTXDESC; 1325 sc->sc_txnext = 0; 1326 1327 /* 1328 * Initialize the transmit job descriptors. 1329 */ 1330 SIMPLEQ_INIT(&sc->sc_txfreeq); 1331 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1332 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1333 txs = &sc->sc_txsoft[i]; 1334 txs->txs_mbuf = NULL; 1335 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1336 } 1337 1338 /* 1339 * Initialize the receive descriptor and receive job 1340 * descriptor rings. 1341 */ 1342 for (i = 0; i < ATW_NRXDESC; i++) { 1343 rxs = &sc->sc_rxsoft[i]; 1344 if (rxs->rxs_mbuf == NULL) { 1345 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1346 printf("%s: unable to allocate or map rx " 1347 "buffer %d, error = %d\n", 1348 sc->sc_dev.dv_xname, i, error); 1349 /* 1350 * XXX Should attempt to run with fewer receive 1351 * XXX buffers instead of just failing. 1352 */ 1353 atw_rxdrain(sc); 1354 goto out; 1355 } 1356 } else 1357 ATW_INIT_RXDESC(sc, i); 1358 } 1359 sc->sc_rxptr = 0; 1360 1361 /* 1362 * Initialize the interrupt mask and enable interrupts. 1363 */ 1364 /* normal interrupts */ 1365 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1366 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1367 1368 /* abnormal interrupts */ 1369 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1370 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1371 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1372 1373 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1374 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1375 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1376 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1377 ATW_INTR_TRT; 1378 1379 sc->sc_linkint_mask &= sc->sc_inten; 1380 sc->sc_rxint_mask &= sc->sc_inten; 1381 sc->sc_txint_mask &= sc->sc_inten; 1382 1383 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1384 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1385 1386 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1387 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1388 1389 /* 1390 * Give the transmit and receive rings to the ADM8211. 1391 */ 1392 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1393 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1394 1395 sc->sc_txthresh = 0; 1396 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1397 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1398 1399 /* common 802.11 configuration */ 1400 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1401 switch (ic->ic_opmode) { 1402 case IEEE80211_M_STA: 1403 break; 1404 case IEEE80211_M_AHDEMO: /* XXX */ 1405 case IEEE80211_M_IBSS: 1406 ic->ic_flags |= IEEE80211_F_IBSSON; 1407 /*FALLTHROUGH*/ 1408 case IEEE80211_M_HOSTAP: /* XXX */ 1409 break; 1410 case IEEE80211_M_MONITOR: /* XXX */ 1411 break; 1412 } 1413 1414 switch (ic->ic_opmode) { 1415 case IEEE80211_M_AHDEMO: 1416 case IEEE80211_M_HOSTAP: 1417 #ifndef IEEE80211_NO_HOSTAP 1418 ic->ic_bss->ni_intval = ic->ic_lintval; 1419 ic->ic_bss->ni_rssi = 0; 1420 ic->ic_bss->ni_rstamp = 0; 1421 #endif /* !IEEE80211_NO_HOSTAP */ 1422 break; 1423 default: /* XXX */ 1424 break; 1425 } 1426 1427 sc->sc_wepctl = 0; 1428 1429 atw_write_ssid(sc); 1430 atw_write_sup_rates(sc); 1431 atw_write_wep(sc); 1432 1433 ic->ic_state = IEEE80211_S_INIT; 1434 1435 /* 1436 * Set the receive filter. This will start the transmit and 1437 * receive processes. 1438 */ 1439 atw_filter_setup(sc); 1440 1441 /* 1442 * Start the receive process. 1443 */ 1444 ATW_WRITE(sc, ATW_RDR, 0x1); 1445 1446 /* 1447 * Note that the interface is now running. 1448 */ 1449 ifp->if_flags |= IFF_RUNNING; 1450 ifp->if_flags &= ~IFF_OACTIVE; 1451 1452 /* send no beacons, yet. */ 1453 atw_start_beacon(sc, 0); 1454 1455 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1456 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1457 else 1458 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1459 out: 1460 if (error) { 1461 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1462 sc->sc_tx_timer = 0; 1463 ifp->if_timer = 0; 1464 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1465 } 1466 #ifdef ATW_DEBUG 1467 atw_print_regs(sc, "end of init"); 1468 #endif /* ATW_DEBUG */ 1469 1470 return (error); 1471 } 1472 1473 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1474 * 0: MAC control of RF3000/Si4126. 1475 * 1476 * Applies power, or selects RF front-end? Sets reset condition. 1477 * 1478 * TBD support non-RFMD BBP, non-SiLabs synth. 1479 */ 1480 static void 1481 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1482 { 1483 if (enable) { 1484 ATW_WRITE(sc, ATW_SYNRF, 1485 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1486 DELAY(atw_bbp_io_enable_delay); 1487 } else { 1488 ATW_WRITE(sc, ATW_SYNRF, 0); 1489 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1490 } 1491 } 1492 1493 static int 1494 atw_tune(struct atw_softc *sc) 1495 { 1496 int rc; 1497 u_int chan; 1498 struct ieee80211com *ic = &sc->sc_ic; 1499 1500 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1501 if (chan == IEEE80211_CHAN_ANY) 1502 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1503 1504 if (chan == sc->sc_cur_chan) 1505 return 0; 1506 1507 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1508 sc->sc_cur_chan, chan)); 1509 1510 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1511 1512 atw_si4126_tune(sc, chan); 1513 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1514 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1515 chan); 1516 1517 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1518 DELAY(atw_nar_delay); 1519 ATW_WRITE(sc, ATW_RDR, 0x1); 1520 1521 if (rc == 0) 1522 sc->sc_cur_chan = chan; 1523 1524 return rc; 1525 } 1526 1527 #ifdef ATW_SYNDEBUG 1528 static void 1529 atw_si4126_print(struct atw_softc *sc) 1530 { 1531 struct ifnet *ifp = &sc->sc_if; 1532 u_int addr, val; 1533 1534 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1535 return; 1536 1537 for (addr = 0; addr <= 8; addr++) { 1538 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1539 if (atw_si4126_read(sc, addr, &val) == 0) { 1540 printf("<unknown> (quitting print-out)\n"); 1541 break; 1542 } 1543 printf("%05x\n", val); 1544 } 1545 } 1546 #endif /* ATW_SYNDEBUG */ 1547 1548 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1549 * 1550 * The RF/IF synthesizer produces two reference frequencies for 1551 * the RF2948B transceiver. The first frequency the RF2948B requires 1552 * is two times the so-called "intermediate frequency" (IF). Since 1553 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1554 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1555 * frequency required by the transceiver is the radio frequency 1556 * (RF). This is a superheterodyne transceiver; for f(chan) the 1557 * center frequency of the channel we are tuning, RF = f(chan) - 1558 * IF. 1559 * 1560 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1561 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1562 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1563 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1564 */ 1565 static void 1566 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1567 { 1568 u_int mhz; 1569 u_int R; 1570 u_int32_t gpio; 1571 u_int16_t gain; 1572 1573 #ifdef ATW_SYNDEBUG 1574 atw_si4126_print(sc); 1575 #endif /* ATW_SYNDEBUG */ 1576 1577 if (chan == 14) 1578 mhz = 2484; 1579 else 1580 mhz = 2412 + 5 * (chan - 1); 1581 1582 /* Tune IF to 748MHz to suit the IF LO input of the 1583 * RF2494B, which is 2 x IF. No need to set an IF divider 1584 * because an IF in 526MHz - 952MHz is allowed. 1585 * 1586 * XIN is 44.000MHz, so divide it by two to get allowable 1587 * range of 2-25MHz. SiLabs tells me that this is not 1588 * strictly necessary. 1589 */ 1590 1591 if (atw_xindiv2) 1592 R = 44; 1593 else 1594 R = 88; 1595 1596 /* Power-up RF, IF synthesizers. */ 1597 atw_si4126_write(sc, SI4126_POWER, 1598 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1599 1600 /* set LPWR, too? */ 1601 atw_si4126_write(sc, SI4126_MAIN, 1602 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1603 1604 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1605 * set KP2 to 1. 1606 * 1607 * REFDIF This is different from the reference driver, which 1608 * always sets SI4126_GAIN to 0. 1609 */ 1610 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1611 1612 atw_si4126_write(sc, SI4126_GAIN, gain); 1613 1614 /* XIN = 44MHz. 1615 * 1616 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1617 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1618 * 1619 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1620 * so that 1496/88 * 44MHz = 748MHz. 1621 */ 1622 atw_si4126_write(sc, SI4126_IFN, 1496); 1623 1624 atw_si4126_write(sc, SI4126_IFR, R); 1625 1626 #ifndef ATW_REFSLAVE 1627 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1628 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1629 * which has no RF1! 1630 */ 1631 atw_si4126_write(sc, SI4126_RF1R, R); 1632 1633 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1634 #endif 1635 1636 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1637 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1638 * Now let's multiply it to mhz. So mhz - IF = N. 1639 */ 1640 atw_si4126_write(sc, SI4126_RF2R, R); 1641 1642 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1643 1644 /* wait 100us from power-up for RF, IF to settle */ 1645 DELAY(100); 1646 1647 gpio = ATW_READ(sc, ATW_GPIO); 1648 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1649 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1650 1651 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1652 /* Set a Prism RF front-end to a special mode for channel 14? 1653 * 1654 * Apparently the SMC2635W needs this, although I don't think 1655 * it has a Prism RF. 1656 */ 1657 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1658 } 1659 ATW_WRITE(sc, ATW_GPIO, gpio); 1660 1661 #ifdef ATW_SYNDEBUG 1662 atw_si4126_print(sc); 1663 #endif /* ATW_SYNDEBUG */ 1664 } 1665 1666 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1667 * diversity. 1668 * 1669 * !!! 1670 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1671 * !!! 1672 */ 1673 static int 1674 atw_rf3000_init(struct atw_softc *sc) 1675 { 1676 int rc = 0; 1677 1678 atw_bbp_io_enable(sc, 1); 1679 1680 /* CCA is acquisition sensitive */ 1681 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1682 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1683 1684 if (rc != 0) 1685 goto out; 1686 1687 /* enable diversity */ 1688 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1689 1690 if (rc != 0) 1691 goto out; 1692 1693 /* sensible setting from a binary-only driver */ 1694 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1695 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1696 1697 if (rc != 0) 1698 goto out; 1699 1700 /* magic from a binary-only driver */ 1701 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1702 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1703 1704 if (rc != 0) 1705 goto out; 1706 1707 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1708 1709 if (rc != 0) 1710 goto out; 1711 1712 /* XXX Reference driver remarks that Abocom sets this to 50. 1713 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1714 * in the "reserved" area of register RF3000_OPTIONS1. 1715 */ 1716 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1717 1718 if (rc != 0) 1719 goto out; 1720 1721 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1722 1723 if (rc != 0) 1724 goto out; 1725 1726 out: 1727 atw_bbp_io_enable(sc, 0); 1728 return rc; 1729 } 1730 1731 #ifdef ATW_BBPDEBUG 1732 static void 1733 atw_rf3000_print(struct atw_softc *sc) 1734 { 1735 struct ifnet *ifp = &sc->sc_if; 1736 u_int addr, val; 1737 1738 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1739 return; 1740 1741 for (addr = 0x01; addr <= 0x15; addr++) { 1742 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1743 if (atw_rf3000_read(sc, addr, &val) != 0) { 1744 printf("<unknown> (quitting print-out)\n"); 1745 break; 1746 } 1747 printf("%08x\n", val); 1748 } 1749 } 1750 #endif /* ATW_BBPDEBUG */ 1751 1752 /* Set the power settings on the BBP for channel `chan'. */ 1753 static int 1754 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1755 { 1756 int rc = 0; 1757 u_int32_t reg; 1758 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1759 1760 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1761 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1762 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1763 1764 /* odd channels: LSB, even channels: MSB */ 1765 if (chan % 2 == 1) { 1766 txpower &= 0xFF; 1767 lpf_cutoff &= 0xFF; 1768 lna_gs_thresh &= 0xFF; 1769 } else { 1770 txpower >>= 8; 1771 lpf_cutoff >>= 8; 1772 lna_gs_thresh >>= 8; 1773 } 1774 1775 #ifdef ATW_BBPDEBUG 1776 atw_rf3000_print(sc); 1777 #endif /* ATW_BBPDEBUG */ 1778 1779 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1780 "lna_gs_thresh %02x\n", 1781 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1782 1783 atw_bbp_io_enable(sc, 1); 1784 1785 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1786 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1787 goto out; 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1790 goto out; 1791 1792 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1793 goto out; 1794 1795 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1796 1797 if (rc != 0) 1798 goto out; 1799 1800 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1801 1802 if (rc != 0) 1803 goto out; 1804 1805 #ifdef ATW_BBPDEBUG 1806 atw_rf3000_print(sc); 1807 #endif /* ATW_BBPDEBUG */ 1808 1809 out: 1810 atw_bbp_io_enable(sc, 0); 1811 1812 /* set beacon, rts, atim transmit power */ 1813 reg = ATW_READ(sc, ATW_PLCPHD); 1814 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1815 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1816 ATW_PLCPHD_SERVICE_MASK); 1817 ATW_WRITE(sc, ATW_PLCPHD, reg); 1818 DELAY(atw_plcphd_delay); 1819 1820 return rc; 1821 } 1822 1823 /* Write a register on the RF3000 baseband processor using the 1824 * registers provided by the ADM8211 for this purpose. 1825 * 1826 * Return 0 on success. 1827 */ 1828 static int 1829 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1830 { 1831 u_int32_t reg; 1832 int i; 1833 1834 reg = sc->sc_bbpctl_wr | 1835 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1836 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1837 1838 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1839 ATW_WRITE(sc, ATW_BBPCTL, reg); 1840 DELAY(2 * atw_pseudo_milli); 1841 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1842 break; 1843 } 1844 1845 if (i < 0) { 1846 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1847 return ETIMEDOUT; 1848 } 1849 return 0; 1850 } 1851 1852 /* Read a register on the RF3000 baseband processor using the registers 1853 * the ADM8211 provides for this purpose. 1854 * 1855 * The 7-bit register address is addr. Record the 8-bit data in the register 1856 * in *val. 1857 * 1858 * Return 0 on success. 1859 * 1860 * XXX This does not seem to work. The ADM8211 must require more or 1861 * different magic to read the chip than to write it. Possibly some 1862 * of the magic I have derived from a binary-only driver concerns 1863 * the "chip address" (see the RF3000 manual). 1864 */ 1865 #ifdef ATW_BBPDEBUG 1866 static int 1867 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1868 { 1869 u_int32_t reg; 1870 int i; 1871 1872 for (i = 1000; --i >= 0; ) { 1873 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1874 break; 1875 DELAY(100); 1876 } 1877 1878 if (i < 0) { 1879 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1880 sc->sc_dev.dv_xname); 1881 return ETIMEDOUT; 1882 } 1883 1884 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1885 1886 ATW_WRITE(sc, ATW_BBPCTL, reg); 1887 1888 for (i = 1000; --i >= 0; ) { 1889 DELAY(100); 1890 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1891 break; 1892 } 1893 1894 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1895 1896 if (i < 0) { 1897 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1898 sc->sc_dev.dv_xname, reg); 1899 return ETIMEDOUT; 1900 } 1901 if (val != NULL) 1902 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1903 return 0; 1904 } 1905 #endif /* ATW_BBPDEBUG */ 1906 1907 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1908 * provided by the ADM8211 for that purpose. 1909 * 1910 * val is 18 bits of data, and val is the 4-bit address of the register. 1911 * 1912 * Return 0 on success. 1913 */ 1914 static void 1915 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1916 { 1917 uint32_t bits, mask, reg; 1918 const int nbits = 22; 1919 1920 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1921 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1922 1923 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1924 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1925 1926 reg = ATW_SYNRF_SELSYN; 1927 /* reference driver: reset Si4126 serial bus to initial 1928 * conditions? 1929 */ 1930 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1931 ATW_WRITE(sc, ATW_SYNRF, reg); 1932 1933 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1934 if ((bits & mask) != 0) 1935 reg |= ATW_SYNRF_SYNDATA; 1936 else 1937 reg &= ~ATW_SYNRF_SYNDATA; 1938 ATW_WRITE(sc, ATW_SYNRF, reg); 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1940 ATW_WRITE(sc, ATW_SYNRF, reg); 1941 } 1942 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1943 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1944 } 1945 1946 /* Read 18-bit data from the 4-bit address addr in Si4126 1947 * RF synthesizer and write the data to *val. Return 0 on success. 1948 * 1949 * XXX This does not seem to work. The ADM8211 must require more or 1950 * different magic to read the chip than to write it. 1951 */ 1952 #ifdef ATW_SYNDEBUG 1953 static int 1954 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1955 { 1956 u_int32_t reg; 1957 int i; 1958 1959 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1960 1961 for (i = 1000; --i >= 0; ) { 1962 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1963 break; 1964 DELAY(100); 1965 } 1966 1967 if (i < 0) { 1968 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1969 sc->sc_dev.dv_xname); 1970 return ETIMEDOUT; 1971 } 1972 1973 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1974 1975 ATW_WRITE(sc, ATW_SYNCTL, reg); 1976 1977 for (i = 1000; --i >= 0; ) { 1978 DELAY(100); 1979 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1980 break; 1981 } 1982 1983 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1984 1985 if (i < 0) { 1986 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1987 sc->sc_dev.dv_xname, reg); 1988 return ETIMEDOUT; 1989 } 1990 if (val != NULL) 1991 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1992 ATW_SYNCTL_DATA_MASK); 1993 return 0; 1994 } 1995 #endif /* ATW_SYNDEBUG */ 1996 1997 /* XXX is the endianness correct? test. */ 1998 #define atw_calchash(addr) \ 1999 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 2000 2001 /* 2002 * atw_filter_setup: 2003 * 2004 * Set the ADM8211's receive filter. 2005 */ 2006 static void 2007 atw_filter_setup(struct atw_softc *sc) 2008 { 2009 struct ieee80211com *ic = &sc->sc_ic; 2010 struct ethercom *ec = &sc->sc_ec; 2011 struct ifnet *ifp = &sc->sc_if; 2012 int hash; 2013 u_int32_t hashes[2]; 2014 struct ether_multi *enm; 2015 struct ether_multistep step; 2016 2017 /* According to comments in tlp_al981_filter_setup 2018 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2019 * multicast filter to be set while it is running. Hopefully 2020 * the ADM8211 is not the same! 2021 */ 2022 if ((ifp->if_flags & IFF_RUNNING) != 0) 2023 atw_idle(sc, ATW_NAR_SR); 2024 2025 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2026 ifp->if_flags &= ~IFF_ALLMULTI; 2027 2028 /* XXX in scan mode, do not filter packets. Maybe this is 2029 * unnecessary. 2030 */ 2031 if (ic->ic_state == IEEE80211_S_SCAN || 2032 (ifp->if_flags & IFF_PROMISC) != 0) { 2033 sc->sc_opmode |= ATW_NAR_PR; 2034 goto allmulti; 2035 } 2036 2037 hashes[0] = hashes[1] = 0x0; 2038 2039 /* 2040 * Program the 64-bit multicast hash filter. 2041 */ 2042 ETHER_FIRST_MULTI(step, ec, enm); 2043 while (enm != NULL) { 2044 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2045 ETHER_ADDR_LEN) != 0) 2046 goto allmulti; 2047 2048 hash = atw_calchash(enm->enm_addrlo); 2049 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2050 ETHER_NEXT_MULTI(step, enm); 2051 sc->sc_opmode |= ATW_NAR_MM; 2052 } 2053 ifp->if_flags &= ~IFF_ALLMULTI; 2054 goto setit; 2055 2056 allmulti: 2057 sc->sc_opmode |= ATW_NAR_MM; 2058 ifp->if_flags |= IFF_ALLMULTI; 2059 hashes[0] = hashes[1] = 0xffffffff; 2060 2061 setit: 2062 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2063 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2064 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2065 DELAY(atw_nar_delay); 2066 ATW_WRITE(sc, ATW_RDR, 0x1); 2067 2068 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2069 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2070 } 2071 2072 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2073 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2074 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2075 * no beacon with the preferred BSSID and SSID in the number of 2076 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2077 */ 2078 static void 2079 atw_write_bssid(struct atw_softc *sc) 2080 { 2081 struct ieee80211com *ic = &sc->sc_ic; 2082 u_int8_t *bssid; 2083 2084 bssid = ic->ic_bss->ni_bssid; 2085 2086 ATW_WRITE(sc, ATW_BSSID0, 2087 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2088 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2089 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2090 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2091 2092 ATW_WRITE(sc, ATW_ABDA1, 2093 (ATW_READ(sc, ATW_ABDA1) & 2094 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2095 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2096 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2097 2098 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2099 ether_sprintf(sc->sc_bssid))); 2100 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2101 2102 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2103 } 2104 2105 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2106 * 16-bit word. 2107 */ 2108 static void 2109 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2110 { 2111 u_int i; 2112 u_int8_t *ptr; 2113 2114 memcpy(&sc->sc_sram[ofs], buf, buflen); 2115 2116 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2117 2118 KASSERT(buflen + ofs <= sc->sc_sramlen); 2119 2120 ptr = &sc->sc_sram[ofs]; 2121 2122 for (i = 0; i < buflen; i += 2) { 2123 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2124 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2125 DELAY(atw_writewep_delay); 2126 2127 ATW_WRITE(sc, ATW_WESK, 2128 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2129 DELAY(atw_writewep_delay); 2130 } 2131 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2132 2133 if (sc->sc_if.if_flags & IFF_DEBUG) { 2134 int n_octets = 0; 2135 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2136 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2137 for (i = 0; i < buflen; i++) { 2138 printf(" %02x", ptr[i]); 2139 if (++n_octets % 24 == 0) 2140 printf("\n"); 2141 } 2142 if (n_octets % 24 != 0) 2143 printf("\n"); 2144 } 2145 } 2146 2147 static int 2148 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2149 { 2150 struct atw_softc *sc = ic->ic_ifp->if_softc; 2151 u_int keyix = k->wk_keyix; 2152 2153 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2154 2155 if (keyix >= IEEE80211_WEP_NKID) 2156 return 0; 2157 if (k->wk_keylen != 0) 2158 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2159 2160 return 1; 2161 } 2162 2163 static int 2164 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2165 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2166 { 2167 struct atw_softc *sc = ic->ic_ifp->if_softc; 2168 2169 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2170 2171 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2172 return 0; 2173 2174 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2175 2176 return 1; 2177 } 2178 2179 static void 2180 atw_key_update_begin(struct ieee80211com *ic) 2181 { 2182 #ifdef ATW_DEBUG 2183 struct ifnet *ifp = ic->ic_ifp; 2184 struct atw_softc *sc = ifp->if_softc; 2185 #endif 2186 2187 DPRINTF(sc, ("%s:\n", __func__)); 2188 } 2189 2190 static void 2191 atw_key_update_end(struct ieee80211com *ic) 2192 { 2193 struct ifnet *ifp = ic->ic_ifp; 2194 struct atw_softc *sc = ifp->if_softc; 2195 2196 DPRINTF(sc, ("%s:\n", __func__)); 2197 2198 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2199 return; 2200 if (ATW_IS_ENABLED(sc) == 0) 2201 return; 2202 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2203 atw_write_wep(sc); 2204 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2205 DELAY(atw_nar_delay); 2206 ATW_WRITE(sc, ATW_RDR, 0x1); 2207 } 2208 2209 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2210 static void 2211 atw_write_wep(struct atw_softc *sc) 2212 { 2213 struct ieee80211com *ic = &sc->sc_ic; 2214 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2215 u_int8_t buf[IEEE80211_WEP_NKID] 2216 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2217 u_int32_t reg; 2218 int i; 2219 2220 sc->sc_wepctl = 0; 2221 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2222 2223 memset(&buf[0][0], 0, sizeof(buf)); 2224 2225 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2226 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2227 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2228 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2229 buf[i][1] = ATW_WEP_ENABLED; 2230 } else { 2231 buf[i][1] = 0; 2232 continue; 2233 } 2234 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2235 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2236 ic->ic_nw_keys[i].wk_keylen - 1); 2237 } 2238 2239 reg = ATW_READ(sc, ATW_MACTEST); 2240 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2241 reg &= ~ATW_MACTEST_KEYID_MASK; 2242 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2243 ATW_WRITE(sc, ATW_MACTEST, reg); 2244 2245 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2246 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2247 2248 switch (sc->sc_rev) { 2249 case ATW_REVISION_AB: 2250 case ATW_REVISION_AF: 2251 /* Bypass WEP on Rx. */ 2252 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2253 break; 2254 default: 2255 break; 2256 } 2257 2258 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2259 sizeof(buf)); 2260 2261 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2262 } 2263 2264 static void 2265 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2266 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2267 { 2268 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2269 2270 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2271 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2272 return; 2273 2274 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2275 2276 switch (subtype) { 2277 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2278 case IEEE80211_FC0_SUBTYPE_BEACON: 2279 if (ic->ic_opmode == IEEE80211_M_IBSS && 2280 ic->ic_state == IEEE80211_S_RUN) { 2281 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2282 (void)ieee80211_ibss_merge(ni); 2283 } 2284 break; 2285 default: 2286 break; 2287 } 2288 return; 2289 } 2290 2291 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2292 * In ad hoc mode, the SSID is written to the beacons sent by the 2293 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2294 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2295 * indications. 2296 */ 2297 static void 2298 atw_write_ssid(struct atw_softc *sc) 2299 { 2300 struct ieee80211com *ic = &sc->sc_ic; 2301 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2302 * it only expects the element length, not its ID. 2303 */ 2304 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2305 2306 memset(buf, 0, sizeof(buf)); 2307 buf[0] = ic->ic_bss->ni_esslen; 2308 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2309 2310 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2311 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2312 } 2313 2314 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2315 * In ad hoc mode, the supported rates are written to beacons sent by the 2316 * ADM8211. 2317 */ 2318 static void 2319 atw_write_sup_rates(struct atw_softc *sc) 2320 { 2321 struct ieee80211com *ic = &sc->sc_ic; 2322 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2323 * supported rates 2324 */ 2325 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2326 2327 memset(buf, 0, sizeof(buf)); 2328 2329 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2330 2331 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2332 ic->ic_bss->ni_rates.rs_nrates); 2333 2334 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2335 } 2336 2337 /* Start/stop sending beacons. */ 2338 void 2339 atw_start_beacon(struct atw_softc *sc, int start) 2340 { 2341 struct ieee80211com *ic = &sc->sc_ic; 2342 uint16_t chan; 2343 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2344 size_t len; 2345 2346 if (ATW_IS_ENABLED(sc) == 0) 2347 return; 2348 2349 /* start beacons */ 2350 len = sizeof(struct ieee80211_frame) + 2351 8 /* timestamp */ + 2 /* beacon interval */ + 2352 2 /* capability info */ + 2353 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2354 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2355 3 /* DS parameters */ + 2356 IEEE80211_CRC_LEN; 2357 2358 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2359 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2360 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2361 2362 ATW_WRITE(sc, ATW_BCNT, bcnt); 2363 ATW_WRITE(sc, ATW_CAP1, cap1); 2364 2365 if (!start) 2366 return; 2367 2368 /* TBD use ni_capinfo */ 2369 2370 capinfo = 0; 2371 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2372 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2373 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2374 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2375 2376 switch (ic->ic_opmode) { 2377 case IEEE80211_M_IBSS: 2378 len += 4; /* IBSS parameters */ 2379 capinfo |= IEEE80211_CAPINFO_IBSS; 2380 break; 2381 case IEEE80211_M_HOSTAP: 2382 /* XXX 6-byte minimum TIM */ 2383 len += atw_beacon_len_adjust; 2384 capinfo |= IEEE80211_CAPINFO_ESS; 2385 break; 2386 default: 2387 return; 2388 } 2389 2390 /* set listen interval 2391 * XXX do software units agree w/ hardware? 2392 */ 2393 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2394 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2395 2396 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2397 2398 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2399 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2400 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2401 2402 ATW_WRITE(sc, ATW_BCNT, bcnt); 2403 ATW_WRITE(sc, ATW_BPLI, bpli); 2404 ATW_WRITE(sc, ATW_CAP0, cap0); 2405 ATW_WRITE(sc, ATW_CAP1, cap1); 2406 2407 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2408 sc->sc_dev.dv_xname, bcnt)); 2409 2410 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2411 sc->sc_dev.dv_xname, cap1)); 2412 } 2413 2414 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2415 static inline uint32_t 2416 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2417 { 2418 /* Following the reference driver's lead, I compute 2419 * 2420 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2421 * 2422 * without using 64-bit arithmetic, using the following 2423 * relationship: 2424 * 2425 * (0x100000000 * H + L) % m 2426 * = ((0x100000000 % m) * H + L) % m 2427 * = (((0xffffffff + 1) % m) * H + L) % m 2428 * = ((0xffffffff % m + 1 % m) * H + L) % m 2429 * = ((0xffffffff % m + 1) * H + L) % m 2430 */ 2431 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2432 } 2433 2434 static uint64_t 2435 atw_get_tsft(struct atw_softc *sc) 2436 { 2437 int i; 2438 uint32_t tsfth, tsftl; 2439 for (i = 0; i < 2; i++) { 2440 tsfth = ATW_READ(sc, ATW_TSFTH); 2441 tsftl = ATW_READ(sc, ATW_TSFTL); 2442 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2443 break; 2444 } 2445 return ((uint64_t)tsfth << 32) | tsftl; 2446 } 2447 2448 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2449 * the ieee80211com. 2450 * 2451 * Predict the next target beacon transmission time (TBTT) and 2452 * write it to the ADM8211. 2453 */ 2454 static void 2455 atw_predict_beacon(struct atw_softc *sc) 2456 { 2457 #define TBTTOFS 20 /* TU */ 2458 2459 struct ieee80211com *ic = &sc->sc_ic; 2460 uint64_t tsft; 2461 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2462 union { 2463 uint64_t word; 2464 uint8_t tstamp[8]; 2465 } u; 2466 2467 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2468 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2469 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2470 tsft = atw_get_tsft(sc); 2471 u.word = htole64(tsft); 2472 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2473 sizeof(ic->ic_bss->ni_tstamp)); 2474 } else 2475 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2476 2477 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2478 2479 tsftl = tsft & 0xFFFFFFFF; 2480 tsfth = tsft >> 32; 2481 2482 /* We sent/received the last beacon `past' microseconds 2483 * after the interval divided the TSF timer. 2484 */ 2485 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2486 2487 /* Skip ten beacons so that the TBTT cannot pass before 2488 * we've programmed it. Ten is an arbitrary number. 2489 */ 2490 tbtt = past_even + ival * 10; 2491 2492 ATW_WRITE(sc, ATW_TOFS1, 2493 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2494 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2495 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2496 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2497 #undef TBTTOFS 2498 } 2499 2500 static void 2501 atw_next_scan(void *arg) 2502 { 2503 struct atw_softc *sc = arg; 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 int s; 2506 2507 /* don't call atw_start w/o network interrupts blocked */ 2508 s = splnet(); 2509 if (ic->ic_state == IEEE80211_S_SCAN) 2510 ieee80211_next_scan(ic); 2511 splx(s); 2512 } 2513 2514 /* Synchronize the hardware state with the software state. */ 2515 static int 2516 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2517 { 2518 struct ifnet *ifp = ic->ic_ifp; 2519 struct atw_softc *sc = ifp->if_softc; 2520 enum ieee80211_state ostate; 2521 int error = 0; 2522 2523 ostate = ic->ic_state; 2524 callout_stop(&sc->sc_scan_ch); 2525 2526 switch (nstate) { 2527 case IEEE80211_S_AUTH: 2528 case IEEE80211_S_ASSOC: 2529 atw_write_bssid(sc); 2530 error = atw_tune(sc); 2531 break; 2532 case IEEE80211_S_INIT: 2533 callout_stop(&sc->sc_scan_ch); 2534 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2535 atw_start_beacon(sc, 0); 2536 break; 2537 case IEEE80211_S_SCAN: 2538 error = atw_tune(sc); 2539 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2540 atw_next_scan, sc); 2541 break; 2542 case IEEE80211_S_RUN: 2543 error = atw_tune(sc); 2544 atw_write_bssid(sc); 2545 atw_write_ssid(sc); 2546 atw_write_sup_rates(sc); 2547 2548 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2549 ic->ic_opmode == IEEE80211_M_MONITOR) 2550 break; 2551 2552 /* set listen interval 2553 * XXX do software units agree w/ hardware? 2554 */ 2555 ATW_WRITE(sc, ATW_BPLI, 2556 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2557 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2558 ATW_BPLI_LI_MASK)); 2559 2560 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2561 ATW_READ(sc, ATW_BPLI))); 2562 2563 atw_predict_beacon(sc); 2564 2565 switch (ic->ic_opmode) { 2566 case IEEE80211_M_AHDEMO: 2567 case IEEE80211_M_HOSTAP: 2568 case IEEE80211_M_IBSS: 2569 atw_start_beacon(sc, 1); 2570 break; 2571 case IEEE80211_M_MONITOR: 2572 case IEEE80211_M_STA: 2573 break; 2574 } 2575 2576 break; 2577 } 2578 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2579 } 2580 2581 /* 2582 * atw_add_rxbuf: 2583 * 2584 * Add a receive buffer to the indicated descriptor. 2585 */ 2586 int 2587 atw_add_rxbuf(struct atw_softc *sc, int idx) 2588 { 2589 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2590 struct mbuf *m; 2591 int error; 2592 2593 MGETHDR(m, M_DONTWAIT, MT_DATA); 2594 if (m == NULL) 2595 return (ENOBUFS); 2596 2597 MCLGET(m, M_DONTWAIT); 2598 if ((m->m_flags & M_EXT) == 0) { 2599 m_freem(m); 2600 return (ENOBUFS); 2601 } 2602 2603 if (rxs->rxs_mbuf != NULL) 2604 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2605 2606 rxs->rxs_mbuf = m; 2607 2608 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2609 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2610 BUS_DMA_READ|BUS_DMA_NOWAIT); 2611 if (error) { 2612 printf("%s: can't load rx DMA map %d, error = %d\n", 2613 sc->sc_dev.dv_xname, idx, error); 2614 panic("atw_add_rxbuf"); /* XXX */ 2615 } 2616 2617 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2618 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2619 2620 ATW_INIT_RXDESC(sc, idx); 2621 2622 return (0); 2623 } 2624 2625 /* 2626 * Release any queued transmit buffers. 2627 */ 2628 void 2629 atw_txdrain(struct atw_softc *sc) 2630 { 2631 struct atw_txsoft *txs; 2632 2633 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2634 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2635 if (txs->txs_mbuf != NULL) { 2636 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2637 m_freem(txs->txs_mbuf); 2638 txs->txs_mbuf = NULL; 2639 } 2640 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2641 sc->sc_txfree += txs->txs_ndescs; 2642 } 2643 2644 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2645 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2646 sc->sc_txfree != ATW_NTXDESC)); 2647 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2648 sc->sc_tx_timer = 0; 2649 } 2650 2651 /* 2652 * atw_stop: [ ifnet interface function ] 2653 * 2654 * Stop transmission on the interface. 2655 */ 2656 void 2657 atw_stop(struct ifnet *ifp, int disable) 2658 { 2659 struct atw_softc *sc = ifp->if_softc; 2660 struct ieee80211com *ic = &sc->sc_ic; 2661 2662 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2663 2664 /* Disable interrupts. */ 2665 ATW_WRITE(sc, ATW_IER, 0); 2666 2667 /* Stop the transmit and receive processes. */ 2668 sc->sc_opmode = 0; 2669 ATW_WRITE(sc, ATW_NAR, 0); 2670 DELAY(atw_nar_delay); 2671 ATW_WRITE(sc, ATW_TDBD, 0); 2672 ATW_WRITE(sc, ATW_TDBP, 0); 2673 ATW_WRITE(sc, ATW_RDB, 0); 2674 2675 atw_txdrain(sc); 2676 2677 if (disable) { 2678 atw_rxdrain(sc); 2679 atw_disable(sc); 2680 } 2681 2682 /* 2683 * Mark the interface down and cancel the watchdog timer. 2684 */ 2685 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2686 sc->sc_tx_timer = 0; 2687 ifp->if_timer = 0; 2688 2689 if (!disable) 2690 atw_reset(sc); 2691 } 2692 2693 /* 2694 * atw_rxdrain: 2695 * 2696 * Drain the receive queue. 2697 */ 2698 void 2699 atw_rxdrain(struct atw_softc *sc) 2700 { 2701 struct atw_rxsoft *rxs; 2702 int i; 2703 2704 for (i = 0; i < ATW_NRXDESC; i++) { 2705 rxs = &sc->sc_rxsoft[i]; 2706 if (rxs->rxs_mbuf == NULL) 2707 continue; 2708 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2709 m_freem(rxs->rxs_mbuf); 2710 rxs->rxs_mbuf = NULL; 2711 } 2712 } 2713 2714 /* 2715 * atw_detach: 2716 * 2717 * Detach an ADM8211 interface. 2718 */ 2719 int 2720 atw_detach(struct atw_softc *sc) 2721 { 2722 struct ifnet *ifp = &sc->sc_if; 2723 struct atw_rxsoft *rxs; 2724 struct atw_txsoft *txs; 2725 int i; 2726 2727 /* 2728 * Succeed now if there isn't any work to do. 2729 */ 2730 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2731 return (0); 2732 2733 callout_stop(&sc->sc_scan_ch); 2734 2735 ieee80211_ifdetach(&sc->sc_ic); 2736 if_detach(ifp); 2737 2738 for (i = 0; i < ATW_NRXDESC; i++) { 2739 rxs = &sc->sc_rxsoft[i]; 2740 if (rxs->rxs_mbuf != NULL) { 2741 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2742 m_freem(rxs->rxs_mbuf); 2743 rxs->rxs_mbuf = NULL; 2744 } 2745 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2746 } 2747 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2748 txs = &sc->sc_txsoft[i]; 2749 if (txs->txs_mbuf != NULL) { 2750 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2751 m_freem(txs->txs_mbuf); 2752 txs->txs_mbuf = NULL; 2753 } 2754 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2755 } 2756 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2757 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2758 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2759 sizeof(struct atw_control_data)); 2760 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2761 2762 shutdownhook_disestablish(sc->sc_sdhook); 2763 powerhook_disestablish(sc->sc_powerhook); 2764 2765 if (sc->sc_srom) 2766 free(sc->sc_srom, M_DEVBUF); 2767 2768 return (0); 2769 } 2770 2771 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2772 void 2773 atw_shutdown(void *arg) 2774 { 2775 struct atw_softc *sc = arg; 2776 2777 atw_stop(&sc->sc_if, 1); 2778 } 2779 2780 int 2781 atw_intr(void *arg) 2782 { 2783 struct atw_softc *sc = arg; 2784 struct ifnet *ifp = &sc->sc_if; 2785 u_int32_t status, rxstatus, txstatus, linkstatus; 2786 int handled = 0, txthresh; 2787 2788 #ifdef DEBUG 2789 if (ATW_IS_ENABLED(sc) == 0) 2790 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2791 #endif 2792 2793 /* 2794 * If the interface isn't running, the interrupt couldn't 2795 * possibly have come from us. 2796 */ 2797 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2798 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2799 return (0); 2800 2801 for (;;) { 2802 status = ATW_READ(sc, ATW_STSR); 2803 2804 if (status) 2805 ATW_WRITE(sc, ATW_STSR, status); 2806 2807 #ifdef ATW_DEBUG 2808 #define PRINTINTR(flag) do { \ 2809 if ((status & flag) != 0) { \ 2810 printf("%s" #flag, delim); \ 2811 delim = ","; \ 2812 } \ 2813 } while (0) 2814 2815 if (atw_debug > 1 && status) { 2816 const char *delim = "<"; 2817 2818 printf("%s: reg[STSR] = %x", 2819 sc->sc_dev.dv_xname, status); 2820 2821 PRINTINTR(ATW_INTR_FBE); 2822 PRINTINTR(ATW_INTR_LINKOFF); 2823 PRINTINTR(ATW_INTR_LINKON); 2824 PRINTINTR(ATW_INTR_RCI); 2825 PRINTINTR(ATW_INTR_RDU); 2826 PRINTINTR(ATW_INTR_REIS); 2827 PRINTINTR(ATW_INTR_RPS); 2828 PRINTINTR(ATW_INTR_TCI); 2829 PRINTINTR(ATW_INTR_TDU); 2830 PRINTINTR(ATW_INTR_TLT); 2831 PRINTINTR(ATW_INTR_TPS); 2832 PRINTINTR(ATW_INTR_TRT); 2833 PRINTINTR(ATW_INTR_TUF); 2834 PRINTINTR(ATW_INTR_BCNTC); 2835 PRINTINTR(ATW_INTR_ATIME); 2836 PRINTINTR(ATW_INTR_TBTT); 2837 PRINTINTR(ATW_INTR_TSCZ); 2838 PRINTINTR(ATW_INTR_TSFTF); 2839 printf(">\n"); 2840 } 2841 #undef PRINTINTR 2842 #endif /* ATW_DEBUG */ 2843 2844 if ((status & sc->sc_inten) == 0) 2845 break; 2846 2847 handled = 1; 2848 2849 rxstatus = status & sc->sc_rxint_mask; 2850 txstatus = status & sc->sc_txint_mask; 2851 linkstatus = status & sc->sc_linkint_mask; 2852 2853 if (linkstatus) { 2854 atw_linkintr(sc, linkstatus); 2855 } 2856 2857 if (rxstatus) { 2858 /* Grab any new packets. */ 2859 atw_rxintr(sc); 2860 2861 if (rxstatus & ATW_INTR_RDU) { 2862 printf("%s: receive ring overrun\n", 2863 sc->sc_dev.dv_xname); 2864 /* Get the receive process going again. */ 2865 ATW_WRITE(sc, ATW_RDR, 0x1); 2866 break; 2867 } 2868 } 2869 2870 if (txstatus) { 2871 /* Sweep up transmit descriptors. */ 2872 atw_txintr(sc); 2873 2874 if (txstatus & ATW_INTR_TLT) 2875 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2876 sc->sc_dev.dv_xname)); 2877 2878 if (txstatus & ATW_INTR_TRT) 2879 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2880 sc->sc_dev.dv_xname)); 2881 2882 /* If Tx under-run, increase our transmit threshold 2883 * if another is available. 2884 */ 2885 txthresh = sc->sc_txthresh + 1; 2886 if ((txstatus & ATW_INTR_TUF) && 2887 sc->sc_txth[txthresh].txth_name != NULL) { 2888 /* Idle the transmit process. */ 2889 atw_idle(sc, ATW_NAR_ST); 2890 2891 sc->sc_txthresh = txthresh; 2892 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2893 sc->sc_opmode |= 2894 sc->sc_txth[txthresh].txth_opmode; 2895 printf("%s: transmit underrun; new " 2896 "threshold: %s\n", sc->sc_dev.dv_xname, 2897 sc->sc_txth[txthresh].txth_name); 2898 2899 /* Set the new threshold and restart 2900 * the transmit process. 2901 */ 2902 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2903 DELAY(atw_nar_delay); 2904 ATW_WRITE(sc, ATW_RDR, 0x1); 2905 /* XXX Log every Nth underrun from 2906 * XXX now on? 2907 */ 2908 } 2909 } 2910 2911 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2912 if (status & ATW_INTR_TPS) 2913 printf("%s: transmit process stopped\n", 2914 sc->sc_dev.dv_xname); 2915 if (status & ATW_INTR_RPS) 2916 printf("%s: receive process stopped\n", 2917 sc->sc_dev.dv_xname); 2918 (void)atw_init(ifp); 2919 break; 2920 } 2921 2922 if (status & ATW_INTR_FBE) { 2923 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2924 (void)atw_init(ifp); 2925 break; 2926 } 2927 2928 /* 2929 * Not handled: 2930 * 2931 * Transmit buffer unavailable -- normal 2932 * condition, nothing to do, really. 2933 * 2934 * Early receive interrupt -- not available on 2935 * all chips, we just use RI. We also only 2936 * use single-segment receive DMA, so this 2937 * is mostly useless. 2938 * 2939 * TBD others 2940 */ 2941 } 2942 2943 /* Try to get more packets going. */ 2944 atw_start(ifp); 2945 2946 return (handled); 2947 } 2948 2949 /* 2950 * atw_idle: 2951 * 2952 * Cause the transmit and/or receive processes to go idle. 2953 * 2954 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2955 * process in STSR if I clear SR or ST after the process has already 2956 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2957 * do not seem to be too reliable. Perhaps I have the sense of the 2958 * Rx bits switched with the Tx bits? 2959 */ 2960 void 2961 atw_idle(struct atw_softc *sc, u_int32_t bits) 2962 { 2963 u_int32_t ackmask = 0, opmode, stsr, test0; 2964 int i, s; 2965 2966 s = splnet(); 2967 2968 opmode = sc->sc_opmode & ~bits; 2969 2970 if (bits & ATW_NAR_SR) 2971 ackmask |= ATW_INTR_RPS; 2972 2973 if (bits & ATW_NAR_ST) { 2974 ackmask |= ATW_INTR_TPS; 2975 /* set ATW_NAR_HF to flush TX FIFO. */ 2976 opmode |= ATW_NAR_HF; 2977 } 2978 2979 ATW_WRITE(sc, ATW_NAR, opmode); 2980 DELAY(atw_nar_delay); 2981 2982 for (i = 0; i < 1000; i++) { 2983 stsr = ATW_READ(sc, ATW_STSR); 2984 if ((stsr & ackmask) == ackmask) 2985 break; 2986 DELAY(10); 2987 } 2988 2989 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2990 2991 if ((stsr & ackmask) == ackmask) 2992 goto out; 2993 2994 test0 = ATW_READ(sc, ATW_TEST0); 2995 2996 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2997 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2998 printf("%s: transmit process not idle [%s]\n", 2999 sc->sc_dev.dv_xname, 3000 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 3001 printf("%s: bits %08x test0 %08x stsr %08x\n", 3002 sc->sc_dev.dv_xname, bits, test0, stsr); 3003 } 3004 3005 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3006 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3007 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3008 sc->sc_dev.dv_xname, 3009 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3010 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3011 sc->sc_dev.dv_xname, bits, test0, stsr)); 3012 } 3013 out: 3014 if ((bits & ATW_NAR_ST) != 0) 3015 atw_txdrain(sc); 3016 splx(s); 3017 return; 3018 } 3019 3020 /* 3021 * atw_linkintr: 3022 * 3023 * Helper; handle link-status interrupts. 3024 */ 3025 void 3026 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3027 { 3028 struct ieee80211com *ic = &sc->sc_ic; 3029 3030 if (ic->ic_state != IEEE80211_S_RUN) 3031 return; 3032 3033 if (linkstatus & ATW_INTR_LINKON) { 3034 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3035 sc->sc_rescan_timer = 0; 3036 } else if (linkstatus & ATW_INTR_LINKOFF) { 3037 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3038 if (ic->ic_opmode != IEEE80211_M_STA) 3039 return; 3040 sc->sc_rescan_timer = 3; 3041 sc->sc_if.if_timer = 1; 3042 } 3043 } 3044 3045 static inline int 3046 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3047 { 3048 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3049 return 0; 3050 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3051 return 0; 3052 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3053 } 3054 3055 /* 3056 * atw_rxintr: 3057 * 3058 * Helper; handle receive interrupts. 3059 */ 3060 void 3061 atw_rxintr(struct atw_softc *sc) 3062 { 3063 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3064 struct ieee80211com *ic = &sc->sc_ic; 3065 struct ieee80211_node *ni; 3066 struct ieee80211_frame_min *wh; 3067 struct ifnet *ifp = &sc->sc_if; 3068 struct atw_rxsoft *rxs; 3069 struct mbuf *m; 3070 u_int32_t rxstat; 3071 int i, len, rate, rate0; 3072 u_int32_t rssi, rssi0; 3073 3074 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3075 rxs = &sc->sc_rxsoft[i]; 3076 3077 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3078 3079 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3080 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3081 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3082 3083 if (rxstat & ATW_RXSTAT_OWN) 3084 break; /* We have processed all receive buffers. */ 3085 3086 DPRINTF3(sc, 3087 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3088 sc->sc_dev.dv_xname, 3089 rxstat, rssi0, 3090 le32toh(sc->sc_rxdescs[i].ar_buf1), 3091 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3092 3093 /* 3094 * Make sure the packet fits in one buffer. This should 3095 * always be the case. 3096 */ 3097 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3098 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3099 printf("%s: incoming packet spilled, resetting\n", 3100 sc->sc_dev.dv_xname); 3101 (void)atw_init(ifp); 3102 return; 3103 } 3104 3105 /* 3106 * If an error occurred, update stats, clear the status 3107 * word, and leave the packet buffer in place. It will 3108 * simply be reused the next time the ring comes around. 3109 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3110 * error. 3111 */ 3112 3113 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3114 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3115 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3116 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3117 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3118 ATW_RXSTAT_ICVE)) != 0)) { 3119 #define PRINTERR(bit, str) \ 3120 if (rxstat & (bit)) \ 3121 printf("%s: receive error: %s\n", \ 3122 sc->sc_dev.dv_xname, str) 3123 ifp->if_ierrors++; 3124 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3125 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3126 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3127 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3128 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3129 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3130 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3131 #undef PRINTERR 3132 ATW_INIT_RXDESC(sc, i); 3133 continue; 3134 } 3135 3136 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3137 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3138 3139 /* 3140 * No errors; receive the packet. Note the ADM8211 3141 * includes the CRC in promiscuous mode. 3142 */ 3143 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3144 3145 /* 3146 * Allocate a new mbuf cluster. If that fails, we are 3147 * out of memory, and must drop the packet and recycle 3148 * the buffer that's already attached to this descriptor. 3149 */ 3150 m = rxs->rxs_mbuf; 3151 if (atw_add_rxbuf(sc, i) != 0) { 3152 ifp->if_ierrors++; 3153 ATW_INIT_RXDESC(sc, i); 3154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3156 continue; 3157 } 3158 3159 ifp->if_ipackets++; 3160 if (sc->sc_opmode & ATW_NAR_PR) 3161 len -= IEEE80211_CRC_LEN; 3162 m->m_pkthdr.rcvif = ifp; 3163 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3164 3165 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3166 rate = 0; 3167 else 3168 rate = rate_tbl[rate0]; 3169 3170 /* The RSSI comes straight from a register in the 3171 * baseband processor. I know that for the RF3000, 3172 * the RSSI register also contains the antenna-selection 3173 * bits. Mask those off. 3174 * 3175 * TBD Treat other basebands. 3176 */ 3177 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3178 rssi = rssi0 & RF3000_RSSI_MASK; 3179 else 3180 rssi = rssi0; 3181 3182 #if NBPFILTER > 0 3183 /* Pass this up to any BPF listeners. */ 3184 if (sc->sc_radiobpf != NULL) { 3185 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3186 3187 tap->ar_rate = rate; 3188 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3189 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3190 3191 /* TBD verify units are dB */ 3192 tap->ar_antsignal = (int)rssi; 3193 /* TBD tap->ar_flags */ 3194 3195 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3196 tap->ar_ihdr.it_len, m); 3197 } 3198 #endif /* NPBFILTER > 0 */ 3199 3200 wh = mtod(m, struct ieee80211_frame_min *); 3201 ni = ieee80211_find_rxnode(ic, wh); 3202 if (atw_hw_decrypted(sc, wh)) { 3203 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3204 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3205 } 3206 ieee80211_input(ic, m, ni, (int)rssi, 0); 3207 ieee80211_free_node(ni); 3208 } 3209 3210 /* Update the receive pointer. */ 3211 sc->sc_rxptr = i; 3212 } 3213 3214 /* 3215 * atw_txintr: 3216 * 3217 * Helper; handle transmit interrupts. 3218 */ 3219 void 3220 atw_txintr(struct atw_softc *sc) 3221 { 3222 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3223 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3224 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3225 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3226 3227 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3228 struct ifnet *ifp = &sc->sc_if; 3229 struct atw_txsoft *txs; 3230 u_int32_t txstat; 3231 3232 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3233 sc->sc_dev.dv_xname, sc->sc_flags)); 3234 3235 /* 3236 * Go through our Tx list and free mbufs for those 3237 * frames that have been transmitted. 3238 */ 3239 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3240 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3241 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3242 3243 #ifdef ATW_DEBUG 3244 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3245 int i; 3246 printf(" txsoft %p transmit chain:\n", txs); 3247 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3248 txs->txs_ndescs - 1, 3249 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3250 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3251 printf(" descriptor %d:\n", i); 3252 printf(" at_status: 0x%08x\n", 3253 le32toh(sc->sc_txdescs[i].at_stat)); 3254 printf(" at_flags: 0x%08x\n", 3255 le32toh(sc->sc_txdescs[i].at_flags)); 3256 printf(" at_buf1: 0x%08x\n", 3257 le32toh(sc->sc_txdescs[i].at_buf1)); 3258 printf(" at_buf2: 0x%08x\n", 3259 le32toh(sc->sc_txdescs[i].at_buf2)); 3260 if (i == txs->txs_lastdesc) 3261 break; 3262 } 3263 } 3264 #endif 3265 3266 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3267 if (txstat & ATW_TXSTAT_OWN) 3268 break; 3269 3270 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3271 3272 sc->sc_txfree += txs->txs_ndescs; 3273 3274 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3275 0, txs->txs_dmamap->dm_mapsize, 3276 BUS_DMASYNC_POSTWRITE); 3277 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3278 m_freem(txs->txs_mbuf); 3279 txs->txs_mbuf = NULL; 3280 3281 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3282 3283 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3284 sc->sc_txfree == 0)); 3285 ifp->if_flags &= ~IFF_OACTIVE; 3286 3287 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3288 (txstat & TXSTAT_ERRMASK) != 0) { 3289 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3290 txstat_buf, sizeof(txstat_buf)); 3291 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3292 txstat_buf, 3293 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3294 } 3295 3296 /* 3297 * Check for errors and collisions. 3298 */ 3299 if (txstat & ATW_TXSTAT_TUF) 3300 sc->sc_stats.ts_tx_tuf++; 3301 if (txstat & ATW_TXSTAT_TLT) 3302 sc->sc_stats.ts_tx_tlt++; 3303 if (txstat & ATW_TXSTAT_TRT) 3304 sc->sc_stats.ts_tx_trt++; 3305 if (txstat & ATW_TXSTAT_TRO) 3306 sc->sc_stats.ts_tx_tro++; 3307 if (txstat & ATW_TXSTAT_SOFBR) { 3308 sc->sc_stats.ts_tx_sofbr++; 3309 } 3310 3311 if ((txstat & ATW_TXSTAT_ES) == 0) 3312 ifp->if_collisions += 3313 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3314 else 3315 ifp->if_oerrors++; 3316 3317 ifp->if_opackets++; 3318 } 3319 3320 /* 3321 * If there are no more pending transmissions, cancel the watchdog 3322 * timer. 3323 */ 3324 if (txs == NULL) { 3325 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3326 sc->sc_tx_timer = 0; 3327 } 3328 #undef TXSTAT_ERRMASK 3329 #undef TXSTAT_FMT 3330 } 3331 3332 /* 3333 * atw_watchdog: [ifnet interface function] 3334 * 3335 * Watchdog timer handler. 3336 */ 3337 void 3338 atw_watchdog(struct ifnet *ifp) 3339 { 3340 struct atw_softc *sc = ifp->if_softc; 3341 struct ieee80211com *ic = &sc->sc_ic; 3342 3343 ifp->if_timer = 0; 3344 if (ATW_IS_ENABLED(sc) == 0) 3345 return; 3346 3347 if (sc->sc_rescan_timer) { 3348 if (--sc->sc_rescan_timer == 0) 3349 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3350 } 3351 if (sc->sc_tx_timer) { 3352 if (--sc->sc_tx_timer == 0 && 3353 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3354 printf("%s: transmit timeout\n", ifp->if_xname); 3355 ifp->if_oerrors++; 3356 (void)atw_init(ifp); 3357 atw_start(ifp); 3358 } 3359 } 3360 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3361 ifp->if_timer = 1; 3362 ieee80211_watchdog(ic); 3363 } 3364 3365 #ifdef ATW_DEBUG 3366 static void 3367 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3368 { 3369 struct atw_softc *sc = ifp->if_softc; 3370 struct mbuf *m; 3371 int i, noctets = 0; 3372 3373 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3374 m0->m_pkthdr.len); 3375 3376 for (m = m0; m; m = m->m_next) { 3377 if (m->m_len == 0) 3378 continue; 3379 for (i = 0; i < m->m_len; i++) { 3380 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3381 if (++noctets % 24 == 0) 3382 printf("\n"); 3383 } 3384 } 3385 printf("%s%s: %d bytes emitted\n", 3386 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3387 } 3388 #endif /* ATW_DEBUG */ 3389 3390 /* 3391 * atw_start: [ifnet interface function] 3392 * 3393 * Start packet transmission on the interface. 3394 */ 3395 void 3396 atw_start(struct ifnet *ifp) 3397 { 3398 struct atw_softc *sc = ifp->if_softc; 3399 struct ieee80211_key *k; 3400 struct ieee80211com *ic = &sc->sc_ic; 3401 struct ieee80211_node *ni; 3402 struct ieee80211_frame_min *whm; 3403 struct ieee80211_frame *wh; 3404 struct atw_frame *hh; 3405 struct mbuf *m0, *m; 3406 struct atw_txsoft *txs, *last_txs; 3407 struct atw_txdesc *txd; 3408 int do_encrypt, npkt, rate; 3409 bus_dmamap_t dmamap; 3410 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3411 3412 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3413 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3414 3415 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3416 return; 3417 3418 /* 3419 * Remember the previous number of free descriptors and 3420 * the first descriptor we'll use. 3421 */ 3422 ofree = sc->sc_txfree; 3423 firsttx = sc->sc_txnext; 3424 3425 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3426 sc->sc_dev.dv_xname, ofree, firsttx)); 3427 3428 /* 3429 * Loop through the send queue, setting up transmit descriptors 3430 * until we drain the queue, or use up all available transmit 3431 * descriptors. 3432 */ 3433 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3434 sc->sc_txfree != 0) { 3435 3436 /* 3437 * Grab a packet off the management queue, if it 3438 * is not empty. Otherwise, from the data queue. 3439 */ 3440 IF_DEQUEUE(&ic->ic_mgtq, m0); 3441 if (m0 != NULL) { 3442 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3443 m0->m_pkthdr.rcvif = NULL; 3444 } else if (ic->ic_state != IEEE80211_S_RUN) 3445 break; /* send no data until associated */ 3446 else { 3447 IFQ_DEQUEUE(&ifp->if_snd, m0); 3448 if (m0 == NULL) 3449 break; 3450 #if NBPFILTER > 0 3451 if (ifp->if_bpf != NULL) 3452 bpf_mtap(ifp->if_bpf, m0); 3453 #endif /* NBPFILTER > 0 */ 3454 ni = ieee80211_find_txnode(ic, 3455 mtod(m0, struct ether_header *)->ether_dhost); 3456 if (ni == NULL) { 3457 ifp->if_oerrors++; 3458 break; 3459 } 3460 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3461 ieee80211_free_node(ni); 3462 ifp->if_oerrors++; 3463 break; 3464 } 3465 } 3466 3467 rate = MAX(ieee80211_get_rate(ic), 2); 3468 3469 whm = mtod(m0, struct ieee80211_frame_min *); 3470 3471 do_encrypt = ((whm->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3472 if (do_encrypt) 3473 k = &ic->ic_nw_keys[ic->ic_def_txkey]; 3474 else 3475 k = NULL; 3476 3477 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3478 ic->ic_flags, ic->ic_fragthreshold, rate, 3479 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3480 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3481 m_freem(m0); 3482 break; 3483 } 3484 3485 /* XXX Misleading if fragmentation is enabled. Better 3486 * to fragment in software? 3487 */ 3488 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3489 3490 #if NBPFILTER > 0 3491 /* 3492 * Pass the packet to any BPF listeners. 3493 */ 3494 if (ic->ic_rawbpf != NULL) 3495 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3496 3497 if (sc->sc_radiobpf != NULL) { 3498 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3499 3500 tap->at_rate = rate; 3501 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3502 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3503 3504 /* TBD tap->at_flags */ 3505 3506 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3507 tap->at_ihdr.it_len, m0); 3508 } 3509 #endif /* NBPFILTER > 0 */ 3510 3511 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3512 3513 if (ni != NULL) 3514 ieee80211_free_node(ni); 3515 3516 if (m0 == NULL) { 3517 ifp->if_oerrors++; 3518 break; 3519 } 3520 3521 /* just to make sure. */ 3522 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3523 3524 if (m0 == NULL) { 3525 ifp->if_oerrors++; 3526 break; 3527 } 3528 3529 hh = mtod(m0, struct atw_frame *); 3530 wh = &hh->atw_ihdr; 3531 3532 /* Copy everything we need from the 802.11 header: 3533 * Frame Control; address 1, address 3, or addresses 3534 * 3 and 4. NIC fills in BSSID, SA. 3535 */ 3536 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3537 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3538 panic("%s: illegal WDS frame", 3539 sc->sc_dev.dv_xname); 3540 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3541 } else 3542 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3543 3544 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3545 3546 /* initialize remaining Tx parameters */ 3547 memset(&hh->u, 0, sizeof(hh->u)); 3548 3549 hh->atw_rate = rate * 5; 3550 /* XXX this could be incorrect if M_FCS. _encap should 3551 * probably strip FCS just in case it sticks around in 3552 * bridged packets. 3553 */ 3554 hh->atw_service = 0x00; /* XXX guess */ 3555 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3556 sizeof(struct atw_frame)); 3557 3558 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3559 hh->atw_rtylmt = 3; 3560 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3561 if (do_encrypt) { 3562 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3563 hh->atw_keyid = ic->ic_def_txkey; 3564 } 3565 3566 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3567 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3568 if (txs->txs_d0.d_residue) 3569 hh->atw_head_plcplen |= htole16(0x8000); 3570 if (txs->txs_dn.d_residue) 3571 hh->atw_tail_plcplen |= htole16(0x8000); 3572 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3573 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3574 3575 /* never fragment multicast frames */ 3576 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3577 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3578 } else if (sc->sc_flags & ATWF_RTSCTS) { 3579 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3580 } 3581 3582 #ifdef ATW_DEBUG 3583 hh->atw_fragnum = 0; 3584 3585 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3586 printf("%s: dst = %s, rate = 0x%02x, " 3587 "service = 0x%02x, paylen = 0x%04x\n", 3588 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3589 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3590 3591 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3592 "dur1 = 0x%04x, dur2 = 0x%04x, " 3593 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3594 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3595 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3596 hh->atw_tail_dur, hh->atw_head_dur); 3597 3598 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3599 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3600 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3601 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3602 3603 printf("%s: keyid = %d\n", 3604 sc->sc_dev.dv_xname, hh->atw_keyid); 3605 3606 atw_dump_pkt(ifp, m0); 3607 } 3608 #endif /* ATW_DEBUG */ 3609 3610 dmamap = txs->txs_dmamap; 3611 3612 /* 3613 * Load the DMA map. Copy and try (once) again if the packet 3614 * didn't fit in the alloted number of segments. 3615 */ 3616 for (first = 1; 3617 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3618 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3619 first = 0) { 3620 MGETHDR(m, M_DONTWAIT, MT_DATA); 3621 if (m == NULL) { 3622 printf("%s: unable to allocate Tx mbuf\n", 3623 sc->sc_dev.dv_xname); 3624 break; 3625 } 3626 if (m0->m_pkthdr.len > MHLEN) { 3627 MCLGET(m, M_DONTWAIT); 3628 if ((m->m_flags & M_EXT) == 0) { 3629 printf("%s: unable to allocate Tx " 3630 "cluster\n", sc->sc_dev.dv_xname); 3631 m_freem(m); 3632 break; 3633 } 3634 } 3635 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3636 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3637 m_freem(m0); 3638 m0 = m; 3639 m = NULL; 3640 } 3641 if (error != 0) { 3642 printf("%s: unable to load Tx buffer, " 3643 "error = %d\n", sc->sc_dev.dv_xname, error); 3644 m_freem(m0); 3645 break; 3646 } 3647 3648 /* 3649 * Ensure we have enough descriptors free to describe 3650 * the packet. 3651 */ 3652 if (dmamap->dm_nsegs > sc->sc_txfree) { 3653 /* 3654 * Not enough free descriptors to transmit 3655 * this packet. Unload the DMA map and 3656 * drop the packet. Notify the upper layer 3657 * that there are no more slots left. 3658 * 3659 * XXX We could allocate an mbuf and copy, but 3660 * XXX it is worth it? 3661 */ 3662 bus_dmamap_unload(sc->sc_dmat, dmamap); 3663 m_freem(m0); 3664 break; 3665 } 3666 3667 /* 3668 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3669 */ 3670 3671 /* Sync the DMA map. */ 3672 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3673 BUS_DMASYNC_PREWRITE); 3674 3675 /* XXX arbitrary retry limit; 8 because I have seen it in 3676 * use already and maybe 0 means "no tries" ! 3677 */ 3678 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3679 3680 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3681 sc->sc_dev.dv_xname, rate * 5)); 3682 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3683 3684 /* 3685 * Initialize the transmit descriptors. 3686 */ 3687 for (nexttx = sc->sc_txnext, seg = 0; 3688 seg < dmamap->dm_nsegs; 3689 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3690 /* 3691 * If this is the first descriptor we're 3692 * enqueueing, don't set the OWN bit just 3693 * yet. That could cause a race condition. 3694 * We'll do it below. 3695 */ 3696 txd = &sc->sc_txdescs[nexttx]; 3697 txd->at_ctl = ctl | 3698 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3699 3700 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3701 txd->at_flags = 3702 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3703 ATW_TXFLAG_TBS1_MASK)) | 3704 ((nexttx == (ATW_NTXDESC - 1)) 3705 ? htole32(ATW_TXFLAG_TER) : 0); 3706 lasttx = nexttx; 3707 } 3708 3709 IASSERT(lasttx != -1, ("bad lastx")); 3710 /* Set `first segment' and `last segment' appropriately. */ 3711 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3712 htole32(ATW_TXFLAG_FS); 3713 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3714 3715 #ifdef ATW_DEBUG 3716 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3717 printf(" txsoft %p transmit chain:\n", txs); 3718 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3719 printf(" descriptor %d:\n", seg); 3720 printf(" at_ctl: 0x%08x\n", 3721 le32toh(sc->sc_txdescs[seg].at_ctl)); 3722 printf(" at_flags: 0x%08x\n", 3723 le32toh(sc->sc_txdescs[seg].at_flags)); 3724 printf(" at_buf1: 0x%08x\n", 3725 le32toh(sc->sc_txdescs[seg].at_buf1)); 3726 printf(" at_buf2: 0x%08x\n", 3727 le32toh(sc->sc_txdescs[seg].at_buf2)); 3728 if (seg == lasttx) 3729 break; 3730 } 3731 } 3732 #endif 3733 3734 /* Sync the descriptors we're using. */ 3735 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3736 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3737 3738 /* 3739 * Store a pointer to the packet so we can free it later, 3740 * and remember what txdirty will be once the packet is 3741 * done. 3742 */ 3743 txs->txs_mbuf = m0; 3744 txs->txs_firstdesc = sc->sc_txnext; 3745 txs->txs_lastdesc = lasttx; 3746 txs->txs_ndescs = dmamap->dm_nsegs; 3747 3748 /* Advance the tx pointer. */ 3749 sc->sc_txfree -= dmamap->dm_nsegs; 3750 sc->sc_txnext = nexttx; 3751 3752 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3753 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3754 3755 last_txs = txs; 3756 } 3757 3758 if (sc->sc_txfree != ofree) { 3759 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3760 sc->sc_dev.dv_xname, lasttx, firsttx)); 3761 /* 3762 * Cause a transmit interrupt to happen on the 3763 * last packet we enqueued. 3764 */ 3765 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3766 ATW_CDTXSYNC(sc, lasttx, 1, 3767 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3768 3769 /* 3770 * The entire packet chain is set up. Give the 3771 * first descriptor to the chip now. 3772 */ 3773 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3774 ATW_CDTXSYNC(sc, firsttx, 1, 3775 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3776 3777 /* Wake up the transmitter. */ 3778 ATW_WRITE(sc, ATW_TDR, 0x1); 3779 3780 if (txs == NULL || sc->sc_txfree == 0) 3781 ifp->if_flags |= IFF_OACTIVE; 3782 3783 /* Set a watchdog timer in case the chip flakes out. */ 3784 sc->sc_tx_timer = 5; 3785 ifp->if_timer = 1; 3786 } 3787 } 3788 3789 /* 3790 * atw_power: 3791 * 3792 * Power management (suspend/resume) hook. 3793 */ 3794 void 3795 atw_power(int why, void *arg) 3796 { 3797 struct atw_softc *sc = arg; 3798 struct ifnet *ifp = &sc->sc_if; 3799 int s; 3800 3801 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3802 3803 s = splnet(); 3804 switch (why) { 3805 case PWR_STANDBY: 3806 /* XXX do nothing. */ 3807 break; 3808 case PWR_SUSPEND: 3809 atw_stop(ifp, 0); 3810 if (sc->sc_power != NULL) 3811 (*sc->sc_power)(sc, why); 3812 break; 3813 case PWR_RESUME: 3814 if (ifp->if_flags & IFF_UP) { 3815 if (sc->sc_power != NULL) 3816 (*sc->sc_power)(sc, why); 3817 atw_init(ifp); 3818 } 3819 break; 3820 case PWR_SOFTSUSPEND: 3821 case PWR_SOFTSTANDBY: 3822 case PWR_SOFTRESUME: 3823 break; 3824 } 3825 splx(s); 3826 } 3827 3828 /* 3829 * atw_ioctl: [ifnet interface function] 3830 * 3831 * Handle control requests from the operator. 3832 */ 3833 int 3834 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3835 { 3836 struct atw_softc *sc = ifp->if_softc; 3837 struct ifreq *ifr = (struct ifreq *)data; 3838 int s, error = 0; 3839 3840 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3841 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3842 return ENXIO; 3843 3844 s = splnet(); 3845 3846 switch (cmd) { 3847 case SIOCSIFFLAGS: 3848 if (ifp->if_flags & IFF_UP) { 3849 if (ATW_IS_ENABLED(sc)) { 3850 /* 3851 * To avoid rescanning another access point, 3852 * do not call atw_init() here. Instead, 3853 * only reflect media settings. 3854 */ 3855 atw_filter_setup(sc); 3856 } else 3857 error = atw_init(ifp); 3858 } else if (ATW_IS_ENABLED(sc)) 3859 atw_stop(ifp, 1); 3860 break; 3861 case SIOCADDMULTI: 3862 case SIOCDELMULTI: 3863 error = (cmd == SIOCADDMULTI) ? 3864 ether_addmulti(ifr, &sc->sc_ec) : 3865 ether_delmulti(ifr, &sc->sc_ec); 3866 if (error == ENETRESET) { 3867 if (ifp->if_flags & IFF_RUNNING) 3868 atw_filter_setup(sc); /* do not rescan */ 3869 error = 0; 3870 } 3871 break; 3872 default: 3873 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3874 if (error == ENETRESET || error == ERESTART) { 3875 if (is_running(ifp)) 3876 error = atw_init(ifp); 3877 else 3878 error = 0; 3879 } 3880 break; 3881 } 3882 3883 /* Try to get more packets going. */ 3884 if (ATW_IS_ENABLED(sc)) 3885 atw_start(ifp); 3886 3887 splx(s); 3888 return (error); 3889 } 3890 3891 static int 3892 atw_media_change(struct ifnet *ifp) 3893 { 3894 int error; 3895 3896 error = ieee80211_media_change(ifp); 3897 if (error == ENETRESET) { 3898 if (is_running(ifp)) 3899 error = atw_init(ifp); 3900 else 3901 error = 0; 3902 } 3903 return error; 3904 } 3905
Indexes created Mon Sep 22 13:09:51 GMT 2025