atw.c revision 1.117
1 /* $NetBSD: atw.c,v 1.117 2006/04/06 06:08:26 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.117 2006/04/06 06:08:26 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 #include <lib/libkern/libkern.h> 60 61 #include <machine/endian.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #include <net80211/ieee80211_netbsd.h> 71 #include <net80211/ieee80211_var.h> 72 #include <net80211/ieee80211_radiotap.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/ic/atwreg.h> 82 #include <dev/ic/rf3000reg.h> 83 #include <dev/ic/si4136reg.h> 84 #include <dev/ic/atwvar.h> 85 #include <dev/ic/smc93cx6var.h> 86 87 /* XXX TBD open questions 88 * 89 * 90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 92 * handle this for me? 93 * 94 */ 95 /* device attachment 96 * 97 * print TOFS[012] 98 * 99 * device initialization 100 * 101 * clear ATW_FRCTL_MAXPSP to disable max power saving 102 * set ATW_TXBR_ALCUPDATE to enable ALC 103 * set TOFS[012]? (hope not) 104 * disable rx/tx 105 * set ATW_PAR_SWR (software reset) 106 * wait for ATW_PAR_SWR clear 107 * disable interrupts 108 * ack status register 109 * enable interrupts 110 * 111 * rx/tx initialization 112 * 113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * allocate and init descriptor rings 115 * write ATW_PAR_DSL (descriptor skip length) 116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * write ATW_NAR_SQ for one/both transmit descriptor rings 119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 120 * 121 * rx/tx end 122 * 123 * stop DMA 124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 125 * flush tx w/ ATW_NAR_HF 126 * 127 * scan 128 * 129 * initialize rx/tx 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 140 141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 143 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 144 145 int atw_pseudo_milli = 1; 146 int atw_magic_delay1 = 100 * 1000; 147 int atw_magic_delay2 = 100 * 1000; 148 /* more magic multi-millisecond delays (units: microseconds) */ 149 int atw_nar_delay = 20 * 1000; 150 int atw_magic_delay4 = 10 * 1000; 151 int atw_rf_delay1 = 10 * 1000; 152 int atw_rf_delay2 = 5 * 1000; 153 int atw_plcphd_delay = 2 * 1000; 154 int atw_bbp_io_enable_delay = 20 * 1000; 155 int atw_bbp_io_disable_delay = 2 * 1000; 156 int atw_writewep_delay = 1000; 157 int atw_beacon_len_adjust = 4; 158 int atw_dwelltime = 200; 159 int atw_xindiv2 = 0; 160 161 #ifdef ATW_DEBUG 162 int atw_debug = 0; 163 164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 170 171 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 172 static void atw_print_regs(struct atw_softc *, const char *); 173 174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 175 # ifdef ATW_BBPDEBUG 176 static void atw_rf3000_print(struct atw_softc *); 177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 178 # endif /* ATW_BBPDEBUG */ 179 180 # ifdef ATW_SYNDEBUG 181 static void atw_si4126_print(struct atw_softc *); 182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 183 # endif /* ATW_SYNDEBUG */ 184 185 #else 186 #define ATW_DPRINTF(x) 187 #define ATW_DPRINTF2(x) 188 #define ATW_DPRINTF3(x) 189 #define DPRINTF(sc, x) /* nothing */ 190 #define DPRINTF2(sc, x) /* nothing */ 191 #define DPRINTF3(sc, x) /* nothing */ 192 #endif 193 194 /* ifnet methods */ 195 int atw_init(struct ifnet *); 196 int atw_ioctl(struct ifnet *, u_long, caddr_t); 197 void atw_start(struct ifnet *); 198 void atw_stop(struct ifnet *, int); 199 void atw_watchdog(struct ifnet *); 200 201 /* Device attachment */ 202 void atw_attach(struct atw_softc *); 203 int atw_detach(struct atw_softc *); 204 205 /* Rx/Tx process */ 206 int atw_add_rxbuf(struct atw_softc *, int); 207 void atw_idle(struct atw_softc *, u_int32_t); 208 void atw_rxdrain(struct atw_softc *); 209 void atw_txdrain(struct atw_softc *); 210 211 /* Device (de)activation and power state */ 212 void atw_disable(struct atw_softc *); 213 int atw_enable(struct atw_softc *); 214 void atw_power(int, void *); 215 void atw_reset(struct atw_softc *); 216 void atw_shutdown(void *); 217 218 /* Interrupt handlers */ 219 void atw_linkintr(struct atw_softc *, u_int32_t); 220 void atw_rxintr(struct atw_softc *); 221 void atw_txintr(struct atw_softc *); 222 223 /* 802.11 state machine */ 224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 225 static void atw_next_scan(void *); 226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static int atw_tune(struct atw_softc *); 229 230 /* Device initialization */ 231 static void atw_bbp_io_init(struct atw_softc *); 232 static void atw_cfp_init(struct atw_softc *); 233 static void atw_cmdr_init(struct atw_softc *); 234 static void atw_ifs_init(struct atw_softc *); 235 static void atw_nar_init(struct atw_softc *); 236 static void atw_response_times_init(struct atw_softc *); 237 static void atw_rf_reset(struct atw_softc *); 238 static void atw_test1_init(struct atw_softc *); 239 static void atw_tofs0_init(struct atw_softc *); 240 static void atw_tofs2_init(struct atw_softc *); 241 static void atw_txlmt_init(struct atw_softc *); 242 static void atw_wcsr_init(struct atw_softc *); 243 244 /* Key management */ 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(struct device *self, enum devact act) 323 { 324 struct atw_softc *sc = (struct atw_softc *)self; 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 printf("%s: device enable failed\n", 353 sc->sc_dev.dv_xname); 354 return (EIO); 355 } 356 sc->sc_flags |= ATWF_ENABLED; 357 /* Power may have been removed, and WEP keys thus 358 * reset. 359 */ 360 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 361 } 362 return (0); 363 } 364 365 /* 366 * atw_disable: 367 * 368 * Disable the ADM8211 chip. 369 */ 370 void 371 atw_disable(struct atw_softc *sc) 372 { 373 if (!ATW_IS_ENABLED(sc)) 374 return; 375 if (sc->sc_disable != NULL) 376 (*sc->sc_disable)(sc); 377 sc->sc_flags &= ~ATWF_ENABLED; 378 } 379 380 /* Returns -1 on failure. */ 381 static int 382 atw_read_srom(struct atw_softc *sc) 383 { 384 struct seeprom_descriptor sd; 385 uint32_t test0, fail_bits; 386 387 (void)memset(&sd, 0, sizeof(sd)); 388 389 test0 = ATW_READ(sc, ATW_TEST0); 390 391 switch (sc->sc_rev) { 392 case ATW_REVISION_BA: 393 case ATW_REVISION_CA: 394 fail_bits = ATW_TEST0_EPNE; 395 break; 396 default: 397 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 398 break; 399 } 400 if ((test0 & fail_bits) != 0) { 401 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 switch (test0 & ATW_TEST0_EPTYP_MASK) { 406 case ATW_TEST0_EPTYP_93c66: 407 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 408 sc->sc_sromsz = 512; 409 sd.sd_chip = C56_66; 410 break; 411 case ATW_TEST0_EPTYP_93c46: 412 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 413 sc->sc_sromsz = 128; 414 sd.sd_chip = C46; 415 break; 416 default: 417 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 418 SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 419 return -1; 420 } 421 422 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 423 424 if (sc->sc_srom == NULL) { 425 printf("%s: unable to allocate SROM buffer\n", 426 sc->sc_dev.dv_xname); 427 return -1; 428 } 429 430 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 431 432 /* ADM8211 has a single 32-bit register for controlling the 433 * 93cx6 SROM. Bit SRS enables the serial port. There is no 434 * "ready" bit. The ADM8211 input/output sense is the reverse 435 * of read_seeprom's. 436 */ 437 sd.sd_tag = sc->sc_st; 438 sd.sd_bsh = sc->sc_sh; 439 sd.sd_regsize = 4; 440 sd.sd_control_offset = ATW_SPR; 441 sd.sd_status_offset = ATW_SPR; 442 sd.sd_dataout_offset = ATW_SPR; 443 sd.sd_CK = ATW_SPR_SCLK; 444 sd.sd_CS = ATW_SPR_SCS; 445 sd.sd_DI = ATW_SPR_SDO; 446 sd.sd_DO = ATW_SPR_SDI; 447 sd.sd_MS = ATW_SPR_SRS; 448 sd.sd_RDY = 0; 449 450 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 451 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 452 free(sc->sc_srom, M_DEVBUF); 453 return -1; 454 } 455 #ifdef ATW_DEBUG 456 { 457 int i; 458 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 459 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 460 if (((i % 8) == 0) && (i != 0)) { 461 ATW_DPRINTF(("\n\t")); 462 } 463 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 464 } 465 ATW_DPRINTF(("\n")); 466 } 467 #endif /* ATW_DEBUG */ 468 return 0; 469 } 470 471 #ifdef ATW_DEBUG 472 static void 473 atw_print_regs(struct atw_softc *sc, const char *where) 474 { 475 #define PRINTREG(sc, reg) \ 476 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 477 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 478 479 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 480 481 PRINTREG(sc, ATW_PAR); 482 PRINTREG(sc, ATW_FRCTL); 483 PRINTREG(sc, ATW_TDR); 484 PRINTREG(sc, ATW_WTDP); 485 PRINTREG(sc, ATW_RDR); 486 PRINTREG(sc, ATW_WRDP); 487 PRINTREG(sc, ATW_RDB); 488 PRINTREG(sc, ATW_CSR3A); 489 PRINTREG(sc, ATW_TDBD); 490 PRINTREG(sc, ATW_TDBP); 491 PRINTREG(sc, ATW_STSR); 492 PRINTREG(sc, ATW_CSR5A); 493 PRINTREG(sc, ATW_NAR); 494 PRINTREG(sc, ATW_CSR6A); 495 PRINTREG(sc, ATW_IER); 496 PRINTREG(sc, ATW_CSR7A); 497 PRINTREG(sc, ATW_LPC); 498 PRINTREG(sc, ATW_TEST1); 499 PRINTREG(sc, ATW_SPR); 500 PRINTREG(sc, ATW_TEST0); 501 PRINTREG(sc, ATW_WCSR); 502 PRINTREG(sc, ATW_WPDR); 503 PRINTREG(sc, ATW_GPTMR); 504 PRINTREG(sc, ATW_GPIO); 505 PRINTREG(sc, ATW_BBPCTL); 506 PRINTREG(sc, ATW_SYNCTL); 507 PRINTREG(sc, ATW_PLCPHD); 508 PRINTREG(sc, ATW_MMIWADDR); 509 PRINTREG(sc, ATW_MMIRADDR1); 510 PRINTREG(sc, ATW_MMIRADDR2); 511 PRINTREG(sc, ATW_TXBR); 512 PRINTREG(sc, ATW_CSR15A); 513 PRINTREG(sc, ATW_ALCSTAT); 514 PRINTREG(sc, ATW_TOFS2); 515 PRINTREG(sc, ATW_CMDR); 516 PRINTREG(sc, ATW_PCIC); 517 PRINTREG(sc, ATW_PMCSR); 518 PRINTREG(sc, ATW_PAR0); 519 PRINTREG(sc, ATW_PAR1); 520 PRINTREG(sc, ATW_MAR0); 521 PRINTREG(sc, ATW_MAR1); 522 PRINTREG(sc, ATW_ATIMDA0); 523 PRINTREG(sc, ATW_ABDA1); 524 PRINTREG(sc, ATW_BSSID0); 525 PRINTREG(sc, ATW_TXLMT); 526 PRINTREG(sc, ATW_MIBCNT); 527 PRINTREG(sc, ATW_BCNT); 528 PRINTREG(sc, ATW_TSFTH); 529 PRINTREG(sc, ATW_TSC); 530 PRINTREG(sc, ATW_SYNRF); 531 PRINTREG(sc, ATW_BPLI); 532 PRINTREG(sc, ATW_CAP0); 533 PRINTREG(sc, ATW_CAP1); 534 PRINTREG(sc, ATW_RMD); 535 PRINTREG(sc, ATW_CFPP); 536 PRINTREG(sc, ATW_TOFS0); 537 PRINTREG(sc, ATW_TOFS1); 538 PRINTREG(sc, ATW_IFST); 539 PRINTREG(sc, ATW_RSPT); 540 PRINTREG(sc, ATW_TSFTL); 541 PRINTREG(sc, ATW_WEPCTL); 542 PRINTREG(sc, ATW_WESK); 543 PRINTREG(sc, ATW_WEPCNT); 544 PRINTREG(sc, ATW_MACTEST); 545 PRINTREG(sc, ATW_FER); 546 PRINTREG(sc, ATW_FEMR); 547 PRINTREG(sc, ATW_FPSR); 548 PRINTREG(sc, ATW_FFER); 549 #undef PRINTREG 550 } 551 #endif /* ATW_DEBUG */ 552 553 /* 554 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 555 */ 556 void 557 atw_attach(struct atw_softc *sc) 558 { 559 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 561 }; 562 struct ieee80211com *ic = &sc->sc_ic; 563 struct ifnet *ifp = &sc->sc_if; 564 int country_code, error, i, nrate, srom_major; 565 u_int32_t reg; 566 static const char *type_strings[] = {"Intersil (not supported)", 567 "RFMD", "Marvel (not supported)"}; 568 569 sc->sc_txth = atw_txthresh_tab_lo; 570 571 SIMPLEQ_INIT(&sc->sc_txfreeq); 572 SIMPLEQ_INIT(&sc->sc_txdirtyq); 573 574 #ifdef ATW_DEBUG 575 atw_print_regs(sc, "atw_attach"); 576 #endif /* ATW_DEBUG */ 577 578 /* 579 * Allocate the control data structures, and create and load the 580 * DMA map for it. 581 */ 582 if ((error = bus_dmamem_alloc(sc->sc_dmat, 583 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 584 1, &sc->sc_cdnseg, 0)) != 0) { 585 printf("%s: unable to allocate control data, error = %d\n", 586 sc->sc_dev.dv_xname, error); 587 goto fail_0; 588 } 589 590 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 591 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 592 BUS_DMA_COHERENT)) != 0) { 593 printf("%s: unable to map control data, error = %d\n", 594 sc->sc_dev.dv_xname, error); 595 goto fail_1; 596 } 597 598 if ((error = bus_dmamap_create(sc->sc_dmat, 599 sizeof(struct atw_control_data), 1, 600 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 601 printf("%s: unable to create control data DMA map, " 602 "error = %d\n", sc->sc_dev.dv_xname, error); 603 goto fail_2; 604 } 605 606 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 607 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 608 0)) != 0) { 609 printf("%s: unable to load control data DMA map, error = %d\n", 610 sc->sc_dev.dv_xname, error); 611 goto fail_3; 612 } 613 614 /* 615 * Create the transmit buffer DMA maps. 616 */ 617 sc->sc_ntxsegs = ATW_NTXSEGS; 618 for (i = 0; i < ATW_TXQUEUELEN; i++) { 619 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 620 sc->sc_ntxsegs, MCLBYTES, 0, 0, 621 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 622 printf("%s: unable to create tx DMA map %d, " 623 "error = %d\n", sc->sc_dev.dv_xname, i, error); 624 goto fail_4; 625 } 626 } 627 628 /* 629 * Create the receive buffer DMA maps. 630 */ 631 for (i = 0; i < ATW_NRXDESC; i++) { 632 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 633 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 634 printf("%s: unable to create rx DMA map %d, " 635 "error = %d\n", sc->sc_dev.dv_xname, i, error); 636 goto fail_5; 637 } 638 } 639 for (i = 0; i < ATW_NRXDESC; i++) { 640 sc->sc_rxsoft[i].rxs_mbuf = NULL; 641 } 642 643 switch (sc->sc_rev) { 644 case ATW_REVISION_AB: 645 case ATW_REVISION_AF: 646 sc->sc_sramlen = ATW_SRAM_A_SIZE; 647 break; 648 case ATW_REVISION_BA: 649 case ATW_REVISION_CA: 650 sc->sc_sramlen = ATW_SRAM_B_SIZE; 651 break; 652 } 653 654 /* Reset the chip to a known state. */ 655 atw_reset(sc); 656 657 if (atw_read_srom(sc) == -1) 658 return; 659 660 sc->sc_rftype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 661 ATW_SR_RFTYPE_MASK); 662 663 sc->sc_bbptype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 664 ATW_SR_BBPTYPE_MASK); 665 666 if (sc->sc_rftype >= __arraycount(type_strings)) { 667 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 668 return; 669 } 670 if (sc->sc_bbptype >= __arraycount(type_strings)) { 671 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 672 return; 673 } 674 675 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 676 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 677 678 /* XXX There exists a Linux driver which seems to use RFType = 0 for 679 * MARVEL. My bug, or theirs? 680 */ 681 682 reg = SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 683 684 switch (sc->sc_rftype) { 685 case ATW_RFTYPE_INTERSIL: 686 reg |= ATW_SYNCTL_CS1; 687 break; 688 case ATW_RFTYPE_RFMD: 689 reg |= ATW_SYNCTL_CS0; 690 break; 691 case ATW_RFTYPE_MARVEL: 692 break; 693 } 694 695 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 696 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 697 698 reg = SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 699 700 switch (sc->sc_bbptype) { 701 case ATW_BBPTYPE_INTERSIL: 702 reg |= ATW_BBPCTL_TWI; 703 break; 704 case ATW_BBPTYPE_RFMD: 705 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 706 ATW_BBPCTL_CCA_ACTLO; 707 break; 708 case ATW_BBPTYPE_MARVEL: 709 break; 710 case ATW_C_BBPTYPE_RFMD: 711 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 712 sc->sc_dev.dv_xname); 713 break; 714 } 715 716 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 717 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 718 719 /* 720 * From this point forward, the attachment cannot fail. A failure 721 * before this point releases all resources that may have been 722 * allocated. 723 */ 724 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 725 726 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 727 htole16(sc->sc_srom[ATW_SR_MAC00]), 728 htole16(sc->sc_srom[ATW_SR_MAC01]), 729 htole16(sc->sc_srom[ATW_SR_MAC10]))); 730 731 srom_major = SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 732 ATW_SR_MAJOR_MASK); 733 734 if (srom_major < 2) 735 sc->sc_rf3000_options1 = 0; 736 else if (sc->sc_rev == ATW_REVISION_BA) { 737 sc->sc_rf3000_options1 = 738 SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 739 ATW_SR_CR28_MASK); 740 } else 741 sc->sc_rf3000_options1 = 0; 742 743 sc->sc_rf3000_options2 = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 744 ATW_SR_CR29_MASK); 745 746 country_code = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 747 ATW_SR_CTRY_MASK); 748 749 #define ADD_CHANNEL(_ic, _chan) do { \ 750 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 751 _ic->ic_channels[_chan].ic_freq = \ 752 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 753 } while (0) 754 755 /* Find available channels */ 756 switch (country_code) { 757 case COUNTRY_MMK2: /* 1-14 */ 758 ADD_CHANNEL(ic, 14); 759 /*FALLTHROUGH*/ 760 case COUNTRY_ETSI: /* 1-13 */ 761 for (i = 1; i <= 13; i++) 762 ADD_CHANNEL(ic, i); 763 break; 764 case COUNTRY_FCC: /* 1-11 */ 765 case COUNTRY_IC: /* 1-11 */ 766 for (i = 1; i <= 11; i++) 767 ADD_CHANNEL(ic, i); 768 break; 769 case COUNTRY_MMK: /* 14 */ 770 ADD_CHANNEL(ic, 14); 771 break; 772 case COUNTRY_FRANCE: /* 10-13 */ 773 for (i = 10; i <= 13; i++) 774 ADD_CHANNEL(ic, i); 775 break; 776 default: /* assume channels 10-11 */ 777 case COUNTRY_SPAIN: /* 10-11 */ 778 for (i = 10; i <= 11; i++) 779 ADD_CHANNEL(ic, i); 780 break; 781 } 782 783 /* Read the MAC address. */ 784 reg = ATW_READ(sc, ATW_PAR0); 785 ic->ic_myaddr[0] = SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 786 ic->ic_myaddr[1] = SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 787 ic->ic_myaddr[2] = SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 788 ic->ic_myaddr[3] = SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 789 reg = ATW_READ(sc, ATW_PAR1); 790 ic->ic_myaddr[4] = SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 791 ic->ic_myaddr[5] = SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 792 793 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 794 printf(" could not get mac address, attach failed\n"); 795 return; 796 } 797 798 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 799 800 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 801 ifp->if_softc = sc; 802 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 803 IFF_NOTRAILERS; 804 ifp->if_ioctl = atw_ioctl; 805 ifp->if_start = atw_start; 806 ifp->if_watchdog = atw_watchdog; 807 ifp->if_init = atw_init; 808 ifp->if_stop = atw_stop; 809 IFQ_SET_READY(&ifp->if_snd); 810 811 ic->ic_ifp = ifp; 812 ic->ic_phytype = IEEE80211_T_DS; 813 ic->ic_opmode = IEEE80211_M_STA; 814 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 815 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 816 817 nrate = 0; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 822 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 823 824 /* 825 * Call MI attach routines. 826 */ 827 828 if_attach(ifp); 829 ieee80211_ifattach(ic); 830 831 sc->sc_newstate = ic->ic_newstate; 832 ic->ic_newstate = atw_newstate; 833 834 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 835 ic->ic_recv_mgmt = atw_recv_mgmt; 836 837 sc->sc_node_free = ic->ic_node_free; 838 ic->ic_node_free = atw_node_free; 839 840 sc->sc_node_alloc = ic->ic_node_alloc; 841 ic->ic_node_alloc = atw_node_alloc; 842 843 ic->ic_crypto.cs_key_delete = atw_key_delete; 844 ic->ic_crypto.cs_key_set = atw_key_set; 845 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 846 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 847 848 /* possibly we should fill in our own sc_send_prresp, since 849 * the ADM8211 is probably sending probe responses in ad hoc 850 * mode. 851 */ 852 853 /* complete initialization */ 854 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 855 callout_init(&sc->sc_scan_ch); 856 857 #if NBPFILTER > 0 858 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 859 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 860 #endif 861 862 /* 863 * Make sure the interface is shutdown during reboot. 864 */ 865 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 866 if (sc->sc_sdhook == NULL) 867 printf("%s: WARNING: unable to establish shutdown hook\n", 868 sc->sc_dev.dv_xname); 869 870 /* 871 * Add a suspend hook to make sure we come back up after a 872 * resume. 873 */ 874 sc->sc_powerhook = powerhook_establish(atw_power, sc); 875 if (sc->sc_powerhook == NULL) 876 printf("%s: WARNING: unable to establish power hook\n", 877 sc->sc_dev.dv_xname); 878 879 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 880 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 881 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 882 883 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 884 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 885 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 886 887 ieee80211_announce(ic); 888 return; 889 890 /* 891 * Free any resources we've allocated during the failed attach 892 * attempt. Do this in reverse order and fall through. 893 */ 894 fail_5: 895 for (i = 0; i < ATW_NRXDESC; i++) { 896 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 897 continue; 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 899 } 900 fail_4: 901 for (i = 0; i < ATW_TXQUEUELEN; i++) { 902 if (sc->sc_txsoft[i].txs_dmamap == NULL) 903 continue; 904 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 905 } 906 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 907 fail_3: 908 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 909 fail_2: 910 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 911 sizeof(struct atw_control_data)); 912 fail_1: 913 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 914 fail_0: 915 return; 916 } 917 918 static struct ieee80211_node * 919 atw_node_alloc(struct ieee80211_node_table *nt) 920 { 921 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 922 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 923 924 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 925 return ni; 926 } 927 928 static void 929 atw_node_free(struct ieee80211_node *ni) 930 { 931 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 932 933 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 934 ether_sprintf(ni->ni_bssid))); 935 (*sc->sc_node_free)(ni); 936 } 937 938 939 static void 940 atw_test1_reset(struct atw_softc *sc) 941 { 942 switch (sc->sc_rev) { 943 case ATW_REVISION_BA: 944 if (1 /* XXX condition on transceiver type */) { 945 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 946 } 947 break; 948 case ATW_REVISION_CA: 949 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 950 break; 951 default: 952 break; 953 } 954 } 955 956 /* 957 * atw_reset: 958 * 959 * Perform a soft reset on the ADM8211. 960 */ 961 void 962 atw_reset(struct atw_softc *sc) 963 { 964 int i; 965 uint32_t lpc; 966 967 ATW_WRITE(sc, ATW_NAR, 0x0); 968 DELAY(atw_nar_delay); 969 970 /* Reference driver has a cryptic remark indicating that this might 971 * power-on the chip. I know that it turns off power-saving.... 972 */ 973 ATW_WRITE(sc, ATW_FRCTL, 0x0); 974 975 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 976 977 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 978 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 979 break; 980 DELAY(atw_pseudo_milli); 981 } 982 983 /* ... and then pause 100ms longer for good measure. */ 984 DELAY(atw_magic_delay1); 985 986 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 987 988 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 989 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 990 991 /* 992 * Initialize the PCI Access Register. 993 */ 994 sc->sc_busmode = ATW_PAR_PBL_8DW; 995 996 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 997 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 998 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 999 1000 atw_test1_reset(sc); 1001 1002 /* Turn off maximum power saving, etc. */ 1003 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1004 1005 DELAY(atw_magic_delay2); 1006 1007 /* Recall EEPROM. */ 1008 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1009 1010 DELAY(atw_magic_delay4); 1011 1012 lpc = ATW_READ(sc, ATW_LPC); 1013 1014 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1015 1016 /* A reset seems to affect the SRAM contents, so put them into 1017 * a known state. 1018 */ 1019 atw_clear_sram(sc); 1020 1021 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1022 } 1023 1024 static void 1025 atw_clear_sram(struct atw_softc *sc) 1026 { 1027 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1028 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1029 /* XXX not for revision 0x20. */ 1030 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1031 } 1032 1033 /* TBD atw_init 1034 * 1035 * set MAC based on ic->ic_bss->myaddr 1036 * write WEP keys 1037 * set TX rate 1038 */ 1039 1040 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1041 * without receiving a beacon with the preferred BSSID & SSID. 1042 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1043 */ 1044 static void 1045 atw_wcsr_init(struct atw_softc *sc) 1046 { 1047 uint32_t wcsr; 1048 1049 wcsr = ATW_READ(sc, ATW_WCSR); 1050 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1051 wcsr |= SHIFTIN(7, ATW_WCSR_BLN_MASK); 1052 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1053 1054 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1055 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1056 } 1057 1058 /* Turn off power management. Set Rx store-and-forward mode. */ 1059 static void 1060 atw_cmdr_init(struct atw_softc *sc) 1061 { 1062 uint32_t cmdr; 1063 cmdr = ATW_READ(sc, ATW_CMDR); 1064 cmdr &= ~ATW_CMDR_APM; 1065 cmdr |= ATW_CMDR_RTE; 1066 cmdr &= ~ATW_CMDR_DRT_MASK; 1067 cmdr |= ATW_CMDR_DRT_SF; 1068 1069 ATW_WRITE(sc, ATW_CMDR, cmdr); 1070 } 1071 1072 static void 1073 atw_tofs2_init(struct atw_softc *sc) 1074 { 1075 uint32_t tofs2; 1076 /* XXX this magic can probably be figured out from the RFMD docs */ 1077 #ifndef ATW_REFSLAVE 1078 tofs2 = SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1079 SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1080 SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1081 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1082 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1083 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1084 SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1085 SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1086 #else 1087 /* XXX new magic from reference driver source */ 1088 tofs2 = SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1089 SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1090 SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1091 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1092 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1093 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1094 SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1095 SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1096 #endif 1097 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1098 } 1099 1100 static void 1101 atw_nar_init(struct atw_softc *sc) 1102 { 1103 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1104 } 1105 1106 static void 1107 atw_txlmt_init(struct atw_softc *sc) 1108 { 1109 ATW_WRITE(sc, ATW_TXLMT, SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1110 SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1111 } 1112 1113 static void 1114 atw_test1_init(struct atw_softc *sc) 1115 { 1116 uint32_t test1; 1117 1118 test1 = ATW_READ(sc, ATW_TEST1); 1119 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1120 /* XXX magic 0x1 */ 1121 test1 |= SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1122 ATW_WRITE(sc, ATW_TEST1, test1); 1123 } 1124 1125 static void 1126 atw_rf_reset(struct atw_softc *sc) 1127 { 1128 /* XXX this resets an Intersil RF front-end? */ 1129 /* TBD condition on Intersil RFType? */ 1130 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1131 DELAY(atw_rf_delay1); 1132 ATW_WRITE(sc, ATW_SYNRF, 0); 1133 DELAY(atw_rf_delay2); 1134 } 1135 1136 /* Set 16 TU max duration for the contention-free period (CFP). */ 1137 static void 1138 atw_cfp_init(struct atw_softc *sc) 1139 { 1140 uint32_t cfpp; 1141 1142 cfpp = ATW_READ(sc, ATW_CFPP); 1143 cfpp &= ~ATW_CFPP_CFPMD; 1144 cfpp |= SHIFTIN(16, ATW_CFPP_CFPMD); 1145 ATW_WRITE(sc, ATW_CFPP, cfpp); 1146 } 1147 1148 static void 1149 atw_tofs0_init(struct atw_softc *sc) 1150 { 1151 /* XXX I guess that the Cardbus clock is 22 MHz? 1152 * I am assuming that the role of ATW_TOFS0_USCNT is 1153 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1154 * very clear on this point. It says in the datasheet that it is 1155 * possible for the ADM8211 to accomodate bus speeds between 22 MHz 1156 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1157 * these values. These values are also the power-on default. 1158 */ 1159 ATW_WRITE(sc, ATW_TOFS0, 1160 SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1161 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1162 } 1163 1164 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1165 static void 1166 atw_ifs_init(struct atw_softc *sc) 1167 { 1168 uint32_t ifst; 1169 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1170 * Go figure. 1171 */ 1172 ifst = SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1173 SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1174 ATW_IFST_SIFS_MASK) | 1175 SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1176 SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1177 1178 ATW_WRITE(sc, ATW_IFST, ifst); 1179 } 1180 1181 static void 1182 atw_response_times_init(struct atw_softc *sc) 1183 { 1184 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1185 * indicate that the MAC expects at least SIFS + MIRT microseconds 1186 * to pass after it transmits a frame that requires a response; 1187 * it waits at most SIFS + MART microseconds for the response. 1188 * Surely this is not the ACK timeout? 1189 */ 1190 ATW_WRITE(sc, ATW_RSPT, SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1191 SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1192 } 1193 1194 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1195 * engines read and write baseband registers after Rx and before 1196 * Tx, respectively. 1197 */ 1198 static void 1199 atw_bbp_io_init(struct atw_softc *sc) 1200 { 1201 uint32_t mmiraddr2; 1202 1203 /* XXX The reference driver does this, but is it *really* 1204 * necessary? 1205 */ 1206 switch (sc->sc_rev) { 1207 case ATW_REVISION_AB: 1208 case ATW_REVISION_AF: 1209 mmiraddr2 = 0x0; 1210 break; 1211 default: 1212 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1213 mmiraddr2 &= 1214 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1215 break; 1216 } 1217 1218 switch (sc->sc_bbptype) { 1219 case ATW_BBPTYPE_INTERSIL: 1220 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1221 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1222 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1223 break; 1224 case ATW_BBPTYPE_MARVEL: 1225 /* TBD find out the Marvel settings. */ 1226 break; 1227 case ATW_BBPTYPE_RFMD: 1228 default: 1229 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1230 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1231 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1232 break; 1233 } 1234 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1235 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1236 } 1237 1238 /* 1239 * atw_init: [ ifnet interface function ] 1240 * 1241 * Initialize the interface. Must be called at splnet(). 1242 */ 1243 int 1244 atw_init(struct ifnet *ifp) 1245 { 1246 struct atw_softc *sc = ifp->if_softc; 1247 struct ieee80211com *ic = &sc->sc_ic; 1248 struct atw_txsoft *txs; 1249 struct atw_rxsoft *rxs; 1250 int i, error = 0; 1251 1252 if ((error = atw_enable(sc)) != 0) 1253 goto out; 1254 1255 /* 1256 * Cancel any pending I/O. This also resets. 1257 */ 1258 atw_stop(ifp, 0); 1259 1260 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1261 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1262 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1263 1264 atw_wcsr_init(sc); 1265 1266 atw_cmdr_init(sc); 1267 1268 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1269 * 1270 * XXX Set transmit power for ATIM, RTS, Beacon. 1271 */ 1272 ATW_WRITE(sc, ATW_PLCPHD, SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1273 SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1274 1275 atw_tofs2_init(sc); 1276 1277 atw_nar_init(sc); 1278 1279 atw_txlmt_init(sc); 1280 1281 atw_test1_init(sc); 1282 1283 atw_rf_reset(sc); 1284 1285 atw_cfp_init(sc); 1286 1287 atw_tofs0_init(sc); 1288 1289 atw_ifs_init(sc); 1290 1291 /* XXX Fall asleep after one second of inactivity. 1292 * XXX A frame may only dribble in for 65536us. 1293 */ 1294 ATW_WRITE(sc, ATW_RMD, 1295 SHIFTIN(1, ATW_RMD_PCNT) | SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1296 1297 atw_response_times_init(sc); 1298 1299 atw_bbp_io_init(sc); 1300 1301 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1302 1303 if ((error = atw_rf3000_init(sc)) != 0) 1304 goto out; 1305 1306 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1307 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1308 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1309 1310 /* 1311 * Initialize the transmit descriptor ring. 1312 */ 1313 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1314 for (i = 0; i < ATW_NTXDESC; i++) { 1315 sc->sc_txdescs[i].at_ctl = 0; 1316 /* no transmit chaining */ 1317 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1318 sc->sc_txdescs[i].at_buf2 = 1319 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1320 } 1321 /* use ring mode */ 1322 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1323 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1324 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1325 sc->sc_txfree = ATW_NTXDESC; 1326 sc->sc_txnext = 0; 1327 1328 /* 1329 * Initialize the transmit job descriptors. 1330 */ 1331 SIMPLEQ_INIT(&sc->sc_txfreeq); 1332 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1333 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1334 txs = &sc->sc_txsoft[i]; 1335 txs->txs_mbuf = NULL; 1336 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1337 } 1338 1339 /* 1340 * Initialize the receive descriptor and receive job 1341 * descriptor rings. 1342 */ 1343 for (i = 0; i < ATW_NRXDESC; i++) { 1344 rxs = &sc->sc_rxsoft[i]; 1345 if (rxs->rxs_mbuf == NULL) { 1346 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1347 printf("%s: unable to allocate or map rx " 1348 "buffer %d, error = %d\n", 1349 sc->sc_dev.dv_xname, i, error); 1350 /* 1351 * XXX Should attempt to run with fewer receive 1352 * XXX buffers instead of just failing. 1353 */ 1354 atw_rxdrain(sc); 1355 goto out; 1356 } 1357 } else 1358 ATW_INIT_RXDESC(sc, i); 1359 } 1360 sc->sc_rxptr = 0; 1361 1362 /* 1363 * Initialize the interrupt mask and enable interrupts. 1364 */ 1365 /* normal interrupts */ 1366 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1367 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1368 1369 /* abnormal interrupts */ 1370 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1371 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1372 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1373 1374 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1375 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1376 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1377 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1378 ATW_INTR_TRT; 1379 1380 sc->sc_linkint_mask &= sc->sc_inten; 1381 sc->sc_rxint_mask &= sc->sc_inten; 1382 sc->sc_txint_mask &= sc->sc_inten; 1383 1384 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1385 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1386 1387 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1388 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1389 1390 /* 1391 * Give the transmit and receive rings to the ADM8211. 1392 */ 1393 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1394 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1395 1396 sc->sc_txthresh = 0; 1397 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1398 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1399 1400 /* common 802.11 configuration */ 1401 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1402 switch (ic->ic_opmode) { 1403 case IEEE80211_M_STA: 1404 break; 1405 case IEEE80211_M_AHDEMO: /* XXX */ 1406 case IEEE80211_M_IBSS: 1407 ic->ic_flags |= IEEE80211_F_IBSSON; 1408 /*FALLTHROUGH*/ 1409 case IEEE80211_M_HOSTAP: /* XXX */ 1410 break; 1411 case IEEE80211_M_MONITOR: /* XXX */ 1412 break; 1413 } 1414 1415 switch (ic->ic_opmode) { 1416 case IEEE80211_M_AHDEMO: 1417 case IEEE80211_M_HOSTAP: 1418 #ifndef IEEE80211_NO_HOSTAP 1419 ic->ic_bss->ni_intval = ic->ic_lintval; 1420 ic->ic_bss->ni_rssi = 0; 1421 ic->ic_bss->ni_rstamp = 0; 1422 #endif /* !IEEE80211_NO_HOSTAP */ 1423 break; 1424 default: /* XXX */ 1425 break; 1426 } 1427 1428 sc->sc_wepctl = 0; 1429 1430 atw_write_ssid(sc); 1431 atw_write_sup_rates(sc); 1432 atw_write_wep(sc); 1433 1434 ic->ic_state = IEEE80211_S_INIT; 1435 1436 /* 1437 * Set the receive filter. This will start the transmit and 1438 * receive processes. 1439 */ 1440 atw_filter_setup(sc); 1441 1442 /* 1443 * Start the receive process. 1444 */ 1445 ATW_WRITE(sc, ATW_RDR, 0x1); 1446 1447 /* 1448 * Note that the interface is now running. 1449 */ 1450 ifp->if_flags |= IFF_RUNNING; 1451 ifp->if_flags &= ~IFF_OACTIVE; 1452 1453 /* send no beacons, yet. */ 1454 atw_start_beacon(sc, 0); 1455 1456 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1457 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1458 else 1459 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1460 out: 1461 if (error) { 1462 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1463 sc->sc_tx_timer = 0; 1464 ifp->if_timer = 0; 1465 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1466 } 1467 #ifdef ATW_DEBUG 1468 atw_print_regs(sc, "end of init"); 1469 #endif /* ATW_DEBUG */ 1470 1471 return (error); 1472 } 1473 1474 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1475 * 0: MAC control of RF3000/Si4126. 1476 * 1477 * Applies power, or selects RF front-end? Sets reset condition. 1478 * 1479 * TBD support non-RFMD BBP, non-SiLabs synth. 1480 */ 1481 static void 1482 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1483 { 1484 if (enable) { 1485 ATW_WRITE(sc, ATW_SYNRF, 1486 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1487 DELAY(atw_bbp_io_enable_delay); 1488 } else { 1489 ATW_WRITE(sc, ATW_SYNRF, 0); 1490 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1491 } 1492 } 1493 1494 static int 1495 atw_tune(struct atw_softc *sc) 1496 { 1497 int rc; 1498 u_int chan; 1499 struct ieee80211com *ic = &sc->sc_ic; 1500 1501 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1502 if (chan == IEEE80211_CHAN_ANY) 1503 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1504 1505 if (chan == sc->sc_cur_chan) 1506 return 0; 1507 1508 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1509 sc->sc_cur_chan, chan)); 1510 1511 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1512 1513 atw_si4126_tune(sc, chan); 1514 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1515 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1516 chan); 1517 1518 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1519 DELAY(atw_nar_delay); 1520 ATW_WRITE(sc, ATW_RDR, 0x1); 1521 1522 if (rc == 0) 1523 sc->sc_cur_chan = chan; 1524 1525 return rc; 1526 } 1527 1528 #ifdef ATW_SYNDEBUG 1529 static void 1530 atw_si4126_print(struct atw_softc *sc) 1531 { 1532 struct ifnet *ifp = &sc->sc_if; 1533 u_int addr, val; 1534 1535 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1536 return; 1537 1538 for (addr = 0; addr <= 8; addr++) { 1539 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1540 if (atw_si4126_read(sc, addr, &val) == 0) { 1541 printf("<unknown> (quitting print-out)\n"); 1542 break; 1543 } 1544 printf("%05x\n", val); 1545 } 1546 } 1547 #endif /* ATW_SYNDEBUG */ 1548 1549 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1550 * 1551 * The RF/IF synthesizer produces two reference frequencies for 1552 * the RF2948B transceiver. The first frequency the RF2948B requires 1553 * is two times the so-called "intermediate frequency" (IF). Since 1554 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1555 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1556 * frequency required by the transceiver is the radio frequency 1557 * (RF). This is a superheterodyne transceiver; for f(chan) the 1558 * center frequency of the channel we are tuning, RF = f(chan) - 1559 * IF. 1560 * 1561 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1562 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1563 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1564 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1565 */ 1566 static void 1567 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1568 { 1569 u_int mhz; 1570 u_int R; 1571 u_int32_t gpio; 1572 u_int16_t gain; 1573 1574 #ifdef ATW_SYNDEBUG 1575 atw_si4126_print(sc); 1576 #endif /* ATW_SYNDEBUG */ 1577 1578 if (chan == 14) 1579 mhz = 2484; 1580 else 1581 mhz = 2412 + 5 * (chan - 1); 1582 1583 /* Tune IF to 748 MHz to suit the IF LO input of the 1584 * RF2494B, which is 2 x IF. No need to set an IF divider 1585 * because an IF in 526 MHz - 952 MHz is allowed. 1586 * 1587 * XIN is 44.000 MHz, so divide it by two to get allowable 1588 * range of 2-25 MHz. SiLabs tells me that this is not 1589 * strictly necessary. 1590 */ 1591 1592 if (atw_xindiv2) 1593 R = 44; 1594 else 1595 R = 88; 1596 1597 /* Power-up RF, IF synthesizers. */ 1598 atw_si4126_write(sc, SI4126_POWER, 1599 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1600 1601 /* set LPWR, too? */ 1602 atw_si4126_write(sc, SI4126_MAIN, 1603 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1604 1605 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1606 * set KP2 to 1. 1607 * 1608 * REFDIF This is different from the reference driver, which 1609 * always sets SI4126_GAIN to 0. 1610 */ 1611 gain = SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1612 1613 atw_si4126_write(sc, SI4126_GAIN, gain); 1614 1615 /* XIN = 44 MHz. 1616 * 1617 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1618 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1619 * 1620 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1621 * so that 1496/88 * 44 MHz = 748 MHz. 1622 */ 1623 atw_si4126_write(sc, SI4126_IFN, 1496); 1624 1625 atw_si4126_write(sc, SI4126_IFR, R); 1626 1627 #ifndef ATW_REFSLAVE 1628 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1629 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1630 * which has no RF1! 1631 */ 1632 atw_si4126_write(sc, SI4126_RF1R, R); 1633 1634 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1635 #endif 1636 1637 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1638 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1639 * Now let's multiply it to mhz. So mhz - IF = N. 1640 */ 1641 atw_si4126_write(sc, SI4126_RF2R, R); 1642 1643 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1644 1645 /* wait 100us from power-up for RF, IF to settle */ 1646 DELAY(100); 1647 1648 gpio = ATW_READ(sc, ATW_GPIO); 1649 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1650 gpio |= SHIFTIN(1, ATW_GPIO_EN_MASK); 1651 1652 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1653 /* Set a Prism RF front-end to a special mode for channel 14? 1654 * 1655 * Apparently the SMC2635W needs this, although I don't think 1656 * it has a Prism RF. 1657 */ 1658 gpio |= SHIFTIN(1, ATW_GPIO_O_MASK); 1659 } 1660 ATW_WRITE(sc, ATW_GPIO, gpio); 1661 1662 #ifdef ATW_SYNDEBUG 1663 atw_si4126_print(sc); 1664 #endif /* ATW_SYNDEBUG */ 1665 } 1666 1667 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1668 * diversity. 1669 * 1670 * !!! 1671 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1672 * !!! 1673 */ 1674 static int 1675 atw_rf3000_init(struct atw_softc *sc) 1676 { 1677 int rc = 0; 1678 1679 atw_bbp_io_enable(sc, 1); 1680 1681 /* CCA is acquisition sensitive */ 1682 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1683 SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1684 1685 if (rc != 0) 1686 goto out; 1687 1688 /* enable diversity */ 1689 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1690 1691 if (rc != 0) 1692 goto out; 1693 1694 /* sensible setting from a binary-only driver */ 1695 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1696 SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1697 1698 if (rc != 0) 1699 goto out; 1700 1701 /* magic from a binary-only driver */ 1702 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1703 SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1704 1705 if (rc != 0) 1706 goto out; 1707 1708 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1709 1710 if (rc != 0) 1711 goto out; 1712 1713 /* XXX Reference driver remarks that Abocom sets this to 50. 1714 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1715 * in the "reserved" area of register RF3000_OPTIONS1. 1716 */ 1717 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1718 1719 if (rc != 0) 1720 goto out; 1721 1722 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1723 1724 if (rc != 0) 1725 goto out; 1726 1727 out: 1728 atw_bbp_io_enable(sc, 0); 1729 return rc; 1730 } 1731 1732 #ifdef ATW_BBPDEBUG 1733 static void 1734 atw_rf3000_print(struct atw_softc *sc) 1735 { 1736 struct ifnet *ifp = &sc->sc_if; 1737 u_int addr, val; 1738 1739 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1740 return; 1741 1742 for (addr = 0x01; addr <= 0x15; addr++) { 1743 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1744 if (atw_rf3000_read(sc, addr, &val) != 0) { 1745 printf("<unknown> (quitting print-out)\n"); 1746 break; 1747 } 1748 printf("%08x\n", val); 1749 } 1750 } 1751 #endif /* ATW_BBPDEBUG */ 1752 1753 /* Set the power settings on the BBP for channel `chan'. */ 1754 static int 1755 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1756 { 1757 int rc = 0; 1758 u_int32_t reg; 1759 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1760 1761 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1762 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1763 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1764 1765 /* odd channels: LSB, even channels: MSB */ 1766 if (chan % 2 == 1) { 1767 txpower &= 0xFF; 1768 lpf_cutoff &= 0xFF; 1769 lna_gs_thresh &= 0xFF; 1770 } else { 1771 txpower >>= 8; 1772 lpf_cutoff >>= 8; 1773 lna_gs_thresh >>= 8; 1774 } 1775 1776 #ifdef ATW_BBPDEBUG 1777 atw_rf3000_print(sc); 1778 #endif /* ATW_BBPDEBUG */ 1779 1780 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1781 "lna_gs_thresh %02x\n", 1782 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1783 1784 atw_bbp_io_enable(sc, 1); 1785 1786 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1787 SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1788 goto out; 1789 1790 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1791 goto out; 1792 1793 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1794 goto out; 1795 1796 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1797 1798 if (rc != 0) 1799 goto out; 1800 1801 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1802 1803 if (rc != 0) 1804 goto out; 1805 1806 #ifdef ATW_BBPDEBUG 1807 atw_rf3000_print(sc); 1808 #endif /* ATW_BBPDEBUG */ 1809 1810 out: 1811 atw_bbp_io_enable(sc, 0); 1812 1813 /* set beacon, rts, atim transmit power */ 1814 reg = ATW_READ(sc, ATW_PLCPHD); 1815 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1816 reg |= SHIFTIN(SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1817 ATW_PLCPHD_SERVICE_MASK); 1818 ATW_WRITE(sc, ATW_PLCPHD, reg); 1819 DELAY(atw_plcphd_delay); 1820 1821 return rc; 1822 } 1823 1824 /* Write a register on the RF3000 baseband processor using the 1825 * registers provided by the ADM8211 for this purpose. 1826 * 1827 * Return 0 on success. 1828 */ 1829 static int 1830 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1831 { 1832 u_int32_t reg; 1833 int i; 1834 1835 reg = sc->sc_bbpctl_wr | 1836 SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1837 SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1838 1839 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1840 ATW_WRITE(sc, ATW_BBPCTL, reg); 1841 DELAY(2 * atw_pseudo_milli); 1842 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1843 break; 1844 } 1845 1846 if (i < 0) { 1847 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1848 return ETIMEDOUT; 1849 } 1850 return 0; 1851 } 1852 1853 /* Read a register on the RF3000 baseband processor using the registers 1854 * the ADM8211 provides for this purpose. 1855 * 1856 * The 7-bit register address is addr. Record the 8-bit data in the register 1857 * in *val. 1858 * 1859 * Return 0 on success. 1860 * 1861 * XXX This does not seem to work. The ADM8211 must require more or 1862 * different magic to read the chip than to write it. Possibly some 1863 * of the magic I have derived from a binary-only driver concerns 1864 * the "chip address" (see the RF3000 manual). 1865 */ 1866 #ifdef ATW_BBPDEBUG 1867 static int 1868 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1869 { 1870 u_int32_t reg; 1871 int i; 1872 1873 for (i = 1000; --i >= 0; ) { 1874 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1875 break; 1876 DELAY(100); 1877 } 1878 1879 if (i < 0) { 1880 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1881 sc->sc_dev.dv_xname); 1882 return ETIMEDOUT; 1883 } 1884 1885 reg = sc->sc_bbpctl_rd | SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1886 1887 ATW_WRITE(sc, ATW_BBPCTL, reg); 1888 1889 for (i = 1000; --i >= 0; ) { 1890 DELAY(100); 1891 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1892 break; 1893 } 1894 1895 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1896 1897 if (i < 0) { 1898 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1899 sc->sc_dev.dv_xname, reg); 1900 return ETIMEDOUT; 1901 } 1902 if (val != NULL) 1903 *val = SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1904 return 0; 1905 } 1906 #endif /* ATW_BBPDEBUG */ 1907 1908 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1909 * provided by the ADM8211 for that purpose. 1910 * 1911 * val is 18 bits of data, and val is the 4-bit address of the register. 1912 * 1913 * Return 0 on success. 1914 */ 1915 static void 1916 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1917 { 1918 uint32_t bits, mask, reg; 1919 const int nbits = 22; 1920 1921 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1922 KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1923 1924 bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1925 SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1926 1927 reg = ATW_SYNRF_SELSYN; 1928 /* reference driver: reset Si4126 serial bus to initial 1929 * conditions? 1930 */ 1931 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1932 ATW_WRITE(sc, ATW_SYNRF, reg); 1933 1934 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1935 if ((bits & mask) != 0) 1936 reg |= ATW_SYNRF_SYNDATA; 1937 else 1938 reg &= ~ATW_SYNRF_SYNDATA; 1939 ATW_WRITE(sc, ATW_SYNRF, reg); 1940 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1941 ATW_WRITE(sc, ATW_SYNRF, reg); 1942 } 1943 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1944 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1945 } 1946 1947 /* Read 18-bit data from the 4-bit address addr in Si4126 1948 * RF synthesizer and write the data to *val. Return 0 on success. 1949 * 1950 * XXX This does not seem to work. The ADM8211 must require more or 1951 * different magic to read the chip than to write it. 1952 */ 1953 #ifdef ATW_SYNDEBUG 1954 static int 1955 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1956 { 1957 u_int32_t reg; 1958 int i; 1959 1960 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1961 1962 for (i = 1000; --i >= 0; ) { 1963 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1964 break; 1965 DELAY(100); 1966 } 1967 1968 if (i < 0) { 1969 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1970 sc->sc_dev.dv_xname); 1971 return ETIMEDOUT; 1972 } 1973 1974 reg = sc->sc_synctl_rd | SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1975 1976 ATW_WRITE(sc, ATW_SYNCTL, reg); 1977 1978 for (i = 1000; --i >= 0; ) { 1979 DELAY(100); 1980 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1981 break; 1982 } 1983 1984 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1985 1986 if (i < 0) { 1987 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1988 sc->sc_dev.dv_xname, reg); 1989 return ETIMEDOUT; 1990 } 1991 if (val != NULL) 1992 *val = SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1993 ATW_SYNCTL_DATA_MASK); 1994 return 0; 1995 } 1996 #endif /* ATW_SYNDEBUG */ 1997 1998 /* XXX is the endianness correct? test. */ 1999 #define atw_calchash(addr) \ 2000 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 2001 2002 /* 2003 * atw_filter_setup: 2004 * 2005 * Set the ADM8211's receive filter. 2006 */ 2007 static void 2008 atw_filter_setup(struct atw_softc *sc) 2009 { 2010 struct ieee80211com *ic = &sc->sc_ic; 2011 struct ethercom *ec = &sc->sc_ec; 2012 struct ifnet *ifp = &sc->sc_if; 2013 int hash; 2014 u_int32_t hashes[2]; 2015 struct ether_multi *enm; 2016 struct ether_multistep step; 2017 2018 /* According to comments in tlp_al981_filter_setup 2019 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2020 * multicast filter to be set while it is running. Hopefully 2021 * the ADM8211 is not the same! 2022 */ 2023 if ((ifp->if_flags & IFF_RUNNING) != 0) 2024 atw_idle(sc, ATW_NAR_SR); 2025 2026 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2027 ifp->if_flags &= ~IFF_ALLMULTI; 2028 2029 /* XXX in scan mode, do not filter packets. Maybe this is 2030 * unnecessary. 2031 */ 2032 if (ic->ic_state == IEEE80211_S_SCAN || 2033 (ifp->if_flags & IFF_PROMISC) != 0) { 2034 sc->sc_opmode |= ATW_NAR_PR; 2035 goto allmulti; 2036 } 2037 2038 hashes[0] = hashes[1] = 0x0; 2039 2040 /* 2041 * Program the 64-bit multicast hash filter. 2042 */ 2043 ETHER_FIRST_MULTI(step, ec, enm); 2044 while (enm != NULL) { 2045 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2046 ETHER_ADDR_LEN) != 0) 2047 goto allmulti; 2048 2049 hash = atw_calchash(enm->enm_addrlo); 2050 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2051 ETHER_NEXT_MULTI(step, enm); 2052 sc->sc_opmode |= ATW_NAR_MM; 2053 } 2054 ifp->if_flags &= ~IFF_ALLMULTI; 2055 goto setit; 2056 2057 allmulti: 2058 sc->sc_opmode |= ATW_NAR_MM; 2059 ifp->if_flags |= IFF_ALLMULTI; 2060 hashes[0] = hashes[1] = 0xffffffff; 2061 2062 setit: 2063 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2064 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2065 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2066 DELAY(atw_nar_delay); 2067 ATW_WRITE(sc, ATW_RDR, 0x1); 2068 2069 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2070 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2071 } 2072 2073 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2074 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2075 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2076 * no beacon with the preferred BSSID and SSID in the number of 2077 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2078 */ 2079 static void 2080 atw_write_bssid(struct atw_softc *sc) 2081 { 2082 struct ieee80211com *ic = &sc->sc_ic; 2083 u_int8_t *bssid; 2084 2085 bssid = ic->ic_bss->ni_bssid; 2086 2087 ATW_WRITE(sc, ATW_BSSID0, 2088 SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2089 SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2090 SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2091 SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2092 2093 ATW_WRITE(sc, ATW_ABDA1, 2094 (ATW_READ(sc, ATW_ABDA1) & 2095 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2096 SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2097 SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2098 2099 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2100 ether_sprintf(sc->sc_bssid))); 2101 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2102 2103 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2104 } 2105 2106 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2107 * 16-bit word. 2108 */ 2109 static void 2110 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2111 { 2112 u_int i; 2113 u_int8_t *ptr; 2114 2115 memcpy(&sc->sc_sram[ofs], buf, buflen); 2116 2117 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2118 2119 KASSERT(buflen + ofs <= sc->sc_sramlen); 2120 2121 ptr = &sc->sc_sram[ofs]; 2122 2123 for (i = 0; i < buflen; i += 2) { 2124 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2125 SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2126 DELAY(atw_writewep_delay); 2127 2128 ATW_WRITE(sc, ATW_WESK, 2129 SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2130 DELAY(atw_writewep_delay); 2131 } 2132 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2133 2134 if (sc->sc_if.if_flags & IFF_DEBUG) { 2135 int n_octets = 0; 2136 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2137 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2138 for (i = 0; i < buflen; i++) { 2139 printf(" %02x", ptr[i]); 2140 if (++n_octets % 24 == 0) 2141 printf("\n"); 2142 } 2143 if (n_octets % 24 != 0) 2144 printf("\n"); 2145 } 2146 } 2147 2148 static int 2149 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2150 { 2151 struct atw_softc *sc = ic->ic_ifp->if_softc; 2152 u_int keyix = k->wk_keyix; 2153 2154 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2155 2156 if (keyix >= IEEE80211_WEP_NKID) 2157 return 0; 2158 if (k->wk_keylen != 0) 2159 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2160 2161 return 1; 2162 } 2163 2164 static int 2165 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2166 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2167 { 2168 struct atw_softc *sc = ic->ic_ifp->if_softc; 2169 2170 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2171 2172 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2173 return 0; 2174 2175 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2176 2177 return 1; 2178 } 2179 2180 static void 2181 atw_key_update_begin(struct ieee80211com *ic) 2182 { 2183 #ifdef ATW_DEBUG 2184 struct ifnet *ifp = ic->ic_ifp; 2185 struct atw_softc *sc = ifp->if_softc; 2186 #endif 2187 2188 DPRINTF(sc, ("%s:\n", __func__)); 2189 } 2190 2191 static void 2192 atw_key_update_end(struct ieee80211com *ic) 2193 { 2194 struct ifnet *ifp = ic->ic_ifp; 2195 struct atw_softc *sc = ifp->if_softc; 2196 2197 DPRINTF(sc, ("%s:\n", __func__)); 2198 2199 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2200 return; 2201 if (ATW_IS_ENABLED(sc) == 0) 2202 return; 2203 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2204 atw_write_wep(sc); 2205 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2206 DELAY(atw_nar_delay); 2207 ATW_WRITE(sc, ATW_RDR, 0x1); 2208 } 2209 2210 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2211 static void 2212 atw_write_wep(struct atw_softc *sc) 2213 { 2214 #if 0 2215 struct ieee80211com *ic = &sc->sc_ic; 2216 u_int32_t reg; 2217 int i; 2218 #endif 2219 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2220 u_int8_t buf[IEEE80211_WEP_NKID] 2221 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2222 2223 sc->sc_wepctl = 0; 2224 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2225 2226 memset(&buf[0][0], 0, sizeof(buf)); 2227 2228 #if 0 2229 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2230 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2231 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2232 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2233 buf[i][1] = ATW_WEP_ENABLED; 2234 } else { 2235 buf[i][1] = 0; 2236 continue; 2237 } 2238 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2239 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2240 ic->ic_nw_keys[i].wk_keylen - 1); 2241 } 2242 2243 reg = ATW_READ(sc, ATW_MACTEST); 2244 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2245 reg &= ~ATW_MACTEST_KEYID_MASK; 2246 reg |= SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2247 ATW_WRITE(sc, ATW_MACTEST, reg); 2248 2249 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2250 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2251 2252 switch (sc->sc_rev) { 2253 case ATW_REVISION_AB: 2254 case ATW_REVISION_AF: 2255 /* Bypass WEP on Rx. */ 2256 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2257 break; 2258 default: 2259 break; 2260 } 2261 #endif 2262 2263 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2264 sizeof(buf)); 2265 2266 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2267 } 2268 2269 static void 2270 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2271 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2272 { 2273 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2274 2275 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2276 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2277 return; 2278 2279 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2280 2281 switch (subtype) { 2282 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2283 case IEEE80211_FC0_SUBTYPE_BEACON: 2284 if (ic->ic_opmode == IEEE80211_M_IBSS && 2285 ic->ic_state == IEEE80211_S_RUN) { 2286 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2287 (void)ieee80211_ibss_merge(ni); 2288 } 2289 break; 2290 default: 2291 break; 2292 } 2293 return; 2294 } 2295 2296 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2297 * In ad hoc mode, the SSID is written to the beacons sent by the 2298 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2299 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2300 * indications. 2301 */ 2302 static void 2303 atw_write_ssid(struct atw_softc *sc) 2304 { 2305 struct ieee80211com *ic = &sc->sc_ic; 2306 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2307 * it only expects the element length, not its ID. 2308 */ 2309 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2310 2311 memset(buf, 0, sizeof(buf)); 2312 buf[0] = ic->ic_bss->ni_esslen; 2313 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2314 2315 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2316 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2317 } 2318 2319 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2320 * In ad hoc mode, the supported rates are written to beacons sent by the 2321 * ADM8211. 2322 */ 2323 static void 2324 atw_write_sup_rates(struct atw_softc *sc) 2325 { 2326 struct ieee80211com *ic = &sc->sc_ic; 2327 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2328 * supported rates 2329 */ 2330 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2331 2332 memset(buf, 0, sizeof(buf)); 2333 2334 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2335 2336 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2337 ic->ic_bss->ni_rates.rs_nrates); 2338 2339 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2340 } 2341 2342 /* Start/stop sending beacons. */ 2343 void 2344 atw_start_beacon(struct atw_softc *sc, int start) 2345 { 2346 struct ieee80211com *ic = &sc->sc_ic; 2347 uint16_t chan; 2348 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2349 size_t len; 2350 2351 if (ATW_IS_ENABLED(sc) == 0) 2352 return; 2353 2354 /* start beacons */ 2355 len = sizeof(struct ieee80211_frame) + 2356 8 /* timestamp */ + 2 /* beacon interval */ + 2357 2 /* capability info */ + 2358 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2359 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2360 3 /* DS parameters */ + 2361 IEEE80211_CRC_LEN; 2362 2363 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2364 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2365 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2366 2367 ATW_WRITE(sc, ATW_BCNT, bcnt); 2368 ATW_WRITE(sc, ATW_CAP1, cap1); 2369 2370 if (!start) 2371 return; 2372 2373 /* TBD use ni_capinfo */ 2374 2375 capinfo = 0; 2376 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2377 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2378 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2379 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2380 2381 switch (ic->ic_opmode) { 2382 case IEEE80211_M_IBSS: 2383 len += 4; /* IBSS parameters */ 2384 capinfo |= IEEE80211_CAPINFO_IBSS; 2385 break; 2386 case IEEE80211_M_HOSTAP: 2387 /* XXX 6-byte minimum TIM */ 2388 len += atw_beacon_len_adjust; 2389 capinfo |= IEEE80211_CAPINFO_ESS; 2390 break; 2391 default: 2392 return; 2393 } 2394 2395 /* set listen interval 2396 * XXX do software units agree w/ hardware? 2397 */ 2398 bpli = SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2399 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2400 2401 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2402 2403 bcnt |= SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2404 cap0 |= SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2405 cap1 |= SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2406 2407 ATW_WRITE(sc, ATW_BCNT, bcnt); 2408 ATW_WRITE(sc, ATW_BPLI, bpli); 2409 ATW_WRITE(sc, ATW_CAP0, cap0); 2410 ATW_WRITE(sc, ATW_CAP1, cap1); 2411 2412 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2413 sc->sc_dev.dv_xname, bcnt)); 2414 2415 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2416 sc->sc_dev.dv_xname, cap1)); 2417 } 2418 2419 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2420 static inline uint32_t 2421 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2422 { 2423 /* Following the reference driver's lead, I compute 2424 * 2425 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2426 * 2427 * without using 64-bit arithmetic, using the following 2428 * relationship: 2429 * 2430 * (0x100000000 * H + L) % m 2431 * = ((0x100000000 % m) * H + L) % m 2432 * = (((0xffffffff + 1) % m) * H + L) % m 2433 * = ((0xffffffff % m + 1 % m) * H + L) % m 2434 * = ((0xffffffff % m + 1) * H + L) % m 2435 */ 2436 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2437 } 2438 2439 static uint64_t 2440 atw_get_tsft(struct atw_softc *sc) 2441 { 2442 int i; 2443 uint32_t tsfth, tsftl; 2444 for (i = 0; i < 2; i++) { 2445 tsfth = ATW_READ(sc, ATW_TSFTH); 2446 tsftl = ATW_READ(sc, ATW_TSFTL); 2447 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2448 break; 2449 } 2450 return ((uint64_t)tsfth << 32) | tsftl; 2451 } 2452 2453 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2454 * the ieee80211com. 2455 * 2456 * Predict the next target beacon transmission time (TBTT) and 2457 * write it to the ADM8211. 2458 */ 2459 static void 2460 atw_predict_beacon(struct atw_softc *sc) 2461 { 2462 #define TBTTOFS 20 /* TU */ 2463 2464 struct ieee80211com *ic = &sc->sc_ic; 2465 uint64_t tsft; 2466 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2467 union { 2468 uint64_t word; 2469 uint8_t tstamp[8]; 2470 } u; 2471 2472 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2473 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2474 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2475 tsft = atw_get_tsft(sc); 2476 u.word = htole64(tsft); 2477 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2478 sizeof(ic->ic_bss->ni_tstamp)); 2479 } else 2480 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2481 2482 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2483 2484 tsftl = tsft & 0xFFFFFFFF; 2485 tsfth = tsft >> 32; 2486 2487 /* We sent/received the last beacon `past' microseconds 2488 * after the interval divided the TSF timer. 2489 */ 2490 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2491 2492 /* Skip ten beacons so that the TBTT cannot pass before 2493 * we've programmed it. Ten is an arbitrary number. 2494 */ 2495 tbtt = past_even + ival * 10; 2496 2497 ATW_WRITE(sc, ATW_TOFS1, 2498 SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2499 SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2500 SHIFTIN(SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2501 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2502 #undef TBTTOFS 2503 } 2504 2505 static void 2506 atw_next_scan(void *arg) 2507 { 2508 struct atw_softc *sc = arg; 2509 struct ieee80211com *ic = &sc->sc_ic; 2510 int s; 2511 2512 /* don't call atw_start w/o network interrupts blocked */ 2513 s = splnet(); 2514 if (ic->ic_state == IEEE80211_S_SCAN) 2515 ieee80211_next_scan(ic); 2516 splx(s); 2517 } 2518 2519 /* Synchronize the hardware state with the software state. */ 2520 static int 2521 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2522 { 2523 struct ifnet *ifp = ic->ic_ifp; 2524 struct atw_softc *sc = ifp->if_softc; 2525 enum ieee80211_state ostate; 2526 int error = 0; 2527 2528 ostate = ic->ic_state; 2529 callout_stop(&sc->sc_scan_ch); 2530 2531 switch (nstate) { 2532 case IEEE80211_S_AUTH: 2533 case IEEE80211_S_ASSOC: 2534 atw_write_bssid(sc); 2535 error = atw_tune(sc); 2536 break; 2537 case IEEE80211_S_INIT: 2538 callout_stop(&sc->sc_scan_ch); 2539 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2540 atw_start_beacon(sc, 0); 2541 break; 2542 case IEEE80211_S_SCAN: 2543 error = atw_tune(sc); 2544 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2545 atw_next_scan, sc); 2546 break; 2547 case IEEE80211_S_RUN: 2548 error = atw_tune(sc); 2549 atw_write_bssid(sc); 2550 atw_write_ssid(sc); 2551 atw_write_sup_rates(sc); 2552 2553 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2554 ic->ic_opmode == IEEE80211_M_MONITOR) 2555 break; 2556 2557 /* set listen interval 2558 * XXX do software units agree w/ hardware? 2559 */ 2560 ATW_WRITE(sc, ATW_BPLI, 2561 SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2562 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2563 ATW_BPLI_LI_MASK)); 2564 2565 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2566 ATW_READ(sc, ATW_BPLI))); 2567 2568 atw_predict_beacon(sc); 2569 2570 switch (ic->ic_opmode) { 2571 case IEEE80211_M_AHDEMO: 2572 case IEEE80211_M_HOSTAP: 2573 case IEEE80211_M_IBSS: 2574 atw_start_beacon(sc, 1); 2575 break; 2576 case IEEE80211_M_MONITOR: 2577 case IEEE80211_M_STA: 2578 break; 2579 } 2580 2581 break; 2582 } 2583 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2584 } 2585 2586 /* 2587 * atw_add_rxbuf: 2588 * 2589 * Add a receive buffer to the indicated descriptor. 2590 */ 2591 int 2592 atw_add_rxbuf(struct atw_softc *sc, int idx) 2593 { 2594 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2595 struct mbuf *m; 2596 int error; 2597 2598 MGETHDR(m, M_DONTWAIT, MT_DATA); 2599 if (m == NULL) 2600 return (ENOBUFS); 2601 2602 MCLGET(m, M_DONTWAIT); 2603 if ((m->m_flags & M_EXT) == 0) { 2604 m_freem(m); 2605 return (ENOBUFS); 2606 } 2607 2608 if (rxs->rxs_mbuf != NULL) 2609 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2610 2611 rxs->rxs_mbuf = m; 2612 2613 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2614 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2615 BUS_DMA_READ|BUS_DMA_NOWAIT); 2616 if (error) { 2617 printf("%s: can't load rx DMA map %d, error = %d\n", 2618 sc->sc_dev.dv_xname, idx, error); 2619 panic("atw_add_rxbuf"); /* XXX */ 2620 } 2621 2622 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2623 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2624 2625 ATW_INIT_RXDESC(sc, idx); 2626 2627 return (0); 2628 } 2629 2630 /* 2631 * Release any queued transmit buffers. 2632 */ 2633 void 2634 atw_txdrain(struct atw_softc *sc) 2635 { 2636 struct atw_txsoft *txs; 2637 2638 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2639 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2640 if (txs->txs_mbuf != NULL) { 2641 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2642 m_freem(txs->txs_mbuf); 2643 txs->txs_mbuf = NULL; 2644 } 2645 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2646 sc->sc_txfree += txs->txs_ndescs; 2647 } 2648 2649 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2650 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2651 sc->sc_txfree != ATW_NTXDESC)); 2652 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2653 sc->sc_tx_timer = 0; 2654 } 2655 2656 /* 2657 * atw_stop: [ ifnet interface function ] 2658 * 2659 * Stop transmission on the interface. 2660 */ 2661 void 2662 atw_stop(struct ifnet *ifp, int disable) 2663 { 2664 struct atw_softc *sc = ifp->if_softc; 2665 struct ieee80211com *ic = &sc->sc_ic; 2666 2667 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2668 2669 /* Disable interrupts. */ 2670 ATW_WRITE(sc, ATW_IER, 0); 2671 2672 /* Stop the transmit and receive processes. */ 2673 sc->sc_opmode = 0; 2674 ATW_WRITE(sc, ATW_NAR, 0); 2675 DELAY(atw_nar_delay); 2676 ATW_WRITE(sc, ATW_TDBD, 0); 2677 ATW_WRITE(sc, ATW_TDBP, 0); 2678 ATW_WRITE(sc, ATW_RDB, 0); 2679 2680 atw_txdrain(sc); 2681 2682 if (disable) { 2683 atw_rxdrain(sc); 2684 atw_disable(sc); 2685 } 2686 2687 /* 2688 * Mark the interface down and cancel the watchdog timer. 2689 */ 2690 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2691 sc->sc_tx_timer = 0; 2692 ifp->if_timer = 0; 2693 2694 if (!disable) 2695 atw_reset(sc); 2696 } 2697 2698 /* 2699 * atw_rxdrain: 2700 * 2701 * Drain the receive queue. 2702 */ 2703 void 2704 atw_rxdrain(struct atw_softc *sc) 2705 { 2706 struct atw_rxsoft *rxs; 2707 int i; 2708 2709 for (i = 0; i < ATW_NRXDESC; i++) { 2710 rxs = &sc->sc_rxsoft[i]; 2711 if (rxs->rxs_mbuf == NULL) 2712 continue; 2713 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2714 m_freem(rxs->rxs_mbuf); 2715 rxs->rxs_mbuf = NULL; 2716 } 2717 } 2718 2719 /* 2720 * atw_detach: 2721 * 2722 * Detach an ADM8211 interface. 2723 */ 2724 int 2725 atw_detach(struct atw_softc *sc) 2726 { 2727 struct ifnet *ifp = &sc->sc_if; 2728 struct atw_rxsoft *rxs; 2729 struct atw_txsoft *txs; 2730 int i; 2731 2732 /* 2733 * Succeed now if there isn't any work to do. 2734 */ 2735 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2736 return (0); 2737 2738 callout_stop(&sc->sc_scan_ch); 2739 2740 ieee80211_ifdetach(&sc->sc_ic); 2741 if_detach(ifp); 2742 2743 for (i = 0; i < ATW_NRXDESC; i++) { 2744 rxs = &sc->sc_rxsoft[i]; 2745 if (rxs->rxs_mbuf != NULL) { 2746 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2747 m_freem(rxs->rxs_mbuf); 2748 rxs->rxs_mbuf = NULL; 2749 } 2750 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2751 } 2752 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2753 txs = &sc->sc_txsoft[i]; 2754 if (txs->txs_mbuf != NULL) { 2755 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2756 m_freem(txs->txs_mbuf); 2757 txs->txs_mbuf = NULL; 2758 } 2759 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2760 } 2761 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2762 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2763 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2764 sizeof(struct atw_control_data)); 2765 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2766 2767 shutdownhook_disestablish(sc->sc_sdhook); 2768 powerhook_disestablish(sc->sc_powerhook); 2769 2770 if (sc->sc_srom) 2771 free(sc->sc_srom, M_DEVBUF); 2772 2773 return (0); 2774 } 2775 2776 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2777 void 2778 atw_shutdown(void *arg) 2779 { 2780 struct atw_softc *sc = arg; 2781 2782 atw_stop(&sc->sc_if, 1); 2783 } 2784 2785 int 2786 atw_intr(void *arg) 2787 { 2788 struct atw_softc *sc = arg; 2789 struct ifnet *ifp = &sc->sc_if; 2790 u_int32_t status, rxstatus, txstatus, linkstatus; 2791 int handled = 0, txthresh; 2792 2793 #ifdef DEBUG 2794 if (ATW_IS_ENABLED(sc) == 0) 2795 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2796 #endif 2797 2798 /* 2799 * If the interface isn't running, the interrupt couldn't 2800 * possibly have come from us. 2801 */ 2802 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2803 !device_is_active(&sc->sc_dev)) 2804 return (0); 2805 2806 for (;;) { 2807 status = ATW_READ(sc, ATW_STSR); 2808 2809 if (status) 2810 ATW_WRITE(sc, ATW_STSR, status); 2811 2812 #ifdef ATW_DEBUG 2813 #define PRINTINTR(flag) do { \ 2814 if ((status & flag) != 0) { \ 2815 printf("%s" #flag, delim); \ 2816 delim = ","; \ 2817 } \ 2818 } while (0) 2819 2820 if (atw_debug > 1 && status) { 2821 const char *delim = "<"; 2822 2823 printf("%s: reg[STSR] = %x", 2824 sc->sc_dev.dv_xname, status); 2825 2826 PRINTINTR(ATW_INTR_FBE); 2827 PRINTINTR(ATW_INTR_LINKOFF); 2828 PRINTINTR(ATW_INTR_LINKON); 2829 PRINTINTR(ATW_INTR_RCI); 2830 PRINTINTR(ATW_INTR_RDU); 2831 PRINTINTR(ATW_INTR_REIS); 2832 PRINTINTR(ATW_INTR_RPS); 2833 PRINTINTR(ATW_INTR_TCI); 2834 PRINTINTR(ATW_INTR_TDU); 2835 PRINTINTR(ATW_INTR_TLT); 2836 PRINTINTR(ATW_INTR_TPS); 2837 PRINTINTR(ATW_INTR_TRT); 2838 PRINTINTR(ATW_INTR_TUF); 2839 PRINTINTR(ATW_INTR_BCNTC); 2840 PRINTINTR(ATW_INTR_ATIME); 2841 PRINTINTR(ATW_INTR_TBTT); 2842 PRINTINTR(ATW_INTR_TSCZ); 2843 PRINTINTR(ATW_INTR_TSFTF); 2844 printf(">\n"); 2845 } 2846 #undef PRINTINTR 2847 #endif /* ATW_DEBUG */ 2848 2849 if ((status & sc->sc_inten) == 0) 2850 break; 2851 2852 handled = 1; 2853 2854 rxstatus = status & sc->sc_rxint_mask; 2855 txstatus = status & sc->sc_txint_mask; 2856 linkstatus = status & sc->sc_linkint_mask; 2857 2858 if (linkstatus) { 2859 atw_linkintr(sc, linkstatus); 2860 } 2861 2862 if (rxstatus) { 2863 /* Grab any new packets. */ 2864 atw_rxintr(sc); 2865 2866 if (rxstatus & ATW_INTR_RDU) { 2867 printf("%s: receive ring overrun\n", 2868 sc->sc_dev.dv_xname); 2869 /* Get the receive process going again. */ 2870 ATW_WRITE(sc, ATW_RDR, 0x1); 2871 break; 2872 } 2873 } 2874 2875 if (txstatus) { 2876 /* Sweep up transmit descriptors. */ 2877 atw_txintr(sc); 2878 2879 if (txstatus & ATW_INTR_TLT) 2880 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2881 sc->sc_dev.dv_xname)); 2882 2883 if (txstatus & ATW_INTR_TRT) 2884 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2885 sc->sc_dev.dv_xname)); 2886 2887 /* If Tx under-run, increase our transmit threshold 2888 * if another is available. 2889 */ 2890 txthresh = sc->sc_txthresh + 1; 2891 if ((txstatus & ATW_INTR_TUF) && 2892 sc->sc_txth[txthresh].txth_name != NULL) { 2893 /* Idle the transmit process. */ 2894 atw_idle(sc, ATW_NAR_ST); 2895 2896 sc->sc_txthresh = txthresh; 2897 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2898 sc->sc_opmode |= 2899 sc->sc_txth[txthresh].txth_opmode; 2900 printf("%s: transmit underrun; new " 2901 "threshold: %s\n", sc->sc_dev.dv_xname, 2902 sc->sc_txth[txthresh].txth_name); 2903 2904 /* Set the new threshold and restart 2905 * the transmit process. 2906 */ 2907 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2908 DELAY(atw_nar_delay); 2909 ATW_WRITE(sc, ATW_RDR, 0x1); 2910 /* XXX Log every Nth underrun from 2911 * XXX now on? 2912 */ 2913 } 2914 } 2915 2916 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2917 if (status & ATW_INTR_TPS) 2918 printf("%s: transmit process stopped\n", 2919 sc->sc_dev.dv_xname); 2920 if (status & ATW_INTR_RPS) 2921 printf("%s: receive process stopped\n", 2922 sc->sc_dev.dv_xname); 2923 (void)atw_init(ifp); 2924 break; 2925 } 2926 2927 if (status & ATW_INTR_FBE) { 2928 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2929 (void)atw_init(ifp); 2930 break; 2931 } 2932 2933 /* 2934 * Not handled: 2935 * 2936 * Transmit buffer unavailable -- normal 2937 * condition, nothing to do, really. 2938 * 2939 * Early receive interrupt -- not available on 2940 * all chips, we just use RI. We also only 2941 * use single-segment receive DMA, so this 2942 * is mostly useless. 2943 * 2944 * TBD others 2945 */ 2946 } 2947 2948 /* Try to get more packets going. */ 2949 atw_start(ifp); 2950 2951 return (handled); 2952 } 2953 2954 /* 2955 * atw_idle: 2956 * 2957 * Cause the transmit and/or receive processes to go idle. 2958 * 2959 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2960 * process in STSR if I clear SR or ST after the process has already 2961 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2962 * do not seem to be too reliable. Perhaps I have the sense of the 2963 * Rx bits switched with the Tx bits? 2964 */ 2965 void 2966 atw_idle(struct atw_softc *sc, u_int32_t bits) 2967 { 2968 u_int32_t ackmask = 0, opmode, stsr, test0; 2969 int i, s; 2970 2971 s = splnet(); 2972 2973 opmode = sc->sc_opmode & ~bits; 2974 2975 if (bits & ATW_NAR_SR) 2976 ackmask |= ATW_INTR_RPS; 2977 2978 if (bits & ATW_NAR_ST) { 2979 ackmask |= ATW_INTR_TPS; 2980 /* set ATW_NAR_HF to flush TX FIFO. */ 2981 opmode |= ATW_NAR_HF; 2982 } 2983 2984 ATW_WRITE(sc, ATW_NAR, opmode); 2985 DELAY(atw_nar_delay); 2986 2987 for (i = 0; i < 1000; i++) { 2988 stsr = ATW_READ(sc, ATW_STSR); 2989 if ((stsr & ackmask) == ackmask) 2990 break; 2991 DELAY(10); 2992 } 2993 2994 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2995 2996 if ((stsr & ackmask) == ackmask) 2997 goto out; 2998 2999 test0 = ATW_READ(sc, ATW_TEST0); 3000 3001 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3002 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3003 printf("%s: transmit process not idle [%s]\n", 3004 sc->sc_dev.dv_xname, 3005 atw_tx_state[SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3006 printf("%s: bits %08x test0 %08x stsr %08x\n", 3007 sc->sc_dev.dv_xname, bits, test0, stsr); 3008 } 3009 3010 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3011 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3012 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3013 sc->sc_dev.dv_xname, 3014 atw_rx_state[SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3015 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3016 sc->sc_dev.dv_xname, bits, test0, stsr)); 3017 } 3018 out: 3019 if ((bits & ATW_NAR_ST) != 0) 3020 atw_txdrain(sc); 3021 splx(s); 3022 return; 3023 } 3024 3025 /* 3026 * atw_linkintr: 3027 * 3028 * Helper; handle link-status interrupts. 3029 */ 3030 void 3031 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3032 { 3033 struct ieee80211com *ic = &sc->sc_ic; 3034 3035 if (ic->ic_state != IEEE80211_S_RUN) 3036 return; 3037 3038 if (linkstatus & ATW_INTR_LINKON) { 3039 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3040 sc->sc_rescan_timer = 0; 3041 } else if (linkstatus & ATW_INTR_LINKOFF) { 3042 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3043 if (ic->ic_opmode != IEEE80211_M_STA) 3044 return; 3045 sc->sc_rescan_timer = 3; 3046 sc->sc_if.if_timer = 1; 3047 } 3048 } 3049 3050 static inline int 3051 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3052 { 3053 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3054 return 0; 3055 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3056 return 0; 3057 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3058 } 3059 3060 /* 3061 * atw_rxintr: 3062 * 3063 * Helper; handle receive interrupts. 3064 */ 3065 void 3066 atw_rxintr(struct atw_softc *sc) 3067 { 3068 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3069 struct ieee80211com *ic = &sc->sc_ic; 3070 struct ieee80211_node *ni; 3071 struct ieee80211_frame_min *wh; 3072 struct ifnet *ifp = &sc->sc_if; 3073 struct atw_rxsoft *rxs; 3074 struct mbuf *m; 3075 u_int32_t rxstat; 3076 int i, len, rate, rate0; 3077 u_int32_t rssi, rssi0; 3078 3079 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3080 rxs = &sc->sc_rxsoft[i]; 3081 3082 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3083 3084 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3085 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3086 rate0 = SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3087 3088 if (rxstat & ATW_RXSTAT_OWN) 3089 break; /* We have processed all receive buffers. */ 3090 3091 DPRINTF3(sc, 3092 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3093 sc->sc_dev.dv_xname, 3094 rxstat, rssi0, 3095 le32toh(sc->sc_rxdescs[i].ar_buf1), 3096 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3097 3098 /* 3099 * Make sure the packet fits in one buffer. This should 3100 * always be the case. 3101 */ 3102 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3103 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3104 printf("%s: incoming packet spilled, resetting\n", 3105 sc->sc_dev.dv_xname); 3106 (void)atw_init(ifp); 3107 return; 3108 } 3109 3110 /* 3111 * If an error occurred, update stats, clear the status 3112 * word, and leave the packet buffer in place. It will 3113 * simply be reused the next time the ring comes around. 3114 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3115 * error. 3116 */ 3117 3118 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3119 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3120 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3121 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3122 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3123 ATW_RXSTAT_ICVE)) != 0)) { 3124 #define PRINTERR(bit, str) \ 3125 if (rxstat & (bit)) \ 3126 printf("%s: receive error: %s\n", \ 3127 sc->sc_dev.dv_xname, str) 3128 ifp->if_ierrors++; 3129 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3130 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3131 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3132 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3133 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3134 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3135 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3136 #undef PRINTERR 3137 ATW_INIT_RXDESC(sc, i); 3138 continue; 3139 } 3140 3141 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3142 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3143 3144 /* 3145 * No errors; receive the packet. Note the ADM8211 3146 * includes the CRC in promiscuous mode. 3147 */ 3148 len = SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3149 3150 /* 3151 * Allocate a new mbuf cluster. If that fails, we are 3152 * out of memory, and must drop the packet and recycle 3153 * the buffer that's already attached to this descriptor. 3154 */ 3155 m = rxs->rxs_mbuf; 3156 if (atw_add_rxbuf(sc, i) != 0) { 3157 ifp->if_ierrors++; 3158 ATW_INIT_RXDESC(sc, i); 3159 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3160 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3161 continue; 3162 } 3163 3164 ifp->if_ipackets++; 3165 if (sc->sc_opmode & ATW_NAR_PR) 3166 len -= IEEE80211_CRC_LEN; 3167 m->m_pkthdr.rcvif = ifp; 3168 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3169 3170 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3171 rate = 0; 3172 else 3173 rate = rate_tbl[rate0]; 3174 3175 /* The RSSI comes straight from a register in the 3176 * baseband processor. I know that for the RF3000, 3177 * the RSSI register also contains the antenna-selection 3178 * bits. Mask those off. 3179 * 3180 * TBD Treat other basebands. 3181 */ 3182 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3183 rssi = rssi0 & RF3000_RSSI_MASK; 3184 else 3185 rssi = rssi0; 3186 3187 #if NBPFILTER > 0 3188 /* Pass this up to any BPF listeners. */ 3189 if (sc->sc_radiobpf != NULL) { 3190 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3191 3192 tap->ar_rate = rate; 3193 tap->ar_chan_freq = htole16(ic->ic_curchan->ic_freq); 3194 tap->ar_chan_flags = htole16(ic->ic_curchan->ic_flags); 3195 3196 /* TBD verify units are dB */ 3197 tap->ar_antsignal = (int)rssi; 3198 /* TBD tap->ar_flags */ 3199 3200 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3201 tap->ar_ihdr.it_len, m); 3202 } 3203 #endif /* NPBFILTER > 0 */ 3204 3205 wh = mtod(m, struct ieee80211_frame_min *); 3206 ni = ieee80211_find_rxnode(ic, wh); 3207 #if 0 3208 if (atw_hw_decrypted(sc, wh)) { 3209 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3210 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3211 } 3212 #endif 3213 ieee80211_input(ic, m, ni, (int)rssi, 0); 3214 ieee80211_free_node(ni); 3215 } 3216 3217 /* Update the receive pointer. */ 3218 sc->sc_rxptr = i; 3219 } 3220 3221 /* 3222 * atw_txintr: 3223 * 3224 * Helper; handle transmit interrupts. 3225 */ 3226 void 3227 atw_txintr(struct atw_softc *sc) 3228 { 3229 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3230 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3231 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3232 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3233 3234 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3235 struct ifnet *ifp = &sc->sc_if; 3236 struct atw_txsoft *txs; 3237 u_int32_t txstat; 3238 3239 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3240 sc->sc_dev.dv_xname, sc->sc_flags)); 3241 3242 /* 3243 * Go through our Tx list and free mbufs for those 3244 * frames that have been transmitted. 3245 */ 3246 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3247 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3248 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3249 3250 #ifdef ATW_DEBUG 3251 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3252 int i; 3253 printf(" txsoft %p transmit chain:\n", txs); 3254 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3255 txs->txs_ndescs - 1, 3256 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3257 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3258 printf(" descriptor %d:\n", i); 3259 printf(" at_status: 0x%08x\n", 3260 le32toh(sc->sc_txdescs[i].at_stat)); 3261 printf(" at_flags: 0x%08x\n", 3262 le32toh(sc->sc_txdescs[i].at_flags)); 3263 printf(" at_buf1: 0x%08x\n", 3264 le32toh(sc->sc_txdescs[i].at_buf1)); 3265 printf(" at_buf2: 0x%08x\n", 3266 le32toh(sc->sc_txdescs[i].at_buf2)); 3267 if (i == txs->txs_lastdesc) 3268 break; 3269 } 3270 } 3271 #endif 3272 3273 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3274 if (txstat & ATW_TXSTAT_OWN) 3275 break; 3276 3277 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3278 3279 sc->sc_txfree += txs->txs_ndescs; 3280 3281 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3282 0, txs->txs_dmamap->dm_mapsize, 3283 BUS_DMASYNC_POSTWRITE); 3284 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3285 m_freem(txs->txs_mbuf); 3286 txs->txs_mbuf = NULL; 3287 3288 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3289 3290 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3291 sc->sc_txfree == 0)); 3292 ifp->if_flags &= ~IFF_OACTIVE; 3293 3294 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3295 (txstat & TXSTAT_ERRMASK) != 0) { 3296 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3297 txstat_buf, sizeof(txstat_buf)); 3298 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3299 txstat_buf, 3300 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3301 } 3302 3303 /* 3304 * Check for errors and collisions. 3305 */ 3306 if (txstat & ATW_TXSTAT_TUF) 3307 sc->sc_stats.ts_tx_tuf++; 3308 if (txstat & ATW_TXSTAT_TLT) 3309 sc->sc_stats.ts_tx_tlt++; 3310 if (txstat & ATW_TXSTAT_TRT) 3311 sc->sc_stats.ts_tx_trt++; 3312 if (txstat & ATW_TXSTAT_TRO) 3313 sc->sc_stats.ts_tx_tro++; 3314 if (txstat & ATW_TXSTAT_SOFBR) { 3315 sc->sc_stats.ts_tx_sofbr++; 3316 } 3317 3318 if ((txstat & ATW_TXSTAT_ES) == 0) 3319 ifp->if_collisions += 3320 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3321 else 3322 ifp->if_oerrors++; 3323 3324 ifp->if_opackets++; 3325 } 3326 3327 /* 3328 * If there are no more pending transmissions, cancel the watchdog 3329 * timer. 3330 */ 3331 if (txs == NULL) { 3332 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3333 sc->sc_tx_timer = 0; 3334 } 3335 #undef TXSTAT_ERRMASK 3336 #undef TXSTAT_FMT 3337 } 3338 3339 /* 3340 * atw_watchdog: [ifnet interface function] 3341 * 3342 * Watchdog timer handler. 3343 */ 3344 void 3345 atw_watchdog(struct ifnet *ifp) 3346 { 3347 struct atw_softc *sc = ifp->if_softc; 3348 struct ieee80211com *ic = &sc->sc_ic; 3349 3350 ifp->if_timer = 0; 3351 if (ATW_IS_ENABLED(sc) == 0) 3352 return; 3353 3354 if (sc->sc_rescan_timer) { 3355 if (--sc->sc_rescan_timer == 0) 3356 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3357 } 3358 if (sc->sc_tx_timer) { 3359 if (--sc->sc_tx_timer == 0 && 3360 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3361 printf("%s: transmit timeout\n", ifp->if_xname); 3362 ifp->if_oerrors++; 3363 (void)atw_init(ifp); 3364 atw_start(ifp); 3365 } 3366 } 3367 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3368 ifp->if_timer = 1; 3369 ieee80211_watchdog(ic); 3370 } 3371 3372 #ifdef ATW_DEBUG 3373 static void 3374 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3375 { 3376 struct atw_softc *sc = ifp->if_softc; 3377 struct mbuf *m; 3378 int i, noctets = 0; 3379 3380 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3381 m0->m_pkthdr.len); 3382 3383 for (m = m0; m; m = m->m_next) { 3384 if (m->m_len == 0) 3385 continue; 3386 for (i = 0; i < m->m_len; i++) { 3387 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3388 if (++noctets % 24 == 0) 3389 printf("\n"); 3390 } 3391 } 3392 printf("%s%s: %d bytes emitted\n", 3393 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3394 } 3395 #endif /* ATW_DEBUG */ 3396 3397 /* 3398 * atw_start: [ifnet interface function] 3399 * 3400 * Start packet transmission on the interface. 3401 */ 3402 void 3403 atw_start(struct ifnet *ifp) 3404 { 3405 struct atw_softc *sc = ifp->if_softc; 3406 struct ieee80211_key *k; 3407 struct ieee80211com *ic = &sc->sc_ic; 3408 struct ieee80211_node *ni; 3409 struct ieee80211_frame_min *whm; 3410 struct ieee80211_frame *wh; 3411 struct atw_frame *hh; 3412 struct mbuf *m0, *m; 3413 struct atw_txsoft *txs, *last_txs; 3414 struct atw_txdesc *txd; 3415 int npkt, rate; 3416 bus_dmamap_t dmamap; 3417 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3418 3419 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3420 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3421 3422 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3423 return; 3424 3425 /* 3426 * Remember the previous number of free descriptors and 3427 * the first descriptor we'll use. 3428 */ 3429 ofree = sc->sc_txfree; 3430 firsttx = lasttx = sc->sc_txnext; 3431 3432 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3433 sc->sc_dev.dv_xname, ofree, firsttx)); 3434 3435 /* 3436 * Loop through the send queue, setting up transmit descriptors 3437 * until we drain the queue, or use up all available transmit 3438 * descriptors. 3439 */ 3440 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3441 sc->sc_txfree != 0) { 3442 3443 /* 3444 * Grab a packet off the management queue, if it 3445 * is not empty. Otherwise, from the data queue. 3446 */ 3447 IF_DEQUEUE(&ic->ic_mgtq, m0); 3448 if (m0 != NULL) { 3449 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3450 m0->m_pkthdr.rcvif = NULL; 3451 } else if (ic->ic_state != IEEE80211_S_RUN) 3452 break; /* send no data until associated */ 3453 else { 3454 IFQ_DEQUEUE(&ifp->if_snd, m0); 3455 if (m0 == NULL) 3456 break; 3457 #if NBPFILTER > 0 3458 if (ifp->if_bpf != NULL) 3459 bpf_mtap(ifp->if_bpf, m0); 3460 #endif /* NBPFILTER > 0 */ 3461 ni = ieee80211_find_txnode(ic, 3462 mtod(m0, struct ether_header *)->ether_dhost); 3463 if (ni == NULL) { 3464 ifp->if_oerrors++; 3465 break; 3466 } 3467 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3468 ieee80211_free_node(ni); 3469 ifp->if_oerrors++; 3470 break; 3471 } 3472 } 3473 3474 rate = MAX(ieee80211_get_rate(ni), 2); 3475 3476 whm = mtod(m0, struct ieee80211_frame_min *); 3477 3478 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3479 k = NULL; 3480 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3481 m_freem(m0); 3482 ieee80211_free_node(ni); 3483 ifp->if_oerrors++; 3484 break; 3485 } 3486 3487 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3488 ic->ic_flags, ic->ic_fragthreshold, rate, 3489 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3490 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3491 m_freem(m0); 3492 break; 3493 } 3494 3495 /* XXX Misleading if fragmentation is enabled. Better 3496 * to fragment in software? 3497 */ 3498 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3499 3500 #if NBPFILTER > 0 3501 /* 3502 * Pass the packet to any BPF listeners. 3503 */ 3504 if (ic->ic_rawbpf != NULL) 3505 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3506 3507 if (sc->sc_radiobpf != NULL) { 3508 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3509 3510 tap->at_rate = rate; 3511 tap->at_chan_freq = htole16(ic->ic_curchan->ic_freq); 3512 tap->at_chan_flags = htole16(ic->ic_curchan->ic_flags); 3513 3514 /* TBD tap->at_flags */ 3515 3516 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3517 tap->at_ihdr.it_len, m0); 3518 } 3519 #endif /* NBPFILTER > 0 */ 3520 3521 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3522 3523 if (ni != NULL) 3524 ieee80211_free_node(ni); 3525 3526 if (m0 == NULL) { 3527 ifp->if_oerrors++; 3528 break; 3529 } 3530 3531 /* just to make sure. */ 3532 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3533 3534 if (m0 == NULL) { 3535 ifp->if_oerrors++; 3536 break; 3537 } 3538 3539 hh = mtod(m0, struct atw_frame *); 3540 wh = &hh->atw_ihdr; 3541 3542 /* Copy everything we need from the 802.11 header: 3543 * Frame Control; address 1, address 3, or addresses 3544 * 3 and 4. NIC fills in BSSID, SA. 3545 */ 3546 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3547 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3548 panic("%s: illegal WDS frame", 3549 sc->sc_dev.dv_xname); 3550 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3551 } else 3552 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3553 3554 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3555 3556 /* initialize remaining Tx parameters */ 3557 memset(&hh->u, 0, sizeof(hh->u)); 3558 3559 hh->atw_rate = rate * 5; 3560 /* XXX this could be incorrect if M_FCS. _encap should 3561 * probably strip FCS just in case it sticks around in 3562 * bridged packets. 3563 */ 3564 hh->atw_service = 0x00; /* XXX guess */ 3565 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3566 sizeof(struct atw_frame)); 3567 3568 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3569 hh->atw_rtylmt = 3; 3570 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3571 #if 0 3572 if (do_encrypt) { 3573 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3574 hh->atw_keyid = ic->ic_def_txkey; 3575 } 3576 #endif 3577 3578 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3579 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3580 if (txs->txs_d0.d_residue) 3581 hh->atw_head_plcplen |= htole16(0x8000); 3582 if (txs->txs_dn.d_residue) 3583 hh->atw_tail_plcplen |= htole16(0x8000); 3584 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3585 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3586 3587 /* never fragment multicast frames */ 3588 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3589 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3590 } else if (sc->sc_flags & ATWF_RTSCTS) { 3591 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3592 } 3593 3594 #ifdef ATW_DEBUG 3595 hh->atw_fragnum = 0; 3596 3597 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3598 printf("%s: dst = %s, rate = 0x%02x, " 3599 "service = 0x%02x, paylen = 0x%04x\n", 3600 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3601 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3602 3603 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3604 "dur1 = 0x%04x, dur2 = 0x%04x, " 3605 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3606 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3607 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3608 hh->atw_tail_dur, hh->atw_head_dur); 3609 3610 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3611 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3612 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3613 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3614 3615 printf("%s: keyid = %d\n", 3616 sc->sc_dev.dv_xname, hh->atw_keyid); 3617 3618 atw_dump_pkt(ifp, m0); 3619 } 3620 #endif /* ATW_DEBUG */ 3621 3622 dmamap = txs->txs_dmamap; 3623 3624 /* 3625 * Load the DMA map. Copy and try (once) again if the packet 3626 * didn't fit in the alloted number of segments. 3627 */ 3628 for (first = 1; 3629 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3630 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3631 first = 0) { 3632 MGETHDR(m, M_DONTWAIT, MT_DATA); 3633 if (m == NULL) { 3634 printf("%s: unable to allocate Tx mbuf\n", 3635 sc->sc_dev.dv_xname); 3636 break; 3637 } 3638 if (m0->m_pkthdr.len > MHLEN) { 3639 MCLGET(m, M_DONTWAIT); 3640 if ((m->m_flags & M_EXT) == 0) { 3641 printf("%s: unable to allocate Tx " 3642 "cluster\n", sc->sc_dev.dv_xname); 3643 m_freem(m); 3644 break; 3645 } 3646 } 3647 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3648 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3649 m_freem(m0); 3650 m0 = m; 3651 m = NULL; 3652 } 3653 if (error != 0) { 3654 printf("%s: unable to load Tx buffer, " 3655 "error = %d\n", sc->sc_dev.dv_xname, error); 3656 m_freem(m0); 3657 break; 3658 } 3659 3660 /* 3661 * Ensure we have enough descriptors free to describe 3662 * the packet. 3663 */ 3664 if (dmamap->dm_nsegs > sc->sc_txfree) { 3665 /* 3666 * Not enough free descriptors to transmit 3667 * this packet. Unload the DMA map and 3668 * drop the packet. Notify the upper layer 3669 * that there are no more slots left. 3670 * 3671 * XXX We could allocate an mbuf and copy, but 3672 * XXX it is worth it? 3673 */ 3674 bus_dmamap_unload(sc->sc_dmat, dmamap); 3675 m_freem(m0); 3676 break; 3677 } 3678 3679 /* 3680 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3681 */ 3682 3683 /* Sync the DMA map. */ 3684 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3685 BUS_DMASYNC_PREWRITE); 3686 3687 /* XXX arbitrary retry limit; 8 because I have seen it in 3688 * use already and maybe 0 means "no tries" ! 3689 */ 3690 ctl = htole32(SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3691 3692 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3693 sc->sc_dev.dv_xname, rate * 5)); 3694 ctl |= htole32(SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3695 3696 /* 3697 * Initialize the transmit descriptors. 3698 */ 3699 for (nexttx = sc->sc_txnext, seg = 0; 3700 seg < dmamap->dm_nsegs; 3701 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3702 /* 3703 * If this is the first descriptor we're 3704 * enqueueing, don't set the OWN bit just 3705 * yet. That could cause a race condition. 3706 * We'll do it below. 3707 */ 3708 txd = &sc->sc_txdescs[nexttx]; 3709 txd->at_ctl = ctl | 3710 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3711 3712 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3713 txd->at_flags = 3714 htole32(SHIFTIN(dmamap->dm_segs[seg].ds_len, 3715 ATW_TXFLAG_TBS1_MASK)) | 3716 ((nexttx == (ATW_NTXDESC - 1)) 3717 ? htole32(ATW_TXFLAG_TER) : 0); 3718 lasttx = nexttx; 3719 } 3720 3721 /* Set `first segment' and `last segment' appropriately. */ 3722 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3723 htole32(ATW_TXFLAG_FS); 3724 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3725 3726 #ifdef ATW_DEBUG 3727 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3728 printf(" txsoft %p transmit chain:\n", txs); 3729 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3730 printf(" descriptor %d:\n", seg); 3731 printf(" at_ctl: 0x%08x\n", 3732 le32toh(sc->sc_txdescs[seg].at_ctl)); 3733 printf(" at_flags: 0x%08x\n", 3734 le32toh(sc->sc_txdescs[seg].at_flags)); 3735 printf(" at_buf1: 0x%08x\n", 3736 le32toh(sc->sc_txdescs[seg].at_buf1)); 3737 printf(" at_buf2: 0x%08x\n", 3738 le32toh(sc->sc_txdescs[seg].at_buf2)); 3739 if (seg == lasttx) 3740 break; 3741 } 3742 } 3743 #endif 3744 3745 /* Sync the descriptors we're using. */ 3746 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3748 3749 /* 3750 * Store a pointer to the packet so we can free it later, 3751 * and remember what txdirty will be once the packet is 3752 * done. 3753 */ 3754 txs->txs_mbuf = m0; 3755 txs->txs_firstdesc = sc->sc_txnext; 3756 txs->txs_lastdesc = lasttx; 3757 txs->txs_ndescs = dmamap->dm_nsegs; 3758 3759 /* Advance the tx pointer. */ 3760 sc->sc_txfree -= dmamap->dm_nsegs; 3761 sc->sc_txnext = nexttx; 3762 3763 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3764 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3765 3766 last_txs = txs; 3767 } 3768 3769 if (sc->sc_txfree != ofree) { 3770 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3771 sc->sc_dev.dv_xname, lasttx, firsttx)); 3772 /* 3773 * Cause a transmit interrupt to happen on the 3774 * last packet we enqueued. 3775 */ 3776 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3777 ATW_CDTXSYNC(sc, lasttx, 1, 3778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3779 3780 /* 3781 * The entire packet chain is set up. Give the 3782 * first descriptor to the chip now. 3783 */ 3784 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3785 ATW_CDTXSYNC(sc, firsttx, 1, 3786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3787 3788 /* Wake up the transmitter. */ 3789 ATW_WRITE(sc, ATW_TDR, 0x1); 3790 3791 if (txs == NULL || sc->sc_txfree == 0) 3792 ifp->if_flags |= IFF_OACTIVE; 3793 3794 /* Set a watchdog timer in case the chip flakes out. */ 3795 sc->sc_tx_timer = 5; 3796 ifp->if_timer = 1; 3797 } 3798 } 3799 3800 /* 3801 * atw_power: 3802 * 3803 * Power management (suspend/resume) hook. 3804 */ 3805 void 3806 atw_power(int why, void *arg) 3807 { 3808 struct atw_softc *sc = arg; 3809 struct ifnet *ifp = &sc->sc_if; 3810 int s; 3811 3812 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3813 3814 s = splnet(); 3815 switch (why) { 3816 case PWR_STANDBY: 3817 /* XXX do nothing. */ 3818 break; 3819 case PWR_SUSPEND: 3820 atw_stop(ifp, 0); 3821 if (sc->sc_power != NULL) 3822 (*sc->sc_power)(sc, why); 3823 break; 3824 case PWR_RESUME: 3825 if (ifp->if_flags & IFF_UP) { 3826 if (sc->sc_power != NULL) 3827 (*sc->sc_power)(sc, why); 3828 atw_init(ifp); 3829 } 3830 break; 3831 case PWR_SOFTSUSPEND: 3832 case PWR_SOFTSTANDBY: 3833 case PWR_SOFTRESUME: 3834 break; 3835 } 3836 splx(s); 3837 } 3838 3839 /* 3840 * atw_ioctl: [ifnet interface function] 3841 * 3842 * Handle control requests from the operator. 3843 */ 3844 int 3845 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3846 { 3847 struct atw_softc *sc = ifp->if_softc; 3848 struct ifreq *ifr = (struct ifreq *)data; 3849 int s, error = 0; 3850 3851 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3852 if (!device_is_active(&sc->sc_dev)) 3853 return ENXIO; 3854 3855 s = splnet(); 3856 3857 switch (cmd) { 3858 case SIOCSIFFLAGS: 3859 if (ifp->if_flags & IFF_UP) { 3860 if (ATW_IS_ENABLED(sc)) { 3861 /* 3862 * To avoid rescanning another access point, 3863 * do not call atw_init() here. Instead, 3864 * only reflect media settings. 3865 */ 3866 atw_filter_setup(sc); 3867 } else 3868 error = atw_init(ifp); 3869 } else if (ATW_IS_ENABLED(sc)) 3870 atw_stop(ifp, 1); 3871 break; 3872 case SIOCADDMULTI: 3873 case SIOCDELMULTI: 3874 error = (cmd == SIOCADDMULTI) ? 3875 ether_addmulti(ifr, &sc->sc_ec) : 3876 ether_delmulti(ifr, &sc->sc_ec); 3877 if (error == ENETRESET) { 3878 if (ifp->if_flags & IFF_RUNNING) 3879 atw_filter_setup(sc); /* do not rescan */ 3880 error = 0; 3881 } 3882 break; 3883 default: 3884 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3885 if (error == ENETRESET || error == ERESTART) { 3886 if (is_running(ifp)) 3887 error = atw_init(ifp); 3888 else 3889 error = 0; 3890 } 3891 break; 3892 } 3893 3894 /* Try to get more packets going. */ 3895 if (ATW_IS_ENABLED(sc)) 3896 atw_start(ifp); 3897 3898 splx(s); 3899 return (error); 3900 } 3901 3902 static int 3903 atw_media_change(struct ifnet *ifp) 3904 { 3905 int error; 3906 3907 error = ieee80211_media_change(ifp); 3908 if (error == ENETRESET) { 3909 if (is_running(ifp)) 3910 error = atw_init(ifp); 3911 else 3912 error = 0; 3913 } 3914 return error; 3915 } 3916
Indexes created Tue Sep 23 07:09:52 GMT 2025