atw.c revision 1.118
1 /* $NetBSD: atw.c,v 1.118 2006/08/17 17:11:27 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.118 2006/08/17 17:11:27 christos Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 #include <lib/libkern/libkern.h> 60 61 #include <machine/endian.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #include <net80211/ieee80211_netbsd.h> 71 #include <net80211/ieee80211_var.h> 72 #include <net80211/ieee80211_radiotap.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/ic/atwreg.h> 82 #include <dev/ic/rf3000reg.h> 83 #include <dev/ic/si4136reg.h> 84 #include <dev/ic/atwvar.h> 85 #include <dev/ic/smc93cx6var.h> 86 87 /* XXX TBD open questions 88 * 89 * 90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 92 * handle this for me? 93 * 94 */ 95 /* device attachment 96 * 97 * print TOFS[012] 98 * 99 * device initialization 100 * 101 * clear ATW_FRCTL_MAXPSP to disable max power saving 102 * set ATW_TXBR_ALCUPDATE to enable ALC 103 * set TOFS[012]? (hope not) 104 * disable rx/tx 105 * set ATW_PAR_SWR (software reset) 106 * wait for ATW_PAR_SWR clear 107 * disable interrupts 108 * ack status register 109 * enable interrupts 110 * 111 * rx/tx initialization 112 * 113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * allocate and init descriptor rings 115 * write ATW_PAR_DSL (descriptor skip length) 116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * write ATW_NAR_SQ for one/both transmit descriptor rings 119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 120 * 121 * rx/tx end 122 * 123 * stop DMA 124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 125 * flush tx w/ ATW_NAR_HF 126 * 127 * scan 128 * 129 * initialize rx/tx 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 140 141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 143 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 144 145 int atw_pseudo_milli = 1; 146 int atw_magic_delay1 = 100 * 1000; 147 int atw_magic_delay2 = 100 * 1000; 148 /* more magic multi-millisecond delays (units: microseconds) */ 149 int atw_nar_delay = 20 * 1000; 150 int atw_magic_delay4 = 10 * 1000; 151 int atw_rf_delay1 = 10 * 1000; 152 int atw_rf_delay2 = 5 * 1000; 153 int atw_plcphd_delay = 2 * 1000; 154 int atw_bbp_io_enable_delay = 20 * 1000; 155 int atw_bbp_io_disable_delay = 2 * 1000; 156 int atw_writewep_delay = 1000; 157 int atw_beacon_len_adjust = 4; 158 int atw_dwelltime = 200; 159 int atw_xindiv2 = 0; 160 161 #ifdef ATW_DEBUG 162 int atw_debug = 0; 163 164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 170 171 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 172 static void atw_print_regs(struct atw_softc *, const char *); 173 174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 175 # ifdef ATW_BBPDEBUG 176 static void atw_rf3000_print(struct atw_softc *); 177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 178 # endif /* ATW_BBPDEBUG */ 179 180 # ifdef ATW_SYNDEBUG 181 static void atw_si4126_print(struct atw_softc *); 182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 183 # endif /* ATW_SYNDEBUG */ 184 185 #else 186 #define ATW_DPRINTF(x) 187 #define ATW_DPRINTF2(x) 188 #define ATW_DPRINTF3(x) 189 #define DPRINTF(sc, x) /* nothing */ 190 #define DPRINTF2(sc, x) /* nothing */ 191 #define DPRINTF3(sc, x) /* nothing */ 192 #endif 193 194 /* ifnet methods */ 195 int atw_init(struct ifnet *); 196 int atw_ioctl(struct ifnet *, u_long, caddr_t); 197 void atw_start(struct ifnet *); 198 void atw_stop(struct ifnet *, int); 199 void atw_watchdog(struct ifnet *); 200 201 /* Device attachment */ 202 void atw_attach(struct atw_softc *); 203 int atw_detach(struct atw_softc *); 204 205 /* Rx/Tx process */ 206 int atw_add_rxbuf(struct atw_softc *, int); 207 void atw_idle(struct atw_softc *, u_int32_t); 208 void atw_rxdrain(struct atw_softc *); 209 void atw_txdrain(struct atw_softc *); 210 211 /* Device (de)activation and power state */ 212 void atw_disable(struct atw_softc *); 213 int atw_enable(struct atw_softc *); 214 void atw_power(int, void *); 215 void atw_reset(struct atw_softc *); 216 void atw_shutdown(void *); 217 218 /* Interrupt handlers */ 219 void atw_linkintr(struct atw_softc *, u_int32_t); 220 void atw_rxintr(struct atw_softc *); 221 void atw_txintr(struct atw_softc *); 222 223 /* 802.11 state machine */ 224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 225 static void atw_next_scan(void *); 226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static int atw_tune(struct atw_softc *); 229 230 /* Device initialization */ 231 static void atw_bbp_io_init(struct atw_softc *); 232 static void atw_cfp_init(struct atw_softc *); 233 static void atw_cmdr_init(struct atw_softc *); 234 static void atw_ifs_init(struct atw_softc *); 235 static void atw_nar_init(struct atw_softc *); 236 static void atw_response_times_init(struct atw_softc *); 237 static void atw_rf_reset(struct atw_softc *); 238 static void atw_test1_init(struct atw_softc *); 239 static void atw_tofs0_init(struct atw_softc *); 240 static void atw_tofs2_init(struct atw_softc *); 241 static void atw_txlmt_init(struct atw_softc *); 242 static void atw_wcsr_init(struct atw_softc *); 243 244 /* Key management */ 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(struct device *self, enum devact act) 323 { 324 struct atw_softc *sc = (struct atw_softc *)self; 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 printf("%s: device enable failed\n", 353 sc->sc_dev.dv_xname); 354 return (EIO); 355 } 356 sc->sc_flags |= ATWF_ENABLED; 357 /* Power may have been removed, and WEP keys thus 358 * reset. 359 */ 360 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 361 } 362 return (0); 363 } 364 365 /* 366 * atw_disable: 367 * 368 * Disable the ADM8211 chip. 369 */ 370 void 371 atw_disable(struct atw_softc *sc) 372 { 373 if (!ATW_IS_ENABLED(sc)) 374 return; 375 if (sc->sc_disable != NULL) 376 (*sc->sc_disable)(sc); 377 sc->sc_flags &= ~ATWF_ENABLED; 378 } 379 380 /* Returns -1 on failure. */ 381 static int 382 atw_read_srom(struct atw_softc *sc) 383 { 384 struct seeprom_descriptor sd; 385 uint32_t test0, fail_bits; 386 387 (void)memset(&sd, 0, sizeof(sd)); 388 389 test0 = ATW_READ(sc, ATW_TEST0); 390 391 switch (sc->sc_rev) { 392 case ATW_REVISION_BA: 393 case ATW_REVISION_CA: 394 fail_bits = ATW_TEST0_EPNE; 395 break; 396 default: 397 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 398 break; 399 } 400 if ((test0 & fail_bits) != 0) { 401 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 switch (test0 & ATW_TEST0_EPTYP_MASK) { 406 case ATW_TEST0_EPTYP_93c66: 407 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 408 sc->sc_sromsz = 512; 409 sd.sd_chip = C56_66; 410 break; 411 case ATW_TEST0_EPTYP_93c46: 412 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 413 sc->sc_sromsz = 128; 414 sd.sd_chip = C46; 415 break; 416 default: 417 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 418 SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 419 return -1; 420 } 421 422 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 423 424 if (sc->sc_srom == NULL) { 425 printf("%s: unable to allocate SROM buffer\n", 426 sc->sc_dev.dv_xname); 427 return -1; 428 } 429 430 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 431 432 /* ADM8211 has a single 32-bit register for controlling the 433 * 93cx6 SROM. Bit SRS enables the serial port. There is no 434 * "ready" bit. The ADM8211 input/output sense is the reverse 435 * of read_seeprom's. 436 */ 437 sd.sd_tag = sc->sc_st; 438 sd.sd_bsh = sc->sc_sh; 439 sd.sd_regsize = 4; 440 sd.sd_control_offset = ATW_SPR; 441 sd.sd_status_offset = ATW_SPR; 442 sd.sd_dataout_offset = ATW_SPR; 443 sd.sd_CK = ATW_SPR_SCLK; 444 sd.sd_CS = ATW_SPR_SCS; 445 sd.sd_DI = ATW_SPR_SDO; 446 sd.sd_DO = ATW_SPR_SDI; 447 sd.sd_MS = ATW_SPR_SRS; 448 sd.sd_RDY = 0; 449 450 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 451 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 452 free(sc->sc_srom, M_DEVBUF); 453 return -1; 454 } 455 #ifdef ATW_DEBUG 456 { 457 int i; 458 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 459 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 460 if (((i % 8) == 0) && (i != 0)) { 461 ATW_DPRINTF(("\n\t")); 462 } 463 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 464 } 465 ATW_DPRINTF(("\n")); 466 } 467 #endif /* ATW_DEBUG */ 468 return 0; 469 } 470 471 #ifdef ATW_DEBUG 472 static void 473 atw_print_regs(struct atw_softc *sc, const char *where) 474 { 475 #define PRINTREG(sc, reg) \ 476 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 477 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 478 479 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 480 481 PRINTREG(sc, ATW_PAR); 482 PRINTREG(sc, ATW_FRCTL); 483 PRINTREG(sc, ATW_TDR); 484 PRINTREG(sc, ATW_WTDP); 485 PRINTREG(sc, ATW_RDR); 486 PRINTREG(sc, ATW_WRDP); 487 PRINTREG(sc, ATW_RDB); 488 PRINTREG(sc, ATW_CSR3A); 489 PRINTREG(sc, ATW_TDBD); 490 PRINTREG(sc, ATW_TDBP); 491 PRINTREG(sc, ATW_STSR); 492 PRINTREG(sc, ATW_CSR5A); 493 PRINTREG(sc, ATW_NAR); 494 PRINTREG(sc, ATW_CSR6A); 495 PRINTREG(sc, ATW_IER); 496 PRINTREG(sc, ATW_CSR7A); 497 PRINTREG(sc, ATW_LPC); 498 PRINTREG(sc, ATW_TEST1); 499 PRINTREG(sc, ATW_SPR); 500 PRINTREG(sc, ATW_TEST0); 501 PRINTREG(sc, ATW_WCSR); 502 PRINTREG(sc, ATW_WPDR); 503 PRINTREG(sc, ATW_GPTMR); 504 PRINTREG(sc, ATW_GPIO); 505 PRINTREG(sc, ATW_BBPCTL); 506 PRINTREG(sc, ATW_SYNCTL); 507 PRINTREG(sc, ATW_PLCPHD); 508 PRINTREG(sc, ATW_MMIWADDR); 509 PRINTREG(sc, ATW_MMIRADDR1); 510 PRINTREG(sc, ATW_MMIRADDR2); 511 PRINTREG(sc, ATW_TXBR); 512 PRINTREG(sc, ATW_CSR15A); 513 PRINTREG(sc, ATW_ALCSTAT); 514 PRINTREG(sc, ATW_TOFS2); 515 PRINTREG(sc, ATW_CMDR); 516 PRINTREG(sc, ATW_PCIC); 517 PRINTREG(sc, ATW_PMCSR); 518 PRINTREG(sc, ATW_PAR0); 519 PRINTREG(sc, ATW_PAR1); 520 PRINTREG(sc, ATW_MAR0); 521 PRINTREG(sc, ATW_MAR1); 522 PRINTREG(sc, ATW_ATIMDA0); 523 PRINTREG(sc, ATW_ABDA1); 524 PRINTREG(sc, ATW_BSSID0); 525 PRINTREG(sc, ATW_TXLMT); 526 PRINTREG(sc, ATW_MIBCNT); 527 PRINTREG(sc, ATW_BCNT); 528 PRINTREG(sc, ATW_TSFTH); 529 PRINTREG(sc, ATW_TSC); 530 PRINTREG(sc, ATW_SYNRF); 531 PRINTREG(sc, ATW_BPLI); 532 PRINTREG(sc, ATW_CAP0); 533 PRINTREG(sc, ATW_CAP1); 534 PRINTREG(sc, ATW_RMD); 535 PRINTREG(sc, ATW_CFPP); 536 PRINTREG(sc, ATW_TOFS0); 537 PRINTREG(sc, ATW_TOFS1); 538 PRINTREG(sc, ATW_IFST); 539 PRINTREG(sc, ATW_RSPT); 540 PRINTREG(sc, ATW_TSFTL); 541 PRINTREG(sc, ATW_WEPCTL); 542 PRINTREG(sc, ATW_WESK); 543 PRINTREG(sc, ATW_WEPCNT); 544 PRINTREG(sc, ATW_MACTEST); 545 PRINTREG(sc, ATW_FER); 546 PRINTREG(sc, ATW_FEMR); 547 PRINTREG(sc, ATW_FPSR); 548 PRINTREG(sc, ATW_FFER); 549 #undef PRINTREG 550 } 551 #endif /* ATW_DEBUG */ 552 553 /* 554 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 555 */ 556 void 557 atw_attach(struct atw_softc *sc) 558 { 559 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 561 }; 562 struct ieee80211com *ic = &sc->sc_ic; 563 struct ifnet *ifp = &sc->sc_if; 564 int country_code, error, i, nrate, srom_major; 565 u_int32_t reg; 566 static const char *type_strings[] = {"Intersil (not supported)", 567 "RFMD", "Marvel (not supported)"}; 568 569 sc->sc_txth = atw_txthresh_tab_lo; 570 571 SIMPLEQ_INIT(&sc->sc_txfreeq); 572 SIMPLEQ_INIT(&sc->sc_txdirtyq); 573 574 #ifdef ATW_DEBUG 575 atw_print_regs(sc, "atw_attach"); 576 #endif /* ATW_DEBUG */ 577 578 /* 579 * Allocate the control data structures, and create and load the 580 * DMA map for it. 581 */ 582 if ((error = bus_dmamem_alloc(sc->sc_dmat, 583 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 584 1, &sc->sc_cdnseg, 0)) != 0) { 585 printf("%s: unable to allocate control data, error = %d\n", 586 sc->sc_dev.dv_xname, error); 587 goto fail_0; 588 } 589 590 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 591 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 592 BUS_DMA_COHERENT)) != 0) { 593 printf("%s: unable to map control data, error = %d\n", 594 sc->sc_dev.dv_xname, error); 595 goto fail_1; 596 } 597 598 if ((error = bus_dmamap_create(sc->sc_dmat, 599 sizeof(struct atw_control_data), 1, 600 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 601 printf("%s: unable to create control data DMA map, " 602 "error = %d\n", sc->sc_dev.dv_xname, error); 603 goto fail_2; 604 } 605 606 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 607 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 608 0)) != 0) { 609 printf("%s: unable to load control data DMA map, error = %d\n", 610 sc->sc_dev.dv_xname, error); 611 goto fail_3; 612 } 613 614 /* 615 * Create the transmit buffer DMA maps. 616 */ 617 sc->sc_ntxsegs = ATW_NTXSEGS; 618 for (i = 0; i < ATW_TXQUEUELEN; i++) { 619 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 620 sc->sc_ntxsegs, MCLBYTES, 0, 0, 621 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 622 printf("%s: unable to create tx DMA map %d, " 623 "error = %d\n", sc->sc_dev.dv_xname, i, error); 624 goto fail_4; 625 } 626 } 627 628 /* 629 * Create the receive buffer DMA maps. 630 */ 631 for (i = 0; i < ATW_NRXDESC; i++) { 632 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 633 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 634 printf("%s: unable to create rx DMA map %d, " 635 "error = %d\n", sc->sc_dev.dv_xname, i, error); 636 goto fail_5; 637 } 638 } 639 for (i = 0; i < ATW_NRXDESC; i++) { 640 sc->sc_rxsoft[i].rxs_mbuf = NULL; 641 } 642 643 switch (sc->sc_rev) { 644 case ATW_REVISION_AB: 645 case ATW_REVISION_AF: 646 sc->sc_sramlen = ATW_SRAM_A_SIZE; 647 break; 648 case ATW_REVISION_BA: 649 case ATW_REVISION_CA: 650 sc->sc_sramlen = ATW_SRAM_B_SIZE; 651 break; 652 } 653 654 /* Reset the chip to a known state. */ 655 atw_reset(sc); 656 657 if (atw_read_srom(sc) == -1) 658 return; 659 660 sc->sc_rftype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 661 ATW_SR_RFTYPE_MASK); 662 663 sc->sc_bbptype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 664 ATW_SR_BBPTYPE_MASK); 665 666 if (sc->sc_rftype >= __arraycount(type_strings)) { 667 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 668 return; 669 } 670 if (sc->sc_bbptype >= __arraycount(type_strings)) { 671 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 672 return; 673 } 674 675 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 676 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 677 678 /* XXX There exists a Linux driver which seems to use RFType = 0 for 679 * MARVEL. My bug, or theirs? 680 */ 681 682 reg = SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 683 684 switch (sc->sc_rftype) { 685 case ATW_RFTYPE_INTERSIL: 686 reg |= ATW_SYNCTL_CS1; 687 break; 688 case ATW_RFTYPE_RFMD: 689 reg |= ATW_SYNCTL_CS0; 690 break; 691 case ATW_RFTYPE_MARVEL: 692 break; 693 } 694 695 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 696 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 697 698 reg = SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 699 700 switch (sc->sc_bbptype) { 701 case ATW_BBPTYPE_INTERSIL: 702 reg |= ATW_BBPCTL_TWI; 703 break; 704 case ATW_BBPTYPE_RFMD: 705 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 706 ATW_BBPCTL_CCA_ACTLO; 707 break; 708 case ATW_BBPTYPE_MARVEL: 709 break; 710 case ATW_C_BBPTYPE_RFMD: 711 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 712 sc->sc_dev.dv_xname); 713 break; 714 } 715 716 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 717 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 718 719 /* 720 * From this point forward, the attachment cannot fail. A failure 721 * before this point releases all resources that may have been 722 * allocated. 723 */ 724 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 725 726 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 727 htole16(sc->sc_srom[ATW_SR_MAC00]), 728 htole16(sc->sc_srom[ATW_SR_MAC01]), 729 htole16(sc->sc_srom[ATW_SR_MAC10]))); 730 731 srom_major = SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 732 ATW_SR_MAJOR_MASK); 733 734 if (srom_major < 2) 735 sc->sc_rf3000_options1 = 0; 736 else if (sc->sc_rev == ATW_REVISION_BA) { 737 sc->sc_rf3000_options1 = 738 SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 739 ATW_SR_CR28_MASK); 740 } else 741 sc->sc_rf3000_options1 = 0; 742 743 sc->sc_rf3000_options2 = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 744 ATW_SR_CR29_MASK); 745 746 country_code = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 747 ATW_SR_CTRY_MASK); 748 749 #define ADD_CHANNEL(_ic, _chan) do { \ 750 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 751 _ic->ic_channels[_chan].ic_freq = \ 752 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 753 } while (0) 754 755 /* Find available channels */ 756 switch (country_code) { 757 case COUNTRY_MMK2: /* 1-14 */ 758 ADD_CHANNEL(ic, 14); 759 /*FALLTHROUGH*/ 760 case COUNTRY_ETSI: /* 1-13 */ 761 for (i = 1; i <= 13; i++) 762 ADD_CHANNEL(ic, i); 763 break; 764 case COUNTRY_FCC: /* 1-11 */ 765 case COUNTRY_IC: /* 1-11 */ 766 for (i = 1; i <= 11; i++) 767 ADD_CHANNEL(ic, i); 768 break; 769 case COUNTRY_MMK: /* 14 */ 770 ADD_CHANNEL(ic, 14); 771 break; 772 case COUNTRY_FRANCE: /* 10-13 */ 773 for (i = 10; i <= 13; i++) 774 ADD_CHANNEL(ic, i); 775 break; 776 default: /* assume channels 10-11 */ 777 case COUNTRY_SPAIN: /* 10-11 */ 778 for (i = 10; i <= 11; i++) 779 ADD_CHANNEL(ic, i); 780 break; 781 } 782 783 /* Read the MAC address. */ 784 reg = ATW_READ(sc, ATW_PAR0); 785 ic->ic_myaddr[0] = SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 786 ic->ic_myaddr[1] = SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 787 ic->ic_myaddr[2] = SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 788 ic->ic_myaddr[3] = SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 789 reg = ATW_READ(sc, ATW_PAR1); 790 ic->ic_myaddr[4] = SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 791 ic->ic_myaddr[5] = SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 792 793 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 794 printf(" could not get mac address, attach failed\n"); 795 return; 796 } 797 798 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 799 800 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 801 ifp->if_softc = sc; 802 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 803 IFF_NOTRAILERS; 804 ifp->if_ioctl = atw_ioctl; 805 ifp->if_start = atw_start; 806 ifp->if_watchdog = atw_watchdog; 807 ifp->if_init = atw_init; 808 ifp->if_stop = atw_stop; 809 IFQ_SET_READY(&ifp->if_snd); 810 811 ic->ic_ifp = ifp; 812 ic->ic_phytype = IEEE80211_T_DS; 813 ic->ic_opmode = IEEE80211_M_STA; 814 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 815 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 816 817 nrate = 0; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 822 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 823 824 /* 825 * Call MI attach routines. 826 */ 827 828 if_attach(ifp); 829 ieee80211_ifattach(ic); 830 831 sc->sc_newstate = ic->ic_newstate; 832 ic->ic_newstate = atw_newstate; 833 834 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 835 ic->ic_recv_mgmt = atw_recv_mgmt; 836 837 sc->sc_node_free = ic->ic_node_free; 838 ic->ic_node_free = atw_node_free; 839 840 sc->sc_node_alloc = ic->ic_node_alloc; 841 ic->ic_node_alloc = atw_node_alloc; 842 843 ic->ic_crypto.cs_key_delete = atw_key_delete; 844 ic->ic_crypto.cs_key_set = atw_key_set; 845 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 846 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 847 848 /* possibly we should fill in our own sc_send_prresp, since 849 * the ADM8211 is probably sending probe responses in ad hoc 850 * mode. 851 */ 852 853 /* complete initialization */ 854 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 855 callout_init(&sc->sc_scan_ch); 856 857 #if NBPFILTER > 0 858 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 859 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 860 #endif 861 862 /* 863 * Make sure the interface is shutdown during reboot. 864 */ 865 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 866 if (sc->sc_sdhook == NULL) 867 printf("%s: WARNING: unable to establish shutdown hook\n", 868 sc->sc_dev.dv_xname); 869 870 /* 871 * Add a suspend hook to make sure we come back up after a 872 * resume. 873 */ 874 sc->sc_powerhook = powerhook_establish(atw_power, sc); 875 if (sc->sc_powerhook == NULL) 876 printf("%s: WARNING: unable to establish power hook\n", 877 sc->sc_dev.dv_xname); 878 879 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 880 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 881 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 882 883 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 884 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 885 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 886 887 ieee80211_announce(ic); 888 return; 889 890 /* 891 * Free any resources we've allocated during the failed attach 892 * attempt. Do this in reverse order and fall through. 893 */ 894 fail_5: 895 for (i = 0; i < ATW_NRXDESC; i++) { 896 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 897 continue; 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 899 } 900 fail_4: 901 for (i = 0; i < ATW_TXQUEUELEN; i++) { 902 if (sc->sc_txsoft[i].txs_dmamap == NULL) 903 continue; 904 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 905 } 906 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 907 fail_3: 908 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 909 fail_2: 910 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 911 sizeof(struct atw_control_data)); 912 fail_1: 913 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 914 fail_0: 915 return; 916 } 917 918 static struct ieee80211_node * 919 atw_node_alloc(struct ieee80211_node_table *nt) 920 { 921 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 922 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 923 924 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 925 return ni; 926 } 927 928 static void 929 atw_node_free(struct ieee80211_node *ni) 930 { 931 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 932 933 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 934 ether_sprintf(ni->ni_bssid))); 935 (*sc->sc_node_free)(ni); 936 } 937 938 939 static void 940 atw_test1_reset(struct atw_softc *sc) 941 { 942 switch (sc->sc_rev) { 943 case ATW_REVISION_BA: 944 if (1 /* XXX condition on transceiver type */) { 945 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 946 } 947 break; 948 case ATW_REVISION_CA: 949 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 950 break; 951 default: 952 break; 953 } 954 } 955 956 /* 957 * atw_reset: 958 * 959 * Perform a soft reset on the ADM8211. 960 */ 961 void 962 atw_reset(struct atw_softc *sc) 963 { 964 int i; 965 uint32_t lpc; 966 967 ATW_WRITE(sc, ATW_NAR, 0x0); 968 DELAY(atw_nar_delay); 969 970 /* Reference driver has a cryptic remark indicating that this might 971 * power-on the chip. I know that it turns off power-saving.... 972 */ 973 ATW_WRITE(sc, ATW_FRCTL, 0x0); 974 975 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 976 977 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 978 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 979 break; 980 DELAY(atw_pseudo_milli); 981 } 982 983 /* ... and then pause 100ms longer for good measure. */ 984 DELAY(atw_magic_delay1); 985 986 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 987 988 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 989 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 990 991 /* 992 * Initialize the PCI Access Register. 993 */ 994 sc->sc_busmode = ATW_PAR_PBL_8DW; 995 996 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 997 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 998 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 999 1000 atw_test1_reset(sc); 1001 1002 /* Turn off maximum power saving, etc. */ 1003 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1004 1005 DELAY(atw_magic_delay2); 1006 1007 /* Recall EEPROM. */ 1008 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1009 1010 DELAY(atw_magic_delay4); 1011 1012 lpc = ATW_READ(sc, ATW_LPC); 1013 1014 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1015 1016 /* A reset seems to affect the SRAM contents, so put them into 1017 * a known state. 1018 */ 1019 atw_clear_sram(sc); 1020 1021 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1022 } 1023 1024 static void 1025 atw_clear_sram(struct atw_softc *sc) 1026 { 1027 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1028 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1029 /* XXX not for revision 0x20. */ 1030 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1031 } 1032 1033 /* TBD atw_init 1034 * 1035 * set MAC based on ic->ic_bss->myaddr 1036 * write WEP keys 1037 * set TX rate 1038 */ 1039 1040 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1041 * without receiving a beacon with the preferred BSSID & SSID. 1042 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1043 */ 1044 static void 1045 atw_wcsr_init(struct atw_softc *sc) 1046 { 1047 uint32_t wcsr; 1048 1049 wcsr = ATW_READ(sc, ATW_WCSR); 1050 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1051 wcsr |= SHIFTIN(7, ATW_WCSR_BLN_MASK); 1052 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1053 1054 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1055 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1056 } 1057 1058 /* Turn off power management. Set Rx store-and-forward mode. */ 1059 static void 1060 atw_cmdr_init(struct atw_softc *sc) 1061 { 1062 uint32_t cmdr; 1063 cmdr = ATW_READ(sc, ATW_CMDR); 1064 cmdr &= ~ATW_CMDR_APM; 1065 cmdr |= ATW_CMDR_RTE; 1066 cmdr &= ~ATW_CMDR_DRT_MASK; 1067 cmdr |= ATW_CMDR_DRT_SF; 1068 1069 ATW_WRITE(sc, ATW_CMDR, cmdr); 1070 } 1071 1072 static void 1073 atw_tofs2_init(struct atw_softc *sc) 1074 { 1075 uint32_t tofs2; 1076 /* XXX this magic can probably be figured out from the RFMD docs */ 1077 #ifndef ATW_REFSLAVE 1078 tofs2 = SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1079 SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1080 SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1081 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1082 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1083 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1084 SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1085 SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1086 #else 1087 /* XXX new magic from reference driver source */ 1088 tofs2 = SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1089 SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1090 SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1091 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1092 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1093 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1094 SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1095 SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1096 #endif 1097 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1098 } 1099 1100 static void 1101 atw_nar_init(struct atw_softc *sc) 1102 { 1103 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1104 } 1105 1106 static void 1107 atw_txlmt_init(struct atw_softc *sc) 1108 { 1109 ATW_WRITE(sc, ATW_TXLMT, SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1110 SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1111 } 1112 1113 static void 1114 atw_test1_init(struct atw_softc *sc) 1115 { 1116 uint32_t test1; 1117 1118 test1 = ATW_READ(sc, ATW_TEST1); 1119 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1120 /* XXX magic 0x1 */ 1121 test1 |= SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1122 ATW_WRITE(sc, ATW_TEST1, test1); 1123 } 1124 1125 static void 1126 atw_rf_reset(struct atw_softc *sc) 1127 { 1128 /* XXX this resets an Intersil RF front-end? */ 1129 /* TBD condition on Intersil RFType? */ 1130 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1131 DELAY(atw_rf_delay1); 1132 ATW_WRITE(sc, ATW_SYNRF, 0); 1133 DELAY(atw_rf_delay2); 1134 } 1135 1136 /* Set 16 TU max duration for the contention-free period (CFP). */ 1137 static void 1138 atw_cfp_init(struct atw_softc *sc) 1139 { 1140 uint32_t cfpp; 1141 1142 cfpp = ATW_READ(sc, ATW_CFPP); 1143 cfpp &= ~ATW_CFPP_CFPMD; 1144 cfpp |= SHIFTIN(16, ATW_CFPP_CFPMD); 1145 ATW_WRITE(sc, ATW_CFPP, cfpp); 1146 } 1147 1148 static void 1149 atw_tofs0_init(struct atw_softc *sc) 1150 { 1151 /* XXX I guess that the Cardbus clock is 22 MHz? 1152 * I am assuming that the role of ATW_TOFS0_USCNT is 1153 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1154 * very clear on this point. It says in the datasheet that it is 1155 * possible for the ADM8211 to accomodate bus speeds between 22 MHz 1156 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1157 * these values. These values are also the power-on default. 1158 */ 1159 ATW_WRITE(sc, ATW_TOFS0, 1160 SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1161 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1162 } 1163 1164 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1165 static void 1166 atw_ifs_init(struct atw_softc *sc) 1167 { 1168 uint32_t ifst; 1169 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1170 * Go figure. 1171 */ 1172 ifst = SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1173 SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1174 ATW_IFST_SIFS_MASK) | 1175 SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1176 SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1177 1178 ATW_WRITE(sc, ATW_IFST, ifst); 1179 } 1180 1181 static void 1182 atw_response_times_init(struct atw_softc *sc) 1183 { 1184 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1185 * indicate that the MAC expects at least SIFS + MIRT microseconds 1186 * to pass after it transmits a frame that requires a response; 1187 * it waits at most SIFS + MART microseconds for the response. 1188 * Surely this is not the ACK timeout? 1189 */ 1190 ATW_WRITE(sc, ATW_RSPT, SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1191 SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1192 } 1193 1194 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1195 * engines read and write baseband registers after Rx and before 1196 * Tx, respectively. 1197 */ 1198 static void 1199 atw_bbp_io_init(struct atw_softc *sc) 1200 { 1201 uint32_t mmiraddr2; 1202 1203 /* XXX The reference driver does this, but is it *really* 1204 * necessary? 1205 */ 1206 switch (sc->sc_rev) { 1207 case ATW_REVISION_AB: 1208 case ATW_REVISION_AF: 1209 mmiraddr2 = 0x0; 1210 break; 1211 default: 1212 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1213 mmiraddr2 &= 1214 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1215 break; 1216 } 1217 1218 switch (sc->sc_bbptype) { 1219 case ATW_BBPTYPE_INTERSIL: 1220 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1221 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1222 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1223 break; 1224 case ATW_BBPTYPE_MARVEL: 1225 /* TBD find out the Marvel settings. */ 1226 break; 1227 case ATW_BBPTYPE_RFMD: 1228 default: 1229 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1230 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1231 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1232 break; 1233 } 1234 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1235 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1236 } 1237 1238 /* 1239 * atw_init: [ ifnet interface function ] 1240 * 1241 * Initialize the interface. Must be called at splnet(). 1242 */ 1243 int 1244 atw_init(struct ifnet *ifp) 1245 { 1246 struct atw_softc *sc = ifp->if_softc; 1247 struct ieee80211com *ic = &sc->sc_ic; 1248 struct atw_txsoft *txs; 1249 struct atw_rxsoft *rxs; 1250 int i, error = 0; 1251 1252 if ((error = atw_enable(sc)) != 0) 1253 goto out; 1254 1255 /* 1256 * Cancel any pending I/O. This also resets. 1257 */ 1258 atw_stop(ifp, 0); 1259 1260 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1261 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1262 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1263 1264 atw_wcsr_init(sc); 1265 1266 atw_cmdr_init(sc); 1267 1268 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1269 * 1270 * XXX Set transmit power for ATIM, RTS, Beacon. 1271 */ 1272 ATW_WRITE(sc, ATW_PLCPHD, SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1273 SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1274 1275 atw_tofs2_init(sc); 1276 1277 atw_nar_init(sc); 1278 1279 atw_txlmt_init(sc); 1280 1281 atw_test1_init(sc); 1282 1283 atw_rf_reset(sc); 1284 1285 atw_cfp_init(sc); 1286 1287 atw_tofs0_init(sc); 1288 1289 atw_ifs_init(sc); 1290 1291 /* XXX Fall asleep after one second of inactivity. 1292 * XXX A frame may only dribble in for 65536us. 1293 */ 1294 ATW_WRITE(sc, ATW_RMD, 1295 SHIFTIN(1, ATW_RMD_PCNT) | SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1296 1297 atw_response_times_init(sc); 1298 1299 atw_bbp_io_init(sc); 1300 1301 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1302 1303 if ((error = atw_rf3000_init(sc)) != 0) 1304 goto out; 1305 1306 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1307 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1308 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1309 1310 /* 1311 * Initialize the transmit descriptor ring. 1312 */ 1313 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1314 for (i = 0; i < ATW_NTXDESC; i++) { 1315 sc->sc_txdescs[i].at_ctl = 0; 1316 /* no transmit chaining */ 1317 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1318 sc->sc_txdescs[i].at_buf2 = 1319 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1320 } 1321 /* use ring mode */ 1322 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1323 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1324 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1325 sc->sc_txfree = ATW_NTXDESC; 1326 sc->sc_txnext = 0; 1327 1328 /* 1329 * Initialize the transmit job descriptors. 1330 */ 1331 SIMPLEQ_INIT(&sc->sc_txfreeq); 1332 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1333 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1334 txs = &sc->sc_txsoft[i]; 1335 txs->txs_mbuf = NULL; 1336 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1337 } 1338 1339 /* 1340 * Initialize the receive descriptor and receive job 1341 * descriptor rings. 1342 */ 1343 for (i = 0; i < ATW_NRXDESC; i++) { 1344 rxs = &sc->sc_rxsoft[i]; 1345 if (rxs->rxs_mbuf == NULL) { 1346 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1347 printf("%s: unable to allocate or map rx " 1348 "buffer %d, error = %d\n", 1349 sc->sc_dev.dv_xname, i, error); 1350 /* 1351 * XXX Should attempt to run with fewer receive 1352 * XXX buffers instead of just failing. 1353 */ 1354 atw_rxdrain(sc); 1355 goto out; 1356 } 1357 } else 1358 ATW_INIT_RXDESC(sc, i); 1359 } 1360 sc->sc_rxptr = 0; 1361 1362 /* 1363 * Initialize the interrupt mask and enable interrupts. 1364 */ 1365 /* normal interrupts */ 1366 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1367 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1368 1369 /* abnormal interrupts */ 1370 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1371 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1372 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1373 1374 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1375 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1376 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1377 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1378 ATW_INTR_TRT; 1379 1380 sc->sc_linkint_mask &= sc->sc_inten; 1381 sc->sc_rxint_mask &= sc->sc_inten; 1382 sc->sc_txint_mask &= sc->sc_inten; 1383 1384 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1385 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1386 1387 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1388 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1389 1390 /* 1391 * Give the transmit and receive rings to the ADM8211. 1392 */ 1393 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1394 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1395 1396 sc->sc_txthresh = 0; 1397 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1398 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1399 1400 /* common 802.11 configuration */ 1401 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1402 switch (ic->ic_opmode) { 1403 case IEEE80211_M_STA: 1404 break; 1405 case IEEE80211_M_AHDEMO: /* XXX */ 1406 case IEEE80211_M_IBSS: 1407 ic->ic_flags |= IEEE80211_F_IBSSON; 1408 /*FALLTHROUGH*/ 1409 case IEEE80211_M_HOSTAP: /* XXX */ 1410 break; 1411 case IEEE80211_M_MONITOR: /* XXX */ 1412 break; 1413 } 1414 1415 switch (ic->ic_opmode) { 1416 case IEEE80211_M_AHDEMO: 1417 case IEEE80211_M_HOSTAP: 1418 #ifndef IEEE80211_NO_HOSTAP 1419 ic->ic_bss->ni_intval = ic->ic_lintval; 1420 ic->ic_bss->ni_rssi = 0; 1421 ic->ic_bss->ni_rstamp = 0; 1422 #endif /* !IEEE80211_NO_HOSTAP */ 1423 break; 1424 default: /* XXX */ 1425 break; 1426 } 1427 1428 sc->sc_wepctl = 0; 1429 1430 atw_write_ssid(sc); 1431 atw_write_sup_rates(sc); 1432 atw_write_wep(sc); 1433 1434 ic->ic_state = IEEE80211_S_INIT; 1435 1436 /* 1437 * Set the receive filter. This will start the transmit and 1438 * receive processes. 1439 */ 1440 atw_filter_setup(sc); 1441 1442 /* 1443 * Start the receive process. 1444 */ 1445 ATW_WRITE(sc, ATW_RDR, 0x1); 1446 1447 /* 1448 * Note that the interface is now running. 1449 */ 1450 ifp->if_flags |= IFF_RUNNING; 1451 ifp->if_flags &= ~IFF_OACTIVE; 1452 1453 /* send no beacons, yet. */ 1454 atw_start_beacon(sc, 0); 1455 1456 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1457 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1458 else 1459 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1460 out: 1461 if (error) { 1462 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1463 sc->sc_tx_timer = 0; 1464 ifp->if_timer = 0; 1465 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1466 } 1467 #ifdef ATW_DEBUG 1468 atw_print_regs(sc, "end of init"); 1469 #endif /* ATW_DEBUG */ 1470 1471 return (error); 1472 } 1473 1474 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1475 * 0: MAC control of RF3000/Si4126. 1476 * 1477 * Applies power, or selects RF front-end? Sets reset condition. 1478 * 1479 * TBD support non-RFMD BBP, non-SiLabs synth. 1480 */ 1481 static void 1482 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1483 { 1484 if (enable) { 1485 ATW_WRITE(sc, ATW_SYNRF, 1486 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1487 DELAY(atw_bbp_io_enable_delay); 1488 } else { 1489 ATW_WRITE(sc, ATW_SYNRF, 0); 1490 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1491 } 1492 } 1493 1494 static int 1495 atw_tune(struct atw_softc *sc) 1496 { 1497 int rc; 1498 u_int chan; 1499 struct ieee80211com *ic = &sc->sc_ic; 1500 1501 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1502 if (chan == IEEE80211_CHAN_ANY) 1503 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1504 1505 if (chan == sc->sc_cur_chan) 1506 return 0; 1507 1508 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1509 sc->sc_cur_chan, chan)); 1510 1511 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1512 1513 atw_si4126_tune(sc, chan); 1514 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1515 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1516 chan); 1517 1518 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1519 DELAY(atw_nar_delay); 1520 ATW_WRITE(sc, ATW_RDR, 0x1); 1521 1522 if (rc == 0) 1523 sc->sc_cur_chan = chan; 1524 1525 return rc; 1526 } 1527 1528 #ifdef ATW_SYNDEBUG 1529 static void 1530 atw_si4126_print(struct atw_softc *sc) 1531 { 1532 struct ifnet *ifp = &sc->sc_if; 1533 u_int addr, val; 1534 1535 val = 0; 1536 1537 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1538 return; 1539 1540 for (addr = 0; addr <= 8; addr++) { 1541 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1542 if (atw_si4126_read(sc, addr, &val) == 0) { 1543 printf("<unknown> (quitting print-out)\n"); 1544 break; 1545 } 1546 printf("%05x\n", val); 1547 } 1548 } 1549 #endif /* ATW_SYNDEBUG */ 1550 1551 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1552 * 1553 * The RF/IF synthesizer produces two reference frequencies for 1554 * the RF2948B transceiver. The first frequency the RF2948B requires 1555 * is two times the so-called "intermediate frequency" (IF). Since 1556 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1557 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1558 * frequency required by the transceiver is the radio frequency 1559 * (RF). This is a superheterodyne transceiver; for f(chan) the 1560 * center frequency of the channel we are tuning, RF = f(chan) - 1561 * IF. 1562 * 1563 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1564 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1565 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1566 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1567 */ 1568 static void 1569 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1570 { 1571 u_int mhz; 1572 u_int R; 1573 u_int32_t gpio; 1574 u_int16_t gain; 1575 1576 #ifdef ATW_SYNDEBUG 1577 atw_si4126_print(sc); 1578 #endif /* ATW_SYNDEBUG */ 1579 1580 if (chan == 14) 1581 mhz = 2484; 1582 else 1583 mhz = 2412 + 5 * (chan - 1); 1584 1585 /* Tune IF to 748 MHz to suit the IF LO input of the 1586 * RF2494B, which is 2 x IF. No need to set an IF divider 1587 * because an IF in 526 MHz - 952 MHz is allowed. 1588 * 1589 * XIN is 44.000 MHz, so divide it by two to get allowable 1590 * range of 2-25 MHz. SiLabs tells me that this is not 1591 * strictly necessary. 1592 */ 1593 1594 if (atw_xindiv2) 1595 R = 44; 1596 else 1597 R = 88; 1598 1599 /* Power-up RF, IF synthesizers. */ 1600 atw_si4126_write(sc, SI4126_POWER, 1601 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1602 1603 /* set LPWR, too? */ 1604 atw_si4126_write(sc, SI4126_MAIN, 1605 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1606 1607 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1608 * set KP2 to 1. 1609 * 1610 * REFDIF This is different from the reference driver, which 1611 * always sets SI4126_GAIN to 0. 1612 */ 1613 gain = SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1614 1615 atw_si4126_write(sc, SI4126_GAIN, gain); 1616 1617 /* XIN = 44 MHz. 1618 * 1619 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1620 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1621 * 1622 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1623 * so that 1496/88 * 44 MHz = 748 MHz. 1624 */ 1625 atw_si4126_write(sc, SI4126_IFN, 1496); 1626 1627 atw_si4126_write(sc, SI4126_IFR, R); 1628 1629 #ifndef ATW_REFSLAVE 1630 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1631 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1632 * which has no RF1! 1633 */ 1634 atw_si4126_write(sc, SI4126_RF1R, R); 1635 1636 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1637 #endif 1638 1639 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1640 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1641 * Now let's multiply it to mhz. So mhz - IF = N. 1642 */ 1643 atw_si4126_write(sc, SI4126_RF2R, R); 1644 1645 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1646 1647 /* wait 100us from power-up for RF, IF to settle */ 1648 DELAY(100); 1649 1650 gpio = ATW_READ(sc, ATW_GPIO); 1651 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1652 gpio |= SHIFTIN(1, ATW_GPIO_EN_MASK); 1653 1654 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1655 /* Set a Prism RF front-end to a special mode for channel 14? 1656 * 1657 * Apparently the SMC2635W needs this, although I don't think 1658 * it has a Prism RF. 1659 */ 1660 gpio |= SHIFTIN(1, ATW_GPIO_O_MASK); 1661 } 1662 ATW_WRITE(sc, ATW_GPIO, gpio); 1663 1664 #ifdef ATW_SYNDEBUG 1665 atw_si4126_print(sc); 1666 #endif /* ATW_SYNDEBUG */ 1667 } 1668 1669 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1670 * diversity. 1671 * 1672 * !!! 1673 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1674 * !!! 1675 */ 1676 static int 1677 atw_rf3000_init(struct atw_softc *sc) 1678 { 1679 int rc = 0; 1680 1681 atw_bbp_io_enable(sc, 1); 1682 1683 /* CCA is acquisition sensitive */ 1684 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1685 SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1686 1687 if (rc != 0) 1688 goto out; 1689 1690 /* enable diversity */ 1691 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1692 1693 if (rc != 0) 1694 goto out; 1695 1696 /* sensible setting from a binary-only driver */ 1697 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1698 SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1699 1700 if (rc != 0) 1701 goto out; 1702 1703 /* magic from a binary-only driver */ 1704 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1705 SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1706 1707 if (rc != 0) 1708 goto out; 1709 1710 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1711 1712 if (rc != 0) 1713 goto out; 1714 1715 /* XXX Reference driver remarks that Abocom sets this to 50. 1716 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1717 * in the "reserved" area of register RF3000_OPTIONS1. 1718 */ 1719 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1720 1721 if (rc != 0) 1722 goto out; 1723 1724 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1725 1726 if (rc != 0) 1727 goto out; 1728 1729 out: 1730 atw_bbp_io_enable(sc, 0); 1731 return rc; 1732 } 1733 1734 #ifdef ATW_BBPDEBUG 1735 static void 1736 atw_rf3000_print(struct atw_softc *sc) 1737 { 1738 struct ifnet *ifp = &sc->sc_if; 1739 u_int addr, val; 1740 1741 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1742 return; 1743 1744 for (addr = 0x01; addr <= 0x15; addr++) { 1745 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1746 if (atw_rf3000_read(sc, addr, &val) != 0) { 1747 printf("<unknown> (quitting print-out)\n"); 1748 break; 1749 } 1750 printf("%08x\n", val); 1751 } 1752 } 1753 #endif /* ATW_BBPDEBUG */ 1754 1755 /* Set the power settings on the BBP for channel `chan'. */ 1756 static int 1757 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1758 { 1759 int rc = 0; 1760 u_int32_t reg; 1761 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1762 1763 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1764 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1765 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1766 1767 /* odd channels: LSB, even channels: MSB */ 1768 if (chan % 2 == 1) { 1769 txpower &= 0xFF; 1770 lpf_cutoff &= 0xFF; 1771 lna_gs_thresh &= 0xFF; 1772 } else { 1773 txpower >>= 8; 1774 lpf_cutoff >>= 8; 1775 lna_gs_thresh >>= 8; 1776 } 1777 1778 #ifdef ATW_BBPDEBUG 1779 atw_rf3000_print(sc); 1780 #endif /* ATW_BBPDEBUG */ 1781 1782 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1783 "lna_gs_thresh %02x\n", 1784 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1785 1786 atw_bbp_io_enable(sc, 1); 1787 1788 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1789 SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1790 goto out; 1791 1792 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1793 goto out; 1794 1795 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1796 goto out; 1797 1798 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1799 1800 if (rc != 0) 1801 goto out; 1802 1803 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1804 1805 if (rc != 0) 1806 goto out; 1807 1808 #ifdef ATW_BBPDEBUG 1809 atw_rf3000_print(sc); 1810 #endif /* ATW_BBPDEBUG */ 1811 1812 out: 1813 atw_bbp_io_enable(sc, 0); 1814 1815 /* set beacon, rts, atim transmit power */ 1816 reg = ATW_READ(sc, ATW_PLCPHD); 1817 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1818 reg |= SHIFTIN(SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1819 ATW_PLCPHD_SERVICE_MASK); 1820 ATW_WRITE(sc, ATW_PLCPHD, reg); 1821 DELAY(atw_plcphd_delay); 1822 1823 return rc; 1824 } 1825 1826 /* Write a register on the RF3000 baseband processor using the 1827 * registers provided by the ADM8211 for this purpose. 1828 * 1829 * Return 0 on success. 1830 */ 1831 static int 1832 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1833 { 1834 u_int32_t reg; 1835 int i; 1836 1837 reg = sc->sc_bbpctl_wr | 1838 SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1839 SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1840 1841 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1842 ATW_WRITE(sc, ATW_BBPCTL, reg); 1843 DELAY(2 * atw_pseudo_milli); 1844 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1845 break; 1846 } 1847 1848 if (i < 0) { 1849 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1850 return ETIMEDOUT; 1851 } 1852 return 0; 1853 } 1854 1855 /* Read a register on the RF3000 baseband processor using the registers 1856 * the ADM8211 provides for this purpose. 1857 * 1858 * The 7-bit register address is addr. Record the 8-bit data in the register 1859 * in *val. 1860 * 1861 * Return 0 on success. 1862 * 1863 * XXX This does not seem to work. The ADM8211 must require more or 1864 * different magic to read the chip than to write it. Possibly some 1865 * of the magic I have derived from a binary-only driver concerns 1866 * the "chip address" (see the RF3000 manual). 1867 */ 1868 #ifdef ATW_BBPDEBUG 1869 static int 1870 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1871 { 1872 u_int32_t reg; 1873 int i; 1874 1875 for (i = 1000; --i >= 0; ) { 1876 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1877 break; 1878 DELAY(100); 1879 } 1880 1881 if (i < 0) { 1882 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1883 sc->sc_dev.dv_xname); 1884 return ETIMEDOUT; 1885 } 1886 1887 reg = sc->sc_bbpctl_rd | SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1888 1889 ATW_WRITE(sc, ATW_BBPCTL, reg); 1890 1891 for (i = 1000; --i >= 0; ) { 1892 DELAY(100); 1893 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1894 break; 1895 } 1896 1897 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1898 1899 if (i < 0) { 1900 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1901 sc->sc_dev.dv_xname, reg); 1902 return ETIMEDOUT; 1903 } 1904 if (val != NULL) 1905 *val = SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1906 return 0; 1907 } 1908 #endif /* ATW_BBPDEBUG */ 1909 1910 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1911 * provided by the ADM8211 for that purpose. 1912 * 1913 * val is 18 bits of data, and val is the 4-bit address of the register. 1914 * 1915 * Return 0 on success. 1916 */ 1917 static void 1918 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1919 { 1920 uint32_t bits, mask, reg; 1921 const int nbits = 22; 1922 1923 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1924 KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1925 1926 bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1927 SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1928 1929 reg = ATW_SYNRF_SELSYN; 1930 /* reference driver: reset Si4126 serial bus to initial 1931 * conditions? 1932 */ 1933 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1934 ATW_WRITE(sc, ATW_SYNRF, reg); 1935 1936 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1937 if ((bits & mask) != 0) 1938 reg |= ATW_SYNRF_SYNDATA; 1939 else 1940 reg &= ~ATW_SYNRF_SYNDATA; 1941 ATW_WRITE(sc, ATW_SYNRF, reg); 1942 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1943 ATW_WRITE(sc, ATW_SYNRF, reg); 1944 } 1945 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1946 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1947 } 1948 1949 /* Read 18-bit data from the 4-bit address addr in Si4126 1950 * RF synthesizer and write the data to *val. Return 0 on success. 1951 * 1952 * XXX This does not seem to work. The ADM8211 must require more or 1953 * different magic to read the chip than to write it. 1954 */ 1955 #ifdef ATW_SYNDEBUG 1956 static int 1957 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1958 { 1959 u_int32_t reg; 1960 int i; 1961 1962 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1963 1964 for (i = 1000; --i >= 0; ) { 1965 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1966 break; 1967 DELAY(100); 1968 } 1969 1970 if (i < 0) { 1971 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1972 sc->sc_dev.dv_xname); 1973 return ETIMEDOUT; 1974 } 1975 1976 reg = sc->sc_synctl_rd | SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1977 1978 ATW_WRITE(sc, ATW_SYNCTL, reg); 1979 1980 for (i = 1000; --i >= 0; ) { 1981 DELAY(100); 1982 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1983 break; 1984 } 1985 1986 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1987 1988 if (i < 0) { 1989 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1990 sc->sc_dev.dv_xname, reg); 1991 return ETIMEDOUT; 1992 } 1993 if (val != NULL) 1994 *val = SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1995 ATW_SYNCTL_DATA_MASK); 1996 return 0; 1997 } 1998 #endif /* ATW_SYNDEBUG */ 1999 2000 /* XXX is the endianness correct? test. */ 2001 #define atw_calchash(addr) \ 2002 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 2003 2004 /* 2005 * atw_filter_setup: 2006 * 2007 * Set the ADM8211's receive filter. 2008 */ 2009 static void 2010 atw_filter_setup(struct atw_softc *sc) 2011 { 2012 struct ieee80211com *ic = &sc->sc_ic; 2013 struct ethercom *ec = &sc->sc_ec; 2014 struct ifnet *ifp = &sc->sc_if; 2015 int hash; 2016 u_int32_t hashes[2]; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 2020 /* According to comments in tlp_al981_filter_setup 2021 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2022 * multicast filter to be set while it is running. Hopefully 2023 * the ADM8211 is not the same! 2024 */ 2025 if ((ifp->if_flags & IFF_RUNNING) != 0) 2026 atw_idle(sc, ATW_NAR_SR); 2027 2028 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 2031 /* XXX in scan mode, do not filter packets. Maybe this is 2032 * unnecessary. 2033 */ 2034 if (ic->ic_state == IEEE80211_S_SCAN || 2035 (ifp->if_flags & IFF_PROMISC) != 0) { 2036 sc->sc_opmode |= ATW_NAR_PR; 2037 goto allmulti; 2038 } 2039 2040 hashes[0] = hashes[1] = 0x0; 2041 2042 /* 2043 * Program the 64-bit multicast hash filter. 2044 */ 2045 ETHER_FIRST_MULTI(step, ec, enm); 2046 while (enm != NULL) { 2047 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2048 ETHER_ADDR_LEN) != 0) 2049 goto allmulti; 2050 2051 hash = atw_calchash(enm->enm_addrlo); 2052 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2053 ETHER_NEXT_MULTI(step, enm); 2054 sc->sc_opmode |= ATW_NAR_MM; 2055 } 2056 ifp->if_flags &= ~IFF_ALLMULTI; 2057 goto setit; 2058 2059 allmulti: 2060 sc->sc_opmode |= ATW_NAR_MM; 2061 ifp->if_flags |= IFF_ALLMULTI; 2062 hashes[0] = hashes[1] = 0xffffffff; 2063 2064 setit: 2065 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2066 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2067 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2068 DELAY(atw_nar_delay); 2069 ATW_WRITE(sc, ATW_RDR, 0x1); 2070 2071 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2072 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2073 } 2074 2075 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2076 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2077 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2078 * no beacon with the preferred BSSID and SSID in the number of 2079 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2080 */ 2081 static void 2082 atw_write_bssid(struct atw_softc *sc) 2083 { 2084 struct ieee80211com *ic = &sc->sc_ic; 2085 u_int8_t *bssid; 2086 2087 bssid = ic->ic_bss->ni_bssid; 2088 2089 ATW_WRITE(sc, ATW_BSSID0, 2090 SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2091 SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2092 SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2093 SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2094 2095 ATW_WRITE(sc, ATW_ABDA1, 2096 (ATW_READ(sc, ATW_ABDA1) & 2097 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2098 SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2099 SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2100 2101 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2102 ether_sprintf(sc->sc_bssid))); 2103 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2104 2105 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2106 } 2107 2108 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2109 * 16-bit word. 2110 */ 2111 static void 2112 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2113 { 2114 u_int i; 2115 u_int8_t *ptr; 2116 2117 memcpy(&sc->sc_sram[ofs], buf, buflen); 2118 2119 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2120 2121 KASSERT(buflen + ofs <= sc->sc_sramlen); 2122 2123 ptr = &sc->sc_sram[ofs]; 2124 2125 for (i = 0; i < buflen; i += 2) { 2126 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2127 SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2128 DELAY(atw_writewep_delay); 2129 2130 ATW_WRITE(sc, ATW_WESK, 2131 SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2132 DELAY(atw_writewep_delay); 2133 } 2134 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2135 2136 if (sc->sc_if.if_flags & IFF_DEBUG) { 2137 int n_octets = 0; 2138 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2139 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2140 for (i = 0; i < buflen; i++) { 2141 printf(" %02x", ptr[i]); 2142 if (++n_octets % 24 == 0) 2143 printf("\n"); 2144 } 2145 if (n_octets % 24 != 0) 2146 printf("\n"); 2147 } 2148 } 2149 2150 static int 2151 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2152 { 2153 struct atw_softc *sc = ic->ic_ifp->if_softc; 2154 u_int keyix = k->wk_keyix; 2155 2156 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2157 2158 if (keyix >= IEEE80211_WEP_NKID) 2159 return 0; 2160 if (k->wk_keylen != 0) 2161 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2162 2163 return 1; 2164 } 2165 2166 static int 2167 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2168 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2169 { 2170 struct atw_softc *sc = ic->ic_ifp->if_softc; 2171 2172 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2173 2174 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2175 return 0; 2176 2177 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2178 2179 return 1; 2180 } 2181 2182 static void 2183 atw_key_update_begin(struct ieee80211com *ic) 2184 { 2185 #ifdef ATW_DEBUG 2186 struct ifnet *ifp = ic->ic_ifp; 2187 struct atw_softc *sc = ifp->if_softc; 2188 #endif 2189 2190 DPRINTF(sc, ("%s:\n", __func__)); 2191 } 2192 2193 static void 2194 atw_key_update_end(struct ieee80211com *ic) 2195 { 2196 struct ifnet *ifp = ic->ic_ifp; 2197 struct atw_softc *sc = ifp->if_softc; 2198 2199 DPRINTF(sc, ("%s:\n", __func__)); 2200 2201 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2202 return; 2203 if (ATW_IS_ENABLED(sc) == 0) 2204 return; 2205 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2206 atw_write_wep(sc); 2207 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2208 DELAY(atw_nar_delay); 2209 ATW_WRITE(sc, ATW_RDR, 0x1); 2210 } 2211 2212 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2213 static void 2214 atw_write_wep(struct atw_softc *sc) 2215 { 2216 #if 0 2217 struct ieee80211com *ic = &sc->sc_ic; 2218 u_int32_t reg; 2219 int i; 2220 #endif 2221 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2222 u_int8_t buf[IEEE80211_WEP_NKID] 2223 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2224 2225 sc->sc_wepctl = 0; 2226 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2227 2228 memset(&buf[0][0], 0, sizeof(buf)); 2229 2230 #if 0 2231 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2232 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2233 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2234 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2235 buf[i][1] = ATW_WEP_ENABLED; 2236 } else { 2237 buf[i][1] = 0; 2238 continue; 2239 } 2240 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2241 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2242 ic->ic_nw_keys[i].wk_keylen - 1); 2243 } 2244 2245 reg = ATW_READ(sc, ATW_MACTEST); 2246 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2247 reg &= ~ATW_MACTEST_KEYID_MASK; 2248 reg |= SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2249 ATW_WRITE(sc, ATW_MACTEST, reg); 2250 2251 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2252 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2253 2254 switch (sc->sc_rev) { 2255 case ATW_REVISION_AB: 2256 case ATW_REVISION_AF: 2257 /* Bypass WEP on Rx. */ 2258 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2259 break; 2260 default: 2261 break; 2262 } 2263 #endif 2264 2265 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2266 sizeof(buf)); 2267 2268 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2269 } 2270 2271 static void 2272 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2273 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2274 { 2275 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2276 2277 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2278 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2279 return; 2280 2281 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2282 2283 switch (subtype) { 2284 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2285 case IEEE80211_FC0_SUBTYPE_BEACON: 2286 if (ic->ic_opmode == IEEE80211_M_IBSS && 2287 ic->ic_state == IEEE80211_S_RUN) { 2288 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2289 (void)ieee80211_ibss_merge(ni); 2290 } 2291 break; 2292 default: 2293 break; 2294 } 2295 return; 2296 } 2297 2298 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2299 * In ad hoc mode, the SSID is written to the beacons sent by the 2300 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2301 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2302 * indications. 2303 */ 2304 static void 2305 atw_write_ssid(struct atw_softc *sc) 2306 { 2307 struct ieee80211com *ic = &sc->sc_ic; 2308 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2309 * it only expects the element length, not its ID. 2310 */ 2311 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2312 2313 memset(buf, 0, sizeof(buf)); 2314 buf[0] = ic->ic_bss->ni_esslen; 2315 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2316 2317 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2318 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2319 } 2320 2321 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2322 * In ad hoc mode, the supported rates are written to beacons sent by the 2323 * ADM8211. 2324 */ 2325 static void 2326 atw_write_sup_rates(struct atw_softc *sc) 2327 { 2328 struct ieee80211com *ic = &sc->sc_ic; 2329 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2330 * supported rates 2331 */ 2332 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2333 2334 memset(buf, 0, sizeof(buf)); 2335 2336 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2337 2338 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2339 ic->ic_bss->ni_rates.rs_nrates); 2340 2341 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2342 } 2343 2344 /* Start/stop sending beacons. */ 2345 void 2346 atw_start_beacon(struct atw_softc *sc, int start) 2347 { 2348 struct ieee80211com *ic = &sc->sc_ic; 2349 uint16_t chan; 2350 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2351 size_t len; 2352 2353 if (ATW_IS_ENABLED(sc) == 0) 2354 return; 2355 2356 /* start beacons */ 2357 len = sizeof(struct ieee80211_frame) + 2358 8 /* timestamp */ + 2 /* beacon interval */ + 2359 2 /* capability info */ + 2360 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2361 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2362 3 /* DS parameters */ + 2363 IEEE80211_CRC_LEN; 2364 2365 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2366 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2367 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2368 2369 ATW_WRITE(sc, ATW_BCNT, bcnt); 2370 ATW_WRITE(sc, ATW_CAP1, cap1); 2371 2372 if (!start) 2373 return; 2374 2375 /* TBD use ni_capinfo */ 2376 2377 capinfo = 0; 2378 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2379 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2380 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2381 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2382 2383 switch (ic->ic_opmode) { 2384 case IEEE80211_M_IBSS: 2385 len += 4; /* IBSS parameters */ 2386 capinfo |= IEEE80211_CAPINFO_IBSS; 2387 break; 2388 case IEEE80211_M_HOSTAP: 2389 /* XXX 6-byte minimum TIM */ 2390 len += atw_beacon_len_adjust; 2391 capinfo |= IEEE80211_CAPINFO_ESS; 2392 break; 2393 default: 2394 return; 2395 } 2396 2397 /* set listen interval 2398 * XXX do software units agree w/ hardware? 2399 */ 2400 bpli = SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2401 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2402 2403 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2404 2405 bcnt |= SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2406 cap0 |= SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2407 cap1 |= SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2408 2409 ATW_WRITE(sc, ATW_BCNT, bcnt); 2410 ATW_WRITE(sc, ATW_BPLI, bpli); 2411 ATW_WRITE(sc, ATW_CAP0, cap0); 2412 ATW_WRITE(sc, ATW_CAP1, cap1); 2413 2414 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2415 sc->sc_dev.dv_xname, bcnt)); 2416 2417 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2418 sc->sc_dev.dv_xname, cap1)); 2419 } 2420 2421 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2422 static inline uint32_t 2423 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2424 { 2425 /* Following the reference driver's lead, I compute 2426 * 2427 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2428 * 2429 * without using 64-bit arithmetic, using the following 2430 * relationship: 2431 * 2432 * (0x100000000 * H + L) % m 2433 * = ((0x100000000 % m) * H + L) % m 2434 * = (((0xffffffff + 1) % m) * H + L) % m 2435 * = ((0xffffffff % m + 1 % m) * H + L) % m 2436 * = ((0xffffffff % m + 1) * H + L) % m 2437 */ 2438 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2439 } 2440 2441 static uint64_t 2442 atw_get_tsft(struct atw_softc *sc) 2443 { 2444 int i; 2445 uint32_t tsfth, tsftl; 2446 for (i = 0; i < 2; i++) { 2447 tsfth = ATW_READ(sc, ATW_TSFTH); 2448 tsftl = ATW_READ(sc, ATW_TSFTL); 2449 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2450 break; 2451 } 2452 return ((uint64_t)tsfth << 32) | tsftl; 2453 } 2454 2455 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2456 * the ieee80211com. 2457 * 2458 * Predict the next target beacon transmission time (TBTT) and 2459 * write it to the ADM8211. 2460 */ 2461 static void 2462 atw_predict_beacon(struct atw_softc *sc) 2463 { 2464 #define TBTTOFS 20 /* TU */ 2465 2466 struct ieee80211com *ic = &sc->sc_ic; 2467 uint64_t tsft; 2468 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2469 union { 2470 uint64_t word; 2471 uint8_t tstamp[8]; 2472 } u; 2473 2474 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2475 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2476 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2477 tsft = atw_get_tsft(sc); 2478 u.word = htole64(tsft); 2479 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2480 sizeof(ic->ic_bss->ni_tstamp)); 2481 } else 2482 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2483 2484 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2485 2486 tsftl = tsft & 0xFFFFFFFF; 2487 tsfth = tsft >> 32; 2488 2489 /* We sent/received the last beacon `past' microseconds 2490 * after the interval divided the TSF timer. 2491 */ 2492 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2493 2494 /* Skip ten beacons so that the TBTT cannot pass before 2495 * we've programmed it. Ten is an arbitrary number. 2496 */ 2497 tbtt = past_even + ival * 10; 2498 2499 ATW_WRITE(sc, ATW_TOFS1, 2500 SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2501 SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2502 SHIFTIN(SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2503 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2504 #undef TBTTOFS 2505 } 2506 2507 static void 2508 atw_next_scan(void *arg) 2509 { 2510 struct atw_softc *sc = arg; 2511 struct ieee80211com *ic = &sc->sc_ic; 2512 int s; 2513 2514 /* don't call atw_start w/o network interrupts blocked */ 2515 s = splnet(); 2516 if (ic->ic_state == IEEE80211_S_SCAN) 2517 ieee80211_next_scan(ic); 2518 splx(s); 2519 } 2520 2521 /* Synchronize the hardware state with the software state. */ 2522 static int 2523 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2524 { 2525 struct ifnet *ifp = ic->ic_ifp; 2526 struct atw_softc *sc = ifp->if_softc; 2527 enum ieee80211_state ostate; 2528 int error = 0; 2529 2530 ostate = ic->ic_state; 2531 callout_stop(&sc->sc_scan_ch); 2532 2533 switch (nstate) { 2534 case IEEE80211_S_AUTH: 2535 case IEEE80211_S_ASSOC: 2536 atw_write_bssid(sc); 2537 error = atw_tune(sc); 2538 break; 2539 case IEEE80211_S_INIT: 2540 callout_stop(&sc->sc_scan_ch); 2541 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2542 atw_start_beacon(sc, 0); 2543 break; 2544 case IEEE80211_S_SCAN: 2545 error = atw_tune(sc); 2546 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2547 atw_next_scan, sc); 2548 break; 2549 case IEEE80211_S_RUN: 2550 error = atw_tune(sc); 2551 atw_write_bssid(sc); 2552 atw_write_ssid(sc); 2553 atw_write_sup_rates(sc); 2554 2555 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2556 ic->ic_opmode == IEEE80211_M_MONITOR) 2557 break; 2558 2559 /* set listen interval 2560 * XXX do software units agree w/ hardware? 2561 */ 2562 ATW_WRITE(sc, ATW_BPLI, 2563 SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2564 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2565 ATW_BPLI_LI_MASK)); 2566 2567 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2568 ATW_READ(sc, ATW_BPLI))); 2569 2570 atw_predict_beacon(sc); 2571 2572 switch (ic->ic_opmode) { 2573 case IEEE80211_M_AHDEMO: 2574 case IEEE80211_M_HOSTAP: 2575 case IEEE80211_M_IBSS: 2576 atw_start_beacon(sc, 1); 2577 break; 2578 case IEEE80211_M_MONITOR: 2579 case IEEE80211_M_STA: 2580 break; 2581 } 2582 2583 break; 2584 } 2585 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2586 } 2587 2588 /* 2589 * atw_add_rxbuf: 2590 * 2591 * Add a receive buffer to the indicated descriptor. 2592 */ 2593 int 2594 atw_add_rxbuf(struct atw_softc *sc, int idx) 2595 { 2596 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2597 struct mbuf *m; 2598 int error; 2599 2600 MGETHDR(m, M_DONTWAIT, MT_DATA); 2601 if (m == NULL) 2602 return (ENOBUFS); 2603 2604 MCLGET(m, M_DONTWAIT); 2605 if ((m->m_flags & M_EXT) == 0) { 2606 m_freem(m); 2607 return (ENOBUFS); 2608 } 2609 2610 if (rxs->rxs_mbuf != NULL) 2611 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2612 2613 rxs->rxs_mbuf = m; 2614 2615 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2616 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2617 BUS_DMA_READ|BUS_DMA_NOWAIT); 2618 if (error) { 2619 printf("%s: can't load rx DMA map %d, error = %d\n", 2620 sc->sc_dev.dv_xname, idx, error); 2621 panic("atw_add_rxbuf"); /* XXX */ 2622 } 2623 2624 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2625 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2626 2627 ATW_INIT_RXDESC(sc, idx); 2628 2629 return (0); 2630 } 2631 2632 /* 2633 * Release any queued transmit buffers. 2634 */ 2635 void 2636 atw_txdrain(struct atw_softc *sc) 2637 { 2638 struct atw_txsoft *txs; 2639 2640 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2641 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2642 if (txs->txs_mbuf != NULL) { 2643 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2644 m_freem(txs->txs_mbuf); 2645 txs->txs_mbuf = NULL; 2646 } 2647 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2648 sc->sc_txfree += txs->txs_ndescs; 2649 } 2650 2651 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2652 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2653 sc->sc_txfree != ATW_NTXDESC)); 2654 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2655 sc->sc_tx_timer = 0; 2656 } 2657 2658 /* 2659 * atw_stop: [ ifnet interface function ] 2660 * 2661 * Stop transmission on the interface. 2662 */ 2663 void 2664 atw_stop(struct ifnet *ifp, int disable) 2665 { 2666 struct atw_softc *sc = ifp->if_softc; 2667 struct ieee80211com *ic = &sc->sc_ic; 2668 2669 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2670 2671 /* Disable interrupts. */ 2672 ATW_WRITE(sc, ATW_IER, 0); 2673 2674 /* Stop the transmit and receive processes. */ 2675 sc->sc_opmode = 0; 2676 ATW_WRITE(sc, ATW_NAR, 0); 2677 DELAY(atw_nar_delay); 2678 ATW_WRITE(sc, ATW_TDBD, 0); 2679 ATW_WRITE(sc, ATW_TDBP, 0); 2680 ATW_WRITE(sc, ATW_RDB, 0); 2681 2682 atw_txdrain(sc); 2683 2684 if (disable) { 2685 atw_rxdrain(sc); 2686 atw_disable(sc); 2687 } 2688 2689 /* 2690 * Mark the interface down and cancel the watchdog timer. 2691 */ 2692 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2693 sc->sc_tx_timer = 0; 2694 ifp->if_timer = 0; 2695 2696 if (!disable) 2697 atw_reset(sc); 2698 } 2699 2700 /* 2701 * atw_rxdrain: 2702 * 2703 * Drain the receive queue. 2704 */ 2705 void 2706 atw_rxdrain(struct atw_softc *sc) 2707 { 2708 struct atw_rxsoft *rxs; 2709 int i; 2710 2711 for (i = 0; i < ATW_NRXDESC; i++) { 2712 rxs = &sc->sc_rxsoft[i]; 2713 if (rxs->rxs_mbuf == NULL) 2714 continue; 2715 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2716 m_freem(rxs->rxs_mbuf); 2717 rxs->rxs_mbuf = NULL; 2718 } 2719 } 2720 2721 /* 2722 * atw_detach: 2723 * 2724 * Detach an ADM8211 interface. 2725 */ 2726 int 2727 atw_detach(struct atw_softc *sc) 2728 { 2729 struct ifnet *ifp = &sc->sc_if; 2730 struct atw_rxsoft *rxs; 2731 struct atw_txsoft *txs; 2732 int i; 2733 2734 /* 2735 * Succeed now if there isn't any work to do. 2736 */ 2737 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2738 return (0); 2739 2740 callout_stop(&sc->sc_scan_ch); 2741 2742 ieee80211_ifdetach(&sc->sc_ic); 2743 if_detach(ifp); 2744 2745 for (i = 0; i < ATW_NRXDESC; i++) { 2746 rxs = &sc->sc_rxsoft[i]; 2747 if (rxs->rxs_mbuf != NULL) { 2748 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2749 m_freem(rxs->rxs_mbuf); 2750 rxs->rxs_mbuf = NULL; 2751 } 2752 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2753 } 2754 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2755 txs = &sc->sc_txsoft[i]; 2756 if (txs->txs_mbuf != NULL) { 2757 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2758 m_freem(txs->txs_mbuf); 2759 txs->txs_mbuf = NULL; 2760 } 2761 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2762 } 2763 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2764 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2765 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2766 sizeof(struct atw_control_data)); 2767 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2768 2769 shutdownhook_disestablish(sc->sc_sdhook); 2770 powerhook_disestablish(sc->sc_powerhook); 2771 2772 if (sc->sc_srom) 2773 free(sc->sc_srom, M_DEVBUF); 2774 2775 return (0); 2776 } 2777 2778 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2779 void 2780 atw_shutdown(void *arg) 2781 { 2782 struct atw_softc *sc = arg; 2783 2784 atw_stop(&sc->sc_if, 1); 2785 } 2786 2787 int 2788 atw_intr(void *arg) 2789 { 2790 struct atw_softc *sc = arg; 2791 struct ifnet *ifp = &sc->sc_if; 2792 u_int32_t status, rxstatus, txstatus, linkstatus; 2793 int handled = 0, txthresh; 2794 2795 #ifdef DEBUG 2796 if (ATW_IS_ENABLED(sc) == 0) 2797 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2798 #endif 2799 2800 /* 2801 * If the interface isn't running, the interrupt couldn't 2802 * possibly have come from us. 2803 */ 2804 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2805 !device_is_active(&sc->sc_dev)) 2806 return (0); 2807 2808 for (;;) { 2809 status = ATW_READ(sc, ATW_STSR); 2810 2811 if (status) 2812 ATW_WRITE(sc, ATW_STSR, status); 2813 2814 #ifdef ATW_DEBUG 2815 #define PRINTINTR(flag) do { \ 2816 if ((status & flag) != 0) { \ 2817 printf("%s" #flag, delim); \ 2818 delim = ","; \ 2819 } \ 2820 } while (0) 2821 2822 if (atw_debug > 1 && status) { 2823 const char *delim = "<"; 2824 2825 printf("%s: reg[STSR] = %x", 2826 sc->sc_dev.dv_xname, status); 2827 2828 PRINTINTR(ATW_INTR_FBE); 2829 PRINTINTR(ATW_INTR_LINKOFF); 2830 PRINTINTR(ATW_INTR_LINKON); 2831 PRINTINTR(ATW_INTR_RCI); 2832 PRINTINTR(ATW_INTR_RDU); 2833 PRINTINTR(ATW_INTR_REIS); 2834 PRINTINTR(ATW_INTR_RPS); 2835 PRINTINTR(ATW_INTR_TCI); 2836 PRINTINTR(ATW_INTR_TDU); 2837 PRINTINTR(ATW_INTR_TLT); 2838 PRINTINTR(ATW_INTR_TPS); 2839 PRINTINTR(ATW_INTR_TRT); 2840 PRINTINTR(ATW_INTR_TUF); 2841 PRINTINTR(ATW_INTR_BCNTC); 2842 PRINTINTR(ATW_INTR_ATIME); 2843 PRINTINTR(ATW_INTR_TBTT); 2844 PRINTINTR(ATW_INTR_TSCZ); 2845 PRINTINTR(ATW_INTR_TSFTF); 2846 printf(">\n"); 2847 } 2848 #undef PRINTINTR 2849 #endif /* ATW_DEBUG */ 2850 2851 if ((status & sc->sc_inten) == 0) 2852 break; 2853 2854 handled = 1; 2855 2856 rxstatus = status & sc->sc_rxint_mask; 2857 txstatus = status & sc->sc_txint_mask; 2858 linkstatus = status & sc->sc_linkint_mask; 2859 2860 if (linkstatus) { 2861 atw_linkintr(sc, linkstatus); 2862 } 2863 2864 if (rxstatus) { 2865 /* Grab any new packets. */ 2866 atw_rxintr(sc); 2867 2868 if (rxstatus & ATW_INTR_RDU) { 2869 printf("%s: receive ring overrun\n", 2870 sc->sc_dev.dv_xname); 2871 /* Get the receive process going again. */ 2872 ATW_WRITE(sc, ATW_RDR, 0x1); 2873 break; 2874 } 2875 } 2876 2877 if (txstatus) { 2878 /* Sweep up transmit descriptors. */ 2879 atw_txintr(sc); 2880 2881 if (txstatus & ATW_INTR_TLT) 2882 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2883 sc->sc_dev.dv_xname)); 2884 2885 if (txstatus & ATW_INTR_TRT) 2886 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2887 sc->sc_dev.dv_xname)); 2888 2889 /* If Tx under-run, increase our transmit threshold 2890 * if another is available. 2891 */ 2892 txthresh = sc->sc_txthresh + 1; 2893 if ((txstatus & ATW_INTR_TUF) && 2894 sc->sc_txth[txthresh].txth_name != NULL) { 2895 /* Idle the transmit process. */ 2896 atw_idle(sc, ATW_NAR_ST); 2897 2898 sc->sc_txthresh = txthresh; 2899 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2900 sc->sc_opmode |= 2901 sc->sc_txth[txthresh].txth_opmode; 2902 printf("%s: transmit underrun; new " 2903 "threshold: %s\n", sc->sc_dev.dv_xname, 2904 sc->sc_txth[txthresh].txth_name); 2905 2906 /* Set the new threshold and restart 2907 * the transmit process. 2908 */ 2909 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2910 DELAY(atw_nar_delay); 2911 ATW_WRITE(sc, ATW_RDR, 0x1); 2912 /* XXX Log every Nth underrun from 2913 * XXX now on? 2914 */ 2915 } 2916 } 2917 2918 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2919 if (status & ATW_INTR_TPS) 2920 printf("%s: transmit process stopped\n", 2921 sc->sc_dev.dv_xname); 2922 if (status & ATW_INTR_RPS) 2923 printf("%s: receive process stopped\n", 2924 sc->sc_dev.dv_xname); 2925 (void)atw_init(ifp); 2926 break; 2927 } 2928 2929 if (status & ATW_INTR_FBE) { 2930 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2931 (void)atw_init(ifp); 2932 break; 2933 } 2934 2935 /* 2936 * Not handled: 2937 * 2938 * Transmit buffer unavailable -- normal 2939 * condition, nothing to do, really. 2940 * 2941 * Early receive interrupt -- not available on 2942 * all chips, we just use RI. We also only 2943 * use single-segment receive DMA, so this 2944 * is mostly useless. 2945 * 2946 * TBD others 2947 */ 2948 } 2949 2950 /* Try to get more packets going. */ 2951 atw_start(ifp); 2952 2953 return (handled); 2954 } 2955 2956 /* 2957 * atw_idle: 2958 * 2959 * Cause the transmit and/or receive processes to go idle. 2960 * 2961 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2962 * process in STSR if I clear SR or ST after the process has already 2963 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2964 * do not seem to be too reliable. Perhaps I have the sense of the 2965 * Rx bits switched with the Tx bits? 2966 */ 2967 void 2968 atw_idle(struct atw_softc *sc, u_int32_t bits) 2969 { 2970 u_int32_t ackmask = 0, opmode, stsr, test0; 2971 int i, s; 2972 2973 s = splnet(); 2974 2975 opmode = sc->sc_opmode & ~bits; 2976 2977 if (bits & ATW_NAR_SR) 2978 ackmask |= ATW_INTR_RPS; 2979 2980 if (bits & ATW_NAR_ST) { 2981 ackmask |= ATW_INTR_TPS; 2982 /* set ATW_NAR_HF to flush TX FIFO. */ 2983 opmode |= ATW_NAR_HF; 2984 } 2985 2986 ATW_WRITE(sc, ATW_NAR, opmode); 2987 DELAY(atw_nar_delay); 2988 2989 for (i = 0; i < 1000; i++) { 2990 stsr = ATW_READ(sc, ATW_STSR); 2991 if ((stsr & ackmask) == ackmask) 2992 break; 2993 DELAY(10); 2994 } 2995 2996 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2997 2998 if ((stsr & ackmask) == ackmask) 2999 goto out; 3000 3001 test0 = ATW_READ(sc, ATW_TEST0); 3002 3003 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3004 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3005 printf("%s: transmit process not idle [%s]\n", 3006 sc->sc_dev.dv_xname, 3007 atw_tx_state[SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3008 printf("%s: bits %08x test0 %08x stsr %08x\n", 3009 sc->sc_dev.dv_xname, bits, test0, stsr); 3010 } 3011 3012 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3013 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3014 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3015 sc->sc_dev.dv_xname, 3016 atw_rx_state[SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3017 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3018 sc->sc_dev.dv_xname, bits, test0, stsr)); 3019 } 3020 out: 3021 if ((bits & ATW_NAR_ST) != 0) 3022 atw_txdrain(sc); 3023 splx(s); 3024 return; 3025 } 3026 3027 /* 3028 * atw_linkintr: 3029 * 3030 * Helper; handle link-status interrupts. 3031 */ 3032 void 3033 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3034 { 3035 struct ieee80211com *ic = &sc->sc_ic; 3036 3037 if (ic->ic_state != IEEE80211_S_RUN) 3038 return; 3039 3040 if (linkstatus & ATW_INTR_LINKON) { 3041 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3042 sc->sc_rescan_timer = 0; 3043 } else if (linkstatus & ATW_INTR_LINKOFF) { 3044 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3045 if (ic->ic_opmode != IEEE80211_M_STA) 3046 return; 3047 sc->sc_rescan_timer = 3; 3048 sc->sc_if.if_timer = 1; 3049 } 3050 } 3051 3052 static inline int 3053 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3054 { 3055 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3056 return 0; 3057 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3058 return 0; 3059 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3060 } 3061 3062 /* 3063 * atw_rxintr: 3064 * 3065 * Helper; handle receive interrupts. 3066 */ 3067 void 3068 atw_rxintr(struct atw_softc *sc) 3069 { 3070 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3071 struct ieee80211com *ic = &sc->sc_ic; 3072 struct ieee80211_node *ni; 3073 struct ieee80211_frame_min *wh; 3074 struct ifnet *ifp = &sc->sc_if; 3075 struct atw_rxsoft *rxs; 3076 struct mbuf *m; 3077 u_int32_t rxstat; 3078 int i, len, rate, rate0; 3079 u_int32_t rssi, rssi0; 3080 3081 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3082 rxs = &sc->sc_rxsoft[i]; 3083 3084 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3085 3086 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3087 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3088 rate0 = SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3089 3090 if (rxstat & ATW_RXSTAT_OWN) 3091 break; /* We have processed all receive buffers. */ 3092 3093 DPRINTF3(sc, 3094 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3095 sc->sc_dev.dv_xname, 3096 rxstat, rssi0, 3097 le32toh(sc->sc_rxdescs[i].ar_buf1), 3098 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3099 3100 /* 3101 * Make sure the packet fits in one buffer. This should 3102 * always be the case. 3103 */ 3104 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3105 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3106 printf("%s: incoming packet spilled, resetting\n", 3107 sc->sc_dev.dv_xname); 3108 (void)atw_init(ifp); 3109 return; 3110 } 3111 3112 /* 3113 * If an error occurred, update stats, clear the status 3114 * word, and leave the packet buffer in place. It will 3115 * simply be reused the next time the ring comes around. 3116 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3117 * error. 3118 */ 3119 3120 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3121 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3122 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3123 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3124 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3125 ATW_RXSTAT_ICVE)) != 0)) { 3126 #define PRINTERR(bit, str) \ 3127 if (rxstat & (bit)) \ 3128 printf("%s: receive error: %s\n", \ 3129 sc->sc_dev.dv_xname, str) 3130 ifp->if_ierrors++; 3131 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3132 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3133 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3134 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3135 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3136 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3137 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3138 #undef PRINTERR 3139 ATW_INIT_RXDESC(sc, i); 3140 continue; 3141 } 3142 3143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3145 3146 /* 3147 * No errors; receive the packet. Note the ADM8211 3148 * includes the CRC in promiscuous mode. 3149 */ 3150 len = SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3151 3152 /* 3153 * Allocate a new mbuf cluster. If that fails, we are 3154 * out of memory, and must drop the packet and recycle 3155 * the buffer that's already attached to this descriptor. 3156 */ 3157 m = rxs->rxs_mbuf; 3158 if (atw_add_rxbuf(sc, i) != 0) { 3159 ifp->if_ierrors++; 3160 ATW_INIT_RXDESC(sc, i); 3161 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3162 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3163 continue; 3164 } 3165 3166 ifp->if_ipackets++; 3167 if (sc->sc_opmode & ATW_NAR_PR) 3168 len -= IEEE80211_CRC_LEN; 3169 m->m_pkthdr.rcvif = ifp; 3170 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3171 3172 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3173 rate = 0; 3174 else 3175 rate = rate_tbl[rate0]; 3176 3177 /* The RSSI comes straight from a register in the 3178 * baseband processor. I know that for the RF3000, 3179 * the RSSI register also contains the antenna-selection 3180 * bits. Mask those off. 3181 * 3182 * TBD Treat other basebands. 3183 */ 3184 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3185 rssi = rssi0 & RF3000_RSSI_MASK; 3186 else 3187 rssi = rssi0; 3188 3189 #if NBPFILTER > 0 3190 /* Pass this up to any BPF listeners. */ 3191 if (sc->sc_radiobpf != NULL) { 3192 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3193 3194 tap->ar_rate = rate; 3195 tap->ar_chan_freq = htole16(ic->ic_curchan->ic_freq); 3196 tap->ar_chan_flags = htole16(ic->ic_curchan->ic_flags); 3197 3198 /* TBD verify units are dB */ 3199 tap->ar_antsignal = (int)rssi; 3200 /* TBD tap->ar_flags */ 3201 3202 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3203 tap->ar_ihdr.it_len, m); 3204 } 3205 #endif /* NPBFILTER > 0 */ 3206 3207 wh = mtod(m, struct ieee80211_frame_min *); 3208 ni = ieee80211_find_rxnode(ic, wh); 3209 #if 0 3210 if (atw_hw_decrypted(sc, wh)) { 3211 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3212 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3213 } 3214 #endif 3215 ieee80211_input(ic, m, ni, (int)rssi, 0); 3216 ieee80211_free_node(ni); 3217 } 3218 3219 /* Update the receive pointer. */ 3220 sc->sc_rxptr = i; 3221 } 3222 3223 /* 3224 * atw_txintr: 3225 * 3226 * Helper; handle transmit interrupts. 3227 */ 3228 void 3229 atw_txintr(struct atw_softc *sc) 3230 { 3231 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3232 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3233 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3234 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3235 3236 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3237 struct ifnet *ifp = &sc->sc_if; 3238 struct atw_txsoft *txs; 3239 u_int32_t txstat; 3240 3241 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3242 sc->sc_dev.dv_xname, sc->sc_flags)); 3243 3244 /* 3245 * Go through our Tx list and free mbufs for those 3246 * frames that have been transmitted. 3247 */ 3248 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3249 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3250 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3251 3252 #ifdef ATW_DEBUG 3253 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3254 int i; 3255 printf(" txsoft %p transmit chain:\n", txs); 3256 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3257 txs->txs_ndescs - 1, 3258 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3259 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3260 printf(" descriptor %d:\n", i); 3261 printf(" at_status: 0x%08x\n", 3262 le32toh(sc->sc_txdescs[i].at_stat)); 3263 printf(" at_flags: 0x%08x\n", 3264 le32toh(sc->sc_txdescs[i].at_flags)); 3265 printf(" at_buf1: 0x%08x\n", 3266 le32toh(sc->sc_txdescs[i].at_buf1)); 3267 printf(" at_buf2: 0x%08x\n", 3268 le32toh(sc->sc_txdescs[i].at_buf2)); 3269 if (i == txs->txs_lastdesc) 3270 break; 3271 } 3272 } 3273 #endif 3274 3275 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3276 if (txstat & ATW_TXSTAT_OWN) 3277 break; 3278 3279 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3280 3281 sc->sc_txfree += txs->txs_ndescs; 3282 3283 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3284 0, txs->txs_dmamap->dm_mapsize, 3285 BUS_DMASYNC_POSTWRITE); 3286 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3287 m_freem(txs->txs_mbuf); 3288 txs->txs_mbuf = NULL; 3289 3290 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3291 3292 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3293 sc->sc_txfree == 0)); 3294 ifp->if_flags &= ~IFF_OACTIVE; 3295 3296 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3297 (txstat & TXSTAT_ERRMASK) != 0) { 3298 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3299 txstat_buf, sizeof(txstat_buf)); 3300 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3301 txstat_buf, 3302 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3303 } 3304 3305 /* 3306 * Check for errors and collisions. 3307 */ 3308 if (txstat & ATW_TXSTAT_TUF) 3309 sc->sc_stats.ts_tx_tuf++; 3310 if (txstat & ATW_TXSTAT_TLT) 3311 sc->sc_stats.ts_tx_tlt++; 3312 if (txstat & ATW_TXSTAT_TRT) 3313 sc->sc_stats.ts_tx_trt++; 3314 if (txstat & ATW_TXSTAT_TRO) 3315 sc->sc_stats.ts_tx_tro++; 3316 if (txstat & ATW_TXSTAT_SOFBR) { 3317 sc->sc_stats.ts_tx_sofbr++; 3318 } 3319 3320 if ((txstat & ATW_TXSTAT_ES) == 0) 3321 ifp->if_collisions += 3322 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3323 else 3324 ifp->if_oerrors++; 3325 3326 ifp->if_opackets++; 3327 } 3328 3329 /* 3330 * If there are no more pending transmissions, cancel the watchdog 3331 * timer. 3332 */ 3333 if (txs == NULL) { 3334 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3335 sc->sc_tx_timer = 0; 3336 } 3337 #undef TXSTAT_ERRMASK 3338 #undef TXSTAT_FMT 3339 } 3340 3341 /* 3342 * atw_watchdog: [ifnet interface function] 3343 * 3344 * Watchdog timer handler. 3345 */ 3346 void 3347 atw_watchdog(struct ifnet *ifp) 3348 { 3349 struct atw_softc *sc = ifp->if_softc; 3350 struct ieee80211com *ic = &sc->sc_ic; 3351 3352 ifp->if_timer = 0; 3353 if (ATW_IS_ENABLED(sc) == 0) 3354 return; 3355 3356 if (sc->sc_rescan_timer) { 3357 if (--sc->sc_rescan_timer == 0) 3358 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3359 } 3360 if (sc->sc_tx_timer) { 3361 if (--sc->sc_tx_timer == 0 && 3362 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3363 printf("%s: transmit timeout\n", ifp->if_xname); 3364 ifp->if_oerrors++; 3365 (void)atw_init(ifp); 3366 atw_start(ifp); 3367 } 3368 } 3369 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3370 ifp->if_timer = 1; 3371 ieee80211_watchdog(ic); 3372 } 3373 3374 #ifdef ATW_DEBUG 3375 static void 3376 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3377 { 3378 struct atw_softc *sc = ifp->if_softc; 3379 struct mbuf *m; 3380 int i, noctets = 0; 3381 3382 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3383 m0->m_pkthdr.len); 3384 3385 for (m = m0; m; m = m->m_next) { 3386 if (m->m_len == 0) 3387 continue; 3388 for (i = 0; i < m->m_len; i++) { 3389 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3390 if (++noctets % 24 == 0) 3391 printf("\n"); 3392 } 3393 } 3394 printf("%s%s: %d bytes emitted\n", 3395 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3396 } 3397 #endif /* ATW_DEBUG */ 3398 3399 /* 3400 * atw_start: [ifnet interface function] 3401 * 3402 * Start packet transmission on the interface. 3403 */ 3404 void 3405 atw_start(struct ifnet *ifp) 3406 { 3407 struct atw_softc *sc = ifp->if_softc; 3408 struct ieee80211_key *k; 3409 struct ieee80211com *ic = &sc->sc_ic; 3410 struct ieee80211_node *ni; 3411 struct ieee80211_frame_min *whm; 3412 struct ieee80211_frame *wh; 3413 struct atw_frame *hh; 3414 struct mbuf *m0, *m; 3415 struct atw_txsoft *txs, *last_txs; 3416 struct atw_txdesc *txd; 3417 int npkt, rate; 3418 bus_dmamap_t dmamap; 3419 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3420 3421 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3422 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3423 3424 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3425 return; 3426 3427 /* 3428 * Remember the previous number of free descriptors and 3429 * the first descriptor we'll use. 3430 */ 3431 ofree = sc->sc_txfree; 3432 firsttx = lasttx = sc->sc_txnext; 3433 3434 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3435 sc->sc_dev.dv_xname, ofree, firsttx)); 3436 3437 /* 3438 * Loop through the send queue, setting up transmit descriptors 3439 * until we drain the queue, or use up all available transmit 3440 * descriptors. 3441 */ 3442 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3443 sc->sc_txfree != 0) { 3444 3445 /* 3446 * Grab a packet off the management queue, if it 3447 * is not empty. Otherwise, from the data queue. 3448 */ 3449 IF_DEQUEUE(&ic->ic_mgtq, m0); 3450 if (m0 != NULL) { 3451 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3452 m0->m_pkthdr.rcvif = NULL; 3453 } else if (ic->ic_state != IEEE80211_S_RUN) 3454 break; /* send no data until associated */ 3455 else { 3456 IFQ_DEQUEUE(&ifp->if_snd, m0); 3457 if (m0 == NULL) 3458 break; 3459 #if NBPFILTER > 0 3460 if (ifp->if_bpf != NULL) 3461 bpf_mtap(ifp->if_bpf, m0); 3462 #endif /* NBPFILTER > 0 */ 3463 ni = ieee80211_find_txnode(ic, 3464 mtod(m0, struct ether_header *)->ether_dhost); 3465 if (ni == NULL) { 3466 ifp->if_oerrors++; 3467 break; 3468 } 3469 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3470 ieee80211_free_node(ni); 3471 ifp->if_oerrors++; 3472 break; 3473 } 3474 } 3475 3476 rate = MAX(ieee80211_get_rate(ni), 2); 3477 3478 whm = mtod(m0, struct ieee80211_frame_min *); 3479 3480 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3481 k = NULL; 3482 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3483 m_freem(m0); 3484 ieee80211_free_node(ni); 3485 ifp->if_oerrors++; 3486 break; 3487 } 3488 3489 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3490 ic->ic_flags, ic->ic_fragthreshold, rate, 3491 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3492 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3493 m_freem(m0); 3494 break; 3495 } 3496 3497 /* XXX Misleading if fragmentation is enabled. Better 3498 * to fragment in software? 3499 */ 3500 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3501 3502 #if NBPFILTER > 0 3503 /* 3504 * Pass the packet to any BPF listeners. 3505 */ 3506 if (ic->ic_rawbpf != NULL) 3507 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3508 3509 if (sc->sc_radiobpf != NULL) { 3510 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3511 3512 tap->at_rate = rate; 3513 tap->at_chan_freq = htole16(ic->ic_curchan->ic_freq); 3514 tap->at_chan_flags = htole16(ic->ic_curchan->ic_flags); 3515 3516 /* TBD tap->at_flags */ 3517 3518 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3519 tap->at_ihdr.it_len, m0); 3520 } 3521 #endif /* NBPFILTER > 0 */ 3522 3523 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3524 3525 if (ni != NULL) 3526 ieee80211_free_node(ni); 3527 3528 if (m0 == NULL) { 3529 ifp->if_oerrors++; 3530 break; 3531 } 3532 3533 /* just to make sure. */ 3534 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3535 3536 if (m0 == NULL) { 3537 ifp->if_oerrors++; 3538 break; 3539 } 3540 3541 hh = mtod(m0, struct atw_frame *); 3542 wh = &hh->atw_ihdr; 3543 3544 /* Copy everything we need from the 802.11 header: 3545 * Frame Control; address 1, address 3, or addresses 3546 * 3 and 4. NIC fills in BSSID, SA. 3547 */ 3548 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3549 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3550 panic("%s: illegal WDS frame", 3551 sc->sc_dev.dv_xname); 3552 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3553 } else 3554 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3555 3556 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3557 3558 /* initialize remaining Tx parameters */ 3559 memset(&hh->u, 0, sizeof(hh->u)); 3560 3561 hh->atw_rate = rate * 5; 3562 /* XXX this could be incorrect if M_FCS. _encap should 3563 * probably strip FCS just in case it sticks around in 3564 * bridged packets. 3565 */ 3566 hh->atw_service = 0x00; /* XXX guess */ 3567 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3568 sizeof(struct atw_frame)); 3569 3570 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3571 hh->atw_rtylmt = 3; 3572 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3573 #if 0 3574 if (do_encrypt) { 3575 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3576 hh->atw_keyid = ic->ic_def_txkey; 3577 } 3578 #endif 3579 3580 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3581 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3582 if (txs->txs_d0.d_residue) 3583 hh->atw_head_plcplen |= htole16(0x8000); 3584 if (txs->txs_dn.d_residue) 3585 hh->atw_tail_plcplen |= htole16(0x8000); 3586 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3587 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3588 3589 /* never fragment multicast frames */ 3590 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3591 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3592 } else if (sc->sc_flags & ATWF_RTSCTS) { 3593 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3594 } 3595 3596 #ifdef ATW_DEBUG 3597 hh->atw_fragnum = 0; 3598 3599 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3600 printf("%s: dst = %s, rate = 0x%02x, " 3601 "service = 0x%02x, paylen = 0x%04x\n", 3602 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3603 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3604 3605 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3606 "dur1 = 0x%04x, dur2 = 0x%04x, " 3607 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3608 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3609 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3610 hh->atw_tail_dur, hh->atw_head_dur); 3611 3612 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3613 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3614 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3615 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3616 3617 printf("%s: keyid = %d\n", 3618 sc->sc_dev.dv_xname, hh->atw_keyid); 3619 3620 atw_dump_pkt(ifp, m0); 3621 } 3622 #endif /* ATW_DEBUG */ 3623 3624 dmamap = txs->txs_dmamap; 3625 3626 /* 3627 * Load the DMA map. Copy and try (once) again if the packet 3628 * didn't fit in the alloted number of segments. 3629 */ 3630 for (first = 1; 3631 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3632 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3633 first = 0) { 3634 MGETHDR(m, M_DONTWAIT, MT_DATA); 3635 if (m == NULL) { 3636 printf("%s: unable to allocate Tx mbuf\n", 3637 sc->sc_dev.dv_xname); 3638 break; 3639 } 3640 if (m0->m_pkthdr.len > MHLEN) { 3641 MCLGET(m, M_DONTWAIT); 3642 if ((m->m_flags & M_EXT) == 0) { 3643 printf("%s: unable to allocate Tx " 3644 "cluster\n", sc->sc_dev.dv_xname); 3645 m_freem(m); 3646 break; 3647 } 3648 } 3649 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3650 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3651 m_freem(m0); 3652 m0 = m; 3653 m = NULL; 3654 } 3655 if (error != 0) { 3656 printf("%s: unable to load Tx buffer, " 3657 "error = %d\n", sc->sc_dev.dv_xname, error); 3658 m_freem(m0); 3659 break; 3660 } 3661 3662 /* 3663 * Ensure we have enough descriptors free to describe 3664 * the packet. 3665 */ 3666 if (dmamap->dm_nsegs > sc->sc_txfree) { 3667 /* 3668 * Not enough free descriptors to transmit 3669 * this packet. Unload the DMA map and 3670 * drop the packet. Notify the upper layer 3671 * that there are no more slots left. 3672 * 3673 * XXX We could allocate an mbuf and copy, but 3674 * XXX it is worth it? 3675 */ 3676 bus_dmamap_unload(sc->sc_dmat, dmamap); 3677 m_freem(m0); 3678 break; 3679 } 3680 3681 /* 3682 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3683 */ 3684 3685 /* Sync the DMA map. */ 3686 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3687 BUS_DMASYNC_PREWRITE); 3688 3689 /* XXX arbitrary retry limit; 8 because I have seen it in 3690 * use already and maybe 0 means "no tries" ! 3691 */ 3692 ctl = htole32(SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3693 3694 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3695 sc->sc_dev.dv_xname, rate * 5)); 3696 ctl |= htole32(SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3697 3698 /* 3699 * Initialize the transmit descriptors. 3700 */ 3701 for (nexttx = sc->sc_txnext, seg = 0; 3702 seg < dmamap->dm_nsegs; 3703 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3704 /* 3705 * If this is the first descriptor we're 3706 * enqueueing, don't set the OWN bit just 3707 * yet. That could cause a race condition. 3708 * We'll do it below. 3709 */ 3710 txd = &sc->sc_txdescs[nexttx]; 3711 txd->at_ctl = ctl | 3712 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3713 3714 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3715 txd->at_flags = 3716 htole32(SHIFTIN(dmamap->dm_segs[seg].ds_len, 3717 ATW_TXFLAG_TBS1_MASK)) | 3718 ((nexttx == (ATW_NTXDESC - 1)) 3719 ? htole32(ATW_TXFLAG_TER) : 0); 3720 lasttx = nexttx; 3721 } 3722 3723 /* Set `first segment' and `last segment' appropriately. */ 3724 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3725 htole32(ATW_TXFLAG_FS); 3726 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3727 3728 #ifdef ATW_DEBUG 3729 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3730 printf(" txsoft %p transmit chain:\n", txs); 3731 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3732 printf(" descriptor %d:\n", seg); 3733 printf(" at_ctl: 0x%08x\n", 3734 le32toh(sc->sc_txdescs[seg].at_ctl)); 3735 printf(" at_flags: 0x%08x\n", 3736 le32toh(sc->sc_txdescs[seg].at_flags)); 3737 printf(" at_buf1: 0x%08x\n", 3738 le32toh(sc->sc_txdescs[seg].at_buf1)); 3739 printf(" at_buf2: 0x%08x\n", 3740 le32toh(sc->sc_txdescs[seg].at_buf2)); 3741 if (seg == lasttx) 3742 break; 3743 } 3744 } 3745 #endif 3746 3747 /* Sync the descriptors we're using. */ 3748 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3750 3751 /* 3752 * Store a pointer to the packet so we can free it later, 3753 * and remember what txdirty will be once the packet is 3754 * done. 3755 */ 3756 txs->txs_mbuf = m0; 3757 txs->txs_firstdesc = sc->sc_txnext; 3758 txs->txs_lastdesc = lasttx; 3759 txs->txs_ndescs = dmamap->dm_nsegs; 3760 3761 /* Advance the tx pointer. */ 3762 sc->sc_txfree -= dmamap->dm_nsegs; 3763 sc->sc_txnext = nexttx; 3764 3765 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3766 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3767 3768 last_txs = txs; 3769 } 3770 3771 if (sc->sc_txfree != ofree) { 3772 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3773 sc->sc_dev.dv_xname, lasttx, firsttx)); 3774 /* 3775 * Cause a transmit interrupt to happen on the 3776 * last packet we enqueued. 3777 */ 3778 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3779 ATW_CDTXSYNC(sc, lasttx, 1, 3780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3781 3782 /* 3783 * The entire packet chain is set up. Give the 3784 * first descriptor to the chip now. 3785 */ 3786 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3787 ATW_CDTXSYNC(sc, firsttx, 1, 3788 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3789 3790 /* Wake up the transmitter. */ 3791 ATW_WRITE(sc, ATW_TDR, 0x1); 3792 3793 if (txs == NULL || sc->sc_txfree == 0) 3794 ifp->if_flags |= IFF_OACTIVE; 3795 3796 /* Set a watchdog timer in case the chip flakes out. */ 3797 sc->sc_tx_timer = 5; 3798 ifp->if_timer = 1; 3799 } 3800 } 3801 3802 /* 3803 * atw_power: 3804 * 3805 * Power management (suspend/resume) hook. 3806 */ 3807 void 3808 atw_power(int why, void *arg) 3809 { 3810 struct atw_softc *sc = arg; 3811 struct ifnet *ifp = &sc->sc_if; 3812 int s; 3813 3814 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3815 3816 s = splnet(); 3817 switch (why) { 3818 case PWR_STANDBY: 3819 /* XXX do nothing. */ 3820 break; 3821 case PWR_SUSPEND: 3822 atw_stop(ifp, 0); 3823 if (sc->sc_power != NULL) 3824 (*sc->sc_power)(sc, why); 3825 break; 3826 case PWR_RESUME: 3827 if (ifp->if_flags & IFF_UP) { 3828 if (sc->sc_power != NULL) 3829 (*sc->sc_power)(sc, why); 3830 atw_init(ifp); 3831 } 3832 break; 3833 case PWR_SOFTSUSPEND: 3834 case PWR_SOFTSTANDBY: 3835 case PWR_SOFTRESUME: 3836 break; 3837 } 3838 splx(s); 3839 } 3840 3841 /* 3842 * atw_ioctl: [ifnet interface function] 3843 * 3844 * Handle control requests from the operator. 3845 */ 3846 int 3847 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3848 { 3849 struct atw_softc *sc = ifp->if_softc; 3850 struct ifreq *ifr = (struct ifreq *)data; 3851 int s, error = 0; 3852 3853 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3854 if (!device_is_active(&sc->sc_dev)) 3855 return ENXIO; 3856 3857 s = splnet(); 3858 3859 switch (cmd) { 3860 case SIOCSIFFLAGS: 3861 if (ifp->if_flags & IFF_UP) { 3862 if (ATW_IS_ENABLED(sc)) { 3863 /* 3864 * To avoid rescanning another access point, 3865 * do not call atw_init() here. Instead, 3866 * only reflect media settings. 3867 */ 3868 atw_filter_setup(sc); 3869 } else 3870 error = atw_init(ifp); 3871 } else if (ATW_IS_ENABLED(sc)) 3872 atw_stop(ifp, 1); 3873 break; 3874 case SIOCADDMULTI: 3875 case SIOCDELMULTI: 3876 error = (cmd == SIOCADDMULTI) ? 3877 ether_addmulti(ifr, &sc->sc_ec) : 3878 ether_delmulti(ifr, &sc->sc_ec); 3879 if (error == ENETRESET) { 3880 if (ifp->if_flags & IFF_RUNNING) 3881 atw_filter_setup(sc); /* do not rescan */ 3882 error = 0; 3883 } 3884 break; 3885 default: 3886 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3887 if (error == ENETRESET || error == ERESTART) { 3888 if (is_running(ifp)) 3889 error = atw_init(ifp); 3890 else 3891 error = 0; 3892 } 3893 break; 3894 } 3895 3896 /* Try to get more packets going. */ 3897 if (ATW_IS_ENABLED(sc)) 3898 atw_start(ifp); 3899 3900 splx(s); 3901 return (error); 3902 } 3903 3904 static int 3905 atw_media_change(struct ifnet *ifp) 3906 { 3907 int error; 3908 3909 error = ieee80211_media_change(ifp); 3910 if (error == ENETRESET) { 3911 if (is_running(ifp)) 3912 error = atw_init(ifp); 3913 else 3914 error = 0; 3915 } 3916 return error; 3917 } 3918
Indexes created Thu Sep 25 16:09:42 GMT 2025