atw.c revision 1.119
1 /* $NetBSD: atw.c,v 1.119 2006/08/31 19:24:37 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.119 2006/08/31 19:24:37 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 #include <lib/libkern/libkern.h> 60 61 #include <machine/endian.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #include <net80211/ieee80211_netbsd.h> 71 #include <net80211/ieee80211_var.h> 72 #include <net80211/ieee80211_radiotap.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/ic/atwreg.h> 82 #include <dev/ic/rf3000reg.h> 83 #include <dev/ic/si4136reg.h> 84 #include <dev/ic/atwvar.h> 85 #include <dev/ic/smc93cx6var.h> 86 87 /* XXX TBD open questions 88 * 89 * 90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 92 * handle this for me? 93 * 94 */ 95 /* device attachment 96 * 97 * print TOFS[012] 98 * 99 * device initialization 100 * 101 * clear ATW_FRCTL_MAXPSP to disable max power saving 102 * set ATW_TXBR_ALCUPDATE to enable ALC 103 * set TOFS[012]? (hope not) 104 * disable rx/tx 105 * set ATW_PAR_SWR (software reset) 106 * wait for ATW_PAR_SWR clear 107 * disable interrupts 108 * ack status register 109 * enable interrupts 110 * 111 * rx/tx initialization 112 * 113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * allocate and init descriptor rings 115 * write ATW_PAR_DSL (descriptor skip length) 116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * write ATW_NAR_SQ for one/both transmit descriptor rings 119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 120 * 121 * rx/tx end 122 * 123 * stop DMA 124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 125 * flush tx w/ ATW_NAR_HF 126 * 127 * scan 128 * 129 * initialize rx/tx 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 140 141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 143 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 144 145 int atw_pseudo_milli = 1; 146 int atw_magic_delay1 = 100 * 1000; 147 int atw_magic_delay2 = 100 * 1000; 148 /* more magic multi-millisecond delays (units: microseconds) */ 149 int atw_nar_delay = 20 * 1000; 150 int atw_magic_delay4 = 10 * 1000; 151 int atw_rf_delay1 = 10 * 1000; 152 int atw_rf_delay2 = 5 * 1000; 153 int atw_plcphd_delay = 2 * 1000; 154 int atw_bbp_io_enable_delay = 20 * 1000; 155 int atw_bbp_io_disable_delay = 2 * 1000; 156 int atw_writewep_delay = 1000; 157 int atw_beacon_len_adjust = 4; 158 int atw_dwelltime = 200; 159 int atw_xindiv2 = 0; 160 161 #ifdef ATW_DEBUG 162 int atw_debug = 0; 163 164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 170 171 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 172 static void atw_print_regs(struct atw_softc *, const char *); 173 174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 175 # ifdef ATW_BBPDEBUG 176 static void atw_rf3000_print(struct atw_softc *); 177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 178 # endif /* ATW_BBPDEBUG */ 179 180 # ifdef ATW_SYNDEBUG 181 static void atw_si4126_print(struct atw_softc *); 182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 183 # endif /* ATW_SYNDEBUG */ 184 185 #else 186 #define ATW_DPRINTF(x) 187 #define ATW_DPRINTF2(x) 188 #define ATW_DPRINTF3(x) 189 #define DPRINTF(sc, x) /* nothing */ 190 #define DPRINTF2(sc, x) /* nothing */ 191 #define DPRINTF3(sc, x) /* nothing */ 192 #endif 193 194 /* ifnet methods */ 195 int atw_init(struct ifnet *); 196 int atw_ioctl(struct ifnet *, u_long, caddr_t); 197 void atw_start(struct ifnet *); 198 void atw_stop(struct ifnet *, int); 199 void atw_watchdog(struct ifnet *); 200 201 /* Device attachment */ 202 void atw_attach(struct atw_softc *); 203 int atw_detach(struct atw_softc *); 204 205 /* Rx/Tx process */ 206 int atw_add_rxbuf(struct atw_softc *, int); 207 void atw_idle(struct atw_softc *, u_int32_t); 208 void atw_rxdrain(struct atw_softc *); 209 void atw_txdrain(struct atw_softc *); 210 211 /* Device (de)activation and power state */ 212 void atw_disable(struct atw_softc *); 213 int atw_enable(struct atw_softc *); 214 void atw_power(int, void *); 215 void atw_reset(struct atw_softc *); 216 void atw_shutdown(void *); 217 218 /* Interrupt handlers */ 219 void atw_linkintr(struct atw_softc *, u_int32_t); 220 void atw_rxintr(struct atw_softc *); 221 void atw_txintr(struct atw_softc *); 222 223 /* 802.11 state machine */ 224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 225 static void atw_next_scan(void *); 226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static int atw_tune(struct atw_softc *); 229 230 /* Device initialization */ 231 static void atw_bbp_io_init(struct atw_softc *); 232 static void atw_cfp_init(struct atw_softc *); 233 static void atw_cmdr_init(struct atw_softc *); 234 static void atw_ifs_init(struct atw_softc *); 235 static void atw_nar_init(struct atw_softc *); 236 static void atw_response_times_init(struct atw_softc *); 237 static void atw_rf_reset(struct atw_softc *); 238 static void atw_test1_init(struct atw_softc *); 239 static void atw_tofs0_init(struct atw_softc *); 240 static void atw_tofs2_init(struct atw_softc *); 241 static void atw_txlmt_init(struct atw_softc *); 242 static void atw_wcsr_init(struct atw_softc *); 243 244 /* Key management */ 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(struct device *self, enum devact act) 323 { 324 struct atw_softc *sc = (struct atw_softc *)self; 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 printf("%s: device enable failed\n", 353 sc->sc_dev.dv_xname); 354 return (EIO); 355 } 356 sc->sc_flags |= ATWF_ENABLED; 357 /* Power may have been removed, and WEP keys thus 358 * reset. 359 */ 360 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 361 } 362 return (0); 363 } 364 365 /* 366 * atw_disable: 367 * 368 * Disable the ADM8211 chip. 369 */ 370 void 371 atw_disable(struct atw_softc *sc) 372 { 373 if (!ATW_IS_ENABLED(sc)) 374 return; 375 if (sc->sc_disable != NULL) 376 (*sc->sc_disable)(sc); 377 sc->sc_flags &= ~ATWF_ENABLED; 378 } 379 380 /* Returns -1 on failure. */ 381 static int 382 atw_read_srom(struct atw_softc *sc) 383 { 384 struct seeprom_descriptor sd; 385 uint32_t test0, fail_bits; 386 387 (void)memset(&sd, 0, sizeof(sd)); 388 389 test0 = ATW_READ(sc, ATW_TEST0); 390 391 switch (sc->sc_rev) { 392 case ATW_REVISION_BA: 393 case ATW_REVISION_CA: 394 fail_bits = ATW_TEST0_EPNE; 395 break; 396 default: 397 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 398 break; 399 } 400 if ((test0 & fail_bits) != 0) { 401 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 switch (test0 & ATW_TEST0_EPTYP_MASK) { 406 case ATW_TEST0_EPTYP_93c66: 407 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 408 sc->sc_sromsz = 512; 409 sd.sd_chip = C56_66; 410 break; 411 case ATW_TEST0_EPTYP_93c46: 412 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 413 sc->sc_sromsz = 128; 414 sd.sd_chip = C46; 415 break; 416 default: 417 printf("%s: unknown SROM type %d\n", 418 sc->sc_dev.dv_xname, 419 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 420 return -1; 421 } 422 423 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 424 425 if (sc->sc_srom == NULL) { 426 printf("%s: unable to allocate SROM buffer\n", 427 sc->sc_dev.dv_xname); 428 return -1; 429 } 430 431 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 432 433 /* ADM8211 has a single 32-bit register for controlling the 434 * 93cx6 SROM. Bit SRS enables the serial port. There is no 435 * "ready" bit. The ADM8211 input/output sense is the reverse 436 * of read_seeprom's. 437 */ 438 sd.sd_tag = sc->sc_st; 439 sd.sd_bsh = sc->sc_sh; 440 sd.sd_regsize = 4; 441 sd.sd_control_offset = ATW_SPR; 442 sd.sd_status_offset = ATW_SPR; 443 sd.sd_dataout_offset = ATW_SPR; 444 sd.sd_CK = ATW_SPR_SCLK; 445 sd.sd_CS = ATW_SPR_SCS; 446 sd.sd_DI = ATW_SPR_SDO; 447 sd.sd_DO = ATW_SPR_SDI; 448 sd.sd_MS = ATW_SPR_SRS; 449 sd.sd_RDY = 0; 450 451 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 452 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 453 free(sc->sc_srom, M_DEVBUF); 454 return -1; 455 } 456 #ifdef ATW_DEBUG 457 { 458 int i; 459 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 460 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 461 if (((i % 8) == 0) && (i != 0)) { 462 ATW_DPRINTF(("\n\t")); 463 } 464 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 465 } 466 ATW_DPRINTF(("\n")); 467 } 468 #endif /* ATW_DEBUG */ 469 return 0; 470 } 471 472 #ifdef ATW_DEBUG 473 static void 474 atw_print_regs(struct atw_softc *sc, const char *where) 475 { 476 #define PRINTREG(sc, reg) \ 477 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 478 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 479 480 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 481 482 PRINTREG(sc, ATW_PAR); 483 PRINTREG(sc, ATW_FRCTL); 484 PRINTREG(sc, ATW_TDR); 485 PRINTREG(sc, ATW_WTDP); 486 PRINTREG(sc, ATW_RDR); 487 PRINTREG(sc, ATW_WRDP); 488 PRINTREG(sc, ATW_RDB); 489 PRINTREG(sc, ATW_CSR3A); 490 PRINTREG(sc, ATW_TDBD); 491 PRINTREG(sc, ATW_TDBP); 492 PRINTREG(sc, ATW_STSR); 493 PRINTREG(sc, ATW_CSR5A); 494 PRINTREG(sc, ATW_NAR); 495 PRINTREG(sc, ATW_CSR6A); 496 PRINTREG(sc, ATW_IER); 497 PRINTREG(sc, ATW_CSR7A); 498 PRINTREG(sc, ATW_LPC); 499 PRINTREG(sc, ATW_TEST1); 500 PRINTREG(sc, ATW_SPR); 501 PRINTREG(sc, ATW_TEST0); 502 PRINTREG(sc, ATW_WCSR); 503 PRINTREG(sc, ATW_WPDR); 504 PRINTREG(sc, ATW_GPTMR); 505 PRINTREG(sc, ATW_GPIO); 506 PRINTREG(sc, ATW_BBPCTL); 507 PRINTREG(sc, ATW_SYNCTL); 508 PRINTREG(sc, ATW_PLCPHD); 509 PRINTREG(sc, ATW_MMIWADDR); 510 PRINTREG(sc, ATW_MMIRADDR1); 511 PRINTREG(sc, ATW_MMIRADDR2); 512 PRINTREG(sc, ATW_TXBR); 513 PRINTREG(sc, ATW_CSR15A); 514 PRINTREG(sc, ATW_ALCSTAT); 515 PRINTREG(sc, ATW_TOFS2); 516 PRINTREG(sc, ATW_CMDR); 517 PRINTREG(sc, ATW_PCIC); 518 PRINTREG(sc, ATW_PMCSR); 519 PRINTREG(sc, ATW_PAR0); 520 PRINTREG(sc, ATW_PAR1); 521 PRINTREG(sc, ATW_MAR0); 522 PRINTREG(sc, ATW_MAR1); 523 PRINTREG(sc, ATW_ATIMDA0); 524 PRINTREG(sc, ATW_ABDA1); 525 PRINTREG(sc, ATW_BSSID0); 526 PRINTREG(sc, ATW_TXLMT); 527 PRINTREG(sc, ATW_MIBCNT); 528 PRINTREG(sc, ATW_BCNT); 529 PRINTREG(sc, ATW_TSFTH); 530 PRINTREG(sc, ATW_TSC); 531 PRINTREG(sc, ATW_SYNRF); 532 PRINTREG(sc, ATW_BPLI); 533 PRINTREG(sc, ATW_CAP0); 534 PRINTREG(sc, ATW_CAP1); 535 PRINTREG(sc, ATW_RMD); 536 PRINTREG(sc, ATW_CFPP); 537 PRINTREG(sc, ATW_TOFS0); 538 PRINTREG(sc, ATW_TOFS1); 539 PRINTREG(sc, ATW_IFST); 540 PRINTREG(sc, ATW_RSPT); 541 PRINTREG(sc, ATW_TSFTL); 542 PRINTREG(sc, ATW_WEPCTL); 543 PRINTREG(sc, ATW_WESK); 544 PRINTREG(sc, ATW_WEPCNT); 545 PRINTREG(sc, ATW_MACTEST); 546 PRINTREG(sc, ATW_FER); 547 PRINTREG(sc, ATW_FEMR); 548 PRINTREG(sc, ATW_FPSR); 549 PRINTREG(sc, ATW_FFER); 550 #undef PRINTREG 551 } 552 #endif /* ATW_DEBUG */ 553 554 /* 555 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 556 */ 557 void 558 atw_attach(struct atw_softc *sc) 559 { 560 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 562 }; 563 struct ieee80211com *ic = &sc->sc_ic; 564 struct ifnet *ifp = &sc->sc_if; 565 int country_code, error, i, nrate, srom_major; 566 u_int32_t reg; 567 static const char *type_strings[] = {"Intersil (not supported)", 568 "RFMD", "Marvel (not supported)"}; 569 570 sc->sc_txth = atw_txthresh_tab_lo; 571 572 SIMPLEQ_INIT(&sc->sc_txfreeq); 573 SIMPLEQ_INIT(&sc->sc_txdirtyq); 574 575 #ifdef ATW_DEBUG 576 atw_print_regs(sc, "atw_attach"); 577 #endif /* ATW_DEBUG */ 578 579 /* 580 * Allocate the control data structures, and create and load the 581 * DMA map for it. 582 */ 583 if ((error = bus_dmamem_alloc(sc->sc_dmat, 584 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 585 1, &sc->sc_cdnseg, 0)) != 0) { 586 printf("%s: unable to allocate control data, error = %d\n", 587 sc->sc_dev.dv_xname, error); 588 goto fail_0; 589 } 590 591 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 592 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 593 BUS_DMA_COHERENT)) != 0) { 594 printf("%s: unable to map control data, error = %d\n", 595 sc->sc_dev.dv_xname, error); 596 goto fail_1; 597 } 598 599 if ((error = bus_dmamap_create(sc->sc_dmat, 600 sizeof(struct atw_control_data), 1, 601 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 602 printf("%s: unable to create control data DMA map, " 603 "error = %d\n", sc->sc_dev.dv_xname, error); 604 goto fail_2; 605 } 606 607 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 608 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 609 0)) != 0) { 610 printf("%s: unable to load control data DMA map, error = %d\n", 611 sc->sc_dev.dv_xname, error); 612 goto fail_3; 613 } 614 615 /* 616 * Create the transmit buffer DMA maps. 617 */ 618 sc->sc_ntxsegs = ATW_NTXSEGS; 619 for (i = 0; i < ATW_TXQUEUELEN; i++) { 620 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 621 sc->sc_ntxsegs, MCLBYTES, 0, 0, 622 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 623 printf("%s: unable to create tx DMA map %d, " 624 "error = %d\n", sc->sc_dev.dv_xname, i, error); 625 goto fail_4; 626 } 627 } 628 629 /* 630 * Create the receive buffer DMA maps. 631 */ 632 for (i = 0; i < ATW_NRXDESC; i++) { 633 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 634 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 635 printf("%s: unable to create rx DMA map %d, " 636 "error = %d\n", sc->sc_dev.dv_xname, i, error); 637 goto fail_5; 638 } 639 } 640 for (i = 0; i < ATW_NRXDESC; i++) { 641 sc->sc_rxsoft[i].rxs_mbuf = NULL; 642 } 643 644 switch (sc->sc_rev) { 645 case ATW_REVISION_AB: 646 case ATW_REVISION_AF: 647 sc->sc_sramlen = ATW_SRAM_A_SIZE; 648 break; 649 case ATW_REVISION_BA: 650 case ATW_REVISION_CA: 651 sc->sc_sramlen = ATW_SRAM_B_SIZE; 652 break; 653 } 654 655 /* Reset the chip to a known state. */ 656 atw_reset(sc); 657 658 if (atw_read_srom(sc) == -1) 659 return; 660 661 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 662 ATW_SR_RFTYPE_MASK); 663 664 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 665 ATW_SR_BBPTYPE_MASK); 666 667 if (sc->sc_rftype >= __arraycount(type_strings)) { 668 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 669 return; 670 } 671 if (sc->sc_bbptype >= __arraycount(type_strings)) { 672 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 673 return; 674 } 675 676 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 677 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 678 679 /* XXX There exists a Linux driver which seems to use RFType = 0 for 680 * MARVEL. My bug, or theirs? 681 */ 682 683 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 684 685 switch (sc->sc_rftype) { 686 case ATW_RFTYPE_INTERSIL: 687 reg |= ATW_SYNCTL_CS1; 688 break; 689 case ATW_RFTYPE_RFMD: 690 reg |= ATW_SYNCTL_CS0; 691 break; 692 case ATW_RFTYPE_MARVEL: 693 break; 694 } 695 696 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 697 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 698 699 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 700 701 switch (sc->sc_bbptype) { 702 case ATW_BBPTYPE_INTERSIL: 703 reg |= ATW_BBPCTL_TWI; 704 break; 705 case ATW_BBPTYPE_RFMD: 706 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 707 ATW_BBPCTL_CCA_ACTLO; 708 break; 709 case ATW_BBPTYPE_MARVEL: 710 break; 711 case ATW_C_BBPTYPE_RFMD: 712 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 713 sc->sc_dev.dv_xname); 714 break; 715 } 716 717 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 718 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 719 720 /* 721 * From this point forward, the attachment cannot fail. A failure 722 * before this point releases all resources that may have been 723 * allocated. 724 */ 725 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 726 727 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 728 htole16(sc->sc_srom[ATW_SR_MAC00]), 729 htole16(sc->sc_srom[ATW_SR_MAC01]), 730 htole16(sc->sc_srom[ATW_SR_MAC10]))); 731 732 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 733 ATW_SR_MAJOR_MASK); 734 735 if (srom_major < 2) 736 sc->sc_rf3000_options1 = 0; 737 else if (sc->sc_rev == ATW_REVISION_BA) { 738 sc->sc_rf3000_options1 = 739 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 740 ATW_SR_CR28_MASK); 741 } else 742 sc->sc_rf3000_options1 = 0; 743 744 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 745 ATW_SR_CR29_MASK); 746 747 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 748 ATW_SR_CTRY_MASK); 749 750 #define ADD_CHANNEL(_ic, _chan) do { \ 751 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 752 _ic->ic_channels[_chan].ic_freq = \ 753 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 754 } while (0) 755 756 /* Find available channels */ 757 switch (country_code) { 758 case COUNTRY_MMK2: /* 1-14 */ 759 ADD_CHANNEL(ic, 14); 760 /*FALLTHROUGH*/ 761 case COUNTRY_ETSI: /* 1-13 */ 762 for (i = 1; i <= 13; i++) 763 ADD_CHANNEL(ic, i); 764 break; 765 case COUNTRY_FCC: /* 1-11 */ 766 case COUNTRY_IC: /* 1-11 */ 767 for (i = 1; i <= 11; i++) 768 ADD_CHANNEL(ic, i); 769 break; 770 case COUNTRY_MMK: /* 14 */ 771 ADD_CHANNEL(ic, 14); 772 break; 773 case COUNTRY_FRANCE: /* 10-13 */ 774 for (i = 10; i <= 13; i++) 775 ADD_CHANNEL(ic, i); 776 break; 777 default: /* assume channels 10-11 */ 778 case COUNTRY_SPAIN: /* 10-11 */ 779 for (i = 10; i <= 11; i++) 780 ADD_CHANNEL(ic, i); 781 break; 782 } 783 784 /* Read the MAC address. */ 785 reg = ATW_READ(sc, ATW_PAR0); 786 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 787 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 788 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 789 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 790 reg = ATW_READ(sc, ATW_PAR1); 791 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 792 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 793 794 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 795 printf(" could not get mac address, attach failed\n"); 796 return; 797 } 798 799 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 800 801 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 802 ifp->if_softc = sc; 803 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 804 IFF_NOTRAILERS; 805 ifp->if_ioctl = atw_ioctl; 806 ifp->if_start = atw_start; 807 ifp->if_watchdog = atw_watchdog; 808 ifp->if_init = atw_init; 809 ifp->if_stop = atw_stop; 810 IFQ_SET_READY(&ifp->if_snd); 811 812 ic->ic_ifp = ifp; 813 ic->ic_phytype = IEEE80211_T_DS; 814 ic->ic_opmode = IEEE80211_M_STA; 815 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 816 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 817 818 nrate = 0; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 822 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 823 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 824 825 /* 826 * Call MI attach routines. 827 */ 828 829 if_attach(ifp); 830 ieee80211_ifattach(ic); 831 832 sc->sc_newstate = ic->ic_newstate; 833 ic->ic_newstate = atw_newstate; 834 835 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 836 ic->ic_recv_mgmt = atw_recv_mgmt; 837 838 sc->sc_node_free = ic->ic_node_free; 839 ic->ic_node_free = atw_node_free; 840 841 sc->sc_node_alloc = ic->ic_node_alloc; 842 ic->ic_node_alloc = atw_node_alloc; 843 844 ic->ic_crypto.cs_key_delete = atw_key_delete; 845 ic->ic_crypto.cs_key_set = atw_key_set; 846 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 847 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 848 849 /* possibly we should fill in our own sc_send_prresp, since 850 * the ADM8211 is probably sending probe responses in ad hoc 851 * mode. 852 */ 853 854 /* complete initialization */ 855 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 856 callout_init(&sc->sc_scan_ch); 857 858 #if NBPFILTER > 0 859 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 860 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 861 #endif 862 863 /* 864 * Make sure the interface is shutdown during reboot. 865 */ 866 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 867 if (sc->sc_sdhook == NULL) 868 printf("%s: WARNING: unable to establish shutdown hook\n", 869 sc->sc_dev.dv_xname); 870 871 /* 872 * Add a suspend hook to make sure we come back up after a 873 * resume. 874 */ 875 sc->sc_powerhook = powerhook_establish(atw_power, sc); 876 if (sc->sc_powerhook == NULL) 877 printf("%s: WARNING: unable to establish power hook\n", 878 sc->sc_dev.dv_xname); 879 880 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 881 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 882 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 883 884 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 885 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 886 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 887 888 ieee80211_announce(ic); 889 return; 890 891 /* 892 * Free any resources we've allocated during the failed attach 893 * attempt. Do this in reverse order and fall through. 894 */ 895 fail_5: 896 for (i = 0; i < ATW_NRXDESC; i++) { 897 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 898 continue; 899 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 900 } 901 fail_4: 902 for (i = 0; i < ATW_TXQUEUELEN; i++) { 903 if (sc->sc_txsoft[i].txs_dmamap == NULL) 904 continue; 905 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 906 } 907 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 908 fail_3: 909 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 910 fail_2: 911 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 912 sizeof(struct atw_control_data)); 913 fail_1: 914 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 915 fail_0: 916 return; 917 } 918 919 static struct ieee80211_node * 920 atw_node_alloc(struct ieee80211_node_table *nt) 921 { 922 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 923 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 924 925 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 926 return ni; 927 } 928 929 static void 930 atw_node_free(struct ieee80211_node *ni) 931 { 932 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 933 934 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 935 ether_sprintf(ni->ni_bssid))); 936 (*sc->sc_node_free)(ni); 937 } 938 939 940 static void 941 atw_test1_reset(struct atw_softc *sc) 942 { 943 switch (sc->sc_rev) { 944 case ATW_REVISION_BA: 945 if (1 /* XXX condition on transceiver type */) { 946 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 947 } 948 break; 949 case ATW_REVISION_CA: 950 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 951 break; 952 default: 953 break; 954 } 955 } 956 957 /* 958 * atw_reset: 959 * 960 * Perform a soft reset on the ADM8211. 961 */ 962 void 963 atw_reset(struct atw_softc *sc) 964 { 965 int i; 966 uint32_t lpc; 967 968 ATW_WRITE(sc, ATW_NAR, 0x0); 969 DELAY(atw_nar_delay); 970 971 /* Reference driver has a cryptic remark indicating that this might 972 * power-on the chip. I know that it turns off power-saving.... 973 */ 974 ATW_WRITE(sc, ATW_FRCTL, 0x0); 975 976 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 977 978 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 979 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 980 break; 981 DELAY(atw_pseudo_milli); 982 } 983 984 /* ... and then pause 100ms longer for good measure. */ 985 DELAY(atw_magic_delay1); 986 987 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 988 989 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 990 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 991 992 /* 993 * Initialize the PCI Access Register. 994 */ 995 sc->sc_busmode = ATW_PAR_PBL_8DW; 996 997 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 998 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 999 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1000 1001 atw_test1_reset(sc); 1002 1003 /* Turn off maximum power saving, etc. */ 1004 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1005 1006 DELAY(atw_magic_delay2); 1007 1008 /* Recall EEPROM. */ 1009 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1010 1011 DELAY(atw_magic_delay4); 1012 1013 lpc = ATW_READ(sc, ATW_LPC); 1014 1015 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1016 1017 /* A reset seems to affect the SRAM contents, so put them into 1018 * a known state. 1019 */ 1020 atw_clear_sram(sc); 1021 1022 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1023 } 1024 1025 static void 1026 atw_clear_sram(struct atw_softc *sc) 1027 { 1028 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1029 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1030 /* XXX not for revision 0x20. */ 1031 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1032 } 1033 1034 /* TBD atw_init 1035 * 1036 * set MAC based on ic->ic_bss->myaddr 1037 * write WEP keys 1038 * set TX rate 1039 */ 1040 1041 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1042 * without receiving a beacon with the preferred BSSID & SSID. 1043 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1044 */ 1045 static void 1046 atw_wcsr_init(struct atw_softc *sc) 1047 { 1048 uint32_t wcsr; 1049 1050 wcsr = ATW_READ(sc, ATW_WCSR); 1051 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1052 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1053 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1054 1055 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1056 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1057 } 1058 1059 /* Turn off power management. Set Rx store-and-forward mode. */ 1060 static void 1061 atw_cmdr_init(struct atw_softc *sc) 1062 { 1063 uint32_t cmdr; 1064 cmdr = ATW_READ(sc, ATW_CMDR); 1065 cmdr &= ~ATW_CMDR_APM; 1066 cmdr |= ATW_CMDR_RTE; 1067 cmdr &= ~ATW_CMDR_DRT_MASK; 1068 cmdr |= ATW_CMDR_DRT_SF; 1069 1070 ATW_WRITE(sc, ATW_CMDR, cmdr); 1071 } 1072 1073 static void 1074 atw_tofs2_init(struct atw_softc *sc) 1075 { 1076 uint32_t tofs2; 1077 /* XXX this magic can probably be figured out from the RFMD docs */ 1078 #ifndef ATW_REFSLAVE 1079 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1080 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1081 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1082 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1083 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1084 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1085 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1086 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1087 #else 1088 /* XXX new magic from reference driver source */ 1089 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1090 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1091 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1092 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1093 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1094 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1095 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1096 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1097 #endif 1098 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1099 } 1100 1101 static void 1102 atw_nar_init(struct atw_softc *sc) 1103 { 1104 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1105 } 1106 1107 static void 1108 atw_txlmt_init(struct atw_softc *sc) 1109 { 1110 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1111 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1112 } 1113 1114 static void 1115 atw_test1_init(struct atw_softc *sc) 1116 { 1117 uint32_t test1; 1118 1119 test1 = ATW_READ(sc, ATW_TEST1); 1120 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1121 /* XXX magic 0x1 */ 1122 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1123 ATW_WRITE(sc, ATW_TEST1, test1); 1124 } 1125 1126 static void 1127 atw_rf_reset(struct atw_softc *sc) 1128 { 1129 /* XXX this resets an Intersil RF front-end? */ 1130 /* TBD condition on Intersil RFType? */ 1131 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1132 DELAY(atw_rf_delay1); 1133 ATW_WRITE(sc, ATW_SYNRF, 0); 1134 DELAY(atw_rf_delay2); 1135 } 1136 1137 /* Set 16 TU max duration for the contention-free period (CFP). */ 1138 static void 1139 atw_cfp_init(struct atw_softc *sc) 1140 { 1141 uint32_t cfpp; 1142 1143 cfpp = ATW_READ(sc, ATW_CFPP); 1144 cfpp &= ~ATW_CFPP_CFPMD; 1145 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1146 ATW_WRITE(sc, ATW_CFPP, cfpp); 1147 } 1148 1149 static void 1150 atw_tofs0_init(struct atw_softc *sc) 1151 { 1152 /* XXX I guess that the Cardbus clock is 22 MHz? 1153 * I am assuming that the role of ATW_TOFS0_USCNT is 1154 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1155 * very clear on this point. It says in the datasheet that it is 1156 * possible for the ADM8211 to accomodate bus speeds between 22 MHz 1157 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1158 * these values. These values are also the power-on default. 1159 */ 1160 ATW_WRITE(sc, ATW_TOFS0, 1161 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1162 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1163 } 1164 1165 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1166 static void 1167 atw_ifs_init(struct atw_softc *sc) 1168 { 1169 uint32_t ifst; 1170 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1171 * Go figure. 1172 */ 1173 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1174 __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1175 ATW_IFST_SIFS_MASK) | 1176 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1177 __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1178 1179 ATW_WRITE(sc, ATW_IFST, ifst); 1180 } 1181 1182 static void 1183 atw_response_times_init(struct atw_softc *sc) 1184 { 1185 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1186 * indicate that the MAC expects at least SIFS + MIRT microseconds 1187 * to pass after it transmits a frame that requires a response; 1188 * it waits at most SIFS + MART microseconds for the response. 1189 * Surely this is not the ACK timeout? 1190 */ 1191 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1192 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1193 } 1194 1195 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1196 * engines read and write baseband registers after Rx and before 1197 * Tx, respectively. 1198 */ 1199 static void 1200 atw_bbp_io_init(struct atw_softc *sc) 1201 { 1202 uint32_t mmiraddr2; 1203 1204 /* XXX The reference driver does this, but is it *really* 1205 * necessary? 1206 */ 1207 switch (sc->sc_rev) { 1208 case ATW_REVISION_AB: 1209 case ATW_REVISION_AF: 1210 mmiraddr2 = 0x0; 1211 break; 1212 default: 1213 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1214 mmiraddr2 &= 1215 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1216 break; 1217 } 1218 1219 switch (sc->sc_bbptype) { 1220 case ATW_BBPTYPE_INTERSIL: 1221 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1222 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1223 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1224 break; 1225 case ATW_BBPTYPE_MARVEL: 1226 /* TBD find out the Marvel settings. */ 1227 break; 1228 case ATW_BBPTYPE_RFMD: 1229 default: 1230 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1231 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1232 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1233 break; 1234 } 1235 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1236 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1237 } 1238 1239 /* 1240 * atw_init: [ ifnet interface function ] 1241 * 1242 * Initialize the interface. Must be called at splnet(). 1243 */ 1244 int 1245 atw_init(struct ifnet *ifp) 1246 { 1247 struct atw_softc *sc = ifp->if_softc; 1248 struct ieee80211com *ic = &sc->sc_ic; 1249 struct atw_txsoft *txs; 1250 struct atw_rxsoft *rxs; 1251 int i, error = 0; 1252 1253 if ((error = atw_enable(sc)) != 0) 1254 goto out; 1255 1256 /* 1257 * Cancel any pending I/O. This also resets. 1258 */ 1259 atw_stop(ifp, 0); 1260 1261 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1262 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1263 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1264 1265 atw_wcsr_init(sc); 1266 1267 atw_cmdr_init(sc); 1268 1269 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1270 * 1271 * XXX Set transmit power for ATIM, RTS, Beacon. 1272 */ 1273 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1274 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1275 1276 atw_tofs2_init(sc); 1277 1278 atw_nar_init(sc); 1279 1280 atw_txlmt_init(sc); 1281 1282 atw_test1_init(sc); 1283 1284 atw_rf_reset(sc); 1285 1286 atw_cfp_init(sc); 1287 1288 atw_tofs0_init(sc); 1289 1290 atw_ifs_init(sc); 1291 1292 /* XXX Fall asleep after one second of inactivity. 1293 * XXX A frame may only dribble in for 65536us. 1294 */ 1295 ATW_WRITE(sc, ATW_RMD, 1296 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1297 1298 atw_response_times_init(sc); 1299 1300 atw_bbp_io_init(sc); 1301 1302 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1303 1304 if ((error = atw_rf3000_init(sc)) != 0) 1305 goto out; 1306 1307 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1308 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1309 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1310 1311 /* 1312 * Initialize the transmit descriptor ring. 1313 */ 1314 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1315 for (i = 0; i < ATW_NTXDESC; i++) { 1316 sc->sc_txdescs[i].at_ctl = 0; 1317 /* no transmit chaining */ 1318 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1319 sc->sc_txdescs[i].at_buf2 = 1320 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1321 } 1322 /* use ring mode */ 1323 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1324 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1325 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1326 sc->sc_txfree = ATW_NTXDESC; 1327 sc->sc_txnext = 0; 1328 1329 /* 1330 * Initialize the transmit job descriptors. 1331 */ 1332 SIMPLEQ_INIT(&sc->sc_txfreeq); 1333 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1334 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1335 txs = &sc->sc_txsoft[i]; 1336 txs->txs_mbuf = NULL; 1337 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1338 } 1339 1340 /* 1341 * Initialize the receive descriptor and receive job 1342 * descriptor rings. 1343 */ 1344 for (i = 0; i < ATW_NRXDESC; i++) { 1345 rxs = &sc->sc_rxsoft[i]; 1346 if (rxs->rxs_mbuf == NULL) { 1347 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1348 printf("%s: unable to allocate or map rx " 1349 "buffer %d, error = %d\n", 1350 sc->sc_dev.dv_xname, i, error); 1351 /* 1352 * XXX Should attempt to run with fewer receive 1353 * XXX buffers instead of just failing. 1354 */ 1355 atw_rxdrain(sc); 1356 goto out; 1357 } 1358 } else 1359 ATW_INIT_RXDESC(sc, i); 1360 } 1361 sc->sc_rxptr = 0; 1362 1363 /* 1364 * Initialize the interrupt mask and enable interrupts. 1365 */ 1366 /* normal interrupts */ 1367 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1368 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1369 1370 /* abnormal interrupts */ 1371 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1372 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1373 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1374 1375 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1376 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1377 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1378 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1379 ATW_INTR_TRT; 1380 1381 sc->sc_linkint_mask &= sc->sc_inten; 1382 sc->sc_rxint_mask &= sc->sc_inten; 1383 sc->sc_txint_mask &= sc->sc_inten; 1384 1385 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1386 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1387 1388 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1389 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1390 1391 /* 1392 * Give the transmit and receive rings to the ADM8211. 1393 */ 1394 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1395 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1396 1397 sc->sc_txthresh = 0; 1398 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1399 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1400 1401 /* common 802.11 configuration */ 1402 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1403 switch (ic->ic_opmode) { 1404 case IEEE80211_M_STA: 1405 break; 1406 case IEEE80211_M_AHDEMO: /* XXX */ 1407 case IEEE80211_M_IBSS: 1408 ic->ic_flags |= IEEE80211_F_IBSSON; 1409 /*FALLTHROUGH*/ 1410 case IEEE80211_M_HOSTAP: /* XXX */ 1411 break; 1412 case IEEE80211_M_MONITOR: /* XXX */ 1413 break; 1414 } 1415 1416 switch (ic->ic_opmode) { 1417 case IEEE80211_M_AHDEMO: 1418 case IEEE80211_M_HOSTAP: 1419 #ifndef IEEE80211_NO_HOSTAP 1420 ic->ic_bss->ni_intval = ic->ic_lintval; 1421 ic->ic_bss->ni_rssi = 0; 1422 ic->ic_bss->ni_rstamp = 0; 1423 #endif /* !IEEE80211_NO_HOSTAP */ 1424 break; 1425 default: /* XXX */ 1426 break; 1427 } 1428 1429 sc->sc_wepctl = 0; 1430 1431 atw_write_ssid(sc); 1432 atw_write_sup_rates(sc); 1433 atw_write_wep(sc); 1434 1435 ic->ic_state = IEEE80211_S_INIT; 1436 1437 /* 1438 * Set the receive filter. This will start the transmit and 1439 * receive processes. 1440 */ 1441 atw_filter_setup(sc); 1442 1443 /* 1444 * Start the receive process. 1445 */ 1446 ATW_WRITE(sc, ATW_RDR, 0x1); 1447 1448 /* 1449 * Note that the interface is now running. 1450 */ 1451 ifp->if_flags |= IFF_RUNNING; 1452 ifp->if_flags &= ~IFF_OACTIVE; 1453 1454 /* send no beacons, yet. */ 1455 atw_start_beacon(sc, 0); 1456 1457 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1458 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1459 else 1460 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1461 out: 1462 if (error) { 1463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1464 sc->sc_tx_timer = 0; 1465 ifp->if_timer = 0; 1466 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1467 } 1468 #ifdef ATW_DEBUG 1469 atw_print_regs(sc, "end of init"); 1470 #endif /* ATW_DEBUG */ 1471 1472 return (error); 1473 } 1474 1475 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1476 * 0: MAC control of RF3000/Si4126. 1477 * 1478 * Applies power, or selects RF front-end? Sets reset condition. 1479 * 1480 * TBD support non-RFMD BBP, non-SiLabs synth. 1481 */ 1482 static void 1483 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1484 { 1485 if (enable) { 1486 ATW_WRITE(sc, ATW_SYNRF, 1487 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1488 DELAY(atw_bbp_io_enable_delay); 1489 } else { 1490 ATW_WRITE(sc, ATW_SYNRF, 0); 1491 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1492 } 1493 } 1494 1495 static int 1496 atw_tune(struct atw_softc *sc) 1497 { 1498 int rc; 1499 u_int chan; 1500 struct ieee80211com *ic = &sc->sc_ic; 1501 1502 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1503 if (chan == IEEE80211_CHAN_ANY) 1504 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1505 1506 if (chan == sc->sc_cur_chan) 1507 return 0; 1508 1509 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1510 sc->sc_cur_chan, chan)); 1511 1512 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1513 1514 atw_si4126_tune(sc, chan); 1515 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1516 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1517 chan); 1518 1519 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1520 DELAY(atw_nar_delay); 1521 ATW_WRITE(sc, ATW_RDR, 0x1); 1522 1523 if (rc == 0) 1524 sc->sc_cur_chan = chan; 1525 1526 return rc; 1527 } 1528 1529 #ifdef ATW_SYNDEBUG 1530 static void 1531 atw_si4126_print(struct atw_softc *sc) 1532 { 1533 struct ifnet *ifp = &sc->sc_if; 1534 u_int addr, val; 1535 1536 val = 0; 1537 1538 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1539 return; 1540 1541 for (addr = 0; addr <= 8; addr++) { 1542 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1543 if (atw_si4126_read(sc, addr, &val) == 0) { 1544 printf("<unknown> (quitting print-out)\n"); 1545 break; 1546 } 1547 printf("%05x\n", val); 1548 } 1549 } 1550 #endif /* ATW_SYNDEBUG */ 1551 1552 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1553 * 1554 * The RF/IF synthesizer produces two reference frequencies for 1555 * the RF2948B transceiver. The first frequency the RF2948B requires 1556 * is two times the so-called "intermediate frequency" (IF). Since 1557 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1558 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1559 * frequency required by the transceiver is the radio frequency 1560 * (RF). This is a superheterodyne transceiver; for f(chan) the 1561 * center frequency of the channel we are tuning, RF = f(chan) - 1562 * IF. 1563 * 1564 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1565 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1566 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1567 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1568 */ 1569 static void 1570 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1571 { 1572 u_int mhz; 1573 u_int R; 1574 u_int32_t gpio; 1575 u_int16_t gain; 1576 1577 #ifdef ATW_SYNDEBUG 1578 atw_si4126_print(sc); 1579 #endif /* ATW_SYNDEBUG */ 1580 1581 if (chan == 14) 1582 mhz = 2484; 1583 else 1584 mhz = 2412 + 5 * (chan - 1); 1585 1586 /* Tune IF to 748 MHz to suit the IF LO input of the 1587 * RF2494B, which is 2 x IF. No need to set an IF divider 1588 * because an IF in 526 MHz - 952 MHz is allowed. 1589 * 1590 * XIN is 44.000 MHz, so divide it by two to get allowable 1591 * range of 2-25 MHz. SiLabs tells me that this is not 1592 * strictly necessary. 1593 */ 1594 1595 if (atw_xindiv2) 1596 R = 44; 1597 else 1598 R = 88; 1599 1600 /* Power-up RF, IF synthesizers. */ 1601 atw_si4126_write(sc, SI4126_POWER, 1602 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1603 1604 /* set LPWR, too? */ 1605 atw_si4126_write(sc, SI4126_MAIN, 1606 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1607 1608 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1609 * set KP2 to 1. 1610 * 1611 * REFDIF This is different from the reference driver, which 1612 * always sets SI4126_GAIN to 0. 1613 */ 1614 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1615 1616 atw_si4126_write(sc, SI4126_GAIN, gain); 1617 1618 /* XIN = 44 MHz. 1619 * 1620 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1621 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1622 * 1623 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1624 * so that 1496/88 * 44 MHz = 748 MHz. 1625 */ 1626 atw_si4126_write(sc, SI4126_IFN, 1496); 1627 1628 atw_si4126_write(sc, SI4126_IFR, R); 1629 1630 #ifndef ATW_REFSLAVE 1631 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1632 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1633 * which has no RF1! 1634 */ 1635 atw_si4126_write(sc, SI4126_RF1R, R); 1636 1637 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1638 #endif 1639 1640 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1641 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1642 * Now let's multiply it to mhz. So mhz - IF = N. 1643 */ 1644 atw_si4126_write(sc, SI4126_RF2R, R); 1645 1646 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1647 1648 /* wait 100us from power-up for RF, IF to settle */ 1649 DELAY(100); 1650 1651 gpio = ATW_READ(sc, ATW_GPIO); 1652 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1653 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1654 1655 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1656 /* Set a Prism RF front-end to a special mode for channel 14? 1657 * 1658 * Apparently the SMC2635W needs this, although I don't think 1659 * it has a Prism RF. 1660 */ 1661 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1662 } 1663 ATW_WRITE(sc, ATW_GPIO, gpio); 1664 1665 #ifdef ATW_SYNDEBUG 1666 atw_si4126_print(sc); 1667 #endif /* ATW_SYNDEBUG */ 1668 } 1669 1670 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1671 * diversity. 1672 * 1673 * !!! 1674 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1675 * !!! 1676 */ 1677 static int 1678 atw_rf3000_init(struct atw_softc *sc) 1679 { 1680 int rc = 0; 1681 1682 atw_bbp_io_enable(sc, 1); 1683 1684 /* CCA is acquisition sensitive */ 1685 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1686 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1687 1688 if (rc != 0) 1689 goto out; 1690 1691 /* enable diversity */ 1692 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 /* sensible setting from a binary-only driver */ 1698 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1699 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1700 1701 if (rc != 0) 1702 goto out; 1703 1704 /* magic from a binary-only driver */ 1705 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1706 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1707 1708 if (rc != 0) 1709 goto out; 1710 1711 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1712 1713 if (rc != 0) 1714 goto out; 1715 1716 /* XXX Reference driver remarks that Abocom sets this to 50. 1717 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1718 * in the "reserved" area of register RF3000_OPTIONS1. 1719 */ 1720 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1721 1722 if (rc != 0) 1723 goto out; 1724 1725 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1726 1727 if (rc != 0) 1728 goto out; 1729 1730 out: 1731 atw_bbp_io_enable(sc, 0); 1732 return rc; 1733 } 1734 1735 #ifdef ATW_BBPDEBUG 1736 static void 1737 atw_rf3000_print(struct atw_softc *sc) 1738 { 1739 struct ifnet *ifp = &sc->sc_if; 1740 u_int addr, val; 1741 1742 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1743 return; 1744 1745 for (addr = 0x01; addr <= 0x15; addr++) { 1746 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1747 if (atw_rf3000_read(sc, addr, &val) != 0) { 1748 printf("<unknown> (quitting print-out)\n"); 1749 break; 1750 } 1751 printf("%08x\n", val); 1752 } 1753 } 1754 #endif /* ATW_BBPDEBUG */ 1755 1756 /* Set the power settings on the BBP for channel `chan'. */ 1757 static int 1758 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1759 { 1760 int rc = 0; 1761 u_int32_t reg; 1762 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1763 1764 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1765 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1766 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1767 1768 /* odd channels: LSB, even channels: MSB */ 1769 if (chan % 2 == 1) { 1770 txpower &= 0xFF; 1771 lpf_cutoff &= 0xFF; 1772 lna_gs_thresh &= 0xFF; 1773 } else { 1774 txpower >>= 8; 1775 lpf_cutoff >>= 8; 1776 lna_gs_thresh >>= 8; 1777 } 1778 1779 #ifdef ATW_BBPDEBUG 1780 atw_rf3000_print(sc); 1781 #endif /* ATW_BBPDEBUG */ 1782 1783 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1784 "lna_gs_thresh %02x\n", 1785 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1786 1787 atw_bbp_io_enable(sc, 1); 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1790 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1791 goto out; 1792 1793 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1794 goto out; 1795 1796 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1797 goto out; 1798 1799 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1800 1801 if (rc != 0) 1802 goto out; 1803 1804 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1805 1806 if (rc != 0) 1807 goto out; 1808 1809 #ifdef ATW_BBPDEBUG 1810 atw_rf3000_print(sc); 1811 #endif /* ATW_BBPDEBUG */ 1812 1813 out: 1814 atw_bbp_io_enable(sc, 0); 1815 1816 /* set beacon, rts, atim transmit power */ 1817 reg = ATW_READ(sc, ATW_PLCPHD); 1818 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1819 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1820 ATW_PLCPHD_SERVICE_MASK); 1821 ATW_WRITE(sc, ATW_PLCPHD, reg); 1822 DELAY(atw_plcphd_delay); 1823 1824 return rc; 1825 } 1826 1827 /* Write a register on the RF3000 baseband processor using the 1828 * registers provided by the ADM8211 for this purpose. 1829 * 1830 * Return 0 on success. 1831 */ 1832 static int 1833 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1834 { 1835 u_int32_t reg; 1836 int i; 1837 1838 reg = sc->sc_bbpctl_wr | 1839 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1840 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1841 1842 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1843 ATW_WRITE(sc, ATW_BBPCTL, reg); 1844 DELAY(2 * atw_pseudo_milli); 1845 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1846 break; 1847 } 1848 1849 if (i < 0) { 1850 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1851 return ETIMEDOUT; 1852 } 1853 return 0; 1854 } 1855 1856 /* Read a register on the RF3000 baseband processor using the registers 1857 * the ADM8211 provides for this purpose. 1858 * 1859 * The 7-bit register address is addr. Record the 8-bit data in the register 1860 * in *val. 1861 * 1862 * Return 0 on success. 1863 * 1864 * XXX This does not seem to work. The ADM8211 must require more or 1865 * different magic to read the chip than to write it. Possibly some 1866 * of the magic I have derived from a binary-only driver concerns 1867 * the "chip address" (see the RF3000 manual). 1868 */ 1869 #ifdef ATW_BBPDEBUG 1870 static int 1871 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1872 { 1873 u_int32_t reg; 1874 int i; 1875 1876 for (i = 1000; --i >= 0; ) { 1877 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1878 break; 1879 DELAY(100); 1880 } 1881 1882 if (i < 0) { 1883 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1884 sc->sc_dev.dv_xname); 1885 return ETIMEDOUT; 1886 } 1887 1888 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1889 1890 ATW_WRITE(sc, ATW_BBPCTL, reg); 1891 1892 for (i = 1000; --i >= 0; ) { 1893 DELAY(100); 1894 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1895 break; 1896 } 1897 1898 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1899 1900 if (i < 0) { 1901 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1902 sc->sc_dev.dv_xname, reg); 1903 return ETIMEDOUT; 1904 } 1905 if (val != NULL) 1906 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1907 return 0; 1908 } 1909 #endif /* ATW_BBPDEBUG */ 1910 1911 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1912 * provided by the ADM8211 for that purpose. 1913 * 1914 * val is 18 bits of data, and val is the 4-bit address of the register. 1915 * 1916 * Return 0 on success. 1917 */ 1918 static void 1919 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1920 { 1921 uint32_t bits, mask, reg; 1922 const int nbits = 22; 1923 1924 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1925 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1926 1927 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1928 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1929 1930 reg = ATW_SYNRF_SELSYN; 1931 /* reference driver: reset Si4126 serial bus to initial 1932 * conditions? 1933 */ 1934 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1935 ATW_WRITE(sc, ATW_SYNRF, reg); 1936 1937 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1938 if ((bits & mask) != 0) 1939 reg |= ATW_SYNRF_SYNDATA; 1940 else 1941 reg &= ~ATW_SYNRF_SYNDATA; 1942 ATW_WRITE(sc, ATW_SYNRF, reg); 1943 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1944 ATW_WRITE(sc, ATW_SYNRF, reg); 1945 } 1946 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1947 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1948 } 1949 1950 /* Read 18-bit data from the 4-bit address addr in Si4126 1951 * RF synthesizer and write the data to *val. Return 0 on success. 1952 * 1953 * XXX This does not seem to work. The ADM8211 must require more or 1954 * different magic to read the chip than to write it. 1955 */ 1956 #ifdef ATW_SYNDEBUG 1957 static int 1958 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1959 { 1960 u_int32_t reg; 1961 int i; 1962 1963 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1964 1965 for (i = 1000; --i >= 0; ) { 1966 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1967 break; 1968 DELAY(100); 1969 } 1970 1971 if (i < 0) { 1972 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1973 sc->sc_dev.dv_xname); 1974 return ETIMEDOUT; 1975 } 1976 1977 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1978 1979 ATW_WRITE(sc, ATW_SYNCTL, reg); 1980 1981 for (i = 1000; --i >= 0; ) { 1982 DELAY(100); 1983 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1984 break; 1985 } 1986 1987 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1988 1989 if (i < 0) { 1990 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1991 sc->sc_dev.dv_xname, reg); 1992 return ETIMEDOUT; 1993 } 1994 if (val != NULL) 1995 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1996 ATW_SYNCTL_DATA_MASK); 1997 return 0; 1998 } 1999 #endif /* ATW_SYNDEBUG */ 2000 2001 /* XXX is the endianness correct? test. */ 2002 #define atw_calchash(addr) \ 2003 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 2004 2005 /* 2006 * atw_filter_setup: 2007 * 2008 * Set the ADM8211's receive filter. 2009 */ 2010 static void 2011 atw_filter_setup(struct atw_softc *sc) 2012 { 2013 struct ieee80211com *ic = &sc->sc_ic; 2014 struct ethercom *ec = &sc->sc_ec; 2015 struct ifnet *ifp = &sc->sc_if; 2016 int hash; 2017 u_int32_t hashes[2]; 2018 struct ether_multi *enm; 2019 struct ether_multistep step; 2020 2021 /* According to comments in tlp_al981_filter_setup 2022 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2023 * multicast filter to be set while it is running. Hopefully 2024 * the ADM8211 is not the same! 2025 */ 2026 if ((ifp->if_flags & IFF_RUNNING) != 0) 2027 atw_idle(sc, ATW_NAR_SR); 2028 2029 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2030 ifp->if_flags &= ~IFF_ALLMULTI; 2031 2032 /* XXX in scan mode, do not filter packets. Maybe this is 2033 * unnecessary. 2034 */ 2035 if (ic->ic_state == IEEE80211_S_SCAN || 2036 (ifp->if_flags & IFF_PROMISC) != 0) { 2037 sc->sc_opmode |= ATW_NAR_PR; 2038 goto allmulti; 2039 } 2040 2041 hashes[0] = hashes[1] = 0x0; 2042 2043 /* 2044 * Program the 64-bit multicast hash filter. 2045 */ 2046 ETHER_FIRST_MULTI(step, ec, enm); 2047 while (enm != NULL) { 2048 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2049 ETHER_ADDR_LEN) != 0) 2050 goto allmulti; 2051 2052 hash = atw_calchash(enm->enm_addrlo); 2053 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2054 ETHER_NEXT_MULTI(step, enm); 2055 sc->sc_opmode |= ATW_NAR_MM; 2056 } 2057 ifp->if_flags &= ~IFF_ALLMULTI; 2058 goto setit; 2059 2060 allmulti: 2061 sc->sc_opmode |= ATW_NAR_MM; 2062 ifp->if_flags |= IFF_ALLMULTI; 2063 hashes[0] = hashes[1] = 0xffffffff; 2064 2065 setit: 2066 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2067 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2068 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2069 DELAY(atw_nar_delay); 2070 ATW_WRITE(sc, ATW_RDR, 0x1); 2071 2072 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2073 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2074 } 2075 2076 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2077 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2078 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2079 * no beacon with the preferred BSSID and SSID in the number of 2080 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2081 */ 2082 static void 2083 atw_write_bssid(struct atw_softc *sc) 2084 { 2085 struct ieee80211com *ic = &sc->sc_ic; 2086 u_int8_t *bssid; 2087 2088 bssid = ic->ic_bss->ni_bssid; 2089 2090 ATW_WRITE(sc, ATW_BSSID0, 2091 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2092 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2093 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2094 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2095 2096 ATW_WRITE(sc, ATW_ABDA1, 2097 (ATW_READ(sc, ATW_ABDA1) & 2098 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2099 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2100 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2101 2102 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2103 ether_sprintf(sc->sc_bssid))); 2104 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2105 2106 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2107 } 2108 2109 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2110 * 16-bit word. 2111 */ 2112 static void 2113 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2114 { 2115 u_int i; 2116 u_int8_t *ptr; 2117 2118 memcpy(&sc->sc_sram[ofs], buf, buflen); 2119 2120 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2121 2122 KASSERT(buflen + ofs <= sc->sc_sramlen); 2123 2124 ptr = &sc->sc_sram[ofs]; 2125 2126 for (i = 0; i < buflen; i += 2) { 2127 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2128 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2129 DELAY(atw_writewep_delay); 2130 2131 ATW_WRITE(sc, ATW_WESK, 2132 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2133 DELAY(atw_writewep_delay); 2134 } 2135 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2136 2137 if (sc->sc_if.if_flags & IFF_DEBUG) { 2138 int n_octets = 0; 2139 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2140 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2141 for (i = 0; i < buflen; i++) { 2142 printf(" %02x", ptr[i]); 2143 if (++n_octets % 24 == 0) 2144 printf("\n"); 2145 } 2146 if (n_octets % 24 != 0) 2147 printf("\n"); 2148 } 2149 } 2150 2151 static int 2152 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2153 { 2154 struct atw_softc *sc = ic->ic_ifp->if_softc; 2155 u_int keyix = k->wk_keyix; 2156 2157 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2158 2159 if (keyix >= IEEE80211_WEP_NKID) 2160 return 0; 2161 if (k->wk_keylen != 0) 2162 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2163 2164 return 1; 2165 } 2166 2167 static int 2168 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2169 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2170 { 2171 struct atw_softc *sc = ic->ic_ifp->if_softc; 2172 2173 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2174 2175 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2176 return 0; 2177 2178 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2179 2180 return 1; 2181 } 2182 2183 static void 2184 atw_key_update_begin(struct ieee80211com *ic) 2185 { 2186 #ifdef ATW_DEBUG 2187 struct ifnet *ifp = ic->ic_ifp; 2188 struct atw_softc *sc = ifp->if_softc; 2189 #endif 2190 2191 DPRINTF(sc, ("%s:\n", __func__)); 2192 } 2193 2194 static void 2195 atw_key_update_end(struct ieee80211com *ic) 2196 { 2197 struct ifnet *ifp = ic->ic_ifp; 2198 struct atw_softc *sc = ifp->if_softc; 2199 2200 DPRINTF(sc, ("%s:\n", __func__)); 2201 2202 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2203 return; 2204 if (ATW_IS_ENABLED(sc) == 0) 2205 return; 2206 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2207 atw_write_wep(sc); 2208 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2209 DELAY(atw_nar_delay); 2210 ATW_WRITE(sc, ATW_RDR, 0x1); 2211 } 2212 2213 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2214 static void 2215 atw_write_wep(struct atw_softc *sc) 2216 { 2217 #if 0 2218 struct ieee80211com *ic = &sc->sc_ic; 2219 u_int32_t reg; 2220 int i; 2221 #endif 2222 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2223 u_int8_t buf[IEEE80211_WEP_NKID] 2224 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2225 2226 sc->sc_wepctl = 0; 2227 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2228 2229 memset(&buf[0][0], 0, sizeof(buf)); 2230 2231 #if 0 2232 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2233 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2234 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2235 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2236 buf[i][1] = ATW_WEP_ENABLED; 2237 } else { 2238 buf[i][1] = 0; 2239 continue; 2240 } 2241 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2242 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2243 ic->ic_nw_keys[i].wk_keylen - 1); 2244 } 2245 2246 reg = ATW_READ(sc, ATW_MACTEST); 2247 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2248 reg &= ~ATW_MACTEST_KEYID_MASK; 2249 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2250 ATW_WRITE(sc, ATW_MACTEST, reg); 2251 2252 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2253 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2254 2255 switch (sc->sc_rev) { 2256 case ATW_REVISION_AB: 2257 case ATW_REVISION_AF: 2258 /* Bypass WEP on Rx. */ 2259 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2260 break; 2261 default: 2262 break; 2263 } 2264 #endif 2265 2266 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2267 sizeof(buf)); 2268 2269 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2270 } 2271 2272 static void 2273 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2274 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2275 { 2276 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2277 2278 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2279 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2280 return; 2281 2282 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2283 2284 switch (subtype) { 2285 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2286 case IEEE80211_FC0_SUBTYPE_BEACON: 2287 if (ic->ic_opmode == IEEE80211_M_IBSS && 2288 ic->ic_state == IEEE80211_S_RUN) { 2289 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2290 (void)ieee80211_ibss_merge(ni); 2291 } 2292 break; 2293 default: 2294 break; 2295 } 2296 return; 2297 } 2298 2299 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2300 * In ad hoc mode, the SSID is written to the beacons sent by the 2301 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2302 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2303 * indications. 2304 */ 2305 static void 2306 atw_write_ssid(struct atw_softc *sc) 2307 { 2308 struct ieee80211com *ic = &sc->sc_ic; 2309 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2310 * it only expects the element length, not its ID. 2311 */ 2312 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2313 2314 memset(buf, 0, sizeof(buf)); 2315 buf[0] = ic->ic_bss->ni_esslen; 2316 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2317 2318 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2319 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2320 } 2321 2322 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2323 * In ad hoc mode, the supported rates are written to beacons sent by the 2324 * ADM8211. 2325 */ 2326 static void 2327 atw_write_sup_rates(struct atw_softc *sc) 2328 { 2329 struct ieee80211com *ic = &sc->sc_ic; 2330 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2331 * supported rates 2332 */ 2333 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2334 2335 memset(buf, 0, sizeof(buf)); 2336 2337 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2338 2339 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2340 ic->ic_bss->ni_rates.rs_nrates); 2341 2342 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2343 } 2344 2345 /* Start/stop sending beacons. */ 2346 void 2347 atw_start_beacon(struct atw_softc *sc, int start) 2348 { 2349 struct ieee80211com *ic = &sc->sc_ic; 2350 uint16_t chan; 2351 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2352 size_t len; 2353 2354 if (ATW_IS_ENABLED(sc) == 0) 2355 return; 2356 2357 /* start beacons */ 2358 len = sizeof(struct ieee80211_frame) + 2359 8 /* timestamp */ + 2 /* beacon interval */ + 2360 2 /* capability info */ + 2361 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2362 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2363 3 /* DS parameters */ + 2364 IEEE80211_CRC_LEN; 2365 2366 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2367 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2368 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2369 2370 ATW_WRITE(sc, ATW_BCNT, bcnt); 2371 ATW_WRITE(sc, ATW_CAP1, cap1); 2372 2373 if (!start) 2374 return; 2375 2376 /* TBD use ni_capinfo */ 2377 2378 capinfo = 0; 2379 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2380 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2381 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2382 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2383 2384 switch (ic->ic_opmode) { 2385 case IEEE80211_M_IBSS: 2386 len += 4; /* IBSS parameters */ 2387 capinfo |= IEEE80211_CAPINFO_IBSS; 2388 break; 2389 case IEEE80211_M_HOSTAP: 2390 /* XXX 6-byte minimum TIM */ 2391 len += atw_beacon_len_adjust; 2392 capinfo |= IEEE80211_CAPINFO_ESS; 2393 break; 2394 default: 2395 return; 2396 } 2397 2398 /* set listen interval 2399 * XXX do software units agree w/ hardware? 2400 */ 2401 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2402 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2403 2404 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2405 2406 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2407 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2408 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2409 2410 ATW_WRITE(sc, ATW_BCNT, bcnt); 2411 ATW_WRITE(sc, ATW_BPLI, bpli); 2412 ATW_WRITE(sc, ATW_CAP0, cap0); 2413 ATW_WRITE(sc, ATW_CAP1, cap1); 2414 2415 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2416 sc->sc_dev.dv_xname, bcnt)); 2417 2418 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2419 sc->sc_dev.dv_xname, cap1)); 2420 } 2421 2422 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2423 static inline uint32_t 2424 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2425 { 2426 /* Following the reference driver's lead, I compute 2427 * 2428 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2429 * 2430 * without using 64-bit arithmetic, using the following 2431 * relationship: 2432 * 2433 * (0x100000000 * H + L) % m 2434 * = ((0x100000000 % m) * H + L) % m 2435 * = (((0xffffffff + 1) % m) * H + L) % m 2436 * = ((0xffffffff % m + 1 % m) * H + L) % m 2437 * = ((0xffffffff % m + 1) * H + L) % m 2438 */ 2439 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2440 } 2441 2442 static uint64_t 2443 atw_get_tsft(struct atw_softc *sc) 2444 { 2445 int i; 2446 uint32_t tsfth, tsftl; 2447 for (i = 0; i < 2; i++) { 2448 tsfth = ATW_READ(sc, ATW_TSFTH); 2449 tsftl = ATW_READ(sc, ATW_TSFTL); 2450 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2451 break; 2452 } 2453 return ((uint64_t)tsfth << 32) | tsftl; 2454 } 2455 2456 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2457 * the ieee80211com. 2458 * 2459 * Predict the next target beacon transmission time (TBTT) and 2460 * write it to the ADM8211. 2461 */ 2462 static void 2463 atw_predict_beacon(struct atw_softc *sc) 2464 { 2465 #define TBTTOFS 20 /* TU */ 2466 2467 struct ieee80211com *ic = &sc->sc_ic; 2468 uint64_t tsft; 2469 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2470 union { 2471 uint64_t word; 2472 uint8_t tstamp[8]; 2473 } u; 2474 2475 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2476 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2477 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2478 tsft = atw_get_tsft(sc); 2479 u.word = htole64(tsft); 2480 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2481 sizeof(ic->ic_bss->ni_tstamp)); 2482 } else 2483 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2484 2485 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2486 2487 tsftl = tsft & 0xFFFFFFFF; 2488 tsfth = tsft >> 32; 2489 2490 /* We sent/received the last beacon `past' microseconds 2491 * after the interval divided the TSF timer. 2492 */ 2493 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2494 2495 /* Skip ten beacons so that the TBTT cannot pass before 2496 * we've programmed it. Ten is an arbitrary number. 2497 */ 2498 tbtt = past_even + ival * 10; 2499 2500 ATW_WRITE(sc, ATW_TOFS1, 2501 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2502 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2503 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2504 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2505 #undef TBTTOFS 2506 } 2507 2508 static void 2509 atw_next_scan(void *arg) 2510 { 2511 struct atw_softc *sc = arg; 2512 struct ieee80211com *ic = &sc->sc_ic; 2513 int s; 2514 2515 /* don't call atw_start w/o network interrupts blocked */ 2516 s = splnet(); 2517 if (ic->ic_state == IEEE80211_S_SCAN) 2518 ieee80211_next_scan(ic); 2519 splx(s); 2520 } 2521 2522 /* Synchronize the hardware state with the software state. */ 2523 static int 2524 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2525 { 2526 struct ifnet *ifp = ic->ic_ifp; 2527 struct atw_softc *sc = ifp->if_softc; 2528 enum ieee80211_state ostate; 2529 int error = 0; 2530 2531 ostate = ic->ic_state; 2532 callout_stop(&sc->sc_scan_ch); 2533 2534 switch (nstate) { 2535 case IEEE80211_S_AUTH: 2536 case IEEE80211_S_ASSOC: 2537 atw_write_bssid(sc); 2538 error = atw_tune(sc); 2539 break; 2540 case IEEE80211_S_INIT: 2541 callout_stop(&sc->sc_scan_ch); 2542 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2543 atw_start_beacon(sc, 0); 2544 break; 2545 case IEEE80211_S_SCAN: 2546 error = atw_tune(sc); 2547 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2548 atw_next_scan, sc); 2549 break; 2550 case IEEE80211_S_RUN: 2551 error = atw_tune(sc); 2552 atw_write_bssid(sc); 2553 atw_write_ssid(sc); 2554 atw_write_sup_rates(sc); 2555 2556 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2557 ic->ic_opmode == IEEE80211_M_MONITOR) 2558 break; 2559 2560 /* set listen interval 2561 * XXX do software units agree w/ hardware? 2562 */ 2563 ATW_WRITE(sc, ATW_BPLI, 2564 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2565 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2566 ATW_BPLI_LI_MASK)); 2567 2568 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2569 ATW_READ(sc, ATW_BPLI))); 2570 2571 atw_predict_beacon(sc); 2572 2573 switch (ic->ic_opmode) { 2574 case IEEE80211_M_AHDEMO: 2575 case IEEE80211_M_HOSTAP: 2576 case IEEE80211_M_IBSS: 2577 atw_start_beacon(sc, 1); 2578 break; 2579 case IEEE80211_M_MONITOR: 2580 case IEEE80211_M_STA: 2581 break; 2582 } 2583 2584 break; 2585 } 2586 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2587 } 2588 2589 /* 2590 * atw_add_rxbuf: 2591 * 2592 * Add a receive buffer to the indicated descriptor. 2593 */ 2594 int 2595 atw_add_rxbuf(struct atw_softc *sc, int idx) 2596 { 2597 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2598 struct mbuf *m; 2599 int error; 2600 2601 MGETHDR(m, M_DONTWAIT, MT_DATA); 2602 if (m == NULL) 2603 return (ENOBUFS); 2604 2605 MCLGET(m, M_DONTWAIT); 2606 if ((m->m_flags & M_EXT) == 0) { 2607 m_freem(m); 2608 return (ENOBUFS); 2609 } 2610 2611 if (rxs->rxs_mbuf != NULL) 2612 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2613 2614 rxs->rxs_mbuf = m; 2615 2616 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2617 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2618 BUS_DMA_READ|BUS_DMA_NOWAIT); 2619 if (error) { 2620 printf("%s: can't load rx DMA map %d, error = %d\n", 2621 sc->sc_dev.dv_xname, idx, error); 2622 panic("atw_add_rxbuf"); /* XXX */ 2623 } 2624 2625 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2626 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2627 2628 ATW_INIT_RXDESC(sc, idx); 2629 2630 return (0); 2631 } 2632 2633 /* 2634 * Release any queued transmit buffers. 2635 */ 2636 void 2637 atw_txdrain(struct atw_softc *sc) 2638 { 2639 struct atw_txsoft *txs; 2640 2641 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2643 if (txs->txs_mbuf != NULL) { 2644 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2645 m_freem(txs->txs_mbuf); 2646 txs->txs_mbuf = NULL; 2647 } 2648 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2649 sc->sc_txfree += txs->txs_ndescs; 2650 } 2651 2652 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2653 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2654 sc->sc_txfree != ATW_NTXDESC)); 2655 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2656 sc->sc_tx_timer = 0; 2657 } 2658 2659 /* 2660 * atw_stop: [ ifnet interface function ] 2661 * 2662 * Stop transmission on the interface. 2663 */ 2664 void 2665 atw_stop(struct ifnet *ifp, int disable) 2666 { 2667 struct atw_softc *sc = ifp->if_softc; 2668 struct ieee80211com *ic = &sc->sc_ic; 2669 2670 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2671 2672 /* Disable interrupts. */ 2673 ATW_WRITE(sc, ATW_IER, 0); 2674 2675 /* Stop the transmit and receive processes. */ 2676 sc->sc_opmode = 0; 2677 ATW_WRITE(sc, ATW_NAR, 0); 2678 DELAY(atw_nar_delay); 2679 ATW_WRITE(sc, ATW_TDBD, 0); 2680 ATW_WRITE(sc, ATW_TDBP, 0); 2681 ATW_WRITE(sc, ATW_RDB, 0); 2682 2683 atw_txdrain(sc); 2684 2685 if (disable) { 2686 atw_rxdrain(sc); 2687 atw_disable(sc); 2688 } 2689 2690 /* 2691 * Mark the interface down and cancel the watchdog timer. 2692 */ 2693 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2694 sc->sc_tx_timer = 0; 2695 ifp->if_timer = 0; 2696 2697 if (!disable) 2698 atw_reset(sc); 2699 } 2700 2701 /* 2702 * atw_rxdrain: 2703 * 2704 * Drain the receive queue. 2705 */ 2706 void 2707 atw_rxdrain(struct atw_softc *sc) 2708 { 2709 struct atw_rxsoft *rxs; 2710 int i; 2711 2712 for (i = 0; i < ATW_NRXDESC; i++) { 2713 rxs = &sc->sc_rxsoft[i]; 2714 if (rxs->rxs_mbuf == NULL) 2715 continue; 2716 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2717 m_freem(rxs->rxs_mbuf); 2718 rxs->rxs_mbuf = NULL; 2719 } 2720 } 2721 2722 /* 2723 * atw_detach: 2724 * 2725 * Detach an ADM8211 interface. 2726 */ 2727 int 2728 atw_detach(struct atw_softc *sc) 2729 { 2730 struct ifnet *ifp = &sc->sc_if; 2731 struct atw_rxsoft *rxs; 2732 struct atw_txsoft *txs; 2733 int i; 2734 2735 /* 2736 * Succeed now if there isn't any work to do. 2737 */ 2738 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2739 return (0); 2740 2741 callout_stop(&sc->sc_scan_ch); 2742 2743 ieee80211_ifdetach(&sc->sc_ic); 2744 if_detach(ifp); 2745 2746 for (i = 0; i < ATW_NRXDESC; i++) { 2747 rxs = &sc->sc_rxsoft[i]; 2748 if (rxs->rxs_mbuf != NULL) { 2749 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2750 m_freem(rxs->rxs_mbuf); 2751 rxs->rxs_mbuf = NULL; 2752 } 2753 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2754 } 2755 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2756 txs = &sc->sc_txsoft[i]; 2757 if (txs->txs_mbuf != NULL) { 2758 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2759 m_freem(txs->txs_mbuf); 2760 txs->txs_mbuf = NULL; 2761 } 2762 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2763 } 2764 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2765 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2766 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2767 sizeof(struct atw_control_data)); 2768 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2769 2770 shutdownhook_disestablish(sc->sc_sdhook); 2771 powerhook_disestablish(sc->sc_powerhook); 2772 2773 if (sc->sc_srom) 2774 free(sc->sc_srom, M_DEVBUF); 2775 2776 return (0); 2777 } 2778 2779 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2780 void 2781 atw_shutdown(void *arg) 2782 { 2783 struct atw_softc *sc = arg; 2784 2785 atw_stop(&sc->sc_if, 1); 2786 } 2787 2788 int 2789 atw_intr(void *arg) 2790 { 2791 struct atw_softc *sc = arg; 2792 struct ifnet *ifp = &sc->sc_if; 2793 u_int32_t status, rxstatus, txstatus, linkstatus; 2794 int handled = 0, txthresh; 2795 2796 #ifdef DEBUG 2797 if (ATW_IS_ENABLED(sc) == 0) 2798 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2799 #endif 2800 2801 /* 2802 * If the interface isn't running, the interrupt couldn't 2803 * possibly have come from us. 2804 */ 2805 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2806 !device_is_active(&sc->sc_dev)) 2807 return (0); 2808 2809 for (;;) { 2810 status = ATW_READ(sc, ATW_STSR); 2811 2812 if (status) 2813 ATW_WRITE(sc, ATW_STSR, status); 2814 2815 #ifdef ATW_DEBUG 2816 #define PRINTINTR(flag) do { \ 2817 if ((status & flag) != 0) { \ 2818 printf("%s" #flag, delim); \ 2819 delim = ","; \ 2820 } \ 2821 } while (0) 2822 2823 if (atw_debug > 1 && status) { 2824 const char *delim = "<"; 2825 2826 printf("%s: reg[STSR] = %x", 2827 sc->sc_dev.dv_xname, status); 2828 2829 PRINTINTR(ATW_INTR_FBE); 2830 PRINTINTR(ATW_INTR_LINKOFF); 2831 PRINTINTR(ATW_INTR_LINKON); 2832 PRINTINTR(ATW_INTR_RCI); 2833 PRINTINTR(ATW_INTR_RDU); 2834 PRINTINTR(ATW_INTR_REIS); 2835 PRINTINTR(ATW_INTR_RPS); 2836 PRINTINTR(ATW_INTR_TCI); 2837 PRINTINTR(ATW_INTR_TDU); 2838 PRINTINTR(ATW_INTR_TLT); 2839 PRINTINTR(ATW_INTR_TPS); 2840 PRINTINTR(ATW_INTR_TRT); 2841 PRINTINTR(ATW_INTR_TUF); 2842 PRINTINTR(ATW_INTR_BCNTC); 2843 PRINTINTR(ATW_INTR_ATIME); 2844 PRINTINTR(ATW_INTR_TBTT); 2845 PRINTINTR(ATW_INTR_TSCZ); 2846 PRINTINTR(ATW_INTR_TSFTF); 2847 printf(">\n"); 2848 } 2849 #undef PRINTINTR 2850 #endif /* ATW_DEBUG */ 2851 2852 if ((status & sc->sc_inten) == 0) 2853 break; 2854 2855 handled = 1; 2856 2857 rxstatus = status & sc->sc_rxint_mask; 2858 txstatus = status & sc->sc_txint_mask; 2859 linkstatus = status & sc->sc_linkint_mask; 2860 2861 if (linkstatus) { 2862 atw_linkintr(sc, linkstatus); 2863 } 2864 2865 if (rxstatus) { 2866 /* Grab any new packets. */ 2867 atw_rxintr(sc); 2868 2869 if (rxstatus & ATW_INTR_RDU) { 2870 printf("%s: receive ring overrun\n", 2871 sc->sc_dev.dv_xname); 2872 /* Get the receive process going again. */ 2873 ATW_WRITE(sc, ATW_RDR, 0x1); 2874 break; 2875 } 2876 } 2877 2878 if (txstatus) { 2879 /* Sweep up transmit descriptors. */ 2880 atw_txintr(sc); 2881 2882 if (txstatus & ATW_INTR_TLT) 2883 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2884 sc->sc_dev.dv_xname)); 2885 2886 if (txstatus & ATW_INTR_TRT) 2887 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2888 sc->sc_dev.dv_xname)); 2889 2890 /* If Tx under-run, increase our transmit threshold 2891 * if another is available. 2892 */ 2893 txthresh = sc->sc_txthresh + 1; 2894 if ((txstatus & ATW_INTR_TUF) && 2895 sc->sc_txth[txthresh].txth_name != NULL) { 2896 /* Idle the transmit process. */ 2897 atw_idle(sc, ATW_NAR_ST); 2898 2899 sc->sc_txthresh = txthresh; 2900 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2901 sc->sc_opmode |= 2902 sc->sc_txth[txthresh].txth_opmode; 2903 printf("%s: transmit underrun; new " 2904 "threshold: %s\n", sc->sc_dev.dv_xname, 2905 sc->sc_txth[txthresh].txth_name); 2906 2907 /* Set the new threshold and restart 2908 * the transmit process. 2909 */ 2910 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2911 DELAY(atw_nar_delay); 2912 ATW_WRITE(sc, ATW_RDR, 0x1); 2913 /* XXX Log every Nth underrun from 2914 * XXX now on? 2915 */ 2916 } 2917 } 2918 2919 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2920 if (status & ATW_INTR_TPS) 2921 printf("%s: transmit process stopped\n", 2922 sc->sc_dev.dv_xname); 2923 if (status & ATW_INTR_RPS) 2924 printf("%s: receive process stopped\n", 2925 sc->sc_dev.dv_xname); 2926 (void)atw_init(ifp); 2927 break; 2928 } 2929 2930 if (status & ATW_INTR_FBE) { 2931 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2932 (void)atw_init(ifp); 2933 break; 2934 } 2935 2936 /* 2937 * Not handled: 2938 * 2939 * Transmit buffer unavailable -- normal 2940 * condition, nothing to do, really. 2941 * 2942 * Early receive interrupt -- not available on 2943 * all chips, we just use RI. We also only 2944 * use single-segment receive DMA, so this 2945 * is mostly useless. 2946 * 2947 * TBD others 2948 */ 2949 } 2950 2951 /* Try to get more packets going. */ 2952 atw_start(ifp); 2953 2954 return (handled); 2955 } 2956 2957 /* 2958 * atw_idle: 2959 * 2960 * Cause the transmit and/or receive processes to go idle. 2961 * 2962 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2963 * process in STSR if I clear SR or ST after the process has already 2964 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2965 * do not seem to be too reliable. Perhaps I have the sense of the 2966 * Rx bits switched with the Tx bits? 2967 */ 2968 void 2969 atw_idle(struct atw_softc *sc, u_int32_t bits) 2970 { 2971 u_int32_t ackmask = 0, opmode, stsr, test0; 2972 int i, s; 2973 2974 s = splnet(); 2975 2976 opmode = sc->sc_opmode & ~bits; 2977 2978 if (bits & ATW_NAR_SR) 2979 ackmask |= ATW_INTR_RPS; 2980 2981 if (bits & ATW_NAR_ST) { 2982 ackmask |= ATW_INTR_TPS; 2983 /* set ATW_NAR_HF to flush TX FIFO. */ 2984 opmode |= ATW_NAR_HF; 2985 } 2986 2987 ATW_WRITE(sc, ATW_NAR, opmode); 2988 DELAY(atw_nar_delay); 2989 2990 for (i = 0; i < 1000; i++) { 2991 stsr = ATW_READ(sc, ATW_STSR); 2992 if ((stsr & ackmask) == ackmask) 2993 break; 2994 DELAY(10); 2995 } 2996 2997 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2998 2999 if ((stsr & ackmask) == ackmask) 3000 goto out; 3001 3002 test0 = ATW_READ(sc, ATW_TEST0); 3003 3004 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3005 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3006 printf("%s: transmit process not idle [%s]\n", 3007 sc->sc_dev.dv_xname, 3008 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3009 printf("%s: bits %08x test0 %08x stsr %08x\n", 3010 sc->sc_dev.dv_xname, bits, test0, stsr); 3011 } 3012 3013 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3014 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3015 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3016 sc->sc_dev.dv_xname, 3017 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3018 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3019 sc->sc_dev.dv_xname, bits, test0, stsr)); 3020 } 3021 out: 3022 if ((bits & ATW_NAR_ST) != 0) 3023 atw_txdrain(sc); 3024 splx(s); 3025 return; 3026 } 3027 3028 /* 3029 * atw_linkintr: 3030 * 3031 * Helper; handle link-status interrupts. 3032 */ 3033 void 3034 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3035 { 3036 struct ieee80211com *ic = &sc->sc_ic; 3037 3038 if (ic->ic_state != IEEE80211_S_RUN) 3039 return; 3040 3041 if (linkstatus & ATW_INTR_LINKON) { 3042 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3043 sc->sc_rescan_timer = 0; 3044 } else if (linkstatus & ATW_INTR_LINKOFF) { 3045 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3046 if (ic->ic_opmode != IEEE80211_M_STA) 3047 return; 3048 sc->sc_rescan_timer = 3; 3049 sc->sc_if.if_timer = 1; 3050 } 3051 } 3052 3053 static inline int 3054 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3055 { 3056 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3057 return 0; 3058 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3059 return 0; 3060 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3061 } 3062 3063 /* 3064 * atw_rxintr: 3065 * 3066 * Helper; handle receive interrupts. 3067 */ 3068 void 3069 atw_rxintr(struct atw_softc *sc) 3070 { 3071 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3072 struct ieee80211com *ic = &sc->sc_ic; 3073 struct ieee80211_node *ni; 3074 struct ieee80211_frame_min *wh; 3075 struct ifnet *ifp = &sc->sc_if; 3076 struct atw_rxsoft *rxs; 3077 struct mbuf *m; 3078 u_int32_t rxstat; 3079 int i, len, rate, rate0; 3080 u_int32_t rssi, rssi0; 3081 3082 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3083 rxs = &sc->sc_rxsoft[i]; 3084 3085 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3086 3087 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3088 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3089 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3090 3091 if (rxstat & ATW_RXSTAT_OWN) 3092 break; /* We have processed all receive buffers. */ 3093 3094 DPRINTF3(sc, 3095 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3096 sc->sc_dev.dv_xname, 3097 rxstat, rssi0, 3098 le32toh(sc->sc_rxdescs[i].ar_buf1), 3099 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3100 3101 /* 3102 * Make sure the packet fits in one buffer. This should 3103 * always be the case. 3104 */ 3105 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3106 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3107 printf("%s: incoming packet spilled, resetting\n", 3108 sc->sc_dev.dv_xname); 3109 (void)atw_init(ifp); 3110 return; 3111 } 3112 3113 /* 3114 * If an error occurred, update stats, clear the status 3115 * word, and leave the packet buffer in place. It will 3116 * simply be reused the next time the ring comes around. 3117 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3118 * error. 3119 */ 3120 3121 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3122 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3123 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3124 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3125 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3126 ATW_RXSTAT_ICVE)) != 0)) { 3127 #define PRINTERR(bit, str) \ 3128 if (rxstat & (bit)) \ 3129 printf("%s: receive error: %s\n", \ 3130 sc->sc_dev.dv_xname, str) 3131 ifp->if_ierrors++; 3132 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3133 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3134 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3135 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3136 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3137 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3138 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3139 #undef PRINTERR 3140 ATW_INIT_RXDESC(sc, i); 3141 continue; 3142 } 3143 3144 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3145 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3146 3147 /* 3148 * No errors; receive the packet. Note the ADM8211 3149 * includes the CRC in promiscuous mode. 3150 */ 3151 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3152 3153 /* 3154 * Allocate a new mbuf cluster. If that fails, we are 3155 * out of memory, and must drop the packet and recycle 3156 * the buffer that's already attached to this descriptor. 3157 */ 3158 m = rxs->rxs_mbuf; 3159 if (atw_add_rxbuf(sc, i) != 0) { 3160 ifp->if_ierrors++; 3161 ATW_INIT_RXDESC(sc, i); 3162 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3163 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3164 continue; 3165 } 3166 3167 ifp->if_ipackets++; 3168 if (sc->sc_opmode & ATW_NAR_PR) 3169 len -= IEEE80211_CRC_LEN; 3170 m->m_pkthdr.rcvif = ifp; 3171 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3172 3173 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3174 rate = 0; 3175 else 3176 rate = rate_tbl[rate0]; 3177 3178 /* The RSSI comes straight from a register in the 3179 * baseband processor. I know that for the RF3000, 3180 * the RSSI register also contains the antenna-selection 3181 * bits. Mask those off. 3182 * 3183 * TBD Treat other basebands. 3184 */ 3185 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3186 rssi = rssi0 & RF3000_RSSI_MASK; 3187 else 3188 rssi = rssi0; 3189 3190 #if NBPFILTER > 0 3191 /* Pass this up to any BPF listeners. */ 3192 if (sc->sc_radiobpf != NULL) { 3193 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3194 3195 tap->ar_rate = rate; 3196 tap->ar_chan_freq = htole16(ic->ic_curchan->ic_freq); 3197 tap->ar_chan_flags = htole16(ic->ic_curchan->ic_flags); 3198 3199 /* TBD verify units are dB */ 3200 tap->ar_antsignal = (int)rssi; 3201 /* TBD tap->ar_flags */ 3202 3203 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3204 tap->ar_ihdr.it_len, m); 3205 } 3206 #endif /* NPBFILTER > 0 */ 3207 3208 wh = mtod(m, struct ieee80211_frame_min *); 3209 ni = ieee80211_find_rxnode(ic, wh); 3210 #if 0 3211 if (atw_hw_decrypted(sc, wh)) { 3212 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3213 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3214 } 3215 #endif 3216 ieee80211_input(ic, m, ni, (int)rssi, 0); 3217 ieee80211_free_node(ni); 3218 } 3219 3220 /* Update the receive pointer. */ 3221 sc->sc_rxptr = i; 3222 } 3223 3224 /* 3225 * atw_txintr: 3226 * 3227 * Helper; handle transmit interrupts. 3228 */ 3229 void 3230 atw_txintr(struct atw_softc *sc) 3231 { 3232 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3233 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3234 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3235 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3236 3237 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3238 struct ifnet *ifp = &sc->sc_if; 3239 struct atw_txsoft *txs; 3240 u_int32_t txstat; 3241 3242 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3243 sc->sc_dev.dv_xname, sc->sc_flags)); 3244 3245 /* 3246 * Go through our Tx list and free mbufs for those 3247 * frames that have been transmitted. 3248 */ 3249 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3250 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3251 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3252 3253 #ifdef ATW_DEBUG 3254 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3255 int i; 3256 printf(" txsoft %p transmit chain:\n", txs); 3257 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3258 txs->txs_ndescs - 1, 3259 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3260 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3261 printf(" descriptor %d:\n", i); 3262 printf(" at_status: 0x%08x\n", 3263 le32toh(sc->sc_txdescs[i].at_stat)); 3264 printf(" at_flags: 0x%08x\n", 3265 le32toh(sc->sc_txdescs[i].at_flags)); 3266 printf(" at_buf1: 0x%08x\n", 3267 le32toh(sc->sc_txdescs[i].at_buf1)); 3268 printf(" at_buf2: 0x%08x\n", 3269 le32toh(sc->sc_txdescs[i].at_buf2)); 3270 if (i == txs->txs_lastdesc) 3271 break; 3272 } 3273 } 3274 #endif 3275 3276 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3277 if (txstat & ATW_TXSTAT_OWN) 3278 break; 3279 3280 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3281 3282 sc->sc_txfree += txs->txs_ndescs; 3283 3284 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3285 0, txs->txs_dmamap->dm_mapsize, 3286 BUS_DMASYNC_POSTWRITE); 3287 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3288 m_freem(txs->txs_mbuf); 3289 txs->txs_mbuf = NULL; 3290 3291 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3292 3293 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3294 sc->sc_txfree == 0)); 3295 ifp->if_flags &= ~IFF_OACTIVE; 3296 3297 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3298 (txstat & TXSTAT_ERRMASK) != 0) { 3299 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3300 txstat_buf, sizeof(txstat_buf)); 3301 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3302 txstat_buf, 3303 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3304 } 3305 3306 /* 3307 * Check for errors and collisions. 3308 */ 3309 if (txstat & ATW_TXSTAT_TUF) 3310 sc->sc_stats.ts_tx_tuf++; 3311 if (txstat & ATW_TXSTAT_TLT) 3312 sc->sc_stats.ts_tx_tlt++; 3313 if (txstat & ATW_TXSTAT_TRT) 3314 sc->sc_stats.ts_tx_trt++; 3315 if (txstat & ATW_TXSTAT_TRO) 3316 sc->sc_stats.ts_tx_tro++; 3317 if (txstat & ATW_TXSTAT_SOFBR) { 3318 sc->sc_stats.ts_tx_sofbr++; 3319 } 3320 3321 if ((txstat & ATW_TXSTAT_ES) == 0) 3322 ifp->if_collisions += 3323 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3324 else 3325 ifp->if_oerrors++; 3326 3327 ifp->if_opackets++; 3328 } 3329 3330 /* 3331 * If there are no more pending transmissions, cancel the watchdog 3332 * timer. 3333 */ 3334 if (txs == NULL) { 3335 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3336 sc->sc_tx_timer = 0; 3337 } 3338 #undef TXSTAT_ERRMASK 3339 #undef TXSTAT_FMT 3340 } 3341 3342 /* 3343 * atw_watchdog: [ifnet interface function] 3344 * 3345 * Watchdog timer handler. 3346 */ 3347 void 3348 atw_watchdog(struct ifnet *ifp) 3349 { 3350 struct atw_softc *sc = ifp->if_softc; 3351 struct ieee80211com *ic = &sc->sc_ic; 3352 3353 ifp->if_timer = 0; 3354 if (ATW_IS_ENABLED(sc) == 0) 3355 return; 3356 3357 if (sc->sc_rescan_timer) { 3358 if (--sc->sc_rescan_timer == 0) 3359 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3360 } 3361 if (sc->sc_tx_timer) { 3362 if (--sc->sc_tx_timer == 0 && 3363 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3364 printf("%s: transmit timeout\n", ifp->if_xname); 3365 ifp->if_oerrors++; 3366 (void)atw_init(ifp); 3367 atw_start(ifp); 3368 } 3369 } 3370 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3371 ifp->if_timer = 1; 3372 ieee80211_watchdog(ic); 3373 } 3374 3375 #ifdef ATW_DEBUG 3376 static void 3377 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3378 { 3379 struct atw_softc *sc = ifp->if_softc; 3380 struct mbuf *m; 3381 int i, noctets = 0; 3382 3383 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3384 m0->m_pkthdr.len); 3385 3386 for (m = m0; m; m = m->m_next) { 3387 if (m->m_len == 0) 3388 continue; 3389 for (i = 0; i < m->m_len; i++) { 3390 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3391 if (++noctets % 24 == 0) 3392 printf("\n"); 3393 } 3394 } 3395 printf("%s%s: %d bytes emitted\n", 3396 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3397 } 3398 #endif /* ATW_DEBUG */ 3399 3400 /* 3401 * atw_start: [ifnet interface function] 3402 * 3403 * Start packet transmission on the interface. 3404 */ 3405 void 3406 atw_start(struct ifnet *ifp) 3407 { 3408 struct atw_softc *sc = ifp->if_softc; 3409 struct ieee80211_key *k; 3410 struct ieee80211com *ic = &sc->sc_ic; 3411 struct ieee80211_node *ni; 3412 struct ieee80211_frame_min *whm; 3413 struct ieee80211_frame *wh; 3414 struct atw_frame *hh; 3415 struct mbuf *m0, *m; 3416 struct atw_txsoft *txs, *last_txs; 3417 struct atw_txdesc *txd; 3418 int npkt, rate; 3419 bus_dmamap_t dmamap; 3420 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3421 3422 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3423 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3424 3425 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3426 return; 3427 3428 /* 3429 * Remember the previous number of free descriptors and 3430 * the first descriptor we'll use. 3431 */ 3432 ofree = sc->sc_txfree; 3433 firsttx = lasttx = sc->sc_txnext; 3434 3435 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3436 sc->sc_dev.dv_xname, ofree, firsttx)); 3437 3438 /* 3439 * Loop through the send queue, setting up transmit descriptors 3440 * until we drain the queue, or use up all available transmit 3441 * descriptors. 3442 */ 3443 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3444 sc->sc_txfree != 0) { 3445 3446 /* 3447 * Grab a packet off the management queue, if it 3448 * is not empty. Otherwise, from the data queue. 3449 */ 3450 IF_DEQUEUE(&ic->ic_mgtq, m0); 3451 if (m0 != NULL) { 3452 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3453 m0->m_pkthdr.rcvif = NULL; 3454 } else if (ic->ic_state != IEEE80211_S_RUN) 3455 break; /* send no data until associated */ 3456 else { 3457 IFQ_DEQUEUE(&ifp->if_snd, m0); 3458 if (m0 == NULL) 3459 break; 3460 #if NBPFILTER > 0 3461 if (ifp->if_bpf != NULL) 3462 bpf_mtap(ifp->if_bpf, m0); 3463 #endif /* NBPFILTER > 0 */ 3464 ni = ieee80211_find_txnode(ic, 3465 mtod(m0, struct ether_header *)->ether_dhost); 3466 if (ni == NULL) { 3467 ifp->if_oerrors++; 3468 break; 3469 } 3470 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3471 ieee80211_free_node(ni); 3472 ifp->if_oerrors++; 3473 break; 3474 } 3475 } 3476 3477 rate = MAX(ieee80211_get_rate(ni), 2); 3478 3479 whm = mtod(m0, struct ieee80211_frame_min *); 3480 3481 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3482 k = NULL; 3483 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3484 m_freem(m0); 3485 ieee80211_free_node(ni); 3486 ifp->if_oerrors++; 3487 break; 3488 } 3489 3490 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3491 ic->ic_flags, ic->ic_fragthreshold, rate, 3492 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3493 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3494 m_freem(m0); 3495 break; 3496 } 3497 3498 /* XXX Misleading if fragmentation is enabled. Better 3499 * to fragment in software? 3500 */ 3501 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3502 3503 #if NBPFILTER > 0 3504 /* 3505 * Pass the packet to any BPF listeners. 3506 */ 3507 if (ic->ic_rawbpf != NULL) 3508 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3509 3510 if (sc->sc_radiobpf != NULL) { 3511 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3512 3513 tap->at_rate = rate; 3514 tap->at_chan_freq = htole16(ic->ic_curchan->ic_freq); 3515 tap->at_chan_flags = htole16(ic->ic_curchan->ic_flags); 3516 3517 /* TBD tap->at_flags */ 3518 3519 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3520 tap->at_ihdr.it_len, m0); 3521 } 3522 #endif /* NBPFILTER > 0 */ 3523 3524 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3525 3526 if (ni != NULL) 3527 ieee80211_free_node(ni); 3528 3529 if (m0 == NULL) { 3530 ifp->if_oerrors++; 3531 break; 3532 } 3533 3534 /* just to make sure. */ 3535 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3536 3537 if (m0 == NULL) { 3538 ifp->if_oerrors++; 3539 break; 3540 } 3541 3542 hh = mtod(m0, struct atw_frame *); 3543 wh = &hh->atw_ihdr; 3544 3545 /* Copy everything we need from the 802.11 header: 3546 * Frame Control; address 1, address 3, or addresses 3547 * 3 and 4. NIC fills in BSSID, SA. 3548 */ 3549 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3550 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3551 panic("%s: illegal WDS frame", 3552 sc->sc_dev.dv_xname); 3553 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3554 } else 3555 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3556 3557 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3558 3559 /* initialize remaining Tx parameters */ 3560 memset(&hh->u, 0, sizeof(hh->u)); 3561 3562 hh->atw_rate = rate * 5; 3563 /* XXX this could be incorrect if M_FCS. _encap should 3564 * probably strip FCS just in case it sticks around in 3565 * bridged packets. 3566 */ 3567 hh->atw_service = 0x00; /* XXX guess */ 3568 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3569 sizeof(struct atw_frame)); 3570 3571 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3572 hh->atw_rtylmt = 3; 3573 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3574 #if 0 3575 if (do_encrypt) { 3576 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3577 hh->atw_keyid = ic->ic_def_txkey; 3578 } 3579 #endif 3580 3581 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3582 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3583 if (txs->txs_d0.d_residue) 3584 hh->atw_head_plcplen |= htole16(0x8000); 3585 if (txs->txs_dn.d_residue) 3586 hh->atw_tail_plcplen |= htole16(0x8000); 3587 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3588 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3589 3590 /* never fragment multicast frames */ 3591 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3592 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3593 } else if (sc->sc_flags & ATWF_RTSCTS) { 3594 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3595 } 3596 3597 #ifdef ATW_DEBUG 3598 hh->atw_fragnum = 0; 3599 3600 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3601 printf("%s: dst = %s, rate = 0x%02x, " 3602 "service = 0x%02x, paylen = 0x%04x\n", 3603 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3604 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3605 3606 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3607 "dur1 = 0x%04x, dur2 = 0x%04x, " 3608 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3609 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3610 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3611 hh->atw_tail_dur, hh->atw_head_dur); 3612 3613 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3614 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3615 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3616 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3617 3618 printf("%s: keyid = %d\n", 3619 sc->sc_dev.dv_xname, hh->atw_keyid); 3620 3621 atw_dump_pkt(ifp, m0); 3622 } 3623 #endif /* ATW_DEBUG */ 3624 3625 dmamap = txs->txs_dmamap; 3626 3627 /* 3628 * Load the DMA map. Copy and try (once) again if the packet 3629 * didn't fit in the alloted number of segments. 3630 */ 3631 for (first = 1; 3632 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3633 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3634 first = 0) { 3635 MGETHDR(m, M_DONTWAIT, MT_DATA); 3636 if (m == NULL) { 3637 printf("%s: unable to allocate Tx mbuf\n", 3638 sc->sc_dev.dv_xname); 3639 break; 3640 } 3641 if (m0->m_pkthdr.len > MHLEN) { 3642 MCLGET(m, M_DONTWAIT); 3643 if ((m->m_flags & M_EXT) == 0) { 3644 printf("%s: unable to allocate Tx " 3645 "cluster\n", sc->sc_dev.dv_xname); 3646 m_freem(m); 3647 break; 3648 } 3649 } 3650 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3651 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3652 m_freem(m0); 3653 m0 = m; 3654 m = NULL; 3655 } 3656 if (error != 0) { 3657 printf("%s: unable to load Tx buffer, " 3658 "error = %d\n", sc->sc_dev.dv_xname, error); 3659 m_freem(m0); 3660 break; 3661 } 3662 3663 /* 3664 * Ensure we have enough descriptors free to describe 3665 * the packet. 3666 */ 3667 if (dmamap->dm_nsegs > sc->sc_txfree) { 3668 /* 3669 * Not enough free descriptors to transmit 3670 * this packet. Unload the DMA map and 3671 * drop the packet. Notify the upper layer 3672 * that there are no more slots left. 3673 * 3674 * XXX We could allocate an mbuf and copy, but 3675 * XXX it is worth it? 3676 */ 3677 bus_dmamap_unload(sc->sc_dmat, dmamap); 3678 m_freem(m0); 3679 break; 3680 } 3681 3682 /* 3683 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3684 */ 3685 3686 /* Sync the DMA map. */ 3687 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3688 BUS_DMASYNC_PREWRITE); 3689 3690 /* XXX arbitrary retry limit; 8 because I have seen it in 3691 * use already and maybe 0 means "no tries" ! 3692 */ 3693 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3694 3695 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3696 sc->sc_dev.dv_xname, rate * 5)); 3697 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3698 3699 /* 3700 * Initialize the transmit descriptors. 3701 */ 3702 for (nexttx = sc->sc_txnext, seg = 0; 3703 seg < dmamap->dm_nsegs; 3704 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3705 /* 3706 * If this is the first descriptor we're 3707 * enqueueing, don't set the OWN bit just 3708 * yet. That could cause a race condition. 3709 * We'll do it below. 3710 */ 3711 txd = &sc->sc_txdescs[nexttx]; 3712 txd->at_ctl = ctl | 3713 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3714 3715 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3716 txd->at_flags = 3717 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3718 ATW_TXFLAG_TBS1_MASK)) | 3719 ((nexttx == (ATW_NTXDESC - 1)) 3720 ? htole32(ATW_TXFLAG_TER) : 0); 3721 lasttx = nexttx; 3722 } 3723 3724 /* Set `first segment' and `last segment' appropriately. */ 3725 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3726 htole32(ATW_TXFLAG_FS); 3727 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3728 3729 #ifdef ATW_DEBUG 3730 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3731 printf(" txsoft %p transmit chain:\n", txs); 3732 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3733 printf(" descriptor %d:\n", seg); 3734 printf(" at_ctl: 0x%08x\n", 3735 le32toh(sc->sc_txdescs[seg].at_ctl)); 3736 printf(" at_flags: 0x%08x\n", 3737 le32toh(sc->sc_txdescs[seg].at_flags)); 3738 printf(" at_buf1: 0x%08x\n", 3739 le32toh(sc->sc_txdescs[seg].at_buf1)); 3740 printf(" at_buf2: 0x%08x\n", 3741 le32toh(sc->sc_txdescs[seg].at_buf2)); 3742 if (seg == lasttx) 3743 break; 3744 } 3745 } 3746 #endif 3747 3748 /* Sync the descriptors we're using. */ 3749 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3750 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3751 3752 /* 3753 * Store a pointer to the packet so we can free it later, 3754 * and remember what txdirty will be once the packet is 3755 * done. 3756 */ 3757 txs->txs_mbuf = m0; 3758 txs->txs_firstdesc = sc->sc_txnext; 3759 txs->txs_lastdesc = lasttx; 3760 txs->txs_ndescs = dmamap->dm_nsegs; 3761 3762 /* Advance the tx pointer. */ 3763 sc->sc_txfree -= dmamap->dm_nsegs; 3764 sc->sc_txnext = nexttx; 3765 3766 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3767 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3768 3769 last_txs = txs; 3770 } 3771 3772 if (sc->sc_txfree != ofree) { 3773 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3774 sc->sc_dev.dv_xname, lasttx, firsttx)); 3775 /* 3776 * Cause a transmit interrupt to happen on the 3777 * last packet we enqueued. 3778 */ 3779 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3780 ATW_CDTXSYNC(sc, lasttx, 1, 3781 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3782 3783 /* 3784 * The entire packet chain is set up. Give the 3785 * first descriptor to the chip now. 3786 */ 3787 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3788 ATW_CDTXSYNC(sc, firsttx, 1, 3789 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3790 3791 /* Wake up the transmitter. */ 3792 ATW_WRITE(sc, ATW_TDR, 0x1); 3793 3794 if (txs == NULL || sc->sc_txfree == 0) 3795 ifp->if_flags |= IFF_OACTIVE; 3796 3797 /* Set a watchdog timer in case the chip flakes out. */ 3798 sc->sc_tx_timer = 5; 3799 ifp->if_timer = 1; 3800 } 3801 } 3802 3803 /* 3804 * atw_power: 3805 * 3806 * Power management (suspend/resume) hook. 3807 */ 3808 void 3809 atw_power(int why, void *arg) 3810 { 3811 struct atw_softc *sc = arg; 3812 struct ifnet *ifp = &sc->sc_if; 3813 int s; 3814 3815 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3816 3817 s = splnet(); 3818 switch (why) { 3819 case PWR_STANDBY: 3820 /* XXX do nothing. */ 3821 break; 3822 case PWR_SUSPEND: 3823 atw_stop(ifp, 0); 3824 if (sc->sc_power != NULL) 3825 (*sc->sc_power)(sc, why); 3826 break; 3827 case PWR_RESUME: 3828 if (ifp->if_flags & IFF_UP) { 3829 if (sc->sc_power != NULL) 3830 (*sc->sc_power)(sc, why); 3831 atw_init(ifp); 3832 } 3833 break; 3834 case PWR_SOFTSUSPEND: 3835 case PWR_SOFTSTANDBY: 3836 case PWR_SOFTRESUME: 3837 break; 3838 } 3839 splx(s); 3840 } 3841 3842 /* 3843 * atw_ioctl: [ifnet interface function] 3844 * 3845 * Handle control requests from the operator. 3846 */ 3847 int 3848 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3849 { 3850 struct atw_softc *sc = ifp->if_softc; 3851 struct ifreq *ifr = (struct ifreq *)data; 3852 int s, error = 0; 3853 3854 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3855 if (!device_is_active(&sc->sc_dev)) 3856 return ENXIO; 3857 3858 s = splnet(); 3859 3860 switch (cmd) { 3861 case SIOCSIFFLAGS: 3862 if (ifp->if_flags & IFF_UP) { 3863 if (ATW_IS_ENABLED(sc)) { 3864 /* 3865 * To avoid rescanning another access point, 3866 * do not call atw_init() here. Instead, 3867 * only reflect media settings. 3868 */ 3869 atw_filter_setup(sc); 3870 } else 3871 error = atw_init(ifp); 3872 } else if (ATW_IS_ENABLED(sc)) 3873 atw_stop(ifp, 1); 3874 break; 3875 case SIOCADDMULTI: 3876 case SIOCDELMULTI: 3877 error = (cmd == SIOCADDMULTI) ? 3878 ether_addmulti(ifr, &sc->sc_ec) : 3879 ether_delmulti(ifr, &sc->sc_ec); 3880 if (error == ENETRESET) { 3881 if (ifp->if_flags & IFF_RUNNING) 3882 atw_filter_setup(sc); /* do not rescan */ 3883 error = 0; 3884 } 3885 break; 3886 default: 3887 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3888 if (error == ENETRESET || error == ERESTART) { 3889 if (is_running(ifp)) 3890 error = atw_init(ifp); 3891 else 3892 error = 0; 3893 } 3894 break; 3895 } 3896 3897 /* Try to get more packets going. */ 3898 if (ATW_IS_ENABLED(sc)) 3899 atw_start(ifp); 3900 3901 splx(s); 3902 return (error); 3903 } 3904 3905 static int 3906 atw_media_change(struct ifnet *ifp) 3907 { 3908 int error; 3909 3910 error = ieee80211_media_change(ifp); 3911 if (error == ENETRESET) { 3912 if (is_running(ifp)) 3913 error = atw_init(ifp); 3914 else 3915 error = 0; 3916 } 3917 return error; 3918 } 3919
Indexes created Fri Sep 26 20:09:58 GMT 2025