atw.c revision 1.12
1 /* $NetBSD: atw.c,v 1.12 2003/11/16 09:02:42 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.12 2003/11/16 09:02:42 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/atwvar.h> 82 #include <dev/ic/smc93cx6var.h> 83 84 /* XXX TBD open questions 85 * 86 * 87 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 88 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 89 * handle this for me? 90 * 91 */ 92 /* device attachment 93 * 94 * print TOFS[012] 95 * 96 * device initialization 97 * 98 * clear ATW_FRCTL_MAXPSP to disable max power saving 99 * set ATW_TXBR_ALCUPDATE to enable ALC 100 * set TOFS[012]? (hope not) 101 * disable rx/tx 102 * set ATW_PAR_SWR (software reset) 103 * wait for ATW_PAR_SWR clear 104 * disable interrupts 105 * ack status register 106 * enable interrupts 107 * 108 * rx/tx initialization 109 * 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * allocate and init descriptor rings 112 * write ATW_PAR_DSL (descriptor skip length) 113 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * write ATW_NAR_SQ for one/both transmit descriptor rings 116 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * 118 * rx/tx end 119 * 120 * stop DMA 121 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 122 * flush tx w/ ATW_NAR_HF 123 * 124 * scan 125 * 126 * initialize rx/tx 127 * 128 * IBSS join/create 129 * 130 * set ATW_NAR_EA (is set by ASIC?) 131 * 132 * BSS join: (re)association response 133 * 134 * set ATW_FRCTL_AID 135 * 136 * optimizations ??? 137 * 138 */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_rfio_enable_delay = 20 * 1000; 145 int atw_rfio_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 5; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 150 #ifdef ATW_DEBUG 151 int atw_xhdrctl = 0; 152 int atw_xrtylmt = ~0; 153 int atw_xservice = IEEE80211_PLCP_SERVICE; 154 int atw_xpaylen = 0; 155 156 int atw_debug = 0; 157 158 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 159 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 160 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 161 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 162 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 163 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 164 static void atw_print_regs(struct atw_softc *, const char *); 165 static void atw_rf3000_print(struct atw_softc *); 166 static void atw_si4126_print(struct atw_softc *); 167 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 168 #else 169 #define ATW_DPRINTF(x) 170 #define ATW_DPRINTF2(x) 171 #define ATW_DPRINTF3(x) 172 #define DPRINTF(sc, x) /* nothing */ 173 #define DPRINTF2(sc, x) /* nothing */ 174 #define DPRINTF3(sc, x) /* nothing */ 175 #endif 176 177 #ifdef ATW_STATS 178 void atw_print_stats __P((struct atw_softc *)); 179 #endif 180 181 void atw_start __P((struct ifnet *)); 182 void atw_watchdog __P((struct ifnet *)); 183 int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 184 int atw_init __P((struct ifnet *)); 185 void atw_stop __P((struct ifnet *, int)); 186 187 void atw_reset __P((struct atw_softc *)); 188 int atw_read_srom __P((struct atw_softc *)); 189 190 void atw_shutdown __P((void *)); 191 192 void atw_rxdrain __P((struct atw_softc *)); 193 int atw_add_rxbuf __P((struct atw_softc *, int)); 194 void atw_idle __P((struct atw_softc *, u_int32_t)); 195 196 int atw_enable __P((struct atw_softc *)); 197 void atw_disable __P((struct atw_softc *)); 198 void atw_power __P((int, void *)); 199 200 void atw_rxintr __P((struct atw_softc *)); 201 void atw_txintr __P((struct atw_softc *)); 202 void atw_linkintr __P((struct atw_softc *, u_int32_t)); 203 204 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 205 static void atw_tsf(struct atw_softc *); 206 static void atw_start_beacon(struct atw_softc *, int); 207 static void atw_write_wep(struct atw_softc *); 208 static void atw_write_bssid(struct atw_softc *); 209 static void atw_write_bcn_thresh(struct atw_softc *); 210 static void atw_write_ssid(struct atw_softc *); 211 static void atw_write_sup_rates(struct atw_softc *); 212 static void atw_clear_sram(struct atw_softc *); 213 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 214 static int atw_media_change(struct ifnet *); 215 static void atw_media_status(struct ifnet *, struct ifmediareq *); 216 static void atw_filter_setup(struct atw_softc *); 217 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 218 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 219 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 224 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 225 226 static int atw_tune(struct atw_softc *); 227 228 static void atw_rfio_enable(struct atw_softc *, int); 229 230 /* RFMD RF3000 Baseband Processor */ 231 static int atw_rf3000_init(struct atw_softc *); 232 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 233 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 234 #ifdef ATW_DEBUG 235 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 236 #endif /* ATW_DEBUG */ 237 238 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 239 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 240 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 241 #ifdef ATW_DEBUG 242 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 243 #endif /* ATW_DEBUG */ 244 245 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 246 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 247 248 const char *atw_tx_state[] = { 249 "STOPPED", 250 "RUNNING - FETCH", 251 "RUNNING - WAIT", 252 "RUNNING - READING", 253 "-- RESERVED1 --", 254 "-- RESERVED2 --", 255 "SUSPENDED", 256 "RUNNING - CLOSE" 257 }; 258 259 const char *atw_rx_state[] = { 260 "STOPPED", 261 "RUNNING - FETCH", 262 "RUNNING - CHECK", 263 "RUNNING - WAIT", 264 "SUSPENDED", 265 "RUNNING - CLOSE", 266 "RUNNING - FLUSH", 267 "RUNNING - QUEUE" 268 }; 269 270 int 271 atw_activate(struct device *self, enum devact act) 272 { 273 struct atw_softc *sc = (struct atw_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 282 case DVACT_DEACTIVATE: 283 if_deactivate(&sc->sc_ic.ic_if); 284 break; 285 } 286 splx(s); 287 return rv; 288 } 289 290 /* 291 * atw_enable: 292 * 293 * Enable the ADM8211 chip. 294 */ 295 int 296 atw_enable(sc) 297 struct atw_softc *sc; 298 { 299 300 if (ATW_IS_ENABLED(sc) == 0) { 301 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 302 printf("%s: device enable failed\n", 303 sc->sc_dev.dv_xname); 304 return (EIO); 305 } 306 sc->sc_flags |= ATWF_ENABLED; 307 } 308 return (0); 309 } 310 311 /* 312 * atw_disable: 313 * 314 * Disable the ADM8211 chip. 315 */ 316 void 317 atw_disable(sc) 318 struct atw_softc *sc; 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF2(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF2(("\n\t")); 400 } 401 ATW_DPRINTF2((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF2(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 struct ieee80211com *ic = &sc->sc_ic; 498 struct ifnet *ifp = &ic->ic_if; 499 int country_code, error, i, nrate; 500 u_int32_t reg; 501 static const char *type_strings[] = {"Intersil (not supported)", 502 "RFMD", "Marvel (not supported)"}; 503 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 504 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 505 }; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 sc->sc_rxsoft[i].rxs_mbuf = NULL; 577 } 578 579 /* Reset the chip to a known state. */ 580 atw_reset(sc); 581 582 if (atw_read_srom(sc) == -1) 583 return; 584 585 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 586 ATW_SR_RFTYPE_MASK); 587 588 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 589 ATW_SR_BBPTYPE_MASK); 590 591 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 592 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 600 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 601 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 602 603 /* XXX There exists a Linux driver which seems to use RFType = 0 for 604 * MARVEL. My bug, or theirs? 605 */ 606 607 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 608 609 switch (sc->sc_rftype) { 610 case ATW_RFTYPE_INTERSIL: 611 reg |= ATW_SYNCTL_CS1; 612 break; 613 case ATW_RFTYPE_RFMD: 614 reg |= ATW_SYNCTL_CS0; 615 break; 616 case ATW_RFTYPE_MARVEL: 617 break; 618 } 619 620 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 621 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 622 623 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 624 625 switch (sc->sc_bbptype) { 626 case ATW_RFTYPE_INTERSIL: 627 reg |= ATW_BBPCTL_TWI; 628 break; 629 case ATW_RFTYPE_RFMD: 630 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 631 ATW_BBPCTL_CCA_ACTLO; 632 break; 633 case ATW_RFTYPE_MARVEL: 634 break; 635 } 636 637 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 638 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 639 640 /* 641 * From this point forward, the attachment cannot fail. A failure 642 * before this point releases all resources that may have been 643 * allocated. 644 */ 645 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 646 647 ATW_DPRINTF2((" SROM MAC %04x%04x%04x", 648 htole16(sc->sc_srom[ATW_SR_MAC00]), 649 htole16(sc->sc_srom[ATW_SR_MAC01]), 650 htole16(sc->sc_srom[ATW_SR_MAC10]))); 651 652 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 653 ATW_SR_CTRY_MASK); 654 655 #define ADD_CHANNEL(_ic, _chan) do { \ 656 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 657 _ic->ic_channels[_chan].ic_freq = \ 658 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 659 } while (0) 660 661 /* Find available channels */ 662 switch (country_code) { 663 case COUNTRY_MMK2: /* 1-14 */ 664 ADD_CHANNEL(ic, 14); 665 /*FALLTHROUGH*/ 666 case COUNTRY_ETSI: /* 1-13 */ 667 for (i = 1; i <= 13; i++) 668 ADD_CHANNEL(ic, i); 669 break; 670 case COUNTRY_FCC: /* 1-11 */ 671 case COUNTRY_IC: /* 1-11 */ 672 for (i = 1; i <= 11; i++) 673 ADD_CHANNEL(ic, i); 674 break; 675 case COUNTRY_MMK: /* 14 */ 676 ADD_CHANNEL(ic, 14); 677 break; 678 case COUNTRY_FRANCE: /* 10-13 */ 679 for (i = 10; i <= 13; i++) 680 ADD_CHANNEL(ic, i); 681 break; 682 default: /* assume channels 10-11 */ 683 case COUNTRY_SPAIN: /* 10-11 */ 684 for (i = 10; i <= 11; i++) 685 ADD_CHANNEL(ic, i); 686 break; 687 } 688 689 /* Read the MAC address. */ 690 reg = ATW_READ(sc, ATW_PAR0); 691 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 692 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 693 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 694 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 695 reg = ATW_READ(sc, ATW_PAR1); 696 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 697 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 698 699 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 700 printf(" could not get mac address, attach failed\n"); 701 return; 702 } 703 704 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 705 706 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 707 ifp->if_softc = sc; 708 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 709 IFF_NOTRAILERS; 710 ifp->if_ioctl = atw_ioctl; 711 ifp->if_start = atw_start; 712 ifp->if_watchdog = atw_watchdog; 713 ifp->if_init = atw_init; 714 ifp->if_stop = atw_stop; 715 IFQ_SET_READY(&ifp->if_snd); 716 717 ic->ic_phytype = IEEE80211_T_DS; 718 ic->ic_opmode = IEEE80211_M_STA; 719 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 720 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 721 722 nrate = 0; 723 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 724 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 728 729 /* 730 * Call MI attach routines. 731 */ 732 733 if_attach(ifp); 734 ieee80211_ifattach(ifp); 735 736 sc->sc_newstate = ic->ic_newstate; 737 ic->ic_newstate = atw_newstate; 738 739 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 740 ic->ic_recv_mgmt = atw_recv_mgmt; 741 742 sc->sc_node_free = ic->ic_node_free; 743 ic->ic_node_free = atw_node_free; 744 745 sc->sc_node_alloc = ic->ic_node_alloc; 746 ic->ic_node_alloc = atw_node_alloc; 747 748 /* possibly we should fill in our own sc_send_prresp, since 749 * the ADM8211 is probably sending probe responses in ad hoc 750 * mode. 751 */ 752 753 /* complete initialization */ 754 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 755 callout_init(&sc->sc_scan_ch); 756 757 #if NBPFILTER > 0 758 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 759 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 760 #endif 761 762 /* 763 * Make sure the interface is shutdown during reboot. 764 */ 765 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 766 if (sc->sc_sdhook == NULL) 767 printf("%s: WARNING: unable to establish shutdown hook\n", 768 sc->sc_dev.dv_xname); 769 770 /* 771 * Add a suspend hook to make sure we come back up after a 772 * resume. 773 */ 774 sc->sc_powerhook = powerhook_establish(atw_power, sc); 775 if (sc->sc_powerhook == NULL) 776 printf("%s: WARNING: unable to establish power hook\n", 777 sc->sc_dev.dv_xname); 778 779 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 780 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 781 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 782 783 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 784 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 785 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 786 787 return; 788 789 /* 790 * Free any resources we've allocated during the failed attach 791 * attempt. Do this in reverse order and fall through. 792 */ 793 fail_5: 794 for (i = 0; i < ATW_NRXDESC; i++) { 795 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 796 continue; 797 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 798 } 799 fail_4: 800 for (i = 0; i < ATW_TXQUEUELEN; i++) { 801 if (sc->sc_txsoft[i].txs_dmamap == NULL) 802 continue; 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 804 } 805 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 806 fail_3: 807 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 808 fail_2: 809 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 810 sizeof(struct atw_control_data)); 811 fail_1: 812 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 813 fail_0: 814 return; 815 } 816 817 static struct ieee80211_node * 818 atw_node_alloc(struct ieee80211com *ic) 819 { 820 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 821 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 822 823 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 824 return ni; 825 } 826 827 static void 828 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 829 { 830 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 831 832 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 833 ether_sprintf(ni->ni_bssid))); 834 (*sc->sc_node_free)(ic, ni); 835 } 836 837 /* 838 * atw_reset: 839 * 840 * Perform a soft reset on the ADM8211. 841 */ 842 void 843 atw_reset(sc) 844 struct atw_softc *sc; 845 { 846 int i; 847 848 if (ATW_IS_ENABLED(sc) == 0) 849 return; 850 851 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 852 853 for (i = 0; i < 10000; i++) { 854 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 855 break; 856 DELAY(1); 857 } 858 859 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 860 861 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 862 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 863 864 /* Turn off maximum power saving. */ 865 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 866 867 /* Recall EEPROM. */ 868 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 869 870 DELAY(10 * 1000); 871 872 /* A reset seems to affect the SRAM contents, so put them into 873 * a known state. 874 */ 875 atw_clear_sram(sc); 876 877 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 878 879 sc->sc_lost_bcn_thresh = 0; 880 } 881 882 static void 883 atw_clear_sram(sc) 884 struct atw_softc *sc; 885 { 886 #if 0 887 for (addr = 0; addr < 448; addr++) { 888 ATW_WRITE(sc, ATW_WEPCTL, 889 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 890 DELAY(1000); 891 ATW_WRITE(sc, ATW_WESK, 0); 892 DELAY(1000); /* paranoia */ 893 } 894 return; 895 #endif 896 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 897 /* XXX not for revision 0x20. */ 898 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 899 } 900 901 /* TBD atw_init 902 * 903 * set MAC based on ic->ic_bss->myaddr 904 * write WEP keys 905 * set TX rate 906 */ 907 908 /* 909 * atw_init: [ ifnet interface function ] 910 * 911 * Initialize the interface. Must be called at splnet(). 912 */ 913 int 914 atw_init(ifp) 915 struct ifnet *ifp; 916 { 917 struct atw_softc *sc = ifp->if_softc; 918 struct ieee80211com *ic = &sc->sc_ic; 919 struct atw_txsoft *txs; 920 struct atw_rxsoft *rxs; 921 u_int32_t reg; 922 int i, error = 0; 923 924 if ((error = atw_enable(sc)) != 0) 925 goto out; 926 927 /* 928 * Cancel any pending I/O. This also resets. 929 */ 930 atw_stop(ifp, 0); 931 932 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 933 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 934 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 935 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 936 937 /* Turn off APM??? (A binary-only driver does this.) 938 * 939 * Set Rx store-and-forward mode. 940 */ 941 reg = ATW_READ(sc, ATW_CMDR); 942 reg &= ~ATW_CMDR_APM; 943 reg &= ~ATW_CMDR_DRT_MASK; 944 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 945 946 ATW_WRITE(sc, ATW_CMDR, reg); 947 948 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 949 * 950 * XXX a binary-only driver sets a different service field than 951 * 0. why? 952 */ 953 reg = ATW_READ(sc, ATW_PLCPHD); 954 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 955 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 956 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 957 ATW_WRITE(sc, ATW_PLCPHD, reg); 958 959 /* XXX */ 960 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 961 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 962 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 963 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 964 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 965 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 966 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 967 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 968 ATW_WRITE(sc, ATW_TOFS2, reg); 969 970 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 971 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 972 973 /* XXX this resets an Intersil RF front-end? */ 974 /* TBD condition on Intersil RFType? */ 975 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 976 DELAY(10 * 1000); 977 ATW_WRITE(sc, ATW_SYNRF, 0); 978 DELAY(5 * 1000); 979 980 /* 16 TU max duration for contention-free period */ 981 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 982 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 983 984 /* XXX I guess that the Cardbus clock is 22MHz? 985 * I am assuming that the role of ATW_TOFS0_USCNT is 986 * to divide the bus clock to get a 1MHz clock---the datasheet is not 987 * very clear on this point. It says in the datasheet that it is 988 * possible for the ADM8211 to accomodate bus speeds between 22MHz 989 * and 33MHz; maybe this is the way? I see a binary-only driver write 990 * these values. These values are also the power-on default. 991 */ 992 ATW_WRITE(sc, ATW_TOFS0, 993 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 994 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 995 996 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 997 * driver. go figure. 998 */ 999 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1000 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1001 ATW_IFST_SIFS_MASK) | 1002 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1003 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1004 1005 ATW_WRITE(sc, ATW_IFST, reg); 1006 1007 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1008 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1009 1010 /* Set up the MMI read/write addresses for the BBP. 1011 * 1012 * TBD find out the Marvel settings. 1013 */ 1014 switch (sc->sc_bbptype) { 1015 case ATW_BBPTYPE_INTERSIL: 1016 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1017 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1018 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1019 break; 1020 case ATW_BBPTYPE_MARVEL: 1021 break; 1022 case ATW_BBPTYPE_RFMD: 1023 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1024 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1025 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1026 default: 1027 break; 1028 } 1029 1030 sc->sc_wepctl = 0; 1031 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1032 1033 if ((error = atw_rf3000_init(sc)) != 0) 1034 goto out; 1035 1036 /* 1037 * Initialize the PCI Access Register. 1038 */ 1039 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1040 1041 /* 1042 * If we're allowed to do so, use Memory Read Line 1043 * and Memory Read Multiple. 1044 * 1045 * XXX Should we use Memory Write and Invalidate? 1046 */ 1047 if (sc->sc_flags & ATWF_MRL) 1048 sc->sc_busmode |= ATW_PAR_MRLE; 1049 if (sc->sc_flags & ATWF_MRM) 1050 sc->sc_busmode |= ATW_PAR_MRME; 1051 if (sc->sc_flags & ATWF_MWI) 1052 sc->sc_busmode |= ATW_PAR_MWIE; 1053 if (sc->sc_maxburst == 0) 1054 sc->sc_maxburst = 8; /* ADM8211 default */ 1055 1056 switch (sc->sc_cacheline) { 1057 default: 1058 /* Use burst length. */ 1059 break; 1060 case 8: 1061 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1062 break; 1063 case 16: 1064 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1065 break; 1066 case 32: 1067 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1068 break; 1069 } 1070 switch (sc->sc_maxburst) { 1071 case 1: 1072 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1073 break; 1074 case 2: 1075 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1076 break; 1077 case 4: 1078 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1079 break; 1080 case 8: 1081 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1082 break; 1083 case 16: 1084 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1085 break; 1086 case 32: 1087 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1088 break; 1089 default: 1090 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1091 break; 1092 } 1093 1094 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1095 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1096 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1097 1098 /* 1099 * Initialize the OPMODE register. We don't write it until 1100 * we're ready to begin the transmit and receive processes. 1101 */ 1102 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1103 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1104 1105 /* 1106 * Initialize the transmit descriptor ring. 1107 */ 1108 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1109 for (i = 0; i < ATW_NTXDESC; i++) { 1110 /* no transmit chaining */ 1111 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1112 sc->sc_txdescs[i].at_buf2 = 1113 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1114 } 1115 /* use ring mode */ 1116 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1117 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 sc->sc_txfree = ATW_NTXDESC; 1120 sc->sc_txnext = 0; 1121 1122 /* 1123 * Initialize the transmit job descriptors. 1124 */ 1125 SIMPLEQ_INIT(&sc->sc_txfreeq); 1126 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1127 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1128 txs = &sc->sc_txsoft[i]; 1129 txs->txs_mbuf = NULL; 1130 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1131 } 1132 1133 /* 1134 * Initialize the receive descriptor and receive job 1135 * descriptor rings. 1136 */ 1137 for (i = 0; i < ATW_NRXDESC; i++) { 1138 rxs = &sc->sc_rxsoft[i]; 1139 if (rxs->rxs_mbuf == NULL) { 1140 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1141 printf("%s: unable to allocate or map rx " 1142 "buffer %d, error = %d\n", 1143 sc->sc_dev.dv_xname, i, error); 1144 /* 1145 * XXX Should attempt to run with fewer receive 1146 * XXX buffers instead of just failing. 1147 */ 1148 atw_rxdrain(sc); 1149 goto out; 1150 } 1151 } else 1152 ATW_INIT_RXDESC(sc, i); 1153 } 1154 sc->sc_rxptr = 0; 1155 1156 /* disable all wake-up events */ 1157 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1158 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1159 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1160 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1161 1162 /* ack all wake-up events */ 1163 ATW_SET(sc, ATW_WCSR, 0); 1164 1165 /* 1166 * Initialize the interrupt mask and enable interrupts. 1167 */ 1168 /* normal interrupts */ 1169 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1170 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1171 1172 /* abnormal interrupts */ 1173 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1174 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1175 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1176 1177 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1178 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1179 1180 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1181 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1182 ATW_INTR_TRT; 1183 1184 sc->sc_linkint_mask &= sc->sc_inten; 1185 sc->sc_rxint_mask &= sc->sc_inten; 1186 sc->sc_txint_mask &= sc->sc_inten; 1187 1188 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1189 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1190 if (sc->sc_intr_ack != NULL) 1191 (*sc->sc_intr_ack)(sc); 1192 1193 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1194 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1195 1196 /* 1197 * Give the transmit and receive rings to the ADM8211. 1198 */ 1199 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1200 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1201 1202 /* common 802.11 configuration */ 1203 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1204 switch (ic->ic_opmode) { 1205 case IEEE80211_M_HOSTAP: /* XXX */ 1206 case IEEE80211_M_STA: 1207 sc->sc_opmode &= ~ATW_NAR_EA; 1208 break; 1209 case IEEE80211_M_AHDEMO: /* XXX */ 1210 case IEEE80211_M_IBSS: 1211 /* EA bit seems important for ad hoc reception. */ 1212 sc->sc_opmode |= ATW_NAR_EA; 1213 ic->ic_flags |= IEEE80211_F_IBSSON; 1214 break; 1215 case IEEE80211_M_MONITOR: /* XXX */ 1216 break; 1217 } 1218 1219 atw_start_beacon(sc, 0); 1220 1221 switch (ic->ic_opmode) { 1222 case IEEE80211_M_AHDEMO: 1223 case IEEE80211_M_HOSTAP: 1224 ic->ic_bss->ni_intval = ic->ic_lintval; 1225 ic->ic_bss->ni_rssi = 0; 1226 ic->ic_bss->ni_rstamp = 0; 1227 break; 1228 default: /* XXX */ 1229 break; 1230 } 1231 1232 atw_write_ssid(sc); 1233 atw_write_sup_rates(sc); 1234 if (ic->ic_caps & IEEE80211_C_WEP) 1235 atw_write_wep(sc); 1236 1237 /* 1238 * Set the receive filter. This will start the transmit and 1239 * receive processes. 1240 */ 1241 atw_filter_setup(sc); 1242 1243 /* 1244 * Start the receive process. 1245 */ 1246 ATW_WRITE(sc, ATW_RDR, 0x1); 1247 1248 /* 1249 * Note that the interface is now running. 1250 */ 1251 ifp->if_flags |= IFF_RUNNING; 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 ic->ic_state = IEEE80211_S_INIT; 1254 1255 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1256 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1257 else 1258 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1259 out: 1260 if (error) { 1261 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1262 ifp->if_timer = 0; 1263 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1264 } 1265 #ifdef ATW_DEBUG 1266 atw_print_regs(sc, "end of init"); 1267 #endif /* ATW_DEBUG */ 1268 1269 return (error); 1270 } 1271 1272 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1273 * 0: MAC control of RF3000/Si4126. 1274 * 1275 * Applies power, or selects RF front-end? Sets reset condition. 1276 * 1277 * TBD support non-RFMD BBP, non-SiLabs synth. 1278 */ 1279 static void 1280 atw_rfio_enable(struct atw_softc *sc, int enable) 1281 { 1282 if (enable) { 1283 ATW_WRITE(sc, ATW_SYNRF, 1284 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1285 DELAY(atw_rfio_enable_delay); 1286 } else { 1287 ATW_WRITE(sc, ATW_SYNRF, 0); 1288 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1289 } 1290 } 1291 1292 static int 1293 atw_tune(sc) 1294 struct atw_softc *sc; 1295 { 1296 int rc; 1297 u_int32_t reg; 1298 int chan; 1299 struct ieee80211com *ic = &sc->sc_ic; 1300 1301 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1302 if (chan == IEEE80211_CHAN_ANY) 1303 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1304 1305 if (chan == sc->sc_cur_chan) 1306 return 0; 1307 1308 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1309 sc->sc_cur_chan, chan)); 1310 1311 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1312 1313 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1314 (rc = atw_rf3000_tune(sc, chan)) != 0) 1315 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1316 chan); 1317 1318 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1319 ATW_WRITE(sc, ATW_CAP0, 1320 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1321 1322 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1323 1324 if (rc == 0) 1325 sc->sc_cur_chan = chan; 1326 1327 return rc; 1328 } 1329 1330 #ifdef ATW_DEBUG 1331 static void 1332 atw_si4126_print(sc) 1333 struct atw_softc *sc; 1334 { 1335 struct ifnet *ifp = &sc->sc_ic.ic_if; 1336 u_int addr, val; 1337 1338 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1339 return; 1340 1341 for (addr = 0; addr <= 8; addr++) { 1342 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1343 if (atw_si4126_read(sc, addr, &val) == 0) { 1344 printf("<unknown> (quitting print-out)\n"); 1345 break; 1346 } 1347 printf("%05x\n", val); 1348 } 1349 } 1350 #endif /* ATW_DEBUG */ 1351 1352 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1353 * 1354 * The RF/IF synthesizer produces two reference frequencies for 1355 * the RF2948B transceiver. The first frequency the RF2948B requires 1356 * is two times the so-called "intermediate frequency" (IF). Since 1357 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1358 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1359 * frequency required by the transceiver is the radio frequency 1360 * (RF). This is a superheterodyne transceiver; for f(chan) the 1361 * center frequency of the channel we are tuning, RF = f(chan) - 1362 * IF. 1363 * 1364 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1365 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1366 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1367 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1368 */ 1369 static int 1370 atw_si4126_tune(sc, chan) 1371 struct atw_softc *sc; 1372 u_int8_t chan; 1373 { 1374 int rc = 0; 1375 u_int mhz; 1376 u_int R; 1377 u_int32_t reg; 1378 u_int16_t gain; 1379 1380 #ifdef ATW_DEBUG 1381 atw_si4126_print(sc); 1382 #endif /* ATW_DEBUG */ 1383 1384 if (chan == 14) 1385 mhz = 2484; 1386 else 1387 mhz = 2412 + 5 * (chan - 1); 1388 1389 /* Tune IF to 748MHz to suit the IF LO input of the 1390 * RF2494B, which is 2 x IF. No need to set an IF divider 1391 * because an IF in 526MHz - 952MHz is allowed. 1392 * 1393 * XIN is 44.000MHz, so divide it by two to get allowable 1394 * range of 2-25MHz. SiLabs tells me that this is not 1395 * strictly necessary. 1396 */ 1397 1398 R = 44; 1399 1400 atw_rfio_enable(sc, 1); 1401 1402 /* Power-up RF, IF synthesizers. */ 1403 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1404 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1405 goto out; 1406 1407 /* If RF2 N > 2047, then set KP2 to 1. */ 1408 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1409 1410 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1411 goto out; 1412 1413 /* set LPWR, too? */ 1414 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1415 SI4126_MAIN_XINDIV2)) != 0) 1416 goto out; 1417 1418 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1419 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1420 */ 1421 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1422 goto out; 1423 1424 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1425 goto out; 1426 1427 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1428 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1429 * which has no RF1! 1430 */ 1431 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1432 goto out; 1433 1434 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1435 goto out; 1436 1437 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1438 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1439 * Now let's multiply it to mhz. So mhz - IF = N. 1440 */ 1441 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1442 goto out; 1443 1444 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1445 goto out; 1446 1447 /* wait 100us from power-up for RF, IF to settle */ 1448 DELAY(100); 1449 1450 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1451 /* XXX there is a binary driver which sends 1452 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1453 * that this enables the Si4126 by raising its PWDN#, but I 1454 * think that it actually sets the Prism RF front-end 1455 * to a special mode for channel 14. 1456 */ 1457 reg = ATW_READ(sc, ATW_GPIO); 1458 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1459 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1460 ATW_WRITE(sc, ATW_GPIO, reg); 1461 } 1462 1463 #ifdef ATW_DEBUG 1464 atw_si4126_print(sc); 1465 #endif /* ATW_DEBUG */ 1466 1467 out: 1468 atw_rfio_enable(sc, 0); 1469 1470 return rc; 1471 } 1472 1473 /* Baseline initialization of RF3000 BBP: set CCA mode, enable antenna 1474 * diversity, and write some magic. 1475 * 1476 * Call this w/ Tx/Rx suspended. 1477 */ 1478 static int 1479 atw_rf3000_init(sc) 1480 struct atw_softc *sc; 1481 { 1482 int rc = 0; 1483 1484 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1485 1486 atw_rfio_enable(sc, 1); 1487 1488 /* enable diversity */ 1489 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1490 1491 if (rc != 0) 1492 goto out; 1493 1494 /* sensible setting from a binary-only driver */ 1495 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1496 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 /* magic from a binary-only driver */ 1502 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1503 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1504 1505 if (rc != 0) 1506 goto out; 1507 1508 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1509 1510 if (rc != 0) 1511 goto out; 1512 1513 /* magic derived from binary-only driver */ 1514 rc = atw_rf3000_write(sc, RF3000_MAGIC0, RF3000_MAGIC0_VAL); 1515 1516 if (rc != 0) 1517 goto out; 1518 1519 rc = atw_rf3000_write(sc, RF3000_MAGIC1, RF3000_MAGIC1_VAL); 1520 1521 if (rc != 0) 1522 goto out; 1523 1524 /* CCA is acquisition sensitive */ 1525 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1526 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1527 1528 if (rc != 0) 1529 goto out; 1530 1531 out: 1532 atw_rfio_enable(sc, 0); 1533 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1534 return rc; 1535 } 1536 1537 #ifdef ATW_DEBUG 1538 static void 1539 atw_rf3000_print(sc) 1540 struct atw_softc *sc; 1541 { 1542 struct ifnet *ifp = &sc->sc_ic.ic_if; 1543 u_int addr, val; 1544 1545 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1546 return; 1547 1548 for (addr = 0x01; addr <= 0x15; addr++) { 1549 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1550 if (atw_rf3000_read(sc, addr, &val) != 0) { 1551 printf("<unknown> (quitting print-out)\n"); 1552 break; 1553 } 1554 printf("%08x\n", val); 1555 } 1556 } 1557 #endif /* ATW_DEBUG */ 1558 1559 /* Set the power settings on the BBP for channel `chan'. */ 1560 static int 1561 atw_rf3000_tune(sc, chan) 1562 struct atw_softc *sc; 1563 u_int8_t chan; 1564 { 1565 int rc = 0; 1566 u_int32_t reg; 1567 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1568 1569 atw_rfio_enable(sc, 1); 1570 1571 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1572 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1573 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1574 1575 /* odd channels: LSB, even channels: MSB */ 1576 if (chan % 2 == 1) { 1577 txpower &= 0xFF; 1578 lpf_cutoff &= 0xFF; 1579 lna_gs_thresh &= 0xFF; 1580 } else { 1581 txpower >>= 8; 1582 lpf_cutoff >>= 8; 1583 lna_gs_thresh >>= 8; 1584 } 1585 1586 #ifdef ATW_DEBUG 1587 atw_rf3000_print(sc); 1588 #endif /* ATW_DEBUG */ 1589 1590 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1591 "lna_gs_thresh %02x\n", 1592 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1593 1594 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1595 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1596 goto out; 1597 1598 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1599 goto out; 1600 1601 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1602 goto out; 1603 1604 /* from a binary-only driver. */ 1605 reg = ATW_READ(sc, ATW_PLCPHD); 1606 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1607 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1608 ATW_WRITE(sc, ATW_PLCPHD, reg); 1609 1610 #ifdef ATW_DEBUG 1611 atw_rf3000_print(sc); 1612 #endif /* ATW_DEBUG */ 1613 1614 out: 1615 atw_rfio_enable(sc, 0); 1616 1617 return rc; 1618 } 1619 1620 /* Write a register on the RF3000 baseband processor using the 1621 * registers provided by the ADM8211 for this purpose. 1622 * 1623 * Return 0 on success. 1624 */ 1625 static int 1626 atw_rf3000_write(sc, addr, val) 1627 struct atw_softc *sc; 1628 u_int addr, val; 1629 { 1630 u_int32_t reg; 1631 int i; 1632 1633 for (i = 1000; --i >= 0; ) { 1634 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1635 break; 1636 DELAY(100); 1637 } 1638 1639 if (i < 0) { 1640 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1641 return ETIMEDOUT; 1642 } 1643 1644 reg = sc->sc_bbpctl_wr | 1645 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1646 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1647 1648 ATW_WRITE(sc, ATW_BBPCTL, reg); 1649 1650 for (i = 1000; --i >= 0; ) { 1651 DELAY(100); 1652 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1653 break; 1654 } 1655 1656 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1657 1658 if (i < 0) { 1659 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1660 return ETIMEDOUT; 1661 } 1662 return 0; 1663 } 1664 1665 /* Read a register on the RF3000 baseband processor using the registers 1666 * the ADM8211 provides for this purpose. 1667 * 1668 * The 7-bit register address is addr. Record the 8-bit data in the register 1669 * in *val. 1670 * 1671 * Return 0 on success. 1672 * 1673 * XXX This does not seem to work. The ADM8211 must require more or 1674 * different magic to read the chip than to write it. Possibly some 1675 * of the magic I have derived from a binary-only driver concerns 1676 * the "chip address" (see the RF3000 manual). 1677 */ 1678 #ifdef ATW_DEBUG 1679 static int 1680 atw_rf3000_read(sc, addr, val) 1681 struct atw_softc *sc; 1682 u_int addr, *val; 1683 { 1684 u_int32_t reg; 1685 int i; 1686 1687 for (i = 1000; --i >= 0; ) { 1688 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1689 break; 1690 DELAY(100); 1691 } 1692 1693 if (i < 0) { 1694 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1695 sc->sc_dev.dv_xname); 1696 return ETIMEDOUT; 1697 } 1698 1699 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1700 1701 ATW_WRITE(sc, ATW_BBPCTL, reg); 1702 1703 for (i = 1000; --i >= 0; ) { 1704 DELAY(100); 1705 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1706 break; 1707 } 1708 1709 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1710 1711 if (i < 0) { 1712 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1713 sc->sc_dev.dv_xname, reg); 1714 return ETIMEDOUT; 1715 } 1716 if (val != NULL) 1717 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1718 return 0; 1719 } 1720 #endif /* ATW_DEBUG */ 1721 1722 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1723 * provided by the ADM8211 for that purpose. 1724 * 1725 * val is 18 bits of data, and val is the 4-bit address of the register. 1726 * 1727 * Return 0 on success. 1728 */ 1729 static int 1730 atw_si4126_write(sc, addr, val) 1731 struct atw_softc *sc; 1732 u_int addr, val; 1733 { 1734 u_int32_t reg; 1735 int i; 1736 1737 for (i = 1000; --i >= 0; ) { 1738 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1739 break; 1740 DELAY(100); 1741 } 1742 1743 if (i < 0) { 1744 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1745 sc->sc_dev.dv_xname); 1746 return ETIMEDOUT; 1747 } 1748 1749 reg = sc->sc_synctl_wr | 1750 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1751 1752 ATW_WRITE(sc, ATW_SYNCTL, reg); 1753 1754 for (i = 1000; --i >= 0; ) { 1755 DELAY(100); 1756 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1757 break; 1758 } 1759 1760 /* restore to acceptable starting condition */ 1761 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1762 1763 if (i < 0) { 1764 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1765 sc->sc_dev.dv_xname, reg); 1766 return ETIMEDOUT; 1767 } 1768 return 0; 1769 } 1770 1771 /* Read 18-bit data from the 4-bit address addr in Si4126 1772 * RF synthesizer and write the data to *val. Return 0 on success. 1773 * 1774 * XXX This does not seem to work. The ADM8211 must require more or 1775 * different magic to read the chip than to write it. 1776 */ 1777 #ifdef ATW_DEBUG 1778 static int 1779 atw_si4126_read(sc, addr, val) 1780 struct atw_softc *sc; 1781 u_int addr; 1782 u_int *val; 1783 { 1784 u_int32_t reg; 1785 int i; 1786 1787 for (i = 1000; --i >= 0; ) { 1788 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1789 break; 1790 DELAY(100); 1791 } 1792 1793 if (i < 0) { 1794 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1795 sc->sc_dev.dv_xname); 1796 return ETIMEDOUT; 1797 } 1798 1799 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1800 1801 ATW_WRITE(sc, ATW_SYNCTL, reg); 1802 1803 for (i = 1000; --i >= 0; ) { 1804 DELAY(100); 1805 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1806 break; 1807 } 1808 1809 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1810 1811 if (i < 0) { 1812 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1813 sc->sc_dev.dv_xname, reg); 1814 return ETIMEDOUT; 1815 } 1816 if (val != NULL) 1817 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1818 ATW_SYNCTL_DATA_MASK); 1819 return 0; 1820 } 1821 #endif /* ATW_DEBUG */ 1822 1823 /* XXX is the endianness correct? test. */ 1824 #define atw_calchash(addr) \ 1825 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1826 1827 /* 1828 * atw_filter_setup: 1829 * 1830 * Set the ADM8211's receive filter. 1831 */ 1832 static void 1833 atw_filter_setup(sc) 1834 struct atw_softc *sc; 1835 { 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ethercom *ec = &ic->ic_ec; 1838 struct ifnet *ifp = &sc->sc_ic.ic_if; 1839 int hash; 1840 u_int32_t hashes[2] = { 0, 0 }; 1841 struct ether_multi *enm; 1842 struct ether_multistep step; 1843 1844 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1845 sc->sc_dev.dv_xname, sc->sc_flags)); 1846 1847 /* 1848 * If we're running, idle the receive engine. If we're NOT running, 1849 * we're being called from atw_init(), and our writing ATW_NAR will 1850 * start the transmit and receive processes in motion. 1851 */ 1852 if (ifp->if_flags & IFF_RUNNING) 1853 atw_idle(sc, ATW_NAR_SR); 1854 1855 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1856 1857 ifp->if_flags &= ~IFF_ALLMULTI; 1858 1859 if (ifp->if_flags & IFF_PROMISC) { 1860 sc->sc_opmode |= ATW_NAR_PR; 1861 allmulti: 1862 ifp->if_flags |= IFF_ALLMULTI; 1863 goto setit; 1864 } 1865 1866 /* 1867 * Program the 64-bit multicast hash filter. 1868 */ 1869 ETHER_FIRST_MULTI(step, ec, enm); 1870 while (enm != NULL) { 1871 /* XXX */ 1872 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1873 ETHER_ADDR_LEN) != 0) 1874 goto allmulti; 1875 1876 hash = atw_calchash(enm->enm_addrlo); 1877 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1878 ETHER_NEXT_MULTI(step, enm); 1879 } 1880 1881 if (ifp->if_flags & IFF_BROADCAST) { 1882 hash = atw_calchash(etherbroadcastaddr); 1883 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1884 } 1885 1886 /* all bits set => hash is useless */ 1887 if (~(hashes[0] & hashes[1]) == 0) 1888 goto allmulti; 1889 1890 setit: 1891 if (ifp->if_flags & IFF_ALLMULTI) 1892 sc->sc_opmode |= ATW_NAR_MM; 1893 1894 /* XXX in scan mode, do not filter packets. maybe this is 1895 * unnecessary. 1896 */ 1897 if (ic->ic_state == IEEE80211_S_SCAN) 1898 sc->sc_opmode |= ATW_NAR_PR; 1899 1900 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1901 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1902 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1903 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1904 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1905 1906 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1907 } 1908 1909 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1910 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1911 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1912 * no beacon with the preferred BSSID and SSID in the number of 1913 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1914 */ 1915 static void 1916 atw_write_bssid(sc) 1917 struct atw_softc *sc; 1918 { 1919 struct ieee80211com *ic = &sc->sc_ic; 1920 u_int8_t *bssid; 1921 1922 bssid = ic->ic_bss->ni_bssid; 1923 1924 ATW_WRITE(sc, ATW_ABDA1, 1925 (ATW_READ(sc, ATW_ABDA1) & 1926 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1927 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1928 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1929 1930 ATW_WRITE(sc, ATW_BSSID0, 1931 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1932 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1933 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1934 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1935 1936 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1937 ether_sprintf(sc->sc_bssid))); 1938 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1939 1940 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1941 } 1942 1943 /* Tell the ADM8211 how many beacon intervals must pass without 1944 * receiving a beacon with the preferred BSSID & SSID set by 1945 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1946 * raised. 1947 */ 1948 static void 1949 atw_write_bcn_thresh(sc) 1950 struct atw_softc *sc; 1951 { 1952 struct ieee80211com *ic = &sc->sc_ic; 1953 int lost_bcn_thresh; 1954 1955 /* Lose link after one second or 7 beacons, whichever comes 1956 * first, but do not lose link before 2 beacons are lost. 1957 * 1958 * In host AP mode, set the lost-beacon threshold to 0. 1959 */ 1960 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1961 lost_bcn_thresh = 0; 1962 else 1963 lost_bcn_thresh = MAX(2, 1964 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss->ni_intval), 7)); 1965 1966 /* XXX resets wake-up status bits */ 1967 ATW_WRITE(sc, ATW_WCSR, 1968 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1969 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1970 1971 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1972 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1973 1974 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1975 1976 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1977 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1978 } 1979 1980 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1981 * 16-bit word. 1982 */ 1983 static void 1984 atw_write_sram(sc, ofs, buf, buflen) 1985 struct atw_softc *sc; 1986 u_int ofs; 1987 u_int8_t *buf; 1988 u_int buflen; 1989 { 1990 u_int i; 1991 u_int8_t *ptr; 1992 1993 memcpy(&sc->sc_sram[ofs], buf, buflen); 1994 1995 if (ofs % 2 != 0) { 1996 ofs--; 1997 buflen++; 1998 } 1999 2000 if (buflen % 2 != 0) 2001 buflen++; 2002 2003 assert(buflen + ofs <= ATW_SRAM_SIZE); 2004 2005 ptr = &sc->sc_sram[ofs]; 2006 2007 for (i = 0; i < buflen; i += 2) { 2008 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2009 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2010 DELAY(atw_writewep_delay); 2011 2012 ATW_WRITE(sc, ATW_WESK, 2013 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2014 DELAY(atw_writewep_delay); 2015 } 2016 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2017 2018 if (sc->sc_if.if_flags & IFF_DEBUG) { 2019 int n_octets = 0; 2020 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2021 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2022 for (i = 0; i < buflen; i++) { 2023 printf(" %02x", ptr[i]); 2024 if (++n_octets % 24 == 0) 2025 printf("\n"); 2026 } 2027 if (n_octets % 24 != 0) 2028 printf("\n"); 2029 } 2030 } 2031 2032 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2033 static void 2034 atw_write_wep(sc) 2035 struct atw_softc *sc; 2036 { 2037 struct ieee80211com *ic = &sc->sc_ic; 2038 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2039 u_int8_t buf[IEEE80211_WEP_NKID] 2040 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2041 u_int32_t reg; 2042 int i; 2043 2044 sc->sc_wepctl = 0; 2045 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2046 2047 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2048 return; 2049 2050 memset(&buf[0][0], 0, sizeof(buf)); 2051 2052 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2053 if (ic->ic_nw_keys[i].wk_len > 5) { 2054 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2055 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2056 buf[i][1] = ATW_WEP_ENABLED; 2057 } else { 2058 buf[i][1] = 0; 2059 continue; 2060 } 2061 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2062 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2063 ic->ic_nw_keys[i].wk_len - 1); 2064 } 2065 2066 reg = ATW_READ(sc, ATW_MACTEST); 2067 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2068 reg &= ~ATW_MACTEST_KEYID_MASK; 2069 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2070 ATW_WRITE(sc, ATW_MACTEST, reg); 2071 2072 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2073 * throughout.) 2074 */ 2075 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2076 if (sc->sc_if.if_flags & IFF_LINK2) 2077 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2078 2079 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2080 sizeof(buf)); 2081 } 2082 2083 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2084 2085 static void 2086 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2087 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2088 { 2089 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2090 2091 switch (subtype) { 2092 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2093 /* do nothing: hardware answers probe request */ 2094 break; 2095 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2096 case IEEE80211_FC0_SUBTYPE_BEACON: 2097 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2098 break; 2099 default: 2100 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2101 break; 2102 } 2103 return; 2104 } 2105 2106 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2107 * of IBSSs with like SSID/channel but different BSSID. It joins the 2108 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2109 * convention. Possibly the ADMtek chip does this for us; I will have 2110 * to test to find out. 2111 * 2112 * XXX we should add the duration field of the received beacon to 2113 * the TSF time it contains before comparing it with the ADM8211's 2114 * TSF. 2115 */ 2116 static void 2117 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2118 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2119 { 2120 struct atw_softc *sc; 2121 struct ieee80211_frame *wh; 2122 u_int64_t tsft, bcn_tsft; 2123 u_int32_t tsftl, tsfth; 2124 int do_print = 0; 2125 2126 sc = (struct atw_softc*)ic->ic_if.if_softc; 2127 2128 if (ic->ic_if.if_flags & IFF_DEBUG) 2129 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2130 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2131 2132 wh = mtod(m0, struct ieee80211_frame *); 2133 2134 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2135 2136 if (ic->ic_state != IEEE80211_S_RUN) { 2137 if (do_print) 2138 printf("%s: atw_recv_beacon: not running\n", 2139 sc->sc_dev.dv_xname); 2140 return; 2141 } 2142 2143 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2144 ic->ic_bss->ni_chan)) == NULL) { 2145 if (do_print) 2146 printf("%s: atw_recv_beacon: no node %s\n", 2147 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2148 return; 2149 } 2150 2151 if (ieee80211_match_bss(ic, ni) != 0) { 2152 if (do_print) 2153 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2154 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2155 return; 2156 } 2157 2158 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2159 return; 2160 2161 if (do_print) 2162 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2163 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2164 2165 if (ic->ic_opmode != IEEE80211_M_IBSS) 2166 return; 2167 2168 /* If we read TSFTL right before rollover, we read a TSF timer 2169 * that is too high rather than too low. This prevents a spurious 2170 * synchronization down the line, however, our IBSS could suffer 2171 * from a creeping TSF.... 2172 */ 2173 tsftl = ATW_READ(sc, ATW_TSFTL); 2174 tsfth = ATW_READ(sc, ATW_TSFTH); 2175 2176 tsft = (u_int64_t)tsfth << 32 | tsftl; 2177 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2178 2179 if (do_print) 2180 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2181 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2182 2183 /* we are faster, let the other guy catch up */ 2184 if (bcn_tsft < tsft) 2185 return; 2186 2187 if (do_print) 2188 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2189 ether_sprintf(wh->i_addr2)); 2190 2191 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2192 2193 #if 0 2194 atw_tsf(sc); 2195 #endif 2196 2197 /* negotiate rates with new IBSS */ 2198 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2199 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2200 if (ni->ni_rates.rs_nrates == 0) { 2201 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2202 ether_sprintf(ni->ni_bssid)); 2203 return; 2204 } 2205 2206 if (do_print) { 2207 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2208 ether_sprintf(ic->ic_bss->ni_bssid)); 2209 printf("%s ", ether_sprintf(ni->ni_bssid)); 2210 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2211 } 2212 2213 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2214 2215 atw_write_bssid(sc); 2216 atw_write_bcn_thresh(sc); 2217 atw_start_beacon(sc, 1); 2218 } 2219 2220 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2221 * In ad hoc mode, the SSID is written to the beacons sent by the 2222 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2223 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2224 * indications. 2225 */ 2226 static void 2227 atw_write_ssid(sc) 2228 struct atw_softc *sc; 2229 { 2230 struct ieee80211com *ic = &sc->sc_ic; 2231 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2232 u_int8_t buf[1 /* length */ + IEEE80211_NWID_LEN + 2233 1 /* for a round number */]; 2234 2235 memset(buf, 0, sizeof(buf)); 2236 buf[0] = ic->ic_bss->ni_esslen; 2237 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2238 2239 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2240 } 2241 2242 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2243 * In ad hoc mode, the supported rates are written to beacons sent by the 2244 * ADM8211. 2245 */ 2246 static void 2247 atw_write_sup_rates(sc) 2248 struct atw_softc *sc; 2249 { 2250 struct ieee80211com *ic = &sc->sc_ic; 2251 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2252 * supported rates 2253 */ 2254 u_int8_t buf[1 /* length */ + IEEE80211_RATE_SIZE + 2255 1 /* for a round number */]; 2256 2257 memset(buf, 0, sizeof(buf)); 2258 2259 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2260 2261 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2262 ic->ic_bss->ni_rates.rs_nrates); 2263 2264 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2265 } 2266 2267 /* Start/stop sending beacons. */ 2268 void 2269 atw_start_beacon(struct atw_softc *sc, int start) 2270 { 2271 struct ieee80211com *ic = &sc->sc_ic; 2272 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2273 2274 if (ATW_IS_ENABLED(sc) == 0) 2275 return; 2276 2277 len = capinfo = 0; 2278 2279 /* start beacons */ 2280 len = sizeof(struct ieee80211_frame) + 2281 8 /* timestamp */ + 2 /* beacon interval */ + 2282 2 /* capability info */ + 2283 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2284 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2285 3 /* DS parameters */ + 2286 IEEE80211_CRC_LEN; 2287 2288 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2289 2290 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2291 2292 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2293 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2294 2295 if (!start) 2296 return; 2297 2298 /* TBD use ni_capinfo */ 2299 2300 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2301 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2302 if (ic->ic_flags & IEEE80211_F_WEPON) 2303 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2304 2305 switch (ic->ic_opmode) { 2306 case IEEE80211_M_IBSS: 2307 len += 4; /* IBSS parameters */ 2308 capinfo |= IEEE80211_CAPINFO_IBSS; 2309 break; 2310 case IEEE80211_M_HOSTAP: 2311 /* XXX 6-byte minimum TIM */ 2312 len += atw_beacon_len_adjust; 2313 capinfo |= IEEE80211_CAPINFO_ESS; 2314 break; 2315 default: 2316 return; 2317 } 2318 2319 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2320 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2321 2322 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2323 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2324 2325 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2326 sc->sc_dev.dv_xname, reg_bcnt)); 2327 2328 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2329 sc->sc_dev.dv_xname, reg_cap1)); 2330 } 2331 2332 /* First beacon was sent at time 0 microseconds, current time is 2333 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2334 * microseconds. Return the expected time in microseconds for the 2335 * beacon after next. 2336 */ 2337 static __inline u_int64_t 2338 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2339 { 2340 return tsft + (tbtt - tsft % tbtt); 2341 } 2342 2343 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2344 * the ieee80211com. 2345 * 2346 * Predict the next target beacon transmission time (TBTT) and 2347 * write it to the ADM8211. 2348 */ 2349 static void 2350 atw_tsf(struct atw_softc *sc) 2351 { 2352 #define TBTTOFS 20 /* TU */ 2353 2354 struct ieee80211com *ic = &sc->sc_ic; 2355 u_int64_t tsft, tbtt; 2356 2357 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2358 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2359 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2360 tsft = ATW_READ(sc, ATW_TSFTH); 2361 tsft <<= 32; 2362 tsft |= ATW_READ(sc, ATW_TSFTL); 2363 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2364 } else 2365 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2366 2367 tbtt = atw_predict_beacon(tsft, 2368 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2369 2370 /* skip one more beacon so that the TBTT cannot pass before 2371 * we've programmed it, and also so that we can subtract a 2372 * few TU so that we wake a little before TBTT. 2373 */ 2374 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2375 2376 /* wake up a little early */ 2377 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2378 2379 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2380 sc->sc_dev.dv_xname, tsft, tbtt)); 2381 2382 ATW_WRITE(sc, ATW_TOFS1, 2383 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2384 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2385 LSHIFT( 2386 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2387 ATW_TOFS1_TBTTPRE_MASK)); 2388 #undef TBTTOFS 2389 } 2390 2391 static void 2392 atw_next_scan(void *arg) 2393 { 2394 struct atw_softc *sc = arg; 2395 struct ieee80211com *ic = &sc->sc_ic; 2396 struct ifnet *ifp = &ic->ic_if; 2397 int s; 2398 2399 /* don't call atw_start w/o network interrupts blocked */ 2400 s = splnet(); 2401 if (ic->ic_state == IEEE80211_S_SCAN) 2402 ieee80211_next_scan(ifp); 2403 splx(s); 2404 } 2405 2406 /* Synchronize the hardware state with the software state. */ 2407 static int 2408 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2409 { 2410 struct ifnet *ifp = &ic->ic_if; 2411 struct atw_softc *sc = ifp->if_softc; 2412 enum ieee80211_state ostate; 2413 int error; 2414 2415 ostate = ic->ic_state; 2416 2417 if (nstate == IEEE80211_S_INIT) { 2418 callout_stop(&sc->sc_scan_ch); 2419 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2420 atw_start_beacon(sc, 0); 2421 return (*sc->sc_newstate)(ic, nstate, arg); 2422 } 2423 2424 if ((error = atw_tune(sc)) != 0) 2425 return error; 2426 2427 switch (nstate) { 2428 case IEEE80211_S_ASSOC: 2429 break; 2430 case IEEE80211_S_INIT: 2431 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2432 break; 2433 case IEEE80211_S_SCAN: 2434 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2435 atw_write_bssid(sc); 2436 2437 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2438 atw_next_scan, sc); 2439 2440 break; 2441 case IEEE80211_S_RUN: 2442 if (ic->ic_opmode == IEEE80211_M_STA) 2443 break; 2444 /*FALLTHROUGH*/ 2445 case IEEE80211_S_AUTH: 2446 atw_write_bssid(sc); 2447 atw_write_bcn_thresh(sc); 2448 atw_write_ssid(sc); 2449 atw_write_sup_rates(sc); 2450 2451 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2452 ic->ic_opmode == IEEE80211_M_MONITOR) 2453 break; 2454 2455 /* set listen interval 2456 * XXX do software units agree w/ hardware? 2457 */ 2458 ATW_WRITE(sc, ATW_BPLI, 2459 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2460 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2461 ATW_BPLI_LI_MASK)); 2462 2463 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2464 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2465 2466 atw_tsf(sc); 2467 break; 2468 } 2469 2470 if (nstate != IEEE80211_S_SCAN) 2471 callout_stop(&sc->sc_scan_ch); 2472 2473 if (nstate == IEEE80211_S_RUN && 2474 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2475 ic->ic_opmode == IEEE80211_M_IBSS)) 2476 atw_start_beacon(sc, 1); 2477 else 2478 atw_start_beacon(sc, 0); 2479 2480 return (*sc->sc_newstate)(ic, nstate, arg); 2481 } 2482 2483 /* 2484 * atw_add_rxbuf: 2485 * 2486 * Add a receive buffer to the indicated descriptor. 2487 */ 2488 int 2489 atw_add_rxbuf(sc, idx) 2490 struct atw_softc *sc; 2491 int idx; 2492 { 2493 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2494 struct mbuf *m; 2495 int error; 2496 2497 MGETHDR(m, M_DONTWAIT, MT_DATA); 2498 if (m == NULL) 2499 return (ENOBUFS); 2500 2501 MCLGET(m, M_DONTWAIT); 2502 if ((m->m_flags & M_EXT) == 0) { 2503 m_freem(m); 2504 return (ENOBUFS); 2505 } 2506 2507 if (rxs->rxs_mbuf != NULL) 2508 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2509 2510 rxs->rxs_mbuf = m; 2511 2512 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2513 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2514 BUS_DMA_READ|BUS_DMA_NOWAIT); 2515 if (error) { 2516 printf("%s: can't load rx DMA map %d, error = %d\n", 2517 sc->sc_dev.dv_xname, idx, error); 2518 panic("atw_add_rxbuf"); /* XXX */ 2519 } 2520 2521 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2522 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2523 2524 ATW_INIT_RXDESC(sc, idx); 2525 2526 return (0); 2527 } 2528 2529 /* 2530 * atw_stop: [ ifnet interface function ] 2531 * 2532 * Stop transmission on the interface. 2533 */ 2534 void 2535 atw_stop(ifp, disable) 2536 struct ifnet *ifp; 2537 int disable; 2538 { 2539 struct atw_softc *sc = ifp->if_softc; 2540 struct ieee80211com *ic = &sc->sc_ic; 2541 struct atw_txsoft *txs; 2542 2543 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2544 2545 /* Disable interrupts. */ 2546 ATW_WRITE(sc, ATW_IER, 0); 2547 2548 /* Stop the transmit and receive processes. */ 2549 sc->sc_opmode = 0; 2550 ATW_WRITE(sc, ATW_NAR, 0); 2551 ATW_WRITE(sc, ATW_TDBD, 0); 2552 ATW_WRITE(sc, ATW_TDBP, 0); 2553 ATW_WRITE(sc, ATW_RDB, 0); 2554 2555 /* 2556 * Release any queued transmit buffers. 2557 */ 2558 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2559 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2560 if (txs->txs_mbuf != NULL) { 2561 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2562 m_freem(txs->txs_mbuf); 2563 txs->txs_mbuf = NULL; 2564 } 2565 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2566 } 2567 2568 if (disable) { 2569 atw_rxdrain(sc); 2570 atw_disable(sc); 2571 } 2572 2573 /* 2574 * Mark the interface down and cancel the watchdog timer. 2575 */ 2576 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2577 ifp->if_timer = 0; 2578 2579 /* XXX */ 2580 atw_reset(sc); 2581 } 2582 2583 /* 2584 * atw_rxdrain: 2585 * 2586 * Drain the receive queue. 2587 */ 2588 void 2589 atw_rxdrain(sc) 2590 struct atw_softc *sc; 2591 { 2592 struct atw_rxsoft *rxs; 2593 int i; 2594 2595 for (i = 0; i < ATW_NRXDESC; i++) { 2596 rxs = &sc->sc_rxsoft[i]; 2597 if (rxs->rxs_mbuf == NULL) 2598 continue; 2599 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2600 m_freem(rxs->rxs_mbuf); 2601 rxs->rxs_mbuf = NULL; 2602 } 2603 } 2604 2605 /* 2606 * atw_detach: 2607 * 2608 * Detach an ADM8211 interface. 2609 */ 2610 int 2611 atw_detach(sc) 2612 struct atw_softc *sc; 2613 { 2614 struct ifnet *ifp = &sc->sc_ic.ic_if; 2615 struct atw_rxsoft *rxs; 2616 struct atw_txsoft *txs; 2617 int i; 2618 2619 /* 2620 * Succeed now if there isn't any work to do. 2621 */ 2622 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2623 return (0); 2624 2625 ieee80211_ifdetach(ifp); 2626 if_detach(ifp); 2627 2628 for (i = 0; i < ATW_NRXDESC; i++) { 2629 rxs = &sc->sc_rxsoft[i]; 2630 if (rxs->rxs_mbuf != NULL) { 2631 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2632 m_freem(rxs->rxs_mbuf); 2633 rxs->rxs_mbuf = NULL; 2634 } 2635 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2636 } 2637 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2638 txs = &sc->sc_txsoft[i]; 2639 if (txs->txs_mbuf != NULL) { 2640 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2641 m_freem(txs->txs_mbuf); 2642 txs->txs_mbuf = NULL; 2643 } 2644 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2645 } 2646 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2647 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2648 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2649 sizeof(struct atw_control_data)); 2650 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2651 2652 shutdownhook_disestablish(sc->sc_sdhook); 2653 powerhook_disestablish(sc->sc_powerhook); 2654 2655 if (sc->sc_srom) 2656 free(sc->sc_srom, M_DEVBUF); 2657 2658 return (0); 2659 } 2660 2661 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2662 void 2663 atw_shutdown(arg) 2664 void *arg; 2665 { 2666 struct atw_softc *sc = arg; 2667 2668 atw_stop(&sc->sc_ic.ic_if, 1); 2669 } 2670 2671 int 2672 atw_intr(arg) 2673 void *arg; 2674 { 2675 struct atw_softc *sc = arg; 2676 struct ifnet *ifp = &sc->sc_ic.ic_if; 2677 u_int32_t status, rxstatus, txstatus, linkstatus; 2678 int handled = 0, txthresh; 2679 2680 #ifdef DEBUG 2681 if (ATW_IS_ENABLED(sc) == 0) 2682 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2683 #endif 2684 2685 /* 2686 * If the interface isn't running, the interrupt couldn't 2687 * possibly have come from us. 2688 */ 2689 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2690 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2691 return (0); 2692 2693 for (;;) { 2694 status = ATW_READ(sc, ATW_STSR); 2695 2696 if (status) 2697 ATW_WRITE(sc, ATW_STSR, status); 2698 2699 if (sc->sc_intr_ack != NULL) 2700 (*sc->sc_intr_ack)(sc); 2701 2702 #ifdef ATW_DEBUG 2703 #define PRINTINTR(flag) do { \ 2704 if ((status & flag) != 0) { \ 2705 printf("%s" #flag, delim); \ 2706 delim = ","; \ 2707 } \ 2708 } while (0) 2709 2710 if (atw_debug > 1 && status) { 2711 const char *delim = "<"; 2712 2713 printf("%s: reg[STSR] = %x", 2714 sc->sc_dev.dv_xname, status); 2715 2716 PRINTINTR(ATW_INTR_FBE); 2717 PRINTINTR(ATW_INTR_LINKOFF); 2718 PRINTINTR(ATW_INTR_LINKON); 2719 PRINTINTR(ATW_INTR_RCI); 2720 PRINTINTR(ATW_INTR_RDU); 2721 PRINTINTR(ATW_INTR_RPS); 2722 PRINTINTR(ATW_INTR_TCI); 2723 PRINTINTR(ATW_INTR_TDU); 2724 PRINTINTR(ATW_INTR_TLT); 2725 PRINTINTR(ATW_INTR_TPS); 2726 PRINTINTR(ATW_INTR_TRT); 2727 PRINTINTR(ATW_INTR_TUF); 2728 PRINTINTR(ATW_INTR_BCNTC); 2729 PRINTINTR(ATW_INTR_ATIME); 2730 PRINTINTR(ATW_INTR_TBTT); 2731 PRINTINTR(ATW_INTR_TSCZ); 2732 PRINTINTR(ATW_INTR_TSFTF); 2733 printf(">\n"); 2734 } 2735 #undef PRINTINTR 2736 #endif /* ATW_DEBUG */ 2737 2738 if ((status & sc->sc_inten) == 0) 2739 break; 2740 2741 handled = 1; 2742 2743 rxstatus = status & sc->sc_rxint_mask; 2744 txstatus = status & sc->sc_txint_mask; 2745 linkstatus = status & sc->sc_linkint_mask; 2746 2747 if (linkstatus) { 2748 atw_linkintr(sc, linkstatus); 2749 } 2750 2751 if (rxstatus) { 2752 /* Grab any new packets. */ 2753 atw_rxintr(sc); 2754 2755 if (rxstatus & ATW_INTR_RDU) { 2756 printf("%s: receive ring overrun\n", 2757 sc->sc_dev.dv_xname); 2758 /* Get the receive process going again. */ 2759 ATW_WRITE(sc, ATW_RDR, 0x1); 2760 break; 2761 } 2762 } 2763 2764 if (txstatus) { 2765 /* Sweep up transmit descriptors. */ 2766 atw_txintr(sc); 2767 2768 if (txstatus & ATW_INTR_TLT) 2769 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2770 sc->sc_dev.dv_xname)); 2771 2772 if (txstatus & ATW_INTR_TRT) 2773 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2774 sc->sc_dev.dv_xname)); 2775 2776 /* If Tx under-run, increase our transmit threshold 2777 * if another is available. 2778 */ 2779 txthresh = sc->sc_txthresh + 1; 2780 if ((txstatus & ATW_INTR_TUF) && 2781 sc->sc_txth[txthresh].txth_name != NULL) { 2782 /* Idle the transmit process. */ 2783 atw_idle(sc, ATW_NAR_ST); 2784 2785 sc->sc_txthresh = txthresh; 2786 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2787 sc->sc_opmode |= 2788 sc->sc_txth[txthresh].txth_opmode; 2789 printf("%s: transmit underrun; new " 2790 "threshold: %s\n", sc->sc_dev.dv_xname, 2791 sc->sc_txth[txthresh].txth_name); 2792 2793 /* Set the new threshold and restart 2794 * the transmit process. 2795 */ 2796 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2797 /* XXX Log every Nth underrun from 2798 * XXX now on? 2799 */ 2800 } 2801 } 2802 2803 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2804 if (status & ATW_INTR_TPS) 2805 printf("%s: transmit process stopped\n", 2806 sc->sc_dev.dv_xname); 2807 if (status & ATW_INTR_RPS) 2808 printf("%s: receive process stopped\n", 2809 sc->sc_dev.dv_xname); 2810 (void)atw_init(ifp); 2811 break; 2812 } 2813 2814 if (status & ATW_INTR_FBE) { 2815 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2816 (void)atw_init(ifp); 2817 break; 2818 } 2819 2820 /* 2821 * Not handled: 2822 * 2823 * Transmit buffer unavailable -- normal 2824 * condition, nothing to do, really. 2825 * 2826 * Early receive interrupt -- not available on 2827 * all chips, we just use RI. We also only 2828 * use single-segment receive DMA, so this 2829 * is mostly useless. 2830 * 2831 * TBD others 2832 */ 2833 } 2834 2835 /* Try to get more packets going. */ 2836 atw_start(ifp); 2837 2838 return (handled); 2839 } 2840 2841 /* 2842 * atw_idle: 2843 * 2844 * Cause the transmit and/or receive processes to go idle. 2845 * 2846 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2847 * process in STSR if I clear SR or ST after the process has already 2848 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2849 * do not seem to be too reliable. Perhaps I have the sense of the 2850 * Rx bits switched with the Tx bits? 2851 */ 2852 void 2853 atw_idle(sc, bits) 2854 struct atw_softc *sc; 2855 u_int32_t bits; 2856 { 2857 u_int32_t ackmask = 0, opmode, stsr, test0; 2858 int i, s; 2859 2860 /* without this, somehow we run concurrently w/ interrupt handler */ 2861 s = splnet(); 2862 2863 opmode = sc->sc_opmode & ~bits; 2864 2865 if (bits & ATW_NAR_SR) 2866 ackmask |= ATW_INTR_RPS; 2867 2868 if (bits & ATW_NAR_ST) { 2869 ackmask |= ATW_INTR_TPS; 2870 /* set ATW_NAR_HF to flush TX FIFO. */ 2871 opmode |= ATW_NAR_HF; 2872 } 2873 2874 ATW_WRITE(sc, ATW_NAR, opmode); 2875 2876 for (i = 0; i < 1000; i++) { 2877 stsr = ATW_READ(sc, ATW_STSR); 2878 if ((stsr & ackmask) == ackmask) 2879 break; 2880 DELAY(10); 2881 } 2882 2883 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2884 2885 if ((stsr & ackmask) == ackmask) 2886 goto out; 2887 2888 test0 = ATW_READ(sc, ATW_TEST0); 2889 2890 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2891 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2892 printf("%s: transmit process not idle [%s]\n", 2893 sc->sc_dev.dv_xname, 2894 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2895 printf("%s: bits %08x test0 %08x stsr %08x\n", 2896 sc->sc_dev.dv_xname, bits, test0, stsr); 2897 } 2898 2899 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2900 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2901 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2902 sc->sc_dev.dv_xname, 2903 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2904 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2905 sc->sc_dev.dv_xname, bits, test0, stsr)); 2906 } 2907 out: 2908 splx(s); 2909 return; 2910 } 2911 2912 /* 2913 * atw_linkintr: 2914 * 2915 * Helper; handle link-status interrupts. 2916 */ 2917 void 2918 atw_linkintr(sc, linkstatus) 2919 struct atw_softc *sc; 2920 u_int32_t linkstatus; 2921 { 2922 struct ieee80211com *ic = &sc->sc_ic; 2923 2924 if (ic->ic_state != IEEE80211_S_RUN) 2925 return; 2926 2927 if (linkstatus & ATW_INTR_LINKON) { 2928 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2929 sc->sc_rescan_timer = 0; 2930 } else if (linkstatus & ATW_INTR_LINKOFF) { 2931 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2932 switch (ic->ic_opmode) { 2933 case IEEE80211_M_IBSS: 2934 if (ic->ic_flags & IEEE80211_F_SIBSS) 2935 return; 2936 /* FALL THROUGH */ 2937 case IEEE80211_M_STA: 2938 sc->sc_rescan_timer = 3; 2939 ic->ic_if.if_timer = 1; 2940 break; 2941 default: 2942 break; 2943 } 2944 } 2945 } 2946 2947 /* 2948 * atw_rxintr: 2949 * 2950 * Helper; handle receive interrupts. 2951 */ 2952 void 2953 atw_rxintr(sc) 2954 struct atw_softc *sc; 2955 { 2956 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2957 struct ieee80211com *ic = &sc->sc_ic; 2958 struct ieee80211_node *ni; 2959 struct ieee80211_frame *wh; 2960 struct ifnet *ifp = &ic->ic_if; 2961 struct atw_rxsoft *rxs; 2962 struct mbuf *m; 2963 u_int32_t rxstat; 2964 int i, len, rate, rate0, rssi; 2965 2966 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2967 rxs = &sc->sc_rxsoft[i]; 2968 2969 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2970 2971 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2972 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2973 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2974 2975 if (rxstat & ATW_RXSTAT_OWN) 2976 break; /* We have processed all receive buffers. */ 2977 2978 ATW_DPRINTF3(("%s: rssi %d\n", sc->sc_dev.dv_xname, rssi)); 2979 2980 /* 2981 * Make sure the packet fit in one buffer. This should 2982 * always be the case. 2983 */ 2984 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2985 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2986 printf("%s: incoming packet spilled, resetting\n", 2987 sc->sc_dev.dv_xname); 2988 (void)atw_init(ifp); 2989 return; 2990 } 2991 2992 /* 2993 * If an error occurred, update stats, clear the status 2994 * word, and leave the packet buffer in place. It will 2995 * simply be reused the next time the ring comes around. 2996 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2997 * error. 2998 */ 2999 3000 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3001 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3002 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3003 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3004 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3005 ATW_RXSTAT_ICVE)) != 0)) { 3006 #define PRINTERR(bit, str) \ 3007 if (rxstat & (bit)) \ 3008 printf("%s: receive error: %s\n", \ 3009 sc->sc_dev.dv_xname, str) 3010 ifp->if_ierrors++; 3011 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3012 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3013 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3014 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3015 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3016 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3017 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3018 #undef PRINTERR 3019 ATW_INIT_RXDESC(sc, i); 3020 continue; 3021 } 3022 3023 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3024 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3025 3026 /* 3027 * No errors; receive the packet. Note the ADM8211 3028 * includes the CRC in promiscuous mode. 3029 */ 3030 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3031 3032 /* 3033 * Allocate a new mbuf cluster. If that fails, we are 3034 * out of memory, and must drop the packet and recycle 3035 * the buffer that's already attached to this descriptor. 3036 */ 3037 m = rxs->rxs_mbuf; 3038 if (atw_add_rxbuf(sc, i) != 0) { 3039 ifp->if_ierrors++; 3040 ATW_INIT_RXDESC(sc, i); 3041 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3042 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3043 continue; 3044 } 3045 3046 ifp->if_ipackets++; 3047 if (sc->sc_opmode & ATW_NAR_PR) 3048 m->m_flags |= M_HASFCS; 3049 m->m_pkthdr.rcvif = ifp; 3050 m->m_pkthdr.len = m->m_len = len; 3051 3052 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3053 rate = 0; 3054 else 3055 rate = rate_tbl[rate0]; 3056 3057 #if NBPFILTER > 0 3058 /* Pass this up to any BPF listeners. */ 3059 if (sc->sc_radiobpf != NULL) { 3060 struct mbuf mb; 3061 3062 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3063 3064 tap->ar_rate = rate; 3065 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3066 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3067 3068 /* TBD verify units are dB */ 3069 tap->ar_antsignal = rssi; 3070 /* TBD tap->ar_flags */ 3071 3072 M_COPY_PKTHDR(&mb, m); 3073 mb.m_data = (caddr_t)tap; 3074 mb.m_len = tap->ar_ihdr.it_len; 3075 mb.m_next = m; 3076 mb.m_pkthdr.len += mb.m_len; 3077 bpf_mtap(sc->sc_radiobpf, &mb); 3078 } 3079 #endif /* NPBFILTER > 0 */ 3080 3081 wh = mtod(m, struct ieee80211_frame *); 3082 ni = ieee80211_find_rxnode(ic, wh); 3083 ieee80211_input(ifp, m, ni, rssi, 0); 3084 /* 3085 * The frame may have caused the node to be marked for 3086 * reclamation (e.g. in response to a DEAUTH message) 3087 * so use free_node here instead of unref_node. 3088 */ 3089 if (ni == ic->ic_bss) 3090 ieee80211_unref_node(&ni); 3091 else 3092 ieee80211_free_node(ic, ni); 3093 } 3094 3095 /* Update the receive pointer. */ 3096 sc->sc_rxptr = i; 3097 } 3098 3099 /* 3100 * atw_txintr: 3101 * 3102 * Helper; handle transmit interrupts. 3103 */ 3104 void 3105 atw_txintr(sc) 3106 struct atw_softc *sc; 3107 { 3108 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3109 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3110 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3111 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3112 3113 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3114 struct ifnet *ifp = &sc->sc_ic.ic_if; 3115 struct atw_txsoft *txs; 3116 u_int32_t txstat; 3117 3118 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3119 sc->sc_dev.dv_xname, sc->sc_flags)); 3120 3121 ifp->if_flags &= ~IFF_OACTIVE; 3122 3123 /* 3124 * Go through our Tx list and free mbufs for those 3125 * frames that have been transmitted. 3126 */ 3127 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3128 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3129 txs->txs_ndescs, 3130 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3131 3132 #ifdef ATW_DEBUG 3133 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3134 int i; 3135 printf(" txsoft %p transmit chain:\n", txs); 3136 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3137 printf(" descriptor %d:\n", i); 3138 printf(" at_status: 0x%08x\n", 3139 le32toh(sc->sc_txdescs[i].at_stat)); 3140 printf(" at_flags: 0x%08x\n", 3141 le32toh(sc->sc_txdescs[i].at_flags)); 3142 printf(" at_buf1: 0x%08x\n", 3143 le32toh(sc->sc_txdescs[i].at_buf1)); 3144 printf(" at_buf2: 0x%08x\n", 3145 le32toh(sc->sc_txdescs[i].at_buf2)); 3146 if (i == txs->txs_lastdesc) 3147 break; 3148 } 3149 } 3150 #endif 3151 3152 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3153 if (txstat & ATW_TXSTAT_OWN) 3154 break; 3155 3156 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3157 3158 sc->sc_txfree += txs->txs_ndescs; 3159 3160 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3161 0, txs->txs_dmamap->dm_mapsize, 3162 BUS_DMASYNC_POSTWRITE); 3163 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3164 m_freem(txs->txs_mbuf); 3165 txs->txs_mbuf = NULL; 3166 3167 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3168 3169 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3170 (txstat & TXSTAT_ERRMASK) != 0) { 3171 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3172 txstat_buf, sizeof(txstat_buf)); 3173 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3174 txstat_buf, 3175 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3176 } 3177 3178 /* 3179 * Check for errors and collisions. 3180 */ 3181 if (txstat & ATW_TXSTAT_TUF) 3182 sc->sc_stats.ts_tx_tuf++; 3183 if (txstat & ATW_TXSTAT_TLT) 3184 sc->sc_stats.ts_tx_tlt++; 3185 if (txstat & ATW_TXSTAT_TRT) 3186 sc->sc_stats.ts_tx_trt++; 3187 if (txstat & ATW_TXSTAT_TRO) 3188 sc->sc_stats.ts_tx_tro++; 3189 if (txstat & ATW_TXSTAT_SOFBR) { 3190 sc->sc_stats.ts_tx_sofbr++; 3191 } 3192 3193 if ((txstat & ATW_TXSTAT_ES) == 0) 3194 ifp->if_collisions += 3195 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3196 else 3197 ifp->if_oerrors++; 3198 3199 ifp->if_opackets++; 3200 } 3201 3202 /* 3203 * If there are no more pending transmissions, cancel the watchdog 3204 * timer. 3205 */ 3206 if (txs == NULL) 3207 sc->sc_tx_timer = 0; 3208 #undef TXSTAT_ERRMASK 3209 #undef TXSTAT_FMT 3210 } 3211 3212 /* 3213 * atw_watchdog: [ifnet interface function] 3214 * 3215 * Watchdog timer handler. 3216 */ 3217 void 3218 atw_watchdog(ifp) 3219 struct ifnet *ifp; 3220 { 3221 struct atw_softc *sc = ifp->if_softc; 3222 struct ieee80211com *ic = &sc->sc_ic; 3223 3224 ifp->if_timer = 0; 3225 if (ATW_IS_ENABLED(sc) == 0) 3226 return; 3227 3228 if (sc->sc_rescan_timer) { 3229 if (--sc->sc_rescan_timer == 0) 3230 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3231 } 3232 if (sc->sc_tx_timer) { 3233 if (--sc->sc_tx_timer == 0 && 3234 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3235 printf("%s: transmit timeout\n", ifp->if_xname); 3236 ifp->if_oerrors++; 3237 (void)atw_init(ifp); 3238 atw_start(ifp); 3239 } 3240 } 3241 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3242 ifp->if_timer = 1; 3243 ieee80211_watchdog(ifp); 3244 } 3245 3246 /* Compute the 802.11 Duration field and the PLCP Length fields for 3247 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3248 * Write the fields to the ADM8211 Tx header, frm. 3249 * 3250 * TBD use the fragmentation threshold to find the right duration for 3251 * the first & last fragments. 3252 * 3253 * TBD make certain of the duration fields applied by the ADM8211 to each 3254 * fragment. I think that the ADM8211 knows how to subtract the CTS 3255 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3256 * I also think that the ADM8211 does *some* arithmetic for us, because 3257 * otherwise I think we would have to set a first duration for CTS/first 3258 * fragment, a second duration for fragments between the first and the 3259 * last, and a third duration for the last fragment. 3260 * 3261 * TBD make certain that duration fields reflect addition of FCS/WEP 3262 * and correct duration arithmetic as necessary. 3263 */ 3264 static void 3265 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3266 int len) 3267 { 3268 int remainder; 3269 3270 /* deal also with encrypted fragments */ 3271 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3272 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3273 sc->sc_dev.dv_xname)); 3274 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3275 IEEE80211_WEP_CRCLEN; 3276 } 3277 3278 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3279 * duration (XXX added by MAC?). 3280 */ 3281 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3282 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3283 3284 if (rate <= 4) 3285 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3286 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3287 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3288 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3289 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3290 else 3291 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3292 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3293 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3294 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3295 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3296 3297 /* lengthen duration if long preamble */ 3298 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3299 frm->atw_head_dur += 3300 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3301 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3302 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3303 IEEE80211_DUR_DS_FAST_PLCPHDR); 3304 3305 if (remainder != 0) 3306 frm->atw_head_dur++; 3307 3308 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3309 (rate == 2 || rate == 4)) { 3310 /* derived from Linux: how could this be right? */ 3311 frm->atw_head_plcplen = frm->atw_head_dur; 3312 } else { 3313 frm->atw_head_plcplen = (16 * len) / rate; 3314 remainder = (80 * len) % (rate * 5); 3315 3316 if (remainder != 0) { 3317 frm->atw_head_plcplen++; 3318 3319 /* XXX magic */ 3320 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3321 rate == 22 && remainder <= 30) 3322 frm->atw_head_plcplen |= 0x8000; 3323 } 3324 } 3325 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3326 htole16(frm->atw_head_plcplen); 3327 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3328 } 3329 3330 #ifdef ATW_DEBUG 3331 static void 3332 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3333 { 3334 struct atw_softc *sc = ifp->if_softc; 3335 struct mbuf *m; 3336 int i, noctets = 0; 3337 3338 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3339 m0->m_pkthdr.len); 3340 3341 for (m = m0; m; m = m->m_next) { 3342 if (m->m_len == 0) 3343 continue; 3344 for (i = 0; i < m->m_len; i++) { 3345 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3346 if (++noctets % 24 == 0) 3347 printf("\n"); 3348 } 3349 } 3350 printf("%s%s: %d bytes emitted\n", 3351 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3352 } 3353 #endif /* ATW_DEBUG */ 3354 3355 /* 3356 * atw_start: [ifnet interface function] 3357 * 3358 * Start packet transmission on the interface. 3359 */ 3360 void 3361 atw_start(ifp) 3362 struct ifnet *ifp; 3363 { 3364 struct atw_softc *sc = ifp->if_softc; 3365 struct ieee80211com *ic = &sc->sc_ic; 3366 struct ieee80211_node *ni; 3367 struct ieee80211_frame *wh; 3368 struct atw_frame *hh; 3369 struct mbuf *m0, *m; 3370 struct atw_txsoft *txs, *last_txs; 3371 struct atw_txdesc *txd; 3372 int do_encrypt, rate; 3373 bus_dmamap_t dmamap; 3374 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3375 3376 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3377 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3378 3379 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3380 return; 3381 3382 #if 0 /* TBD ??? */ 3383 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3384 return; 3385 #endif 3386 3387 /* 3388 * Remember the previous number of free descriptors and 3389 * the first descriptor we'll use. 3390 */ 3391 ofree = sc->sc_txfree; 3392 firsttx = sc->sc_txnext; 3393 3394 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3395 sc->sc_dev.dv_xname, ofree, firsttx)); 3396 3397 /* 3398 * Loop through the send queue, setting up transmit descriptors 3399 * until we drain the queue, or use up all available transmit 3400 * descriptors. 3401 */ 3402 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3403 sc->sc_txfree != 0) { 3404 3405 do_encrypt = 0; 3406 /* 3407 * Grab a packet off the management queue, if it 3408 * is not empty. Otherwise, from the data queue. 3409 */ 3410 IF_DEQUEUE(&ic->ic_mgtq, m0); 3411 if (m0 != NULL) { 3412 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3413 m0->m_pkthdr.rcvif = NULL; 3414 } else { 3415 IFQ_DEQUEUE(&ifp->if_snd, m0); 3416 if (m0 == NULL) 3417 break; 3418 #if NBPFILTER > 0 3419 if (ifp->if_bpf != NULL) 3420 bpf_mtap(ifp->if_bpf, m0); 3421 #endif /* NBPFILTER > 0 */ 3422 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3423 ifp->if_oerrors++; 3424 break; 3425 } 3426 } 3427 3428 rate = MAX(ieee80211_get_rate(ic), 2); 3429 3430 #if NBPFILTER > 0 3431 /* 3432 * Pass the packet to any BPF listeners. 3433 */ 3434 if (ic->ic_rawbpf != NULL) 3435 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3436 3437 if (sc->sc_radiobpf != NULL) { 3438 struct mbuf mb; 3439 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3440 3441 tap->at_rate = rate; 3442 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3443 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3444 3445 /* TBD tap->at_flags */ 3446 3447 M_COPY_PKTHDR(&mb, m0); 3448 mb.m_data = (caddr_t)tap; 3449 mb.m_len = tap->at_ihdr.it_len; 3450 mb.m_next = m0; 3451 mb.m_pkthdr.len += mb.m_len; 3452 bpf_mtap(sc->sc_radiobpf, &mb); 3453 } 3454 #endif /* NBPFILTER > 0 */ 3455 3456 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3457 3458 if (ni != NULL && ni != ic->ic_bss) 3459 ieee80211_free_node(ic, ni); 3460 3461 if (m0 == NULL) { 3462 ifp->if_oerrors++; 3463 break; 3464 } 3465 3466 /* just to make sure. */ 3467 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3468 3469 if (m0 == NULL) { 3470 ifp->if_oerrors++; 3471 break; 3472 } 3473 3474 hh = mtod(m0, struct atw_frame *); 3475 wh = &hh->atw_ihdr; 3476 3477 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3478 3479 /* Copy everything we need from the 802.11 header: 3480 * Frame Control; address 1, address 3, or addresses 3481 * 3 and 4. NIC fills in BSSID, SA. 3482 */ 3483 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3484 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3485 panic("%s: illegal WDS frame", 3486 sc->sc_dev.dv_xname); 3487 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3488 } else 3489 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3490 3491 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3492 3493 /* initialize remaining Tx parameters */ 3494 memset(&hh->u, 0, sizeof(hh->u)); 3495 3496 hh->atw_rate = rate * 5; 3497 /* XXX this could be incorrect if M_FCS. _encap should 3498 * probably strip FCS just in case it sticks around in 3499 * bridged packets. 3500 */ 3501 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3502 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3503 sizeof(struct atw_frame)); 3504 3505 #if 0 3506 /* this virtually guaranteed that WEP-encrypted frames 3507 * are fragmented. oops. 3508 */ 3509 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3510 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3511 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3512 #else 3513 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3514 #endif 3515 3516 hh->atw_rtylmt = 3; 3517 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3518 if (do_encrypt) { 3519 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3520 hh->atw_keyid = ic->ic_wep_txkey; 3521 } 3522 3523 /* TBD 4-addr frames */ 3524 atw_frame_setdurs(sc, hh, rate, 3525 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3526 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3527 3528 /* never fragment multicast frames */ 3529 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3530 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3531 } else if (sc->sc_flags & ATWF_RTSCTS) { 3532 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3533 } 3534 3535 #ifdef ATW_DEBUG 3536 /* experimental stuff */ 3537 if (atw_xrtylmt != ~0) 3538 hh->atw_rtylmt = atw_xrtylmt; 3539 if (atw_xhdrctl != 0) 3540 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3541 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3542 hh->atw_service = atw_xservice; 3543 if (atw_xpaylen != 0) 3544 hh->atw_paylen = htole16(atw_xpaylen); 3545 hh->atw_fragnum = 0; 3546 3547 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3548 printf("%s: dst = %s, rate = 0x%02x, " 3549 "service = 0x%02x, paylen = 0x%04x\n", 3550 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3551 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3552 3553 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3554 "dur1 = 0x%04x, dur2 = 0x%04x, " 3555 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3556 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3557 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3558 hh->atw_tail_dur, hh->atw_head_dur); 3559 3560 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3561 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3562 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3563 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3564 3565 printf("%s: keyid = %d\n", 3566 sc->sc_dev.dv_xname, hh->atw_keyid); 3567 3568 atw_dump_pkt(ifp, m0); 3569 } 3570 #endif /* ATW_DEBUG */ 3571 3572 dmamap = txs->txs_dmamap; 3573 3574 /* 3575 * Load the DMA map. Copy and try (once) again if the packet 3576 * didn't fit in the alloted number of segments. 3577 */ 3578 for (first = 1; 3579 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3580 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3581 first = 0) { 3582 MGETHDR(m, M_DONTWAIT, MT_DATA); 3583 if (m == NULL) { 3584 printf("%s: unable to allocate Tx mbuf\n", 3585 sc->sc_dev.dv_xname); 3586 break; 3587 } 3588 if (m0->m_pkthdr.len > MHLEN) { 3589 MCLGET(m, M_DONTWAIT); 3590 if ((m->m_flags & M_EXT) == 0) { 3591 printf("%s: unable to allocate Tx " 3592 "cluster\n", sc->sc_dev.dv_xname); 3593 m_freem(m); 3594 break; 3595 } 3596 } 3597 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3598 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3599 m_freem(m0); 3600 m0 = m; 3601 m = NULL; 3602 } 3603 if (error != 0) { 3604 printf("%s: unable to load Tx buffer, " 3605 "error = %d\n", sc->sc_dev.dv_xname, error); 3606 m_freem(m0); 3607 break; 3608 } 3609 3610 /* 3611 * Ensure we have enough descriptors free to describe 3612 * the packet. 3613 */ 3614 if (dmamap->dm_nsegs > sc->sc_txfree) { 3615 /* 3616 * Not enough free descriptors to transmit 3617 * this packet. Unload the DMA map and 3618 * drop the packet. Notify the upper layer 3619 * that there are no more slots left. 3620 * 3621 * XXX We could allocate an mbuf and copy, but 3622 * XXX it is worth it? 3623 */ 3624 ifp->if_flags |= IFF_OACTIVE; 3625 bus_dmamap_unload(sc->sc_dmat, dmamap); 3626 m_freem(m0); 3627 break; 3628 } 3629 3630 /* 3631 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3632 */ 3633 3634 /* Sync the DMA map. */ 3635 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3636 BUS_DMASYNC_PREWRITE); 3637 3638 /* XXX arbitrary retry limit; 8 because I have seen it in 3639 * use already and maybe 0 means "no tries" ! 3640 */ 3641 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3642 3643 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3644 sc->sc_dev.dv_xname, rate * 5)); 3645 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3646 3647 /* 3648 * Initialize the transmit descriptors. 3649 */ 3650 for (nexttx = sc->sc_txnext, seg = 0; 3651 seg < dmamap->dm_nsegs; 3652 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3653 /* 3654 * If this is the first descriptor we're 3655 * enqueueing, don't set the OWN bit just 3656 * yet. That could cause a race condition. 3657 * We'll do it below. 3658 */ 3659 txd = &sc->sc_txdescs[nexttx]; 3660 txd->at_ctl = ctl | 3661 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3662 3663 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3664 txd->at_flags = 3665 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3666 ATW_TXFLAG_TBS1_MASK)) | 3667 ((nexttx == (ATW_NTXDESC - 1)) 3668 ? htole32(ATW_TXFLAG_TER) : 0); 3669 lasttx = nexttx; 3670 } 3671 3672 KASSERT(lasttx != -1, ("bad lastx")); 3673 /* Set `first segment' and `last segment' appropriately. */ 3674 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3675 htole32(ATW_TXFLAG_FS); 3676 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3677 3678 #ifdef ATW_DEBUG 3679 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3680 printf(" txsoft %p transmit chain:\n", txs); 3681 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3682 printf(" descriptor %d:\n", seg); 3683 printf(" at_ctl: 0x%08x\n", 3684 le32toh(sc->sc_txdescs[seg].at_ctl)); 3685 printf(" at_flags: 0x%08x\n", 3686 le32toh(sc->sc_txdescs[seg].at_flags)); 3687 printf(" at_buf1: 0x%08x\n", 3688 le32toh(sc->sc_txdescs[seg].at_buf1)); 3689 printf(" at_buf2: 0x%08x\n", 3690 le32toh(sc->sc_txdescs[seg].at_buf2)); 3691 if (seg == lasttx) 3692 break; 3693 } 3694 } 3695 #endif 3696 3697 /* Sync the descriptors we're using. */ 3698 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3699 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3700 3701 /* 3702 * Store a pointer to the packet so we can free it later, 3703 * and remember what txdirty will be once the packet is 3704 * done. 3705 */ 3706 txs->txs_mbuf = m0; 3707 txs->txs_firstdesc = sc->sc_txnext; 3708 txs->txs_lastdesc = lasttx; 3709 txs->txs_ndescs = dmamap->dm_nsegs; 3710 3711 /* Advance the tx pointer. */ 3712 sc->sc_txfree -= dmamap->dm_nsegs; 3713 sc->sc_txnext = nexttx; 3714 3715 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3716 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3717 3718 last_txs = txs; 3719 } 3720 3721 if (txs == NULL || sc->sc_txfree == 0) { 3722 /* No more slots left; notify upper layer. */ 3723 ifp->if_flags |= IFF_OACTIVE; 3724 } 3725 3726 if (sc->sc_txfree != ofree) { 3727 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3728 sc->sc_dev.dv_xname, lasttx, firsttx)); 3729 /* 3730 * Cause a transmit interrupt to happen on the 3731 * last packet we enqueued. 3732 */ 3733 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3734 ATW_CDTXSYNC(sc, lasttx, 1, 3735 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3736 3737 /* 3738 * The entire packet chain is set up. Give the 3739 * first descriptor to the chip now. 3740 */ 3741 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3742 ATW_CDTXSYNC(sc, firsttx, 1, 3743 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3744 3745 /* Wake up the transmitter. */ 3746 /* XXX USE AUTOPOLLING? */ 3747 ATW_WRITE(sc, ATW_TDR, 0x1); 3748 3749 /* Set a watchdog timer in case the chip flakes out. */ 3750 sc->sc_tx_timer = 5; 3751 ifp->if_timer = 1; 3752 } 3753 } 3754 3755 /* 3756 * atw_power: 3757 * 3758 * Power management (suspend/resume) hook. 3759 */ 3760 void 3761 atw_power(why, arg) 3762 int why; 3763 void *arg; 3764 { 3765 struct atw_softc *sc = arg; 3766 struct ifnet *ifp = &sc->sc_ic.ic_if; 3767 int s; 3768 3769 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3770 3771 s = splnet(); 3772 switch (why) { 3773 case PWR_STANDBY: 3774 /* XXX do nothing. */ 3775 break; 3776 case PWR_SUSPEND: 3777 atw_stop(ifp, 0); 3778 if (sc->sc_power != NULL) 3779 (*sc->sc_power)(sc, why); 3780 break; 3781 case PWR_RESUME: 3782 if (ifp->if_flags & IFF_UP) { 3783 if (sc->sc_power != NULL) 3784 (*sc->sc_power)(sc, why); 3785 atw_init(ifp); 3786 } 3787 break; 3788 case PWR_SOFTSUSPEND: 3789 case PWR_SOFTSTANDBY: 3790 case PWR_SOFTRESUME: 3791 break; 3792 } 3793 splx(s); 3794 } 3795 3796 /* 3797 * atw_ioctl: [ifnet interface function] 3798 * 3799 * Handle control requests from the operator. 3800 */ 3801 int 3802 atw_ioctl(ifp, cmd, data) 3803 struct ifnet *ifp; 3804 u_long cmd; 3805 caddr_t data; 3806 { 3807 struct atw_softc *sc = ifp->if_softc; 3808 struct ifreq *ifr = (struct ifreq *)data; 3809 int s, error = 0; 3810 3811 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3812 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3813 return ENXIO; 3814 3815 s = splnet(); 3816 3817 switch (cmd) { 3818 case SIOCSIFFLAGS: 3819 if (ifp->if_flags & IFF_UP) { 3820 if (ATW_IS_ENABLED(sc)) { 3821 /* 3822 * To avoid rescanning another access point, 3823 * do not call atw_init() here. Instead, 3824 * only reflect media settings. 3825 */ 3826 atw_filter_setup(sc); 3827 } else 3828 error = atw_init(ifp); 3829 } else if (ATW_IS_ENABLED(sc)) 3830 atw_stop(ifp, 1); 3831 break; 3832 case SIOCADDMULTI: 3833 case SIOCDELMULTI: 3834 error = (cmd == SIOCADDMULTI) ? 3835 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3836 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3837 if (error == ENETRESET) { 3838 if (ATW_IS_ENABLED(sc)) 3839 atw_filter_setup(sc); /* do not rescan */ 3840 error = 0; 3841 } 3842 break; 3843 default: 3844 error = ieee80211_ioctl(ifp, cmd, data); 3845 if (error == ENETRESET) { 3846 if (ATW_IS_ENABLED(sc)) 3847 error = atw_init(ifp); 3848 else 3849 error = 0; 3850 } 3851 break; 3852 } 3853 3854 /* Try to get more packets going. */ 3855 if (ATW_IS_ENABLED(sc)) 3856 atw_start(ifp); 3857 3858 splx(s); 3859 return (error); 3860 } 3861 3862 static int 3863 atw_media_change(struct ifnet *ifp) 3864 { 3865 int error; 3866 3867 error = ieee80211_media_change(ifp); 3868 if (error == ENETRESET) { 3869 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3870 (IFF_RUNNING|IFF_UP)) 3871 atw_init(ifp); /* XXX lose error */ 3872 error = 0; 3873 } 3874 return error; 3875 } 3876 3877 static void 3878 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3879 { 3880 struct atw_softc *sc = ifp->if_softc; 3881 3882 if (ATW_IS_ENABLED(sc) == 0) { 3883 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3884 imr->ifm_status = 0; 3885 return; 3886 } 3887 ieee80211_media_status(ifp, imr); 3888 } 3889
Indexes created Wed Sep 24 05:09:52 GMT 2025