atw.c revision 1.13
1 /* $NetBSD: atw.c,v 1.13 2004/01/10 06:30:35 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.13 2004/01/10 06:30:35 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/atwvar.h> 82 #include <dev/ic/smc93cx6var.h> 83 84 /* XXX TBD open questions 85 * 86 * 87 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 88 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 89 * handle this for me? 90 * 91 */ 92 /* device attachment 93 * 94 * print TOFS[012] 95 * 96 * device initialization 97 * 98 * clear ATW_FRCTL_MAXPSP to disable max power saving 99 * set ATW_TXBR_ALCUPDATE to enable ALC 100 * set TOFS[012]? (hope not) 101 * disable rx/tx 102 * set ATW_PAR_SWR (software reset) 103 * wait for ATW_PAR_SWR clear 104 * disable interrupts 105 * ack status register 106 * enable interrupts 107 * 108 * rx/tx initialization 109 * 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * allocate and init descriptor rings 112 * write ATW_PAR_DSL (descriptor skip length) 113 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * write ATW_NAR_SQ for one/both transmit descriptor rings 116 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * 118 * rx/tx end 119 * 120 * stop DMA 121 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 122 * flush tx w/ ATW_NAR_HF 123 * 124 * scan 125 * 126 * initialize rx/tx 127 * 128 * IBSS join/create 129 * 130 * set ATW_NAR_EA (is set by ASIC?) 131 * 132 * BSS join: (re)association response 133 * 134 * set ATW_FRCTL_AID 135 * 136 * optimizations ??? 137 * 138 */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_rfio_enable_delay = 20 * 1000; 145 int atw_rfio_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 5; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 150 #ifdef ATW_DEBUG 151 int atw_xhdrctl = 0; 152 int atw_xrtylmt = ~0; 153 int atw_xservice = IEEE80211_PLCP_SERVICE; 154 int atw_xpaylen = 0; 155 156 int atw_debug = 0; 157 158 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 159 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 160 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 161 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 162 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 163 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 164 static void atw_print_regs(struct atw_softc *, const char *); 165 static void atw_rf3000_print(struct atw_softc *); 166 static void atw_si4126_print(struct atw_softc *); 167 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 168 #else 169 #define ATW_DPRINTF(x) 170 #define ATW_DPRINTF2(x) 171 #define ATW_DPRINTF3(x) 172 #define DPRINTF(sc, x) /* nothing */ 173 #define DPRINTF2(sc, x) /* nothing */ 174 #define DPRINTF3(sc, x) /* nothing */ 175 #endif 176 177 #ifdef ATW_STATS 178 void atw_print_stats __P((struct atw_softc *)); 179 #endif 180 181 void atw_start __P((struct ifnet *)); 182 void atw_watchdog __P((struct ifnet *)); 183 int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 184 int atw_init __P((struct ifnet *)); 185 void atw_stop __P((struct ifnet *, int)); 186 187 void atw_reset __P((struct atw_softc *)); 188 int atw_read_srom __P((struct atw_softc *)); 189 190 void atw_shutdown __P((void *)); 191 192 void atw_rxdrain __P((struct atw_softc *)); 193 int atw_add_rxbuf __P((struct atw_softc *, int)); 194 void atw_idle __P((struct atw_softc *, u_int32_t)); 195 196 int atw_enable __P((struct atw_softc *)); 197 void atw_disable __P((struct atw_softc *)); 198 void atw_power __P((int, void *)); 199 200 void atw_rxintr __P((struct atw_softc *)); 201 void atw_txintr __P((struct atw_softc *)); 202 void atw_linkintr __P((struct atw_softc *, u_int32_t)); 203 204 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 205 static void atw_tsf(struct atw_softc *); 206 static void atw_start_beacon(struct atw_softc *, int); 207 static void atw_write_wep(struct atw_softc *); 208 static void atw_write_bssid(struct atw_softc *); 209 static void atw_write_bcn_thresh(struct atw_softc *); 210 static void atw_write_ssid(struct atw_softc *); 211 static void atw_write_sup_rates(struct atw_softc *); 212 static void atw_clear_sram(struct atw_softc *); 213 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 214 static int atw_media_change(struct ifnet *); 215 static void atw_media_status(struct ifnet *, struct ifmediareq *); 216 static void atw_filter_setup(struct atw_softc *); 217 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 218 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 219 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 224 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 225 226 static int atw_tune(struct atw_softc *); 227 228 static void atw_rfio_enable(struct atw_softc *, int); 229 230 /* RFMD RF3000 Baseband Processor */ 231 static int atw_rf3000_init(struct atw_softc *); 232 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 233 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 234 #ifdef ATW_DEBUG 235 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 236 #endif /* ATW_DEBUG */ 237 238 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 239 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 240 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 241 #ifdef ATW_DEBUG 242 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 243 #endif /* ATW_DEBUG */ 244 245 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 246 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 247 248 const char *atw_tx_state[] = { 249 "STOPPED", 250 "RUNNING - FETCH", 251 "RUNNING - WAIT", 252 "RUNNING - READING", 253 "-- RESERVED1 --", 254 "-- RESERVED2 --", 255 "SUSPENDED", 256 "RUNNING - CLOSE" 257 }; 258 259 const char *atw_rx_state[] = { 260 "STOPPED", 261 "RUNNING - FETCH", 262 "RUNNING - CHECK", 263 "RUNNING - WAIT", 264 "SUSPENDED", 265 "RUNNING - CLOSE", 266 "RUNNING - FLUSH", 267 "RUNNING - QUEUE" 268 }; 269 270 int 271 atw_activate(struct device *self, enum devact act) 272 { 273 struct atw_softc *sc = (struct atw_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 282 case DVACT_DEACTIVATE: 283 if_deactivate(&sc->sc_ic.ic_if); 284 break; 285 } 286 splx(s); 287 return rv; 288 } 289 290 /* 291 * atw_enable: 292 * 293 * Enable the ADM8211 chip. 294 */ 295 int 296 atw_enable(sc) 297 struct atw_softc *sc; 298 { 299 300 if (ATW_IS_ENABLED(sc) == 0) { 301 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 302 printf("%s: device enable failed\n", 303 sc->sc_dev.dv_xname); 304 return (EIO); 305 } 306 sc->sc_flags |= ATWF_ENABLED; 307 } 308 return (0); 309 } 310 311 /* 312 * atw_disable: 313 * 314 * Disable the ADM8211 chip. 315 */ 316 void 317 atw_disable(sc) 318 struct atw_softc *sc; 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF2(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF2(("\n\t")); 400 } 401 ATW_DPRINTF2((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF2(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 struct ieee80211com *ic = &sc->sc_ic; 498 struct ifnet *ifp = &ic->ic_if; 499 int country_code, error, i, nrate; 500 u_int32_t reg; 501 static const char *type_strings[] = {"Intersil (not supported)", 502 "RFMD", "Marvel (not supported)"}; 503 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 504 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 505 }; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 sc->sc_rxsoft[i].rxs_mbuf = NULL; 577 } 578 579 /* Reset the chip to a known state. */ 580 atw_reset(sc); 581 582 if (atw_read_srom(sc) == -1) 583 return; 584 585 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 586 ATW_SR_RFTYPE_MASK); 587 588 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 589 ATW_SR_BBPTYPE_MASK); 590 591 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 592 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 600 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 601 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 602 603 /* XXX There exists a Linux driver which seems to use RFType = 0 for 604 * MARVEL. My bug, or theirs? 605 */ 606 607 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 608 609 switch (sc->sc_rftype) { 610 case ATW_RFTYPE_INTERSIL: 611 reg |= ATW_SYNCTL_CS1; 612 break; 613 case ATW_RFTYPE_RFMD: 614 reg |= ATW_SYNCTL_CS0; 615 break; 616 case ATW_RFTYPE_MARVEL: 617 break; 618 } 619 620 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 621 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 622 623 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 624 625 switch (sc->sc_bbptype) { 626 case ATW_RFTYPE_INTERSIL: 627 reg |= ATW_BBPCTL_TWI; 628 break; 629 case ATW_RFTYPE_RFMD: 630 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 631 ATW_BBPCTL_CCA_ACTLO; 632 break; 633 case ATW_RFTYPE_MARVEL: 634 break; 635 } 636 637 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 638 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 639 640 /* 641 * From this point forward, the attachment cannot fail. A failure 642 * before this point releases all resources that may have been 643 * allocated. 644 */ 645 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 646 647 ATW_DPRINTF2((" SROM MAC %04x%04x%04x", 648 htole16(sc->sc_srom[ATW_SR_MAC00]), 649 htole16(sc->sc_srom[ATW_SR_MAC01]), 650 htole16(sc->sc_srom[ATW_SR_MAC10]))); 651 652 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 653 ATW_SR_CTRY_MASK); 654 655 #define ADD_CHANNEL(_ic, _chan) do { \ 656 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 657 _ic->ic_channels[_chan].ic_freq = \ 658 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 659 } while (0) 660 661 /* Find available channels */ 662 switch (country_code) { 663 case COUNTRY_MMK2: /* 1-14 */ 664 ADD_CHANNEL(ic, 14); 665 /*FALLTHROUGH*/ 666 case COUNTRY_ETSI: /* 1-13 */ 667 for (i = 1; i <= 13; i++) 668 ADD_CHANNEL(ic, i); 669 break; 670 case COUNTRY_FCC: /* 1-11 */ 671 case COUNTRY_IC: /* 1-11 */ 672 for (i = 1; i <= 11; i++) 673 ADD_CHANNEL(ic, i); 674 break; 675 case COUNTRY_MMK: /* 14 */ 676 ADD_CHANNEL(ic, 14); 677 break; 678 case COUNTRY_FRANCE: /* 10-13 */ 679 for (i = 10; i <= 13; i++) 680 ADD_CHANNEL(ic, i); 681 break; 682 default: /* assume channels 10-11 */ 683 case COUNTRY_SPAIN: /* 10-11 */ 684 for (i = 10; i <= 11; i++) 685 ADD_CHANNEL(ic, i); 686 break; 687 } 688 689 /* Read the MAC address. */ 690 reg = ATW_READ(sc, ATW_PAR0); 691 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 692 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 693 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 694 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 695 reg = ATW_READ(sc, ATW_PAR1); 696 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 697 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 698 699 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 700 printf(" could not get mac address, attach failed\n"); 701 return; 702 } 703 704 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 705 706 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 707 ifp->if_softc = sc; 708 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 709 IFF_NOTRAILERS; 710 ifp->if_ioctl = atw_ioctl; 711 ifp->if_start = atw_start; 712 ifp->if_watchdog = atw_watchdog; 713 ifp->if_init = atw_init; 714 ifp->if_stop = atw_stop; 715 IFQ_SET_READY(&ifp->if_snd); 716 717 ic->ic_phytype = IEEE80211_T_DS; 718 ic->ic_opmode = IEEE80211_M_STA; 719 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 720 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 721 722 nrate = 0; 723 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 724 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 728 729 /* 730 * Call MI attach routines. 731 */ 732 733 if_attach(ifp); 734 ieee80211_ifattach(ifp); 735 736 sc->sc_newstate = ic->ic_newstate; 737 ic->ic_newstate = atw_newstate; 738 739 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 740 ic->ic_recv_mgmt = atw_recv_mgmt; 741 742 sc->sc_node_free = ic->ic_node_free; 743 ic->ic_node_free = atw_node_free; 744 745 sc->sc_node_alloc = ic->ic_node_alloc; 746 ic->ic_node_alloc = atw_node_alloc; 747 748 /* possibly we should fill in our own sc_send_prresp, since 749 * the ADM8211 is probably sending probe responses in ad hoc 750 * mode. 751 */ 752 753 /* complete initialization */ 754 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 755 callout_init(&sc->sc_scan_ch); 756 757 #if NBPFILTER > 0 758 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 759 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 760 #endif 761 762 /* 763 * Make sure the interface is shutdown during reboot. 764 */ 765 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 766 if (sc->sc_sdhook == NULL) 767 printf("%s: WARNING: unable to establish shutdown hook\n", 768 sc->sc_dev.dv_xname); 769 770 /* 771 * Add a suspend hook to make sure we come back up after a 772 * resume. 773 */ 774 sc->sc_powerhook = powerhook_establish(atw_power, sc); 775 if (sc->sc_powerhook == NULL) 776 printf("%s: WARNING: unable to establish power hook\n", 777 sc->sc_dev.dv_xname); 778 779 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 780 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 781 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 782 783 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 784 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 785 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 786 787 return; 788 789 /* 790 * Free any resources we've allocated during the failed attach 791 * attempt. Do this in reverse order and fall through. 792 */ 793 fail_5: 794 for (i = 0; i < ATW_NRXDESC; i++) { 795 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 796 continue; 797 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 798 } 799 fail_4: 800 for (i = 0; i < ATW_TXQUEUELEN; i++) { 801 if (sc->sc_txsoft[i].txs_dmamap == NULL) 802 continue; 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 804 } 805 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 806 fail_3: 807 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 808 fail_2: 809 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 810 sizeof(struct atw_control_data)); 811 fail_1: 812 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 813 fail_0: 814 return; 815 } 816 817 static struct ieee80211_node * 818 atw_node_alloc(struct ieee80211com *ic) 819 { 820 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 821 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 822 823 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 824 return ni; 825 } 826 827 static void 828 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 829 { 830 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 831 832 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 833 ether_sprintf(ni->ni_bssid))); 834 (*sc->sc_node_free)(ic, ni); 835 } 836 837 /* 838 * atw_reset: 839 * 840 * Perform a soft reset on the ADM8211. 841 */ 842 void 843 atw_reset(sc) 844 struct atw_softc *sc; 845 { 846 int i; 847 848 if (ATW_IS_ENABLED(sc) == 0) 849 return; 850 851 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 852 853 for (i = 0; i < 10000; i++) { 854 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 855 break; 856 DELAY(1); 857 } 858 859 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 860 861 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 862 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 863 864 /* Turn off maximum power saving. */ 865 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 866 867 /* Recall EEPROM. */ 868 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 869 870 DELAY(10 * 1000); 871 872 /* A reset seems to affect the SRAM contents, so put them into 873 * a known state. 874 */ 875 atw_clear_sram(sc); 876 877 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 878 879 sc->sc_lost_bcn_thresh = 0; 880 } 881 882 static void 883 atw_clear_sram(sc) 884 struct atw_softc *sc; 885 { 886 #if 0 887 for (addr = 0; addr < 448; addr++) { 888 ATW_WRITE(sc, ATW_WEPCTL, 889 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 890 DELAY(1000); 891 ATW_WRITE(sc, ATW_WESK, 0); 892 DELAY(1000); /* paranoia */ 893 } 894 return; 895 #endif 896 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 897 /* XXX not for revision 0x20. */ 898 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 899 } 900 901 /* TBD atw_init 902 * 903 * set MAC based on ic->ic_bss->myaddr 904 * write WEP keys 905 * set TX rate 906 */ 907 908 /* 909 * atw_init: [ ifnet interface function ] 910 * 911 * Initialize the interface. Must be called at splnet(). 912 */ 913 int 914 atw_init(ifp) 915 struct ifnet *ifp; 916 { 917 struct atw_softc *sc = ifp->if_softc; 918 struct ieee80211com *ic = &sc->sc_ic; 919 struct atw_txsoft *txs; 920 struct atw_rxsoft *rxs; 921 u_int32_t reg; 922 int i, error = 0; 923 924 if ((error = atw_enable(sc)) != 0) 925 goto out; 926 927 /* 928 * Cancel any pending I/O. This also resets. 929 */ 930 atw_stop(ifp, 0); 931 932 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 933 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 934 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 935 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 936 937 /* Turn off APM??? (A binary-only driver does this.) 938 * 939 * Set Rx store-and-forward mode. 940 */ 941 reg = ATW_READ(sc, ATW_CMDR); 942 reg &= ~ATW_CMDR_APM; 943 reg &= ~ATW_CMDR_DRT_MASK; 944 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 945 946 ATW_WRITE(sc, ATW_CMDR, reg); 947 948 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 949 * 950 * XXX a binary-only driver sets a different service field than 951 * 0. why? 952 */ 953 reg = ATW_READ(sc, ATW_PLCPHD); 954 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 955 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 956 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 957 ATW_WRITE(sc, ATW_PLCPHD, reg); 958 959 /* XXX */ 960 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 961 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 962 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 963 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 964 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 965 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 966 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 967 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 968 ATW_WRITE(sc, ATW_TOFS2, reg); 969 970 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 971 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 972 973 /* XXX this resets an Intersil RF front-end? */ 974 /* TBD condition on Intersil RFType? */ 975 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 976 DELAY(10 * 1000); 977 ATW_WRITE(sc, ATW_SYNRF, 0); 978 DELAY(5 * 1000); 979 980 /* 16 TU max duration for contention-free period */ 981 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 982 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 983 984 /* XXX I guess that the Cardbus clock is 22MHz? 985 * I am assuming that the role of ATW_TOFS0_USCNT is 986 * to divide the bus clock to get a 1MHz clock---the datasheet is not 987 * very clear on this point. It says in the datasheet that it is 988 * possible for the ADM8211 to accomodate bus speeds between 22MHz 989 * and 33MHz; maybe this is the way? I see a binary-only driver write 990 * these values. These values are also the power-on default. 991 */ 992 ATW_WRITE(sc, ATW_TOFS0, 993 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 994 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 995 996 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 997 * driver. go figure. 998 */ 999 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1000 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1001 ATW_IFST_SIFS_MASK) | 1002 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1003 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1004 1005 ATW_WRITE(sc, ATW_IFST, reg); 1006 1007 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1008 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1009 1010 /* Set up the MMI read/write addresses for the BBP. 1011 * 1012 * TBD find out the Marvel settings. 1013 */ 1014 switch (sc->sc_bbptype) { 1015 case ATW_BBPTYPE_INTERSIL: 1016 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1017 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1018 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1019 break; 1020 case ATW_BBPTYPE_MARVEL: 1021 break; 1022 case ATW_BBPTYPE_RFMD: 1023 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1024 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1025 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1026 default: 1027 break; 1028 } 1029 1030 sc->sc_wepctl = 0; 1031 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1032 1033 if ((error = atw_rf3000_init(sc)) != 0) 1034 goto out; 1035 1036 /* 1037 * Initialize the PCI Access Register. 1038 */ 1039 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1040 1041 /* 1042 * If we're allowed to do so, use Memory Read Line 1043 * and Memory Read Multiple. 1044 * 1045 * XXX Should we use Memory Write and Invalidate? 1046 */ 1047 if (sc->sc_flags & ATWF_MRL) 1048 sc->sc_busmode |= ATW_PAR_MRLE; 1049 if (sc->sc_flags & ATWF_MRM) 1050 sc->sc_busmode |= ATW_PAR_MRME; 1051 if (sc->sc_flags & ATWF_MWI) 1052 sc->sc_busmode |= ATW_PAR_MWIE; 1053 if (sc->sc_maxburst == 0) 1054 sc->sc_maxburst = 8; /* ADM8211 default */ 1055 1056 switch (sc->sc_cacheline) { 1057 default: 1058 /* Use burst length. */ 1059 break; 1060 case 8: 1061 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1062 break; 1063 case 16: 1064 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1065 break; 1066 case 32: 1067 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1068 break; 1069 } 1070 switch (sc->sc_maxburst) { 1071 case 1: 1072 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1073 break; 1074 case 2: 1075 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1076 break; 1077 case 4: 1078 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1079 break; 1080 case 8: 1081 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1082 break; 1083 case 16: 1084 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1085 break; 1086 case 32: 1087 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1088 break; 1089 default: 1090 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1091 break; 1092 } 1093 1094 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1095 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1096 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1097 1098 /* 1099 * Initialize the OPMODE register. We don't write it until 1100 * we're ready to begin the transmit and receive processes. 1101 */ 1102 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1103 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1104 1105 /* 1106 * Initialize the transmit descriptor ring. 1107 */ 1108 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1109 for (i = 0; i < ATW_NTXDESC; i++) { 1110 /* no transmit chaining */ 1111 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1112 sc->sc_txdescs[i].at_buf2 = 1113 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1114 } 1115 /* use ring mode */ 1116 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1117 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 sc->sc_txfree = ATW_NTXDESC; 1120 sc->sc_txnext = 0; 1121 1122 /* 1123 * Initialize the transmit job descriptors. 1124 */ 1125 SIMPLEQ_INIT(&sc->sc_txfreeq); 1126 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1127 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1128 txs = &sc->sc_txsoft[i]; 1129 txs->txs_mbuf = NULL; 1130 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1131 } 1132 1133 /* 1134 * Initialize the receive descriptor and receive job 1135 * descriptor rings. 1136 */ 1137 for (i = 0; i < ATW_NRXDESC; i++) { 1138 rxs = &sc->sc_rxsoft[i]; 1139 if (rxs->rxs_mbuf == NULL) { 1140 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1141 printf("%s: unable to allocate or map rx " 1142 "buffer %d, error = %d\n", 1143 sc->sc_dev.dv_xname, i, error); 1144 /* 1145 * XXX Should attempt to run with fewer receive 1146 * XXX buffers instead of just failing. 1147 */ 1148 atw_rxdrain(sc); 1149 goto out; 1150 } 1151 } else 1152 ATW_INIT_RXDESC(sc, i); 1153 } 1154 sc->sc_rxptr = 0; 1155 1156 /* disable all wake-up events */ 1157 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1158 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1159 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1160 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1161 1162 /* ack all wake-up events */ 1163 ATW_SET(sc, ATW_WCSR, 0); 1164 1165 /* 1166 * Initialize the interrupt mask and enable interrupts. 1167 */ 1168 /* normal interrupts */ 1169 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1170 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1171 1172 /* abnormal interrupts */ 1173 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1174 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1175 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1176 1177 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1178 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1179 1180 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1181 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1182 ATW_INTR_TRT; 1183 1184 sc->sc_linkint_mask &= sc->sc_inten; 1185 sc->sc_rxint_mask &= sc->sc_inten; 1186 sc->sc_txint_mask &= sc->sc_inten; 1187 1188 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1189 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1190 if (sc->sc_intr_ack != NULL) 1191 (*sc->sc_intr_ack)(sc); 1192 1193 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1194 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1195 1196 /* 1197 * Give the transmit and receive rings to the ADM8211. 1198 */ 1199 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1200 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1201 1202 /* common 802.11 configuration */ 1203 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1204 switch (ic->ic_opmode) { 1205 case IEEE80211_M_HOSTAP: /* XXX */ 1206 case IEEE80211_M_STA: 1207 sc->sc_opmode &= ~ATW_NAR_EA; 1208 break; 1209 case IEEE80211_M_AHDEMO: /* XXX */ 1210 case IEEE80211_M_IBSS: 1211 /* EA bit seems important for ad hoc reception. */ 1212 sc->sc_opmode |= ATW_NAR_EA; 1213 ic->ic_flags |= IEEE80211_F_IBSSON; 1214 break; 1215 case IEEE80211_M_MONITOR: /* XXX */ 1216 break; 1217 } 1218 1219 atw_start_beacon(sc, 0); 1220 1221 switch (ic->ic_opmode) { 1222 case IEEE80211_M_AHDEMO: 1223 case IEEE80211_M_HOSTAP: 1224 ic->ic_bss->ni_intval = ic->ic_lintval; 1225 ic->ic_bss->ni_rssi = 0; 1226 ic->ic_bss->ni_rstamp = 0; 1227 break; 1228 default: /* XXX */ 1229 break; 1230 } 1231 1232 atw_write_ssid(sc); 1233 atw_write_sup_rates(sc); 1234 if (ic->ic_caps & IEEE80211_C_WEP) 1235 atw_write_wep(sc); 1236 1237 /* 1238 * Set the receive filter. This will start the transmit and 1239 * receive processes. 1240 */ 1241 atw_filter_setup(sc); 1242 1243 /* 1244 * Start the receive process. 1245 */ 1246 ATW_WRITE(sc, ATW_RDR, 0x1); 1247 1248 /* 1249 * Note that the interface is now running. 1250 */ 1251 ifp->if_flags |= IFF_RUNNING; 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 ic->ic_state = IEEE80211_S_INIT; 1254 1255 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1256 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1257 else 1258 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1259 out: 1260 if (error) { 1261 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1262 ifp->if_timer = 0; 1263 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1264 } 1265 #ifdef ATW_DEBUG 1266 atw_print_regs(sc, "end of init"); 1267 #endif /* ATW_DEBUG */ 1268 1269 return (error); 1270 } 1271 1272 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1273 * 0: MAC control of RF3000/Si4126. 1274 * 1275 * Applies power, or selects RF front-end? Sets reset condition. 1276 * 1277 * TBD support non-RFMD BBP, non-SiLabs synth. 1278 */ 1279 static void 1280 atw_rfio_enable(struct atw_softc *sc, int enable) 1281 { 1282 if (enable) { 1283 ATW_WRITE(sc, ATW_SYNRF, 1284 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1285 DELAY(atw_rfio_enable_delay); 1286 } else { 1287 ATW_WRITE(sc, ATW_SYNRF, 0); 1288 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1289 } 1290 } 1291 1292 static int 1293 atw_tune(sc) 1294 struct atw_softc *sc; 1295 { 1296 int rc; 1297 u_int32_t reg; 1298 int chan; 1299 struct ieee80211com *ic = &sc->sc_ic; 1300 1301 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1302 if (chan == IEEE80211_CHAN_ANY) 1303 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1304 1305 if (chan == sc->sc_cur_chan) 1306 return 0; 1307 1308 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1309 sc->sc_cur_chan, chan)); 1310 1311 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1312 1313 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1314 (rc = atw_rf3000_tune(sc, chan)) != 0) 1315 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1316 chan); 1317 1318 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1319 ATW_WRITE(sc, ATW_CAP0, 1320 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1321 1322 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1323 1324 if (rc == 0) 1325 sc->sc_cur_chan = chan; 1326 1327 return rc; 1328 } 1329 1330 #ifdef ATW_DEBUG 1331 static void 1332 atw_si4126_print(sc) 1333 struct atw_softc *sc; 1334 { 1335 struct ifnet *ifp = &sc->sc_ic.ic_if; 1336 u_int addr, val; 1337 1338 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1339 return; 1340 1341 for (addr = 0; addr <= 8; addr++) { 1342 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1343 if (atw_si4126_read(sc, addr, &val) == 0) { 1344 printf("<unknown> (quitting print-out)\n"); 1345 break; 1346 } 1347 printf("%05x\n", val); 1348 } 1349 } 1350 #endif /* ATW_DEBUG */ 1351 1352 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1353 * 1354 * The RF/IF synthesizer produces two reference frequencies for 1355 * the RF2948B transceiver. The first frequency the RF2948B requires 1356 * is two times the so-called "intermediate frequency" (IF). Since 1357 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1358 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1359 * frequency required by the transceiver is the radio frequency 1360 * (RF). This is a superheterodyne transceiver; for f(chan) the 1361 * center frequency of the channel we are tuning, RF = f(chan) - 1362 * IF. 1363 * 1364 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1365 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1366 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1367 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1368 */ 1369 static int 1370 atw_si4126_tune(sc, chan) 1371 struct atw_softc *sc; 1372 u_int8_t chan; 1373 { 1374 int rc = 0; 1375 u_int mhz; 1376 u_int R; 1377 u_int32_t reg; 1378 u_int16_t gain; 1379 1380 #ifdef ATW_DEBUG 1381 atw_si4126_print(sc); 1382 #endif /* ATW_DEBUG */ 1383 1384 if (chan == 14) 1385 mhz = 2484; 1386 else 1387 mhz = 2412 + 5 * (chan - 1); 1388 1389 /* Tune IF to 748MHz to suit the IF LO input of the 1390 * RF2494B, which is 2 x IF. No need to set an IF divider 1391 * because an IF in 526MHz - 952MHz is allowed. 1392 * 1393 * XIN is 44.000MHz, so divide it by two to get allowable 1394 * range of 2-25MHz. SiLabs tells me that this is not 1395 * strictly necessary. 1396 */ 1397 1398 R = 44; 1399 1400 atw_rfio_enable(sc, 1); 1401 1402 /* Power-up RF, IF synthesizers. */ 1403 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1404 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1405 goto out; 1406 1407 /* If RF2 N > 2047, then set KP2 to 1. */ 1408 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1409 1410 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1411 goto out; 1412 1413 /* set LPWR, too? */ 1414 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1415 SI4126_MAIN_XINDIV2)) != 0) 1416 goto out; 1417 1418 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1419 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1420 */ 1421 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1422 goto out; 1423 1424 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1425 goto out; 1426 1427 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1428 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1429 * which has no RF1! 1430 */ 1431 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1432 goto out; 1433 1434 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1435 goto out; 1436 1437 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1438 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1439 * Now let's multiply it to mhz. So mhz - IF = N. 1440 */ 1441 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1442 goto out; 1443 1444 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1445 goto out; 1446 1447 /* wait 100us from power-up for RF, IF to settle */ 1448 DELAY(100); 1449 1450 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1451 /* XXX there is a binary driver which sends 1452 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1453 * that this enables the Si4126 by raising its PWDN#, but I 1454 * think that it actually sets the Prism RF front-end 1455 * to a special mode for channel 14. 1456 */ 1457 reg = ATW_READ(sc, ATW_GPIO); 1458 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1459 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1460 ATW_WRITE(sc, ATW_GPIO, reg); 1461 } 1462 1463 #ifdef ATW_DEBUG 1464 atw_si4126_print(sc); 1465 #endif /* ATW_DEBUG */ 1466 1467 out: 1468 atw_rfio_enable(sc, 0); 1469 1470 return rc; 1471 } 1472 1473 /* Baseline initialization of RF3000 BBP: set CCA mode, enable antenna 1474 * diversity, and write some magic. 1475 * 1476 * Call this w/ Tx/Rx suspended. 1477 */ 1478 static int 1479 atw_rf3000_init(sc) 1480 struct atw_softc *sc; 1481 { 1482 int rc = 0; 1483 1484 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1485 1486 atw_rfio_enable(sc, 1); 1487 1488 /* enable diversity */ 1489 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1490 1491 if (rc != 0) 1492 goto out; 1493 1494 /* sensible setting from a binary-only driver */ 1495 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1496 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 /* magic from a binary-only driver */ 1502 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1503 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1504 1505 if (rc != 0) 1506 goto out; 1507 1508 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1509 1510 if (rc != 0) 1511 goto out; 1512 1513 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1514 1515 if (rc != 0) 1516 goto out; 1517 1518 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1519 1520 if (rc != 0) 1521 goto out; 1522 1523 /* CCA is acquisition sensitive */ 1524 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1525 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1526 1527 if (rc != 0) 1528 goto out; 1529 1530 out: 1531 atw_rfio_enable(sc, 0); 1532 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1533 return rc; 1534 } 1535 1536 #ifdef ATW_DEBUG 1537 static void 1538 atw_rf3000_print(sc) 1539 struct atw_softc *sc; 1540 { 1541 struct ifnet *ifp = &sc->sc_ic.ic_if; 1542 u_int addr, val; 1543 1544 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1545 return; 1546 1547 for (addr = 0x01; addr <= 0x15; addr++) { 1548 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1549 if (atw_rf3000_read(sc, addr, &val) != 0) { 1550 printf("<unknown> (quitting print-out)\n"); 1551 break; 1552 } 1553 printf("%08x\n", val); 1554 } 1555 } 1556 #endif /* ATW_DEBUG */ 1557 1558 /* Set the power settings on the BBP for channel `chan'. */ 1559 static int 1560 atw_rf3000_tune(sc, chan) 1561 struct atw_softc *sc; 1562 u_int8_t chan; 1563 { 1564 int rc = 0; 1565 u_int32_t reg; 1566 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1567 1568 atw_rfio_enable(sc, 1); 1569 1570 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1571 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1572 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1573 1574 /* odd channels: LSB, even channels: MSB */ 1575 if (chan % 2 == 1) { 1576 txpower &= 0xFF; 1577 lpf_cutoff &= 0xFF; 1578 lna_gs_thresh &= 0xFF; 1579 } else { 1580 txpower >>= 8; 1581 lpf_cutoff >>= 8; 1582 lna_gs_thresh >>= 8; 1583 } 1584 1585 #ifdef ATW_DEBUG 1586 atw_rf3000_print(sc); 1587 #endif /* ATW_DEBUG */ 1588 1589 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1590 "lna_gs_thresh %02x\n", 1591 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1592 1593 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1594 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1595 goto out; 1596 1597 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1598 goto out; 1599 1600 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1601 goto out; 1602 1603 /* from a binary-only driver. */ 1604 reg = ATW_READ(sc, ATW_PLCPHD); 1605 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1606 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1607 ATW_WRITE(sc, ATW_PLCPHD, reg); 1608 1609 #ifdef ATW_DEBUG 1610 atw_rf3000_print(sc); 1611 #endif /* ATW_DEBUG */ 1612 1613 out: 1614 atw_rfio_enable(sc, 0); 1615 1616 return rc; 1617 } 1618 1619 /* Write a register on the RF3000 baseband processor using the 1620 * registers provided by the ADM8211 for this purpose. 1621 * 1622 * Return 0 on success. 1623 */ 1624 static int 1625 atw_rf3000_write(sc, addr, val) 1626 struct atw_softc *sc; 1627 u_int addr, val; 1628 { 1629 u_int32_t reg; 1630 int i; 1631 1632 for (i = 1000; --i >= 0; ) { 1633 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1634 break; 1635 DELAY(100); 1636 } 1637 1638 if (i < 0) { 1639 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1640 return ETIMEDOUT; 1641 } 1642 1643 reg = sc->sc_bbpctl_wr | 1644 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1645 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1646 1647 ATW_WRITE(sc, ATW_BBPCTL, reg); 1648 1649 for (i = 1000; --i >= 0; ) { 1650 DELAY(100); 1651 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1652 break; 1653 } 1654 1655 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1656 1657 if (i < 0) { 1658 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1659 return ETIMEDOUT; 1660 } 1661 return 0; 1662 } 1663 1664 /* Read a register on the RF3000 baseband processor using the registers 1665 * the ADM8211 provides for this purpose. 1666 * 1667 * The 7-bit register address is addr. Record the 8-bit data in the register 1668 * in *val. 1669 * 1670 * Return 0 on success. 1671 * 1672 * XXX This does not seem to work. The ADM8211 must require more or 1673 * different magic to read the chip than to write it. Possibly some 1674 * of the magic I have derived from a binary-only driver concerns 1675 * the "chip address" (see the RF3000 manual). 1676 */ 1677 #ifdef ATW_DEBUG 1678 static int 1679 atw_rf3000_read(sc, addr, val) 1680 struct atw_softc *sc; 1681 u_int addr, *val; 1682 { 1683 u_int32_t reg; 1684 int i; 1685 1686 for (i = 1000; --i >= 0; ) { 1687 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1688 break; 1689 DELAY(100); 1690 } 1691 1692 if (i < 0) { 1693 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1694 sc->sc_dev.dv_xname); 1695 return ETIMEDOUT; 1696 } 1697 1698 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1699 1700 ATW_WRITE(sc, ATW_BBPCTL, reg); 1701 1702 for (i = 1000; --i >= 0; ) { 1703 DELAY(100); 1704 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1705 break; 1706 } 1707 1708 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1709 1710 if (i < 0) { 1711 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1712 sc->sc_dev.dv_xname, reg); 1713 return ETIMEDOUT; 1714 } 1715 if (val != NULL) 1716 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1717 return 0; 1718 } 1719 #endif /* ATW_DEBUG */ 1720 1721 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1722 * provided by the ADM8211 for that purpose. 1723 * 1724 * val is 18 bits of data, and val is the 4-bit address of the register. 1725 * 1726 * Return 0 on success. 1727 */ 1728 static int 1729 atw_si4126_write(sc, addr, val) 1730 struct atw_softc *sc; 1731 u_int addr, val; 1732 { 1733 u_int32_t reg; 1734 int i; 1735 1736 for (i = 1000; --i >= 0; ) { 1737 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1738 break; 1739 DELAY(100); 1740 } 1741 1742 if (i < 0) { 1743 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1744 sc->sc_dev.dv_xname); 1745 return ETIMEDOUT; 1746 } 1747 1748 reg = sc->sc_synctl_wr | 1749 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1750 1751 ATW_WRITE(sc, ATW_SYNCTL, reg); 1752 1753 for (i = 1000; --i >= 0; ) { 1754 DELAY(100); 1755 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1756 break; 1757 } 1758 1759 /* restore to acceptable starting condition */ 1760 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1761 1762 if (i < 0) { 1763 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1764 sc->sc_dev.dv_xname, reg); 1765 return ETIMEDOUT; 1766 } 1767 return 0; 1768 } 1769 1770 /* Read 18-bit data from the 4-bit address addr in Si4126 1771 * RF synthesizer and write the data to *val. Return 0 on success. 1772 * 1773 * XXX This does not seem to work. The ADM8211 must require more or 1774 * different magic to read the chip than to write it. 1775 */ 1776 #ifdef ATW_DEBUG 1777 static int 1778 atw_si4126_read(sc, addr, val) 1779 struct atw_softc *sc; 1780 u_int addr; 1781 u_int *val; 1782 { 1783 u_int32_t reg; 1784 int i; 1785 1786 for (i = 1000; --i >= 0; ) { 1787 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1788 break; 1789 DELAY(100); 1790 } 1791 1792 if (i < 0) { 1793 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1794 sc->sc_dev.dv_xname); 1795 return ETIMEDOUT; 1796 } 1797 1798 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1799 1800 ATW_WRITE(sc, ATW_SYNCTL, reg); 1801 1802 for (i = 1000; --i >= 0; ) { 1803 DELAY(100); 1804 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1805 break; 1806 } 1807 1808 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1809 1810 if (i < 0) { 1811 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1812 sc->sc_dev.dv_xname, reg); 1813 return ETIMEDOUT; 1814 } 1815 if (val != NULL) 1816 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1817 ATW_SYNCTL_DATA_MASK); 1818 return 0; 1819 } 1820 #endif /* ATW_DEBUG */ 1821 1822 /* XXX is the endianness correct? test. */ 1823 #define atw_calchash(addr) \ 1824 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1825 1826 /* 1827 * atw_filter_setup: 1828 * 1829 * Set the ADM8211's receive filter. 1830 */ 1831 static void 1832 atw_filter_setup(sc) 1833 struct atw_softc *sc; 1834 { 1835 struct ieee80211com *ic = &sc->sc_ic; 1836 struct ethercom *ec = &ic->ic_ec; 1837 struct ifnet *ifp = &sc->sc_ic.ic_if; 1838 int hash; 1839 u_int32_t hashes[2] = { 0, 0 }; 1840 struct ether_multi *enm; 1841 struct ether_multistep step; 1842 1843 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1844 sc->sc_dev.dv_xname, sc->sc_flags)); 1845 1846 /* 1847 * If we're running, idle the receive engine. If we're NOT running, 1848 * we're being called from atw_init(), and our writing ATW_NAR will 1849 * start the transmit and receive processes in motion. 1850 */ 1851 if (ifp->if_flags & IFF_RUNNING) 1852 atw_idle(sc, ATW_NAR_SR); 1853 1854 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1855 1856 ifp->if_flags &= ~IFF_ALLMULTI; 1857 1858 if (ifp->if_flags & IFF_PROMISC) { 1859 sc->sc_opmode |= ATW_NAR_PR; 1860 allmulti: 1861 ifp->if_flags |= IFF_ALLMULTI; 1862 goto setit; 1863 } 1864 1865 /* 1866 * Program the 64-bit multicast hash filter. 1867 */ 1868 ETHER_FIRST_MULTI(step, ec, enm); 1869 while (enm != NULL) { 1870 /* XXX */ 1871 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1872 ETHER_ADDR_LEN) != 0) 1873 goto allmulti; 1874 1875 hash = atw_calchash(enm->enm_addrlo); 1876 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1877 ETHER_NEXT_MULTI(step, enm); 1878 } 1879 1880 if (ifp->if_flags & IFF_BROADCAST) { 1881 hash = atw_calchash(etherbroadcastaddr); 1882 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1883 } 1884 1885 /* all bits set => hash is useless */ 1886 if (~(hashes[0] & hashes[1]) == 0) 1887 goto allmulti; 1888 1889 setit: 1890 if (ifp->if_flags & IFF_ALLMULTI) 1891 sc->sc_opmode |= ATW_NAR_MM; 1892 1893 /* XXX in scan mode, do not filter packets. maybe this is 1894 * unnecessary. 1895 */ 1896 if (ic->ic_state == IEEE80211_S_SCAN) 1897 sc->sc_opmode |= ATW_NAR_PR; 1898 1899 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1900 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1901 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1902 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1903 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1904 1905 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1906 } 1907 1908 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1909 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1910 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1911 * no beacon with the preferred BSSID and SSID in the number of 1912 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1913 */ 1914 static void 1915 atw_write_bssid(sc) 1916 struct atw_softc *sc; 1917 { 1918 struct ieee80211com *ic = &sc->sc_ic; 1919 u_int8_t *bssid; 1920 1921 bssid = ic->ic_bss->ni_bssid; 1922 1923 ATW_WRITE(sc, ATW_ABDA1, 1924 (ATW_READ(sc, ATW_ABDA1) & 1925 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1926 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1927 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1928 1929 ATW_WRITE(sc, ATW_BSSID0, 1930 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1931 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1932 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1933 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1934 1935 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1936 ether_sprintf(sc->sc_bssid))); 1937 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1938 1939 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1940 } 1941 1942 /* Tell the ADM8211 how many beacon intervals must pass without 1943 * receiving a beacon with the preferred BSSID & SSID set by 1944 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1945 * raised. 1946 */ 1947 static void 1948 atw_write_bcn_thresh(sc) 1949 struct atw_softc *sc; 1950 { 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 int lost_bcn_thresh; 1953 1954 /* Lose link after one second or 7 beacons, whichever comes 1955 * first, but do not lose link before 2 beacons are lost. 1956 * 1957 * In host AP mode, set the lost-beacon threshold to 0. 1958 */ 1959 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1960 lost_bcn_thresh = 0; 1961 else 1962 lost_bcn_thresh = MAX(2, 1963 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss->ni_intval), 7)); 1964 1965 /* XXX resets wake-up status bits */ 1966 ATW_WRITE(sc, ATW_WCSR, 1967 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1968 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1969 1970 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1971 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1972 1973 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1974 1975 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1976 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1977 } 1978 1979 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1980 * 16-bit word. 1981 */ 1982 static void 1983 atw_write_sram(sc, ofs, buf, buflen) 1984 struct atw_softc *sc; 1985 u_int ofs; 1986 u_int8_t *buf; 1987 u_int buflen; 1988 { 1989 u_int i; 1990 u_int8_t *ptr; 1991 1992 memcpy(&sc->sc_sram[ofs], buf, buflen); 1993 1994 if (ofs % 2 != 0) { 1995 ofs--; 1996 buflen++; 1997 } 1998 1999 if (buflen % 2 != 0) 2000 buflen++; 2001 2002 assert(buflen + ofs <= ATW_SRAM_SIZE); 2003 2004 ptr = &sc->sc_sram[ofs]; 2005 2006 for (i = 0; i < buflen; i += 2) { 2007 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2008 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2009 DELAY(atw_writewep_delay); 2010 2011 ATW_WRITE(sc, ATW_WESK, 2012 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2013 DELAY(atw_writewep_delay); 2014 } 2015 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2016 2017 if (sc->sc_if.if_flags & IFF_DEBUG) { 2018 int n_octets = 0; 2019 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2020 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2021 for (i = 0; i < buflen; i++) { 2022 printf(" %02x", ptr[i]); 2023 if (++n_octets % 24 == 0) 2024 printf("\n"); 2025 } 2026 if (n_octets % 24 != 0) 2027 printf("\n"); 2028 } 2029 } 2030 2031 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2032 static void 2033 atw_write_wep(sc) 2034 struct atw_softc *sc; 2035 { 2036 struct ieee80211com *ic = &sc->sc_ic; 2037 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2038 u_int8_t buf[IEEE80211_WEP_NKID] 2039 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2040 u_int32_t reg; 2041 int i; 2042 2043 sc->sc_wepctl = 0; 2044 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2045 2046 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2047 return; 2048 2049 memset(&buf[0][0], 0, sizeof(buf)); 2050 2051 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2052 if (ic->ic_nw_keys[i].wk_len > 5) { 2053 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2054 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2055 buf[i][1] = ATW_WEP_ENABLED; 2056 } else { 2057 buf[i][1] = 0; 2058 continue; 2059 } 2060 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2061 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2062 ic->ic_nw_keys[i].wk_len - 1); 2063 } 2064 2065 reg = ATW_READ(sc, ATW_MACTEST); 2066 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2067 reg &= ~ATW_MACTEST_KEYID_MASK; 2068 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2069 ATW_WRITE(sc, ATW_MACTEST, reg); 2070 2071 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2072 * throughout.) 2073 */ 2074 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2075 if (sc->sc_if.if_flags & IFF_LINK2) 2076 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2077 2078 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2079 sizeof(buf)); 2080 } 2081 2082 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2083 2084 static void 2085 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2086 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2087 { 2088 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2089 2090 switch (subtype) { 2091 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2092 /* do nothing: hardware answers probe request */ 2093 break; 2094 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2095 case IEEE80211_FC0_SUBTYPE_BEACON: 2096 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2097 break; 2098 default: 2099 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2100 break; 2101 } 2102 return; 2103 } 2104 2105 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2106 * of IBSSs with like SSID/channel but different BSSID. It joins the 2107 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2108 * convention. Possibly the ADMtek chip does this for us; I will have 2109 * to test to find out. 2110 * 2111 * XXX we should add the duration field of the received beacon to 2112 * the TSF time it contains before comparing it with the ADM8211's 2113 * TSF. 2114 */ 2115 static void 2116 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2117 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2118 { 2119 struct atw_softc *sc; 2120 struct ieee80211_frame *wh; 2121 u_int64_t tsft, bcn_tsft; 2122 u_int32_t tsftl, tsfth; 2123 int do_print = 0; 2124 2125 sc = (struct atw_softc*)ic->ic_if.if_softc; 2126 2127 if (ic->ic_if.if_flags & IFF_DEBUG) 2128 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2129 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2130 2131 wh = mtod(m0, struct ieee80211_frame *); 2132 2133 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2134 2135 if (ic->ic_state != IEEE80211_S_RUN) { 2136 if (do_print) 2137 printf("%s: atw_recv_beacon: not running\n", 2138 sc->sc_dev.dv_xname); 2139 return; 2140 } 2141 2142 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2143 ic->ic_bss->ni_chan)) == NULL) { 2144 if (do_print) 2145 printf("%s: atw_recv_beacon: no node %s\n", 2146 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2147 return; 2148 } 2149 2150 if (ieee80211_match_bss(ic, ni) != 0) { 2151 if (do_print) 2152 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2153 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2154 return; 2155 } 2156 2157 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2158 return; 2159 2160 if (do_print) 2161 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2162 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2163 2164 if (ic->ic_opmode != IEEE80211_M_IBSS) 2165 return; 2166 2167 /* If we read TSFTL right before rollover, we read a TSF timer 2168 * that is too high rather than too low. This prevents a spurious 2169 * synchronization down the line, however, our IBSS could suffer 2170 * from a creeping TSF.... 2171 */ 2172 tsftl = ATW_READ(sc, ATW_TSFTL); 2173 tsfth = ATW_READ(sc, ATW_TSFTH); 2174 2175 tsft = (u_int64_t)tsfth << 32 | tsftl; 2176 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2177 2178 if (do_print) 2179 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2180 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2181 2182 /* we are faster, let the other guy catch up */ 2183 if (bcn_tsft < tsft) 2184 return; 2185 2186 if (do_print) 2187 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2188 ether_sprintf(wh->i_addr2)); 2189 2190 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2191 2192 #if 0 2193 atw_tsf(sc); 2194 #endif 2195 2196 /* negotiate rates with new IBSS */ 2197 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2198 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2199 if (ni->ni_rates.rs_nrates == 0) { 2200 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2201 ether_sprintf(ni->ni_bssid)); 2202 return; 2203 } 2204 2205 if (do_print) { 2206 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2207 ether_sprintf(ic->ic_bss->ni_bssid)); 2208 printf("%s ", ether_sprintf(ni->ni_bssid)); 2209 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2210 } 2211 2212 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2213 2214 atw_write_bssid(sc); 2215 atw_write_bcn_thresh(sc); 2216 atw_start_beacon(sc, 1); 2217 } 2218 2219 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2220 * In ad hoc mode, the SSID is written to the beacons sent by the 2221 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2222 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2223 * indications. 2224 */ 2225 static void 2226 atw_write_ssid(sc) 2227 struct atw_softc *sc; 2228 { 2229 struct ieee80211com *ic = &sc->sc_ic; 2230 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2231 u_int8_t buf[1 /* length */ + IEEE80211_NWID_LEN + 2232 1 /* for a round number */]; 2233 2234 memset(buf, 0, sizeof(buf)); 2235 buf[0] = ic->ic_bss->ni_esslen; 2236 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2237 2238 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2239 } 2240 2241 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2242 * In ad hoc mode, the supported rates are written to beacons sent by the 2243 * ADM8211. 2244 */ 2245 static void 2246 atw_write_sup_rates(sc) 2247 struct atw_softc *sc; 2248 { 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2251 * supported rates 2252 */ 2253 u_int8_t buf[1 /* length */ + IEEE80211_RATE_SIZE + 2254 1 /* for a round number */]; 2255 2256 memset(buf, 0, sizeof(buf)); 2257 2258 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2259 2260 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2261 ic->ic_bss->ni_rates.rs_nrates); 2262 2263 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2264 } 2265 2266 /* Start/stop sending beacons. */ 2267 void 2268 atw_start_beacon(struct atw_softc *sc, int start) 2269 { 2270 struct ieee80211com *ic = &sc->sc_ic; 2271 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2272 2273 if (ATW_IS_ENABLED(sc) == 0) 2274 return; 2275 2276 len = capinfo = 0; 2277 2278 /* start beacons */ 2279 len = sizeof(struct ieee80211_frame) + 2280 8 /* timestamp */ + 2 /* beacon interval */ + 2281 2 /* capability info */ + 2282 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2283 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2284 3 /* DS parameters */ + 2285 IEEE80211_CRC_LEN; 2286 2287 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2288 2289 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2290 2291 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2292 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2293 2294 if (!start) 2295 return; 2296 2297 /* TBD use ni_capinfo */ 2298 2299 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2300 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2301 if (ic->ic_flags & IEEE80211_F_WEPON) 2302 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2303 2304 switch (ic->ic_opmode) { 2305 case IEEE80211_M_IBSS: 2306 len += 4; /* IBSS parameters */ 2307 capinfo |= IEEE80211_CAPINFO_IBSS; 2308 break; 2309 case IEEE80211_M_HOSTAP: 2310 /* XXX 6-byte minimum TIM */ 2311 len += atw_beacon_len_adjust; 2312 capinfo |= IEEE80211_CAPINFO_ESS; 2313 break; 2314 default: 2315 return; 2316 } 2317 2318 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2319 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2320 2321 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2322 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2323 2324 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2325 sc->sc_dev.dv_xname, reg_bcnt)); 2326 2327 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2328 sc->sc_dev.dv_xname, reg_cap1)); 2329 } 2330 2331 /* First beacon was sent at time 0 microseconds, current time is 2332 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2333 * microseconds. Return the expected time in microseconds for the 2334 * beacon after next. 2335 */ 2336 static __inline u_int64_t 2337 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2338 { 2339 return tsft + (tbtt - tsft % tbtt); 2340 } 2341 2342 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2343 * the ieee80211com. 2344 * 2345 * Predict the next target beacon transmission time (TBTT) and 2346 * write it to the ADM8211. 2347 */ 2348 static void 2349 atw_tsf(struct atw_softc *sc) 2350 { 2351 #define TBTTOFS 20 /* TU */ 2352 2353 struct ieee80211com *ic = &sc->sc_ic; 2354 u_int64_t tsft, tbtt; 2355 2356 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2357 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2358 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2359 tsft = ATW_READ(sc, ATW_TSFTH); 2360 tsft <<= 32; 2361 tsft |= ATW_READ(sc, ATW_TSFTL); 2362 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2363 } else 2364 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2365 2366 tbtt = atw_predict_beacon(tsft, 2367 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2368 2369 /* skip one more beacon so that the TBTT cannot pass before 2370 * we've programmed it, and also so that we can subtract a 2371 * few TU so that we wake a little before TBTT. 2372 */ 2373 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2374 2375 /* wake up a little early */ 2376 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2377 2378 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2379 sc->sc_dev.dv_xname, tsft, tbtt)); 2380 2381 ATW_WRITE(sc, ATW_TOFS1, 2382 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2383 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2384 LSHIFT( 2385 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2386 ATW_TOFS1_TBTTPRE_MASK)); 2387 #undef TBTTOFS 2388 } 2389 2390 static void 2391 atw_next_scan(void *arg) 2392 { 2393 struct atw_softc *sc = arg; 2394 struct ieee80211com *ic = &sc->sc_ic; 2395 struct ifnet *ifp = &ic->ic_if; 2396 int s; 2397 2398 /* don't call atw_start w/o network interrupts blocked */ 2399 s = splnet(); 2400 if (ic->ic_state == IEEE80211_S_SCAN) 2401 ieee80211_next_scan(ifp); 2402 splx(s); 2403 } 2404 2405 /* Synchronize the hardware state with the software state. */ 2406 static int 2407 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2408 { 2409 struct ifnet *ifp = &ic->ic_if; 2410 struct atw_softc *sc = ifp->if_softc; 2411 enum ieee80211_state ostate; 2412 int error; 2413 2414 ostate = ic->ic_state; 2415 2416 if (nstate == IEEE80211_S_INIT) { 2417 callout_stop(&sc->sc_scan_ch); 2418 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2419 atw_start_beacon(sc, 0); 2420 return (*sc->sc_newstate)(ic, nstate, arg); 2421 } 2422 2423 if ((error = atw_tune(sc)) != 0) 2424 return error; 2425 2426 switch (nstate) { 2427 case IEEE80211_S_ASSOC: 2428 break; 2429 case IEEE80211_S_INIT: 2430 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2431 break; 2432 case IEEE80211_S_SCAN: 2433 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2434 atw_write_bssid(sc); 2435 2436 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2437 atw_next_scan, sc); 2438 2439 break; 2440 case IEEE80211_S_RUN: 2441 if (ic->ic_opmode == IEEE80211_M_STA) 2442 break; 2443 /*FALLTHROUGH*/ 2444 case IEEE80211_S_AUTH: 2445 atw_write_bssid(sc); 2446 atw_write_bcn_thresh(sc); 2447 atw_write_ssid(sc); 2448 atw_write_sup_rates(sc); 2449 2450 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2451 ic->ic_opmode == IEEE80211_M_MONITOR) 2452 break; 2453 2454 /* set listen interval 2455 * XXX do software units agree w/ hardware? 2456 */ 2457 ATW_WRITE(sc, ATW_BPLI, 2458 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2459 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2460 ATW_BPLI_LI_MASK)); 2461 2462 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2463 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2464 2465 atw_tsf(sc); 2466 break; 2467 } 2468 2469 if (nstate != IEEE80211_S_SCAN) 2470 callout_stop(&sc->sc_scan_ch); 2471 2472 if (nstate == IEEE80211_S_RUN && 2473 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2474 ic->ic_opmode == IEEE80211_M_IBSS)) 2475 atw_start_beacon(sc, 1); 2476 else 2477 atw_start_beacon(sc, 0); 2478 2479 return (*sc->sc_newstate)(ic, nstate, arg); 2480 } 2481 2482 /* 2483 * atw_add_rxbuf: 2484 * 2485 * Add a receive buffer to the indicated descriptor. 2486 */ 2487 int 2488 atw_add_rxbuf(sc, idx) 2489 struct atw_softc *sc; 2490 int idx; 2491 { 2492 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2493 struct mbuf *m; 2494 int error; 2495 2496 MGETHDR(m, M_DONTWAIT, MT_DATA); 2497 if (m == NULL) 2498 return (ENOBUFS); 2499 2500 MCLGET(m, M_DONTWAIT); 2501 if ((m->m_flags & M_EXT) == 0) { 2502 m_freem(m); 2503 return (ENOBUFS); 2504 } 2505 2506 if (rxs->rxs_mbuf != NULL) 2507 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2508 2509 rxs->rxs_mbuf = m; 2510 2511 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2512 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2513 BUS_DMA_READ|BUS_DMA_NOWAIT); 2514 if (error) { 2515 printf("%s: can't load rx DMA map %d, error = %d\n", 2516 sc->sc_dev.dv_xname, idx, error); 2517 panic("atw_add_rxbuf"); /* XXX */ 2518 } 2519 2520 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2521 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2522 2523 ATW_INIT_RXDESC(sc, idx); 2524 2525 return (0); 2526 } 2527 2528 /* 2529 * atw_stop: [ ifnet interface function ] 2530 * 2531 * Stop transmission on the interface. 2532 */ 2533 void 2534 atw_stop(ifp, disable) 2535 struct ifnet *ifp; 2536 int disable; 2537 { 2538 struct atw_softc *sc = ifp->if_softc; 2539 struct ieee80211com *ic = &sc->sc_ic; 2540 struct atw_txsoft *txs; 2541 2542 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2543 2544 /* Disable interrupts. */ 2545 ATW_WRITE(sc, ATW_IER, 0); 2546 2547 /* Stop the transmit and receive processes. */ 2548 sc->sc_opmode = 0; 2549 ATW_WRITE(sc, ATW_NAR, 0); 2550 ATW_WRITE(sc, ATW_TDBD, 0); 2551 ATW_WRITE(sc, ATW_TDBP, 0); 2552 ATW_WRITE(sc, ATW_RDB, 0); 2553 2554 /* 2555 * Release any queued transmit buffers. 2556 */ 2557 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2558 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2559 if (txs->txs_mbuf != NULL) { 2560 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2561 m_freem(txs->txs_mbuf); 2562 txs->txs_mbuf = NULL; 2563 } 2564 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2565 } 2566 2567 if (disable) { 2568 atw_rxdrain(sc); 2569 atw_disable(sc); 2570 } 2571 2572 /* 2573 * Mark the interface down and cancel the watchdog timer. 2574 */ 2575 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2576 ifp->if_timer = 0; 2577 2578 /* XXX */ 2579 atw_reset(sc); 2580 } 2581 2582 /* 2583 * atw_rxdrain: 2584 * 2585 * Drain the receive queue. 2586 */ 2587 void 2588 atw_rxdrain(sc) 2589 struct atw_softc *sc; 2590 { 2591 struct atw_rxsoft *rxs; 2592 int i; 2593 2594 for (i = 0; i < ATW_NRXDESC; i++) { 2595 rxs = &sc->sc_rxsoft[i]; 2596 if (rxs->rxs_mbuf == NULL) 2597 continue; 2598 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2599 m_freem(rxs->rxs_mbuf); 2600 rxs->rxs_mbuf = NULL; 2601 } 2602 } 2603 2604 /* 2605 * atw_detach: 2606 * 2607 * Detach an ADM8211 interface. 2608 */ 2609 int 2610 atw_detach(sc) 2611 struct atw_softc *sc; 2612 { 2613 struct ifnet *ifp = &sc->sc_ic.ic_if; 2614 struct atw_rxsoft *rxs; 2615 struct atw_txsoft *txs; 2616 int i; 2617 2618 /* 2619 * Succeed now if there isn't any work to do. 2620 */ 2621 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2622 return (0); 2623 2624 ieee80211_ifdetach(ifp); 2625 if_detach(ifp); 2626 2627 for (i = 0; i < ATW_NRXDESC; i++) { 2628 rxs = &sc->sc_rxsoft[i]; 2629 if (rxs->rxs_mbuf != NULL) { 2630 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2631 m_freem(rxs->rxs_mbuf); 2632 rxs->rxs_mbuf = NULL; 2633 } 2634 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2635 } 2636 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2637 txs = &sc->sc_txsoft[i]; 2638 if (txs->txs_mbuf != NULL) { 2639 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2640 m_freem(txs->txs_mbuf); 2641 txs->txs_mbuf = NULL; 2642 } 2643 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2644 } 2645 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2646 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2647 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2648 sizeof(struct atw_control_data)); 2649 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2650 2651 shutdownhook_disestablish(sc->sc_sdhook); 2652 powerhook_disestablish(sc->sc_powerhook); 2653 2654 if (sc->sc_srom) 2655 free(sc->sc_srom, M_DEVBUF); 2656 2657 return (0); 2658 } 2659 2660 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2661 void 2662 atw_shutdown(arg) 2663 void *arg; 2664 { 2665 struct atw_softc *sc = arg; 2666 2667 atw_stop(&sc->sc_ic.ic_if, 1); 2668 } 2669 2670 int 2671 atw_intr(arg) 2672 void *arg; 2673 { 2674 struct atw_softc *sc = arg; 2675 struct ifnet *ifp = &sc->sc_ic.ic_if; 2676 u_int32_t status, rxstatus, txstatus, linkstatus; 2677 int handled = 0, txthresh; 2678 2679 #ifdef DEBUG 2680 if (ATW_IS_ENABLED(sc) == 0) 2681 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2682 #endif 2683 2684 /* 2685 * If the interface isn't running, the interrupt couldn't 2686 * possibly have come from us. 2687 */ 2688 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2689 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2690 return (0); 2691 2692 for (;;) { 2693 status = ATW_READ(sc, ATW_STSR); 2694 2695 if (status) 2696 ATW_WRITE(sc, ATW_STSR, status); 2697 2698 if (sc->sc_intr_ack != NULL) 2699 (*sc->sc_intr_ack)(sc); 2700 2701 #ifdef ATW_DEBUG 2702 #define PRINTINTR(flag) do { \ 2703 if ((status & flag) != 0) { \ 2704 printf("%s" #flag, delim); \ 2705 delim = ","; \ 2706 } \ 2707 } while (0) 2708 2709 if (atw_debug > 1 && status) { 2710 const char *delim = "<"; 2711 2712 printf("%s: reg[STSR] = %x", 2713 sc->sc_dev.dv_xname, status); 2714 2715 PRINTINTR(ATW_INTR_FBE); 2716 PRINTINTR(ATW_INTR_LINKOFF); 2717 PRINTINTR(ATW_INTR_LINKON); 2718 PRINTINTR(ATW_INTR_RCI); 2719 PRINTINTR(ATW_INTR_RDU); 2720 PRINTINTR(ATW_INTR_RPS); 2721 PRINTINTR(ATW_INTR_TCI); 2722 PRINTINTR(ATW_INTR_TDU); 2723 PRINTINTR(ATW_INTR_TLT); 2724 PRINTINTR(ATW_INTR_TPS); 2725 PRINTINTR(ATW_INTR_TRT); 2726 PRINTINTR(ATW_INTR_TUF); 2727 PRINTINTR(ATW_INTR_BCNTC); 2728 PRINTINTR(ATW_INTR_ATIME); 2729 PRINTINTR(ATW_INTR_TBTT); 2730 PRINTINTR(ATW_INTR_TSCZ); 2731 PRINTINTR(ATW_INTR_TSFTF); 2732 printf(">\n"); 2733 } 2734 #undef PRINTINTR 2735 #endif /* ATW_DEBUG */ 2736 2737 if ((status & sc->sc_inten) == 0) 2738 break; 2739 2740 handled = 1; 2741 2742 rxstatus = status & sc->sc_rxint_mask; 2743 txstatus = status & sc->sc_txint_mask; 2744 linkstatus = status & sc->sc_linkint_mask; 2745 2746 if (linkstatus) { 2747 atw_linkintr(sc, linkstatus); 2748 } 2749 2750 if (rxstatus) { 2751 /* Grab any new packets. */ 2752 atw_rxintr(sc); 2753 2754 if (rxstatus & ATW_INTR_RDU) { 2755 printf("%s: receive ring overrun\n", 2756 sc->sc_dev.dv_xname); 2757 /* Get the receive process going again. */ 2758 ATW_WRITE(sc, ATW_RDR, 0x1); 2759 break; 2760 } 2761 } 2762 2763 if (txstatus) { 2764 /* Sweep up transmit descriptors. */ 2765 atw_txintr(sc); 2766 2767 if (txstatus & ATW_INTR_TLT) 2768 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2769 sc->sc_dev.dv_xname)); 2770 2771 if (txstatus & ATW_INTR_TRT) 2772 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2773 sc->sc_dev.dv_xname)); 2774 2775 /* If Tx under-run, increase our transmit threshold 2776 * if another is available. 2777 */ 2778 txthresh = sc->sc_txthresh + 1; 2779 if ((txstatus & ATW_INTR_TUF) && 2780 sc->sc_txth[txthresh].txth_name != NULL) { 2781 /* Idle the transmit process. */ 2782 atw_idle(sc, ATW_NAR_ST); 2783 2784 sc->sc_txthresh = txthresh; 2785 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2786 sc->sc_opmode |= 2787 sc->sc_txth[txthresh].txth_opmode; 2788 printf("%s: transmit underrun; new " 2789 "threshold: %s\n", sc->sc_dev.dv_xname, 2790 sc->sc_txth[txthresh].txth_name); 2791 2792 /* Set the new threshold and restart 2793 * the transmit process. 2794 */ 2795 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2796 /* XXX Log every Nth underrun from 2797 * XXX now on? 2798 */ 2799 } 2800 } 2801 2802 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2803 if (status & ATW_INTR_TPS) 2804 printf("%s: transmit process stopped\n", 2805 sc->sc_dev.dv_xname); 2806 if (status & ATW_INTR_RPS) 2807 printf("%s: receive process stopped\n", 2808 sc->sc_dev.dv_xname); 2809 (void)atw_init(ifp); 2810 break; 2811 } 2812 2813 if (status & ATW_INTR_FBE) { 2814 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2815 (void)atw_init(ifp); 2816 break; 2817 } 2818 2819 /* 2820 * Not handled: 2821 * 2822 * Transmit buffer unavailable -- normal 2823 * condition, nothing to do, really. 2824 * 2825 * Early receive interrupt -- not available on 2826 * all chips, we just use RI. We also only 2827 * use single-segment receive DMA, so this 2828 * is mostly useless. 2829 * 2830 * TBD others 2831 */ 2832 } 2833 2834 /* Try to get more packets going. */ 2835 atw_start(ifp); 2836 2837 return (handled); 2838 } 2839 2840 /* 2841 * atw_idle: 2842 * 2843 * Cause the transmit and/or receive processes to go idle. 2844 * 2845 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2846 * process in STSR if I clear SR or ST after the process has already 2847 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2848 * do not seem to be too reliable. Perhaps I have the sense of the 2849 * Rx bits switched with the Tx bits? 2850 */ 2851 void 2852 atw_idle(sc, bits) 2853 struct atw_softc *sc; 2854 u_int32_t bits; 2855 { 2856 u_int32_t ackmask = 0, opmode, stsr, test0; 2857 int i, s; 2858 2859 /* without this, somehow we run concurrently w/ interrupt handler */ 2860 s = splnet(); 2861 2862 opmode = sc->sc_opmode & ~bits; 2863 2864 if (bits & ATW_NAR_SR) 2865 ackmask |= ATW_INTR_RPS; 2866 2867 if (bits & ATW_NAR_ST) { 2868 ackmask |= ATW_INTR_TPS; 2869 /* set ATW_NAR_HF to flush TX FIFO. */ 2870 opmode |= ATW_NAR_HF; 2871 } 2872 2873 ATW_WRITE(sc, ATW_NAR, opmode); 2874 2875 for (i = 0; i < 1000; i++) { 2876 stsr = ATW_READ(sc, ATW_STSR); 2877 if ((stsr & ackmask) == ackmask) 2878 break; 2879 DELAY(10); 2880 } 2881 2882 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2883 2884 if ((stsr & ackmask) == ackmask) 2885 goto out; 2886 2887 test0 = ATW_READ(sc, ATW_TEST0); 2888 2889 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2890 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2891 printf("%s: transmit process not idle [%s]\n", 2892 sc->sc_dev.dv_xname, 2893 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2894 printf("%s: bits %08x test0 %08x stsr %08x\n", 2895 sc->sc_dev.dv_xname, bits, test0, stsr); 2896 } 2897 2898 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2899 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2900 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2901 sc->sc_dev.dv_xname, 2902 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2903 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2904 sc->sc_dev.dv_xname, bits, test0, stsr)); 2905 } 2906 out: 2907 splx(s); 2908 return; 2909 } 2910 2911 /* 2912 * atw_linkintr: 2913 * 2914 * Helper; handle link-status interrupts. 2915 */ 2916 void 2917 atw_linkintr(sc, linkstatus) 2918 struct atw_softc *sc; 2919 u_int32_t linkstatus; 2920 { 2921 struct ieee80211com *ic = &sc->sc_ic; 2922 2923 if (ic->ic_state != IEEE80211_S_RUN) 2924 return; 2925 2926 if (linkstatus & ATW_INTR_LINKON) { 2927 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2928 sc->sc_rescan_timer = 0; 2929 } else if (linkstatus & ATW_INTR_LINKOFF) { 2930 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2931 switch (ic->ic_opmode) { 2932 case IEEE80211_M_IBSS: 2933 if (ic->ic_flags & IEEE80211_F_SIBSS) 2934 return; 2935 /* FALL THROUGH */ 2936 case IEEE80211_M_STA: 2937 sc->sc_rescan_timer = 3; 2938 ic->ic_if.if_timer = 1; 2939 break; 2940 default: 2941 break; 2942 } 2943 } 2944 } 2945 2946 /* 2947 * atw_rxintr: 2948 * 2949 * Helper; handle receive interrupts. 2950 */ 2951 void 2952 atw_rxintr(sc) 2953 struct atw_softc *sc; 2954 { 2955 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2956 struct ieee80211com *ic = &sc->sc_ic; 2957 struct ieee80211_node *ni; 2958 struct ieee80211_frame *wh; 2959 struct ifnet *ifp = &ic->ic_if; 2960 struct atw_rxsoft *rxs; 2961 struct mbuf *m; 2962 u_int32_t rxstat; 2963 int i, len, rate, rate0, rssi; 2964 2965 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2966 rxs = &sc->sc_rxsoft[i]; 2967 2968 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2969 2970 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2971 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2972 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2973 2974 if (rxstat & ATW_RXSTAT_OWN) 2975 break; /* We have processed all receive buffers. */ 2976 2977 ATW_DPRINTF3(("%s: rssi %d\n", sc->sc_dev.dv_xname, rssi)); 2978 2979 /* 2980 * Make sure the packet fit in one buffer. This should 2981 * always be the case. 2982 */ 2983 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2984 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2985 printf("%s: incoming packet spilled, resetting\n", 2986 sc->sc_dev.dv_xname); 2987 (void)atw_init(ifp); 2988 return; 2989 } 2990 2991 /* 2992 * If an error occurred, update stats, clear the status 2993 * word, and leave the packet buffer in place. It will 2994 * simply be reused the next time the ring comes around. 2995 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2996 * error. 2997 */ 2998 2999 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3000 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3001 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3002 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3003 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3004 ATW_RXSTAT_ICVE)) != 0)) { 3005 #define PRINTERR(bit, str) \ 3006 if (rxstat & (bit)) \ 3007 printf("%s: receive error: %s\n", \ 3008 sc->sc_dev.dv_xname, str) 3009 ifp->if_ierrors++; 3010 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3011 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3012 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3013 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3014 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3015 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3016 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3017 #undef PRINTERR 3018 ATW_INIT_RXDESC(sc, i); 3019 continue; 3020 } 3021 3022 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3023 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3024 3025 /* 3026 * No errors; receive the packet. Note the ADM8211 3027 * includes the CRC in promiscuous mode. 3028 */ 3029 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3030 3031 /* 3032 * Allocate a new mbuf cluster. If that fails, we are 3033 * out of memory, and must drop the packet and recycle 3034 * the buffer that's already attached to this descriptor. 3035 */ 3036 m = rxs->rxs_mbuf; 3037 if (atw_add_rxbuf(sc, i) != 0) { 3038 ifp->if_ierrors++; 3039 ATW_INIT_RXDESC(sc, i); 3040 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3041 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3042 continue; 3043 } 3044 3045 ifp->if_ipackets++; 3046 if (sc->sc_opmode & ATW_NAR_PR) 3047 m->m_flags |= M_HASFCS; 3048 m->m_pkthdr.rcvif = ifp; 3049 m->m_pkthdr.len = m->m_len = len; 3050 3051 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3052 rate = 0; 3053 else 3054 rate = rate_tbl[rate0]; 3055 3056 #if NBPFILTER > 0 3057 /* Pass this up to any BPF listeners. */ 3058 if (sc->sc_radiobpf != NULL) { 3059 struct mbuf mb; 3060 3061 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3062 3063 tap->ar_rate = rate; 3064 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3065 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3066 3067 /* TBD verify units are dB */ 3068 tap->ar_antsignal = rssi; 3069 /* TBD tap->ar_flags */ 3070 3071 M_COPY_PKTHDR(&mb, m); 3072 mb.m_data = (caddr_t)tap; 3073 mb.m_len = tap->ar_ihdr.it_len; 3074 mb.m_next = m; 3075 mb.m_pkthdr.len += mb.m_len; 3076 bpf_mtap(sc->sc_radiobpf, &mb); 3077 } 3078 #endif /* NPBFILTER > 0 */ 3079 3080 wh = mtod(m, struct ieee80211_frame *); 3081 ni = ieee80211_find_rxnode(ic, wh); 3082 ieee80211_input(ifp, m, ni, rssi, 0); 3083 /* 3084 * The frame may have caused the node to be marked for 3085 * reclamation (e.g. in response to a DEAUTH message) 3086 * so use free_node here instead of unref_node. 3087 */ 3088 if (ni == ic->ic_bss) 3089 ieee80211_unref_node(&ni); 3090 else 3091 ieee80211_free_node(ic, ni); 3092 } 3093 3094 /* Update the receive pointer. */ 3095 sc->sc_rxptr = i; 3096 } 3097 3098 /* 3099 * atw_txintr: 3100 * 3101 * Helper; handle transmit interrupts. 3102 */ 3103 void 3104 atw_txintr(sc) 3105 struct atw_softc *sc; 3106 { 3107 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3108 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3109 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3110 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3111 3112 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3113 struct ifnet *ifp = &sc->sc_ic.ic_if; 3114 struct atw_txsoft *txs; 3115 u_int32_t txstat; 3116 3117 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3118 sc->sc_dev.dv_xname, sc->sc_flags)); 3119 3120 ifp->if_flags &= ~IFF_OACTIVE; 3121 3122 /* 3123 * Go through our Tx list and free mbufs for those 3124 * frames that have been transmitted. 3125 */ 3126 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3127 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3128 txs->txs_ndescs, 3129 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3130 3131 #ifdef ATW_DEBUG 3132 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3133 int i; 3134 printf(" txsoft %p transmit chain:\n", txs); 3135 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3136 printf(" descriptor %d:\n", i); 3137 printf(" at_status: 0x%08x\n", 3138 le32toh(sc->sc_txdescs[i].at_stat)); 3139 printf(" at_flags: 0x%08x\n", 3140 le32toh(sc->sc_txdescs[i].at_flags)); 3141 printf(" at_buf1: 0x%08x\n", 3142 le32toh(sc->sc_txdescs[i].at_buf1)); 3143 printf(" at_buf2: 0x%08x\n", 3144 le32toh(sc->sc_txdescs[i].at_buf2)); 3145 if (i == txs->txs_lastdesc) 3146 break; 3147 } 3148 } 3149 #endif 3150 3151 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3152 if (txstat & ATW_TXSTAT_OWN) 3153 break; 3154 3155 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3156 3157 sc->sc_txfree += txs->txs_ndescs; 3158 3159 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3160 0, txs->txs_dmamap->dm_mapsize, 3161 BUS_DMASYNC_POSTWRITE); 3162 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3163 m_freem(txs->txs_mbuf); 3164 txs->txs_mbuf = NULL; 3165 3166 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3167 3168 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3169 (txstat & TXSTAT_ERRMASK) != 0) { 3170 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3171 txstat_buf, sizeof(txstat_buf)); 3172 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3173 txstat_buf, 3174 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3175 } 3176 3177 /* 3178 * Check for errors and collisions. 3179 */ 3180 if (txstat & ATW_TXSTAT_TUF) 3181 sc->sc_stats.ts_tx_tuf++; 3182 if (txstat & ATW_TXSTAT_TLT) 3183 sc->sc_stats.ts_tx_tlt++; 3184 if (txstat & ATW_TXSTAT_TRT) 3185 sc->sc_stats.ts_tx_trt++; 3186 if (txstat & ATW_TXSTAT_TRO) 3187 sc->sc_stats.ts_tx_tro++; 3188 if (txstat & ATW_TXSTAT_SOFBR) { 3189 sc->sc_stats.ts_tx_sofbr++; 3190 } 3191 3192 if ((txstat & ATW_TXSTAT_ES) == 0) 3193 ifp->if_collisions += 3194 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3195 else 3196 ifp->if_oerrors++; 3197 3198 ifp->if_opackets++; 3199 } 3200 3201 /* 3202 * If there are no more pending transmissions, cancel the watchdog 3203 * timer. 3204 */ 3205 if (txs == NULL) 3206 sc->sc_tx_timer = 0; 3207 #undef TXSTAT_ERRMASK 3208 #undef TXSTAT_FMT 3209 } 3210 3211 /* 3212 * atw_watchdog: [ifnet interface function] 3213 * 3214 * Watchdog timer handler. 3215 */ 3216 void 3217 atw_watchdog(ifp) 3218 struct ifnet *ifp; 3219 { 3220 struct atw_softc *sc = ifp->if_softc; 3221 struct ieee80211com *ic = &sc->sc_ic; 3222 3223 ifp->if_timer = 0; 3224 if (ATW_IS_ENABLED(sc) == 0) 3225 return; 3226 3227 if (sc->sc_rescan_timer) { 3228 if (--sc->sc_rescan_timer == 0) 3229 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3230 } 3231 if (sc->sc_tx_timer) { 3232 if (--sc->sc_tx_timer == 0 && 3233 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3234 printf("%s: transmit timeout\n", ifp->if_xname); 3235 ifp->if_oerrors++; 3236 (void)atw_init(ifp); 3237 atw_start(ifp); 3238 } 3239 } 3240 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3241 ifp->if_timer = 1; 3242 ieee80211_watchdog(ifp); 3243 } 3244 3245 /* Compute the 802.11 Duration field and the PLCP Length fields for 3246 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3247 * Write the fields to the ADM8211 Tx header, frm. 3248 * 3249 * TBD use the fragmentation threshold to find the right duration for 3250 * the first & last fragments. 3251 * 3252 * TBD make certain of the duration fields applied by the ADM8211 to each 3253 * fragment. I think that the ADM8211 knows how to subtract the CTS 3254 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3255 * I also think that the ADM8211 does *some* arithmetic for us, because 3256 * otherwise I think we would have to set a first duration for CTS/first 3257 * fragment, a second duration for fragments between the first and the 3258 * last, and a third duration for the last fragment. 3259 * 3260 * TBD make certain that duration fields reflect addition of FCS/WEP 3261 * and correct duration arithmetic as necessary. 3262 */ 3263 static void 3264 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3265 int len) 3266 { 3267 int remainder; 3268 3269 /* deal also with encrypted fragments */ 3270 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3271 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3272 sc->sc_dev.dv_xname)); 3273 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3274 IEEE80211_WEP_CRCLEN; 3275 } 3276 3277 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3278 * duration (XXX added by MAC?). 3279 */ 3280 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3281 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3282 3283 if (rate <= 4) 3284 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3285 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3286 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3287 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3288 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3289 else 3290 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3291 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3292 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3293 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3294 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3295 3296 /* lengthen duration if long preamble */ 3297 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3298 frm->atw_head_dur += 3299 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3300 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3301 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3302 IEEE80211_DUR_DS_FAST_PLCPHDR); 3303 3304 if (remainder != 0) 3305 frm->atw_head_dur++; 3306 3307 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3308 (rate == 2 || rate == 4)) { 3309 /* derived from Linux: how could this be right? */ 3310 frm->atw_head_plcplen = frm->atw_head_dur; 3311 } else { 3312 frm->atw_head_plcplen = (16 * len) / rate; 3313 remainder = (80 * len) % (rate * 5); 3314 3315 if (remainder != 0) { 3316 frm->atw_head_plcplen++; 3317 3318 /* XXX magic */ 3319 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3320 rate == 22 && remainder <= 30) 3321 frm->atw_head_plcplen |= 0x8000; 3322 } 3323 } 3324 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3325 htole16(frm->atw_head_plcplen); 3326 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3327 } 3328 3329 #ifdef ATW_DEBUG 3330 static void 3331 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3332 { 3333 struct atw_softc *sc = ifp->if_softc; 3334 struct mbuf *m; 3335 int i, noctets = 0; 3336 3337 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3338 m0->m_pkthdr.len); 3339 3340 for (m = m0; m; m = m->m_next) { 3341 if (m->m_len == 0) 3342 continue; 3343 for (i = 0; i < m->m_len; i++) { 3344 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3345 if (++noctets % 24 == 0) 3346 printf("\n"); 3347 } 3348 } 3349 printf("%s%s: %d bytes emitted\n", 3350 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3351 } 3352 #endif /* ATW_DEBUG */ 3353 3354 /* 3355 * atw_start: [ifnet interface function] 3356 * 3357 * Start packet transmission on the interface. 3358 */ 3359 void 3360 atw_start(ifp) 3361 struct ifnet *ifp; 3362 { 3363 struct atw_softc *sc = ifp->if_softc; 3364 struct ieee80211com *ic = &sc->sc_ic; 3365 struct ieee80211_node *ni; 3366 struct ieee80211_frame *wh; 3367 struct atw_frame *hh; 3368 struct mbuf *m0, *m; 3369 struct atw_txsoft *txs, *last_txs; 3370 struct atw_txdesc *txd; 3371 int do_encrypt, rate; 3372 bus_dmamap_t dmamap; 3373 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3374 3375 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3376 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3377 3378 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3379 return; 3380 3381 #if 0 /* TBD ??? */ 3382 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3383 return; 3384 #endif 3385 3386 /* 3387 * Remember the previous number of free descriptors and 3388 * the first descriptor we'll use. 3389 */ 3390 ofree = sc->sc_txfree; 3391 firsttx = sc->sc_txnext; 3392 3393 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3394 sc->sc_dev.dv_xname, ofree, firsttx)); 3395 3396 /* 3397 * Loop through the send queue, setting up transmit descriptors 3398 * until we drain the queue, or use up all available transmit 3399 * descriptors. 3400 */ 3401 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3402 sc->sc_txfree != 0) { 3403 3404 do_encrypt = 0; 3405 /* 3406 * Grab a packet off the management queue, if it 3407 * is not empty. Otherwise, from the data queue. 3408 */ 3409 IF_DEQUEUE(&ic->ic_mgtq, m0); 3410 if (m0 != NULL) { 3411 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3412 m0->m_pkthdr.rcvif = NULL; 3413 } else { 3414 IFQ_DEQUEUE(&ifp->if_snd, m0); 3415 if (m0 == NULL) 3416 break; 3417 #if NBPFILTER > 0 3418 if (ifp->if_bpf != NULL) 3419 bpf_mtap(ifp->if_bpf, m0); 3420 #endif /* NBPFILTER > 0 */ 3421 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3422 ifp->if_oerrors++; 3423 break; 3424 } 3425 } 3426 3427 rate = MAX(ieee80211_get_rate(ic), 2); 3428 3429 #if NBPFILTER > 0 3430 /* 3431 * Pass the packet to any BPF listeners. 3432 */ 3433 if (ic->ic_rawbpf != NULL) 3434 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3435 3436 if (sc->sc_radiobpf != NULL) { 3437 struct mbuf mb; 3438 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3439 3440 tap->at_rate = rate; 3441 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3442 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3443 3444 /* TBD tap->at_flags */ 3445 3446 M_COPY_PKTHDR(&mb, m0); 3447 mb.m_data = (caddr_t)tap; 3448 mb.m_len = tap->at_ihdr.it_len; 3449 mb.m_next = m0; 3450 mb.m_pkthdr.len += mb.m_len; 3451 bpf_mtap(sc->sc_radiobpf, &mb); 3452 } 3453 #endif /* NBPFILTER > 0 */ 3454 3455 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3456 3457 if (ni != NULL && ni != ic->ic_bss) 3458 ieee80211_free_node(ic, ni); 3459 3460 if (m0 == NULL) { 3461 ifp->if_oerrors++; 3462 break; 3463 } 3464 3465 /* just to make sure. */ 3466 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3467 3468 if (m0 == NULL) { 3469 ifp->if_oerrors++; 3470 break; 3471 } 3472 3473 hh = mtod(m0, struct atw_frame *); 3474 wh = &hh->atw_ihdr; 3475 3476 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3477 3478 /* Copy everything we need from the 802.11 header: 3479 * Frame Control; address 1, address 3, or addresses 3480 * 3 and 4. NIC fills in BSSID, SA. 3481 */ 3482 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3483 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3484 panic("%s: illegal WDS frame", 3485 sc->sc_dev.dv_xname); 3486 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3487 } else 3488 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3489 3490 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3491 3492 /* initialize remaining Tx parameters */ 3493 memset(&hh->u, 0, sizeof(hh->u)); 3494 3495 hh->atw_rate = rate * 5; 3496 /* XXX this could be incorrect if M_FCS. _encap should 3497 * probably strip FCS just in case it sticks around in 3498 * bridged packets. 3499 */ 3500 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3501 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3502 sizeof(struct atw_frame)); 3503 3504 #if 0 3505 /* this virtually guaranteed that WEP-encrypted frames 3506 * are fragmented. oops. 3507 */ 3508 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3509 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3510 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3511 #else 3512 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3513 #endif 3514 3515 hh->atw_rtylmt = 3; 3516 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3517 if (do_encrypt) { 3518 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3519 hh->atw_keyid = ic->ic_wep_txkey; 3520 } 3521 3522 /* TBD 4-addr frames */ 3523 atw_frame_setdurs(sc, hh, rate, 3524 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3525 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3526 3527 /* never fragment multicast frames */ 3528 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3529 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3530 } else if (sc->sc_flags & ATWF_RTSCTS) { 3531 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3532 } 3533 3534 #ifdef ATW_DEBUG 3535 /* experimental stuff */ 3536 if (atw_xrtylmt != ~0) 3537 hh->atw_rtylmt = atw_xrtylmt; 3538 if (atw_xhdrctl != 0) 3539 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3540 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3541 hh->atw_service = atw_xservice; 3542 if (atw_xpaylen != 0) 3543 hh->atw_paylen = htole16(atw_xpaylen); 3544 hh->atw_fragnum = 0; 3545 3546 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3547 printf("%s: dst = %s, rate = 0x%02x, " 3548 "service = 0x%02x, paylen = 0x%04x\n", 3549 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3550 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3551 3552 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3553 "dur1 = 0x%04x, dur2 = 0x%04x, " 3554 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3555 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3556 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3557 hh->atw_tail_dur, hh->atw_head_dur); 3558 3559 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3560 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3561 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3562 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3563 3564 printf("%s: keyid = %d\n", 3565 sc->sc_dev.dv_xname, hh->atw_keyid); 3566 3567 atw_dump_pkt(ifp, m0); 3568 } 3569 #endif /* ATW_DEBUG */ 3570 3571 dmamap = txs->txs_dmamap; 3572 3573 /* 3574 * Load the DMA map. Copy and try (once) again if the packet 3575 * didn't fit in the alloted number of segments. 3576 */ 3577 for (first = 1; 3578 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3579 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3580 first = 0) { 3581 MGETHDR(m, M_DONTWAIT, MT_DATA); 3582 if (m == NULL) { 3583 printf("%s: unable to allocate Tx mbuf\n", 3584 sc->sc_dev.dv_xname); 3585 break; 3586 } 3587 if (m0->m_pkthdr.len > MHLEN) { 3588 MCLGET(m, M_DONTWAIT); 3589 if ((m->m_flags & M_EXT) == 0) { 3590 printf("%s: unable to allocate Tx " 3591 "cluster\n", sc->sc_dev.dv_xname); 3592 m_freem(m); 3593 break; 3594 } 3595 } 3596 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3597 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3598 m_freem(m0); 3599 m0 = m; 3600 m = NULL; 3601 } 3602 if (error != 0) { 3603 printf("%s: unable to load Tx buffer, " 3604 "error = %d\n", sc->sc_dev.dv_xname, error); 3605 m_freem(m0); 3606 break; 3607 } 3608 3609 /* 3610 * Ensure we have enough descriptors free to describe 3611 * the packet. 3612 */ 3613 if (dmamap->dm_nsegs > sc->sc_txfree) { 3614 /* 3615 * Not enough free descriptors to transmit 3616 * this packet. Unload the DMA map and 3617 * drop the packet. Notify the upper layer 3618 * that there are no more slots left. 3619 * 3620 * XXX We could allocate an mbuf and copy, but 3621 * XXX it is worth it? 3622 */ 3623 ifp->if_flags |= IFF_OACTIVE; 3624 bus_dmamap_unload(sc->sc_dmat, dmamap); 3625 m_freem(m0); 3626 break; 3627 } 3628 3629 /* 3630 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3631 */ 3632 3633 /* Sync the DMA map. */ 3634 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3635 BUS_DMASYNC_PREWRITE); 3636 3637 /* XXX arbitrary retry limit; 8 because I have seen it in 3638 * use already and maybe 0 means "no tries" ! 3639 */ 3640 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3641 3642 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3643 sc->sc_dev.dv_xname, rate * 5)); 3644 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3645 3646 /* 3647 * Initialize the transmit descriptors. 3648 */ 3649 for (nexttx = sc->sc_txnext, seg = 0; 3650 seg < dmamap->dm_nsegs; 3651 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3652 /* 3653 * If this is the first descriptor we're 3654 * enqueueing, don't set the OWN bit just 3655 * yet. That could cause a race condition. 3656 * We'll do it below. 3657 */ 3658 txd = &sc->sc_txdescs[nexttx]; 3659 txd->at_ctl = ctl | 3660 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3661 3662 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3663 txd->at_flags = 3664 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3665 ATW_TXFLAG_TBS1_MASK)) | 3666 ((nexttx == (ATW_NTXDESC - 1)) 3667 ? htole32(ATW_TXFLAG_TER) : 0); 3668 lasttx = nexttx; 3669 } 3670 3671 KASSERT(lasttx != -1, ("bad lastx")); 3672 /* Set `first segment' and `last segment' appropriately. */ 3673 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3674 htole32(ATW_TXFLAG_FS); 3675 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3676 3677 #ifdef ATW_DEBUG 3678 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3679 printf(" txsoft %p transmit chain:\n", txs); 3680 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3681 printf(" descriptor %d:\n", seg); 3682 printf(" at_ctl: 0x%08x\n", 3683 le32toh(sc->sc_txdescs[seg].at_ctl)); 3684 printf(" at_flags: 0x%08x\n", 3685 le32toh(sc->sc_txdescs[seg].at_flags)); 3686 printf(" at_buf1: 0x%08x\n", 3687 le32toh(sc->sc_txdescs[seg].at_buf1)); 3688 printf(" at_buf2: 0x%08x\n", 3689 le32toh(sc->sc_txdescs[seg].at_buf2)); 3690 if (seg == lasttx) 3691 break; 3692 } 3693 } 3694 #endif 3695 3696 /* Sync the descriptors we're using. */ 3697 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3698 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3699 3700 /* 3701 * Store a pointer to the packet so we can free it later, 3702 * and remember what txdirty will be once the packet is 3703 * done. 3704 */ 3705 txs->txs_mbuf = m0; 3706 txs->txs_firstdesc = sc->sc_txnext; 3707 txs->txs_lastdesc = lasttx; 3708 txs->txs_ndescs = dmamap->dm_nsegs; 3709 3710 /* Advance the tx pointer. */ 3711 sc->sc_txfree -= dmamap->dm_nsegs; 3712 sc->sc_txnext = nexttx; 3713 3714 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3715 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3716 3717 last_txs = txs; 3718 } 3719 3720 if (txs == NULL || sc->sc_txfree == 0) { 3721 /* No more slots left; notify upper layer. */ 3722 ifp->if_flags |= IFF_OACTIVE; 3723 } 3724 3725 if (sc->sc_txfree != ofree) { 3726 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3727 sc->sc_dev.dv_xname, lasttx, firsttx)); 3728 /* 3729 * Cause a transmit interrupt to happen on the 3730 * last packet we enqueued. 3731 */ 3732 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3733 ATW_CDTXSYNC(sc, lasttx, 1, 3734 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3735 3736 /* 3737 * The entire packet chain is set up. Give the 3738 * first descriptor to the chip now. 3739 */ 3740 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3741 ATW_CDTXSYNC(sc, firsttx, 1, 3742 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3743 3744 /* Wake up the transmitter. */ 3745 /* XXX USE AUTOPOLLING? */ 3746 ATW_WRITE(sc, ATW_TDR, 0x1); 3747 3748 /* Set a watchdog timer in case the chip flakes out. */ 3749 sc->sc_tx_timer = 5; 3750 ifp->if_timer = 1; 3751 } 3752 } 3753 3754 /* 3755 * atw_power: 3756 * 3757 * Power management (suspend/resume) hook. 3758 */ 3759 void 3760 atw_power(why, arg) 3761 int why; 3762 void *arg; 3763 { 3764 struct atw_softc *sc = arg; 3765 struct ifnet *ifp = &sc->sc_ic.ic_if; 3766 int s; 3767 3768 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3769 3770 s = splnet(); 3771 switch (why) { 3772 case PWR_STANDBY: 3773 /* XXX do nothing. */ 3774 break; 3775 case PWR_SUSPEND: 3776 atw_stop(ifp, 0); 3777 if (sc->sc_power != NULL) 3778 (*sc->sc_power)(sc, why); 3779 break; 3780 case PWR_RESUME: 3781 if (ifp->if_flags & IFF_UP) { 3782 if (sc->sc_power != NULL) 3783 (*sc->sc_power)(sc, why); 3784 atw_init(ifp); 3785 } 3786 break; 3787 case PWR_SOFTSUSPEND: 3788 case PWR_SOFTSTANDBY: 3789 case PWR_SOFTRESUME: 3790 break; 3791 } 3792 splx(s); 3793 } 3794 3795 /* 3796 * atw_ioctl: [ifnet interface function] 3797 * 3798 * Handle control requests from the operator. 3799 */ 3800 int 3801 atw_ioctl(ifp, cmd, data) 3802 struct ifnet *ifp; 3803 u_long cmd; 3804 caddr_t data; 3805 { 3806 struct atw_softc *sc = ifp->if_softc; 3807 struct ifreq *ifr = (struct ifreq *)data; 3808 int s, error = 0; 3809 3810 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3811 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3812 return ENXIO; 3813 3814 s = splnet(); 3815 3816 switch (cmd) { 3817 case SIOCSIFFLAGS: 3818 if (ifp->if_flags & IFF_UP) { 3819 if (ATW_IS_ENABLED(sc)) { 3820 /* 3821 * To avoid rescanning another access point, 3822 * do not call atw_init() here. Instead, 3823 * only reflect media settings. 3824 */ 3825 atw_filter_setup(sc); 3826 } else 3827 error = atw_init(ifp); 3828 } else if (ATW_IS_ENABLED(sc)) 3829 atw_stop(ifp, 1); 3830 break; 3831 case SIOCADDMULTI: 3832 case SIOCDELMULTI: 3833 error = (cmd == SIOCADDMULTI) ? 3834 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3835 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3836 if (error == ENETRESET) { 3837 if (ATW_IS_ENABLED(sc)) 3838 atw_filter_setup(sc); /* do not rescan */ 3839 error = 0; 3840 } 3841 break; 3842 default: 3843 error = ieee80211_ioctl(ifp, cmd, data); 3844 if (error == ENETRESET) { 3845 if (ATW_IS_ENABLED(sc)) 3846 error = atw_init(ifp); 3847 else 3848 error = 0; 3849 } 3850 break; 3851 } 3852 3853 /* Try to get more packets going. */ 3854 if (ATW_IS_ENABLED(sc)) 3855 atw_start(ifp); 3856 3857 splx(s); 3858 return (error); 3859 } 3860 3861 static int 3862 atw_media_change(struct ifnet *ifp) 3863 { 3864 int error; 3865 3866 error = ieee80211_media_change(ifp); 3867 if (error == ENETRESET) { 3868 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3869 (IFF_RUNNING|IFF_UP)) 3870 atw_init(ifp); /* XXX lose error */ 3871 error = 0; 3872 } 3873 return error; 3874 } 3875 3876 static void 3877 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3878 { 3879 struct atw_softc *sc = ifp->if_softc; 3880 3881 if (ATW_IS_ENABLED(sc) == 0) { 3882 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3883 imr->ifm_status = 0; 3884 return; 3885 } 3886 ieee80211_media_status(ifp, imr); 3887 } 3888
Indexes created Wed Sep 24 02:09:48 GMT 2025