atw.c revision 1.136
1 /* $NetBSD: atw.c,v 1.136 2008/03/11 23:58:06 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.136 2008/03/11 23:58:06 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 #include <lib/libkern/libkern.h> 60 61 #include <machine/endian.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #include <net80211/ieee80211_netbsd.h> 71 #include <net80211/ieee80211_var.h> 72 #include <net80211/ieee80211_radiotap.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #endif 77 78 #include <sys/bus.h> 79 #include <sys/intr.h> 80 81 #include <dev/ic/atwreg.h> 82 #include <dev/ic/rf3000reg.h> 83 #include <dev/ic/si4136reg.h> 84 #include <dev/ic/atwvar.h> 85 #include <dev/ic/smc93cx6var.h> 86 87 /* XXX TBD open questions 88 * 89 * 90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 92 * handle this for me? 93 * 94 */ 95 /* device attachment 96 * 97 * print TOFS[012] 98 * 99 * device initialization 100 * 101 * clear ATW_FRCTL_MAXPSP to disable max power saving 102 * set ATW_TXBR_ALCUPDATE to enable ALC 103 * set TOFS[012]? (hope not) 104 * disable rx/tx 105 * set ATW_PAR_SWR (software reset) 106 * wait for ATW_PAR_SWR clear 107 * disable interrupts 108 * ack status register 109 * enable interrupts 110 * 111 * rx/tx initialization 112 * 113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * allocate and init descriptor rings 115 * write ATW_PAR_DSL (descriptor skip length) 116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * write ATW_NAR_SQ for one/both transmit descriptor rings 119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 120 * 121 * rx/tx end 122 * 123 * stop DMA 124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 125 * flush tx w/ ATW_NAR_HF 126 * 127 * scan 128 * 129 * initialize rx/tx 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 140 141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 143 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 144 145 int atw_pseudo_milli = 1; 146 int atw_magic_delay1 = 100 * 1000; 147 int atw_magic_delay2 = 100 * 1000; 148 /* more magic multi-millisecond delays (units: microseconds) */ 149 int atw_nar_delay = 20 * 1000; 150 int atw_magic_delay4 = 10 * 1000; 151 int atw_rf_delay1 = 10 * 1000; 152 int atw_rf_delay2 = 5 * 1000; 153 int atw_plcphd_delay = 2 * 1000; 154 int atw_bbp_io_enable_delay = 20 * 1000; 155 int atw_bbp_io_disable_delay = 2 * 1000; 156 int atw_writewep_delay = 1000; 157 int atw_beacon_len_adjust = 4; 158 int atw_dwelltime = 200; 159 int atw_xindiv2 = 0; 160 161 #ifdef ATW_DEBUG 162 int atw_debug = 0; 163 164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 170 171 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 172 static void atw_print_regs(struct atw_softc *, const char *); 173 174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 175 # ifdef ATW_BBPDEBUG 176 static void atw_rf3000_print(struct atw_softc *); 177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 178 # endif /* ATW_BBPDEBUG */ 179 180 # ifdef ATW_SYNDEBUG 181 static void atw_si4126_print(struct atw_softc *); 182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 183 # endif /* ATW_SYNDEBUG */ 184 185 #else 186 #define ATW_DPRINTF(x) 187 #define ATW_DPRINTF2(x) 188 #define ATW_DPRINTF3(x) 189 #define DPRINTF(sc, x) /* nothing */ 190 #define DPRINTF2(sc, x) /* nothing */ 191 #define DPRINTF3(sc, x) /* nothing */ 192 #endif 193 194 /* ifnet methods */ 195 int atw_init(struct ifnet *); 196 int atw_ioctl(struct ifnet *, u_long, void *); 197 void atw_start(struct ifnet *); 198 void atw_stop(struct ifnet *, int); 199 void atw_watchdog(struct ifnet *); 200 201 /* Device attachment */ 202 void atw_attach(struct atw_softc *); 203 int atw_detach(struct atw_softc *); 204 static void atw_evcnt_attach(struct atw_softc *); 205 static void atw_evcnt_detach(struct atw_softc *); 206 207 /* Rx/Tx process */ 208 int atw_add_rxbuf(struct atw_softc *, int); 209 void atw_idle(struct atw_softc *, u_int32_t); 210 void atw_rxdrain(struct atw_softc *); 211 void atw_txdrain(struct atw_softc *); 212 213 /* Device (de)activation and power state */ 214 void atw_disable(struct atw_softc *); 215 int atw_enable(struct atw_softc *); 216 void atw_reset(struct atw_softc *); 217 218 /* Interrupt handlers */ 219 void atw_linkintr(struct atw_softc *, u_int32_t); 220 void atw_rxintr(struct atw_softc *); 221 void atw_txintr(struct atw_softc *); 222 223 /* 802.11 state machine */ 224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 225 static void atw_next_scan(void *); 226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static int atw_tune(struct atw_softc *); 229 230 /* Device initialization */ 231 static void atw_bbp_io_init(struct atw_softc *); 232 static void atw_cfp_init(struct atw_softc *); 233 static void atw_cmdr_init(struct atw_softc *); 234 static void atw_ifs_init(struct atw_softc *); 235 static void atw_nar_init(struct atw_softc *); 236 static void atw_response_times_init(struct atw_softc *); 237 static void atw_rf_reset(struct atw_softc *); 238 static void atw_test1_init(struct atw_softc *); 239 static void atw_tofs0_init(struct atw_softc *); 240 static void atw_tofs2_init(struct atw_softc *); 241 static void atw_txlmt_init(struct atw_softc *); 242 static void atw_wcsr_init(struct atw_softc *); 243 244 /* Key management */ 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(device_t self, enum devact act) 323 { 324 struct atw_softc *sc = device_private(self); 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 printf("%s: device enable failed\n", 353 sc->sc_dev.dv_xname); 354 return (EIO); 355 } 356 sc->sc_flags |= ATWF_ENABLED; 357 /* Power may have been removed, and WEP keys thus 358 * reset. 359 */ 360 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 361 } 362 return (0); 363 } 364 365 /* 366 * atw_disable: 367 * 368 * Disable the ADM8211 chip. 369 */ 370 void 371 atw_disable(struct atw_softc *sc) 372 { 373 if (!ATW_IS_ENABLED(sc)) 374 return; 375 if (sc->sc_disable != NULL) 376 (*sc->sc_disable)(sc); 377 sc->sc_flags &= ~ATWF_ENABLED; 378 } 379 380 /* Returns -1 on failure. */ 381 static int 382 atw_read_srom(struct atw_softc *sc) 383 { 384 struct seeprom_descriptor sd; 385 uint32_t test0, fail_bits; 386 387 (void)memset(&sd, 0, sizeof(sd)); 388 389 test0 = ATW_READ(sc, ATW_TEST0); 390 391 switch (sc->sc_rev) { 392 case ATW_REVISION_BA: 393 case ATW_REVISION_CA: 394 fail_bits = ATW_TEST0_EPNE; 395 break; 396 default: 397 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 398 break; 399 } 400 if ((test0 & fail_bits) != 0) { 401 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 switch (test0 & ATW_TEST0_EPTYP_MASK) { 406 case ATW_TEST0_EPTYP_93c66: 407 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 408 sc->sc_sromsz = 512; 409 sd.sd_chip = C56_66; 410 break; 411 case ATW_TEST0_EPTYP_93c46: 412 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 413 sc->sc_sromsz = 128; 414 sd.sd_chip = C46; 415 break; 416 default: 417 printf("%s: unknown SROM type %" __PRIuBITS "\n", 418 sc->sc_dev.dv_xname, 419 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 420 return -1; 421 } 422 423 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 424 425 if (sc->sc_srom == NULL) { 426 printf("%s: unable to allocate SROM buffer\n", 427 sc->sc_dev.dv_xname); 428 return -1; 429 } 430 431 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 432 433 /* ADM8211 has a single 32-bit register for controlling the 434 * 93cx6 SROM. Bit SRS enables the serial port. There is no 435 * "ready" bit. The ADM8211 input/output sense is the reverse 436 * of read_seeprom's. 437 */ 438 sd.sd_tag = sc->sc_st; 439 sd.sd_bsh = sc->sc_sh; 440 sd.sd_regsize = 4; 441 sd.sd_control_offset = ATW_SPR; 442 sd.sd_status_offset = ATW_SPR; 443 sd.sd_dataout_offset = ATW_SPR; 444 sd.sd_CK = ATW_SPR_SCLK; 445 sd.sd_CS = ATW_SPR_SCS; 446 sd.sd_DI = ATW_SPR_SDO; 447 sd.sd_DO = ATW_SPR_SDI; 448 sd.sd_MS = ATW_SPR_SRS; 449 sd.sd_RDY = 0; 450 451 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 452 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 453 free(sc->sc_srom, M_DEVBUF); 454 return -1; 455 } 456 #ifdef ATW_DEBUG 457 { 458 int i; 459 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 460 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 461 if (((i % 8) == 0) && (i != 0)) { 462 ATW_DPRINTF(("\n\t")); 463 } 464 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 465 } 466 ATW_DPRINTF(("\n")); 467 } 468 #endif /* ATW_DEBUG */ 469 return 0; 470 } 471 472 #ifdef ATW_DEBUG 473 static void 474 atw_print_regs(struct atw_softc *sc, const char *where) 475 { 476 #define PRINTREG(sc, reg) \ 477 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 478 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 479 480 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 481 482 PRINTREG(sc, ATW_PAR); 483 PRINTREG(sc, ATW_FRCTL); 484 PRINTREG(sc, ATW_TDR); 485 PRINTREG(sc, ATW_WTDP); 486 PRINTREG(sc, ATW_RDR); 487 PRINTREG(sc, ATW_WRDP); 488 PRINTREG(sc, ATW_RDB); 489 PRINTREG(sc, ATW_CSR3A); 490 PRINTREG(sc, ATW_TDBD); 491 PRINTREG(sc, ATW_TDBP); 492 PRINTREG(sc, ATW_STSR); 493 PRINTREG(sc, ATW_CSR5A); 494 PRINTREG(sc, ATW_NAR); 495 PRINTREG(sc, ATW_CSR6A); 496 PRINTREG(sc, ATW_IER); 497 PRINTREG(sc, ATW_CSR7A); 498 PRINTREG(sc, ATW_LPC); 499 PRINTREG(sc, ATW_TEST1); 500 PRINTREG(sc, ATW_SPR); 501 PRINTREG(sc, ATW_TEST0); 502 PRINTREG(sc, ATW_WCSR); 503 PRINTREG(sc, ATW_WPDR); 504 PRINTREG(sc, ATW_GPTMR); 505 PRINTREG(sc, ATW_GPIO); 506 PRINTREG(sc, ATW_BBPCTL); 507 PRINTREG(sc, ATW_SYNCTL); 508 PRINTREG(sc, ATW_PLCPHD); 509 PRINTREG(sc, ATW_MMIWADDR); 510 PRINTREG(sc, ATW_MMIRADDR1); 511 PRINTREG(sc, ATW_MMIRADDR2); 512 PRINTREG(sc, ATW_TXBR); 513 PRINTREG(sc, ATW_CSR15A); 514 PRINTREG(sc, ATW_ALCSTAT); 515 PRINTREG(sc, ATW_TOFS2); 516 PRINTREG(sc, ATW_CMDR); 517 PRINTREG(sc, ATW_PCIC); 518 PRINTREG(sc, ATW_PMCSR); 519 PRINTREG(sc, ATW_PAR0); 520 PRINTREG(sc, ATW_PAR1); 521 PRINTREG(sc, ATW_MAR0); 522 PRINTREG(sc, ATW_MAR1); 523 PRINTREG(sc, ATW_ATIMDA0); 524 PRINTREG(sc, ATW_ABDA1); 525 PRINTREG(sc, ATW_BSSID0); 526 PRINTREG(sc, ATW_TXLMT); 527 PRINTREG(sc, ATW_MIBCNT); 528 PRINTREG(sc, ATW_BCNT); 529 PRINTREG(sc, ATW_TSFTH); 530 PRINTREG(sc, ATW_TSC); 531 PRINTREG(sc, ATW_SYNRF); 532 PRINTREG(sc, ATW_BPLI); 533 PRINTREG(sc, ATW_CAP0); 534 PRINTREG(sc, ATW_CAP1); 535 PRINTREG(sc, ATW_RMD); 536 PRINTREG(sc, ATW_CFPP); 537 PRINTREG(sc, ATW_TOFS0); 538 PRINTREG(sc, ATW_TOFS1); 539 PRINTREG(sc, ATW_IFST); 540 PRINTREG(sc, ATW_RSPT); 541 PRINTREG(sc, ATW_TSFTL); 542 PRINTREG(sc, ATW_WEPCTL); 543 PRINTREG(sc, ATW_WESK); 544 PRINTREG(sc, ATW_WEPCNT); 545 PRINTREG(sc, ATW_MACTEST); 546 PRINTREG(sc, ATW_FER); 547 PRINTREG(sc, ATW_FEMR); 548 PRINTREG(sc, ATW_FPSR); 549 PRINTREG(sc, ATW_FFER); 550 #undef PRINTREG 551 } 552 #endif /* ATW_DEBUG */ 553 554 /* 555 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 556 */ 557 void 558 atw_attach(struct atw_softc *sc) 559 { 560 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 562 }; 563 struct ieee80211com *ic = &sc->sc_ic; 564 struct ifnet *ifp = &sc->sc_if; 565 int country_code, error, i, nrate, srom_major; 566 u_int32_t reg; 567 static const char *type_strings[] = {"Intersil (not supported)", 568 "RFMD", "Marvel (not supported)"}; 569 570 sc->sc_txth = atw_txthresh_tab_lo; 571 572 SIMPLEQ_INIT(&sc->sc_txfreeq); 573 SIMPLEQ_INIT(&sc->sc_txdirtyq); 574 575 #ifdef ATW_DEBUG 576 atw_print_regs(sc, "atw_attach"); 577 #endif /* ATW_DEBUG */ 578 579 /* 580 * Allocate the control data structures, and create and load the 581 * DMA map for it. 582 */ 583 if ((error = bus_dmamem_alloc(sc->sc_dmat, 584 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 585 1, &sc->sc_cdnseg, 0)) != 0) { 586 printf("%s: unable to allocate control data, error = %d\n", 587 sc->sc_dev.dv_xname, error); 588 goto fail_0; 589 } 590 591 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 592 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 593 BUS_DMA_COHERENT)) != 0) { 594 printf("%s: unable to map control data, error = %d\n", 595 sc->sc_dev.dv_xname, error); 596 goto fail_1; 597 } 598 599 if ((error = bus_dmamap_create(sc->sc_dmat, 600 sizeof(struct atw_control_data), 1, 601 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 602 printf("%s: unable to create control data DMA map, " 603 "error = %d\n", sc->sc_dev.dv_xname, error); 604 goto fail_2; 605 } 606 607 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 608 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 609 0)) != 0) { 610 printf("%s: unable to load control data DMA map, error = %d\n", 611 sc->sc_dev.dv_xname, error); 612 goto fail_3; 613 } 614 615 /* 616 * Create the transmit buffer DMA maps. 617 */ 618 sc->sc_ntxsegs = ATW_NTXSEGS; 619 for (i = 0; i < ATW_TXQUEUELEN; i++) { 620 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 621 sc->sc_ntxsegs, MCLBYTES, 0, 0, 622 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 623 printf("%s: unable to create tx DMA map %d, " 624 "error = %d\n", sc->sc_dev.dv_xname, i, error); 625 goto fail_4; 626 } 627 } 628 629 /* 630 * Create the receive buffer DMA maps. 631 */ 632 for (i = 0; i < ATW_NRXDESC; i++) { 633 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 634 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 635 printf("%s: unable to create rx DMA map %d, " 636 "error = %d\n", sc->sc_dev.dv_xname, i, error); 637 goto fail_5; 638 } 639 } 640 for (i = 0; i < ATW_NRXDESC; i++) { 641 sc->sc_rxsoft[i].rxs_mbuf = NULL; 642 } 643 644 switch (sc->sc_rev) { 645 case ATW_REVISION_AB: 646 case ATW_REVISION_AF: 647 sc->sc_sramlen = ATW_SRAM_A_SIZE; 648 break; 649 case ATW_REVISION_BA: 650 case ATW_REVISION_CA: 651 sc->sc_sramlen = ATW_SRAM_B_SIZE; 652 break; 653 } 654 655 /* Reset the chip to a known state. */ 656 atw_reset(sc); 657 658 if (atw_read_srom(sc) == -1) 659 return; 660 661 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 662 ATW_SR_RFTYPE_MASK); 663 664 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 665 ATW_SR_BBPTYPE_MASK); 666 667 if (sc->sc_rftype >= __arraycount(type_strings)) { 668 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 669 return; 670 } 671 if (sc->sc_bbptype >= __arraycount(type_strings)) { 672 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 673 return; 674 } 675 676 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 677 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 678 679 /* XXX There exists a Linux driver which seems to use RFType = 0 for 680 * MARVEL. My bug, or theirs? 681 */ 682 683 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 684 685 switch (sc->sc_rftype) { 686 case ATW_RFTYPE_INTERSIL: 687 reg |= ATW_SYNCTL_CS1; 688 break; 689 case ATW_RFTYPE_RFMD: 690 reg |= ATW_SYNCTL_CS0; 691 break; 692 case ATW_RFTYPE_MARVEL: 693 break; 694 } 695 696 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 697 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 698 699 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 700 701 switch (sc->sc_bbptype) { 702 case ATW_BBPTYPE_INTERSIL: 703 reg |= ATW_BBPCTL_TWI; 704 break; 705 case ATW_BBPTYPE_RFMD: 706 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 707 ATW_BBPCTL_CCA_ACTLO; 708 break; 709 case ATW_BBPTYPE_MARVEL: 710 break; 711 case ATW_C_BBPTYPE_RFMD: 712 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 713 sc->sc_dev.dv_xname); 714 break; 715 } 716 717 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 718 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 719 720 /* 721 * From this point forward, the attachment cannot fail. A failure 722 * before this point releases all resources that may have been 723 * allocated. 724 */ 725 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 726 727 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 728 htole16(sc->sc_srom[ATW_SR_MAC00]), 729 htole16(sc->sc_srom[ATW_SR_MAC01]), 730 htole16(sc->sc_srom[ATW_SR_MAC10]))); 731 732 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 733 ATW_SR_MAJOR_MASK); 734 735 if (srom_major < 2) 736 sc->sc_rf3000_options1 = 0; 737 else if (sc->sc_rev == ATW_REVISION_BA) { 738 sc->sc_rf3000_options1 = 739 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 740 ATW_SR_CR28_MASK); 741 } else 742 sc->sc_rf3000_options1 = 0; 743 744 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 745 ATW_SR_CR29_MASK); 746 747 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 748 ATW_SR_CTRY_MASK); 749 750 #define ADD_CHANNEL(_ic, _chan) do { \ 751 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 752 _ic->ic_channels[_chan].ic_freq = \ 753 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 754 } while (0) 755 756 /* Find available channels */ 757 switch (country_code) { 758 case COUNTRY_MMK2: /* 1-14 */ 759 ADD_CHANNEL(ic, 14); 760 /*FALLTHROUGH*/ 761 case COUNTRY_ETSI: /* 1-13 */ 762 for (i = 1; i <= 13; i++) 763 ADD_CHANNEL(ic, i); 764 break; 765 case COUNTRY_FCC: /* 1-11 */ 766 case COUNTRY_IC: /* 1-11 */ 767 for (i = 1; i <= 11; i++) 768 ADD_CHANNEL(ic, i); 769 break; 770 case COUNTRY_MMK: /* 14 */ 771 ADD_CHANNEL(ic, 14); 772 break; 773 case COUNTRY_FRANCE: /* 10-13 */ 774 for (i = 10; i <= 13; i++) 775 ADD_CHANNEL(ic, i); 776 break; 777 default: /* assume channels 10-11 */ 778 case COUNTRY_SPAIN: /* 10-11 */ 779 for (i = 10; i <= 11; i++) 780 ADD_CHANNEL(ic, i); 781 break; 782 } 783 784 /* Read the MAC address. */ 785 reg = ATW_READ(sc, ATW_PAR0); 786 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 787 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 788 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 789 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 790 reg = ATW_READ(sc, ATW_PAR1); 791 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 792 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 793 794 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 795 printf(" could not get mac address, attach failed\n"); 796 return; 797 } 798 799 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 800 801 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 802 ifp->if_softc = sc; 803 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 804 IFF_NOTRAILERS; 805 ifp->if_ioctl = atw_ioctl; 806 ifp->if_start = atw_start; 807 ifp->if_watchdog = atw_watchdog; 808 ifp->if_init = atw_init; 809 ifp->if_stop = atw_stop; 810 IFQ_SET_READY(&ifp->if_snd); 811 812 ic->ic_ifp = ifp; 813 ic->ic_phytype = IEEE80211_T_DS; 814 ic->ic_opmode = IEEE80211_M_STA; 815 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 816 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 817 818 nrate = 0; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 822 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 823 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 824 825 /* 826 * Call MI attach routines. 827 */ 828 829 if_attach(ifp); 830 ieee80211_ifattach(ic); 831 832 atw_evcnt_attach(sc); 833 834 sc->sc_newstate = ic->ic_newstate; 835 ic->ic_newstate = atw_newstate; 836 837 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 838 ic->ic_recv_mgmt = atw_recv_mgmt; 839 840 sc->sc_node_free = ic->ic_node_free; 841 ic->ic_node_free = atw_node_free; 842 843 sc->sc_node_alloc = ic->ic_node_alloc; 844 ic->ic_node_alloc = atw_node_alloc; 845 846 ic->ic_crypto.cs_key_delete = atw_key_delete; 847 ic->ic_crypto.cs_key_set = atw_key_set; 848 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 849 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 850 851 /* possibly we should fill in our own sc_send_prresp, since 852 * the ADM8211 is probably sending probe responses in ad hoc 853 * mode. 854 */ 855 856 /* complete initialization */ 857 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 858 callout_init(&sc->sc_scan_ch, 0); 859 860 #if NBPFILTER > 0 861 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 862 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 863 #endif 864 865 if (!pmf_device_register1(&sc->sc_dev, NULL, NULL, atw_shutdown)) { 866 aprint_error_dev(&sc->sc_dev, 867 "couldn't establish power handler\n"); 868 } else 869 pmf_class_network_register(&sc->sc_dev, &sc->sc_if); 870 871 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 872 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 873 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 874 875 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 876 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 877 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 878 879 ieee80211_announce(ic); 880 return; 881 882 /* 883 * Free any resources we've allocated during the failed attach 884 * attempt. Do this in reverse order and fall through. 885 */ 886 fail_5: 887 for (i = 0; i < ATW_NRXDESC; i++) { 888 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 889 continue; 890 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 891 } 892 fail_4: 893 for (i = 0; i < ATW_TXQUEUELEN; i++) { 894 if (sc->sc_txsoft[i].txs_dmamap == NULL) 895 continue; 896 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 897 } 898 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 899 fail_3: 900 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 901 fail_2: 902 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 903 sizeof(struct atw_control_data)); 904 fail_1: 905 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 906 fail_0: 907 return; 908 } 909 910 static struct ieee80211_node * 911 atw_node_alloc(struct ieee80211_node_table *nt) 912 { 913 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 914 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 915 916 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 917 return ni; 918 } 919 920 static void 921 atw_node_free(struct ieee80211_node *ni) 922 { 923 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 924 925 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 926 ether_sprintf(ni->ni_bssid))); 927 (*sc->sc_node_free)(ni); 928 } 929 930 931 static void 932 atw_test1_reset(struct atw_softc *sc) 933 { 934 switch (sc->sc_rev) { 935 case ATW_REVISION_BA: 936 if (1 /* XXX condition on transceiver type */) { 937 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 938 } 939 break; 940 case ATW_REVISION_CA: 941 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 942 break; 943 default: 944 break; 945 } 946 } 947 948 /* 949 * atw_reset: 950 * 951 * Perform a soft reset on the ADM8211. 952 */ 953 void 954 atw_reset(struct atw_softc *sc) 955 { 956 int i; 957 uint32_t lpc; 958 959 ATW_WRITE(sc, ATW_NAR, 0x0); 960 DELAY(atw_nar_delay); 961 962 /* Reference driver has a cryptic remark indicating that this might 963 * power-on the chip. I know that it turns off power-saving.... 964 */ 965 ATW_WRITE(sc, ATW_FRCTL, 0x0); 966 967 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 968 969 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 970 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 971 break; 972 DELAY(atw_pseudo_milli); 973 } 974 975 /* ... and then pause 100ms longer for good measure. */ 976 DELAY(atw_magic_delay1); 977 978 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 979 980 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 981 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 982 983 /* 984 * Initialize the PCI Access Register. 985 */ 986 sc->sc_busmode = ATW_PAR_PBL_8DW; 987 988 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 989 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 990 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 991 992 atw_test1_reset(sc); 993 994 /* Turn off maximum power saving, etc. */ 995 ATW_WRITE(sc, ATW_FRCTL, 0x0); 996 997 DELAY(atw_magic_delay2); 998 999 /* Recall EEPROM. */ 1000 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1001 1002 DELAY(atw_magic_delay4); 1003 1004 lpc = ATW_READ(sc, ATW_LPC); 1005 1006 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1007 1008 /* A reset seems to affect the SRAM contents, so put them into 1009 * a known state. 1010 */ 1011 atw_clear_sram(sc); 1012 1013 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1014 } 1015 1016 static void 1017 atw_clear_sram(struct atw_softc *sc) 1018 { 1019 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1020 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1021 /* XXX not for revision 0x20. */ 1022 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1023 } 1024 1025 /* TBD atw_init 1026 * 1027 * set MAC based on ic->ic_bss->myaddr 1028 * write WEP keys 1029 * set TX rate 1030 */ 1031 1032 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1033 * without receiving a beacon with the preferred BSSID & SSID. 1034 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1035 */ 1036 static void 1037 atw_wcsr_init(struct atw_softc *sc) 1038 { 1039 uint32_t wcsr; 1040 1041 wcsr = ATW_READ(sc, ATW_WCSR); 1042 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1043 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1044 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1045 1046 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1047 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1048 } 1049 1050 /* Turn off power management. Set Rx store-and-forward mode. */ 1051 static void 1052 atw_cmdr_init(struct atw_softc *sc) 1053 { 1054 uint32_t cmdr; 1055 cmdr = ATW_READ(sc, ATW_CMDR); 1056 cmdr &= ~ATW_CMDR_APM; 1057 cmdr |= ATW_CMDR_RTE; 1058 cmdr &= ~ATW_CMDR_DRT_MASK; 1059 cmdr |= ATW_CMDR_DRT_SF; 1060 1061 ATW_WRITE(sc, ATW_CMDR, cmdr); 1062 } 1063 1064 static void 1065 atw_tofs2_init(struct atw_softc *sc) 1066 { 1067 uint32_t tofs2; 1068 /* XXX this magic can probably be figured out from the RFMD docs */ 1069 #ifndef ATW_REFSLAVE 1070 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1071 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1072 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1073 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1074 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1075 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1076 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1077 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1078 #else 1079 /* XXX new magic from reference driver source */ 1080 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1081 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1082 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1083 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1084 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1085 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1086 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1087 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1088 #endif 1089 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1090 } 1091 1092 static void 1093 atw_nar_init(struct atw_softc *sc) 1094 { 1095 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1096 } 1097 1098 static void 1099 atw_txlmt_init(struct atw_softc *sc) 1100 { 1101 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1102 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1103 } 1104 1105 static void 1106 atw_test1_init(struct atw_softc *sc) 1107 { 1108 uint32_t test1; 1109 1110 test1 = ATW_READ(sc, ATW_TEST1); 1111 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1112 /* XXX magic 0x1 */ 1113 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1114 ATW_WRITE(sc, ATW_TEST1, test1); 1115 } 1116 1117 static void 1118 atw_rf_reset(struct atw_softc *sc) 1119 { 1120 /* XXX this resets an Intersil RF front-end? */ 1121 /* TBD condition on Intersil RFType? */ 1122 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1123 DELAY(atw_rf_delay1); 1124 ATW_WRITE(sc, ATW_SYNRF, 0); 1125 DELAY(atw_rf_delay2); 1126 } 1127 1128 /* Set 16 TU max duration for the contention-free period (CFP). */ 1129 static void 1130 atw_cfp_init(struct atw_softc *sc) 1131 { 1132 uint32_t cfpp; 1133 1134 cfpp = ATW_READ(sc, ATW_CFPP); 1135 cfpp &= ~ATW_CFPP_CFPMD; 1136 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1137 ATW_WRITE(sc, ATW_CFPP, cfpp); 1138 } 1139 1140 static void 1141 atw_tofs0_init(struct atw_softc *sc) 1142 { 1143 /* XXX I guess that the Cardbus clock is 22 MHz? 1144 * I am assuming that the role of ATW_TOFS0_USCNT is 1145 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1146 * very clear on this point. It says in the datasheet that it is 1147 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1148 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1149 * these values. These values are also the power-on default. 1150 */ 1151 ATW_WRITE(sc, ATW_TOFS0, 1152 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1153 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1154 } 1155 1156 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1157 static void 1158 atw_ifs_init(struct atw_softc *sc) 1159 { 1160 uint32_t ifst; 1161 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1162 * Go figure. 1163 */ 1164 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1165 __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1166 ATW_IFST_SIFS_MASK) | 1167 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1168 __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1169 1170 ATW_WRITE(sc, ATW_IFST, ifst); 1171 } 1172 1173 static void 1174 atw_response_times_init(struct atw_softc *sc) 1175 { 1176 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1177 * indicate that the MAC expects at least SIFS + MIRT microseconds 1178 * to pass after it transmits a frame that requires a response; 1179 * it waits at most SIFS + MART microseconds for the response. 1180 * Surely this is not the ACK timeout? 1181 */ 1182 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1183 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1184 } 1185 1186 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1187 * engines read and write baseband registers after Rx and before 1188 * Tx, respectively. 1189 */ 1190 static void 1191 atw_bbp_io_init(struct atw_softc *sc) 1192 { 1193 uint32_t mmiraddr2; 1194 1195 /* XXX The reference driver does this, but is it *really* 1196 * necessary? 1197 */ 1198 switch (sc->sc_rev) { 1199 case ATW_REVISION_AB: 1200 case ATW_REVISION_AF: 1201 mmiraddr2 = 0x0; 1202 break; 1203 default: 1204 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1205 mmiraddr2 &= 1206 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1207 break; 1208 } 1209 1210 switch (sc->sc_bbptype) { 1211 case ATW_BBPTYPE_INTERSIL: 1212 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1213 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1214 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1215 break; 1216 case ATW_BBPTYPE_MARVEL: 1217 /* TBD find out the Marvel settings. */ 1218 break; 1219 case ATW_BBPTYPE_RFMD: 1220 default: 1221 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1222 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1223 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1224 break; 1225 } 1226 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1227 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1228 } 1229 1230 /* 1231 * atw_init: [ ifnet interface function ] 1232 * 1233 * Initialize the interface. Must be called at splnet(). 1234 */ 1235 int 1236 atw_init(struct ifnet *ifp) 1237 { 1238 struct atw_softc *sc = ifp->if_softc; 1239 struct ieee80211com *ic = &sc->sc_ic; 1240 struct atw_txsoft *txs; 1241 struct atw_rxsoft *rxs; 1242 int i, error = 0; 1243 1244 if ((error = atw_enable(sc)) != 0) 1245 goto out; 1246 1247 /* 1248 * Cancel any pending I/O. This also resets. 1249 */ 1250 atw_stop(ifp, 0); 1251 1252 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1253 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1254 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1255 1256 atw_wcsr_init(sc); 1257 1258 atw_cmdr_init(sc); 1259 1260 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1261 * 1262 * XXX Set transmit power for ATIM, RTS, Beacon. 1263 */ 1264 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1265 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1266 1267 atw_tofs2_init(sc); 1268 1269 atw_nar_init(sc); 1270 1271 atw_txlmt_init(sc); 1272 1273 atw_test1_init(sc); 1274 1275 atw_rf_reset(sc); 1276 1277 atw_cfp_init(sc); 1278 1279 atw_tofs0_init(sc); 1280 1281 atw_ifs_init(sc); 1282 1283 /* XXX Fall asleep after one second of inactivity. 1284 * XXX A frame may only dribble in for 65536us. 1285 */ 1286 ATW_WRITE(sc, ATW_RMD, 1287 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1288 1289 atw_response_times_init(sc); 1290 1291 atw_bbp_io_init(sc); 1292 1293 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1294 1295 if ((error = atw_rf3000_init(sc)) != 0) 1296 goto out; 1297 1298 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1299 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1300 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1301 1302 /* 1303 * Initialize the transmit descriptor ring. 1304 */ 1305 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1306 for (i = 0; i < ATW_NTXDESC; i++) { 1307 sc->sc_txdescs[i].at_ctl = 0; 1308 /* no transmit chaining */ 1309 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1310 sc->sc_txdescs[i].at_buf2 = 1311 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1312 } 1313 /* use ring mode */ 1314 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1315 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1316 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1317 sc->sc_txfree = ATW_NTXDESC; 1318 sc->sc_txnext = 0; 1319 1320 /* 1321 * Initialize the transmit job descriptors. 1322 */ 1323 SIMPLEQ_INIT(&sc->sc_txfreeq); 1324 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1325 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1326 txs = &sc->sc_txsoft[i]; 1327 txs->txs_mbuf = NULL; 1328 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1329 } 1330 1331 /* 1332 * Initialize the receive descriptor and receive job 1333 * descriptor rings. 1334 */ 1335 for (i = 0; i < ATW_NRXDESC; i++) { 1336 rxs = &sc->sc_rxsoft[i]; 1337 if (rxs->rxs_mbuf == NULL) { 1338 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1339 printf("%s: unable to allocate or map rx " 1340 "buffer %d, error = %d\n", 1341 sc->sc_dev.dv_xname, i, error); 1342 /* 1343 * XXX Should attempt to run with fewer receive 1344 * XXX buffers instead of just failing. 1345 */ 1346 atw_rxdrain(sc); 1347 goto out; 1348 } 1349 } else 1350 atw_init_rxdesc(sc, i); 1351 } 1352 sc->sc_rxptr = 0; 1353 1354 /* 1355 * Initialize the interrupt mask and enable interrupts. 1356 */ 1357 /* normal interrupts */ 1358 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1359 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1360 1361 /* abnormal interrupts */ 1362 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1363 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1364 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1365 1366 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1367 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1368 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1369 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1370 ATW_INTR_TRT; 1371 1372 sc->sc_linkint_mask &= sc->sc_inten; 1373 sc->sc_rxint_mask &= sc->sc_inten; 1374 sc->sc_txint_mask &= sc->sc_inten; 1375 1376 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1377 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1378 1379 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1380 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1381 1382 /* 1383 * Give the transmit and receive rings to the ADM8211. 1384 */ 1385 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1386 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1387 1388 sc->sc_txthresh = 0; 1389 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1390 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1391 1392 /* common 802.11 configuration */ 1393 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1394 switch (ic->ic_opmode) { 1395 case IEEE80211_M_STA: 1396 break; 1397 case IEEE80211_M_AHDEMO: /* XXX */ 1398 case IEEE80211_M_IBSS: 1399 ic->ic_flags |= IEEE80211_F_IBSSON; 1400 /*FALLTHROUGH*/ 1401 case IEEE80211_M_HOSTAP: /* XXX */ 1402 break; 1403 case IEEE80211_M_MONITOR: /* XXX */ 1404 break; 1405 } 1406 1407 switch (ic->ic_opmode) { 1408 case IEEE80211_M_AHDEMO: 1409 case IEEE80211_M_HOSTAP: 1410 #ifndef IEEE80211_NO_HOSTAP 1411 ic->ic_bss->ni_intval = ic->ic_lintval; 1412 ic->ic_bss->ni_rssi = 0; 1413 ic->ic_bss->ni_rstamp = 0; 1414 #endif /* !IEEE80211_NO_HOSTAP */ 1415 break; 1416 default: /* XXX */ 1417 break; 1418 } 1419 1420 sc->sc_wepctl = 0; 1421 1422 atw_write_ssid(sc); 1423 atw_write_sup_rates(sc); 1424 atw_write_wep(sc); 1425 1426 ic->ic_state = IEEE80211_S_INIT; 1427 1428 /* 1429 * Set the receive filter. This will start the transmit and 1430 * receive processes. 1431 */ 1432 atw_filter_setup(sc); 1433 1434 /* 1435 * Start the receive process. 1436 */ 1437 ATW_WRITE(sc, ATW_RDR, 0x1); 1438 1439 /* 1440 * Note that the interface is now running. 1441 */ 1442 ifp->if_flags |= IFF_RUNNING; 1443 ifp->if_flags &= ~IFF_OACTIVE; 1444 1445 /* send no beacons, yet. */ 1446 atw_start_beacon(sc, 0); 1447 1448 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1449 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1450 else 1451 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1452 out: 1453 if (error) { 1454 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1455 sc->sc_tx_timer = 0; 1456 ifp->if_timer = 0; 1457 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1458 } 1459 #ifdef ATW_DEBUG 1460 atw_print_regs(sc, "end of init"); 1461 #endif /* ATW_DEBUG */ 1462 1463 return (error); 1464 } 1465 1466 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1467 * 0: MAC control of RF3000/Si4126. 1468 * 1469 * Applies power, or selects RF front-end? Sets reset condition. 1470 * 1471 * TBD support non-RFMD BBP, non-SiLabs synth. 1472 */ 1473 static void 1474 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1475 { 1476 if (enable) { 1477 ATW_WRITE(sc, ATW_SYNRF, 1478 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1479 DELAY(atw_bbp_io_enable_delay); 1480 } else { 1481 ATW_WRITE(sc, ATW_SYNRF, 0); 1482 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1483 } 1484 } 1485 1486 static int 1487 atw_tune(struct atw_softc *sc) 1488 { 1489 int rc; 1490 u_int chan; 1491 struct ieee80211com *ic = &sc->sc_ic; 1492 1493 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1494 if (chan == IEEE80211_CHAN_ANY) 1495 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1496 1497 if (chan == sc->sc_cur_chan) 1498 return 0; 1499 1500 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1501 sc->sc_cur_chan, chan)); 1502 1503 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1504 1505 atw_si4126_tune(sc, chan); 1506 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1507 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1508 chan); 1509 1510 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1511 DELAY(atw_nar_delay); 1512 ATW_WRITE(sc, ATW_RDR, 0x1); 1513 1514 if (rc == 0) { 1515 sc->sc_cur_chan = chan; 1516 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1517 htole16(ic->ic_curchan->ic_freq); 1518 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1519 htole16(ic->ic_curchan->ic_flags); 1520 } 1521 1522 return rc; 1523 } 1524 1525 #ifdef ATW_SYNDEBUG 1526 static void 1527 atw_si4126_print(struct atw_softc *sc) 1528 { 1529 struct ifnet *ifp = &sc->sc_if; 1530 u_int addr, val; 1531 1532 val = 0; 1533 1534 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1535 return; 1536 1537 for (addr = 0; addr <= 8; addr++) { 1538 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1539 if (atw_si4126_read(sc, addr, &val) == 0) { 1540 printf("<unknown> (quitting print-out)\n"); 1541 break; 1542 } 1543 printf("%05x\n", val); 1544 } 1545 } 1546 #endif /* ATW_SYNDEBUG */ 1547 1548 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1549 * 1550 * The RF/IF synthesizer produces two reference frequencies for 1551 * the RF2948B transceiver. The first frequency the RF2948B requires 1552 * is two times the so-called "intermediate frequency" (IF). Since 1553 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1554 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1555 * frequency required by the transceiver is the radio frequency 1556 * (RF). This is a superheterodyne transceiver; for f(chan) the 1557 * center frequency of the channel we are tuning, RF = f(chan) - 1558 * IF. 1559 * 1560 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1561 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1562 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1563 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1564 */ 1565 static void 1566 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1567 { 1568 u_int mhz; 1569 u_int R; 1570 u_int32_t gpio; 1571 u_int16_t gain; 1572 1573 #ifdef ATW_SYNDEBUG 1574 atw_si4126_print(sc); 1575 #endif /* ATW_SYNDEBUG */ 1576 1577 if (chan == 14) 1578 mhz = 2484; 1579 else 1580 mhz = 2412 + 5 * (chan - 1); 1581 1582 /* Tune IF to 748 MHz to suit the IF LO input of the 1583 * RF2494B, which is 2 x IF. No need to set an IF divider 1584 * because an IF in 526 MHz - 952 MHz is allowed. 1585 * 1586 * XIN is 44.000 MHz, so divide it by two to get allowable 1587 * range of 2-25 MHz. SiLabs tells me that this is not 1588 * strictly necessary. 1589 */ 1590 1591 if (atw_xindiv2) 1592 R = 44; 1593 else 1594 R = 88; 1595 1596 /* Power-up RF, IF synthesizers. */ 1597 atw_si4126_write(sc, SI4126_POWER, 1598 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1599 1600 /* set LPWR, too? */ 1601 atw_si4126_write(sc, SI4126_MAIN, 1602 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1603 1604 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1605 * set KP2 to 1. 1606 * 1607 * REFDIF This is different from the reference driver, which 1608 * always sets SI4126_GAIN to 0. 1609 */ 1610 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1611 1612 atw_si4126_write(sc, SI4126_GAIN, gain); 1613 1614 /* XIN = 44 MHz. 1615 * 1616 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1617 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1618 * 1619 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1620 * so that 1496/88 * 44 MHz = 748 MHz. 1621 */ 1622 atw_si4126_write(sc, SI4126_IFN, 1496); 1623 1624 atw_si4126_write(sc, SI4126_IFR, R); 1625 1626 #ifndef ATW_REFSLAVE 1627 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1628 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1629 * which has no RF1! 1630 */ 1631 atw_si4126_write(sc, SI4126_RF1R, R); 1632 1633 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1634 #endif 1635 1636 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1637 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1638 * Now let's multiply it to mhz. So mhz - IF = N. 1639 */ 1640 atw_si4126_write(sc, SI4126_RF2R, R); 1641 1642 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1643 1644 /* wait 100us from power-up for RF, IF to settle */ 1645 DELAY(100); 1646 1647 gpio = ATW_READ(sc, ATW_GPIO); 1648 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1649 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1650 1651 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1652 /* Set a Prism RF front-end to a special mode for channel 14? 1653 * 1654 * Apparently the SMC2635W needs this, although I don't think 1655 * it has a Prism RF. 1656 */ 1657 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1658 } 1659 ATW_WRITE(sc, ATW_GPIO, gpio); 1660 1661 #ifdef ATW_SYNDEBUG 1662 atw_si4126_print(sc); 1663 #endif /* ATW_SYNDEBUG */ 1664 } 1665 1666 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1667 * diversity. 1668 * 1669 * !!! 1670 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1671 * !!! 1672 */ 1673 static int 1674 atw_rf3000_init(struct atw_softc *sc) 1675 { 1676 int rc = 0; 1677 1678 atw_bbp_io_enable(sc, 1); 1679 1680 /* CCA is acquisition sensitive */ 1681 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1682 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1683 1684 if (rc != 0) 1685 goto out; 1686 1687 /* enable diversity */ 1688 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1689 1690 if (rc != 0) 1691 goto out; 1692 1693 /* sensible setting from a binary-only driver */ 1694 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1695 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1696 1697 if (rc != 0) 1698 goto out; 1699 1700 /* magic from a binary-only driver */ 1701 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1702 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1703 1704 if (rc != 0) 1705 goto out; 1706 1707 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1708 1709 if (rc != 0) 1710 goto out; 1711 1712 /* XXX Reference driver remarks that Abocom sets this to 50. 1713 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1714 * in the "reserved" area of register RF3000_OPTIONS1. 1715 */ 1716 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1717 1718 if (rc != 0) 1719 goto out; 1720 1721 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1722 1723 if (rc != 0) 1724 goto out; 1725 1726 out: 1727 atw_bbp_io_enable(sc, 0); 1728 return rc; 1729 } 1730 1731 #ifdef ATW_BBPDEBUG 1732 static void 1733 atw_rf3000_print(struct atw_softc *sc) 1734 { 1735 struct ifnet *ifp = &sc->sc_if; 1736 u_int addr, val; 1737 1738 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1739 return; 1740 1741 for (addr = 0x01; addr <= 0x15; addr++) { 1742 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1743 if (atw_rf3000_read(sc, addr, &val) != 0) { 1744 printf("<unknown> (quitting print-out)\n"); 1745 break; 1746 } 1747 printf("%08x\n", val); 1748 } 1749 } 1750 #endif /* ATW_BBPDEBUG */ 1751 1752 /* Set the power settings on the BBP for channel `chan'. */ 1753 static int 1754 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1755 { 1756 int rc = 0; 1757 u_int32_t reg; 1758 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1759 1760 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1761 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1762 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1763 1764 /* odd channels: LSB, even channels: MSB */ 1765 if (chan % 2 == 1) { 1766 txpower &= 0xFF; 1767 lpf_cutoff &= 0xFF; 1768 lna_gs_thresh &= 0xFF; 1769 } else { 1770 txpower >>= 8; 1771 lpf_cutoff >>= 8; 1772 lna_gs_thresh >>= 8; 1773 } 1774 1775 #ifdef ATW_BBPDEBUG 1776 atw_rf3000_print(sc); 1777 #endif /* ATW_BBPDEBUG */ 1778 1779 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1780 "lna_gs_thresh %02x\n", 1781 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1782 1783 atw_bbp_io_enable(sc, 1); 1784 1785 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1786 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1787 goto out; 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1790 goto out; 1791 1792 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1793 goto out; 1794 1795 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1796 1797 if (rc != 0) 1798 goto out; 1799 1800 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1801 1802 if (rc != 0) 1803 goto out; 1804 1805 #ifdef ATW_BBPDEBUG 1806 atw_rf3000_print(sc); 1807 #endif /* ATW_BBPDEBUG */ 1808 1809 out: 1810 atw_bbp_io_enable(sc, 0); 1811 1812 /* set beacon, rts, atim transmit power */ 1813 reg = ATW_READ(sc, ATW_PLCPHD); 1814 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1815 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1816 ATW_PLCPHD_SERVICE_MASK); 1817 ATW_WRITE(sc, ATW_PLCPHD, reg); 1818 DELAY(atw_plcphd_delay); 1819 1820 return rc; 1821 } 1822 1823 /* Write a register on the RF3000 baseband processor using the 1824 * registers provided by the ADM8211 for this purpose. 1825 * 1826 * Return 0 on success. 1827 */ 1828 static int 1829 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1830 { 1831 u_int32_t reg; 1832 int i; 1833 1834 reg = sc->sc_bbpctl_wr | 1835 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1836 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1837 1838 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1839 ATW_WRITE(sc, ATW_BBPCTL, reg); 1840 DELAY(2 * atw_pseudo_milli); 1841 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1842 break; 1843 } 1844 1845 if (i < 0) { 1846 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1847 return ETIMEDOUT; 1848 } 1849 return 0; 1850 } 1851 1852 /* Read a register on the RF3000 baseband processor using the registers 1853 * the ADM8211 provides for this purpose. 1854 * 1855 * The 7-bit register address is addr. Record the 8-bit data in the register 1856 * in *val. 1857 * 1858 * Return 0 on success. 1859 * 1860 * XXX This does not seem to work. The ADM8211 must require more or 1861 * different magic to read the chip than to write it. Possibly some 1862 * of the magic I have derived from a binary-only driver concerns 1863 * the "chip address" (see the RF3000 manual). 1864 */ 1865 #ifdef ATW_BBPDEBUG 1866 static int 1867 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1868 { 1869 u_int32_t reg; 1870 int i; 1871 1872 for (i = 1000; --i >= 0; ) { 1873 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1874 break; 1875 DELAY(100); 1876 } 1877 1878 if (i < 0) { 1879 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1880 sc->sc_dev.dv_xname); 1881 return ETIMEDOUT; 1882 } 1883 1884 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1885 1886 ATW_WRITE(sc, ATW_BBPCTL, reg); 1887 1888 for (i = 1000; --i >= 0; ) { 1889 DELAY(100); 1890 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1891 break; 1892 } 1893 1894 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1895 1896 if (i < 0) { 1897 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1898 sc->sc_dev.dv_xname, reg); 1899 return ETIMEDOUT; 1900 } 1901 if (val != NULL) 1902 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1903 return 0; 1904 } 1905 #endif /* ATW_BBPDEBUG */ 1906 1907 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1908 * provided by the ADM8211 for that purpose. 1909 * 1910 * val is 18 bits of data, and val is the 4-bit address of the register. 1911 * 1912 * Return 0 on success. 1913 */ 1914 static void 1915 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1916 { 1917 uint32_t bits, mask, reg; 1918 const int nbits = 22; 1919 1920 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1921 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1922 1923 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1924 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1925 1926 reg = ATW_SYNRF_SELSYN; 1927 /* reference driver: reset Si4126 serial bus to initial 1928 * conditions? 1929 */ 1930 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1931 ATW_WRITE(sc, ATW_SYNRF, reg); 1932 1933 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1934 if ((bits & mask) != 0) 1935 reg |= ATW_SYNRF_SYNDATA; 1936 else 1937 reg &= ~ATW_SYNRF_SYNDATA; 1938 ATW_WRITE(sc, ATW_SYNRF, reg); 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1940 ATW_WRITE(sc, ATW_SYNRF, reg); 1941 } 1942 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1943 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1944 } 1945 1946 /* Read 18-bit data from the 4-bit address addr in Si4126 1947 * RF synthesizer and write the data to *val. Return 0 on success. 1948 * 1949 * XXX This does not seem to work. The ADM8211 must require more or 1950 * different magic to read the chip than to write it. 1951 */ 1952 #ifdef ATW_SYNDEBUG 1953 static int 1954 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1955 { 1956 u_int32_t reg; 1957 int i; 1958 1959 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1960 1961 for (i = 1000; --i >= 0; ) { 1962 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1963 break; 1964 DELAY(100); 1965 } 1966 1967 if (i < 0) { 1968 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1969 sc->sc_dev.dv_xname); 1970 return ETIMEDOUT; 1971 } 1972 1973 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1974 1975 ATW_WRITE(sc, ATW_SYNCTL, reg); 1976 1977 for (i = 1000; --i >= 0; ) { 1978 DELAY(100); 1979 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1980 break; 1981 } 1982 1983 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1984 1985 if (i < 0) { 1986 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1987 sc->sc_dev.dv_xname, reg); 1988 return ETIMEDOUT; 1989 } 1990 if (val != NULL) 1991 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1992 ATW_SYNCTL_DATA_MASK); 1993 return 0; 1994 } 1995 #endif /* ATW_SYNDEBUG */ 1996 1997 /* XXX is the endianness correct? test. */ 1998 #define atw_calchash(addr) \ 1999 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 2000 2001 /* 2002 * atw_filter_setup: 2003 * 2004 * Set the ADM8211's receive filter. 2005 */ 2006 static void 2007 atw_filter_setup(struct atw_softc *sc) 2008 { 2009 struct ieee80211com *ic = &sc->sc_ic; 2010 struct ethercom *ec = &sc->sc_ec; 2011 struct ifnet *ifp = &sc->sc_if; 2012 int hash; 2013 u_int32_t hashes[2]; 2014 struct ether_multi *enm; 2015 struct ether_multistep step; 2016 2017 /* According to comments in tlp_al981_filter_setup 2018 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2019 * multicast filter to be set while it is running. Hopefully 2020 * the ADM8211 is not the same! 2021 */ 2022 if ((ifp->if_flags & IFF_RUNNING) != 0) 2023 atw_idle(sc, ATW_NAR_SR); 2024 2025 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 2026 ifp->if_flags &= ~IFF_ALLMULTI; 2027 2028 /* XXX in scan mode, do not filter packets. Maybe this is 2029 * unnecessary. 2030 */ 2031 if (ic->ic_state == IEEE80211_S_SCAN || 2032 (ifp->if_flags & IFF_PROMISC) != 0) { 2033 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2034 goto allmulti; 2035 } 2036 2037 hashes[0] = hashes[1] = 0x0; 2038 2039 /* 2040 * Program the 64-bit multicast hash filter. 2041 */ 2042 ETHER_FIRST_MULTI(step, ec, enm); 2043 while (enm != NULL) { 2044 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2045 ETHER_ADDR_LEN) != 0) 2046 goto allmulti; 2047 2048 hash = atw_calchash(enm->enm_addrlo); 2049 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2050 ETHER_NEXT_MULTI(step, enm); 2051 sc->sc_opmode |= ATW_NAR_MM; 2052 } 2053 ifp->if_flags &= ~IFF_ALLMULTI; 2054 goto setit; 2055 2056 allmulti: 2057 sc->sc_opmode |= ATW_NAR_MM; 2058 ifp->if_flags |= IFF_ALLMULTI; 2059 hashes[0] = hashes[1] = 0xffffffff; 2060 2061 setit: 2062 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2063 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2064 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2065 DELAY(atw_nar_delay); 2066 ATW_WRITE(sc, ATW_RDR, 0x1); 2067 2068 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2069 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2070 } 2071 2072 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2073 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2074 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2075 * no beacon with the preferred BSSID and SSID in the number of 2076 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2077 */ 2078 static void 2079 atw_write_bssid(struct atw_softc *sc) 2080 { 2081 struct ieee80211com *ic = &sc->sc_ic; 2082 u_int8_t *bssid; 2083 2084 bssid = ic->ic_bss->ni_bssid; 2085 2086 ATW_WRITE(sc, ATW_BSSID0, 2087 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2088 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2089 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2090 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2091 2092 ATW_WRITE(sc, ATW_ABDA1, 2093 (ATW_READ(sc, ATW_ABDA1) & 2094 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2095 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2096 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2097 2098 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2099 ether_sprintf(sc->sc_bssid))); 2100 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2101 2102 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2103 } 2104 2105 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2106 * 16-bit word. 2107 */ 2108 static void 2109 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2110 { 2111 u_int i; 2112 u_int8_t *ptr; 2113 2114 memcpy(&sc->sc_sram[ofs], buf, buflen); 2115 2116 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2117 2118 KASSERT(buflen + ofs <= sc->sc_sramlen); 2119 2120 ptr = &sc->sc_sram[ofs]; 2121 2122 for (i = 0; i < buflen; i += 2) { 2123 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2124 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2125 DELAY(atw_writewep_delay); 2126 2127 ATW_WRITE(sc, ATW_WESK, 2128 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2129 DELAY(atw_writewep_delay); 2130 } 2131 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2132 2133 if (sc->sc_if.if_flags & IFF_DEBUG) { 2134 int n_octets = 0; 2135 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2136 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2137 for (i = 0; i < buflen; i++) { 2138 printf(" %02x", ptr[i]); 2139 if (++n_octets % 24 == 0) 2140 printf("\n"); 2141 } 2142 if (n_octets % 24 != 0) 2143 printf("\n"); 2144 } 2145 } 2146 2147 static int 2148 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2149 { 2150 struct atw_softc *sc = ic->ic_ifp->if_softc; 2151 u_int keyix = k->wk_keyix; 2152 2153 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2154 2155 if (keyix >= IEEE80211_WEP_NKID) 2156 return 0; 2157 if (k->wk_keylen != 0) 2158 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2159 2160 return 1; 2161 } 2162 2163 static int 2164 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2165 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2166 { 2167 struct atw_softc *sc = ic->ic_ifp->if_softc; 2168 2169 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2170 2171 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2172 return 0; 2173 2174 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2175 2176 return 1; 2177 } 2178 2179 static void 2180 atw_key_update_begin(struct ieee80211com *ic) 2181 { 2182 #ifdef ATW_DEBUG 2183 struct ifnet *ifp = ic->ic_ifp; 2184 struct atw_softc *sc = ifp->if_softc; 2185 #endif 2186 2187 DPRINTF(sc, ("%s:\n", __func__)); 2188 } 2189 2190 static void 2191 atw_key_update_end(struct ieee80211com *ic) 2192 { 2193 struct ifnet *ifp = ic->ic_ifp; 2194 struct atw_softc *sc = ifp->if_softc; 2195 2196 DPRINTF(sc, ("%s:\n", __func__)); 2197 2198 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2199 return; 2200 if (ATW_IS_ENABLED(sc) == 0) 2201 return; 2202 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2203 atw_write_wep(sc); 2204 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2205 DELAY(atw_nar_delay); 2206 ATW_WRITE(sc, ATW_RDR, 0x1); 2207 } 2208 2209 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2210 static void 2211 atw_write_wep(struct atw_softc *sc) 2212 { 2213 #if 0 2214 struct ieee80211com *ic = &sc->sc_ic; 2215 u_int32_t reg; 2216 int i; 2217 #endif 2218 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2219 u_int8_t buf[IEEE80211_WEP_NKID] 2220 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2221 2222 sc->sc_wepctl = 0; 2223 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2224 2225 memset(&buf[0][0], 0, sizeof(buf)); 2226 2227 #if 0 2228 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2229 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2230 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2231 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2232 buf[i][1] = ATW_WEP_ENABLED; 2233 } else { 2234 buf[i][1] = 0; 2235 continue; 2236 } 2237 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2238 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2239 ic->ic_nw_keys[i].wk_keylen - 1); 2240 } 2241 2242 reg = ATW_READ(sc, ATW_MACTEST); 2243 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2244 reg &= ~ATW_MACTEST_KEYID_MASK; 2245 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2246 ATW_WRITE(sc, ATW_MACTEST, reg); 2247 2248 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2249 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2250 2251 switch (sc->sc_rev) { 2252 case ATW_REVISION_AB: 2253 case ATW_REVISION_AF: 2254 /* Bypass WEP on Rx. */ 2255 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2256 break; 2257 default: 2258 break; 2259 } 2260 #endif 2261 2262 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2263 sizeof(buf)); 2264 2265 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2266 } 2267 2268 static void 2269 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2270 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2271 { 2272 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2273 2274 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2275 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2276 return; 2277 2278 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2279 2280 switch (subtype) { 2281 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2282 case IEEE80211_FC0_SUBTYPE_BEACON: 2283 if (ic->ic_opmode == IEEE80211_M_IBSS && 2284 ic->ic_state == IEEE80211_S_RUN) { 2285 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2286 (void)ieee80211_ibss_merge(ni); 2287 } 2288 break; 2289 default: 2290 break; 2291 } 2292 return; 2293 } 2294 2295 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2296 * In ad hoc mode, the SSID is written to the beacons sent by the 2297 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2298 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2299 * indications. 2300 */ 2301 static void 2302 atw_write_ssid(struct atw_softc *sc) 2303 { 2304 struct ieee80211com *ic = &sc->sc_ic; 2305 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2306 * it only expects the element length, not its ID. 2307 */ 2308 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2309 2310 memset(buf, 0, sizeof(buf)); 2311 buf[0] = ic->ic_bss->ni_esslen; 2312 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2313 2314 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2315 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2316 } 2317 2318 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2319 * In ad hoc mode, the supported rates are written to beacons sent by the 2320 * ADM8211. 2321 */ 2322 static void 2323 atw_write_sup_rates(struct atw_softc *sc) 2324 { 2325 struct ieee80211com *ic = &sc->sc_ic; 2326 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2327 * supported rates 2328 */ 2329 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2330 2331 memset(buf, 0, sizeof(buf)); 2332 2333 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2334 2335 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2336 ic->ic_bss->ni_rates.rs_nrates); 2337 2338 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2339 } 2340 2341 /* Start/stop sending beacons. */ 2342 void 2343 atw_start_beacon(struct atw_softc *sc, int start) 2344 { 2345 struct ieee80211com *ic = &sc->sc_ic; 2346 uint16_t chan; 2347 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2348 size_t len; 2349 2350 if (ATW_IS_ENABLED(sc) == 0) 2351 return; 2352 2353 /* start beacons */ 2354 len = sizeof(struct ieee80211_frame) + 2355 8 /* timestamp */ + 2 /* beacon interval */ + 2356 2 /* capability info */ + 2357 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2358 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2359 3 /* DS parameters */ + 2360 IEEE80211_CRC_LEN; 2361 2362 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2363 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2364 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2365 2366 ATW_WRITE(sc, ATW_BCNT, bcnt); 2367 ATW_WRITE(sc, ATW_CAP1, cap1); 2368 2369 if (!start) 2370 return; 2371 2372 /* TBD use ni_capinfo */ 2373 2374 capinfo = 0; 2375 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2376 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2377 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2378 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2379 2380 switch (ic->ic_opmode) { 2381 case IEEE80211_M_IBSS: 2382 len += 4; /* IBSS parameters */ 2383 capinfo |= IEEE80211_CAPINFO_IBSS; 2384 break; 2385 case IEEE80211_M_HOSTAP: 2386 /* XXX 6-byte minimum TIM */ 2387 len += atw_beacon_len_adjust; 2388 capinfo |= IEEE80211_CAPINFO_ESS; 2389 break; 2390 default: 2391 return; 2392 } 2393 2394 /* set listen interval 2395 * XXX do software units agree w/ hardware? 2396 */ 2397 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2398 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2399 2400 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2401 2402 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2403 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2404 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2405 2406 ATW_WRITE(sc, ATW_BCNT, bcnt); 2407 ATW_WRITE(sc, ATW_BPLI, bpli); 2408 ATW_WRITE(sc, ATW_CAP0, cap0); 2409 ATW_WRITE(sc, ATW_CAP1, cap1); 2410 2411 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2412 sc->sc_dev.dv_xname, bcnt)); 2413 2414 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2415 sc->sc_dev.dv_xname, cap1)); 2416 } 2417 2418 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2419 static inline uint32_t 2420 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2421 { 2422 /* Following the reference driver's lead, I compute 2423 * 2424 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2425 * 2426 * without using 64-bit arithmetic, using the following 2427 * relationship: 2428 * 2429 * (0x100000000 * H + L) % m 2430 * = ((0x100000000 % m) * H + L) % m 2431 * = (((0xffffffff + 1) % m) * H + L) % m 2432 * = ((0xffffffff % m + 1 % m) * H + L) % m 2433 * = ((0xffffffff % m + 1) * H + L) % m 2434 */ 2435 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2436 } 2437 2438 static uint64_t 2439 atw_get_tsft(struct atw_softc *sc) 2440 { 2441 int i; 2442 uint32_t tsfth, tsftl; 2443 for (i = 0; i < 2; i++) { 2444 tsfth = ATW_READ(sc, ATW_TSFTH); 2445 tsftl = ATW_READ(sc, ATW_TSFTL); 2446 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2447 break; 2448 } 2449 return ((uint64_t)tsfth << 32) | tsftl; 2450 } 2451 2452 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2453 * the ieee80211com. 2454 * 2455 * Predict the next target beacon transmission time (TBTT) and 2456 * write it to the ADM8211. 2457 */ 2458 static void 2459 atw_predict_beacon(struct atw_softc *sc) 2460 { 2461 #define TBTTOFS 20 /* TU */ 2462 2463 struct ieee80211com *ic = &sc->sc_ic; 2464 uint64_t tsft; 2465 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2466 union { 2467 uint64_t word; 2468 uint8_t tstamp[8]; 2469 } u; 2470 2471 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2472 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2473 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2474 tsft = atw_get_tsft(sc); 2475 u.word = htole64(tsft); 2476 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2477 sizeof(ic->ic_bss->ni_tstamp)); 2478 } else 2479 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2480 2481 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2482 2483 tsftl = tsft & 0xFFFFFFFF; 2484 tsfth = tsft >> 32; 2485 2486 /* We sent/received the last beacon `past' microseconds 2487 * after the interval divided the TSF timer. 2488 */ 2489 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2490 2491 /* Skip ten beacons so that the TBTT cannot pass before 2492 * we've programmed it. Ten is an arbitrary number. 2493 */ 2494 tbtt = past_even + ival * 10; 2495 2496 ATW_WRITE(sc, ATW_TOFS1, 2497 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2498 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2499 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2500 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2501 #undef TBTTOFS 2502 } 2503 2504 static void 2505 atw_next_scan(void *arg) 2506 { 2507 struct atw_softc *sc = arg; 2508 struct ieee80211com *ic = &sc->sc_ic; 2509 int s; 2510 2511 /* don't call atw_start w/o network interrupts blocked */ 2512 s = splnet(); 2513 if (ic->ic_state == IEEE80211_S_SCAN) 2514 ieee80211_next_scan(ic); 2515 splx(s); 2516 } 2517 2518 /* Synchronize the hardware state with the software state. */ 2519 static int 2520 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2521 { 2522 struct ifnet *ifp = ic->ic_ifp; 2523 struct atw_softc *sc = ifp->if_softc; 2524 enum ieee80211_state ostate; 2525 int error = 0; 2526 2527 ostate = ic->ic_state; 2528 callout_stop(&sc->sc_scan_ch); 2529 2530 switch (nstate) { 2531 case IEEE80211_S_AUTH: 2532 case IEEE80211_S_ASSOC: 2533 atw_write_bssid(sc); 2534 error = atw_tune(sc); 2535 break; 2536 case IEEE80211_S_INIT: 2537 callout_stop(&sc->sc_scan_ch); 2538 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2539 atw_start_beacon(sc, 0); 2540 break; 2541 case IEEE80211_S_SCAN: 2542 error = atw_tune(sc); 2543 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2544 atw_next_scan, sc); 2545 break; 2546 case IEEE80211_S_RUN: 2547 error = atw_tune(sc); 2548 atw_write_bssid(sc); 2549 atw_write_ssid(sc); 2550 atw_write_sup_rates(sc); 2551 2552 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2553 ic->ic_opmode == IEEE80211_M_MONITOR) 2554 break; 2555 2556 /* set listen interval 2557 * XXX do software units agree w/ hardware? 2558 */ 2559 ATW_WRITE(sc, ATW_BPLI, 2560 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2561 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2562 ATW_BPLI_LI_MASK)); 2563 2564 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2565 ATW_READ(sc, ATW_BPLI))); 2566 2567 atw_predict_beacon(sc); 2568 2569 switch (ic->ic_opmode) { 2570 case IEEE80211_M_AHDEMO: 2571 case IEEE80211_M_HOSTAP: 2572 case IEEE80211_M_IBSS: 2573 atw_start_beacon(sc, 1); 2574 break; 2575 case IEEE80211_M_MONITOR: 2576 case IEEE80211_M_STA: 2577 break; 2578 } 2579 2580 break; 2581 } 2582 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2583 } 2584 2585 /* 2586 * atw_add_rxbuf: 2587 * 2588 * Add a receive buffer to the indicated descriptor. 2589 */ 2590 int 2591 atw_add_rxbuf(struct atw_softc *sc, int idx) 2592 { 2593 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2594 struct mbuf *m; 2595 int error; 2596 2597 MGETHDR(m, M_DONTWAIT, MT_DATA); 2598 if (m == NULL) 2599 return (ENOBUFS); 2600 2601 MCLGET(m, M_DONTWAIT); 2602 if ((m->m_flags & M_EXT) == 0) { 2603 m_freem(m); 2604 return (ENOBUFS); 2605 } 2606 2607 if (rxs->rxs_mbuf != NULL) 2608 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2609 2610 rxs->rxs_mbuf = m; 2611 2612 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2613 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2614 BUS_DMA_READ|BUS_DMA_NOWAIT); 2615 if (error) { 2616 printf("%s: can't load rx DMA map %d, error = %d\n", 2617 sc->sc_dev.dv_xname, idx, error); 2618 panic("atw_add_rxbuf"); /* XXX */ 2619 } 2620 2621 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2622 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2623 2624 atw_init_rxdesc(sc, idx); 2625 2626 return (0); 2627 } 2628 2629 /* 2630 * Release any queued transmit buffers. 2631 */ 2632 void 2633 atw_txdrain(struct atw_softc *sc) 2634 { 2635 struct atw_txsoft *txs; 2636 2637 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2638 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2639 if (txs->txs_mbuf != NULL) { 2640 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2641 m_freem(txs->txs_mbuf); 2642 txs->txs_mbuf = NULL; 2643 } 2644 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2645 sc->sc_txfree += txs->txs_ndescs; 2646 } 2647 2648 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2649 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2650 sc->sc_txfree != ATW_NTXDESC)); 2651 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2652 sc->sc_tx_timer = 0; 2653 } 2654 2655 /* 2656 * atw_stop: [ ifnet interface function ] 2657 * 2658 * Stop transmission on the interface. 2659 */ 2660 void 2661 atw_stop(struct ifnet *ifp, int disable) 2662 { 2663 struct atw_softc *sc = ifp->if_softc; 2664 struct ieee80211com *ic = &sc->sc_ic; 2665 2666 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2667 2668 /* Disable interrupts. */ 2669 ATW_WRITE(sc, ATW_IER, 0); 2670 2671 /* Stop the transmit and receive processes. */ 2672 sc->sc_opmode = 0; 2673 ATW_WRITE(sc, ATW_NAR, 0); 2674 DELAY(atw_nar_delay); 2675 ATW_WRITE(sc, ATW_TDBD, 0); 2676 ATW_WRITE(sc, ATW_TDBP, 0); 2677 ATW_WRITE(sc, ATW_RDB, 0); 2678 2679 atw_txdrain(sc); 2680 2681 /* 2682 * Mark the interface down and cancel the watchdog timer. 2683 */ 2684 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2685 sc->sc_tx_timer = 0; 2686 ifp->if_timer = 0; 2687 2688 if (disable) { 2689 atw_rxdrain(sc); 2690 atw_disable(sc); 2691 } else 2692 atw_reset(sc); 2693 } 2694 2695 /* 2696 * atw_rxdrain: 2697 * 2698 * Drain the receive queue. 2699 */ 2700 void 2701 atw_rxdrain(struct atw_softc *sc) 2702 { 2703 struct atw_rxsoft *rxs; 2704 int i; 2705 2706 for (i = 0; i < ATW_NRXDESC; i++) { 2707 rxs = &sc->sc_rxsoft[i]; 2708 if (rxs->rxs_mbuf == NULL) 2709 continue; 2710 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2711 m_freem(rxs->rxs_mbuf); 2712 rxs->rxs_mbuf = NULL; 2713 } 2714 } 2715 2716 /* 2717 * atw_detach: 2718 * 2719 * Detach an ADM8211 interface. 2720 */ 2721 int 2722 atw_detach(struct atw_softc *sc) 2723 { 2724 struct ifnet *ifp = &sc->sc_if; 2725 struct atw_rxsoft *rxs; 2726 struct atw_txsoft *txs; 2727 int i; 2728 2729 /* 2730 * Succeed now if there isn't any work to do. 2731 */ 2732 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2733 return (0); 2734 2735 pmf_device_deregister(&sc->sc_dev); 2736 2737 callout_stop(&sc->sc_scan_ch); 2738 2739 ieee80211_ifdetach(&sc->sc_ic); 2740 if_detach(ifp); 2741 2742 for (i = 0; i < ATW_NRXDESC; i++) { 2743 rxs = &sc->sc_rxsoft[i]; 2744 if (rxs->rxs_mbuf != NULL) { 2745 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2746 m_freem(rxs->rxs_mbuf); 2747 rxs->rxs_mbuf = NULL; 2748 } 2749 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2750 } 2751 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2752 txs = &sc->sc_txsoft[i]; 2753 if (txs->txs_mbuf != NULL) { 2754 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2755 m_freem(txs->txs_mbuf); 2756 txs->txs_mbuf = NULL; 2757 } 2758 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2759 } 2760 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2761 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2762 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2763 sizeof(struct atw_control_data)); 2764 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2765 2766 if (sc->sc_srom) 2767 free(sc->sc_srom, M_DEVBUF); 2768 2769 atw_evcnt_detach(sc); 2770 2771 return (0); 2772 } 2773 2774 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2775 bool 2776 atw_shutdown(device_t self, int flags) 2777 { 2778 struct atw_softc *sc = device_private(self); 2779 2780 atw_stop(&sc->sc_if, 1); 2781 return true; 2782 } 2783 2784 int 2785 atw_intr(void *arg) 2786 { 2787 struct atw_softc *sc = arg; 2788 struct ifnet *ifp = &sc->sc_if; 2789 u_int32_t status, rxstatus, txstatus, linkstatus; 2790 int handled = 0, txthresh; 2791 2792 #ifdef DEBUG 2793 if (ATW_IS_ENABLED(sc) == 0) 2794 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2795 #endif 2796 2797 /* 2798 * If the interface isn't running, the interrupt couldn't 2799 * possibly have come from us. 2800 */ 2801 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2802 !device_is_active(&sc->sc_dev)) 2803 return (0); 2804 2805 for (;;) { 2806 status = ATW_READ(sc, ATW_STSR); 2807 2808 if (status) 2809 ATW_WRITE(sc, ATW_STSR, status); 2810 2811 #ifdef ATW_DEBUG 2812 #define PRINTINTR(flag) do { \ 2813 if ((status & flag) != 0) { \ 2814 printf("%s" #flag, delim); \ 2815 delim = ","; \ 2816 } \ 2817 } while (0) 2818 2819 if (atw_debug > 1 && status) { 2820 const char *delim = "<"; 2821 2822 printf("%s: reg[STSR] = %x", 2823 sc->sc_dev.dv_xname, status); 2824 2825 PRINTINTR(ATW_INTR_FBE); 2826 PRINTINTR(ATW_INTR_LINKOFF); 2827 PRINTINTR(ATW_INTR_LINKON); 2828 PRINTINTR(ATW_INTR_RCI); 2829 PRINTINTR(ATW_INTR_RDU); 2830 PRINTINTR(ATW_INTR_REIS); 2831 PRINTINTR(ATW_INTR_RPS); 2832 PRINTINTR(ATW_INTR_TCI); 2833 PRINTINTR(ATW_INTR_TDU); 2834 PRINTINTR(ATW_INTR_TLT); 2835 PRINTINTR(ATW_INTR_TPS); 2836 PRINTINTR(ATW_INTR_TRT); 2837 PRINTINTR(ATW_INTR_TUF); 2838 PRINTINTR(ATW_INTR_BCNTC); 2839 PRINTINTR(ATW_INTR_ATIME); 2840 PRINTINTR(ATW_INTR_TBTT); 2841 PRINTINTR(ATW_INTR_TSCZ); 2842 PRINTINTR(ATW_INTR_TSFTF); 2843 printf(">\n"); 2844 } 2845 #undef PRINTINTR 2846 #endif /* ATW_DEBUG */ 2847 2848 if ((status & sc->sc_inten) == 0) 2849 break; 2850 2851 handled = 1; 2852 2853 rxstatus = status & sc->sc_rxint_mask; 2854 txstatus = status & sc->sc_txint_mask; 2855 linkstatus = status & sc->sc_linkint_mask; 2856 2857 if (linkstatus) { 2858 atw_linkintr(sc, linkstatus); 2859 } 2860 2861 if (rxstatus) { 2862 /* Grab any new packets. */ 2863 atw_rxintr(sc); 2864 2865 if (rxstatus & ATW_INTR_RDU) { 2866 printf("%s: receive ring overrun\n", 2867 sc->sc_dev.dv_xname); 2868 /* Get the receive process going again. */ 2869 ATW_WRITE(sc, ATW_RDR, 0x1); 2870 break; 2871 } 2872 } 2873 2874 if (txstatus) { 2875 /* Sweep up transmit descriptors. */ 2876 atw_txintr(sc); 2877 2878 if (txstatus & ATW_INTR_TLT) { 2879 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2880 sc->sc_dev.dv_xname)); 2881 } 2882 2883 if (txstatus & ATW_INTR_TRT) { 2884 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2885 sc->sc_dev.dv_xname)); 2886 } 2887 2888 /* If Tx under-run, increase our transmit threshold 2889 * if another is available. 2890 */ 2891 txthresh = sc->sc_txthresh + 1; 2892 if ((txstatus & ATW_INTR_TUF) && 2893 sc->sc_txth[txthresh].txth_name != NULL) { 2894 /* Idle the transmit process. */ 2895 atw_idle(sc, ATW_NAR_ST); 2896 2897 sc->sc_txthresh = txthresh; 2898 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2899 sc->sc_opmode |= 2900 sc->sc_txth[txthresh].txth_opmode; 2901 printf("%s: transmit underrun; new " 2902 "threshold: %s\n", sc->sc_dev.dv_xname, 2903 sc->sc_txth[txthresh].txth_name); 2904 2905 /* Set the new threshold and restart 2906 * the transmit process. 2907 */ 2908 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2909 DELAY(atw_nar_delay); 2910 ATW_WRITE(sc, ATW_RDR, 0x1); 2911 /* XXX Log every Nth underrun from 2912 * XXX now on? 2913 */ 2914 } 2915 } 2916 2917 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2918 if (status & ATW_INTR_TPS) 2919 printf("%s: transmit process stopped\n", 2920 sc->sc_dev.dv_xname); 2921 if (status & ATW_INTR_RPS) 2922 printf("%s: receive process stopped\n", 2923 sc->sc_dev.dv_xname); 2924 (void)atw_init(ifp); 2925 break; 2926 } 2927 2928 if (status & ATW_INTR_FBE) { 2929 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2930 (void)atw_init(ifp); 2931 break; 2932 } 2933 2934 /* 2935 * Not handled: 2936 * 2937 * Transmit buffer unavailable -- normal 2938 * condition, nothing to do, really. 2939 * 2940 * Early receive interrupt -- not available on 2941 * all chips, we just use RI. We also only 2942 * use single-segment receive DMA, so this 2943 * is mostly useless. 2944 * 2945 * TBD others 2946 */ 2947 } 2948 2949 /* Try to get more packets going. */ 2950 atw_start(ifp); 2951 2952 return (handled); 2953 } 2954 2955 /* 2956 * atw_idle: 2957 * 2958 * Cause the transmit and/or receive processes to go idle. 2959 * 2960 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2961 * process in STSR if I clear SR or ST after the process has already 2962 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2963 * do not seem to be too reliable. Perhaps I have the sense of the 2964 * Rx bits switched with the Tx bits? 2965 */ 2966 void 2967 atw_idle(struct atw_softc *sc, u_int32_t bits) 2968 { 2969 u_int32_t ackmask = 0, opmode, stsr, test0; 2970 int i, s; 2971 2972 s = splnet(); 2973 2974 opmode = sc->sc_opmode & ~bits; 2975 2976 if (bits & ATW_NAR_SR) 2977 ackmask |= ATW_INTR_RPS; 2978 2979 if (bits & ATW_NAR_ST) { 2980 ackmask |= ATW_INTR_TPS; 2981 /* set ATW_NAR_HF to flush TX FIFO. */ 2982 opmode |= ATW_NAR_HF; 2983 } 2984 2985 ATW_WRITE(sc, ATW_NAR, opmode); 2986 DELAY(atw_nar_delay); 2987 2988 for (i = 0; i < 1000; i++) { 2989 stsr = ATW_READ(sc, ATW_STSR); 2990 if ((stsr & ackmask) == ackmask) 2991 break; 2992 DELAY(10); 2993 } 2994 2995 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2996 2997 if ((stsr & ackmask) == ackmask) 2998 goto out; 2999 3000 test0 = ATW_READ(sc, ATW_TEST0); 3001 3002 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3003 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3004 printf("%s: transmit process not idle [%s]\n", 3005 sc->sc_dev.dv_xname, 3006 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3007 printf("%s: bits %08x test0 %08x stsr %08x\n", 3008 sc->sc_dev.dv_xname, bits, test0, stsr); 3009 } 3010 3011 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3012 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3013 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3014 sc->sc_dev.dv_xname, 3015 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3016 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3017 sc->sc_dev.dv_xname, bits, test0, stsr)); 3018 } 3019 out: 3020 if ((bits & ATW_NAR_ST) != 0) 3021 atw_txdrain(sc); 3022 splx(s); 3023 return; 3024 } 3025 3026 /* 3027 * atw_linkintr: 3028 * 3029 * Helper; handle link-status interrupts. 3030 */ 3031 void 3032 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3033 { 3034 struct ieee80211com *ic = &sc->sc_ic; 3035 3036 if (ic->ic_state != IEEE80211_S_RUN) 3037 return; 3038 3039 if (linkstatus & ATW_INTR_LINKON) { 3040 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3041 sc->sc_rescan_timer = 0; 3042 } else if (linkstatus & ATW_INTR_LINKOFF) { 3043 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3044 if (ic->ic_opmode != IEEE80211_M_STA) 3045 return; 3046 sc->sc_rescan_timer = 3; 3047 sc->sc_if.if_timer = 1; 3048 } 3049 } 3050 3051 static inline int 3052 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3053 { 3054 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3055 return 0; 3056 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3057 return 0; 3058 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3059 } 3060 3061 /* 3062 * atw_rxintr: 3063 * 3064 * Helper; handle receive interrupts. 3065 */ 3066 void 3067 atw_rxintr(struct atw_softc *sc) 3068 { 3069 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3070 struct ieee80211com *ic = &sc->sc_ic; 3071 struct ieee80211_node *ni; 3072 struct ieee80211_frame_min *wh; 3073 struct ifnet *ifp = &sc->sc_if; 3074 struct atw_rxsoft *rxs; 3075 struct mbuf *m; 3076 u_int32_t rxstat; 3077 int i, len, rate, rate0; 3078 u_int32_t rssi, ctlrssi; 3079 3080 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3081 rxs = &sc->sc_rxsoft[i]; 3082 3083 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3084 3085 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3086 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3087 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3088 3089 if (rxstat & ATW_RXSTAT_OWN) 3090 break; /* We have processed all receive buffers. */ 3091 3092 DPRINTF3(sc, 3093 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3094 sc->sc_dev.dv_xname, 3095 rxstat, ctlrssi, 3096 le32toh(sc->sc_rxdescs[i].ar_buf1), 3097 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3098 3099 /* 3100 * Make sure the packet fits in one buffer. This should 3101 * always be the case. 3102 */ 3103 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3104 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3105 printf("%s: incoming packet spilled, resetting\n", 3106 sc->sc_dev.dv_xname); 3107 (void)atw_init(ifp); 3108 return; 3109 } 3110 3111 /* 3112 * If an error occurred, update stats, clear the status 3113 * word, and leave the packet buffer in place. It will 3114 * simply be reused the next time the ring comes around. 3115 */ 3116 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3117 #define PRINTERR(bit, str) \ 3118 if (rxstat & (bit)) \ 3119 printf("%s: receive error: %s\n", \ 3120 sc->sc_dev.dv_xname, str) 3121 ifp->if_ierrors++; 3122 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3123 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3124 #if 0 3125 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3126 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3127 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3128 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3129 #endif 3130 #undef PRINTERR 3131 atw_init_rxdesc(sc, i); 3132 continue; 3133 } 3134 3135 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3136 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3137 3138 /* 3139 * No errors; receive the packet. Note the ADM8211 3140 * includes the CRC in promiscuous mode. 3141 */ 3142 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3143 3144 /* 3145 * Allocate a new mbuf cluster. If that fails, we are 3146 * out of memory, and must drop the packet and recycle 3147 * the buffer that's already attached to this descriptor. 3148 */ 3149 m = rxs->rxs_mbuf; 3150 if (atw_add_rxbuf(sc, i) != 0) { 3151 ifp->if_ierrors++; 3152 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3153 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3154 atw_init_rxdesc(sc, i); 3155 continue; 3156 } 3157 3158 ifp->if_ipackets++; 3159 m->m_pkthdr.rcvif = ifp; 3160 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3161 3162 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3163 3164 /* The RSSI comes straight from a register in the 3165 * baseband processor. I know that for the RF3000, 3166 * the RSSI register also contains the antenna-selection 3167 * bits. Mask those off. 3168 * 3169 * TBD Treat other basebands. 3170 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3171 */ 3172 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3173 rssi = ctlrssi & RF3000_RSSI_MASK; 3174 else 3175 rssi = ctlrssi; 3176 3177 #if NBPFILTER > 0 3178 /* Pass this up to any BPF listeners. */ 3179 if (sc->sc_radiobpf != NULL) { 3180 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3181 3182 tap->ar_rate = rate; 3183 3184 /* TBD verify units are dB */ 3185 tap->ar_antsignal = (int)rssi; 3186 if (sc->sc_opmode & ATW_NAR_PR) 3187 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3188 else 3189 tap->ar_flags = 0; 3190 3191 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3192 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3193 3194 bpf_mtap2(sc->sc_radiobpf, tap, 3195 sizeof(sc->sc_rxtapu), m); 3196 } 3197 #endif /* NBPFILTER > 0 */ 3198 3199 sc->sc_recv_ev.ev_count++; 3200 3201 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3202 if (rxstat & ATW_RXSTAT_CRC16E) 3203 sc->sc_crc16e_ev.ev_count++; 3204 if (rxstat & ATW_RXSTAT_CRC32E) 3205 sc->sc_crc32e_ev.ev_count++; 3206 if (rxstat & ATW_RXSTAT_ICVE) 3207 sc->sc_icve_ev.ev_count++; 3208 if (rxstat & ATW_RXSTAT_SFDE) 3209 sc->sc_sfde_ev.ev_count++; 3210 if (rxstat & ATW_RXSTAT_SIGE) 3211 sc->sc_sige_ev.ev_count++; 3212 ifp->if_ierrors++; 3213 m_freem(m); 3214 continue; 3215 } 3216 3217 if (sc->sc_opmode & ATW_NAR_PR) 3218 m_adj(m, -IEEE80211_CRC_LEN); 3219 3220 wh = mtod(m, struct ieee80211_frame_min *); 3221 ni = ieee80211_find_rxnode(ic, wh); 3222 #if 0 3223 if (atw_hw_decrypted(sc, wh)) { 3224 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3225 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3226 } 3227 #endif 3228 ieee80211_input(ic, m, ni, (int)rssi, 0); 3229 ieee80211_free_node(ni); 3230 } 3231 3232 /* Update the receive pointer. */ 3233 sc->sc_rxptr = i; 3234 } 3235 3236 /* 3237 * atw_txintr: 3238 * 3239 * Helper; handle transmit interrupts. 3240 */ 3241 void 3242 atw_txintr(struct atw_softc *sc) 3243 { 3244 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3245 struct ifnet *ifp = &sc->sc_if; 3246 struct atw_txsoft *txs; 3247 u_int32_t txstat; 3248 3249 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3250 sc->sc_dev.dv_xname, sc->sc_flags)); 3251 3252 /* 3253 * Go through our Tx list and free mbufs for those 3254 * frames that have been transmitted. 3255 */ 3256 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3257 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3258 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3259 3260 #ifdef ATW_DEBUG 3261 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3262 int i; 3263 printf(" txsoft %p transmit chain:\n", txs); 3264 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3265 txs->txs_ndescs - 1, 3266 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3267 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3268 printf(" descriptor %d:\n", i); 3269 printf(" at_status: 0x%08x\n", 3270 le32toh(sc->sc_txdescs[i].at_stat)); 3271 printf(" at_flags: 0x%08x\n", 3272 le32toh(sc->sc_txdescs[i].at_flags)); 3273 printf(" at_buf1: 0x%08x\n", 3274 le32toh(sc->sc_txdescs[i].at_buf1)); 3275 printf(" at_buf2: 0x%08x\n", 3276 le32toh(sc->sc_txdescs[i].at_buf2)); 3277 if (i == txs->txs_lastdesc) 3278 break; 3279 } 3280 } 3281 #endif 3282 3283 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3284 if (txstat & ATW_TXSTAT_OWN) 3285 break; 3286 3287 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3288 3289 sc->sc_txfree += txs->txs_ndescs; 3290 3291 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3292 0, txs->txs_dmamap->dm_mapsize, 3293 BUS_DMASYNC_POSTWRITE); 3294 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3295 m_freem(txs->txs_mbuf); 3296 txs->txs_mbuf = NULL; 3297 3298 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3299 3300 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3301 sc->sc_txfree == 0)); 3302 ifp->if_flags &= ~IFF_OACTIVE; 3303 3304 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3305 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3306 bitmask_snprintf(txstat & ATW_TXSTAT_ERRMASK, 3307 ATW_TXSTAT_FMT, txstat_buf, sizeof(txstat_buf)); 3308 printf("%s: txstat %s %" __PRIuBITS "\n", 3309 sc->sc_dev.dv_xname, txstat_buf, 3310 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3311 } 3312 3313 /* 3314 * Check for errors and collisions. 3315 */ 3316 if (txstat & ATW_TXSTAT_TUF) 3317 sc->sc_stats.ts_tx_tuf++; 3318 if (txstat & ATW_TXSTAT_TLT) 3319 sc->sc_stats.ts_tx_tlt++; 3320 if (txstat & ATW_TXSTAT_TRT) 3321 sc->sc_stats.ts_tx_trt++; 3322 if (txstat & ATW_TXSTAT_TRO) 3323 sc->sc_stats.ts_tx_tro++; 3324 if (txstat & ATW_TXSTAT_SOFBR) { 3325 sc->sc_stats.ts_tx_sofbr++; 3326 } 3327 3328 if ((txstat & ATW_TXSTAT_ES) == 0) 3329 ifp->if_collisions += 3330 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3331 else 3332 ifp->if_oerrors++; 3333 3334 ifp->if_opackets++; 3335 } 3336 3337 /* 3338 * If there are no more pending transmissions, cancel the watchdog 3339 * timer. 3340 */ 3341 if (txs == NULL) { 3342 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3343 sc->sc_tx_timer = 0; 3344 } 3345 } 3346 3347 /* 3348 * atw_watchdog: [ifnet interface function] 3349 * 3350 * Watchdog timer handler. 3351 */ 3352 void 3353 atw_watchdog(struct ifnet *ifp) 3354 { 3355 struct atw_softc *sc = ifp->if_softc; 3356 struct ieee80211com *ic = &sc->sc_ic; 3357 3358 ifp->if_timer = 0; 3359 if (ATW_IS_ENABLED(sc) == 0) 3360 return; 3361 3362 if (sc->sc_rescan_timer) { 3363 if (--sc->sc_rescan_timer == 0) 3364 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3365 } 3366 if (sc->sc_tx_timer) { 3367 if (--sc->sc_tx_timer == 0 && 3368 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3369 printf("%s: transmit timeout\n", ifp->if_xname); 3370 ifp->if_oerrors++; 3371 (void)atw_init(ifp); 3372 atw_start(ifp); 3373 } 3374 } 3375 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3376 ifp->if_timer = 1; 3377 ieee80211_watchdog(ic); 3378 } 3379 3380 static void 3381 atw_evcnt_detach(struct atw_softc *sc) 3382 { 3383 evcnt_detach(&sc->sc_sige_ev); 3384 evcnt_detach(&sc->sc_sfde_ev); 3385 evcnt_detach(&sc->sc_icve_ev); 3386 evcnt_detach(&sc->sc_crc32e_ev); 3387 evcnt_detach(&sc->sc_crc16e_ev); 3388 evcnt_detach(&sc->sc_recv_ev); 3389 } 3390 3391 static void 3392 atw_evcnt_attach(struct atw_softc *sc) 3393 { 3394 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3395 NULL, sc->sc_if.if_xname, "recv"); 3396 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3397 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3398 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3399 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3400 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3401 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3402 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3403 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3404 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3405 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3406 } 3407 3408 #ifdef ATW_DEBUG 3409 static void 3410 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3411 { 3412 struct atw_softc *sc = ifp->if_softc; 3413 struct mbuf *m; 3414 int i, noctets = 0; 3415 3416 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3417 m0->m_pkthdr.len); 3418 3419 for (m = m0; m; m = m->m_next) { 3420 if (m->m_len == 0) 3421 continue; 3422 for (i = 0; i < m->m_len; i++) { 3423 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3424 if (++noctets % 24 == 0) 3425 printf("\n"); 3426 } 3427 } 3428 printf("%s%s: %d bytes emitted\n", 3429 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3430 } 3431 #endif /* ATW_DEBUG */ 3432 3433 /* 3434 * atw_start: [ifnet interface function] 3435 * 3436 * Start packet transmission on the interface. 3437 */ 3438 void 3439 atw_start(struct ifnet *ifp) 3440 { 3441 struct atw_softc *sc = ifp->if_softc; 3442 struct ieee80211_key *k; 3443 struct ieee80211com *ic = &sc->sc_ic; 3444 struct ieee80211_node *ni; 3445 struct ieee80211_frame_min *whm; 3446 struct ieee80211_frame *wh; 3447 struct atw_frame *hh; 3448 struct mbuf *m0, *m; 3449 struct atw_txsoft *txs, *last_txs; 3450 struct atw_txdesc *txd; 3451 int npkt, rate; 3452 bus_dmamap_t dmamap; 3453 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3454 3455 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3456 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3457 3458 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3459 return; 3460 3461 /* 3462 * Remember the previous number of free descriptors and 3463 * the first descriptor we'll use. 3464 */ 3465 ofree = sc->sc_txfree; 3466 firsttx = lasttx = sc->sc_txnext; 3467 3468 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3469 sc->sc_dev.dv_xname, ofree, firsttx)); 3470 3471 /* 3472 * Loop through the send queue, setting up transmit descriptors 3473 * until we drain the queue, or use up all available transmit 3474 * descriptors. 3475 */ 3476 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3477 sc->sc_txfree != 0) { 3478 3479 /* 3480 * Grab a packet off the management queue, if it 3481 * is not empty. Otherwise, from the data queue. 3482 */ 3483 IF_DEQUEUE(&ic->ic_mgtq, m0); 3484 if (m0 != NULL) { 3485 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3486 m0->m_pkthdr.rcvif = NULL; 3487 } else if (ic->ic_state != IEEE80211_S_RUN) 3488 break; /* send no data until associated */ 3489 else { 3490 IFQ_DEQUEUE(&ifp->if_snd, m0); 3491 if (m0 == NULL) 3492 break; 3493 #if NBPFILTER > 0 3494 if (ifp->if_bpf != NULL) 3495 bpf_mtap(ifp->if_bpf, m0); 3496 #endif /* NBPFILTER > 0 */ 3497 ni = ieee80211_find_txnode(ic, 3498 mtod(m0, struct ether_header *)->ether_dhost); 3499 if (ni == NULL) { 3500 ifp->if_oerrors++; 3501 break; 3502 } 3503 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3504 ieee80211_free_node(ni); 3505 ifp->if_oerrors++; 3506 break; 3507 } 3508 } 3509 3510 rate = MAX(ieee80211_get_rate(ni), 2); 3511 3512 whm = mtod(m0, struct ieee80211_frame_min *); 3513 3514 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3515 k = NULL; 3516 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3517 m_freem(m0); 3518 ieee80211_free_node(ni); 3519 ifp->if_oerrors++; 3520 break; 3521 } 3522 3523 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3524 ic->ic_flags, ic->ic_fragthreshold, rate, 3525 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3526 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3527 m_freem(m0); 3528 break; 3529 } 3530 3531 /* XXX Misleading if fragmentation is enabled. Better 3532 * to fragment in software? 3533 */ 3534 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3535 3536 #if NBPFILTER > 0 3537 /* 3538 * Pass the packet to any BPF listeners. 3539 */ 3540 if (ic->ic_rawbpf != NULL) 3541 bpf_mtap((void *)ic->ic_rawbpf, m0); 3542 3543 if (sc->sc_radiobpf != NULL) { 3544 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3545 3546 tap->at_rate = rate; 3547 3548 bpf_mtap2(sc->sc_radiobpf, tap, 3549 sizeof(sc->sc_txtapu), m0); 3550 } 3551 #endif /* NBPFILTER > 0 */ 3552 3553 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3554 3555 if (ni != NULL) 3556 ieee80211_free_node(ni); 3557 3558 if (m0 == NULL) { 3559 ifp->if_oerrors++; 3560 break; 3561 } 3562 3563 /* just to make sure. */ 3564 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3565 3566 if (m0 == NULL) { 3567 ifp->if_oerrors++; 3568 break; 3569 } 3570 3571 hh = mtod(m0, struct atw_frame *); 3572 wh = &hh->atw_ihdr; 3573 3574 /* Copy everything we need from the 802.11 header: 3575 * Frame Control; address 1, address 3, or addresses 3576 * 3 and 4. NIC fills in BSSID, SA. 3577 */ 3578 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3579 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3580 panic("%s: illegal WDS frame", 3581 sc->sc_dev.dv_xname); 3582 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3583 } else 3584 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3585 3586 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3587 3588 /* initialize remaining Tx parameters */ 3589 memset(&hh->u, 0, sizeof(hh->u)); 3590 3591 hh->atw_rate = rate * 5; 3592 /* XXX this could be incorrect if M_FCS. _encap should 3593 * probably strip FCS just in case it sticks around in 3594 * bridged packets. 3595 */ 3596 hh->atw_service = 0x00; /* XXX guess */ 3597 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3598 sizeof(struct atw_frame)); 3599 3600 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3601 hh->atw_rtylmt = 3; 3602 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3603 #if 0 3604 if (do_encrypt) { 3605 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3606 hh->atw_keyid = ic->ic_def_txkey; 3607 } 3608 #endif 3609 3610 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3611 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3612 if (txs->txs_d0.d_residue) 3613 hh->atw_head_plcplen |= htole16(0x8000); 3614 if (txs->txs_dn.d_residue) 3615 hh->atw_tail_plcplen |= htole16(0x8000); 3616 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3617 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3618 3619 /* never fragment multicast frames */ 3620 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3621 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3622 } else if (sc->sc_flags & ATWF_RTSCTS) { 3623 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3624 } 3625 3626 #ifdef ATW_DEBUG 3627 hh->atw_fragnum = 0; 3628 3629 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3630 printf("%s: dst = %s, rate = 0x%02x, " 3631 "service = 0x%02x, paylen = 0x%04x\n", 3632 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3633 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3634 3635 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3636 "dur1 = 0x%04x, dur2 = 0x%04x, " 3637 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3638 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3639 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3640 hh->atw_tail_dur, hh->atw_head_dur); 3641 3642 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3643 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3644 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3645 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3646 3647 printf("%s: keyid = %d\n", 3648 sc->sc_dev.dv_xname, hh->atw_keyid); 3649 3650 atw_dump_pkt(ifp, m0); 3651 } 3652 #endif /* ATW_DEBUG */ 3653 3654 dmamap = txs->txs_dmamap; 3655 3656 /* 3657 * Load the DMA map. Copy and try (once) again if the packet 3658 * didn't fit in the alloted number of segments. 3659 */ 3660 for (first = 1; 3661 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3662 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3663 first = 0) { 3664 MGETHDR(m, M_DONTWAIT, MT_DATA); 3665 if (m == NULL) { 3666 printf("%s: unable to allocate Tx mbuf\n", 3667 sc->sc_dev.dv_xname); 3668 break; 3669 } 3670 if (m0->m_pkthdr.len > MHLEN) { 3671 MCLGET(m, M_DONTWAIT); 3672 if ((m->m_flags & M_EXT) == 0) { 3673 printf("%s: unable to allocate Tx " 3674 "cluster\n", sc->sc_dev.dv_xname); 3675 m_freem(m); 3676 break; 3677 } 3678 } 3679 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3680 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3681 m_freem(m0); 3682 m0 = m; 3683 m = NULL; 3684 } 3685 if (error != 0) { 3686 printf("%s: unable to load Tx buffer, " 3687 "error = %d\n", sc->sc_dev.dv_xname, error); 3688 m_freem(m0); 3689 break; 3690 } 3691 3692 /* 3693 * Ensure we have enough descriptors free to describe 3694 * the packet. 3695 */ 3696 if (dmamap->dm_nsegs > sc->sc_txfree) { 3697 /* 3698 * Not enough free descriptors to transmit 3699 * this packet. Unload the DMA map and 3700 * drop the packet. Notify the upper layer 3701 * that there are no more slots left. 3702 * 3703 * XXX We could allocate an mbuf and copy, but 3704 * XXX it is worth it? 3705 */ 3706 bus_dmamap_unload(sc->sc_dmat, dmamap); 3707 m_freem(m0); 3708 break; 3709 } 3710 3711 /* 3712 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3713 */ 3714 3715 /* Sync the DMA map. */ 3716 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3717 BUS_DMASYNC_PREWRITE); 3718 3719 /* XXX arbitrary retry limit; 8 because I have seen it in 3720 * use already and maybe 0 means "no tries" ! 3721 */ 3722 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3723 3724 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3725 sc->sc_dev.dv_xname, rate * 5)); 3726 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3727 3728 /* 3729 * Initialize the transmit descriptors. 3730 */ 3731 for (nexttx = sc->sc_txnext, seg = 0; 3732 seg < dmamap->dm_nsegs; 3733 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3734 /* 3735 * If this is the first descriptor we're 3736 * enqueueing, don't set the OWN bit just 3737 * yet. That could cause a race condition. 3738 * We'll do it below. 3739 */ 3740 txd = &sc->sc_txdescs[nexttx]; 3741 txd->at_ctl = ctl | 3742 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3743 3744 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3745 txd->at_flags = 3746 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3747 ATW_TXFLAG_TBS1_MASK)) | 3748 ((nexttx == (ATW_NTXDESC - 1)) 3749 ? htole32(ATW_TXFLAG_TER) : 0); 3750 lasttx = nexttx; 3751 } 3752 3753 /* Set `first segment' and `last segment' appropriately. */ 3754 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3755 htole32(ATW_TXFLAG_FS); 3756 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3757 3758 #ifdef ATW_DEBUG 3759 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3760 printf(" txsoft %p transmit chain:\n", txs); 3761 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3762 printf(" descriptor %d:\n", seg); 3763 printf(" at_ctl: 0x%08x\n", 3764 le32toh(sc->sc_txdescs[seg].at_ctl)); 3765 printf(" at_flags: 0x%08x\n", 3766 le32toh(sc->sc_txdescs[seg].at_flags)); 3767 printf(" at_buf1: 0x%08x\n", 3768 le32toh(sc->sc_txdescs[seg].at_buf1)); 3769 printf(" at_buf2: 0x%08x\n", 3770 le32toh(sc->sc_txdescs[seg].at_buf2)); 3771 if (seg == lasttx) 3772 break; 3773 } 3774 } 3775 #endif 3776 3777 /* Sync the descriptors we're using. */ 3778 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3779 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3780 3781 /* 3782 * Store a pointer to the packet so we can free it later, 3783 * and remember what txdirty will be once the packet is 3784 * done. 3785 */ 3786 txs->txs_mbuf = m0; 3787 txs->txs_firstdesc = sc->sc_txnext; 3788 txs->txs_lastdesc = lasttx; 3789 txs->txs_ndescs = dmamap->dm_nsegs; 3790 3791 /* Advance the tx pointer. */ 3792 sc->sc_txfree -= dmamap->dm_nsegs; 3793 sc->sc_txnext = nexttx; 3794 3795 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3796 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3797 3798 last_txs = txs; 3799 } 3800 3801 if (sc->sc_txfree != ofree) { 3802 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3803 sc->sc_dev.dv_xname, lasttx, firsttx)); 3804 /* 3805 * Cause a transmit interrupt to happen on the 3806 * last packet we enqueued. 3807 */ 3808 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3809 ATW_CDTXSYNC(sc, lasttx, 1, 3810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3811 3812 /* 3813 * The entire packet chain is set up. Give the 3814 * first descriptor to the chip now. 3815 */ 3816 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3817 ATW_CDTXSYNC(sc, firsttx, 1, 3818 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3819 3820 /* Wake up the transmitter. */ 3821 ATW_WRITE(sc, ATW_TDR, 0x1); 3822 3823 if (txs == NULL || sc->sc_txfree == 0) 3824 ifp->if_flags |= IFF_OACTIVE; 3825 3826 /* Set a watchdog timer in case the chip flakes out. */ 3827 sc->sc_tx_timer = 5; 3828 ifp->if_timer = 1; 3829 } 3830 } 3831 3832 /* 3833 * atw_ioctl: [ifnet interface function] 3834 * 3835 * Handle control requests from the operator. 3836 */ 3837 int 3838 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3839 { 3840 struct atw_softc *sc = ifp->if_softc; 3841 int s, error = 0; 3842 3843 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3844 if (!device_is_active(&sc->sc_dev)) 3845 return ENXIO; 3846 3847 s = splnet(); 3848 3849 switch (cmd) { 3850 case SIOCSIFFLAGS: 3851 if (ifp->if_flags & IFF_UP) { 3852 if (ATW_IS_ENABLED(sc)) { 3853 /* 3854 * To avoid rescanning another access point, 3855 * do not call atw_init() here. Instead, 3856 * only reflect media settings. 3857 */ 3858 atw_filter_setup(sc); 3859 } else 3860 error = atw_init(ifp); 3861 } else if (ATW_IS_ENABLED(sc)) 3862 atw_stop(ifp, 1); 3863 break; 3864 case SIOCADDMULTI: 3865 case SIOCDELMULTI: 3866 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3867 if (ifp->if_flags & IFF_RUNNING) 3868 atw_filter_setup(sc); /* do not rescan */ 3869 error = 0; 3870 } 3871 break; 3872 default: 3873 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3874 if (error == ENETRESET || error == ERESTART) { 3875 if (is_running(ifp)) 3876 error = atw_init(ifp); 3877 else 3878 error = 0; 3879 } 3880 break; 3881 } 3882 3883 /* Try to get more packets going. */ 3884 if (ATW_IS_ENABLED(sc)) 3885 atw_start(ifp); 3886 3887 splx(s); 3888 return (error); 3889 } 3890 3891 static int 3892 atw_media_change(struct ifnet *ifp) 3893 { 3894 int error; 3895 3896 error = ieee80211_media_change(ifp); 3897 if (error == ENETRESET) { 3898 if (is_running(ifp)) 3899 error = atw_init(ifp); 3900 else 3901 error = 0; 3902 } 3903 return error; 3904 } 3905
Indexes created Wed Sep 24 15:09:51 GMT 2025