atw.c revision 1.137
1 /* $NetBSD: atw.c,v 1.137 2008/04/08 12:07:25 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.137 2008/04/08 12:07:25 cegger Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 #include <lib/libkern/libkern.h> 60 61 #include <machine/endian.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #include <net80211/ieee80211_netbsd.h> 71 #include <net80211/ieee80211_var.h> 72 #include <net80211/ieee80211_radiotap.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #endif 77 78 #include <sys/bus.h> 79 #include <sys/intr.h> 80 81 #include <dev/ic/atwreg.h> 82 #include <dev/ic/rf3000reg.h> 83 #include <dev/ic/si4136reg.h> 84 #include <dev/ic/atwvar.h> 85 #include <dev/ic/smc93cx6var.h> 86 87 /* XXX TBD open questions 88 * 89 * 90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 92 * handle this for me? 93 * 94 */ 95 /* device attachment 96 * 97 * print TOFS[012] 98 * 99 * device initialization 100 * 101 * clear ATW_FRCTL_MAXPSP to disable max power saving 102 * set ATW_TXBR_ALCUPDATE to enable ALC 103 * set TOFS[012]? (hope not) 104 * disable rx/tx 105 * set ATW_PAR_SWR (software reset) 106 * wait for ATW_PAR_SWR clear 107 * disable interrupts 108 * ack status register 109 * enable interrupts 110 * 111 * rx/tx initialization 112 * 113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * allocate and init descriptor rings 115 * write ATW_PAR_DSL (descriptor skip length) 116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * write ATW_NAR_SQ for one/both transmit descriptor rings 119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 120 * 121 * rx/tx end 122 * 123 * stop DMA 124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 125 * flush tx w/ ATW_NAR_HF 126 * 127 * scan 128 * 129 * initialize rx/tx 130 * 131 * BSS join: (re)association response 132 * 133 * set ATW_FRCTL_AID 134 * 135 * optimizations ??? 136 * 137 */ 138 139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 140 141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 143 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 144 145 int atw_pseudo_milli = 1; 146 int atw_magic_delay1 = 100 * 1000; 147 int atw_magic_delay2 = 100 * 1000; 148 /* more magic multi-millisecond delays (units: microseconds) */ 149 int atw_nar_delay = 20 * 1000; 150 int atw_magic_delay4 = 10 * 1000; 151 int atw_rf_delay1 = 10 * 1000; 152 int atw_rf_delay2 = 5 * 1000; 153 int atw_plcphd_delay = 2 * 1000; 154 int atw_bbp_io_enable_delay = 20 * 1000; 155 int atw_bbp_io_disable_delay = 2 * 1000; 156 int atw_writewep_delay = 1000; 157 int atw_beacon_len_adjust = 4; 158 int atw_dwelltime = 200; 159 int atw_xindiv2 = 0; 160 161 #ifdef ATW_DEBUG 162 int atw_debug = 0; 163 164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 170 171 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 172 static void atw_print_regs(struct atw_softc *, const char *); 173 174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 175 # ifdef ATW_BBPDEBUG 176 static void atw_rf3000_print(struct atw_softc *); 177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 178 # endif /* ATW_BBPDEBUG */ 179 180 # ifdef ATW_SYNDEBUG 181 static void atw_si4126_print(struct atw_softc *); 182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 183 # endif /* ATW_SYNDEBUG */ 184 185 #else 186 #define ATW_DPRINTF(x) 187 #define ATW_DPRINTF2(x) 188 #define ATW_DPRINTF3(x) 189 #define DPRINTF(sc, x) /* nothing */ 190 #define DPRINTF2(sc, x) /* nothing */ 191 #define DPRINTF3(sc, x) /* nothing */ 192 #endif 193 194 /* ifnet methods */ 195 int atw_init(struct ifnet *); 196 int atw_ioctl(struct ifnet *, u_long, void *); 197 void atw_start(struct ifnet *); 198 void atw_stop(struct ifnet *, int); 199 void atw_watchdog(struct ifnet *); 200 201 /* Device attachment */ 202 void atw_attach(struct atw_softc *); 203 int atw_detach(struct atw_softc *); 204 static void atw_evcnt_attach(struct atw_softc *); 205 static void atw_evcnt_detach(struct atw_softc *); 206 207 /* Rx/Tx process */ 208 int atw_add_rxbuf(struct atw_softc *, int); 209 void atw_idle(struct atw_softc *, u_int32_t); 210 void atw_rxdrain(struct atw_softc *); 211 void atw_txdrain(struct atw_softc *); 212 213 /* Device (de)activation and power state */ 214 void atw_disable(struct atw_softc *); 215 int atw_enable(struct atw_softc *); 216 void atw_reset(struct atw_softc *); 217 218 /* Interrupt handlers */ 219 void atw_linkintr(struct atw_softc *, u_int32_t); 220 void atw_rxintr(struct atw_softc *); 221 void atw_txintr(struct atw_softc *); 222 223 /* 802.11 state machine */ 224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 225 static void atw_next_scan(void *); 226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static int atw_tune(struct atw_softc *); 229 230 /* Device initialization */ 231 static void atw_bbp_io_init(struct atw_softc *); 232 static void atw_cfp_init(struct atw_softc *); 233 static void atw_cmdr_init(struct atw_softc *); 234 static void atw_ifs_init(struct atw_softc *); 235 static void atw_nar_init(struct atw_softc *); 236 static void atw_response_times_init(struct atw_softc *); 237 static void atw_rf_reset(struct atw_softc *); 238 static void atw_test1_init(struct atw_softc *); 239 static void atw_tofs0_init(struct atw_softc *); 240 static void atw_tofs2_init(struct atw_softc *); 241 static void atw_txlmt_init(struct atw_softc *); 242 static void atw_wcsr_init(struct atw_softc *); 243 244 /* Key management */ 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 static inline int 316 is_running(struct ifnet *ifp) 317 { 318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 319 } 320 321 int 322 atw_activate(device_t self, enum devact act) 323 { 324 struct atw_softc *sc = device_private(self); 325 int rv = 0, s; 326 327 s = splnet(); 328 switch (act) { 329 case DVACT_ACTIVATE: 330 rv = EOPNOTSUPP; 331 break; 332 333 case DVACT_DEACTIVATE: 334 if_deactivate(&sc->sc_if); 335 break; 336 } 337 splx(s); 338 return rv; 339 } 340 341 /* 342 * atw_enable: 343 * 344 * Enable the ADM8211 chip. 345 */ 346 int 347 atw_enable(struct atw_softc *sc) 348 { 349 350 if (ATW_IS_ENABLED(sc) == 0) { 351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 352 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 353 return (EIO); 354 } 355 sc->sc_flags |= ATWF_ENABLED; 356 /* Power may have been removed, and WEP keys thus 357 * reset. 358 */ 359 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 360 } 361 return (0); 362 } 363 364 /* 365 * atw_disable: 366 * 367 * Disable the ADM8211 chip. 368 */ 369 void 370 atw_disable(struct atw_softc *sc) 371 { 372 if (!ATW_IS_ENABLED(sc)) 373 return; 374 if (sc->sc_disable != NULL) 375 (*sc->sc_disable)(sc); 376 sc->sc_flags &= ~ATWF_ENABLED; 377 } 378 379 /* Returns -1 on failure. */ 380 static int 381 atw_read_srom(struct atw_softc *sc) 382 { 383 struct seeprom_descriptor sd; 384 uint32_t test0, fail_bits; 385 386 (void)memset(&sd, 0, sizeof(sd)); 387 388 test0 = ATW_READ(sc, ATW_TEST0); 389 390 switch (sc->sc_rev) { 391 case ATW_REVISION_BA: 392 case ATW_REVISION_CA: 393 fail_bits = ATW_TEST0_EPNE; 394 break; 395 default: 396 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 397 break; 398 } 399 if ((test0 & fail_bits) != 0) { 400 aprint_error_dev(&sc->sc_dev, "bad or missing/bad SROM\n"); 401 return -1; 402 } 403 404 switch (test0 & ATW_TEST0_EPTYP_MASK) { 405 case ATW_TEST0_EPTYP_93c66: 406 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(&sc->sc_dev))); 407 sc->sc_sromsz = 512; 408 sd.sd_chip = C56_66; 409 break; 410 case ATW_TEST0_EPTYP_93c46: 411 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(&sc->sc_dev))); 412 sc->sc_sromsz = 128; 413 sd.sd_chip = C46; 414 break; 415 default: 416 printf("%s: unknown SROM type %" __PRIuBITS "\n", 417 device_xname(&sc->sc_dev), 418 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 419 return -1; 420 } 421 422 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 423 424 if (sc->sc_srom == NULL) { 425 aprint_error_dev(&sc->sc_dev, "unable to allocate SROM buffer\n"); 426 return -1; 427 } 428 429 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 430 431 /* ADM8211 has a single 32-bit register for controlling the 432 * 93cx6 SROM. Bit SRS enables the serial port. There is no 433 * "ready" bit. The ADM8211 input/output sense is the reverse 434 * of read_seeprom's. 435 */ 436 sd.sd_tag = sc->sc_st; 437 sd.sd_bsh = sc->sc_sh; 438 sd.sd_regsize = 4; 439 sd.sd_control_offset = ATW_SPR; 440 sd.sd_status_offset = ATW_SPR; 441 sd.sd_dataout_offset = ATW_SPR; 442 sd.sd_CK = ATW_SPR_SCLK; 443 sd.sd_CS = ATW_SPR_SCS; 444 sd.sd_DI = ATW_SPR_SDO; 445 sd.sd_DO = ATW_SPR_SDI; 446 sd.sd_MS = ATW_SPR_SRS; 447 sd.sd_RDY = 0; 448 449 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 450 aprint_error_dev(&sc->sc_dev, "could not read SROM\n"); 451 free(sc->sc_srom, M_DEVBUF); 452 return -1; 453 } 454 #ifdef ATW_DEBUG 455 { 456 int i; 457 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 458 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 459 if (((i % 8) == 0) && (i != 0)) { 460 ATW_DPRINTF(("\n\t")); 461 } 462 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 463 } 464 ATW_DPRINTF(("\n")); 465 } 466 #endif /* ATW_DEBUG */ 467 return 0; 468 } 469 470 #ifdef ATW_DEBUG 471 static void 472 atw_print_regs(struct atw_softc *sc, const char *where) 473 { 474 #define PRINTREG(sc, reg) \ 475 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 476 device_xname(&sc->sc_dev), reg, ATW_READ(sc, reg))) 477 478 ATW_DPRINTF2(("%s: %s\n", device_xname(&sc->sc_dev), where)); 479 480 PRINTREG(sc, ATW_PAR); 481 PRINTREG(sc, ATW_FRCTL); 482 PRINTREG(sc, ATW_TDR); 483 PRINTREG(sc, ATW_WTDP); 484 PRINTREG(sc, ATW_RDR); 485 PRINTREG(sc, ATW_WRDP); 486 PRINTREG(sc, ATW_RDB); 487 PRINTREG(sc, ATW_CSR3A); 488 PRINTREG(sc, ATW_TDBD); 489 PRINTREG(sc, ATW_TDBP); 490 PRINTREG(sc, ATW_STSR); 491 PRINTREG(sc, ATW_CSR5A); 492 PRINTREG(sc, ATW_NAR); 493 PRINTREG(sc, ATW_CSR6A); 494 PRINTREG(sc, ATW_IER); 495 PRINTREG(sc, ATW_CSR7A); 496 PRINTREG(sc, ATW_LPC); 497 PRINTREG(sc, ATW_TEST1); 498 PRINTREG(sc, ATW_SPR); 499 PRINTREG(sc, ATW_TEST0); 500 PRINTREG(sc, ATW_WCSR); 501 PRINTREG(sc, ATW_WPDR); 502 PRINTREG(sc, ATW_GPTMR); 503 PRINTREG(sc, ATW_GPIO); 504 PRINTREG(sc, ATW_BBPCTL); 505 PRINTREG(sc, ATW_SYNCTL); 506 PRINTREG(sc, ATW_PLCPHD); 507 PRINTREG(sc, ATW_MMIWADDR); 508 PRINTREG(sc, ATW_MMIRADDR1); 509 PRINTREG(sc, ATW_MMIRADDR2); 510 PRINTREG(sc, ATW_TXBR); 511 PRINTREG(sc, ATW_CSR15A); 512 PRINTREG(sc, ATW_ALCSTAT); 513 PRINTREG(sc, ATW_TOFS2); 514 PRINTREG(sc, ATW_CMDR); 515 PRINTREG(sc, ATW_PCIC); 516 PRINTREG(sc, ATW_PMCSR); 517 PRINTREG(sc, ATW_PAR0); 518 PRINTREG(sc, ATW_PAR1); 519 PRINTREG(sc, ATW_MAR0); 520 PRINTREG(sc, ATW_MAR1); 521 PRINTREG(sc, ATW_ATIMDA0); 522 PRINTREG(sc, ATW_ABDA1); 523 PRINTREG(sc, ATW_BSSID0); 524 PRINTREG(sc, ATW_TXLMT); 525 PRINTREG(sc, ATW_MIBCNT); 526 PRINTREG(sc, ATW_BCNT); 527 PRINTREG(sc, ATW_TSFTH); 528 PRINTREG(sc, ATW_TSC); 529 PRINTREG(sc, ATW_SYNRF); 530 PRINTREG(sc, ATW_BPLI); 531 PRINTREG(sc, ATW_CAP0); 532 PRINTREG(sc, ATW_CAP1); 533 PRINTREG(sc, ATW_RMD); 534 PRINTREG(sc, ATW_CFPP); 535 PRINTREG(sc, ATW_TOFS0); 536 PRINTREG(sc, ATW_TOFS1); 537 PRINTREG(sc, ATW_IFST); 538 PRINTREG(sc, ATW_RSPT); 539 PRINTREG(sc, ATW_TSFTL); 540 PRINTREG(sc, ATW_WEPCTL); 541 PRINTREG(sc, ATW_WESK); 542 PRINTREG(sc, ATW_WEPCNT); 543 PRINTREG(sc, ATW_MACTEST); 544 PRINTREG(sc, ATW_FER); 545 PRINTREG(sc, ATW_FEMR); 546 PRINTREG(sc, ATW_FPSR); 547 PRINTREG(sc, ATW_FFER); 548 #undef PRINTREG 549 } 550 #endif /* ATW_DEBUG */ 551 552 /* 553 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 554 */ 555 void 556 atw_attach(struct atw_softc *sc) 557 { 558 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 560 }; 561 struct ieee80211com *ic = &sc->sc_ic; 562 struct ifnet *ifp = &sc->sc_if; 563 int country_code, error, i, nrate, srom_major; 564 u_int32_t reg; 565 static const char *type_strings[] = {"Intersil (not supported)", 566 "RFMD", "Marvel (not supported)"}; 567 568 sc->sc_txth = atw_txthresh_tab_lo; 569 570 SIMPLEQ_INIT(&sc->sc_txfreeq); 571 SIMPLEQ_INIT(&sc->sc_txdirtyq); 572 573 #ifdef ATW_DEBUG 574 atw_print_regs(sc, "atw_attach"); 575 #endif /* ATW_DEBUG */ 576 577 /* 578 * Allocate the control data structures, and create and load the 579 * DMA map for it. 580 */ 581 if ((error = bus_dmamem_alloc(sc->sc_dmat, 582 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 583 1, &sc->sc_cdnseg, 0)) != 0) { 584 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 585 error); 586 goto fail_0; 587 } 588 589 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 590 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 591 BUS_DMA_COHERENT)) != 0) { 592 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 593 error); 594 goto fail_1; 595 } 596 597 if ((error = bus_dmamap_create(sc->sc_dmat, 598 sizeof(struct atw_control_data), 1, 599 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 600 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 601 "error = %d\n", error); 602 goto fail_2; 603 } 604 605 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 606 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 607 0)) != 0) { 608 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 609 error); 610 goto fail_3; 611 } 612 613 /* 614 * Create the transmit buffer DMA maps. 615 */ 616 sc->sc_ntxsegs = ATW_NTXSEGS; 617 for (i = 0; i < ATW_TXQUEUELEN; i++) { 618 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 619 sc->sc_ntxsegs, MCLBYTES, 0, 0, 620 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 621 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 622 "error = %d\n", i, error); 623 goto fail_4; 624 } 625 } 626 627 /* 628 * Create the receive buffer DMA maps. 629 */ 630 for (i = 0; i < ATW_NRXDESC; i++) { 631 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 632 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 633 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 634 "error = %d\n", i, error); 635 goto fail_5; 636 } 637 } 638 for (i = 0; i < ATW_NRXDESC; i++) { 639 sc->sc_rxsoft[i].rxs_mbuf = NULL; 640 } 641 642 switch (sc->sc_rev) { 643 case ATW_REVISION_AB: 644 case ATW_REVISION_AF: 645 sc->sc_sramlen = ATW_SRAM_A_SIZE; 646 break; 647 case ATW_REVISION_BA: 648 case ATW_REVISION_CA: 649 sc->sc_sramlen = ATW_SRAM_B_SIZE; 650 break; 651 } 652 653 /* Reset the chip to a known state. */ 654 atw_reset(sc); 655 656 if (atw_read_srom(sc) == -1) 657 return; 658 659 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 660 ATW_SR_RFTYPE_MASK); 661 662 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 663 ATW_SR_BBPTYPE_MASK); 664 665 if (sc->sc_rftype >= __arraycount(type_strings)) { 666 aprint_error_dev(&sc->sc_dev, "unknown RF\n"); 667 return; 668 } 669 if (sc->sc_bbptype >= __arraycount(type_strings)) { 670 aprint_error_dev(&sc->sc_dev, "unknown BBP\n"); 671 return; 672 } 673 674 printf("%s: %s RF, %s BBP", device_xname(&sc->sc_dev), 675 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 676 677 /* XXX There exists a Linux driver which seems to use RFType = 0 for 678 * MARVEL. My bug, or theirs? 679 */ 680 681 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 682 683 switch (sc->sc_rftype) { 684 case ATW_RFTYPE_INTERSIL: 685 reg |= ATW_SYNCTL_CS1; 686 break; 687 case ATW_RFTYPE_RFMD: 688 reg |= ATW_SYNCTL_CS0; 689 break; 690 case ATW_RFTYPE_MARVEL: 691 break; 692 } 693 694 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 695 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 696 697 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 698 699 switch (sc->sc_bbptype) { 700 case ATW_BBPTYPE_INTERSIL: 701 reg |= ATW_BBPCTL_TWI; 702 break; 703 case ATW_BBPTYPE_RFMD: 704 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 705 ATW_BBPCTL_CCA_ACTLO; 706 break; 707 case ATW_BBPTYPE_MARVEL: 708 break; 709 case ATW_C_BBPTYPE_RFMD: 710 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 711 device_xname(&sc->sc_dev)); 712 break; 713 } 714 715 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 716 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 717 718 /* 719 * From this point forward, the attachment cannot fail. A failure 720 * before this point releases all resources that may have been 721 * allocated. 722 */ 723 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 724 725 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 726 htole16(sc->sc_srom[ATW_SR_MAC00]), 727 htole16(sc->sc_srom[ATW_SR_MAC01]), 728 htole16(sc->sc_srom[ATW_SR_MAC10]))); 729 730 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 731 ATW_SR_MAJOR_MASK); 732 733 if (srom_major < 2) 734 sc->sc_rf3000_options1 = 0; 735 else if (sc->sc_rev == ATW_REVISION_BA) { 736 sc->sc_rf3000_options1 = 737 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 738 ATW_SR_CR28_MASK); 739 } else 740 sc->sc_rf3000_options1 = 0; 741 742 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 743 ATW_SR_CR29_MASK); 744 745 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 746 ATW_SR_CTRY_MASK); 747 748 #define ADD_CHANNEL(_ic, _chan) do { \ 749 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 750 _ic->ic_channels[_chan].ic_freq = \ 751 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 752 } while (0) 753 754 /* Find available channels */ 755 switch (country_code) { 756 case COUNTRY_MMK2: /* 1-14 */ 757 ADD_CHANNEL(ic, 14); 758 /*FALLTHROUGH*/ 759 case COUNTRY_ETSI: /* 1-13 */ 760 for (i = 1; i <= 13; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 case COUNTRY_FCC: /* 1-11 */ 764 case COUNTRY_IC: /* 1-11 */ 765 for (i = 1; i <= 11; i++) 766 ADD_CHANNEL(ic, i); 767 break; 768 case COUNTRY_MMK: /* 14 */ 769 ADD_CHANNEL(ic, 14); 770 break; 771 case COUNTRY_FRANCE: /* 10-13 */ 772 for (i = 10; i <= 13; i++) 773 ADD_CHANNEL(ic, i); 774 break; 775 default: /* assume channels 10-11 */ 776 case COUNTRY_SPAIN: /* 10-11 */ 777 for (i = 10; i <= 11; i++) 778 ADD_CHANNEL(ic, i); 779 break; 780 } 781 782 /* Read the MAC address. */ 783 reg = ATW_READ(sc, ATW_PAR0); 784 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 785 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 786 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 787 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 788 reg = ATW_READ(sc, ATW_PAR1); 789 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 790 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 791 792 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 793 printf(" could not get mac address, attach failed\n"); 794 return; 795 } 796 797 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 798 799 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 800 ifp->if_softc = sc; 801 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 802 IFF_NOTRAILERS; 803 ifp->if_ioctl = atw_ioctl; 804 ifp->if_start = atw_start; 805 ifp->if_watchdog = atw_watchdog; 806 ifp->if_init = atw_init; 807 ifp->if_stop = atw_stop; 808 IFQ_SET_READY(&ifp->if_snd); 809 810 ic->ic_ifp = ifp; 811 ic->ic_phytype = IEEE80211_T_DS; 812 ic->ic_opmode = IEEE80211_M_STA; 813 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 814 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 815 816 nrate = 0; 817 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 822 823 /* 824 * Call MI attach routines. 825 */ 826 827 if_attach(ifp); 828 ieee80211_ifattach(ic); 829 830 atw_evcnt_attach(sc); 831 832 sc->sc_newstate = ic->ic_newstate; 833 ic->ic_newstate = atw_newstate; 834 835 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 836 ic->ic_recv_mgmt = atw_recv_mgmt; 837 838 sc->sc_node_free = ic->ic_node_free; 839 ic->ic_node_free = atw_node_free; 840 841 sc->sc_node_alloc = ic->ic_node_alloc; 842 ic->ic_node_alloc = atw_node_alloc; 843 844 ic->ic_crypto.cs_key_delete = atw_key_delete; 845 ic->ic_crypto.cs_key_set = atw_key_set; 846 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 847 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 848 849 /* possibly we should fill in our own sc_send_prresp, since 850 * the ADM8211 is probably sending probe responses in ad hoc 851 * mode. 852 */ 853 854 /* complete initialization */ 855 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 856 callout_init(&sc->sc_scan_ch, 0); 857 858 #if NBPFILTER > 0 859 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 860 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 861 #endif 862 863 if (!pmf_device_register1(&sc->sc_dev, NULL, NULL, atw_shutdown)) { 864 aprint_error_dev(&sc->sc_dev, 865 "couldn't establish power handler\n"); 866 } else 867 pmf_class_network_register(&sc->sc_dev, &sc->sc_if); 868 869 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 870 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 871 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 872 873 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 874 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 875 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 876 877 ieee80211_announce(ic); 878 return; 879 880 /* 881 * Free any resources we've allocated during the failed attach 882 * attempt. Do this in reverse order and fall through. 883 */ 884 fail_5: 885 for (i = 0; i < ATW_NRXDESC; i++) { 886 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 887 continue; 888 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 889 } 890 fail_4: 891 for (i = 0; i < ATW_TXQUEUELEN; i++) { 892 if (sc->sc_txsoft[i].txs_dmamap == NULL) 893 continue; 894 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 895 } 896 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 897 fail_3: 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 899 fail_2: 900 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 901 sizeof(struct atw_control_data)); 902 fail_1: 903 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 904 fail_0: 905 return; 906 } 907 908 static struct ieee80211_node * 909 atw_node_alloc(struct ieee80211_node_table *nt) 910 { 911 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 912 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 913 914 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(&sc->sc_dev), ni)); 915 return ni; 916 } 917 918 static void 919 atw_node_free(struct ieee80211_node *ni) 920 { 921 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 922 923 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(&sc->sc_dev), ni, 924 ether_sprintf(ni->ni_bssid))); 925 (*sc->sc_node_free)(ni); 926 } 927 928 929 static void 930 atw_test1_reset(struct atw_softc *sc) 931 { 932 switch (sc->sc_rev) { 933 case ATW_REVISION_BA: 934 if (1 /* XXX condition on transceiver type */) { 935 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 936 } 937 break; 938 case ATW_REVISION_CA: 939 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 940 break; 941 default: 942 break; 943 } 944 } 945 946 /* 947 * atw_reset: 948 * 949 * Perform a soft reset on the ADM8211. 950 */ 951 void 952 atw_reset(struct atw_softc *sc) 953 { 954 int i; 955 uint32_t lpc; 956 957 ATW_WRITE(sc, ATW_NAR, 0x0); 958 DELAY(atw_nar_delay); 959 960 /* Reference driver has a cryptic remark indicating that this might 961 * power-on the chip. I know that it turns off power-saving.... 962 */ 963 ATW_WRITE(sc, ATW_FRCTL, 0x0); 964 965 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 966 967 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 968 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 969 break; 970 DELAY(atw_pseudo_milli); 971 } 972 973 /* ... and then pause 100ms longer for good measure. */ 974 DELAY(atw_magic_delay1); 975 976 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(&sc->sc_dev), i)); 977 978 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 979 aprint_error_dev(&sc->sc_dev, "reset failed to complete\n"); 980 981 /* 982 * Initialize the PCI Access Register. 983 */ 984 sc->sc_busmode = ATW_PAR_PBL_8DW; 985 986 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 987 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(&sc->sc_dev), 988 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 989 990 atw_test1_reset(sc); 991 992 /* Turn off maximum power saving, etc. */ 993 ATW_WRITE(sc, ATW_FRCTL, 0x0); 994 995 DELAY(atw_magic_delay2); 996 997 /* Recall EEPROM. */ 998 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 999 1000 DELAY(atw_magic_delay4); 1001 1002 lpc = ATW_READ(sc, ATW_LPC); 1003 1004 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1005 1006 /* A reset seems to affect the SRAM contents, so put them into 1007 * a known state. 1008 */ 1009 atw_clear_sram(sc); 1010 1011 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1012 } 1013 1014 static void 1015 atw_clear_sram(struct atw_softc *sc) 1016 { 1017 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1018 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1019 /* XXX not for revision 0x20. */ 1020 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1021 } 1022 1023 /* TBD atw_init 1024 * 1025 * set MAC based on ic->ic_bss->myaddr 1026 * write WEP keys 1027 * set TX rate 1028 */ 1029 1030 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1031 * without receiving a beacon with the preferred BSSID & SSID. 1032 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1033 */ 1034 static void 1035 atw_wcsr_init(struct atw_softc *sc) 1036 { 1037 uint32_t wcsr; 1038 1039 wcsr = ATW_READ(sc, ATW_WCSR); 1040 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1041 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1042 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1043 1044 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1045 device_xname(&sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1046 } 1047 1048 /* Turn off power management. Set Rx store-and-forward mode. */ 1049 static void 1050 atw_cmdr_init(struct atw_softc *sc) 1051 { 1052 uint32_t cmdr; 1053 cmdr = ATW_READ(sc, ATW_CMDR); 1054 cmdr &= ~ATW_CMDR_APM; 1055 cmdr |= ATW_CMDR_RTE; 1056 cmdr &= ~ATW_CMDR_DRT_MASK; 1057 cmdr |= ATW_CMDR_DRT_SF; 1058 1059 ATW_WRITE(sc, ATW_CMDR, cmdr); 1060 } 1061 1062 static void 1063 atw_tofs2_init(struct atw_softc *sc) 1064 { 1065 uint32_t tofs2; 1066 /* XXX this magic can probably be figured out from the RFMD docs */ 1067 #ifndef ATW_REFSLAVE 1068 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1069 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1070 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1071 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1072 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1073 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1074 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1075 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1076 #else 1077 /* XXX new magic from reference driver source */ 1078 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1079 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1080 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1081 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1082 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1083 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1084 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1085 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1086 #endif 1087 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1088 } 1089 1090 static void 1091 atw_nar_init(struct atw_softc *sc) 1092 { 1093 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1094 } 1095 1096 static void 1097 atw_txlmt_init(struct atw_softc *sc) 1098 { 1099 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1100 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1101 } 1102 1103 static void 1104 atw_test1_init(struct atw_softc *sc) 1105 { 1106 uint32_t test1; 1107 1108 test1 = ATW_READ(sc, ATW_TEST1); 1109 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1110 /* XXX magic 0x1 */ 1111 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1112 ATW_WRITE(sc, ATW_TEST1, test1); 1113 } 1114 1115 static void 1116 atw_rf_reset(struct atw_softc *sc) 1117 { 1118 /* XXX this resets an Intersil RF front-end? */ 1119 /* TBD condition on Intersil RFType? */ 1120 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1121 DELAY(atw_rf_delay1); 1122 ATW_WRITE(sc, ATW_SYNRF, 0); 1123 DELAY(atw_rf_delay2); 1124 } 1125 1126 /* Set 16 TU max duration for the contention-free period (CFP). */ 1127 static void 1128 atw_cfp_init(struct atw_softc *sc) 1129 { 1130 uint32_t cfpp; 1131 1132 cfpp = ATW_READ(sc, ATW_CFPP); 1133 cfpp &= ~ATW_CFPP_CFPMD; 1134 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1135 ATW_WRITE(sc, ATW_CFPP, cfpp); 1136 } 1137 1138 static void 1139 atw_tofs0_init(struct atw_softc *sc) 1140 { 1141 /* XXX I guess that the Cardbus clock is 22 MHz? 1142 * I am assuming that the role of ATW_TOFS0_USCNT is 1143 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1144 * very clear on this point. It says in the datasheet that it is 1145 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1146 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1147 * these values. These values are also the power-on default. 1148 */ 1149 ATW_WRITE(sc, ATW_TOFS0, 1150 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1151 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1152 } 1153 1154 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1155 static void 1156 atw_ifs_init(struct atw_softc *sc) 1157 { 1158 uint32_t ifst; 1159 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1160 * Go figure. 1161 */ 1162 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1163 __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1164 ATW_IFST_SIFS_MASK) | 1165 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1166 __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1167 1168 ATW_WRITE(sc, ATW_IFST, ifst); 1169 } 1170 1171 static void 1172 atw_response_times_init(struct atw_softc *sc) 1173 { 1174 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1175 * indicate that the MAC expects at least SIFS + MIRT microseconds 1176 * to pass after it transmits a frame that requires a response; 1177 * it waits at most SIFS + MART microseconds for the response. 1178 * Surely this is not the ACK timeout? 1179 */ 1180 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1181 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1182 } 1183 1184 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1185 * engines read and write baseband registers after Rx and before 1186 * Tx, respectively. 1187 */ 1188 static void 1189 atw_bbp_io_init(struct atw_softc *sc) 1190 { 1191 uint32_t mmiraddr2; 1192 1193 /* XXX The reference driver does this, but is it *really* 1194 * necessary? 1195 */ 1196 switch (sc->sc_rev) { 1197 case ATW_REVISION_AB: 1198 case ATW_REVISION_AF: 1199 mmiraddr2 = 0x0; 1200 break; 1201 default: 1202 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1203 mmiraddr2 &= 1204 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1205 break; 1206 } 1207 1208 switch (sc->sc_bbptype) { 1209 case ATW_BBPTYPE_INTERSIL: 1210 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1211 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1212 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1213 break; 1214 case ATW_BBPTYPE_MARVEL: 1215 /* TBD find out the Marvel settings. */ 1216 break; 1217 case ATW_BBPTYPE_RFMD: 1218 default: 1219 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1220 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1221 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1222 break; 1223 } 1224 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1225 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1226 } 1227 1228 /* 1229 * atw_init: [ ifnet interface function ] 1230 * 1231 * Initialize the interface. Must be called at splnet(). 1232 */ 1233 int 1234 atw_init(struct ifnet *ifp) 1235 { 1236 struct atw_softc *sc = ifp->if_softc; 1237 struct ieee80211com *ic = &sc->sc_ic; 1238 struct atw_txsoft *txs; 1239 struct atw_rxsoft *rxs; 1240 int i, error = 0; 1241 1242 if ((error = atw_enable(sc)) != 0) 1243 goto out; 1244 1245 /* 1246 * Cancel any pending I/O. This also resets. 1247 */ 1248 atw_stop(ifp, 0); 1249 1250 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1251 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1252 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1253 1254 atw_wcsr_init(sc); 1255 1256 atw_cmdr_init(sc); 1257 1258 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1259 * 1260 * XXX Set transmit power for ATIM, RTS, Beacon. 1261 */ 1262 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1263 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1264 1265 atw_tofs2_init(sc); 1266 1267 atw_nar_init(sc); 1268 1269 atw_txlmt_init(sc); 1270 1271 atw_test1_init(sc); 1272 1273 atw_rf_reset(sc); 1274 1275 atw_cfp_init(sc); 1276 1277 atw_tofs0_init(sc); 1278 1279 atw_ifs_init(sc); 1280 1281 /* XXX Fall asleep after one second of inactivity. 1282 * XXX A frame may only dribble in for 65536us. 1283 */ 1284 ATW_WRITE(sc, ATW_RMD, 1285 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1286 1287 atw_response_times_init(sc); 1288 1289 atw_bbp_io_init(sc); 1290 1291 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1292 1293 if ((error = atw_rf3000_init(sc)) != 0) 1294 goto out; 1295 1296 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1297 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(&sc->sc_dev), 1298 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1299 1300 /* 1301 * Initialize the transmit descriptor ring. 1302 */ 1303 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1304 for (i = 0; i < ATW_NTXDESC; i++) { 1305 sc->sc_txdescs[i].at_ctl = 0; 1306 /* no transmit chaining */ 1307 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1308 sc->sc_txdescs[i].at_buf2 = 1309 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1310 } 1311 /* use ring mode */ 1312 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1313 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1314 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1315 sc->sc_txfree = ATW_NTXDESC; 1316 sc->sc_txnext = 0; 1317 1318 /* 1319 * Initialize the transmit job descriptors. 1320 */ 1321 SIMPLEQ_INIT(&sc->sc_txfreeq); 1322 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1323 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1324 txs = &sc->sc_txsoft[i]; 1325 txs->txs_mbuf = NULL; 1326 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1327 } 1328 1329 /* 1330 * Initialize the receive descriptor and receive job 1331 * descriptor rings. 1332 */ 1333 for (i = 0; i < ATW_NRXDESC; i++) { 1334 rxs = &sc->sc_rxsoft[i]; 1335 if (rxs->rxs_mbuf == NULL) { 1336 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1337 aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx " 1338 "buffer %d, error = %d\n", 1339 i, error); 1340 /* 1341 * XXX Should attempt to run with fewer receive 1342 * XXX buffers instead of just failing. 1343 */ 1344 atw_rxdrain(sc); 1345 goto out; 1346 } 1347 } else 1348 atw_init_rxdesc(sc, i); 1349 } 1350 sc->sc_rxptr = 0; 1351 1352 /* 1353 * Initialize the interrupt mask and enable interrupts. 1354 */ 1355 /* normal interrupts */ 1356 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1357 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1358 1359 /* abnormal interrupts */ 1360 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1361 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1362 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1363 1364 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1365 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1366 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1367 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1368 ATW_INTR_TRT; 1369 1370 sc->sc_linkint_mask &= sc->sc_inten; 1371 sc->sc_rxint_mask &= sc->sc_inten; 1372 sc->sc_txint_mask &= sc->sc_inten; 1373 1374 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1375 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1376 1377 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1378 device_xname(&sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1379 1380 /* 1381 * Give the transmit and receive rings to the ADM8211. 1382 */ 1383 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1384 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1385 1386 sc->sc_txthresh = 0; 1387 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1388 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1389 1390 /* common 802.11 configuration */ 1391 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1392 switch (ic->ic_opmode) { 1393 case IEEE80211_M_STA: 1394 break; 1395 case IEEE80211_M_AHDEMO: /* XXX */ 1396 case IEEE80211_M_IBSS: 1397 ic->ic_flags |= IEEE80211_F_IBSSON; 1398 /*FALLTHROUGH*/ 1399 case IEEE80211_M_HOSTAP: /* XXX */ 1400 break; 1401 case IEEE80211_M_MONITOR: /* XXX */ 1402 break; 1403 } 1404 1405 switch (ic->ic_opmode) { 1406 case IEEE80211_M_AHDEMO: 1407 case IEEE80211_M_HOSTAP: 1408 #ifndef IEEE80211_NO_HOSTAP 1409 ic->ic_bss->ni_intval = ic->ic_lintval; 1410 ic->ic_bss->ni_rssi = 0; 1411 ic->ic_bss->ni_rstamp = 0; 1412 #endif /* !IEEE80211_NO_HOSTAP */ 1413 break; 1414 default: /* XXX */ 1415 break; 1416 } 1417 1418 sc->sc_wepctl = 0; 1419 1420 atw_write_ssid(sc); 1421 atw_write_sup_rates(sc); 1422 atw_write_wep(sc); 1423 1424 ic->ic_state = IEEE80211_S_INIT; 1425 1426 /* 1427 * Set the receive filter. This will start the transmit and 1428 * receive processes. 1429 */ 1430 atw_filter_setup(sc); 1431 1432 /* 1433 * Start the receive process. 1434 */ 1435 ATW_WRITE(sc, ATW_RDR, 0x1); 1436 1437 /* 1438 * Note that the interface is now running. 1439 */ 1440 ifp->if_flags |= IFF_RUNNING; 1441 ifp->if_flags &= ~IFF_OACTIVE; 1442 1443 /* send no beacons, yet. */ 1444 atw_start_beacon(sc, 0); 1445 1446 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1447 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1448 else 1449 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1450 out: 1451 if (error) { 1452 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1453 sc->sc_tx_timer = 0; 1454 ifp->if_timer = 0; 1455 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1456 } 1457 #ifdef ATW_DEBUG 1458 atw_print_regs(sc, "end of init"); 1459 #endif /* ATW_DEBUG */ 1460 1461 return (error); 1462 } 1463 1464 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1465 * 0: MAC control of RF3000/Si4126. 1466 * 1467 * Applies power, or selects RF front-end? Sets reset condition. 1468 * 1469 * TBD support non-RFMD BBP, non-SiLabs synth. 1470 */ 1471 static void 1472 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1473 { 1474 if (enable) { 1475 ATW_WRITE(sc, ATW_SYNRF, 1476 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1477 DELAY(atw_bbp_io_enable_delay); 1478 } else { 1479 ATW_WRITE(sc, ATW_SYNRF, 0); 1480 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1481 } 1482 } 1483 1484 static int 1485 atw_tune(struct atw_softc *sc) 1486 { 1487 int rc; 1488 u_int chan; 1489 struct ieee80211com *ic = &sc->sc_ic; 1490 1491 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1492 if (chan == IEEE80211_CHAN_ANY) 1493 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1494 1495 if (chan == sc->sc_cur_chan) 1496 return 0; 1497 1498 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(&sc->sc_dev), 1499 sc->sc_cur_chan, chan)); 1500 1501 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1502 1503 atw_si4126_tune(sc, chan); 1504 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1505 printf("%s: failed to tune channel %d\n", device_xname(&sc->sc_dev), 1506 chan); 1507 1508 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1509 DELAY(atw_nar_delay); 1510 ATW_WRITE(sc, ATW_RDR, 0x1); 1511 1512 if (rc == 0) { 1513 sc->sc_cur_chan = chan; 1514 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1515 htole16(ic->ic_curchan->ic_freq); 1516 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1517 htole16(ic->ic_curchan->ic_flags); 1518 } 1519 1520 return rc; 1521 } 1522 1523 #ifdef ATW_SYNDEBUG 1524 static void 1525 atw_si4126_print(struct atw_softc *sc) 1526 { 1527 struct ifnet *ifp = &sc->sc_if; 1528 u_int addr, val; 1529 1530 val = 0; 1531 1532 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1533 return; 1534 1535 for (addr = 0; addr <= 8; addr++) { 1536 printf("%s: synth[%d] = ", device_xname(&sc->sc_dev), addr); 1537 if (atw_si4126_read(sc, addr, &val) == 0) { 1538 printf("<unknown> (quitting print-out)\n"); 1539 break; 1540 } 1541 printf("%05x\n", val); 1542 } 1543 } 1544 #endif /* ATW_SYNDEBUG */ 1545 1546 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1547 * 1548 * The RF/IF synthesizer produces two reference frequencies for 1549 * the RF2948B transceiver. The first frequency the RF2948B requires 1550 * is two times the so-called "intermediate frequency" (IF). Since 1551 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1552 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1553 * frequency required by the transceiver is the radio frequency 1554 * (RF). This is a superheterodyne transceiver; for f(chan) the 1555 * center frequency of the channel we are tuning, RF = f(chan) - 1556 * IF. 1557 * 1558 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1559 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1560 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1561 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1562 */ 1563 static void 1564 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1565 { 1566 u_int mhz; 1567 u_int R; 1568 u_int32_t gpio; 1569 u_int16_t gain; 1570 1571 #ifdef ATW_SYNDEBUG 1572 atw_si4126_print(sc); 1573 #endif /* ATW_SYNDEBUG */ 1574 1575 if (chan == 14) 1576 mhz = 2484; 1577 else 1578 mhz = 2412 + 5 * (chan - 1); 1579 1580 /* Tune IF to 748 MHz to suit the IF LO input of the 1581 * RF2494B, which is 2 x IF. No need to set an IF divider 1582 * because an IF in 526 MHz - 952 MHz is allowed. 1583 * 1584 * XIN is 44.000 MHz, so divide it by two to get allowable 1585 * range of 2-25 MHz. SiLabs tells me that this is not 1586 * strictly necessary. 1587 */ 1588 1589 if (atw_xindiv2) 1590 R = 44; 1591 else 1592 R = 88; 1593 1594 /* Power-up RF, IF synthesizers. */ 1595 atw_si4126_write(sc, SI4126_POWER, 1596 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1597 1598 /* set LPWR, too? */ 1599 atw_si4126_write(sc, SI4126_MAIN, 1600 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1601 1602 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1603 * set KP2 to 1. 1604 * 1605 * REFDIF This is different from the reference driver, which 1606 * always sets SI4126_GAIN to 0. 1607 */ 1608 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1609 1610 atw_si4126_write(sc, SI4126_GAIN, gain); 1611 1612 /* XIN = 44 MHz. 1613 * 1614 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1615 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1616 * 1617 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1618 * so that 1496/88 * 44 MHz = 748 MHz. 1619 */ 1620 atw_si4126_write(sc, SI4126_IFN, 1496); 1621 1622 atw_si4126_write(sc, SI4126_IFR, R); 1623 1624 #ifndef ATW_REFSLAVE 1625 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1626 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1627 * which has no RF1! 1628 */ 1629 atw_si4126_write(sc, SI4126_RF1R, R); 1630 1631 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1632 #endif 1633 1634 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1635 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1636 * Now let's multiply it to mhz. So mhz - IF = N. 1637 */ 1638 atw_si4126_write(sc, SI4126_RF2R, R); 1639 1640 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1641 1642 /* wait 100us from power-up for RF, IF to settle */ 1643 DELAY(100); 1644 1645 gpio = ATW_READ(sc, ATW_GPIO); 1646 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1647 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1648 1649 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1650 /* Set a Prism RF front-end to a special mode for channel 14? 1651 * 1652 * Apparently the SMC2635W needs this, although I don't think 1653 * it has a Prism RF. 1654 */ 1655 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1656 } 1657 ATW_WRITE(sc, ATW_GPIO, gpio); 1658 1659 #ifdef ATW_SYNDEBUG 1660 atw_si4126_print(sc); 1661 #endif /* ATW_SYNDEBUG */ 1662 } 1663 1664 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1665 * diversity. 1666 * 1667 * !!! 1668 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1669 * !!! 1670 */ 1671 static int 1672 atw_rf3000_init(struct atw_softc *sc) 1673 { 1674 int rc = 0; 1675 1676 atw_bbp_io_enable(sc, 1); 1677 1678 /* CCA is acquisition sensitive */ 1679 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1680 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1681 1682 if (rc != 0) 1683 goto out; 1684 1685 /* enable diversity */ 1686 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1687 1688 if (rc != 0) 1689 goto out; 1690 1691 /* sensible setting from a binary-only driver */ 1692 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1693 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1694 1695 if (rc != 0) 1696 goto out; 1697 1698 /* magic from a binary-only driver */ 1699 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1700 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1701 1702 if (rc != 0) 1703 goto out; 1704 1705 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1706 1707 if (rc != 0) 1708 goto out; 1709 1710 /* XXX Reference driver remarks that Abocom sets this to 50. 1711 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1712 * in the "reserved" area of register RF3000_OPTIONS1. 1713 */ 1714 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1715 1716 if (rc != 0) 1717 goto out; 1718 1719 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1720 1721 if (rc != 0) 1722 goto out; 1723 1724 out: 1725 atw_bbp_io_enable(sc, 0); 1726 return rc; 1727 } 1728 1729 #ifdef ATW_BBPDEBUG 1730 static void 1731 atw_rf3000_print(struct atw_softc *sc) 1732 { 1733 struct ifnet *ifp = &sc->sc_if; 1734 u_int addr, val; 1735 1736 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1737 return; 1738 1739 for (addr = 0x01; addr <= 0x15; addr++) { 1740 printf("%s: bbp[%d] = \n", device_xname(&sc->sc_dev), addr); 1741 if (atw_rf3000_read(sc, addr, &val) != 0) { 1742 printf("<unknown> (quitting print-out)\n"); 1743 break; 1744 } 1745 printf("%08x\n", val); 1746 } 1747 } 1748 #endif /* ATW_BBPDEBUG */ 1749 1750 /* Set the power settings on the BBP for channel `chan'. */ 1751 static int 1752 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1753 { 1754 int rc = 0; 1755 u_int32_t reg; 1756 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1757 1758 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1759 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1760 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1761 1762 /* odd channels: LSB, even channels: MSB */ 1763 if (chan % 2 == 1) { 1764 txpower &= 0xFF; 1765 lpf_cutoff &= 0xFF; 1766 lna_gs_thresh &= 0xFF; 1767 } else { 1768 txpower >>= 8; 1769 lpf_cutoff >>= 8; 1770 lna_gs_thresh >>= 8; 1771 } 1772 1773 #ifdef ATW_BBPDEBUG 1774 atw_rf3000_print(sc); 1775 #endif /* ATW_BBPDEBUG */ 1776 1777 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1778 "lna_gs_thresh %02x\n", 1779 device_xname(&sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1780 1781 atw_bbp_io_enable(sc, 1); 1782 1783 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1784 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1785 goto out; 1786 1787 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1788 goto out; 1789 1790 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1791 goto out; 1792 1793 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1794 1795 if (rc != 0) 1796 goto out; 1797 1798 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1799 1800 if (rc != 0) 1801 goto out; 1802 1803 #ifdef ATW_BBPDEBUG 1804 atw_rf3000_print(sc); 1805 #endif /* ATW_BBPDEBUG */ 1806 1807 out: 1808 atw_bbp_io_enable(sc, 0); 1809 1810 /* set beacon, rts, atim transmit power */ 1811 reg = ATW_READ(sc, ATW_PLCPHD); 1812 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1813 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1814 ATW_PLCPHD_SERVICE_MASK); 1815 ATW_WRITE(sc, ATW_PLCPHD, reg); 1816 DELAY(atw_plcphd_delay); 1817 1818 return rc; 1819 } 1820 1821 /* Write a register on the RF3000 baseband processor using the 1822 * registers provided by the ADM8211 for this purpose. 1823 * 1824 * Return 0 on success. 1825 */ 1826 static int 1827 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1828 { 1829 u_int32_t reg; 1830 int i; 1831 1832 reg = sc->sc_bbpctl_wr | 1833 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1834 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1835 1836 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1837 ATW_WRITE(sc, ATW_BBPCTL, reg); 1838 DELAY(2 * atw_pseudo_milli); 1839 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1840 break; 1841 } 1842 1843 if (i < 0) { 1844 printf("%s: BBPCTL still busy\n", device_xname(&sc->sc_dev)); 1845 return ETIMEDOUT; 1846 } 1847 return 0; 1848 } 1849 1850 /* Read a register on the RF3000 baseband processor using the registers 1851 * the ADM8211 provides for this purpose. 1852 * 1853 * The 7-bit register address is addr. Record the 8-bit data in the register 1854 * in *val. 1855 * 1856 * Return 0 on success. 1857 * 1858 * XXX This does not seem to work. The ADM8211 must require more or 1859 * different magic to read the chip than to write it. Possibly some 1860 * of the magic I have derived from a binary-only driver concerns 1861 * the "chip address" (see the RF3000 manual). 1862 */ 1863 #ifdef ATW_BBPDEBUG 1864 static int 1865 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1866 { 1867 u_int32_t reg; 1868 int i; 1869 1870 for (i = 1000; --i >= 0; ) { 1871 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1872 break; 1873 DELAY(100); 1874 } 1875 1876 if (i < 0) { 1877 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1878 device_xname(&sc->sc_dev)); 1879 return ETIMEDOUT; 1880 } 1881 1882 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1883 1884 ATW_WRITE(sc, ATW_BBPCTL, reg); 1885 1886 for (i = 1000; --i >= 0; ) { 1887 DELAY(100); 1888 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1889 break; 1890 } 1891 1892 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1893 1894 if (i < 0) { 1895 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1896 device_xname(&sc->sc_dev), reg); 1897 return ETIMEDOUT; 1898 } 1899 if (val != NULL) 1900 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1901 return 0; 1902 } 1903 #endif /* ATW_BBPDEBUG */ 1904 1905 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1906 * provided by the ADM8211 for that purpose. 1907 * 1908 * val is 18 bits of data, and val is the 4-bit address of the register. 1909 * 1910 * Return 0 on success. 1911 */ 1912 static void 1913 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1914 { 1915 uint32_t bits, mask, reg; 1916 const int nbits = 22; 1917 1918 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1919 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1920 1921 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1922 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1923 1924 reg = ATW_SYNRF_SELSYN; 1925 /* reference driver: reset Si4126 serial bus to initial 1926 * conditions? 1927 */ 1928 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1929 ATW_WRITE(sc, ATW_SYNRF, reg); 1930 1931 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1932 if ((bits & mask) != 0) 1933 reg |= ATW_SYNRF_SYNDATA; 1934 else 1935 reg &= ~ATW_SYNRF_SYNDATA; 1936 ATW_WRITE(sc, ATW_SYNRF, reg); 1937 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1938 ATW_WRITE(sc, ATW_SYNRF, reg); 1939 } 1940 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1941 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1942 } 1943 1944 /* Read 18-bit data from the 4-bit address addr in Si4126 1945 * RF synthesizer and write the data to *val. Return 0 on success. 1946 * 1947 * XXX This does not seem to work. The ADM8211 must require more or 1948 * different magic to read the chip than to write it. 1949 */ 1950 #ifdef ATW_SYNDEBUG 1951 static int 1952 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1953 { 1954 u_int32_t reg; 1955 int i; 1956 1957 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1958 1959 for (i = 1000; --i >= 0; ) { 1960 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1961 break; 1962 DELAY(100); 1963 } 1964 1965 if (i < 0) { 1966 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1967 device_xname(&sc->sc_dev)); 1968 return ETIMEDOUT; 1969 } 1970 1971 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1972 1973 ATW_WRITE(sc, ATW_SYNCTL, reg); 1974 1975 for (i = 1000; --i >= 0; ) { 1976 DELAY(100); 1977 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1978 break; 1979 } 1980 1981 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1982 1983 if (i < 0) { 1984 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1985 device_xname(&sc->sc_dev), reg); 1986 return ETIMEDOUT; 1987 } 1988 if (val != NULL) 1989 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1990 ATW_SYNCTL_DATA_MASK); 1991 return 0; 1992 } 1993 #endif /* ATW_SYNDEBUG */ 1994 1995 /* XXX is the endianness correct? test. */ 1996 #define atw_calchash(addr) \ 1997 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1998 1999 /* 2000 * atw_filter_setup: 2001 * 2002 * Set the ADM8211's receive filter. 2003 */ 2004 static void 2005 atw_filter_setup(struct atw_softc *sc) 2006 { 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 struct ethercom *ec = &sc->sc_ec; 2009 struct ifnet *ifp = &sc->sc_if; 2010 int hash; 2011 u_int32_t hashes[2]; 2012 struct ether_multi *enm; 2013 struct ether_multistep step; 2014 2015 /* According to comments in tlp_al981_filter_setup 2016 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2017 * multicast filter to be set while it is running. Hopefully 2018 * the ADM8211 is not the same! 2019 */ 2020 if ((ifp->if_flags & IFF_RUNNING) != 0) 2021 atw_idle(sc, ATW_NAR_SR); 2022 2023 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 2024 ifp->if_flags &= ~IFF_ALLMULTI; 2025 2026 /* XXX in scan mode, do not filter packets. Maybe this is 2027 * unnecessary. 2028 */ 2029 if (ic->ic_state == IEEE80211_S_SCAN || 2030 (ifp->if_flags & IFF_PROMISC) != 0) { 2031 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2032 goto allmulti; 2033 } 2034 2035 hashes[0] = hashes[1] = 0x0; 2036 2037 /* 2038 * Program the 64-bit multicast hash filter. 2039 */ 2040 ETHER_FIRST_MULTI(step, ec, enm); 2041 while (enm != NULL) { 2042 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2043 ETHER_ADDR_LEN) != 0) 2044 goto allmulti; 2045 2046 hash = atw_calchash(enm->enm_addrlo); 2047 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2048 ETHER_NEXT_MULTI(step, enm); 2049 sc->sc_opmode |= ATW_NAR_MM; 2050 } 2051 ifp->if_flags &= ~IFF_ALLMULTI; 2052 goto setit; 2053 2054 allmulti: 2055 sc->sc_opmode |= ATW_NAR_MM; 2056 ifp->if_flags |= IFF_ALLMULTI; 2057 hashes[0] = hashes[1] = 0xffffffff; 2058 2059 setit: 2060 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2061 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2062 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2063 DELAY(atw_nar_delay); 2064 ATW_WRITE(sc, ATW_RDR, 0x1); 2065 2066 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(&sc->sc_dev), 2067 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2068 } 2069 2070 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2071 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2072 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2073 * no beacon with the preferred BSSID and SSID in the number of 2074 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2075 */ 2076 static void 2077 atw_write_bssid(struct atw_softc *sc) 2078 { 2079 struct ieee80211com *ic = &sc->sc_ic; 2080 u_int8_t *bssid; 2081 2082 bssid = ic->ic_bss->ni_bssid; 2083 2084 ATW_WRITE(sc, ATW_BSSID0, 2085 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2086 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2087 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2088 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2089 2090 ATW_WRITE(sc, ATW_ABDA1, 2091 (ATW_READ(sc, ATW_ABDA1) & 2092 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2093 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2094 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2095 2096 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(&sc->sc_dev), 2097 ether_sprintf(sc->sc_bssid))); 2098 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2099 2100 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2101 } 2102 2103 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2104 * 16-bit word. 2105 */ 2106 static void 2107 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2108 { 2109 u_int i; 2110 u_int8_t *ptr; 2111 2112 memcpy(&sc->sc_sram[ofs], buf, buflen); 2113 2114 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2115 2116 KASSERT(buflen + ofs <= sc->sc_sramlen); 2117 2118 ptr = &sc->sc_sram[ofs]; 2119 2120 for (i = 0; i < buflen; i += 2) { 2121 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2122 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2123 DELAY(atw_writewep_delay); 2124 2125 ATW_WRITE(sc, ATW_WESK, 2126 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2127 DELAY(atw_writewep_delay); 2128 } 2129 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2130 2131 if (sc->sc_if.if_flags & IFF_DEBUG) { 2132 int n_octets = 0; 2133 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2134 device_xname(&sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2135 for (i = 0; i < buflen; i++) { 2136 printf(" %02x", ptr[i]); 2137 if (++n_octets % 24 == 0) 2138 printf("\n"); 2139 } 2140 if (n_octets % 24 != 0) 2141 printf("\n"); 2142 } 2143 } 2144 2145 static int 2146 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2147 { 2148 struct atw_softc *sc = ic->ic_ifp->if_softc; 2149 u_int keyix = k->wk_keyix; 2150 2151 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2152 2153 if (keyix >= IEEE80211_WEP_NKID) 2154 return 0; 2155 if (k->wk_keylen != 0) 2156 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2157 2158 return 1; 2159 } 2160 2161 static int 2162 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2163 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2164 { 2165 struct atw_softc *sc = ic->ic_ifp->if_softc; 2166 2167 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2168 2169 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2170 return 0; 2171 2172 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2173 2174 return 1; 2175 } 2176 2177 static void 2178 atw_key_update_begin(struct ieee80211com *ic) 2179 { 2180 #ifdef ATW_DEBUG 2181 struct ifnet *ifp = ic->ic_ifp; 2182 struct atw_softc *sc = ifp->if_softc; 2183 #endif 2184 2185 DPRINTF(sc, ("%s:\n", __func__)); 2186 } 2187 2188 static void 2189 atw_key_update_end(struct ieee80211com *ic) 2190 { 2191 struct ifnet *ifp = ic->ic_ifp; 2192 struct atw_softc *sc = ifp->if_softc; 2193 2194 DPRINTF(sc, ("%s:\n", __func__)); 2195 2196 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2197 return; 2198 if (ATW_IS_ENABLED(sc) == 0) 2199 return; 2200 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2201 atw_write_wep(sc); 2202 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2203 DELAY(atw_nar_delay); 2204 ATW_WRITE(sc, ATW_RDR, 0x1); 2205 } 2206 2207 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2208 static void 2209 atw_write_wep(struct atw_softc *sc) 2210 { 2211 #if 0 2212 struct ieee80211com *ic = &sc->sc_ic; 2213 u_int32_t reg; 2214 int i; 2215 #endif 2216 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2217 u_int8_t buf[IEEE80211_WEP_NKID] 2218 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2219 2220 sc->sc_wepctl = 0; 2221 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2222 2223 memset(&buf[0][0], 0, sizeof(buf)); 2224 2225 #if 0 2226 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2227 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2228 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2229 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2230 buf[i][1] = ATW_WEP_ENABLED; 2231 } else { 2232 buf[i][1] = 0; 2233 continue; 2234 } 2235 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2236 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2237 ic->ic_nw_keys[i].wk_keylen - 1); 2238 } 2239 2240 reg = ATW_READ(sc, ATW_MACTEST); 2241 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2242 reg &= ~ATW_MACTEST_KEYID_MASK; 2243 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2244 ATW_WRITE(sc, ATW_MACTEST, reg); 2245 2246 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2247 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2248 2249 switch (sc->sc_rev) { 2250 case ATW_REVISION_AB: 2251 case ATW_REVISION_AF: 2252 /* Bypass WEP on Rx. */ 2253 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2254 break; 2255 default: 2256 break; 2257 } 2258 #endif 2259 2260 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2261 sizeof(buf)); 2262 2263 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2264 } 2265 2266 static void 2267 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2268 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2269 { 2270 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2271 2272 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2273 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2274 return; 2275 2276 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2277 2278 switch (subtype) { 2279 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2280 case IEEE80211_FC0_SUBTYPE_BEACON: 2281 if (ic->ic_opmode == IEEE80211_M_IBSS && 2282 ic->ic_state == IEEE80211_S_RUN) { 2283 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2284 (void)ieee80211_ibss_merge(ni); 2285 } 2286 break; 2287 default: 2288 break; 2289 } 2290 return; 2291 } 2292 2293 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2294 * In ad hoc mode, the SSID is written to the beacons sent by the 2295 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2296 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2297 * indications. 2298 */ 2299 static void 2300 atw_write_ssid(struct atw_softc *sc) 2301 { 2302 struct ieee80211com *ic = &sc->sc_ic; 2303 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2304 * it only expects the element length, not its ID. 2305 */ 2306 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2307 2308 memset(buf, 0, sizeof(buf)); 2309 buf[0] = ic->ic_bss->ni_esslen; 2310 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2311 2312 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2313 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2314 } 2315 2316 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2317 * In ad hoc mode, the supported rates are written to beacons sent by the 2318 * ADM8211. 2319 */ 2320 static void 2321 atw_write_sup_rates(struct atw_softc *sc) 2322 { 2323 struct ieee80211com *ic = &sc->sc_ic; 2324 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2325 * supported rates 2326 */ 2327 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2328 2329 memset(buf, 0, sizeof(buf)); 2330 2331 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2332 2333 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2334 ic->ic_bss->ni_rates.rs_nrates); 2335 2336 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2337 } 2338 2339 /* Start/stop sending beacons. */ 2340 void 2341 atw_start_beacon(struct atw_softc *sc, int start) 2342 { 2343 struct ieee80211com *ic = &sc->sc_ic; 2344 uint16_t chan; 2345 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2346 size_t len; 2347 2348 if (ATW_IS_ENABLED(sc) == 0) 2349 return; 2350 2351 /* start beacons */ 2352 len = sizeof(struct ieee80211_frame) + 2353 8 /* timestamp */ + 2 /* beacon interval */ + 2354 2 /* capability info */ + 2355 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2356 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2357 3 /* DS parameters */ + 2358 IEEE80211_CRC_LEN; 2359 2360 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2361 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2362 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2363 2364 ATW_WRITE(sc, ATW_BCNT, bcnt); 2365 ATW_WRITE(sc, ATW_CAP1, cap1); 2366 2367 if (!start) 2368 return; 2369 2370 /* TBD use ni_capinfo */ 2371 2372 capinfo = 0; 2373 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2374 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2375 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2376 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2377 2378 switch (ic->ic_opmode) { 2379 case IEEE80211_M_IBSS: 2380 len += 4; /* IBSS parameters */ 2381 capinfo |= IEEE80211_CAPINFO_IBSS; 2382 break; 2383 case IEEE80211_M_HOSTAP: 2384 /* XXX 6-byte minimum TIM */ 2385 len += atw_beacon_len_adjust; 2386 capinfo |= IEEE80211_CAPINFO_ESS; 2387 break; 2388 default: 2389 return; 2390 } 2391 2392 /* set listen interval 2393 * XXX do software units agree w/ hardware? 2394 */ 2395 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2396 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2397 2398 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2399 2400 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2401 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2402 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2403 2404 ATW_WRITE(sc, ATW_BCNT, bcnt); 2405 ATW_WRITE(sc, ATW_BPLI, bpli); 2406 ATW_WRITE(sc, ATW_CAP0, cap0); 2407 ATW_WRITE(sc, ATW_CAP1, cap1); 2408 2409 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2410 device_xname(&sc->sc_dev), bcnt)); 2411 2412 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2413 device_xname(&sc->sc_dev), cap1)); 2414 } 2415 2416 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2417 static inline uint32_t 2418 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2419 { 2420 /* Following the reference driver's lead, I compute 2421 * 2422 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2423 * 2424 * without using 64-bit arithmetic, using the following 2425 * relationship: 2426 * 2427 * (0x100000000 * H + L) % m 2428 * = ((0x100000000 % m) * H + L) % m 2429 * = (((0xffffffff + 1) % m) * H + L) % m 2430 * = ((0xffffffff % m + 1 % m) * H + L) % m 2431 * = ((0xffffffff % m + 1) * H + L) % m 2432 */ 2433 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2434 } 2435 2436 static uint64_t 2437 atw_get_tsft(struct atw_softc *sc) 2438 { 2439 int i; 2440 uint32_t tsfth, tsftl; 2441 for (i = 0; i < 2; i++) { 2442 tsfth = ATW_READ(sc, ATW_TSFTH); 2443 tsftl = ATW_READ(sc, ATW_TSFTL); 2444 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2445 break; 2446 } 2447 return ((uint64_t)tsfth << 32) | tsftl; 2448 } 2449 2450 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2451 * the ieee80211com. 2452 * 2453 * Predict the next target beacon transmission time (TBTT) and 2454 * write it to the ADM8211. 2455 */ 2456 static void 2457 atw_predict_beacon(struct atw_softc *sc) 2458 { 2459 #define TBTTOFS 20 /* TU */ 2460 2461 struct ieee80211com *ic = &sc->sc_ic; 2462 uint64_t tsft; 2463 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2464 union { 2465 uint64_t word; 2466 uint8_t tstamp[8]; 2467 } u; 2468 2469 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2470 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2471 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2472 tsft = atw_get_tsft(sc); 2473 u.word = htole64(tsft); 2474 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2475 sizeof(ic->ic_bss->ni_tstamp)); 2476 } else 2477 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2478 2479 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2480 2481 tsftl = tsft & 0xFFFFFFFF; 2482 tsfth = tsft >> 32; 2483 2484 /* We sent/received the last beacon `past' microseconds 2485 * after the interval divided the TSF timer. 2486 */ 2487 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2488 2489 /* Skip ten beacons so that the TBTT cannot pass before 2490 * we've programmed it. Ten is an arbitrary number. 2491 */ 2492 tbtt = past_even + ival * 10; 2493 2494 ATW_WRITE(sc, ATW_TOFS1, 2495 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2496 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2497 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2498 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2499 #undef TBTTOFS 2500 } 2501 2502 static void 2503 atw_next_scan(void *arg) 2504 { 2505 struct atw_softc *sc = arg; 2506 struct ieee80211com *ic = &sc->sc_ic; 2507 int s; 2508 2509 /* don't call atw_start w/o network interrupts blocked */ 2510 s = splnet(); 2511 if (ic->ic_state == IEEE80211_S_SCAN) 2512 ieee80211_next_scan(ic); 2513 splx(s); 2514 } 2515 2516 /* Synchronize the hardware state with the software state. */ 2517 static int 2518 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2519 { 2520 struct ifnet *ifp = ic->ic_ifp; 2521 struct atw_softc *sc = ifp->if_softc; 2522 enum ieee80211_state ostate; 2523 int error = 0; 2524 2525 ostate = ic->ic_state; 2526 callout_stop(&sc->sc_scan_ch); 2527 2528 switch (nstate) { 2529 case IEEE80211_S_AUTH: 2530 case IEEE80211_S_ASSOC: 2531 atw_write_bssid(sc); 2532 error = atw_tune(sc); 2533 break; 2534 case IEEE80211_S_INIT: 2535 callout_stop(&sc->sc_scan_ch); 2536 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2537 atw_start_beacon(sc, 0); 2538 break; 2539 case IEEE80211_S_SCAN: 2540 error = atw_tune(sc); 2541 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2542 atw_next_scan, sc); 2543 break; 2544 case IEEE80211_S_RUN: 2545 error = atw_tune(sc); 2546 atw_write_bssid(sc); 2547 atw_write_ssid(sc); 2548 atw_write_sup_rates(sc); 2549 2550 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2551 ic->ic_opmode == IEEE80211_M_MONITOR) 2552 break; 2553 2554 /* set listen interval 2555 * XXX do software units agree w/ hardware? 2556 */ 2557 ATW_WRITE(sc, ATW_BPLI, 2558 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2559 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2560 ATW_BPLI_LI_MASK)); 2561 2562 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(&sc->sc_dev), 2563 ATW_READ(sc, ATW_BPLI))); 2564 2565 atw_predict_beacon(sc); 2566 2567 switch (ic->ic_opmode) { 2568 case IEEE80211_M_AHDEMO: 2569 case IEEE80211_M_HOSTAP: 2570 case IEEE80211_M_IBSS: 2571 atw_start_beacon(sc, 1); 2572 break; 2573 case IEEE80211_M_MONITOR: 2574 case IEEE80211_M_STA: 2575 break; 2576 } 2577 2578 break; 2579 } 2580 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2581 } 2582 2583 /* 2584 * atw_add_rxbuf: 2585 * 2586 * Add a receive buffer to the indicated descriptor. 2587 */ 2588 int 2589 atw_add_rxbuf(struct atw_softc *sc, int idx) 2590 { 2591 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2592 struct mbuf *m; 2593 int error; 2594 2595 MGETHDR(m, M_DONTWAIT, MT_DATA); 2596 if (m == NULL) 2597 return (ENOBUFS); 2598 2599 MCLGET(m, M_DONTWAIT); 2600 if ((m->m_flags & M_EXT) == 0) { 2601 m_freem(m); 2602 return (ENOBUFS); 2603 } 2604 2605 if (rxs->rxs_mbuf != NULL) 2606 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2607 2608 rxs->rxs_mbuf = m; 2609 2610 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2611 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2612 BUS_DMA_READ|BUS_DMA_NOWAIT); 2613 if (error) { 2614 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2615 idx, error); 2616 panic("atw_add_rxbuf"); /* XXX */ 2617 } 2618 2619 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2620 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2621 2622 atw_init_rxdesc(sc, idx); 2623 2624 return (0); 2625 } 2626 2627 /* 2628 * Release any queued transmit buffers. 2629 */ 2630 void 2631 atw_txdrain(struct atw_softc *sc) 2632 { 2633 struct atw_txsoft *txs; 2634 2635 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2636 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2637 if (txs->txs_mbuf != NULL) { 2638 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2639 m_freem(txs->txs_mbuf); 2640 txs->txs_mbuf = NULL; 2641 } 2642 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2643 sc->sc_txfree += txs->txs_ndescs; 2644 } 2645 2646 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2647 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2648 sc->sc_txfree != ATW_NTXDESC)); 2649 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2650 sc->sc_tx_timer = 0; 2651 } 2652 2653 /* 2654 * atw_stop: [ ifnet interface function ] 2655 * 2656 * Stop transmission on the interface. 2657 */ 2658 void 2659 atw_stop(struct ifnet *ifp, int disable) 2660 { 2661 struct atw_softc *sc = ifp->if_softc; 2662 struct ieee80211com *ic = &sc->sc_ic; 2663 2664 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2665 2666 /* Disable interrupts. */ 2667 ATW_WRITE(sc, ATW_IER, 0); 2668 2669 /* Stop the transmit and receive processes. */ 2670 sc->sc_opmode = 0; 2671 ATW_WRITE(sc, ATW_NAR, 0); 2672 DELAY(atw_nar_delay); 2673 ATW_WRITE(sc, ATW_TDBD, 0); 2674 ATW_WRITE(sc, ATW_TDBP, 0); 2675 ATW_WRITE(sc, ATW_RDB, 0); 2676 2677 atw_txdrain(sc); 2678 2679 /* 2680 * Mark the interface down and cancel the watchdog timer. 2681 */ 2682 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2683 sc->sc_tx_timer = 0; 2684 ifp->if_timer = 0; 2685 2686 if (disable) { 2687 atw_rxdrain(sc); 2688 atw_disable(sc); 2689 } else 2690 atw_reset(sc); 2691 } 2692 2693 /* 2694 * atw_rxdrain: 2695 * 2696 * Drain the receive queue. 2697 */ 2698 void 2699 atw_rxdrain(struct atw_softc *sc) 2700 { 2701 struct atw_rxsoft *rxs; 2702 int i; 2703 2704 for (i = 0; i < ATW_NRXDESC; i++) { 2705 rxs = &sc->sc_rxsoft[i]; 2706 if (rxs->rxs_mbuf == NULL) 2707 continue; 2708 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2709 m_freem(rxs->rxs_mbuf); 2710 rxs->rxs_mbuf = NULL; 2711 } 2712 } 2713 2714 /* 2715 * atw_detach: 2716 * 2717 * Detach an ADM8211 interface. 2718 */ 2719 int 2720 atw_detach(struct atw_softc *sc) 2721 { 2722 struct ifnet *ifp = &sc->sc_if; 2723 struct atw_rxsoft *rxs; 2724 struct atw_txsoft *txs; 2725 int i; 2726 2727 /* 2728 * Succeed now if there isn't any work to do. 2729 */ 2730 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2731 return (0); 2732 2733 pmf_device_deregister(&sc->sc_dev); 2734 2735 callout_stop(&sc->sc_scan_ch); 2736 2737 ieee80211_ifdetach(&sc->sc_ic); 2738 if_detach(ifp); 2739 2740 for (i = 0; i < ATW_NRXDESC; i++) { 2741 rxs = &sc->sc_rxsoft[i]; 2742 if (rxs->rxs_mbuf != NULL) { 2743 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2744 m_freem(rxs->rxs_mbuf); 2745 rxs->rxs_mbuf = NULL; 2746 } 2747 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2748 } 2749 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2750 txs = &sc->sc_txsoft[i]; 2751 if (txs->txs_mbuf != NULL) { 2752 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2753 m_freem(txs->txs_mbuf); 2754 txs->txs_mbuf = NULL; 2755 } 2756 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2757 } 2758 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2759 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2760 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2761 sizeof(struct atw_control_data)); 2762 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2763 2764 if (sc->sc_srom) 2765 free(sc->sc_srom, M_DEVBUF); 2766 2767 atw_evcnt_detach(sc); 2768 2769 return (0); 2770 } 2771 2772 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2773 bool 2774 atw_shutdown(device_t self, int flags) 2775 { 2776 struct atw_softc *sc = device_private(self); 2777 2778 atw_stop(&sc->sc_if, 1); 2779 return true; 2780 } 2781 2782 int 2783 atw_intr(void *arg) 2784 { 2785 struct atw_softc *sc = arg; 2786 struct ifnet *ifp = &sc->sc_if; 2787 u_int32_t status, rxstatus, txstatus, linkstatus; 2788 int handled = 0, txthresh; 2789 2790 #ifdef DEBUG 2791 if (ATW_IS_ENABLED(sc) == 0) 2792 panic("%s: atw_intr: not enabled", device_xname(&sc->sc_dev)); 2793 #endif 2794 2795 /* 2796 * If the interface isn't running, the interrupt couldn't 2797 * possibly have come from us. 2798 */ 2799 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2800 !device_is_active(&sc->sc_dev)) 2801 return (0); 2802 2803 for (;;) { 2804 status = ATW_READ(sc, ATW_STSR); 2805 2806 if (status) 2807 ATW_WRITE(sc, ATW_STSR, status); 2808 2809 #ifdef ATW_DEBUG 2810 #define PRINTINTR(flag) do { \ 2811 if ((status & flag) != 0) { \ 2812 printf("%s" #flag, delim); \ 2813 delim = ","; \ 2814 } \ 2815 } while (0) 2816 2817 if (atw_debug > 1 && status) { 2818 const char *delim = "<"; 2819 2820 printf("%s: reg[STSR] = %x", 2821 device_xname(&sc->sc_dev), status); 2822 2823 PRINTINTR(ATW_INTR_FBE); 2824 PRINTINTR(ATW_INTR_LINKOFF); 2825 PRINTINTR(ATW_INTR_LINKON); 2826 PRINTINTR(ATW_INTR_RCI); 2827 PRINTINTR(ATW_INTR_RDU); 2828 PRINTINTR(ATW_INTR_REIS); 2829 PRINTINTR(ATW_INTR_RPS); 2830 PRINTINTR(ATW_INTR_TCI); 2831 PRINTINTR(ATW_INTR_TDU); 2832 PRINTINTR(ATW_INTR_TLT); 2833 PRINTINTR(ATW_INTR_TPS); 2834 PRINTINTR(ATW_INTR_TRT); 2835 PRINTINTR(ATW_INTR_TUF); 2836 PRINTINTR(ATW_INTR_BCNTC); 2837 PRINTINTR(ATW_INTR_ATIME); 2838 PRINTINTR(ATW_INTR_TBTT); 2839 PRINTINTR(ATW_INTR_TSCZ); 2840 PRINTINTR(ATW_INTR_TSFTF); 2841 printf(">\n"); 2842 } 2843 #undef PRINTINTR 2844 #endif /* ATW_DEBUG */ 2845 2846 if ((status & sc->sc_inten) == 0) 2847 break; 2848 2849 handled = 1; 2850 2851 rxstatus = status & sc->sc_rxint_mask; 2852 txstatus = status & sc->sc_txint_mask; 2853 linkstatus = status & sc->sc_linkint_mask; 2854 2855 if (linkstatus) { 2856 atw_linkintr(sc, linkstatus); 2857 } 2858 2859 if (rxstatus) { 2860 /* Grab any new packets. */ 2861 atw_rxintr(sc); 2862 2863 if (rxstatus & ATW_INTR_RDU) { 2864 printf("%s: receive ring overrun\n", 2865 device_xname(&sc->sc_dev)); 2866 /* Get the receive process going again. */ 2867 ATW_WRITE(sc, ATW_RDR, 0x1); 2868 break; 2869 } 2870 } 2871 2872 if (txstatus) { 2873 /* Sweep up transmit descriptors. */ 2874 atw_txintr(sc); 2875 2876 if (txstatus & ATW_INTR_TLT) { 2877 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2878 device-xname(&sc->sc_dev))); 2879 } 2880 2881 if (txstatus & ATW_INTR_TRT) { 2882 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2883 device_xname(&sc->sc_dev))); 2884 } 2885 2886 /* If Tx under-run, increase our transmit threshold 2887 * if another is available. 2888 */ 2889 txthresh = sc->sc_txthresh + 1; 2890 if ((txstatus & ATW_INTR_TUF) && 2891 sc->sc_txth[txthresh].txth_name != NULL) { 2892 /* Idle the transmit process. */ 2893 atw_idle(sc, ATW_NAR_ST); 2894 2895 sc->sc_txthresh = txthresh; 2896 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2897 sc->sc_opmode |= 2898 sc->sc_txth[txthresh].txth_opmode; 2899 printf("%s: transmit underrun; new " 2900 "threshold: %s\n", device_xname(&sc->sc_dev), 2901 sc->sc_txth[txthresh].txth_name); 2902 2903 /* Set the new threshold and restart 2904 * the transmit process. 2905 */ 2906 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2907 DELAY(atw_nar_delay); 2908 ATW_WRITE(sc, ATW_RDR, 0x1); 2909 /* XXX Log every Nth underrun from 2910 * XXX now on? 2911 */ 2912 } 2913 } 2914 2915 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2916 if (status & ATW_INTR_TPS) 2917 printf("%s: transmit process stopped\n", 2918 device_xname(&sc->sc_dev)); 2919 if (status & ATW_INTR_RPS) 2920 printf("%s: receive process stopped\n", 2921 device_xname(&sc->sc_dev)); 2922 (void)atw_init(ifp); 2923 break; 2924 } 2925 2926 if (status & ATW_INTR_FBE) { 2927 aprint_error_dev(&sc->sc_dev, "fatal bus error\n"); 2928 (void)atw_init(ifp); 2929 break; 2930 } 2931 2932 /* 2933 * Not handled: 2934 * 2935 * Transmit buffer unavailable -- normal 2936 * condition, nothing to do, really. 2937 * 2938 * Early receive interrupt -- not available on 2939 * all chips, we just use RI. We also only 2940 * use single-segment receive DMA, so this 2941 * is mostly useless. 2942 * 2943 * TBD others 2944 */ 2945 } 2946 2947 /* Try to get more packets going. */ 2948 atw_start(ifp); 2949 2950 return (handled); 2951 } 2952 2953 /* 2954 * atw_idle: 2955 * 2956 * Cause the transmit and/or receive processes to go idle. 2957 * 2958 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2959 * process in STSR if I clear SR or ST after the process has already 2960 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2961 * do not seem to be too reliable. Perhaps I have the sense of the 2962 * Rx bits switched with the Tx bits? 2963 */ 2964 void 2965 atw_idle(struct atw_softc *sc, u_int32_t bits) 2966 { 2967 u_int32_t ackmask = 0, opmode, stsr, test0; 2968 int i, s; 2969 2970 s = splnet(); 2971 2972 opmode = sc->sc_opmode & ~bits; 2973 2974 if (bits & ATW_NAR_SR) 2975 ackmask |= ATW_INTR_RPS; 2976 2977 if (bits & ATW_NAR_ST) { 2978 ackmask |= ATW_INTR_TPS; 2979 /* set ATW_NAR_HF to flush TX FIFO. */ 2980 opmode |= ATW_NAR_HF; 2981 } 2982 2983 ATW_WRITE(sc, ATW_NAR, opmode); 2984 DELAY(atw_nar_delay); 2985 2986 for (i = 0; i < 1000; i++) { 2987 stsr = ATW_READ(sc, ATW_STSR); 2988 if ((stsr & ackmask) == ackmask) 2989 break; 2990 DELAY(10); 2991 } 2992 2993 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2994 2995 if ((stsr & ackmask) == ackmask) 2996 goto out; 2997 2998 test0 = ATW_READ(sc, ATW_TEST0); 2999 3000 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3001 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3002 printf("%s: transmit process not idle [%s]\n", 3003 device_xname(&sc->sc_dev), 3004 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3005 printf("%s: bits %08x test0 %08x stsr %08x\n", 3006 device_xname(&sc->sc_dev), bits, test0, stsr); 3007 } 3008 3009 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3010 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3011 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3012 device_xname(&sc->sc_dev), 3013 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3014 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3015 device_xname(&sc->sc_dev), bits, test0, stsr)); 3016 } 3017 out: 3018 if ((bits & ATW_NAR_ST) != 0) 3019 atw_txdrain(sc); 3020 splx(s); 3021 return; 3022 } 3023 3024 /* 3025 * atw_linkintr: 3026 * 3027 * Helper; handle link-status interrupts. 3028 */ 3029 void 3030 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3031 { 3032 struct ieee80211com *ic = &sc->sc_ic; 3033 3034 if (ic->ic_state != IEEE80211_S_RUN) 3035 return; 3036 3037 if (linkstatus & ATW_INTR_LINKON) { 3038 DPRINTF(sc, ("%s: link on\n", device_xname(&sc->sc_dev))); 3039 sc->sc_rescan_timer = 0; 3040 } else if (linkstatus & ATW_INTR_LINKOFF) { 3041 DPRINTF(sc, ("%s: link off\n", device_xname(&sc->sc_dev))); 3042 if (ic->ic_opmode != IEEE80211_M_STA) 3043 return; 3044 sc->sc_rescan_timer = 3; 3045 sc->sc_if.if_timer = 1; 3046 } 3047 } 3048 3049 static inline int 3050 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3051 { 3052 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3053 return 0; 3054 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3055 return 0; 3056 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3057 } 3058 3059 /* 3060 * atw_rxintr: 3061 * 3062 * Helper; handle receive interrupts. 3063 */ 3064 void 3065 atw_rxintr(struct atw_softc *sc) 3066 { 3067 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3068 struct ieee80211com *ic = &sc->sc_ic; 3069 struct ieee80211_node *ni; 3070 struct ieee80211_frame_min *wh; 3071 struct ifnet *ifp = &sc->sc_if; 3072 struct atw_rxsoft *rxs; 3073 struct mbuf *m; 3074 u_int32_t rxstat; 3075 int i, len, rate, rate0; 3076 u_int32_t rssi, ctlrssi; 3077 3078 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3079 rxs = &sc->sc_rxsoft[i]; 3080 3081 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3082 3083 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3084 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3085 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3086 3087 if (rxstat & ATW_RXSTAT_OWN) 3088 break; /* We have processed all receive buffers. */ 3089 3090 DPRINTF3(sc, 3091 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3092 device_xname(&sc->sc_dev), 3093 rxstat, ctlrssi, 3094 le32toh(sc->sc_rxdescs[i].ar_buf1), 3095 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3096 3097 /* 3098 * Make sure the packet fits in one buffer. This should 3099 * always be the case. 3100 */ 3101 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3102 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3103 printf("%s: incoming packet spilled, resetting\n", 3104 device_xname(&sc->sc_dev)); 3105 (void)atw_init(ifp); 3106 return; 3107 } 3108 3109 /* 3110 * If an error occurred, update stats, clear the status 3111 * word, and leave the packet buffer in place. It will 3112 * simply be reused the next time the ring comes around. 3113 */ 3114 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3115 #define PRINTERR(bit, str) \ 3116 if (rxstat & (bit)) \ 3117 aprint_error_dev(&sc->sc_dev, "receive error: %s\n", \ 3118 str) 3119 ifp->if_ierrors++; 3120 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3121 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3122 #if 0 3123 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3124 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3125 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3126 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3127 #endif 3128 #undef PRINTERR 3129 atw_init_rxdesc(sc, i); 3130 continue; 3131 } 3132 3133 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3134 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3135 3136 /* 3137 * No errors; receive the packet. Note the ADM8211 3138 * includes the CRC in promiscuous mode. 3139 */ 3140 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3141 3142 /* 3143 * Allocate a new mbuf cluster. If that fails, we are 3144 * out of memory, and must drop the packet and recycle 3145 * the buffer that's already attached to this descriptor. 3146 */ 3147 m = rxs->rxs_mbuf; 3148 if (atw_add_rxbuf(sc, i) != 0) { 3149 ifp->if_ierrors++; 3150 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3151 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3152 atw_init_rxdesc(sc, i); 3153 continue; 3154 } 3155 3156 ifp->if_ipackets++; 3157 m->m_pkthdr.rcvif = ifp; 3158 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3159 3160 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3161 3162 /* The RSSI comes straight from a register in the 3163 * baseband processor. I know that for the RF3000, 3164 * the RSSI register also contains the antenna-selection 3165 * bits. Mask those off. 3166 * 3167 * TBD Treat other basebands. 3168 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3169 */ 3170 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3171 rssi = ctlrssi & RF3000_RSSI_MASK; 3172 else 3173 rssi = ctlrssi; 3174 3175 #if NBPFILTER > 0 3176 /* Pass this up to any BPF listeners. */ 3177 if (sc->sc_radiobpf != NULL) { 3178 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3179 3180 tap->ar_rate = rate; 3181 3182 /* TBD verify units are dB */ 3183 tap->ar_antsignal = (int)rssi; 3184 if (sc->sc_opmode & ATW_NAR_PR) 3185 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3186 else 3187 tap->ar_flags = 0; 3188 3189 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3190 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3191 3192 bpf_mtap2(sc->sc_radiobpf, tap, 3193 sizeof(sc->sc_rxtapu), m); 3194 } 3195 #endif /* NBPFILTER > 0 */ 3196 3197 sc->sc_recv_ev.ev_count++; 3198 3199 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3200 if (rxstat & ATW_RXSTAT_CRC16E) 3201 sc->sc_crc16e_ev.ev_count++; 3202 if (rxstat & ATW_RXSTAT_CRC32E) 3203 sc->sc_crc32e_ev.ev_count++; 3204 if (rxstat & ATW_RXSTAT_ICVE) 3205 sc->sc_icve_ev.ev_count++; 3206 if (rxstat & ATW_RXSTAT_SFDE) 3207 sc->sc_sfde_ev.ev_count++; 3208 if (rxstat & ATW_RXSTAT_SIGE) 3209 sc->sc_sige_ev.ev_count++; 3210 ifp->if_ierrors++; 3211 m_freem(m); 3212 continue; 3213 } 3214 3215 if (sc->sc_opmode & ATW_NAR_PR) 3216 m_adj(m, -IEEE80211_CRC_LEN); 3217 3218 wh = mtod(m, struct ieee80211_frame_min *); 3219 ni = ieee80211_find_rxnode(ic, wh); 3220 #if 0 3221 if (atw_hw_decrypted(sc, wh)) { 3222 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3223 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3224 } 3225 #endif 3226 ieee80211_input(ic, m, ni, (int)rssi, 0); 3227 ieee80211_free_node(ni); 3228 } 3229 3230 /* Update the receive pointer. */ 3231 sc->sc_rxptr = i; 3232 } 3233 3234 /* 3235 * atw_txintr: 3236 * 3237 * Helper; handle transmit interrupts. 3238 */ 3239 void 3240 atw_txintr(struct atw_softc *sc) 3241 { 3242 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3243 struct ifnet *ifp = &sc->sc_if; 3244 struct atw_txsoft *txs; 3245 u_int32_t txstat; 3246 3247 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3248 device_xname(&sc->sc_dev), sc->sc_flags)); 3249 3250 /* 3251 * Go through our Tx list and free mbufs for those 3252 * frames that have been transmitted. 3253 */ 3254 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3255 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3256 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3257 3258 #ifdef ATW_DEBUG 3259 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3260 int i; 3261 printf(" txsoft %p transmit chain:\n", txs); 3262 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3263 txs->txs_ndescs - 1, 3264 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3265 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3266 printf(" descriptor %d:\n", i); 3267 printf(" at_status: 0x%08x\n", 3268 le32toh(sc->sc_txdescs[i].at_stat)); 3269 printf(" at_flags: 0x%08x\n", 3270 le32toh(sc->sc_txdescs[i].at_flags)); 3271 printf(" at_buf1: 0x%08x\n", 3272 le32toh(sc->sc_txdescs[i].at_buf1)); 3273 printf(" at_buf2: 0x%08x\n", 3274 le32toh(sc->sc_txdescs[i].at_buf2)); 3275 if (i == txs->txs_lastdesc) 3276 break; 3277 } 3278 } 3279 #endif 3280 3281 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3282 if (txstat & ATW_TXSTAT_OWN) 3283 break; 3284 3285 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3286 3287 sc->sc_txfree += txs->txs_ndescs; 3288 3289 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3290 0, txs->txs_dmamap->dm_mapsize, 3291 BUS_DMASYNC_POSTWRITE); 3292 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3293 m_freem(txs->txs_mbuf); 3294 txs->txs_mbuf = NULL; 3295 3296 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3297 3298 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3299 sc->sc_txfree == 0)); 3300 ifp->if_flags &= ~IFF_OACTIVE; 3301 3302 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3303 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3304 bitmask_snprintf(txstat & ATW_TXSTAT_ERRMASK, 3305 ATW_TXSTAT_FMT, txstat_buf, sizeof(txstat_buf)); 3306 printf("%s: txstat %s %" __PRIuBITS "\n", 3307 device_xname(&sc->sc_dev), txstat_buf, 3308 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3309 } 3310 3311 /* 3312 * Check for errors and collisions. 3313 */ 3314 if (txstat & ATW_TXSTAT_TUF) 3315 sc->sc_stats.ts_tx_tuf++; 3316 if (txstat & ATW_TXSTAT_TLT) 3317 sc->sc_stats.ts_tx_tlt++; 3318 if (txstat & ATW_TXSTAT_TRT) 3319 sc->sc_stats.ts_tx_trt++; 3320 if (txstat & ATW_TXSTAT_TRO) 3321 sc->sc_stats.ts_tx_tro++; 3322 if (txstat & ATW_TXSTAT_SOFBR) { 3323 sc->sc_stats.ts_tx_sofbr++; 3324 } 3325 3326 if ((txstat & ATW_TXSTAT_ES) == 0) 3327 ifp->if_collisions += 3328 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3329 else 3330 ifp->if_oerrors++; 3331 3332 ifp->if_opackets++; 3333 } 3334 3335 /* 3336 * If there are no more pending transmissions, cancel the watchdog 3337 * timer. 3338 */ 3339 if (txs == NULL) { 3340 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3341 sc->sc_tx_timer = 0; 3342 } 3343 } 3344 3345 /* 3346 * atw_watchdog: [ifnet interface function] 3347 * 3348 * Watchdog timer handler. 3349 */ 3350 void 3351 atw_watchdog(struct ifnet *ifp) 3352 { 3353 struct atw_softc *sc = ifp->if_softc; 3354 struct ieee80211com *ic = &sc->sc_ic; 3355 3356 ifp->if_timer = 0; 3357 if (ATW_IS_ENABLED(sc) == 0) 3358 return; 3359 3360 if (sc->sc_rescan_timer) { 3361 if (--sc->sc_rescan_timer == 0) 3362 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3363 } 3364 if (sc->sc_tx_timer) { 3365 if (--sc->sc_tx_timer == 0 && 3366 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3367 printf("%s: transmit timeout\n", ifp->if_xname); 3368 ifp->if_oerrors++; 3369 (void)atw_init(ifp); 3370 atw_start(ifp); 3371 } 3372 } 3373 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3374 ifp->if_timer = 1; 3375 ieee80211_watchdog(ic); 3376 } 3377 3378 static void 3379 atw_evcnt_detach(struct atw_softc *sc) 3380 { 3381 evcnt_detach(&sc->sc_sige_ev); 3382 evcnt_detach(&sc->sc_sfde_ev); 3383 evcnt_detach(&sc->sc_icve_ev); 3384 evcnt_detach(&sc->sc_crc32e_ev); 3385 evcnt_detach(&sc->sc_crc16e_ev); 3386 evcnt_detach(&sc->sc_recv_ev); 3387 } 3388 3389 static void 3390 atw_evcnt_attach(struct atw_softc *sc) 3391 { 3392 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3393 NULL, sc->sc_if.if_xname, "recv"); 3394 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3395 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3396 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3397 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3398 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3399 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3400 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3401 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3402 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3403 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3404 } 3405 3406 #ifdef ATW_DEBUG 3407 static void 3408 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3409 { 3410 struct atw_softc *sc = ifp->if_softc; 3411 struct mbuf *m; 3412 int i, noctets = 0; 3413 3414 printf("%s: %d-byte packet\n", device_xname(&sc->sc_dev), 3415 m0->m_pkthdr.len); 3416 3417 for (m = m0; m; m = m->m_next) { 3418 if (m->m_len == 0) 3419 continue; 3420 for (i = 0; i < m->m_len; i++) { 3421 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3422 if (++noctets % 24 == 0) 3423 printf("\n"); 3424 } 3425 } 3426 printf("%s%s: %d bytes emitted\n", 3427 (noctets % 24 != 0) ? "\n" : "", device_xname(&sc->sc_dev), noctets); 3428 } 3429 #endif /* ATW_DEBUG */ 3430 3431 /* 3432 * atw_start: [ifnet interface function] 3433 * 3434 * Start packet transmission on the interface. 3435 */ 3436 void 3437 atw_start(struct ifnet *ifp) 3438 { 3439 struct atw_softc *sc = ifp->if_softc; 3440 struct ieee80211_key *k; 3441 struct ieee80211com *ic = &sc->sc_ic; 3442 struct ieee80211_node *ni; 3443 struct ieee80211_frame_min *whm; 3444 struct ieee80211_frame *wh; 3445 struct atw_frame *hh; 3446 struct mbuf *m0, *m; 3447 struct atw_txsoft *txs, *last_txs; 3448 struct atw_txdesc *txd; 3449 int npkt, rate; 3450 bus_dmamap_t dmamap; 3451 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3452 3453 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3454 device_xname(&sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3455 3456 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3457 return; 3458 3459 /* 3460 * Remember the previous number of free descriptors and 3461 * the first descriptor we'll use. 3462 */ 3463 ofree = sc->sc_txfree; 3464 firsttx = lasttx = sc->sc_txnext; 3465 3466 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3467 device_xname(&sc->sc_dev), ofree, firsttx)); 3468 3469 /* 3470 * Loop through the send queue, setting up transmit descriptors 3471 * until we drain the queue, or use up all available transmit 3472 * descriptors. 3473 */ 3474 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3475 sc->sc_txfree != 0) { 3476 3477 /* 3478 * Grab a packet off the management queue, if it 3479 * is not empty. Otherwise, from the data queue. 3480 */ 3481 IF_DEQUEUE(&ic->ic_mgtq, m0); 3482 if (m0 != NULL) { 3483 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3484 m0->m_pkthdr.rcvif = NULL; 3485 } else if (ic->ic_state != IEEE80211_S_RUN) 3486 break; /* send no data until associated */ 3487 else { 3488 IFQ_DEQUEUE(&ifp->if_snd, m0); 3489 if (m0 == NULL) 3490 break; 3491 #if NBPFILTER > 0 3492 if (ifp->if_bpf != NULL) 3493 bpf_mtap(ifp->if_bpf, m0); 3494 #endif /* NBPFILTER > 0 */ 3495 ni = ieee80211_find_txnode(ic, 3496 mtod(m0, struct ether_header *)->ether_dhost); 3497 if (ni == NULL) { 3498 ifp->if_oerrors++; 3499 break; 3500 } 3501 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3502 ieee80211_free_node(ni); 3503 ifp->if_oerrors++; 3504 break; 3505 } 3506 } 3507 3508 rate = MAX(ieee80211_get_rate(ni), 2); 3509 3510 whm = mtod(m0, struct ieee80211_frame_min *); 3511 3512 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3513 k = NULL; 3514 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3515 m_freem(m0); 3516 ieee80211_free_node(ni); 3517 ifp->if_oerrors++; 3518 break; 3519 } 3520 3521 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3522 ic->ic_flags, ic->ic_fragthreshold, rate, 3523 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3524 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3525 m_freem(m0); 3526 break; 3527 } 3528 3529 /* XXX Misleading if fragmentation is enabled. Better 3530 * to fragment in software? 3531 */ 3532 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3533 3534 #if NBPFILTER > 0 3535 /* 3536 * Pass the packet to any BPF listeners. 3537 */ 3538 if (ic->ic_rawbpf != NULL) 3539 bpf_mtap((void *)ic->ic_rawbpf, m0); 3540 3541 if (sc->sc_radiobpf != NULL) { 3542 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3543 3544 tap->at_rate = rate; 3545 3546 bpf_mtap2(sc->sc_radiobpf, tap, 3547 sizeof(sc->sc_txtapu), m0); 3548 } 3549 #endif /* NBPFILTER > 0 */ 3550 3551 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3552 3553 if (ni != NULL) 3554 ieee80211_free_node(ni); 3555 3556 if (m0 == NULL) { 3557 ifp->if_oerrors++; 3558 break; 3559 } 3560 3561 /* just to make sure. */ 3562 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3563 3564 if (m0 == NULL) { 3565 ifp->if_oerrors++; 3566 break; 3567 } 3568 3569 hh = mtod(m0, struct atw_frame *); 3570 wh = &hh->atw_ihdr; 3571 3572 /* Copy everything we need from the 802.11 header: 3573 * Frame Control; address 1, address 3, or addresses 3574 * 3 and 4. NIC fills in BSSID, SA. 3575 */ 3576 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3577 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3578 panic("%s: illegal WDS frame", 3579 device_xname(&sc->sc_dev)); 3580 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3581 } else 3582 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3583 3584 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3585 3586 /* initialize remaining Tx parameters */ 3587 memset(&hh->u, 0, sizeof(hh->u)); 3588 3589 hh->atw_rate = rate * 5; 3590 /* XXX this could be incorrect if M_FCS. _encap should 3591 * probably strip FCS just in case it sticks around in 3592 * bridged packets. 3593 */ 3594 hh->atw_service = 0x00; /* XXX guess */ 3595 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3596 sizeof(struct atw_frame)); 3597 3598 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3599 hh->atw_rtylmt = 3; 3600 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3601 #if 0 3602 if (do_encrypt) { 3603 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3604 hh->atw_keyid = ic->ic_def_txkey; 3605 } 3606 #endif 3607 3608 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3609 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3610 if (txs->txs_d0.d_residue) 3611 hh->atw_head_plcplen |= htole16(0x8000); 3612 if (txs->txs_dn.d_residue) 3613 hh->atw_tail_plcplen |= htole16(0x8000); 3614 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3615 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3616 3617 /* never fragment multicast frames */ 3618 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3619 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3620 } else if (sc->sc_flags & ATWF_RTSCTS) { 3621 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3622 } 3623 3624 #ifdef ATW_DEBUG 3625 hh->atw_fragnum = 0; 3626 3627 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3628 printf("%s: dst = %s, rate = 0x%02x, " 3629 "service = 0x%02x, paylen = 0x%04x\n", 3630 device_xname(&sc->sc_dev), ether_sprintf(hh->atw_dst), 3631 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3632 3633 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3634 "dur1 = 0x%04x, dur2 = 0x%04x, " 3635 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3636 device_xname(&sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3637 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3638 hh->atw_tail_dur, hh->atw_head_dur); 3639 3640 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3641 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3642 device_xname(&sc->sc_dev), hh->atw_hdrctl, 3643 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3644 3645 printf("%s: keyid = %d\n", 3646 device_xname(&sc->sc_dev), hh->atw_keyid); 3647 3648 atw_dump_pkt(ifp, m0); 3649 } 3650 #endif /* ATW_DEBUG */ 3651 3652 dmamap = txs->txs_dmamap; 3653 3654 /* 3655 * Load the DMA map. Copy and try (once) again if the packet 3656 * didn't fit in the alloted number of segments. 3657 */ 3658 for (first = 1; 3659 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3660 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3661 first = 0) { 3662 MGETHDR(m, M_DONTWAIT, MT_DATA); 3663 if (m == NULL) { 3664 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n"); 3665 break; 3666 } 3667 if (m0->m_pkthdr.len > MHLEN) { 3668 MCLGET(m, M_DONTWAIT); 3669 if ((m->m_flags & M_EXT) == 0) { 3670 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx " 3671 "cluster\n"); 3672 m_freem(m); 3673 break; 3674 } 3675 } 3676 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3677 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3678 m_freem(m0); 3679 m0 = m; 3680 m = NULL; 3681 } 3682 if (error != 0) { 3683 aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, " 3684 "error = %d\n", error); 3685 m_freem(m0); 3686 break; 3687 } 3688 3689 /* 3690 * Ensure we have enough descriptors free to describe 3691 * the packet. 3692 */ 3693 if (dmamap->dm_nsegs > sc->sc_txfree) { 3694 /* 3695 * Not enough free descriptors to transmit 3696 * this packet. Unload the DMA map and 3697 * drop the packet. Notify the upper layer 3698 * that there are no more slots left. 3699 * 3700 * XXX We could allocate an mbuf and copy, but 3701 * XXX it is worth it? 3702 */ 3703 bus_dmamap_unload(sc->sc_dmat, dmamap); 3704 m_freem(m0); 3705 break; 3706 } 3707 3708 /* 3709 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3710 */ 3711 3712 /* Sync the DMA map. */ 3713 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3714 BUS_DMASYNC_PREWRITE); 3715 3716 /* XXX arbitrary retry limit; 8 because I have seen it in 3717 * use already and maybe 0 means "no tries" ! 3718 */ 3719 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3720 3721 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3722 device_xname(&sc->sc_dev), rate * 5)); 3723 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3724 3725 /* 3726 * Initialize the transmit descriptors. 3727 */ 3728 for (nexttx = sc->sc_txnext, seg = 0; 3729 seg < dmamap->dm_nsegs; 3730 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3731 /* 3732 * If this is the first descriptor we're 3733 * enqueueing, don't set the OWN bit just 3734 * yet. That could cause a race condition. 3735 * We'll do it below. 3736 */ 3737 txd = &sc->sc_txdescs[nexttx]; 3738 txd->at_ctl = ctl | 3739 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3740 3741 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3742 txd->at_flags = 3743 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3744 ATW_TXFLAG_TBS1_MASK)) | 3745 ((nexttx == (ATW_NTXDESC - 1)) 3746 ? htole32(ATW_TXFLAG_TER) : 0); 3747 lasttx = nexttx; 3748 } 3749 3750 /* Set `first segment' and `last segment' appropriately. */ 3751 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3752 htole32(ATW_TXFLAG_FS); 3753 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3754 3755 #ifdef ATW_DEBUG 3756 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3757 printf(" txsoft %p transmit chain:\n", txs); 3758 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3759 printf(" descriptor %d:\n", seg); 3760 printf(" at_ctl: 0x%08x\n", 3761 le32toh(sc->sc_txdescs[seg].at_ctl)); 3762 printf(" at_flags: 0x%08x\n", 3763 le32toh(sc->sc_txdescs[seg].at_flags)); 3764 printf(" at_buf1: 0x%08x\n", 3765 le32toh(sc->sc_txdescs[seg].at_buf1)); 3766 printf(" at_buf2: 0x%08x\n", 3767 le32toh(sc->sc_txdescs[seg].at_buf2)); 3768 if (seg == lasttx) 3769 break; 3770 } 3771 } 3772 #endif 3773 3774 /* Sync the descriptors we're using. */ 3775 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3776 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3777 3778 /* 3779 * Store a pointer to the packet so we can free it later, 3780 * and remember what txdirty will be once the packet is 3781 * done. 3782 */ 3783 txs->txs_mbuf = m0; 3784 txs->txs_firstdesc = sc->sc_txnext; 3785 txs->txs_lastdesc = lasttx; 3786 txs->txs_ndescs = dmamap->dm_nsegs; 3787 3788 /* Advance the tx pointer. */ 3789 sc->sc_txfree -= dmamap->dm_nsegs; 3790 sc->sc_txnext = nexttx; 3791 3792 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3793 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3794 3795 last_txs = txs; 3796 } 3797 3798 if (sc->sc_txfree != ofree) { 3799 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3800 device_xname(&sc->sc_dev), lasttx, firsttx)); 3801 /* 3802 * Cause a transmit interrupt to happen on the 3803 * last packet we enqueued. 3804 */ 3805 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3806 ATW_CDTXSYNC(sc, lasttx, 1, 3807 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3808 3809 /* 3810 * The entire packet chain is set up. Give the 3811 * first descriptor to the chip now. 3812 */ 3813 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3814 ATW_CDTXSYNC(sc, firsttx, 1, 3815 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3816 3817 /* Wake up the transmitter. */ 3818 ATW_WRITE(sc, ATW_TDR, 0x1); 3819 3820 if (txs == NULL || sc->sc_txfree == 0) 3821 ifp->if_flags |= IFF_OACTIVE; 3822 3823 /* Set a watchdog timer in case the chip flakes out. */ 3824 sc->sc_tx_timer = 5; 3825 ifp->if_timer = 1; 3826 } 3827 } 3828 3829 /* 3830 * atw_ioctl: [ifnet interface function] 3831 * 3832 * Handle control requests from the operator. 3833 */ 3834 int 3835 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3836 { 3837 struct atw_softc *sc = ifp->if_softc; 3838 int s, error = 0; 3839 3840 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3841 if (!device_is_active(&sc->sc_dev)) 3842 return ENXIO; 3843 3844 s = splnet(); 3845 3846 switch (cmd) { 3847 case SIOCSIFFLAGS: 3848 if (ifp->if_flags & IFF_UP) { 3849 if (ATW_IS_ENABLED(sc)) { 3850 /* 3851 * To avoid rescanning another access point, 3852 * do not call atw_init() here. Instead, 3853 * only reflect media settings. 3854 */ 3855 atw_filter_setup(sc); 3856 } else 3857 error = atw_init(ifp); 3858 } else if (ATW_IS_ENABLED(sc)) 3859 atw_stop(ifp, 1); 3860 break; 3861 case SIOCADDMULTI: 3862 case SIOCDELMULTI: 3863 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3864 if (ifp->if_flags & IFF_RUNNING) 3865 atw_filter_setup(sc); /* do not rescan */ 3866 error = 0; 3867 } 3868 break; 3869 default: 3870 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3871 if (error == ENETRESET || error == ERESTART) { 3872 if (is_running(ifp)) 3873 error = atw_init(ifp); 3874 else 3875 error = 0; 3876 } 3877 break; 3878 } 3879 3880 /* Try to get more packets going. */ 3881 if (ATW_IS_ENABLED(sc)) 3882 atw_start(ifp); 3883 3884 splx(s); 3885 return (error); 3886 } 3887 3888 static int 3889 atw_media_change(struct ifnet *ifp) 3890 { 3891 int error; 3892 3893 error = ieee80211_media_change(ifp); 3894 if (error == ENETRESET) { 3895 if (is_running(ifp)) 3896 error = atw_init(ifp); 3897 else 3898 error = 0; 3899 } 3900 return error; 3901 } 3902
Indexes created Tue Sep 23 07:09:52 GMT 2025