atw.c revision 1.142.2.1
1 /* $NetBSD: atw.c,v 1.142.2.1 2009/07/23 23:31:47 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.142.2.1 2009/07/23 23:31:47 jym Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/time.h> 52 #include <lib/libkern/libkern.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/bus.h> 72 #include <sys/intr.h> 73 74 #include <dev/ic/atwreg.h> 75 #include <dev/ic/rf3000reg.h> 76 #include <dev/ic/si4136reg.h> 77 #include <dev/ic/atwvar.h> 78 #include <dev/ic/smc93cx6var.h> 79 80 /* XXX TBD open questions 81 * 82 * 83 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 84 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 85 * handle this for me? 86 * 87 */ 88 /* device attachment 89 * 90 * print TOFS[012] 91 * 92 * device initialization 93 * 94 * clear ATW_FRCTL_MAXPSP to disable max power saving 95 * set ATW_TXBR_ALCUPDATE to enable ALC 96 * set TOFS[012]? (hope not) 97 * disable rx/tx 98 * set ATW_PAR_SWR (software reset) 99 * wait for ATW_PAR_SWR clear 100 * disable interrupts 101 * ack status register 102 * enable interrupts 103 * 104 * rx/tx initialization 105 * 106 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 107 * allocate and init descriptor rings 108 * write ATW_PAR_DSL (descriptor skip length) 109 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 110 * write ATW_NAR_SQ for one/both transmit descriptor rings 111 * write ATW_NAR_SQ for one/both transmit descriptor rings 112 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * 114 * rx/tx end 115 * 116 * stop DMA 117 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 118 * flush tx w/ ATW_NAR_HF 119 * 120 * scan 121 * 122 * initialize rx/tx 123 * 124 * BSS join: (re)association response 125 * 126 * set ATW_FRCTL_AID 127 * 128 * optimizations ??? 129 * 130 */ 131 132 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 133 134 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 135 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 136 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 137 138 int atw_pseudo_milli = 1; 139 int atw_magic_delay1 = 100 * 1000; 140 int atw_magic_delay2 = 100 * 1000; 141 /* more magic multi-millisecond delays (units: microseconds) */ 142 int atw_nar_delay = 20 * 1000; 143 int atw_magic_delay4 = 10 * 1000; 144 int atw_rf_delay1 = 10 * 1000; 145 int atw_rf_delay2 = 5 * 1000; 146 int atw_plcphd_delay = 2 * 1000; 147 int atw_bbp_io_enable_delay = 20 * 1000; 148 int atw_bbp_io_disable_delay = 2 * 1000; 149 int atw_writewep_delay = 1000; 150 int atw_beacon_len_adjust = 4; 151 int atw_dwelltime = 200; 152 int atw_xindiv2 = 0; 153 154 #ifdef ATW_DEBUG 155 int atw_debug = 0; 156 157 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 158 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 159 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 160 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 161 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 162 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 163 164 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 165 static void atw_print_regs(struct atw_softc *, const char *); 166 167 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 168 # ifdef ATW_BBPDEBUG 169 static void atw_rf3000_print(struct atw_softc *); 170 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 171 # endif /* ATW_BBPDEBUG */ 172 173 # ifdef ATW_SYNDEBUG 174 static void atw_si4126_print(struct atw_softc *); 175 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 176 # endif /* ATW_SYNDEBUG */ 177 178 #else 179 #define ATW_DPRINTF(x) 180 #define ATW_DPRINTF2(x) 181 #define ATW_DPRINTF3(x) 182 #define DPRINTF(sc, x) /* nothing */ 183 #define DPRINTF2(sc, x) /* nothing */ 184 #define DPRINTF3(sc, x) /* nothing */ 185 #endif 186 187 /* ifnet methods */ 188 int atw_init(struct ifnet *); 189 int atw_ioctl(struct ifnet *, u_long, void *); 190 void atw_start(struct ifnet *); 191 void atw_stop(struct ifnet *, int); 192 void atw_watchdog(struct ifnet *); 193 194 /* Device attachment */ 195 void atw_attach(struct atw_softc *); 196 int atw_detach(struct atw_softc *); 197 static void atw_evcnt_attach(struct atw_softc *); 198 static void atw_evcnt_detach(struct atw_softc *); 199 200 /* Rx/Tx process */ 201 int atw_add_rxbuf(struct atw_softc *, int); 202 void atw_idle(struct atw_softc *, u_int32_t); 203 void atw_rxdrain(struct atw_softc *); 204 void atw_txdrain(struct atw_softc *); 205 206 /* Device (de)activation and power state */ 207 void atw_disable(struct atw_softc *); 208 int atw_enable(struct atw_softc *); 209 void atw_reset(struct atw_softc *); 210 211 /* Interrupt handlers */ 212 void atw_linkintr(struct atw_softc *, u_int32_t); 213 void atw_rxintr(struct atw_softc *); 214 void atw_txintr(struct atw_softc *); 215 216 /* 802.11 state machine */ 217 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 218 static void atw_next_scan(void *); 219 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221 static int atw_tune(struct atw_softc *); 222 223 /* Device initialization */ 224 static void atw_bbp_io_init(struct atw_softc *); 225 static void atw_cfp_init(struct atw_softc *); 226 static void atw_cmdr_init(struct atw_softc *); 227 static void atw_ifs_init(struct atw_softc *); 228 static void atw_nar_init(struct atw_softc *); 229 static void atw_response_times_init(struct atw_softc *); 230 static void atw_rf_reset(struct atw_softc *); 231 static void atw_test1_init(struct atw_softc *); 232 static void atw_tofs0_init(struct atw_softc *); 233 static void atw_tofs2_init(struct atw_softc *); 234 static void atw_txlmt_init(struct atw_softc *); 235 static void atw_wcsr_init(struct atw_softc *); 236 237 /* Key management */ 238 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 239 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 240 const u_int8_t[IEEE80211_ADDR_LEN]); 241 static void atw_key_update_begin(struct ieee80211com *); 242 static void atw_key_update_end(struct ieee80211com *); 243 244 /* RAM/ROM utilities */ 245 static void atw_clear_sram(struct atw_softc *); 246 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 247 static int atw_read_srom(struct atw_softc *); 248 249 /* BSS setup */ 250 static void atw_predict_beacon(struct atw_softc *); 251 static void atw_start_beacon(struct atw_softc *, int); 252 static void atw_write_bssid(struct atw_softc *); 253 static void atw_write_ssid(struct atw_softc *); 254 static void atw_write_sup_rates(struct atw_softc *); 255 static void atw_write_wep(struct atw_softc *); 256 257 /* Media */ 258 static int atw_media_change(struct ifnet *); 259 260 static void atw_filter_setup(struct atw_softc *); 261 262 /* 802.11 utilities */ 263 static uint64_t atw_get_tsft(struct atw_softc *); 264 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 265 uint32_t); 266 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 267 static void atw_node_free(struct ieee80211_node *); 268 269 /* 270 * Tuner/transceiver/modem 271 */ 272 static void atw_bbp_io_enable(struct atw_softc *, int); 273 274 /* RFMD RF3000 Baseband Processor */ 275 static int atw_rf3000_init(struct atw_softc *); 276 static int atw_rf3000_tune(struct atw_softc *, u_int); 277 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 278 279 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 280 static void atw_si4126_tune(struct atw_softc *, u_int); 281 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 282 283 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 284 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 285 286 const char *atw_tx_state[] = { 287 "STOPPED", 288 "RUNNING - read descriptor", 289 "RUNNING - transmitting", 290 "RUNNING - filling fifo", /* XXX */ 291 "SUSPENDED", 292 "RUNNING -- write descriptor", 293 "RUNNING -- write last descriptor", 294 "RUNNING - fifo full" 295 }; 296 297 const char *atw_rx_state[] = { 298 "STOPPED", 299 "RUNNING - read descriptor", 300 "RUNNING - check this packet, pre-fetch next", 301 "RUNNING - wait for reception", 302 "SUSPENDED", 303 "RUNNING - write descriptor", 304 "RUNNING - flush fifo", 305 "RUNNING - fifo drain" 306 }; 307 308 static inline int 309 is_running(struct ifnet *ifp) 310 { 311 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 312 } 313 314 int 315 atw_activate(device_t self, enum devact act) 316 { 317 struct atw_softc *sc = device_private(self); 318 int rv = 0, s; 319 320 s = splnet(); 321 switch (act) { 322 case DVACT_ACTIVATE: 323 rv = EOPNOTSUPP; 324 break; 325 326 case DVACT_DEACTIVATE: 327 if_deactivate(&sc->sc_if); 328 break; 329 } 330 splx(s); 331 return rv; 332 } 333 334 /* 335 * atw_enable: 336 * 337 * Enable the ADM8211 chip. 338 */ 339 int 340 atw_enable(struct atw_softc *sc) 341 { 342 343 if (ATW_IS_ENABLED(sc) == 0) { 344 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 345 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 346 return (EIO); 347 } 348 sc->sc_flags |= ATWF_ENABLED; 349 /* Power may have been removed, and WEP keys thus 350 * reset. 351 */ 352 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 353 } 354 return (0); 355 } 356 357 /* 358 * atw_disable: 359 * 360 * Disable the ADM8211 chip. 361 */ 362 void 363 atw_disable(struct atw_softc *sc) 364 { 365 if (!ATW_IS_ENABLED(sc)) 366 return; 367 if (sc->sc_disable != NULL) 368 (*sc->sc_disable)(sc); 369 sc->sc_flags &= ~ATWF_ENABLED; 370 } 371 372 /* Returns -1 on failure. */ 373 static int 374 atw_read_srom(struct atw_softc *sc) 375 { 376 struct seeprom_descriptor sd; 377 uint32_t test0, fail_bits; 378 379 (void)memset(&sd, 0, sizeof(sd)); 380 381 test0 = ATW_READ(sc, ATW_TEST0); 382 383 switch (sc->sc_rev) { 384 case ATW_REVISION_BA: 385 case ATW_REVISION_CA: 386 fail_bits = ATW_TEST0_EPNE; 387 break; 388 default: 389 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 390 break; 391 } 392 if ((test0 & fail_bits) != 0) { 393 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 394 return -1; 395 } 396 397 switch (test0 & ATW_TEST0_EPTYP_MASK) { 398 case ATW_TEST0_EPTYP_93c66: 399 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 400 sc->sc_sromsz = 512; 401 sd.sd_chip = C56_66; 402 break; 403 case ATW_TEST0_EPTYP_93c46: 404 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 405 sc->sc_sromsz = 128; 406 sd.sd_chip = C46; 407 break; 408 default: 409 printf("%s: unknown SROM type %" __PRIuBITS "\n", 410 device_xname(sc->sc_dev), 411 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 412 return -1; 413 } 414 415 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 416 417 if (sc->sc_srom == NULL) { 418 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 419 return -1; 420 } 421 422 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 423 424 /* ADM8211 has a single 32-bit register for controlling the 425 * 93cx6 SROM. Bit SRS enables the serial port. There is no 426 * "ready" bit. The ADM8211 input/output sense is the reverse 427 * of read_seeprom's. 428 */ 429 sd.sd_tag = sc->sc_st; 430 sd.sd_bsh = sc->sc_sh; 431 sd.sd_regsize = 4; 432 sd.sd_control_offset = ATW_SPR; 433 sd.sd_status_offset = ATW_SPR; 434 sd.sd_dataout_offset = ATW_SPR; 435 sd.sd_CK = ATW_SPR_SCLK; 436 sd.sd_CS = ATW_SPR_SCS; 437 sd.sd_DI = ATW_SPR_SDO; 438 sd.sd_DO = ATW_SPR_SDI; 439 sd.sd_MS = ATW_SPR_SRS; 440 sd.sd_RDY = 0; 441 442 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 443 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 444 free(sc->sc_srom, M_DEVBUF); 445 return -1; 446 } 447 #ifdef ATW_DEBUG 448 { 449 int i; 450 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 451 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 452 if (((i % 8) == 0) && (i != 0)) { 453 ATW_DPRINTF(("\n\t")); 454 } 455 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 456 } 457 ATW_DPRINTF(("\n")); 458 } 459 #endif /* ATW_DEBUG */ 460 return 0; 461 } 462 463 #ifdef ATW_DEBUG 464 static void 465 atw_print_regs(struct atw_softc *sc, const char *where) 466 { 467 #define PRINTREG(sc, reg) \ 468 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 469 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 470 471 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 472 473 PRINTREG(sc, ATW_PAR); 474 PRINTREG(sc, ATW_FRCTL); 475 PRINTREG(sc, ATW_TDR); 476 PRINTREG(sc, ATW_WTDP); 477 PRINTREG(sc, ATW_RDR); 478 PRINTREG(sc, ATW_WRDP); 479 PRINTREG(sc, ATW_RDB); 480 PRINTREG(sc, ATW_CSR3A); 481 PRINTREG(sc, ATW_TDBD); 482 PRINTREG(sc, ATW_TDBP); 483 PRINTREG(sc, ATW_STSR); 484 PRINTREG(sc, ATW_CSR5A); 485 PRINTREG(sc, ATW_NAR); 486 PRINTREG(sc, ATW_CSR6A); 487 PRINTREG(sc, ATW_IER); 488 PRINTREG(sc, ATW_CSR7A); 489 PRINTREG(sc, ATW_LPC); 490 PRINTREG(sc, ATW_TEST1); 491 PRINTREG(sc, ATW_SPR); 492 PRINTREG(sc, ATW_TEST0); 493 PRINTREG(sc, ATW_WCSR); 494 PRINTREG(sc, ATW_WPDR); 495 PRINTREG(sc, ATW_GPTMR); 496 PRINTREG(sc, ATW_GPIO); 497 PRINTREG(sc, ATW_BBPCTL); 498 PRINTREG(sc, ATW_SYNCTL); 499 PRINTREG(sc, ATW_PLCPHD); 500 PRINTREG(sc, ATW_MMIWADDR); 501 PRINTREG(sc, ATW_MMIRADDR1); 502 PRINTREG(sc, ATW_MMIRADDR2); 503 PRINTREG(sc, ATW_TXBR); 504 PRINTREG(sc, ATW_CSR15A); 505 PRINTREG(sc, ATW_ALCSTAT); 506 PRINTREG(sc, ATW_TOFS2); 507 PRINTREG(sc, ATW_CMDR); 508 PRINTREG(sc, ATW_PCIC); 509 PRINTREG(sc, ATW_PMCSR); 510 PRINTREG(sc, ATW_PAR0); 511 PRINTREG(sc, ATW_PAR1); 512 PRINTREG(sc, ATW_MAR0); 513 PRINTREG(sc, ATW_MAR1); 514 PRINTREG(sc, ATW_ATIMDA0); 515 PRINTREG(sc, ATW_ABDA1); 516 PRINTREG(sc, ATW_BSSID0); 517 PRINTREG(sc, ATW_TXLMT); 518 PRINTREG(sc, ATW_MIBCNT); 519 PRINTREG(sc, ATW_BCNT); 520 PRINTREG(sc, ATW_TSFTH); 521 PRINTREG(sc, ATW_TSC); 522 PRINTREG(sc, ATW_SYNRF); 523 PRINTREG(sc, ATW_BPLI); 524 PRINTREG(sc, ATW_CAP0); 525 PRINTREG(sc, ATW_CAP1); 526 PRINTREG(sc, ATW_RMD); 527 PRINTREG(sc, ATW_CFPP); 528 PRINTREG(sc, ATW_TOFS0); 529 PRINTREG(sc, ATW_TOFS1); 530 PRINTREG(sc, ATW_IFST); 531 PRINTREG(sc, ATW_RSPT); 532 PRINTREG(sc, ATW_TSFTL); 533 PRINTREG(sc, ATW_WEPCTL); 534 PRINTREG(sc, ATW_WESK); 535 PRINTREG(sc, ATW_WEPCNT); 536 PRINTREG(sc, ATW_MACTEST); 537 PRINTREG(sc, ATW_FER); 538 PRINTREG(sc, ATW_FEMR); 539 PRINTREG(sc, ATW_FPSR); 540 PRINTREG(sc, ATW_FFER); 541 #undef PRINTREG 542 } 543 #endif /* ATW_DEBUG */ 544 545 /* 546 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 547 */ 548 void 549 atw_attach(struct atw_softc *sc) 550 { 551 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 553 }; 554 struct ieee80211com *ic = &sc->sc_ic; 555 struct ifnet *ifp = &sc->sc_if; 556 int country_code, error, i, nrate, srom_major; 557 u_int32_t reg; 558 static const char *type_strings[] = {"Intersil (not supported)", 559 "RFMD", "Marvel (not supported)"}; 560 561 sc->sc_txth = atw_txthresh_tab_lo; 562 563 SIMPLEQ_INIT(&sc->sc_txfreeq); 564 SIMPLEQ_INIT(&sc->sc_txdirtyq); 565 566 #ifdef ATW_DEBUG 567 atw_print_regs(sc, "atw_attach"); 568 #endif /* ATW_DEBUG */ 569 570 /* 571 * Allocate the control data structures, and create and load the 572 * DMA map for it. 573 */ 574 if ((error = bus_dmamem_alloc(sc->sc_dmat, 575 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 576 1, &sc->sc_cdnseg, 0)) != 0) { 577 aprint_error_dev(sc->sc_dev, 578 "unable to allocate control data, error = %d\n", 579 error); 580 goto fail_0; 581 } 582 583 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 584 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 585 BUS_DMA_COHERENT)) != 0) { 586 aprint_error_dev(sc->sc_dev, 587 "unable to map control data, error = %d\n", 588 error); 589 goto fail_1; 590 } 591 592 if ((error = bus_dmamap_create(sc->sc_dmat, 593 sizeof(struct atw_control_data), 1, 594 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "unable to create control data DMA map, error = %d\n", 597 error); 598 goto fail_2; 599 } 600 601 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 602 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 603 0)) != 0) { 604 aprint_error_dev(sc->sc_dev, 605 "unable to load control data DMA map, error = %d\n", error); 606 goto fail_3; 607 } 608 609 /* 610 * Create the transmit buffer DMA maps. 611 */ 612 sc->sc_ntxsegs = ATW_NTXSEGS; 613 for (i = 0; i < ATW_TXQUEUELEN; i++) { 614 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 615 sc->sc_ntxsegs, MCLBYTES, 0, 0, 616 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 617 aprint_error_dev(sc->sc_dev, 618 "unable to create tx DMA map %d, error = %d\n", i, 619 error); 620 goto fail_4; 621 } 622 } 623 624 /* 625 * Create the receive buffer DMA maps. 626 */ 627 for (i = 0; i < ATW_NRXDESC; i++) { 628 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 629 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 630 aprint_error_dev(sc->sc_dev, 631 "unable to create rx DMA map %d, error = %d\n", i, 632 error); 633 goto fail_5; 634 } 635 } 636 for (i = 0; i < ATW_NRXDESC; i++) { 637 sc->sc_rxsoft[i].rxs_mbuf = NULL; 638 } 639 640 switch (sc->sc_rev) { 641 case ATW_REVISION_AB: 642 case ATW_REVISION_AF: 643 sc->sc_sramlen = ATW_SRAM_A_SIZE; 644 break; 645 case ATW_REVISION_BA: 646 case ATW_REVISION_CA: 647 sc->sc_sramlen = ATW_SRAM_B_SIZE; 648 break; 649 } 650 651 /* Reset the chip to a known state. */ 652 atw_reset(sc); 653 654 if (atw_read_srom(sc) == -1) 655 return; 656 657 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 658 ATW_SR_RFTYPE_MASK); 659 660 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 661 ATW_SR_BBPTYPE_MASK); 662 663 if (sc->sc_rftype >= __arraycount(type_strings)) { 664 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 665 return; 666 } 667 if (sc->sc_bbptype >= __arraycount(type_strings)) { 668 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 669 return; 670 } 671 672 printf("%s: %s RF, %s BBP", device_xname(sc->sc_dev), 673 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 674 675 /* XXX There exists a Linux driver which seems to use RFType = 0 for 676 * MARVEL. My bug, or theirs? 677 */ 678 679 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 680 681 switch (sc->sc_rftype) { 682 case ATW_RFTYPE_INTERSIL: 683 reg |= ATW_SYNCTL_CS1; 684 break; 685 case ATW_RFTYPE_RFMD: 686 reg |= ATW_SYNCTL_CS0; 687 break; 688 case ATW_RFTYPE_MARVEL: 689 break; 690 } 691 692 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 693 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 694 695 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 696 697 switch (sc->sc_bbptype) { 698 case ATW_BBPTYPE_INTERSIL: 699 reg |= ATW_BBPCTL_TWI; 700 break; 701 case ATW_BBPTYPE_RFMD: 702 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 703 ATW_BBPCTL_CCA_ACTLO; 704 break; 705 case ATW_BBPTYPE_MARVEL: 706 break; 707 case ATW_C_BBPTYPE_RFMD: 708 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 709 device_xname(sc->sc_dev)); 710 break; 711 } 712 713 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 714 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 715 716 /* 717 * From this point forward, the attachment cannot fail. A failure 718 * before this point releases all resources that may have been 719 * allocated. 720 */ 721 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 722 723 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 724 htole16(sc->sc_srom[ATW_SR_MAC00]), 725 htole16(sc->sc_srom[ATW_SR_MAC01]), 726 htole16(sc->sc_srom[ATW_SR_MAC10]))); 727 728 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 729 ATW_SR_MAJOR_MASK); 730 731 if (srom_major < 2) 732 sc->sc_rf3000_options1 = 0; 733 else if (sc->sc_rev == ATW_REVISION_BA) { 734 sc->sc_rf3000_options1 = 735 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 736 ATW_SR_CR28_MASK); 737 } else 738 sc->sc_rf3000_options1 = 0; 739 740 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 741 ATW_SR_CR29_MASK); 742 743 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 744 ATW_SR_CTRY_MASK); 745 746 #define ADD_CHANNEL(_ic, _chan) do { \ 747 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 748 _ic->ic_channels[_chan].ic_freq = \ 749 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 750 } while (0) 751 752 /* Find available channels */ 753 switch (country_code) { 754 case COUNTRY_MMK2: /* 1-14 */ 755 ADD_CHANNEL(ic, 14); 756 /*FALLTHROUGH*/ 757 case COUNTRY_ETSI: /* 1-13 */ 758 for (i = 1; i <= 13; i++) 759 ADD_CHANNEL(ic, i); 760 break; 761 case COUNTRY_FCC: /* 1-11 */ 762 case COUNTRY_IC: /* 1-11 */ 763 for (i = 1; i <= 11; i++) 764 ADD_CHANNEL(ic, i); 765 break; 766 case COUNTRY_MMK: /* 14 */ 767 ADD_CHANNEL(ic, 14); 768 break; 769 case COUNTRY_FRANCE: /* 10-13 */ 770 for (i = 10; i <= 13; i++) 771 ADD_CHANNEL(ic, i); 772 break; 773 default: /* assume channels 10-11 */ 774 case COUNTRY_SPAIN: /* 10-11 */ 775 for (i = 10; i <= 11; i++) 776 ADD_CHANNEL(ic, i); 777 break; 778 } 779 780 /* Read the MAC address. */ 781 reg = ATW_READ(sc, ATW_PAR0); 782 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 783 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 784 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 785 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 786 reg = ATW_READ(sc, ATW_PAR1); 787 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 788 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 789 790 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 791 printf(" could not get mac address, attach failed\n"); 792 return; 793 } 794 795 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 796 797 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 798 ifp->if_softc = sc; 799 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 800 IFF_NOTRAILERS; 801 ifp->if_ioctl = atw_ioctl; 802 ifp->if_start = atw_start; 803 ifp->if_watchdog = atw_watchdog; 804 ifp->if_init = atw_init; 805 ifp->if_stop = atw_stop; 806 IFQ_SET_READY(&ifp->if_snd); 807 808 ic->ic_ifp = ifp; 809 ic->ic_phytype = IEEE80211_T_DS; 810 ic->ic_opmode = IEEE80211_M_STA; 811 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 812 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 813 814 nrate = 0; 815 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 816 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 817 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 820 821 /* 822 * Call MI attach routines. 823 */ 824 825 if_attach(ifp); 826 ieee80211_ifattach(ic); 827 828 atw_evcnt_attach(sc); 829 830 sc->sc_newstate = ic->ic_newstate; 831 ic->ic_newstate = atw_newstate; 832 833 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 834 ic->ic_recv_mgmt = atw_recv_mgmt; 835 836 sc->sc_node_free = ic->ic_node_free; 837 ic->ic_node_free = atw_node_free; 838 839 sc->sc_node_alloc = ic->ic_node_alloc; 840 ic->ic_node_alloc = atw_node_alloc; 841 842 ic->ic_crypto.cs_key_delete = atw_key_delete; 843 ic->ic_crypto.cs_key_set = atw_key_set; 844 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 845 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 846 847 /* possibly we should fill in our own sc_send_prresp, since 848 * the ADM8211 is probably sending probe responses in ad hoc 849 * mode. 850 */ 851 852 /* complete initialization */ 853 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 854 callout_init(&sc->sc_scan_ch, 0); 855 856 #if NBPFILTER > 0 857 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 858 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 859 #endif 860 861 if (!pmf_device_register1(sc->sc_dev, NULL, NULL, atw_shutdown)) { 862 aprint_error_dev(sc->sc_dev, 863 "couldn't establish power handler\n"); 864 } else 865 pmf_class_network_register(sc->sc_dev, &sc->sc_if); 866 867 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 868 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 869 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 870 871 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 872 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 873 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 874 875 ieee80211_announce(ic); 876 return; 877 878 /* 879 * Free any resources we've allocated during the failed attach 880 * attempt. Do this in reverse order and fall through. 881 */ 882 fail_5: 883 for (i = 0; i < ATW_NRXDESC; i++) { 884 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 885 continue; 886 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 887 } 888 fail_4: 889 for (i = 0; i < ATW_TXQUEUELEN; i++) { 890 if (sc->sc_txsoft[i].txs_dmamap == NULL) 891 continue; 892 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 893 } 894 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 895 fail_3: 896 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 897 fail_2: 898 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 899 sizeof(struct atw_control_data)); 900 fail_1: 901 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 902 fail_0: 903 return; 904 } 905 906 static struct ieee80211_node * 907 atw_node_alloc(struct ieee80211_node_table *nt) 908 { 909 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 910 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 911 912 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 913 return ni; 914 } 915 916 static void 917 atw_node_free(struct ieee80211_node *ni) 918 { 919 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 920 921 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 922 ether_sprintf(ni->ni_bssid))); 923 (*sc->sc_node_free)(ni); 924 } 925 926 927 static void 928 atw_test1_reset(struct atw_softc *sc) 929 { 930 switch (sc->sc_rev) { 931 case ATW_REVISION_BA: 932 if (1 /* XXX condition on transceiver type */) { 933 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 934 } 935 break; 936 case ATW_REVISION_CA: 937 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 938 break; 939 default: 940 break; 941 } 942 } 943 944 /* 945 * atw_reset: 946 * 947 * Perform a soft reset on the ADM8211. 948 */ 949 void 950 atw_reset(struct atw_softc *sc) 951 { 952 int i; 953 uint32_t lpc; 954 955 ATW_WRITE(sc, ATW_NAR, 0x0); 956 DELAY(atw_nar_delay); 957 958 /* Reference driver has a cryptic remark indicating that this might 959 * power-on the chip. I know that it turns off power-saving.... 960 */ 961 ATW_WRITE(sc, ATW_FRCTL, 0x0); 962 963 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 964 965 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 966 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 967 break; 968 DELAY(atw_pseudo_milli); 969 } 970 971 /* ... and then pause 100ms longer for good measure. */ 972 DELAY(atw_magic_delay1); 973 974 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 975 976 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 977 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 978 979 /* 980 * Initialize the PCI Access Register. 981 */ 982 sc->sc_busmode = ATW_PAR_PBL_8DW; 983 984 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 985 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 986 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 987 988 atw_test1_reset(sc); 989 990 /* Turn off maximum power saving, etc. */ 991 ATW_WRITE(sc, ATW_FRCTL, 0x0); 992 993 DELAY(atw_magic_delay2); 994 995 /* Recall EEPROM. */ 996 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 997 998 DELAY(atw_magic_delay4); 999 1000 lpc = ATW_READ(sc, ATW_LPC); 1001 1002 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1003 1004 /* A reset seems to affect the SRAM contents, so put them into 1005 * a known state. 1006 */ 1007 atw_clear_sram(sc); 1008 1009 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1010 } 1011 1012 static void 1013 atw_clear_sram(struct atw_softc *sc) 1014 { 1015 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1016 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1017 /* XXX not for revision 0x20. */ 1018 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1019 } 1020 1021 /* TBD atw_init 1022 * 1023 * set MAC based on ic->ic_bss->myaddr 1024 * write WEP keys 1025 * set TX rate 1026 */ 1027 1028 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1029 * without receiving a beacon with the preferred BSSID & SSID. 1030 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1031 */ 1032 static void 1033 atw_wcsr_init(struct atw_softc *sc) 1034 { 1035 uint32_t wcsr; 1036 1037 wcsr = ATW_READ(sc, ATW_WCSR); 1038 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1039 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1040 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1041 1042 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1043 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1044 } 1045 1046 /* Turn off power management. Set Rx store-and-forward mode. */ 1047 static void 1048 atw_cmdr_init(struct atw_softc *sc) 1049 { 1050 uint32_t cmdr; 1051 cmdr = ATW_READ(sc, ATW_CMDR); 1052 cmdr &= ~ATW_CMDR_APM; 1053 cmdr |= ATW_CMDR_RTE; 1054 cmdr &= ~ATW_CMDR_DRT_MASK; 1055 cmdr |= ATW_CMDR_DRT_SF; 1056 1057 ATW_WRITE(sc, ATW_CMDR, cmdr); 1058 } 1059 1060 static void 1061 atw_tofs2_init(struct atw_softc *sc) 1062 { 1063 uint32_t tofs2; 1064 /* XXX this magic can probably be figured out from the RFMD docs */ 1065 #ifndef ATW_REFSLAVE 1066 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1067 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1068 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1069 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1070 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1071 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1072 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1073 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1074 #else 1075 /* XXX new magic from reference driver source */ 1076 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1077 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1078 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1079 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1080 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1081 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1082 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1083 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1084 #endif 1085 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1086 } 1087 1088 static void 1089 atw_nar_init(struct atw_softc *sc) 1090 { 1091 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1092 } 1093 1094 static void 1095 atw_txlmt_init(struct atw_softc *sc) 1096 { 1097 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1098 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1099 } 1100 1101 static void 1102 atw_test1_init(struct atw_softc *sc) 1103 { 1104 uint32_t test1; 1105 1106 test1 = ATW_READ(sc, ATW_TEST1); 1107 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1108 /* XXX magic 0x1 */ 1109 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1110 ATW_WRITE(sc, ATW_TEST1, test1); 1111 } 1112 1113 static void 1114 atw_rf_reset(struct atw_softc *sc) 1115 { 1116 /* XXX this resets an Intersil RF front-end? */ 1117 /* TBD condition on Intersil RFType? */ 1118 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1119 DELAY(atw_rf_delay1); 1120 ATW_WRITE(sc, ATW_SYNRF, 0); 1121 DELAY(atw_rf_delay2); 1122 } 1123 1124 /* Set 16 TU max duration for the contention-free period (CFP). */ 1125 static void 1126 atw_cfp_init(struct atw_softc *sc) 1127 { 1128 uint32_t cfpp; 1129 1130 cfpp = ATW_READ(sc, ATW_CFPP); 1131 cfpp &= ~ATW_CFPP_CFPMD; 1132 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1133 ATW_WRITE(sc, ATW_CFPP, cfpp); 1134 } 1135 1136 static void 1137 atw_tofs0_init(struct atw_softc *sc) 1138 { 1139 /* XXX I guess that the Cardbus clock is 22 MHz? 1140 * I am assuming that the role of ATW_TOFS0_USCNT is 1141 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1142 * very clear on this point. It says in the datasheet that it is 1143 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1144 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1145 * these values. These values are also the power-on default. 1146 */ 1147 ATW_WRITE(sc, ATW_TOFS0, 1148 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1149 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1150 } 1151 1152 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1153 static void 1154 atw_ifs_init(struct atw_softc *sc) 1155 { 1156 uint32_t ifst; 1157 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1158 * Go figure. 1159 */ 1160 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1161 __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1162 ATW_IFST_SIFS_MASK) | 1163 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1164 __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1165 1166 ATW_WRITE(sc, ATW_IFST, ifst); 1167 } 1168 1169 static void 1170 atw_response_times_init(struct atw_softc *sc) 1171 { 1172 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1173 * indicate that the MAC expects at least SIFS + MIRT microseconds 1174 * to pass after it transmits a frame that requires a response; 1175 * it waits at most SIFS + MART microseconds for the response. 1176 * Surely this is not the ACK timeout? 1177 */ 1178 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1179 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1180 } 1181 1182 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1183 * engines read and write baseband registers after Rx and before 1184 * Tx, respectively. 1185 */ 1186 static void 1187 atw_bbp_io_init(struct atw_softc *sc) 1188 { 1189 uint32_t mmiraddr2; 1190 1191 /* XXX The reference driver does this, but is it *really* 1192 * necessary? 1193 */ 1194 switch (sc->sc_rev) { 1195 case ATW_REVISION_AB: 1196 case ATW_REVISION_AF: 1197 mmiraddr2 = 0x0; 1198 break; 1199 default: 1200 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1201 mmiraddr2 &= 1202 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1203 break; 1204 } 1205 1206 switch (sc->sc_bbptype) { 1207 case ATW_BBPTYPE_INTERSIL: 1208 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1209 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1210 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1211 break; 1212 case ATW_BBPTYPE_MARVEL: 1213 /* TBD find out the Marvel settings. */ 1214 break; 1215 case ATW_BBPTYPE_RFMD: 1216 default: 1217 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1218 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1219 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1220 break; 1221 } 1222 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1223 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1224 } 1225 1226 /* 1227 * atw_init: [ ifnet interface function ] 1228 * 1229 * Initialize the interface. Must be called at splnet(). 1230 */ 1231 int 1232 atw_init(struct ifnet *ifp) 1233 { 1234 struct atw_softc *sc = ifp->if_softc; 1235 struct ieee80211com *ic = &sc->sc_ic; 1236 struct atw_txsoft *txs; 1237 struct atw_rxsoft *rxs; 1238 int i, error = 0; 1239 1240 if ((error = atw_enable(sc)) != 0) 1241 goto out; 1242 1243 /* 1244 * Cancel any pending I/O. This also resets. 1245 */ 1246 atw_stop(ifp, 0); 1247 1248 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1249 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1250 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1251 1252 atw_wcsr_init(sc); 1253 1254 atw_cmdr_init(sc); 1255 1256 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1257 * 1258 * XXX Set transmit power for ATIM, RTS, Beacon. 1259 */ 1260 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1261 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1262 1263 atw_tofs2_init(sc); 1264 1265 atw_nar_init(sc); 1266 1267 atw_txlmt_init(sc); 1268 1269 atw_test1_init(sc); 1270 1271 atw_rf_reset(sc); 1272 1273 atw_cfp_init(sc); 1274 1275 atw_tofs0_init(sc); 1276 1277 atw_ifs_init(sc); 1278 1279 /* XXX Fall asleep after one second of inactivity. 1280 * XXX A frame may only dribble in for 65536us. 1281 */ 1282 ATW_WRITE(sc, ATW_RMD, 1283 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1284 1285 atw_response_times_init(sc); 1286 1287 atw_bbp_io_init(sc); 1288 1289 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1290 1291 if ((error = atw_rf3000_init(sc)) != 0) 1292 goto out; 1293 1294 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1295 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1296 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1297 1298 /* 1299 * Initialize the transmit descriptor ring. 1300 */ 1301 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1302 for (i = 0; i < ATW_NTXDESC; i++) { 1303 sc->sc_txdescs[i].at_ctl = 0; 1304 /* no transmit chaining */ 1305 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1306 sc->sc_txdescs[i].at_buf2 = 1307 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1308 } 1309 /* use ring mode */ 1310 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1311 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1312 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1313 sc->sc_txfree = ATW_NTXDESC; 1314 sc->sc_txnext = 0; 1315 1316 /* 1317 * Initialize the transmit job descriptors. 1318 */ 1319 SIMPLEQ_INIT(&sc->sc_txfreeq); 1320 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1321 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1322 txs = &sc->sc_txsoft[i]; 1323 txs->txs_mbuf = NULL; 1324 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1325 } 1326 1327 /* 1328 * Initialize the receive descriptor and receive job 1329 * descriptor rings. 1330 */ 1331 for (i = 0; i < ATW_NRXDESC; i++) { 1332 rxs = &sc->sc_rxsoft[i]; 1333 if (rxs->rxs_mbuf == NULL) { 1334 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1335 aprint_error_dev(sc->sc_dev, "unable to allocate or map rx " 1336 "buffer %d, error = %d\n", 1337 i, error); 1338 /* 1339 * XXX Should attempt to run with fewer receive 1340 * XXX buffers instead of just failing. 1341 */ 1342 atw_rxdrain(sc); 1343 goto out; 1344 } 1345 } else 1346 atw_init_rxdesc(sc, i); 1347 } 1348 sc->sc_rxptr = 0; 1349 1350 /* 1351 * Initialize the interrupt mask and enable interrupts. 1352 */ 1353 /* normal interrupts */ 1354 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1355 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1356 1357 /* abnormal interrupts */ 1358 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1359 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1360 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1361 1362 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1363 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1364 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1365 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1366 ATW_INTR_TRT; 1367 1368 sc->sc_linkint_mask &= sc->sc_inten; 1369 sc->sc_rxint_mask &= sc->sc_inten; 1370 sc->sc_txint_mask &= sc->sc_inten; 1371 1372 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1373 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1374 1375 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1376 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1377 1378 /* 1379 * Give the transmit and receive rings to the ADM8211. 1380 */ 1381 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1382 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1383 1384 sc->sc_txthresh = 0; 1385 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1386 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1387 1388 /* common 802.11 configuration */ 1389 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1390 switch (ic->ic_opmode) { 1391 case IEEE80211_M_STA: 1392 break; 1393 case IEEE80211_M_AHDEMO: /* XXX */ 1394 case IEEE80211_M_IBSS: 1395 ic->ic_flags |= IEEE80211_F_IBSSON; 1396 /*FALLTHROUGH*/ 1397 case IEEE80211_M_HOSTAP: /* XXX */ 1398 break; 1399 case IEEE80211_M_MONITOR: /* XXX */ 1400 break; 1401 } 1402 1403 switch (ic->ic_opmode) { 1404 case IEEE80211_M_AHDEMO: 1405 case IEEE80211_M_HOSTAP: 1406 #ifndef IEEE80211_NO_HOSTAP 1407 ic->ic_bss->ni_intval = ic->ic_lintval; 1408 ic->ic_bss->ni_rssi = 0; 1409 ic->ic_bss->ni_rstamp = 0; 1410 #endif /* !IEEE80211_NO_HOSTAP */ 1411 break; 1412 default: /* XXX */ 1413 break; 1414 } 1415 1416 sc->sc_wepctl = 0; 1417 1418 atw_write_ssid(sc); 1419 atw_write_sup_rates(sc); 1420 atw_write_wep(sc); 1421 1422 ic->ic_state = IEEE80211_S_INIT; 1423 1424 /* 1425 * Set the receive filter. This will start the transmit and 1426 * receive processes. 1427 */ 1428 atw_filter_setup(sc); 1429 1430 /* 1431 * Start the receive process. 1432 */ 1433 ATW_WRITE(sc, ATW_RDR, 0x1); 1434 1435 /* 1436 * Note that the interface is now running. 1437 */ 1438 ifp->if_flags |= IFF_RUNNING; 1439 ifp->if_flags &= ~IFF_OACTIVE; 1440 1441 /* send no beacons, yet. */ 1442 atw_start_beacon(sc, 0); 1443 1444 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1445 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1446 else 1447 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1448 out: 1449 if (error) { 1450 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1451 sc->sc_tx_timer = 0; 1452 ifp->if_timer = 0; 1453 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1454 } 1455 #ifdef ATW_DEBUG 1456 atw_print_regs(sc, "end of init"); 1457 #endif /* ATW_DEBUG */ 1458 1459 return (error); 1460 } 1461 1462 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1463 * 0: MAC control of RF3000/Si4126. 1464 * 1465 * Applies power, or selects RF front-end? Sets reset condition. 1466 * 1467 * TBD support non-RFMD BBP, non-SiLabs synth. 1468 */ 1469 static void 1470 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1471 { 1472 if (enable) { 1473 ATW_WRITE(sc, ATW_SYNRF, 1474 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1475 DELAY(atw_bbp_io_enable_delay); 1476 } else { 1477 ATW_WRITE(sc, ATW_SYNRF, 0); 1478 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1479 } 1480 } 1481 1482 static int 1483 atw_tune(struct atw_softc *sc) 1484 { 1485 int rc; 1486 u_int chan; 1487 struct ieee80211com *ic = &sc->sc_ic; 1488 1489 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1490 if (chan == IEEE80211_CHAN_ANY) 1491 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1492 1493 if (chan == sc->sc_cur_chan) 1494 return 0; 1495 1496 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1497 sc->sc_cur_chan, chan)); 1498 1499 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1500 1501 atw_si4126_tune(sc, chan); 1502 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1503 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1504 chan); 1505 1506 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1507 DELAY(atw_nar_delay); 1508 ATW_WRITE(sc, ATW_RDR, 0x1); 1509 1510 if (rc == 0) { 1511 sc->sc_cur_chan = chan; 1512 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1513 htole16(ic->ic_curchan->ic_freq); 1514 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1515 htole16(ic->ic_curchan->ic_flags); 1516 } 1517 1518 return rc; 1519 } 1520 1521 #ifdef ATW_SYNDEBUG 1522 static void 1523 atw_si4126_print(struct atw_softc *sc) 1524 { 1525 struct ifnet *ifp = &sc->sc_if; 1526 u_int addr, val; 1527 1528 val = 0; 1529 1530 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1531 return; 1532 1533 for (addr = 0; addr <= 8; addr++) { 1534 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1535 if (atw_si4126_read(sc, addr, &val) == 0) { 1536 printf("<unknown> (quitting print-out)\n"); 1537 break; 1538 } 1539 printf("%05x\n", val); 1540 } 1541 } 1542 #endif /* ATW_SYNDEBUG */ 1543 1544 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1545 * 1546 * The RF/IF synthesizer produces two reference frequencies for 1547 * the RF2948B transceiver. The first frequency the RF2948B requires 1548 * is two times the so-called "intermediate frequency" (IF). Since 1549 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1550 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1551 * frequency required by the transceiver is the radio frequency 1552 * (RF). This is a superheterodyne transceiver; for f(chan) the 1553 * center frequency of the channel we are tuning, RF = f(chan) - 1554 * IF. 1555 * 1556 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1557 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1558 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1559 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1560 */ 1561 static void 1562 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1563 { 1564 u_int mhz; 1565 u_int R; 1566 u_int32_t gpio; 1567 u_int16_t gain; 1568 1569 #ifdef ATW_SYNDEBUG 1570 atw_si4126_print(sc); 1571 #endif /* ATW_SYNDEBUG */ 1572 1573 if (chan == 14) 1574 mhz = 2484; 1575 else 1576 mhz = 2412 + 5 * (chan - 1); 1577 1578 /* Tune IF to 748 MHz to suit the IF LO input of the 1579 * RF2494B, which is 2 x IF. No need to set an IF divider 1580 * because an IF in 526 MHz - 952 MHz is allowed. 1581 * 1582 * XIN is 44.000 MHz, so divide it by two to get allowable 1583 * range of 2-25 MHz. SiLabs tells me that this is not 1584 * strictly necessary. 1585 */ 1586 1587 if (atw_xindiv2) 1588 R = 44; 1589 else 1590 R = 88; 1591 1592 /* Power-up RF, IF synthesizers. */ 1593 atw_si4126_write(sc, SI4126_POWER, 1594 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1595 1596 /* set LPWR, too? */ 1597 atw_si4126_write(sc, SI4126_MAIN, 1598 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1599 1600 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1601 * set KP2 to 1. 1602 * 1603 * REFDIF This is different from the reference driver, which 1604 * always sets SI4126_GAIN to 0. 1605 */ 1606 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1607 1608 atw_si4126_write(sc, SI4126_GAIN, gain); 1609 1610 /* XIN = 44 MHz. 1611 * 1612 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1613 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1614 * 1615 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1616 * so that 1496/88 * 44 MHz = 748 MHz. 1617 */ 1618 atw_si4126_write(sc, SI4126_IFN, 1496); 1619 1620 atw_si4126_write(sc, SI4126_IFR, R); 1621 1622 #ifndef ATW_REFSLAVE 1623 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1624 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1625 * which has no RF1! 1626 */ 1627 atw_si4126_write(sc, SI4126_RF1R, R); 1628 1629 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1630 #endif 1631 1632 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1633 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1634 * Now let's multiply it to mhz. So mhz - IF = N. 1635 */ 1636 atw_si4126_write(sc, SI4126_RF2R, R); 1637 1638 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1639 1640 /* wait 100us from power-up for RF, IF to settle */ 1641 DELAY(100); 1642 1643 gpio = ATW_READ(sc, ATW_GPIO); 1644 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1645 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1646 1647 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1648 /* Set a Prism RF front-end to a special mode for channel 14? 1649 * 1650 * Apparently the SMC2635W needs this, although I don't think 1651 * it has a Prism RF. 1652 */ 1653 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1654 } 1655 ATW_WRITE(sc, ATW_GPIO, gpio); 1656 1657 #ifdef ATW_SYNDEBUG 1658 atw_si4126_print(sc); 1659 #endif /* ATW_SYNDEBUG */ 1660 } 1661 1662 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1663 * diversity. 1664 * 1665 * !!! 1666 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1667 * !!! 1668 */ 1669 static int 1670 atw_rf3000_init(struct atw_softc *sc) 1671 { 1672 int rc = 0; 1673 1674 atw_bbp_io_enable(sc, 1); 1675 1676 /* CCA is acquisition sensitive */ 1677 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1678 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1679 1680 if (rc != 0) 1681 goto out; 1682 1683 /* enable diversity */ 1684 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1685 1686 if (rc != 0) 1687 goto out; 1688 1689 /* sensible setting from a binary-only driver */ 1690 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1691 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1692 1693 if (rc != 0) 1694 goto out; 1695 1696 /* magic from a binary-only driver */ 1697 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1698 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1699 1700 if (rc != 0) 1701 goto out; 1702 1703 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1704 1705 if (rc != 0) 1706 goto out; 1707 1708 /* XXX Reference driver remarks that Abocom sets this to 50. 1709 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1710 * in the "reserved" area of register RF3000_OPTIONS1. 1711 */ 1712 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1713 1714 if (rc != 0) 1715 goto out; 1716 1717 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1718 1719 if (rc != 0) 1720 goto out; 1721 1722 out: 1723 atw_bbp_io_enable(sc, 0); 1724 return rc; 1725 } 1726 1727 #ifdef ATW_BBPDEBUG 1728 static void 1729 atw_rf3000_print(struct atw_softc *sc) 1730 { 1731 struct ifnet *ifp = &sc->sc_if; 1732 u_int addr, val; 1733 1734 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1735 return; 1736 1737 for (addr = 0x01; addr <= 0x15; addr++) { 1738 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1739 if (atw_rf3000_read(sc, addr, &val) != 0) { 1740 printf("<unknown> (quitting print-out)\n"); 1741 break; 1742 } 1743 printf("%08x\n", val); 1744 } 1745 } 1746 #endif /* ATW_BBPDEBUG */ 1747 1748 /* Set the power settings on the BBP for channel `chan'. */ 1749 static int 1750 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1751 { 1752 int rc = 0; 1753 u_int32_t reg; 1754 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1755 1756 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1757 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1758 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1759 1760 /* odd channels: LSB, even channels: MSB */ 1761 if (chan % 2 == 1) { 1762 txpower &= 0xFF; 1763 lpf_cutoff &= 0xFF; 1764 lna_gs_thresh &= 0xFF; 1765 } else { 1766 txpower >>= 8; 1767 lpf_cutoff >>= 8; 1768 lna_gs_thresh >>= 8; 1769 } 1770 1771 #ifdef ATW_BBPDEBUG 1772 atw_rf3000_print(sc); 1773 #endif /* ATW_BBPDEBUG */ 1774 1775 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1776 "lna_gs_thresh %02x\n", 1777 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1778 1779 atw_bbp_io_enable(sc, 1); 1780 1781 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1782 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1783 goto out; 1784 1785 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1786 goto out; 1787 1788 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1789 goto out; 1790 1791 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1792 1793 if (rc != 0) 1794 goto out; 1795 1796 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1797 1798 if (rc != 0) 1799 goto out; 1800 1801 #ifdef ATW_BBPDEBUG 1802 atw_rf3000_print(sc); 1803 #endif /* ATW_BBPDEBUG */ 1804 1805 out: 1806 atw_bbp_io_enable(sc, 0); 1807 1808 /* set beacon, rts, atim transmit power */ 1809 reg = ATW_READ(sc, ATW_PLCPHD); 1810 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1811 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1812 ATW_PLCPHD_SERVICE_MASK); 1813 ATW_WRITE(sc, ATW_PLCPHD, reg); 1814 DELAY(atw_plcphd_delay); 1815 1816 return rc; 1817 } 1818 1819 /* Write a register on the RF3000 baseband processor using the 1820 * registers provided by the ADM8211 for this purpose. 1821 * 1822 * Return 0 on success. 1823 */ 1824 static int 1825 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1826 { 1827 u_int32_t reg; 1828 int i; 1829 1830 reg = sc->sc_bbpctl_wr | 1831 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1832 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1833 1834 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1835 ATW_WRITE(sc, ATW_BBPCTL, reg); 1836 DELAY(2 * atw_pseudo_milli); 1837 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1838 break; 1839 } 1840 1841 if (i < 0) { 1842 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1843 return ETIMEDOUT; 1844 } 1845 return 0; 1846 } 1847 1848 /* Read a register on the RF3000 baseband processor using the registers 1849 * the ADM8211 provides for this purpose. 1850 * 1851 * The 7-bit register address is addr. Record the 8-bit data in the register 1852 * in *val. 1853 * 1854 * Return 0 on success. 1855 * 1856 * XXX This does not seem to work. The ADM8211 must require more or 1857 * different magic to read the chip than to write it. Possibly some 1858 * of the magic I have derived from a binary-only driver concerns 1859 * the "chip address" (see the RF3000 manual). 1860 */ 1861 #ifdef ATW_BBPDEBUG 1862 static int 1863 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1864 { 1865 u_int32_t reg; 1866 int i; 1867 1868 for (i = 1000; --i >= 0; ) { 1869 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1870 break; 1871 DELAY(100); 1872 } 1873 1874 if (i < 0) { 1875 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1876 device_xname(sc->sc_dev)); 1877 return ETIMEDOUT; 1878 } 1879 1880 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1881 1882 ATW_WRITE(sc, ATW_BBPCTL, reg); 1883 1884 for (i = 1000; --i >= 0; ) { 1885 DELAY(100); 1886 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1887 break; 1888 } 1889 1890 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1891 1892 if (i < 0) { 1893 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1894 device_xname(sc->sc_dev), reg); 1895 return ETIMEDOUT; 1896 } 1897 if (val != NULL) 1898 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1899 return 0; 1900 } 1901 #endif /* ATW_BBPDEBUG */ 1902 1903 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1904 * provided by the ADM8211 for that purpose. 1905 * 1906 * val is 18 bits of data, and val is the 4-bit address of the register. 1907 * 1908 * Return 0 on success. 1909 */ 1910 static void 1911 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1912 { 1913 uint32_t bits, mask, reg; 1914 const int nbits = 22; 1915 1916 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1917 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1918 1919 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1920 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1921 1922 reg = ATW_SYNRF_SELSYN; 1923 /* reference driver: reset Si4126 serial bus to initial 1924 * conditions? 1925 */ 1926 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1927 ATW_WRITE(sc, ATW_SYNRF, reg); 1928 1929 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1930 if ((bits & mask) != 0) 1931 reg |= ATW_SYNRF_SYNDATA; 1932 else 1933 reg &= ~ATW_SYNRF_SYNDATA; 1934 ATW_WRITE(sc, ATW_SYNRF, reg); 1935 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1936 ATW_WRITE(sc, ATW_SYNRF, reg); 1937 } 1938 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1939 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1940 } 1941 1942 /* Read 18-bit data from the 4-bit address addr in Si4126 1943 * RF synthesizer and write the data to *val. Return 0 on success. 1944 * 1945 * XXX This does not seem to work. The ADM8211 must require more or 1946 * different magic to read the chip than to write it. 1947 */ 1948 #ifdef ATW_SYNDEBUG 1949 static int 1950 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1951 { 1952 u_int32_t reg; 1953 int i; 1954 1955 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1956 1957 for (i = 1000; --i >= 0; ) { 1958 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1959 break; 1960 DELAY(100); 1961 } 1962 1963 if (i < 0) { 1964 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1965 device_xname(sc->sc_dev)); 1966 return ETIMEDOUT; 1967 } 1968 1969 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1970 1971 ATW_WRITE(sc, ATW_SYNCTL, reg); 1972 1973 for (i = 1000; --i >= 0; ) { 1974 DELAY(100); 1975 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1976 break; 1977 } 1978 1979 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1980 1981 if (i < 0) { 1982 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1983 device_xname(sc->sc_dev), reg); 1984 return ETIMEDOUT; 1985 } 1986 if (val != NULL) 1987 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1988 ATW_SYNCTL_DATA_MASK); 1989 return 0; 1990 } 1991 #endif /* ATW_SYNDEBUG */ 1992 1993 /* XXX is the endianness correct? test. */ 1994 #define atw_calchash(addr) \ 1995 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1996 1997 /* 1998 * atw_filter_setup: 1999 * 2000 * Set the ADM8211's receive filter. 2001 */ 2002 static void 2003 atw_filter_setup(struct atw_softc *sc) 2004 { 2005 struct ieee80211com *ic = &sc->sc_ic; 2006 struct ethercom *ec = &sc->sc_ec; 2007 struct ifnet *ifp = &sc->sc_if; 2008 int hash; 2009 u_int32_t hashes[2]; 2010 struct ether_multi *enm; 2011 struct ether_multistep step; 2012 2013 /* According to comments in tlp_al981_filter_setup 2014 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2015 * multicast filter to be set while it is running. Hopefully 2016 * the ADM8211 is not the same! 2017 */ 2018 if ((ifp->if_flags & IFF_RUNNING) != 0) 2019 atw_idle(sc, ATW_NAR_SR); 2020 2021 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 2022 ifp->if_flags &= ~IFF_ALLMULTI; 2023 2024 /* XXX in scan mode, do not filter packets. Maybe this is 2025 * unnecessary. 2026 */ 2027 if (ic->ic_state == IEEE80211_S_SCAN || 2028 (ifp->if_flags & IFF_PROMISC) != 0) { 2029 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2030 goto allmulti; 2031 } 2032 2033 hashes[0] = hashes[1] = 0x0; 2034 2035 /* 2036 * Program the 64-bit multicast hash filter. 2037 */ 2038 ETHER_FIRST_MULTI(step, ec, enm); 2039 while (enm != NULL) { 2040 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2041 ETHER_ADDR_LEN) != 0) 2042 goto allmulti; 2043 2044 hash = atw_calchash(enm->enm_addrlo); 2045 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2046 ETHER_NEXT_MULTI(step, enm); 2047 sc->sc_opmode |= ATW_NAR_MM; 2048 } 2049 ifp->if_flags &= ~IFF_ALLMULTI; 2050 goto setit; 2051 2052 allmulti: 2053 sc->sc_opmode |= ATW_NAR_MM; 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = 0xffffffff; 2056 2057 setit: 2058 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2059 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2060 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2061 DELAY(atw_nar_delay); 2062 ATW_WRITE(sc, ATW_RDR, 0x1); 2063 2064 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2065 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2066 } 2067 2068 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2069 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2070 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2071 * no beacon with the preferred BSSID and SSID in the number of 2072 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2073 */ 2074 static void 2075 atw_write_bssid(struct atw_softc *sc) 2076 { 2077 struct ieee80211com *ic = &sc->sc_ic; 2078 u_int8_t *bssid; 2079 2080 bssid = ic->ic_bss->ni_bssid; 2081 2082 ATW_WRITE(sc, ATW_BSSID0, 2083 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2084 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2085 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2086 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2087 2088 ATW_WRITE(sc, ATW_ABDA1, 2089 (ATW_READ(sc, ATW_ABDA1) & 2090 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2091 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2092 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2093 2094 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2095 ether_sprintf(sc->sc_bssid))); 2096 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2097 2098 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2099 } 2100 2101 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2102 * 16-bit word. 2103 */ 2104 static void 2105 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2106 { 2107 u_int i; 2108 u_int8_t *ptr; 2109 2110 memcpy(&sc->sc_sram[ofs], buf, buflen); 2111 2112 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2113 2114 KASSERT(buflen + ofs <= sc->sc_sramlen); 2115 2116 ptr = &sc->sc_sram[ofs]; 2117 2118 for (i = 0; i < buflen; i += 2) { 2119 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2120 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2121 DELAY(atw_writewep_delay); 2122 2123 ATW_WRITE(sc, ATW_WESK, 2124 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2125 DELAY(atw_writewep_delay); 2126 } 2127 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2128 2129 if (sc->sc_if.if_flags & IFF_DEBUG) { 2130 int n_octets = 0; 2131 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2132 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2133 for (i = 0; i < buflen; i++) { 2134 printf(" %02x", ptr[i]); 2135 if (++n_octets % 24 == 0) 2136 printf("\n"); 2137 } 2138 if (n_octets % 24 != 0) 2139 printf("\n"); 2140 } 2141 } 2142 2143 static int 2144 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2145 { 2146 struct atw_softc *sc = ic->ic_ifp->if_softc; 2147 u_int keyix = k->wk_keyix; 2148 2149 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2150 2151 if (keyix >= IEEE80211_WEP_NKID) 2152 return 0; 2153 if (k->wk_keylen != 0) 2154 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2155 2156 return 1; 2157 } 2158 2159 static int 2160 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2161 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2162 { 2163 struct atw_softc *sc = ic->ic_ifp->if_softc; 2164 2165 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2166 2167 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2168 return 0; 2169 2170 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2171 2172 return 1; 2173 } 2174 2175 static void 2176 atw_key_update_begin(struct ieee80211com *ic) 2177 { 2178 #ifdef ATW_DEBUG 2179 struct ifnet *ifp = ic->ic_ifp; 2180 struct atw_softc *sc = ifp->if_softc; 2181 #endif 2182 2183 DPRINTF(sc, ("%s:\n", __func__)); 2184 } 2185 2186 static void 2187 atw_key_update_end(struct ieee80211com *ic) 2188 { 2189 struct ifnet *ifp = ic->ic_ifp; 2190 struct atw_softc *sc = ifp->if_softc; 2191 2192 DPRINTF(sc, ("%s:\n", __func__)); 2193 2194 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2195 return; 2196 if (ATW_IS_ENABLED(sc) == 0) 2197 return; 2198 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2199 atw_write_wep(sc); 2200 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2201 DELAY(atw_nar_delay); 2202 ATW_WRITE(sc, ATW_RDR, 0x1); 2203 } 2204 2205 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2206 static void 2207 atw_write_wep(struct atw_softc *sc) 2208 { 2209 #if 0 2210 struct ieee80211com *ic = &sc->sc_ic; 2211 u_int32_t reg; 2212 int i; 2213 #endif 2214 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2215 u_int8_t buf[IEEE80211_WEP_NKID] 2216 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2217 2218 sc->sc_wepctl = 0; 2219 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2220 2221 memset(&buf[0][0], 0, sizeof(buf)); 2222 2223 #if 0 2224 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2225 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2226 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2227 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2228 buf[i][1] = ATW_WEP_ENABLED; 2229 } else { 2230 buf[i][1] = 0; 2231 continue; 2232 } 2233 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2234 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2235 ic->ic_nw_keys[i].wk_keylen - 1); 2236 } 2237 2238 reg = ATW_READ(sc, ATW_MACTEST); 2239 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2240 reg &= ~ATW_MACTEST_KEYID_MASK; 2241 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2242 ATW_WRITE(sc, ATW_MACTEST, reg); 2243 2244 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2245 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2246 2247 switch (sc->sc_rev) { 2248 case ATW_REVISION_AB: 2249 case ATW_REVISION_AF: 2250 /* Bypass WEP on Rx. */ 2251 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2252 break; 2253 default: 2254 break; 2255 } 2256 #endif 2257 2258 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2259 sizeof(buf)); 2260 2261 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2262 } 2263 2264 static void 2265 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2266 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2267 { 2268 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2269 2270 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2271 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2272 return; 2273 2274 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2275 2276 switch (subtype) { 2277 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2278 case IEEE80211_FC0_SUBTYPE_BEACON: 2279 if (ic->ic_opmode == IEEE80211_M_IBSS && 2280 ic->ic_state == IEEE80211_S_RUN) { 2281 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2282 (void)ieee80211_ibss_merge(ni); 2283 } 2284 break; 2285 default: 2286 break; 2287 } 2288 return; 2289 } 2290 2291 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2292 * In ad hoc mode, the SSID is written to the beacons sent by the 2293 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2294 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2295 * indications. 2296 */ 2297 static void 2298 atw_write_ssid(struct atw_softc *sc) 2299 { 2300 struct ieee80211com *ic = &sc->sc_ic; 2301 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2302 * it only expects the element length, not its ID. 2303 */ 2304 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2305 2306 memset(buf, 0, sizeof(buf)); 2307 buf[0] = ic->ic_bss->ni_esslen; 2308 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2309 2310 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2311 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2312 } 2313 2314 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2315 * In ad hoc mode, the supported rates are written to beacons sent by the 2316 * ADM8211. 2317 */ 2318 static void 2319 atw_write_sup_rates(struct atw_softc *sc) 2320 { 2321 struct ieee80211com *ic = &sc->sc_ic; 2322 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2323 * supported rates 2324 */ 2325 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2326 2327 memset(buf, 0, sizeof(buf)); 2328 2329 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2330 2331 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2332 ic->ic_bss->ni_rates.rs_nrates); 2333 2334 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2335 } 2336 2337 /* Start/stop sending beacons. */ 2338 void 2339 atw_start_beacon(struct atw_softc *sc, int start) 2340 { 2341 struct ieee80211com *ic = &sc->sc_ic; 2342 uint16_t chan; 2343 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2344 size_t len; 2345 2346 if (ATW_IS_ENABLED(sc) == 0) 2347 return; 2348 2349 /* start beacons */ 2350 len = sizeof(struct ieee80211_frame) + 2351 8 /* timestamp */ + 2 /* beacon interval */ + 2352 2 /* capability info */ + 2353 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2354 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2355 3 /* DS parameters */ + 2356 IEEE80211_CRC_LEN; 2357 2358 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2359 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2360 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2361 2362 ATW_WRITE(sc, ATW_BCNT, bcnt); 2363 ATW_WRITE(sc, ATW_CAP1, cap1); 2364 2365 if (!start) 2366 return; 2367 2368 /* TBD use ni_capinfo */ 2369 2370 capinfo = 0; 2371 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2372 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2373 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2374 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2375 2376 switch (ic->ic_opmode) { 2377 case IEEE80211_M_IBSS: 2378 len += 4; /* IBSS parameters */ 2379 capinfo |= IEEE80211_CAPINFO_IBSS; 2380 break; 2381 case IEEE80211_M_HOSTAP: 2382 /* XXX 6-byte minimum TIM */ 2383 len += atw_beacon_len_adjust; 2384 capinfo |= IEEE80211_CAPINFO_ESS; 2385 break; 2386 default: 2387 return; 2388 } 2389 2390 /* set listen interval 2391 * XXX do software units agree w/ hardware? 2392 */ 2393 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2394 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2395 2396 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2397 2398 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2399 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2400 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2401 2402 ATW_WRITE(sc, ATW_BCNT, bcnt); 2403 ATW_WRITE(sc, ATW_BPLI, bpli); 2404 ATW_WRITE(sc, ATW_CAP0, cap0); 2405 ATW_WRITE(sc, ATW_CAP1, cap1); 2406 2407 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2408 device_xname(sc->sc_dev), bcnt)); 2409 2410 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2411 device_xname(sc->sc_dev), cap1)); 2412 } 2413 2414 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2415 static inline uint32_t 2416 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2417 { 2418 /* Following the reference driver's lead, I compute 2419 * 2420 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2421 * 2422 * without using 64-bit arithmetic, using the following 2423 * relationship: 2424 * 2425 * (0x100000000 * H + L) % m 2426 * = ((0x100000000 % m) * H + L) % m 2427 * = (((0xffffffff + 1) % m) * H + L) % m 2428 * = ((0xffffffff % m + 1 % m) * H + L) % m 2429 * = ((0xffffffff % m + 1) * H + L) % m 2430 */ 2431 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2432 } 2433 2434 static uint64_t 2435 atw_get_tsft(struct atw_softc *sc) 2436 { 2437 int i; 2438 uint32_t tsfth, tsftl; 2439 for (i = 0; i < 2; i++) { 2440 tsfth = ATW_READ(sc, ATW_TSFTH); 2441 tsftl = ATW_READ(sc, ATW_TSFTL); 2442 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2443 break; 2444 } 2445 return ((uint64_t)tsfth << 32) | tsftl; 2446 } 2447 2448 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2449 * the ieee80211com. 2450 * 2451 * Predict the next target beacon transmission time (TBTT) and 2452 * write it to the ADM8211. 2453 */ 2454 static void 2455 atw_predict_beacon(struct atw_softc *sc) 2456 { 2457 #define TBTTOFS 20 /* TU */ 2458 2459 struct ieee80211com *ic = &sc->sc_ic; 2460 uint64_t tsft; 2461 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2462 union { 2463 uint64_t word; 2464 uint8_t tstamp[8]; 2465 } u; 2466 2467 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2468 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2469 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2470 tsft = atw_get_tsft(sc); 2471 u.word = htole64(tsft); 2472 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2473 sizeof(ic->ic_bss->ni_tstamp)); 2474 } else 2475 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2476 2477 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2478 2479 tsftl = tsft & 0xFFFFFFFF; 2480 tsfth = tsft >> 32; 2481 2482 /* We sent/received the last beacon `past' microseconds 2483 * after the interval divided the TSF timer. 2484 */ 2485 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2486 2487 /* Skip ten beacons so that the TBTT cannot pass before 2488 * we've programmed it. Ten is an arbitrary number. 2489 */ 2490 tbtt = past_even + ival * 10; 2491 2492 ATW_WRITE(sc, ATW_TOFS1, 2493 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2494 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2495 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2496 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2497 #undef TBTTOFS 2498 } 2499 2500 static void 2501 atw_next_scan(void *arg) 2502 { 2503 struct atw_softc *sc = arg; 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 int s; 2506 2507 /* don't call atw_start w/o network interrupts blocked */ 2508 s = splnet(); 2509 if (ic->ic_state == IEEE80211_S_SCAN) 2510 ieee80211_next_scan(ic); 2511 splx(s); 2512 } 2513 2514 /* Synchronize the hardware state with the software state. */ 2515 static int 2516 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2517 { 2518 struct ifnet *ifp = ic->ic_ifp; 2519 struct atw_softc *sc = ifp->if_softc; 2520 enum ieee80211_state ostate; 2521 int error = 0; 2522 2523 ostate = ic->ic_state; 2524 callout_stop(&sc->sc_scan_ch); 2525 2526 switch (nstate) { 2527 case IEEE80211_S_AUTH: 2528 case IEEE80211_S_ASSOC: 2529 atw_write_bssid(sc); 2530 error = atw_tune(sc); 2531 break; 2532 case IEEE80211_S_INIT: 2533 callout_stop(&sc->sc_scan_ch); 2534 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2535 atw_start_beacon(sc, 0); 2536 break; 2537 case IEEE80211_S_SCAN: 2538 error = atw_tune(sc); 2539 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2540 atw_next_scan, sc); 2541 break; 2542 case IEEE80211_S_RUN: 2543 error = atw_tune(sc); 2544 atw_write_bssid(sc); 2545 atw_write_ssid(sc); 2546 atw_write_sup_rates(sc); 2547 2548 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2549 ic->ic_opmode == IEEE80211_M_MONITOR) 2550 break; 2551 2552 /* set listen interval 2553 * XXX do software units agree w/ hardware? 2554 */ 2555 ATW_WRITE(sc, ATW_BPLI, 2556 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2557 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2558 ATW_BPLI_LI_MASK)); 2559 2560 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2561 ATW_READ(sc, ATW_BPLI))); 2562 2563 atw_predict_beacon(sc); 2564 2565 switch (ic->ic_opmode) { 2566 case IEEE80211_M_AHDEMO: 2567 case IEEE80211_M_HOSTAP: 2568 case IEEE80211_M_IBSS: 2569 atw_start_beacon(sc, 1); 2570 break; 2571 case IEEE80211_M_MONITOR: 2572 case IEEE80211_M_STA: 2573 break; 2574 } 2575 2576 break; 2577 } 2578 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2579 } 2580 2581 /* 2582 * atw_add_rxbuf: 2583 * 2584 * Add a receive buffer to the indicated descriptor. 2585 */ 2586 int 2587 atw_add_rxbuf(struct atw_softc *sc, int idx) 2588 { 2589 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2590 struct mbuf *m; 2591 int error; 2592 2593 MGETHDR(m, M_DONTWAIT, MT_DATA); 2594 if (m == NULL) 2595 return (ENOBUFS); 2596 2597 MCLGET(m, M_DONTWAIT); 2598 if ((m->m_flags & M_EXT) == 0) { 2599 m_freem(m); 2600 return (ENOBUFS); 2601 } 2602 2603 if (rxs->rxs_mbuf != NULL) 2604 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2605 2606 rxs->rxs_mbuf = m; 2607 2608 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2609 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2610 BUS_DMA_READ|BUS_DMA_NOWAIT); 2611 if (error) { 2612 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2613 idx, error); 2614 panic("atw_add_rxbuf"); /* XXX */ 2615 } 2616 2617 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2618 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2619 2620 atw_init_rxdesc(sc, idx); 2621 2622 return (0); 2623 } 2624 2625 /* 2626 * Release any queued transmit buffers. 2627 */ 2628 void 2629 atw_txdrain(struct atw_softc *sc) 2630 { 2631 struct atw_txsoft *txs; 2632 2633 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2634 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2635 if (txs->txs_mbuf != NULL) { 2636 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2637 m_freem(txs->txs_mbuf); 2638 txs->txs_mbuf = NULL; 2639 } 2640 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2641 sc->sc_txfree += txs->txs_ndescs; 2642 } 2643 2644 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2645 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2646 sc->sc_txfree != ATW_NTXDESC)); 2647 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2648 sc->sc_tx_timer = 0; 2649 } 2650 2651 /* 2652 * atw_stop: [ ifnet interface function ] 2653 * 2654 * Stop transmission on the interface. 2655 */ 2656 void 2657 atw_stop(struct ifnet *ifp, int disable) 2658 { 2659 struct atw_softc *sc = ifp->if_softc; 2660 struct ieee80211com *ic = &sc->sc_ic; 2661 2662 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2663 2664 /* Disable interrupts. */ 2665 ATW_WRITE(sc, ATW_IER, 0); 2666 2667 /* Stop the transmit and receive processes. */ 2668 sc->sc_opmode = 0; 2669 ATW_WRITE(sc, ATW_NAR, 0); 2670 DELAY(atw_nar_delay); 2671 ATW_WRITE(sc, ATW_TDBD, 0); 2672 ATW_WRITE(sc, ATW_TDBP, 0); 2673 ATW_WRITE(sc, ATW_RDB, 0); 2674 2675 atw_txdrain(sc); 2676 2677 /* 2678 * Mark the interface down and cancel the watchdog timer. 2679 */ 2680 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2681 sc->sc_tx_timer = 0; 2682 ifp->if_timer = 0; 2683 2684 if (disable) { 2685 atw_rxdrain(sc); 2686 atw_disable(sc); 2687 } else 2688 atw_reset(sc); 2689 } 2690 2691 /* 2692 * atw_rxdrain: 2693 * 2694 * Drain the receive queue. 2695 */ 2696 void 2697 atw_rxdrain(struct atw_softc *sc) 2698 { 2699 struct atw_rxsoft *rxs; 2700 int i; 2701 2702 for (i = 0; i < ATW_NRXDESC; i++) { 2703 rxs = &sc->sc_rxsoft[i]; 2704 if (rxs->rxs_mbuf == NULL) 2705 continue; 2706 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2707 m_freem(rxs->rxs_mbuf); 2708 rxs->rxs_mbuf = NULL; 2709 } 2710 } 2711 2712 /* 2713 * atw_detach: 2714 * 2715 * Detach an ADM8211 interface. 2716 */ 2717 int 2718 atw_detach(struct atw_softc *sc) 2719 { 2720 struct ifnet *ifp = &sc->sc_if; 2721 struct atw_rxsoft *rxs; 2722 struct atw_txsoft *txs; 2723 int i; 2724 2725 /* 2726 * Succeed now if there isn't any work to do. 2727 */ 2728 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2729 return (0); 2730 2731 pmf_device_deregister(sc->sc_dev); 2732 2733 callout_stop(&sc->sc_scan_ch); 2734 2735 ieee80211_ifdetach(&sc->sc_ic); 2736 if_detach(ifp); 2737 2738 for (i = 0; i < ATW_NRXDESC; i++) { 2739 rxs = &sc->sc_rxsoft[i]; 2740 if (rxs->rxs_mbuf != NULL) { 2741 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2742 m_freem(rxs->rxs_mbuf); 2743 rxs->rxs_mbuf = NULL; 2744 } 2745 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2746 } 2747 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2748 txs = &sc->sc_txsoft[i]; 2749 if (txs->txs_mbuf != NULL) { 2750 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2751 m_freem(txs->txs_mbuf); 2752 txs->txs_mbuf = NULL; 2753 } 2754 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2755 } 2756 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2757 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2758 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2759 sizeof(struct atw_control_data)); 2760 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2761 2762 if (sc->sc_srom) 2763 free(sc->sc_srom, M_DEVBUF); 2764 2765 atw_evcnt_detach(sc); 2766 2767 return (0); 2768 } 2769 2770 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2771 bool 2772 atw_shutdown(device_t self, int flags) 2773 { 2774 struct atw_softc *sc = device_private(self); 2775 2776 atw_stop(&sc->sc_if, 1); 2777 return true; 2778 } 2779 2780 int 2781 atw_intr(void *arg) 2782 { 2783 struct atw_softc *sc = arg; 2784 struct ifnet *ifp = &sc->sc_if; 2785 u_int32_t status, rxstatus, txstatus, linkstatus; 2786 int handled = 0, txthresh; 2787 2788 #ifdef DEBUG 2789 if (ATW_IS_ENABLED(sc) == 0) 2790 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2791 #endif 2792 2793 /* 2794 * If the interface isn't running, the interrupt couldn't 2795 * possibly have come from us. 2796 */ 2797 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2798 !device_is_active(sc->sc_dev)) 2799 return (0); 2800 2801 for (;;) { 2802 status = ATW_READ(sc, ATW_STSR); 2803 2804 if (status) 2805 ATW_WRITE(sc, ATW_STSR, status); 2806 2807 #ifdef ATW_DEBUG 2808 #define PRINTINTR(flag) do { \ 2809 if ((status & flag) != 0) { \ 2810 printf("%s" #flag, delim); \ 2811 delim = ","; \ 2812 } \ 2813 } while (0) 2814 2815 if (atw_debug > 1 && status) { 2816 const char *delim = "<"; 2817 2818 printf("%s: reg[STSR] = %x", 2819 device_xname(sc->sc_dev), status); 2820 2821 PRINTINTR(ATW_INTR_FBE); 2822 PRINTINTR(ATW_INTR_LINKOFF); 2823 PRINTINTR(ATW_INTR_LINKON); 2824 PRINTINTR(ATW_INTR_RCI); 2825 PRINTINTR(ATW_INTR_RDU); 2826 PRINTINTR(ATW_INTR_REIS); 2827 PRINTINTR(ATW_INTR_RPS); 2828 PRINTINTR(ATW_INTR_TCI); 2829 PRINTINTR(ATW_INTR_TDU); 2830 PRINTINTR(ATW_INTR_TLT); 2831 PRINTINTR(ATW_INTR_TPS); 2832 PRINTINTR(ATW_INTR_TRT); 2833 PRINTINTR(ATW_INTR_TUF); 2834 PRINTINTR(ATW_INTR_BCNTC); 2835 PRINTINTR(ATW_INTR_ATIME); 2836 PRINTINTR(ATW_INTR_TBTT); 2837 PRINTINTR(ATW_INTR_TSCZ); 2838 PRINTINTR(ATW_INTR_TSFTF); 2839 printf(">\n"); 2840 } 2841 #undef PRINTINTR 2842 #endif /* ATW_DEBUG */ 2843 2844 if ((status & sc->sc_inten) == 0) 2845 break; 2846 2847 handled = 1; 2848 2849 rxstatus = status & sc->sc_rxint_mask; 2850 txstatus = status & sc->sc_txint_mask; 2851 linkstatus = status & sc->sc_linkint_mask; 2852 2853 if (linkstatus) { 2854 atw_linkintr(sc, linkstatus); 2855 } 2856 2857 if (rxstatus) { 2858 /* Grab any new packets. */ 2859 atw_rxintr(sc); 2860 2861 if (rxstatus & ATW_INTR_RDU) { 2862 printf("%s: receive ring overrun\n", 2863 device_xname(sc->sc_dev)); 2864 /* Get the receive process going again. */ 2865 ATW_WRITE(sc, ATW_RDR, 0x1); 2866 break; 2867 } 2868 } 2869 2870 if (txstatus) { 2871 /* Sweep up transmit descriptors. */ 2872 atw_txintr(sc); 2873 2874 if (txstatus & ATW_INTR_TLT) { 2875 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2876 device_xname(sc->sc_dev))); 2877 } 2878 2879 if (txstatus & ATW_INTR_TRT) { 2880 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2881 device_xname(sc->sc_dev))); 2882 } 2883 2884 /* If Tx under-run, increase our transmit threshold 2885 * if another is available. 2886 */ 2887 txthresh = sc->sc_txthresh + 1; 2888 if ((txstatus & ATW_INTR_TUF) && 2889 sc->sc_txth[txthresh].txth_name != NULL) { 2890 /* Idle the transmit process. */ 2891 atw_idle(sc, ATW_NAR_ST); 2892 2893 sc->sc_txthresh = txthresh; 2894 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2895 sc->sc_opmode |= 2896 sc->sc_txth[txthresh].txth_opmode; 2897 printf("%s: transmit underrun; new " 2898 "threshold: %s\n", device_xname(sc->sc_dev), 2899 sc->sc_txth[txthresh].txth_name); 2900 2901 /* Set the new threshold and restart 2902 * the transmit process. 2903 */ 2904 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2905 DELAY(atw_nar_delay); 2906 ATW_WRITE(sc, ATW_RDR, 0x1); 2907 /* XXX Log every Nth underrun from 2908 * XXX now on? 2909 */ 2910 } 2911 } 2912 2913 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2914 if (status & ATW_INTR_TPS) 2915 printf("%s: transmit process stopped\n", 2916 device_xname(sc->sc_dev)); 2917 if (status & ATW_INTR_RPS) 2918 printf("%s: receive process stopped\n", 2919 device_xname(sc->sc_dev)); 2920 (void)atw_init(ifp); 2921 break; 2922 } 2923 2924 if (status & ATW_INTR_FBE) { 2925 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2926 (void)atw_init(ifp); 2927 break; 2928 } 2929 2930 /* 2931 * Not handled: 2932 * 2933 * Transmit buffer unavailable -- normal 2934 * condition, nothing to do, really. 2935 * 2936 * Early receive interrupt -- not available on 2937 * all chips, we just use RI. We also only 2938 * use single-segment receive DMA, so this 2939 * is mostly useless. 2940 * 2941 * TBD others 2942 */ 2943 } 2944 2945 /* Try to get more packets going. */ 2946 atw_start(ifp); 2947 2948 return (handled); 2949 } 2950 2951 /* 2952 * atw_idle: 2953 * 2954 * Cause the transmit and/or receive processes to go idle. 2955 * 2956 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2957 * process in STSR if I clear SR or ST after the process has already 2958 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2959 * do not seem to be too reliable. Perhaps I have the sense of the 2960 * Rx bits switched with the Tx bits? 2961 */ 2962 void 2963 atw_idle(struct atw_softc *sc, u_int32_t bits) 2964 { 2965 u_int32_t ackmask = 0, opmode, stsr, test0; 2966 int i, s; 2967 2968 s = splnet(); 2969 2970 opmode = sc->sc_opmode & ~bits; 2971 2972 if (bits & ATW_NAR_SR) 2973 ackmask |= ATW_INTR_RPS; 2974 2975 if (bits & ATW_NAR_ST) { 2976 ackmask |= ATW_INTR_TPS; 2977 /* set ATW_NAR_HF to flush TX FIFO. */ 2978 opmode |= ATW_NAR_HF; 2979 } 2980 2981 ATW_WRITE(sc, ATW_NAR, opmode); 2982 DELAY(atw_nar_delay); 2983 2984 for (i = 0; i < 1000; i++) { 2985 stsr = ATW_READ(sc, ATW_STSR); 2986 if ((stsr & ackmask) == ackmask) 2987 break; 2988 DELAY(10); 2989 } 2990 2991 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2992 2993 if ((stsr & ackmask) == ackmask) 2994 goto out; 2995 2996 test0 = ATW_READ(sc, ATW_TEST0); 2997 2998 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2999 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3000 printf("%s: transmit process not idle [%s]\n", 3001 device_xname(sc->sc_dev), 3002 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3003 printf("%s: bits %08x test0 %08x stsr %08x\n", 3004 device_xname(sc->sc_dev), bits, test0, stsr); 3005 } 3006 3007 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3008 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3009 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3010 device_xname(sc->sc_dev), 3011 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3012 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3013 device_xname(sc->sc_dev), bits, test0, stsr)); 3014 } 3015 out: 3016 if ((bits & ATW_NAR_ST) != 0) 3017 atw_txdrain(sc); 3018 splx(s); 3019 return; 3020 } 3021 3022 /* 3023 * atw_linkintr: 3024 * 3025 * Helper; handle link-status interrupts. 3026 */ 3027 void 3028 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3029 { 3030 struct ieee80211com *ic = &sc->sc_ic; 3031 3032 if (ic->ic_state != IEEE80211_S_RUN) 3033 return; 3034 3035 if (linkstatus & ATW_INTR_LINKON) { 3036 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3037 sc->sc_rescan_timer = 0; 3038 } else if (linkstatus & ATW_INTR_LINKOFF) { 3039 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3040 if (ic->ic_opmode != IEEE80211_M_STA) 3041 return; 3042 sc->sc_rescan_timer = 3; 3043 sc->sc_if.if_timer = 1; 3044 } 3045 } 3046 3047 static inline int 3048 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3049 { 3050 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3051 return 0; 3052 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3053 return 0; 3054 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3055 } 3056 3057 /* 3058 * atw_rxintr: 3059 * 3060 * Helper; handle receive interrupts. 3061 */ 3062 void 3063 atw_rxintr(struct atw_softc *sc) 3064 { 3065 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3066 struct ieee80211com *ic = &sc->sc_ic; 3067 struct ieee80211_node *ni; 3068 struct ieee80211_frame_min *wh; 3069 struct ifnet *ifp = &sc->sc_if; 3070 struct atw_rxsoft *rxs; 3071 struct mbuf *m; 3072 u_int32_t rxstat; 3073 int i, len, rate, rate0; 3074 u_int32_t rssi, ctlrssi; 3075 3076 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3077 rxs = &sc->sc_rxsoft[i]; 3078 3079 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3080 3081 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3082 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3083 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3084 3085 if (rxstat & ATW_RXSTAT_OWN) 3086 break; /* We have processed all receive buffers. */ 3087 3088 DPRINTF3(sc, 3089 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3090 device_xname(sc->sc_dev), 3091 rxstat, ctlrssi, 3092 le32toh(sc->sc_rxdescs[i].ar_buf1), 3093 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3094 3095 /* 3096 * Make sure the packet fits in one buffer. This should 3097 * always be the case. 3098 */ 3099 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3100 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3101 printf("%s: incoming packet spilled, resetting\n", 3102 device_xname(sc->sc_dev)); 3103 (void)atw_init(ifp); 3104 return; 3105 } 3106 3107 /* 3108 * If an error occurred, update stats, clear the status 3109 * word, and leave the packet buffer in place. It will 3110 * simply be reused the next time the ring comes around. 3111 */ 3112 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3113 #define PRINTERR(bit, str) \ 3114 if (rxstat & (bit)) \ 3115 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3116 str) 3117 ifp->if_ierrors++; 3118 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3119 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3120 #if 0 3121 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3122 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3123 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3124 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3125 #endif 3126 #undef PRINTERR 3127 atw_init_rxdesc(sc, i); 3128 continue; 3129 } 3130 3131 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3132 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3133 3134 /* 3135 * No errors; receive the packet. Note the ADM8211 3136 * includes the CRC in promiscuous mode. 3137 */ 3138 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3139 3140 /* 3141 * Allocate a new mbuf cluster. If that fails, we are 3142 * out of memory, and must drop the packet and recycle 3143 * the buffer that's already attached to this descriptor. 3144 */ 3145 m = rxs->rxs_mbuf; 3146 if (atw_add_rxbuf(sc, i) != 0) { 3147 ifp->if_ierrors++; 3148 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3149 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3150 atw_init_rxdesc(sc, i); 3151 continue; 3152 } 3153 3154 ifp->if_ipackets++; 3155 m->m_pkthdr.rcvif = ifp; 3156 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3157 3158 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3159 3160 /* The RSSI comes straight from a register in the 3161 * baseband processor. I know that for the RF3000, 3162 * the RSSI register also contains the antenna-selection 3163 * bits. Mask those off. 3164 * 3165 * TBD Treat other basebands. 3166 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3167 */ 3168 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3169 rssi = ctlrssi & RF3000_RSSI_MASK; 3170 else 3171 rssi = ctlrssi; 3172 3173 #if NBPFILTER > 0 3174 /* Pass this up to any BPF listeners. */ 3175 if (sc->sc_radiobpf != NULL) { 3176 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3177 3178 tap->ar_rate = rate; 3179 3180 /* TBD verify units are dB */ 3181 tap->ar_antsignal = (int)rssi; 3182 if (sc->sc_opmode & ATW_NAR_PR) 3183 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3184 else 3185 tap->ar_flags = 0; 3186 3187 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3188 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3189 3190 bpf_mtap2(sc->sc_radiobpf, tap, 3191 sizeof(sc->sc_rxtapu), m); 3192 } 3193 #endif /* NBPFILTER > 0 */ 3194 3195 sc->sc_recv_ev.ev_count++; 3196 3197 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3198 if (rxstat & ATW_RXSTAT_CRC16E) 3199 sc->sc_crc16e_ev.ev_count++; 3200 if (rxstat & ATW_RXSTAT_CRC32E) 3201 sc->sc_crc32e_ev.ev_count++; 3202 if (rxstat & ATW_RXSTAT_ICVE) 3203 sc->sc_icve_ev.ev_count++; 3204 if (rxstat & ATW_RXSTAT_SFDE) 3205 sc->sc_sfde_ev.ev_count++; 3206 if (rxstat & ATW_RXSTAT_SIGE) 3207 sc->sc_sige_ev.ev_count++; 3208 ifp->if_ierrors++; 3209 m_freem(m); 3210 continue; 3211 } 3212 3213 if (sc->sc_opmode & ATW_NAR_PR) 3214 m_adj(m, -IEEE80211_CRC_LEN); 3215 3216 wh = mtod(m, struct ieee80211_frame_min *); 3217 ni = ieee80211_find_rxnode(ic, wh); 3218 #if 0 3219 if (atw_hw_decrypted(sc, wh)) { 3220 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3221 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3222 } 3223 #endif 3224 ieee80211_input(ic, m, ni, (int)rssi, 0); 3225 ieee80211_free_node(ni); 3226 } 3227 3228 /* Update the receive pointer. */ 3229 sc->sc_rxptr = i; 3230 } 3231 3232 /* 3233 * atw_txintr: 3234 * 3235 * Helper; handle transmit interrupts. 3236 */ 3237 void 3238 atw_txintr(struct atw_softc *sc) 3239 { 3240 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3241 struct ifnet *ifp = &sc->sc_if; 3242 struct atw_txsoft *txs; 3243 u_int32_t txstat; 3244 3245 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3246 device_xname(sc->sc_dev), sc->sc_flags)); 3247 3248 /* 3249 * Go through our Tx list and free mbufs for those 3250 * frames that have been transmitted. 3251 */ 3252 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3253 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3254 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3255 3256 #ifdef ATW_DEBUG 3257 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3258 int i; 3259 printf(" txsoft %p transmit chain:\n", txs); 3260 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3261 txs->txs_ndescs - 1, 3262 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3263 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3264 printf(" descriptor %d:\n", i); 3265 printf(" at_status: 0x%08x\n", 3266 le32toh(sc->sc_txdescs[i].at_stat)); 3267 printf(" at_flags: 0x%08x\n", 3268 le32toh(sc->sc_txdescs[i].at_flags)); 3269 printf(" at_buf1: 0x%08x\n", 3270 le32toh(sc->sc_txdescs[i].at_buf1)); 3271 printf(" at_buf2: 0x%08x\n", 3272 le32toh(sc->sc_txdescs[i].at_buf2)); 3273 if (i == txs->txs_lastdesc) 3274 break; 3275 } 3276 } 3277 #endif 3278 3279 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3280 if (txstat & ATW_TXSTAT_OWN) 3281 break; 3282 3283 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3284 3285 sc->sc_txfree += txs->txs_ndescs; 3286 3287 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3288 0, txs->txs_dmamap->dm_mapsize, 3289 BUS_DMASYNC_POSTWRITE); 3290 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3291 m_freem(txs->txs_mbuf); 3292 txs->txs_mbuf = NULL; 3293 3294 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3295 3296 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3297 sc->sc_txfree == 0)); 3298 ifp->if_flags &= ~IFF_OACTIVE; 3299 3300 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3301 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3302 snprintb(txstat_buf, sizeof(txstat_buf), 3303 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3304 printf("%s: txstat %s %" __PRIuBITS "\n", 3305 device_xname(sc->sc_dev), txstat_buf, 3306 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3307 } 3308 3309 /* 3310 * Check for errors and collisions. 3311 */ 3312 if (txstat & ATW_TXSTAT_TUF) 3313 sc->sc_stats.ts_tx_tuf++; 3314 if (txstat & ATW_TXSTAT_TLT) 3315 sc->sc_stats.ts_tx_tlt++; 3316 if (txstat & ATW_TXSTAT_TRT) 3317 sc->sc_stats.ts_tx_trt++; 3318 if (txstat & ATW_TXSTAT_TRO) 3319 sc->sc_stats.ts_tx_tro++; 3320 if (txstat & ATW_TXSTAT_SOFBR) { 3321 sc->sc_stats.ts_tx_sofbr++; 3322 } 3323 3324 if ((txstat & ATW_TXSTAT_ES) == 0) 3325 ifp->if_collisions += 3326 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3327 else 3328 ifp->if_oerrors++; 3329 3330 ifp->if_opackets++; 3331 } 3332 3333 /* 3334 * If there are no more pending transmissions, cancel the watchdog 3335 * timer. 3336 */ 3337 if (txs == NULL) { 3338 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3339 sc->sc_tx_timer = 0; 3340 } 3341 } 3342 3343 /* 3344 * atw_watchdog: [ifnet interface function] 3345 * 3346 * Watchdog timer handler. 3347 */ 3348 void 3349 atw_watchdog(struct ifnet *ifp) 3350 { 3351 struct atw_softc *sc = ifp->if_softc; 3352 struct ieee80211com *ic = &sc->sc_ic; 3353 3354 ifp->if_timer = 0; 3355 if (ATW_IS_ENABLED(sc) == 0) 3356 return; 3357 3358 if (sc->sc_rescan_timer) { 3359 if (--sc->sc_rescan_timer == 0) 3360 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3361 } 3362 if (sc->sc_tx_timer) { 3363 if (--sc->sc_tx_timer == 0 && 3364 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3365 printf("%s: transmit timeout\n", ifp->if_xname); 3366 ifp->if_oerrors++; 3367 (void)atw_init(ifp); 3368 atw_start(ifp); 3369 } 3370 } 3371 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3372 ifp->if_timer = 1; 3373 ieee80211_watchdog(ic); 3374 } 3375 3376 static void 3377 atw_evcnt_detach(struct atw_softc *sc) 3378 { 3379 evcnt_detach(&sc->sc_sige_ev); 3380 evcnt_detach(&sc->sc_sfde_ev); 3381 evcnt_detach(&sc->sc_icve_ev); 3382 evcnt_detach(&sc->sc_crc32e_ev); 3383 evcnt_detach(&sc->sc_crc16e_ev); 3384 evcnt_detach(&sc->sc_recv_ev); 3385 } 3386 3387 static void 3388 atw_evcnt_attach(struct atw_softc *sc) 3389 { 3390 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3391 NULL, sc->sc_if.if_xname, "recv"); 3392 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3393 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3394 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3395 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3396 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3397 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3398 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3399 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3400 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3401 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3402 } 3403 3404 #ifdef ATW_DEBUG 3405 static void 3406 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3407 { 3408 struct atw_softc *sc = ifp->if_softc; 3409 struct mbuf *m; 3410 int i, noctets = 0; 3411 3412 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3413 m0->m_pkthdr.len); 3414 3415 for (m = m0; m; m = m->m_next) { 3416 if (m->m_len == 0) 3417 continue; 3418 for (i = 0; i < m->m_len; i++) { 3419 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3420 if (++noctets % 24 == 0) 3421 printf("\n"); 3422 } 3423 } 3424 printf("%s%s: %d bytes emitted\n", 3425 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3426 } 3427 #endif /* ATW_DEBUG */ 3428 3429 /* 3430 * atw_start: [ifnet interface function] 3431 * 3432 * Start packet transmission on the interface. 3433 */ 3434 void 3435 atw_start(struct ifnet *ifp) 3436 { 3437 struct atw_softc *sc = ifp->if_softc; 3438 struct ieee80211_key *k; 3439 struct ieee80211com *ic = &sc->sc_ic; 3440 struct ieee80211_node *ni; 3441 struct ieee80211_frame_min *whm; 3442 struct ieee80211_frame *wh; 3443 struct atw_frame *hh; 3444 struct mbuf *m0, *m; 3445 struct atw_txsoft *txs, *last_txs; 3446 struct atw_txdesc *txd; 3447 int npkt, rate; 3448 bus_dmamap_t dmamap; 3449 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3450 3451 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3452 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3453 3454 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3455 return; 3456 3457 /* 3458 * Remember the previous number of free descriptors and 3459 * the first descriptor we'll use. 3460 */ 3461 ofree = sc->sc_txfree; 3462 firsttx = lasttx = sc->sc_txnext; 3463 3464 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3465 device_xname(sc->sc_dev), ofree, firsttx)); 3466 3467 /* 3468 * Loop through the send queue, setting up transmit descriptors 3469 * until we drain the queue, or use up all available transmit 3470 * descriptors. 3471 */ 3472 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3473 sc->sc_txfree != 0) { 3474 3475 /* 3476 * Grab a packet off the management queue, if it 3477 * is not empty. Otherwise, from the data queue. 3478 */ 3479 IF_DEQUEUE(&ic->ic_mgtq, m0); 3480 if (m0 != NULL) { 3481 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3482 m0->m_pkthdr.rcvif = NULL; 3483 } else if (ic->ic_state != IEEE80211_S_RUN) 3484 break; /* send no data until associated */ 3485 else { 3486 IFQ_DEQUEUE(&ifp->if_snd, m0); 3487 if (m0 == NULL) 3488 break; 3489 #if NBPFILTER > 0 3490 if (ifp->if_bpf != NULL) 3491 bpf_mtap(ifp->if_bpf, m0); 3492 #endif /* NBPFILTER > 0 */ 3493 ni = ieee80211_find_txnode(ic, 3494 mtod(m0, struct ether_header *)->ether_dhost); 3495 if (ni == NULL) { 3496 ifp->if_oerrors++; 3497 break; 3498 } 3499 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3500 ieee80211_free_node(ni); 3501 ifp->if_oerrors++; 3502 break; 3503 } 3504 } 3505 3506 rate = MAX(ieee80211_get_rate(ni), 2); 3507 3508 whm = mtod(m0, struct ieee80211_frame_min *); 3509 3510 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3511 k = NULL; 3512 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3513 m_freem(m0); 3514 ieee80211_free_node(ni); 3515 ifp->if_oerrors++; 3516 break; 3517 } 3518 3519 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3520 ic->ic_flags, ic->ic_fragthreshold, rate, 3521 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3522 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3523 m_freem(m0); 3524 break; 3525 } 3526 3527 /* XXX Misleading if fragmentation is enabled. Better 3528 * to fragment in software? 3529 */ 3530 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3531 3532 #if NBPFILTER > 0 3533 /* 3534 * Pass the packet to any BPF listeners. 3535 */ 3536 if (ic->ic_rawbpf != NULL) 3537 bpf_mtap((void *)ic->ic_rawbpf, m0); 3538 3539 if (sc->sc_radiobpf != NULL) { 3540 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3541 3542 tap->at_rate = rate; 3543 3544 bpf_mtap2(sc->sc_radiobpf, tap, 3545 sizeof(sc->sc_txtapu), m0); 3546 } 3547 #endif /* NBPFILTER > 0 */ 3548 3549 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3550 3551 if (ni != NULL) 3552 ieee80211_free_node(ni); 3553 3554 if (m0 == NULL) { 3555 ifp->if_oerrors++; 3556 break; 3557 } 3558 3559 /* just to make sure. */ 3560 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3561 3562 if (m0 == NULL) { 3563 ifp->if_oerrors++; 3564 break; 3565 } 3566 3567 hh = mtod(m0, struct atw_frame *); 3568 wh = &hh->atw_ihdr; 3569 3570 /* Copy everything we need from the 802.11 header: 3571 * Frame Control; address 1, address 3, or addresses 3572 * 3 and 4. NIC fills in BSSID, SA. 3573 */ 3574 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3575 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3576 panic("%s: illegal WDS frame", 3577 device_xname(sc->sc_dev)); 3578 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3579 } else 3580 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3581 3582 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3583 3584 /* initialize remaining Tx parameters */ 3585 memset(&hh->u, 0, sizeof(hh->u)); 3586 3587 hh->atw_rate = rate * 5; 3588 /* XXX this could be incorrect if M_FCS. _encap should 3589 * probably strip FCS just in case it sticks around in 3590 * bridged packets. 3591 */ 3592 hh->atw_service = 0x00; /* XXX guess */ 3593 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3594 sizeof(struct atw_frame)); 3595 3596 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3597 hh->atw_rtylmt = 3; 3598 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3599 #if 0 3600 if (do_encrypt) { 3601 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3602 hh->atw_keyid = ic->ic_def_txkey; 3603 } 3604 #endif 3605 3606 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3607 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3608 if (txs->txs_d0.d_residue) 3609 hh->atw_head_plcplen |= htole16(0x8000); 3610 if (txs->txs_dn.d_residue) 3611 hh->atw_tail_plcplen |= htole16(0x8000); 3612 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3613 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3614 3615 /* never fragment multicast frames */ 3616 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3617 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3618 } else if (sc->sc_flags & ATWF_RTSCTS) { 3619 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3620 } 3621 3622 #ifdef ATW_DEBUG 3623 hh->atw_fragnum = 0; 3624 3625 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3626 printf("%s: dst = %s, rate = 0x%02x, " 3627 "service = 0x%02x, paylen = 0x%04x\n", 3628 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3629 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3630 3631 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3632 "dur1 = 0x%04x, dur2 = 0x%04x, " 3633 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3634 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3635 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3636 hh->atw_tail_dur, hh->atw_head_dur); 3637 3638 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3639 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3640 device_xname(sc->sc_dev), hh->atw_hdrctl, 3641 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3642 3643 printf("%s: keyid = %d\n", 3644 device_xname(sc->sc_dev), hh->atw_keyid); 3645 3646 atw_dump_pkt(ifp, m0); 3647 } 3648 #endif /* ATW_DEBUG */ 3649 3650 dmamap = txs->txs_dmamap; 3651 3652 /* 3653 * Load the DMA map. Copy and try (once) again if the packet 3654 * didn't fit in the alloted number of segments. 3655 */ 3656 for (first = 1; 3657 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3658 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3659 first = 0) { 3660 MGETHDR(m, M_DONTWAIT, MT_DATA); 3661 if (m == NULL) { 3662 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3663 break; 3664 } 3665 if (m0->m_pkthdr.len > MHLEN) { 3666 MCLGET(m, M_DONTWAIT); 3667 if ((m->m_flags & M_EXT) == 0) { 3668 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3669 "cluster\n"); 3670 m_freem(m); 3671 break; 3672 } 3673 } 3674 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3675 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3676 m_freem(m0); 3677 m0 = m; 3678 m = NULL; 3679 } 3680 if (error != 0) { 3681 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3682 "error = %d\n", error); 3683 m_freem(m0); 3684 break; 3685 } 3686 3687 /* 3688 * Ensure we have enough descriptors free to describe 3689 * the packet. 3690 */ 3691 if (dmamap->dm_nsegs > sc->sc_txfree) { 3692 /* 3693 * Not enough free descriptors to transmit 3694 * this packet. Unload the DMA map and 3695 * drop the packet. Notify the upper layer 3696 * that there are no more slots left. 3697 * 3698 * XXX We could allocate an mbuf and copy, but 3699 * XXX it is worth it? 3700 */ 3701 bus_dmamap_unload(sc->sc_dmat, dmamap); 3702 m_freem(m0); 3703 break; 3704 } 3705 3706 /* 3707 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3708 */ 3709 3710 /* Sync the DMA map. */ 3711 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3712 BUS_DMASYNC_PREWRITE); 3713 3714 /* XXX arbitrary retry limit; 8 because I have seen it in 3715 * use already and maybe 0 means "no tries" ! 3716 */ 3717 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3718 3719 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3720 device_xname(sc->sc_dev), rate * 5)); 3721 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3722 3723 /* 3724 * Initialize the transmit descriptors. 3725 */ 3726 for (nexttx = sc->sc_txnext, seg = 0; 3727 seg < dmamap->dm_nsegs; 3728 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3729 /* 3730 * If this is the first descriptor we're 3731 * enqueueing, don't set the OWN bit just 3732 * yet. That could cause a race condition. 3733 * We'll do it below. 3734 */ 3735 txd = &sc->sc_txdescs[nexttx]; 3736 txd->at_ctl = ctl | 3737 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3738 3739 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3740 txd->at_flags = 3741 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3742 ATW_TXFLAG_TBS1_MASK)) | 3743 ((nexttx == (ATW_NTXDESC - 1)) 3744 ? htole32(ATW_TXFLAG_TER) : 0); 3745 lasttx = nexttx; 3746 } 3747 3748 /* Set `first segment' and `last segment' appropriately. */ 3749 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3750 htole32(ATW_TXFLAG_FS); 3751 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3752 3753 #ifdef ATW_DEBUG 3754 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3755 printf(" txsoft %p transmit chain:\n", txs); 3756 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3757 printf(" descriptor %d:\n", seg); 3758 printf(" at_ctl: 0x%08x\n", 3759 le32toh(sc->sc_txdescs[seg].at_ctl)); 3760 printf(" at_flags: 0x%08x\n", 3761 le32toh(sc->sc_txdescs[seg].at_flags)); 3762 printf(" at_buf1: 0x%08x\n", 3763 le32toh(sc->sc_txdescs[seg].at_buf1)); 3764 printf(" at_buf2: 0x%08x\n", 3765 le32toh(sc->sc_txdescs[seg].at_buf2)); 3766 if (seg == lasttx) 3767 break; 3768 } 3769 } 3770 #endif 3771 3772 /* Sync the descriptors we're using. */ 3773 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3774 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3775 3776 /* 3777 * Store a pointer to the packet so we can free it later, 3778 * and remember what txdirty will be once the packet is 3779 * done. 3780 */ 3781 txs->txs_mbuf = m0; 3782 txs->txs_firstdesc = sc->sc_txnext; 3783 txs->txs_lastdesc = lasttx; 3784 txs->txs_ndescs = dmamap->dm_nsegs; 3785 3786 /* Advance the tx pointer. */ 3787 sc->sc_txfree -= dmamap->dm_nsegs; 3788 sc->sc_txnext = nexttx; 3789 3790 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3791 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3792 3793 last_txs = txs; 3794 } 3795 3796 if (sc->sc_txfree != ofree) { 3797 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3798 device_xname(sc->sc_dev), lasttx, firsttx)); 3799 /* 3800 * Cause a transmit interrupt to happen on the 3801 * last packet we enqueued. 3802 */ 3803 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3804 ATW_CDTXSYNC(sc, lasttx, 1, 3805 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3806 3807 /* 3808 * The entire packet chain is set up. Give the 3809 * first descriptor to the chip now. 3810 */ 3811 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3812 ATW_CDTXSYNC(sc, firsttx, 1, 3813 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3814 3815 /* Wake up the transmitter. */ 3816 ATW_WRITE(sc, ATW_TDR, 0x1); 3817 3818 if (txs == NULL || sc->sc_txfree == 0) 3819 ifp->if_flags |= IFF_OACTIVE; 3820 3821 /* Set a watchdog timer in case the chip flakes out. */ 3822 sc->sc_tx_timer = 5; 3823 ifp->if_timer = 1; 3824 } 3825 } 3826 3827 /* 3828 * atw_ioctl: [ifnet interface function] 3829 * 3830 * Handle control requests from the operator. 3831 */ 3832 int 3833 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3834 { 3835 struct atw_softc *sc = ifp->if_softc; 3836 int s, error = 0; 3837 3838 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3839 if (!device_is_active(sc->sc_dev)) 3840 return ENXIO; 3841 3842 s = splnet(); 3843 3844 switch (cmd) { 3845 case SIOCSIFFLAGS: 3846 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3847 break; 3848 if (ifp->if_flags & IFF_UP) { 3849 if (ATW_IS_ENABLED(sc)) { 3850 /* 3851 * To avoid rescanning another access point, 3852 * do not call atw_init() here. Instead, 3853 * only reflect media settings. 3854 */ 3855 atw_filter_setup(sc); 3856 } else 3857 error = atw_init(ifp); 3858 } else if (ATW_IS_ENABLED(sc)) 3859 atw_stop(ifp, 1); 3860 break; 3861 case SIOCADDMULTI: 3862 case SIOCDELMULTI: 3863 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3864 if (ifp->if_flags & IFF_RUNNING) 3865 atw_filter_setup(sc); /* do not rescan */ 3866 error = 0; 3867 } 3868 break; 3869 default: 3870 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3871 if (error == ENETRESET || error == ERESTART) { 3872 if (is_running(ifp)) 3873 error = atw_init(ifp); 3874 else 3875 error = 0; 3876 } 3877 break; 3878 } 3879 3880 /* Try to get more packets going. */ 3881 if (ATW_IS_ENABLED(sc)) 3882 atw_start(ifp); 3883 3884 splx(s); 3885 return (error); 3886 } 3887 3888 static int 3889 atw_media_change(struct ifnet *ifp) 3890 { 3891 int error; 3892 3893 error = ieee80211_media_change(ifp); 3894 if (error == ENETRESET) { 3895 if (is_running(ifp)) 3896 error = atw_init(ifp); 3897 else 3898 error = 0; 3899 } 3900 return error; 3901 } 3902
Indexes created Fri Oct 17 09:09:57 GMT 2025