atw.c revision 1.145
1 /* $NetBSD: atw.c,v 1.145 2009/09/13 22:07:34 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.145 2009/09/13 22:07:34 dyoung Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/kauth.h> 52 #include <sys/time.h> 53 #include <lib/libkern/libkern.h> 54 55 #include <machine/endian.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <net80211/ieee80211_netbsd.h> 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <sys/bus.h> 73 #include <sys/intr.h> 74 75 #include <dev/ic/atwreg.h> 76 #include <dev/ic/rf3000reg.h> 77 #include <dev/ic/si4136reg.h> 78 #include <dev/ic/atwvar.h> 79 #include <dev/ic/smc93cx6var.h> 80 81 /* XXX TBD open questions 82 * 83 * 84 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 85 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 86 * handle this for me? 87 * 88 */ 89 /* device attachment 90 * 91 * print TOFS[012] 92 * 93 * device initialization 94 * 95 * clear ATW_FRCTL_MAXPSP to disable max power saving 96 * set ATW_TXBR_ALCUPDATE to enable ALC 97 * set TOFS[012]? (hope not) 98 * disable rx/tx 99 * set ATW_PAR_SWR (software reset) 100 * wait for ATW_PAR_SWR clear 101 * disable interrupts 102 * ack status register 103 * enable interrupts 104 * 105 * rx/tx initialization 106 * 107 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 108 * allocate and init descriptor rings 109 * write ATW_PAR_DSL (descriptor skip length) 110 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 111 * write ATW_NAR_SQ for one/both transmit descriptor rings 112 * write ATW_NAR_SQ for one/both transmit descriptor rings 113 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 114 * 115 * rx/tx end 116 * 117 * stop DMA 118 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * flush tx w/ ATW_NAR_HF 120 * 121 * scan 122 * 123 * initialize rx/tx 124 * 125 * BSS join: (re)association response 126 * 127 * set ATW_FRCTL_AID 128 * 129 * optimizations ??? 130 * 131 */ 132 133 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 134 135 int atw_pseudo_milli = 1; 136 int atw_magic_delay1 = 100 * 1000; 137 int atw_magic_delay2 = 100 * 1000; 138 /* more magic multi-millisecond delays (units: microseconds) */ 139 int atw_nar_delay = 20 * 1000; 140 int atw_magic_delay4 = 10 * 1000; 141 int atw_rf_delay1 = 10 * 1000; 142 int atw_rf_delay2 = 5 * 1000; 143 int atw_plcphd_delay = 2 * 1000; 144 int atw_bbp_io_enable_delay = 20 * 1000; 145 int atw_bbp_io_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 1000; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 int atw_xindiv2 = 0; 150 151 #ifdef ATW_DEBUG 152 int atw_debug = 0; 153 154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 157 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 158 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 159 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 160 161 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 162 static void atw_print_regs(struct atw_softc *, const char *); 163 164 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 165 # ifdef ATW_BBPDEBUG 166 static void atw_rf3000_print(struct atw_softc *); 167 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 168 # endif /* ATW_BBPDEBUG */ 169 170 # ifdef ATW_SYNDEBUG 171 static void atw_si4126_print(struct atw_softc *); 172 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 173 # endif /* ATW_SYNDEBUG */ 174 175 #else 176 #define ATW_DPRINTF(x) 177 #define ATW_DPRINTF2(x) 178 #define ATW_DPRINTF3(x) 179 #define DPRINTF(sc, x) /* nothing */ 180 #define DPRINTF2(sc, x) /* nothing */ 181 #define DPRINTF3(sc, x) /* nothing */ 182 #endif 183 184 /* ifnet methods */ 185 int atw_init(struct ifnet *); 186 int atw_ioctl(struct ifnet *, u_long, void *); 187 void atw_start(struct ifnet *); 188 void atw_stop(struct ifnet *, int); 189 void atw_watchdog(struct ifnet *); 190 191 /* Device attachment */ 192 void atw_attach(struct atw_softc *); 193 int atw_detach(struct atw_softc *); 194 static void atw_evcnt_attach(struct atw_softc *); 195 static void atw_evcnt_detach(struct atw_softc *); 196 197 /* Rx/Tx process */ 198 int atw_add_rxbuf(struct atw_softc *, int); 199 void atw_idle(struct atw_softc *, u_int32_t); 200 void atw_rxdrain(struct atw_softc *); 201 void atw_txdrain(struct atw_softc *); 202 203 /* Device (de)activation and power state */ 204 void atw_disable(struct atw_softc *); 205 int atw_enable(struct atw_softc *); 206 void atw_reset(struct atw_softc *); 207 208 /* Interrupt handlers */ 209 void atw_linkintr(struct atw_softc *, u_int32_t); 210 void atw_rxintr(struct atw_softc *); 211 void atw_txintr(struct atw_softc *, uint32_t); 212 213 /* 802.11 state machine */ 214 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 215 static void atw_next_scan(void *); 216 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 217 struct ieee80211_node *, int, int, u_int32_t); 218 static int atw_tune(struct atw_softc *); 219 220 /* Device initialization */ 221 static void atw_bbp_io_init(struct atw_softc *); 222 static void atw_cfp_init(struct atw_softc *); 223 static void atw_cmdr_init(struct atw_softc *); 224 static void atw_ifs_init(struct atw_softc *); 225 static void atw_nar_init(struct atw_softc *); 226 static void atw_response_times_init(struct atw_softc *); 227 static void atw_rf_reset(struct atw_softc *); 228 static void atw_test1_init(struct atw_softc *); 229 static void atw_tofs0_init(struct atw_softc *); 230 static void atw_tofs2_init(struct atw_softc *); 231 static void atw_txlmt_init(struct atw_softc *); 232 static void atw_wcsr_init(struct atw_softc *); 233 234 /* Key management */ 235 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 236 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 237 const u_int8_t[IEEE80211_ADDR_LEN]); 238 static void atw_key_update_begin(struct ieee80211com *); 239 static void atw_key_update_end(struct ieee80211com *); 240 241 /* RAM/ROM utilities */ 242 static void atw_clear_sram(struct atw_softc *); 243 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 244 static int atw_read_srom(struct atw_softc *); 245 246 /* BSS setup */ 247 static void atw_predict_beacon(struct atw_softc *); 248 static void atw_start_beacon(struct atw_softc *, int); 249 static void atw_write_bssid(struct atw_softc *); 250 static void atw_write_ssid(struct atw_softc *); 251 static void atw_write_sup_rates(struct atw_softc *); 252 static void atw_write_wep(struct atw_softc *); 253 254 /* Media */ 255 static int atw_media_change(struct ifnet *); 256 257 static void atw_filter_setup(struct atw_softc *); 258 259 /* 802.11 utilities */ 260 static uint64_t atw_get_tsft(struct atw_softc *); 261 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 262 uint32_t); 263 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 264 static void atw_node_free(struct ieee80211_node *); 265 266 /* 267 * Tuner/transceiver/modem 268 */ 269 static void atw_bbp_io_enable(struct atw_softc *, int); 270 271 /* RFMD RF3000 Baseband Processor */ 272 static int atw_rf3000_init(struct atw_softc *); 273 static int atw_rf3000_tune(struct atw_softc *, u_int); 274 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 275 276 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 277 static void atw_si4126_tune(struct atw_softc *, u_int); 278 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 279 280 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 281 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 282 283 const char *atw_tx_state[] = { 284 "STOPPED", 285 "RUNNING - read descriptor", 286 "RUNNING - transmitting", 287 "RUNNING - filling fifo", /* XXX */ 288 "SUSPENDED", 289 "RUNNING -- write descriptor", 290 "RUNNING -- write last descriptor", 291 "RUNNING - fifo full" 292 }; 293 294 const char *atw_rx_state[] = { 295 "STOPPED", 296 "RUNNING - read descriptor", 297 "RUNNING - check this packet, pre-fetch next", 298 "RUNNING - wait for reception", 299 "SUSPENDED", 300 "RUNNING - write descriptor", 301 "RUNNING - flush fifo", 302 "RUNNING - fifo drain" 303 }; 304 305 static inline int 306 is_running(struct ifnet *ifp) 307 { 308 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 309 } 310 311 int 312 atw_activate(device_t self, enum devact act) 313 { 314 struct atw_softc *sc = device_private(self); 315 int rv = 0, s; 316 317 s = splnet(); 318 switch (act) { 319 case DVACT_ACTIVATE: 320 rv = EOPNOTSUPP; 321 break; 322 323 case DVACT_DEACTIVATE: 324 if_deactivate(&sc->sc_if); 325 break; 326 } 327 splx(s); 328 return rv; 329 } 330 331 /* 332 * atw_enable: 333 * 334 * Enable the ADM8211 chip. 335 */ 336 int 337 atw_enable(struct atw_softc *sc) 338 { 339 340 if (ATW_IS_ENABLED(sc) == 0) { 341 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 342 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 343 return (EIO); 344 } 345 sc->sc_flags |= ATWF_ENABLED; 346 /* Power may have been removed, and WEP keys thus 347 * reset. 348 */ 349 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 350 } 351 return (0); 352 } 353 354 /* 355 * atw_disable: 356 * 357 * Disable the ADM8211 chip. 358 */ 359 void 360 atw_disable(struct atw_softc *sc) 361 { 362 if (!ATW_IS_ENABLED(sc)) 363 return; 364 if (sc->sc_disable != NULL) 365 (*sc->sc_disable)(sc); 366 sc->sc_flags &= ~ATWF_ENABLED; 367 } 368 369 /* Returns -1 on failure. */ 370 static int 371 atw_read_srom(struct atw_softc *sc) 372 { 373 struct seeprom_descriptor sd; 374 uint32_t test0, fail_bits; 375 376 (void)memset(&sd, 0, sizeof(sd)); 377 378 test0 = ATW_READ(sc, ATW_TEST0); 379 380 switch (sc->sc_rev) { 381 case ATW_REVISION_BA: 382 case ATW_REVISION_CA: 383 fail_bits = ATW_TEST0_EPNE; 384 break; 385 default: 386 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 387 break; 388 } 389 if ((test0 & fail_bits) != 0) { 390 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 391 return -1; 392 } 393 394 switch (test0 & ATW_TEST0_EPTYP_MASK) { 395 case ATW_TEST0_EPTYP_93c66: 396 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 397 sc->sc_sromsz = 512; 398 sd.sd_chip = C56_66; 399 break; 400 case ATW_TEST0_EPTYP_93c46: 401 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 402 sc->sc_sromsz = 128; 403 sd.sd_chip = C46; 404 break; 405 default: 406 printf("%s: unknown SROM type %" __PRIuBITS "\n", 407 device_xname(sc->sc_dev), 408 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 409 return -1; 410 } 411 412 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 413 414 if (sc->sc_srom == NULL) { 415 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 416 return -1; 417 } 418 419 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 420 421 /* ADM8211 has a single 32-bit register for controlling the 422 * 93cx6 SROM. Bit SRS enables the serial port. There is no 423 * "ready" bit. The ADM8211 input/output sense is the reverse 424 * of read_seeprom's. 425 */ 426 sd.sd_tag = sc->sc_st; 427 sd.sd_bsh = sc->sc_sh; 428 sd.sd_regsize = 4; 429 sd.sd_control_offset = ATW_SPR; 430 sd.sd_status_offset = ATW_SPR; 431 sd.sd_dataout_offset = ATW_SPR; 432 sd.sd_CK = ATW_SPR_SCLK; 433 sd.sd_CS = ATW_SPR_SCS; 434 sd.sd_DI = ATW_SPR_SDO; 435 sd.sd_DO = ATW_SPR_SDI; 436 sd.sd_MS = ATW_SPR_SRS; 437 sd.sd_RDY = 0; 438 439 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 440 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 441 free(sc->sc_srom, M_DEVBUF); 442 return -1; 443 } 444 #ifdef ATW_DEBUG 445 { 446 int i; 447 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 448 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 449 if (((i % 8) == 0) && (i != 0)) { 450 ATW_DPRINTF(("\n\t")); 451 } 452 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 453 } 454 ATW_DPRINTF(("\n")); 455 } 456 #endif /* ATW_DEBUG */ 457 return 0; 458 } 459 460 #ifdef ATW_DEBUG 461 static void 462 atw_print_regs(struct atw_softc *sc, const char *where) 463 { 464 #define PRINTREG(sc, reg) \ 465 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 466 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 467 468 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 469 470 PRINTREG(sc, ATW_PAR); 471 PRINTREG(sc, ATW_FRCTL); 472 PRINTREG(sc, ATW_TDR); 473 PRINTREG(sc, ATW_WTDP); 474 PRINTREG(sc, ATW_RDR); 475 PRINTREG(sc, ATW_WRDP); 476 PRINTREG(sc, ATW_RDB); 477 PRINTREG(sc, ATW_CSR3A); 478 PRINTREG(sc, ATW_TDBD); 479 PRINTREG(sc, ATW_TDBP); 480 PRINTREG(sc, ATW_STSR); 481 PRINTREG(sc, ATW_CSR5A); 482 PRINTREG(sc, ATW_NAR); 483 PRINTREG(sc, ATW_CSR6A); 484 PRINTREG(sc, ATW_IER); 485 PRINTREG(sc, ATW_CSR7A); 486 PRINTREG(sc, ATW_LPC); 487 PRINTREG(sc, ATW_TEST1); 488 PRINTREG(sc, ATW_SPR); 489 PRINTREG(sc, ATW_TEST0); 490 PRINTREG(sc, ATW_WCSR); 491 PRINTREG(sc, ATW_WPDR); 492 PRINTREG(sc, ATW_GPTMR); 493 PRINTREG(sc, ATW_GPIO); 494 PRINTREG(sc, ATW_BBPCTL); 495 PRINTREG(sc, ATW_SYNCTL); 496 PRINTREG(sc, ATW_PLCPHD); 497 PRINTREG(sc, ATW_MMIWADDR); 498 PRINTREG(sc, ATW_MMIRADDR1); 499 PRINTREG(sc, ATW_MMIRADDR2); 500 PRINTREG(sc, ATW_TXBR); 501 PRINTREG(sc, ATW_CSR15A); 502 PRINTREG(sc, ATW_ALCSTAT); 503 PRINTREG(sc, ATW_TOFS2); 504 PRINTREG(sc, ATW_CMDR); 505 PRINTREG(sc, ATW_PCIC); 506 PRINTREG(sc, ATW_PMCSR); 507 PRINTREG(sc, ATW_PAR0); 508 PRINTREG(sc, ATW_PAR1); 509 PRINTREG(sc, ATW_MAR0); 510 PRINTREG(sc, ATW_MAR1); 511 PRINTREG(sc, ATW_ATIMDA0); 512 PRINTREG(sc, ATW_ABDA1); 513 PRINTREG(sc, ATW_BSSID0); 514 PRINTREG(sc, ATW_TXLMT); 515 PRINTREG(sc, ATW_MIBCNT); 516 PRINTREG(sc, ATW_BCNT); 517 PRINTREG(sc, ATW_TSFTH); 518 PRINTREG(sc, ATW_TSC); 519 PRINTREG(sc, ATW_SYNRF); 520 PRINTREG(sc, ATW_BPLI); 521 PRINTREG(sc, ATW_CAP0); 522 PRINTREG(sc, ATW_CAP1); 523 PRINTREG(sc, ATW_RMD); 524 PRINTREG(sc, ATW_CFPP); 525 PRINTREG(sc, ATW_TOFS0); 526 PRINTREG(sc, ATW_TOFS1); 527 PRINTREG(sc, ATW_IFST); 528 PRINTREG(sc, ATW_RSPT); 529 PRINTREG(sc, ATW_TSFTL); 530 PRINTREG(sc, ATW_WEPCTL); 531 PRINTREG(sc, ATW_WESK); 532 PRINTREG(sc, ATW_WEPCNT); 533 PRINTREG(sc, ATW_MACTEST); 534 PRINTREG(sc, ATW_FER); 535 PRINTREG(sc, ATW_FEMR); 536 PRINTREG(sc, ATW_FPSR); 537 PRINTREG(sc, ATW_FFER); 538 #undef PRINTREG 539 } 540 #endif /* ATW_DEBUG */ 541 542 /* 543 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 544 */ 545 void 546 atw_attach(struct atw_softc *sc) 547 { 548 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 550 }; 551 struct ieee80211com *ic = &sc->sc_ic; 552 struct ifnet *ifp = &sc->sc_if; 553 int country_code, error, i, nrate, srom_major; 554 u_int32_t reg; 555 static const char *type_strings[] = {"Intersil (not supported)", 556 "RFMD", "Marvel (not supported)"}; 557 558 sc->sc_txth = atw_txthresh_tab_lo; 559 560 SIMPLEQ_INIT(&sc->sc_txfreeq); 561 SIMPLEQ_INIT(&sc->sc_txdirtyq); 562 563 #ifdef ATW_DEBUG 564 atw_print_regs(sc, "atw_attach"); 565 #endif /* ATW_DEBUG */ 566 567 /* 568 * Allocate the control data structures, and create and load the 569 * DMA map for it. 570 */ 571 if ((error = bus_dmamem_alloc(sc->sc_dmat, 572 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 573 1, &sc->sc_cdnseg, 0)) != 0) { 574 aprint_error_dev(sc->sc_dev, 575 "unable to allocate control data, error = %d\n", 576 error); 577 goto fail_0; 578 } 579 580 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 581 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 582 BUS_DMA_COHERENT)) != 0) { 583 aprint_error_dev(sc->sc_dev, 584 "unable to map control data, error = %d\n", 585 error); 586 goto fail_1; 587 } 588 589 if ((error = bus_dmamap_create(sc->sc_dmat, 590 sizeof(struct atw_control_data), 1, 591 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 592 aprint_error_dev(sc->sc_dev, 593 "unable to create control data DMA map, error = %d\n", 594 error); 595 goto fail_2; 596 } 597 598 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 599 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 600 0)) != 0) { 601 aprint_error_dev(sc->sc_dev, 602 "unable to load control data DMA map, error = %d\n", error); 603 goto fail_3; 604 } 605 606 /* 607 * Create the transmit buffer DMA maps. 608 */ 609 sc->sc_ntxsegs = ATW_NTXSEGS; 610 for (i = 0; i < ATW_TXQUEUELEN; i++) { 611 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 612 sc->sc_ntxsegs, MCLBYTES, 0, 0, 613 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 614 aprint_error_dev(sc->sc_dev, 615 "unable to create tx DMA map %d, error = %d\n", i, 616 error); 617 goto fail_4; 618 } 619 } 620 621 /* 622 * Create the receive buffer DMA maps. 623 */ 624 for (i = 0; i < ATW_NRXDESC; i++) { 625 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 626 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 627 aprint_error_dev(sc->sc_dev, 628 "unable to create rx DMA map %d, error = %d\n", i, 629 error); 630 goto fail_5; 631 } 632 } 633 for (i = 0; i < ATW_NRXDESC; i++) { 634 sc->sc_rxsoft[i].rxs_mbuf = NULL; 635 } 636 637 switch (sc->sc_rev) { 638 case ATW_REVISION_AB: 639 case ATW_REVISION_AF: 640 sc->sc_sramlen = ATW_SRAM_A_SIZE; 641 break; 642 case ATW_REVISION_BA: 643 case ATW_REVISION_CA: 644 sc->sc_sramlen = ATW_SRAM_B_SIZE; 645 break; 646 } 647 648 /* Reset the chip to a known state. */ 649 atw_reset(sc); 650 651 if (atw_read_srom(sc) == -1) 652 return; 653 654 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 655 ATW_SR_RFTYPE_MASK); 656 657 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 658 ATW_SR_BBPTYPE_MASK); 659 660 if (sc->sc_rftype >= __arraycount(type_strings)) { 661 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 662 return; 663 } 664 if (sc->sc_bbptype >= __arraycount(type_strings)) { 665 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 666 return; 667 } 668 669 printf("%s: %s RF, %s BBP", device_xname(sc->sc_dev), 670 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 671 672 /* XXX There exists a Linux driver which seems to use RFType = 0 for 673 * MARVEL. My bug, or theirs? 674 */ 675 676 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 677 678 switch (sc->sc_rftype) { 679 case ATW_RFTYPE_INTERSIL: 680 reg |= ATW_SYNCTL_CS1; 681 break; 682 case ATW_RFTYPE_RFMD: 683 reg |= ATW_SYNCTL_CS0; 684 break; 685 case ATW_RFTYPE_MARVEL: 686 break; 687 } 688 689 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 690 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 691 692 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 693 694 switch (sc->sc_bbptype) { 695 case ATW_BBPTYPE_INTERSIL: 696 reg |= ATW_BBPCTL_TWI; 697 break; 698 case ATW_BBPTYPE_RFMD: 699 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 700 ATW_BBPCTL_CCA_ACTLO; 701 break; 702 case ATW_BBPTYPE_MARVEL: 703 break; 704 case ATW_C_BBPTYPE_RFMD: 705 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 706 device_xname(sc->sc_dev)); 707 break; 708 } 709 710 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 711 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 712 713 /* 714 * From this point forward, the attachment cannot fail. A failure 715 * before this point releases all resources that may have been 716 * allocated. 717 */ 718 sc->sc_flags |= ATWF_ATTACHED; 719 720 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 721 htole16(sc->sc_srom[ATW_SR_MAC00]), 722 htole16(sc->sc_srom[ATW_SR_MAC01]), 723 htole16(sc->sc_srom[ATW_SR_MAC10]))); 724 725 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 726 ATW_SR_MAJOR_MASK); 727 728 if (srom_major < 2) 729 sc->sc_rf3000_options1 = 0; 730 else if (sc->sc_rev == ATW_REVISION_BA) { 731 sc->sc_rf3000_options1 = 732 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 733 ATW_SR_CR28_MASK); 734 } else 735 sc->sc_rf3000_options1 = 0; 736 737 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 738 ATW_SR_CR29_MASK); 739 740 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 741 ATW_SR_CTRY_MASK); 742 743 #define ADD_CHANNEL(_ic, _chan) do { \ 744 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 745 _ic->ic_channels[_chan].ic_freq = \ 746 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 747 } while (0) 748 749 /* Find available channels */ 750 switch (country_code) { 751 case COUNTRY_MMK2: /* 1-14 */ 752 ADD_CHANNEL(ic, 14); 753 /*FALLTHROUGH*/ 754 case COUNTRY_ETSI: /* 1-13 */ 755 for (i = 1; i <= 13; i++) 756 ADD_CHANNEL(ic, i); 757 break; 758 case COUNTRY_FCC: /* 1-11 */ 759 case COUNTRY_IC: /* 1-11 */ 760 for (i = 1; i <= 11; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 case COUNTRY_MMK: /* 14 */ 764 ADD_CHANNEL(ic, 14); 765 break; 766 case COUNTRY_FRANCE: /* 10-13 */ 767 for (i = 10; i <= 13; i++) 768 ADD_CHANNEL(ic, i); 769 break; 770 default: /* assume channels 10-11 */ 771 case COUNTRY_SPAIN: /* 10-11 */ 772 for (i = 10; i <= 11; i++) 773 ADD_CHANNEL(ic, i); 774 break; 775 } 776 777 /* Read the MAC address. */ 778 reg = ATW_READ(sc, ATW_PAR0); 779 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 780 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 781 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 782 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 783 reg = ATW_READ(sc, ATW_PAR1); 784 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 785 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 786 787 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 788 printf(" could not get mac address, attach failed\n"); 789 return; 790 } 791 792 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 793 794 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 795 ifp->if_softc = sc; 796 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 797 IFF_NOTRAILERS; 798 ifp->if_ioctl = atw_ioctl; 799 ifp->if_start = atw_start; 800 ifp->if_watchdog = atw_watchdog; 801 ifp->if_init = atw_init; 802 ifp->if_stop = atw_stop; 803 IFQ_SET_READY(&ifp->if_snd); 804 805 ic->ic_ifp = ifp; 806 ic->ic_phytype = IEEE80211_T_DS; 807 ic->ic_opmode = IEEE80211_M_STA; 808 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 809 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 810 811 nrate = 0; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 813 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 814 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 815 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 816 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 817 818 /* 819 * Call MI attach routines. 820 */ 821 822 if_attach(ifp); 823 ieee80211_ifattach(ic); 824 825 atw_evcnt_attach(sc); 826 827 sc->sc_newstate = ic->ic_newstate; 828 ic->ic_newstate = atw_newstate; 829 830 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 831 ic->ic_recv_mgmt = atw_recv_mgmt; 832 833 sc->sc_node_free = ic->ic_node_free; 834 ic->ic_node_free = atw_node_free; 835 836 sc->sc_node_alloc = ic->ic_node_alloc; 837 ic->ic_node_alloc = atw_node_alloc; 838 839 ic->ic_crypto.cs_key_delete = atw_key_delete; 840 ic->ic_crypto.cs_key_set = atw_key_set; 841 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 842 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 843 844 /* possibly we should fill in our own sc_send_prresp, since 845 * the ADM8211 is probably sending probe responses in ad hoc 846 * mode. 847 */ 848 849 /* complete initialization */ 850 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 851 callout_init(&sc->sc_scan_ch, 0); 852 853 #if NBPFILTER > 0 854 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 855 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 856 #endif 857 858 if (pmf_device_register1(sc->sc_dev, NULL, NULL, atw_shutdown)) 859 pmf_class_network_register(sc->sc_dev, &sc->sc_if); 860 else 861 aprint_error_dev(sc->sc_dev, 862 "couldn't establish power handler\n"); 863 864 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 865 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 866 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 867 868 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 869 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 870 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 871 872 ieee80211_announce(ic); 873 return; 874 875 /* 876 * Free any resources we've allocated during the failed attach 877 * attempt. Do this in reverse order and fall through. 878 */ 879 fail_5: 880 for (i = 0; i < ATW_NRXDESC; i++) { 881 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 882 continue; 883 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 884 } 885 fail_4: 886 for (i = 0; i < ATW_TXQUEUELEN; i++) { 887 if (sc->sc_txsoft[i].txs_dmamap == NULL) 888 continue; 889 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 890 } 891 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 892 fail_3: 893 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 894 fail_2: 895 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 896 sizeof(struct atw_control_data)); 897 fail_1: 898 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 899 fail_0: 900 return; 901 } 902 903 static struct ieee80211_node * 904 atw_node_alloc(struct ieee80211_node_table *nt) 905 { 906 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 907 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 908 909 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 910 return ni; 911 } 912 913 static void 914 atw_node_free(struct ieee80211_node *ni) 915 { 916 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 917 918 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 919 ether_sprintf(ni->ni_bssid))); 920 (*sc->sc_node_free)(ni); 921 } 922 923 924 static void 925 atw_test1_reset(struct atw_softc *sc) 926 { 927 switch (sc->sc_rev) { 928 case ATW_REVISION_BA: 929 if (1 /* XXX condition on transceiver type */) { 930 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 931 } 932 break; 933 case ATW_REVISION_CA: 934 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 935 break; 936 default: 937 break; 938 } 939 } 940 941 /* 942 * atw_reset: 943 * 944 * Perform a soft reset on the ADM8211. 945 */ 946 void 947 atw_reset(struct atw_softc *sc) 948 { 949 int i; 950 uint32_t lpc; 951 952 ATW_WRITE(sc, ATW_NAR, 0x0); 953 DELAY(atw_nar_delay); 954 955 /* Reference driver has a cryptic remark indicating that this might 956 * power-on the chip. I know that it turns off power-saving.... 957 */ 958 ATW_WRITE(sc, ATW_FRCTL, 0x0); 959 960 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 961 962 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 963 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 964 break; 965 DELAY(atw_pseudo_milli); 966 } 967 968 /* ... and then pause 100ms longer for good measure. */ 969 DELAY(atw_magic_delay1); 970 971 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 972 973 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 974 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 975 976 /* 977 * Initialize the PCI Access Register. 978 */ 979 sc->sc_busmode = ATW_PAR_PBL_8DW; 980 981 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 982 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 983 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 984 985 atw_test1_reset(sc); 986 987 /* Turn off maximum power saving, etc. */ 988 ATW_WRITE(sc, ATW_FRCTL, 0x0); 989 990 DELAY(atw_magic_delay2); 991 992 /* Recall EEPROM. */ 993 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 994 995 DELAY(atw_magic_delay4); 996 997 lpc = ATW_READ(sc, ATW_LPC); 998 999 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1000 1001 /* A reset seems to affect the SRAM contents, so put them into 1002 * a known state. 1003 */ 1004 atw_clear_sram(sc); 1005 1006 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1007 } 1008 1009 static void 1010 atw_clear_sram(struct atw_softc *sc) 1011 { 1012 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1013 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1014 /* XXX not for revision 0x20. */ 1015 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1016 } 1017 1018 /* TBD atw_init 1019 * 1020 * set MAC based on ic->ic_bss->myaddr 1021 * write WEP keys 1022 * set TX rate 1023 */ 1024 1025 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1026 * without receiving a beacon with the preferred BSSID & SSID. 1027 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1028 */ 1029 static void 1030 atw_wcsr_init(struct atw_softc *sc) 1031 { 1032 uint32_t wcsr; 1033 1034 wcsr = ATW_READ(sc, ATW_WCSR); 1035 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1036 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1037 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1038 1039 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1040 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1041 } 1042 1043 /* Turn off power management. Set Rx store-and-forward mode. */ 1044 static void 1045 atw_cmdr_init(struct atw_softc *sc) 1046 { 1047 uint32_t cmdr; 1048 cmdr = ATW_READ(sc, ATW_CMDR); 1049 cmdr &= ~ATW_CMDR_APM; 1050 cmdr |= ATW_CMDR_RTE; 1051 cmdr &= ~ATW_CMDR_DRT_MASK; 1052 cmdr |= ATW_CMDR_DRT_SF; 1053 1054 ATW_WRITE(sc, ATW_CMDR, cmdr); 1055 } 1056 1057 static void 1058 atw_tofs2_init(struct atw_softc *sc) 1059 { 1060 uint32_t tofs2; 1061 /* XXX this magic can probably be figured out from the RFMD docs */ 1062 #ifndef ATW_REFSLAVE 1063 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1064 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1065 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1066 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1067 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1068 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1069 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1070 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1071 #else 1072 /* XXX new magic from reference driver source */ 1073 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1074 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1075 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1076 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1077 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1078 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1079 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1080 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1081 #endif 1082 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1083 } 1084 1085 static void 1086 atw_nar_init(struct atw_softc *sc) 1087 { 1088 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1089 } 1090 1091 static void 1092 atw_txlmt_init(struct atw_softc *sc) 1093 { 1094 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1095 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1096 } 1097 1098 static void 1099 atw_test1_init(struct atw_softc *sc) 1100 { 1101 uint32_t test1; 1102 1103 test1 = ATW_READ(sc, ATW_TEST1); 1104 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1105 /* XXX magic 0x1 */ 1106 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1107 ATW_WRITE(sc, ATW_TEST1, test1); 1108 } 1109 1110 static void 1111 atw_rf_reset(struct atw_softc *sc) 1112 { 1113 /* XXX this resets an Intersil RF front-end? */ 1114 /* TBD condition on Intersil RFType? */ 1115 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1116 DELAY(atw_rf_delay1); 1117 ATW_WRITE(sc, ATW_SYNRF, 0); 1118 DELAY(atw_rf_delay2); 1119 } 1120 1121 /* Set 16 TU max duration for the contention-free period (CFP). */ 1122 static void 1123 atw_cfp_init(struct atw_softc *sc) 1124 { 1125 uint32_t cfpp; 1126 1127 cfpp = ATW_READ(sc, ATW_CFPP); 1128 cfpp &= ~ATW_CFPP_CFPMD; 1129 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1130 ATW_WRITE(sc, ATW_CFPP, cfpp); 1131 } 1132 1133 static void 1134 atw_tofs0_init(struct atw_softc *sc) 1135 { 1136 /* XXX I guess that the Cardbus clock is 22 MHz? 1137 * I am assuming that the role of ATW_TOFS0_USCNT is 1138 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1139 * very clear on this point. It says in the datasheet that it is 1140 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1141 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1142 * these values. These values are also the power-on default. 1143 */ 1144 ATW_WRITE(sc, ATW_TOFS0, 1145 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1146 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1147 } 1148 1149 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1150 static void 1151 atw_ifs_init(struct atw_softc *sc) 1152 { 1153 uint32_t ifst; 1154 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1155 * Go figure. 1156 */ 1157 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1158 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1159 ATW_IFST_SIFS_MASK) | 1160 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1161 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1162 1163 ATW_WRITE(sc, ATW_IFST, ifst); 1164 } 1165 1166 static void 1167 atw_response_times_init(struct atw_softc *sc) 1168 { 1169 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1170 * indicate that the MAC expects at least SIFS + MIRT microseconds 1171 * to pass after it transmits a frame that requires a response; 1172 * it waits at most SIFS + MART microseconds for the response. 1173 * Surely this is not the ACK timeout? 1174 */ 1175 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1176 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1177 } 1178 1179 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1180 * engines read and write baseband registers after Rx and before 1181 * Tx, respectively. 1182 */ 1183 static void 1184 atw_bbp_io_init(struct atw_softc *sc) 1185 { 1186 uint32_t mmiraddr2; 1187 1188 /* XXX The reference driver does this, but is it *really* 1189 * necessary? 1190 */ 1191 switch (sc->sc_rev) { 1192 case ATW_REVISION_AB: 1193 case ATW_REVISION_AF: 1194 mmiraddr2 = 0x0; 1195 break; 1196 default: 1197 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1198 mmiraddr2 &= 1199 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1200 break; 1201 } 1202 1203 switch (sc->sc_bbptype) { 1204 case ATW_BBPTYPE_INTERSIL: 1205 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1206 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1207 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1208 break; 1209 case ATW_BBPTYPE_MARVEL: 1210 /* TBD find out the Marvel settings. */ 1211 break; 1212 case ATW_BBPTYPE_RFMD: 1213 default: 1214 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1215 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1216 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1217 break; 1218 } 1219 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1220 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1221 } 1222 1223 /* 1224 * atw_init: [ ifnet interface function ] 1225 * 1226 * Initialize the interface. Must be called at splnet(). 1227 */ 1228 int 1229 atw_init(struct ifnet *ifp) 1230 { 1231 struct atw_softc *sc = ifp->if_softc; 1232 struct ieee80211com *ic = &sc->sc_ic; 1233 struct atw_txsoft *txs; 1234 struct atw_rxsoft *rxs; 1235 int i, error = 0; 1236 1237 if ((error = atw_enable(sc)) != 0) 1238 goto out; 1239 1240 /* 1241 * Cancel any pending I/O. This also resets. 1242 */ 1243 atw_stop(ifp, 0); 1244 1245 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1246 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1247 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1248 1249 atw_wcsr_init(sc); 1250 1251 atw_cmdr_init(sc); 1252 1253 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1254 * 1255 * XXX Set transmit power for ATIM, RTS, Beacon. 1256 */ 1257 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1258 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1259 1260 atw_tofs2_init(sc); 1261 1262 atw_nar_init(sc); 1263 1264 atw_txlmt_init(sc); 1265 1266 atw_test1_init(sc); 1267 1268 atw_rf_reset(sc); 1269 1270 atw_cfp_init(sc); 1271 1272 atw_tofs0_init(sc); 1273 1274 atw_ifs_init(sc); 1275 1276 /* XXX Fall asleep after one second of inactivity. 1277 * XXX A frame may only dribble in for 65536us. 1278 */ 1279 ATW_WRITE(sc, ATW_RMD, 1280 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1281 1282 atw_response_times_init(sc); 1283 1284 atw_bbp_io_init(sc); 1285 1286 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1287 1288 if ((error = atw_rf3000_init(sc)) != 0) 1289 goto out; 1290 1291 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1292 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1293 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1294 1295 /* 1296 * Initialize the transmit descriptor ring. 1297 */ 1298 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1299 for (i = 0; i < ATW_NTXDESC; i++) { 1300 sc->sc_txdescs[i].at_ctl = 0; 1301 /* no transmit chaining */ 1302 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1303 sc->sc_txdescs[i].at_buf2 = 1304 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1305 } 1306 /* use ring mode */ 1307 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1308 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1309 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1310 sc->sc_txfree = ATW_NTXDESC; 1311 sc->sc_txnext = 0; 1312 1313 /* 1314 * Initialize the transmit job descriptors. 1315 */ 1316 SIMPLEQ_INIT(&sc->sc_txfreeq); 1317 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1318 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1319 txs = &sc->sc_txsoft[i]; 1320 txs->txs_mbuf = NULL; 1321 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1322 } 1323 1324 /* 1325 * Initialize the receive descriptor and receive job 1326 * descriptor rings. 1327 */ 1328 for (i = 0; i < ATW_NRXDESC; i++) { 1329 rxs = &sc->sc_rxsoft[i]; 1330 if (rxs->rxs_mbuf == NULL) { 1331 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1332 aprint_error_dev(sc->sc_dev, "unable to allocate or map rx " 1333 "buffer %d, error = %d\n", 1334 i, error); 1335 /* 1336 * XXX Should attempt to run with fewer receive 1337 * XXX buffers instead of just failing. 1338 */ 1339 atw_rxdrain(sc); 1340 goto out; 1341 } 1342 } else 1343 atw_init_rxdesc(sc, i); 1344 } 1345 sc->sc_rxptr = 0; 1346 1347 /* 1348 * Initialize the interrupt mask and enable interrupts. 1349 */ 1350 /* normal interrupts */ 1351 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1352 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1353 1354 /* abnormal interrupts */ 1355 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1356 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1357 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1358 1359 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1360 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1361 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1362 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1363 ATW_INTR_TRT; 1364 1365 sc->sc_linkint_mask &= sc->sc_inten; 1366 sc->sc_rxint_mask &= sc->sc_inten; 1367 sc->sc_txint_mask &= sc->sc_inten; 1368 1369 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1370 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1371 1372 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1373 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1374 1375 /* 1376 * Give the transmit and receive rings to the ADM8211. 1377 */ 1378 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1379 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1380 1381 sc->sc_txthresh = 0; 1382 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1383 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1384 1385 /* common 802.11 configuration */ 1386 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1387 switch (ic->ic_opmode) { 1388 case IEEE80211_M_STA: 1389 break; 1390 case IEEE80211_M_AHDEMO: /* XXX */ 1391 case IEEE80211_M_IBSS: 1392 ic->ic_flags |= IEEE80211_F_IBSSON; 1393 /*FALLTHROUGH*/ 1394 case IEEE80211_M_HOSTAP: /* XXX */ 1395 break; 1396 case IEEE80211_M_MONITOR: /* XXX */ 1397 break; 1398 } 1399 1400 switch (ic->ic_opmode) { 1401 case IEEE80211_M_AHDEMO: 1402 case IEEE80211_M_HOSTAP: 1403 #ifndef IEEE80211_NO_HOSTAP 1404 ic->ic_bss->ni_intval = ic->ic_lintval; 1405 ic->ic_bss->ni_rssi = 0; 1406 ic->ic_bss->ni_rstamp = 0; 1407 #endif /* !IEEE80211_NO_HOSTAP */ 1408 break; 1409 default: /* XXX */ 1410 break; 1411 } 1412 1413 sc->sc_wepctl = 0; 1414 1415 atw_write_ssid(sc); 1416 atw_write_sup_rates(sc); 1417 atw_write_wep(sc); 1418 1419 ic->ic_state = IEEE80211_S_INIT; 1420 1421 /* 1422 * Set the receive filter. This will start the transmit and 1423 * receive processes. 1424 */ 1425 atw_filter_setup(sc); 1426 1427 /* 1428 * Start the receive process. 1429 */ 1430 ATW_WRITE(sc, ATW_RDR, 0x1); 1431 1432 /* 1433 * Note that the interface is now running. 1434 */ 1435 ifp->if_flags |= IFF_RUNNING; 1436 1437 /* send no beacons, yet. */ 1438 atw_start_beacon(sc, 0); 1439 1440 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1441 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1442 else 1443 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1444 out: 1445 if (error) { 1446 ifp->if_flags &= ~IFF_RUNNING; 1447 sc->sc_tx_timer = 0; 1448 ifp->if_timer = 0; 1449 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1450 } 1451 #ifdef ATW_DEBUG 1452 atw_print_regs(sc, "end of init"); 1453 #endif /* ATW_DEBUG */ 1454 1455 return (error); 1456 } 1457 1458 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1459 * 0: MAC control of RF3000/Si4126. 1460 * 1461 * Applies power, or selects RF front-end? Sets reset condition. 1462 * 1463 * TBD support non-RFMD BBP, non-SiLabs synth. 1464 */ 1465 static void 1466 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1467 { 1468 if (enable) { 1469 ATW_WRITE(sc, ATW_SYNRF, 1470 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1471 DELAY(atw_bbp_io_enable_delay); 1472 } else { 1473 ATW_WRITE(sc, ATW_SYNRF, 0); 1474 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1475 } 1476 } 1477 1478 static int 1479 atw_tune(struct atw_softc *sc) 1480 { 1481 int rc; 1482 u_int chan; 1483 struct ieee80211com *ic = &sc->sc_ic; 1484 1485 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1486 if (chan == IEEE80211_CHAN_ANY) 1487 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1488 1489 if (chan == sc->sc_cur_chan) 1490 return 0; 1491 1492 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1493 sc->sc_cur_chan, chan)); 1494 1495 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1496 1497 atw_si4126_tune(sc, chan); 1498 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1499 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1500 chan); 1501 1502 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1503 DELAY(atw_nar_delay); 1504 ATW_WRITE(sc, ATW_RDR, 0x1); 1505 1506 if (rc == 0) { 1507 sc->sc_cur_chan = chan; 1508 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1509 htole16(ic->ic_curchan->ic_freq); 1510 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1511 htole16(ic->ic_curchan->ic_flags); 1512 } 1513 1514 return rc; 1515 } 1516 1517 #ifdef ATW_SYNDEBUG 1518 static void 1519 atw_si4126_print(struct atw_softc *sc) 1520 { 1521 struct ifnet *ifp = &sc->sc_if; 1522 u_int addr, val; 1523 1524 val = 0; 1525 1526 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1527 return; 1528 1529 for (addr = 0; addr <= 8; addr++) { 1530 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1531 if (atw_si4126_read(sc, addr, &val) == 0) { 1532 printf("<unknown> (quitting print-out)\n"); 1533 break; 1534 } 1535 printf("%05x\n", val); 1536 } 1537 } 1538 #endif /* ATW_SYNDEBUG */ 1539 1540 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1541 * 1542 * The RF/IF synthesizer produces two reference frequencies for 1543 * the RF2948B transceiver. The first frequency the RF2948B requires 1544 * is two times the so-called "intermediate frequency" (IF). Since 1545 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1546 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1547 * frequency required by the transceiver is the radio frequency 1548 * (RF). This is a superheterodyne transceiver; for f(chan) the 1549 * center frequency of the channel we are tuning, RF = f(chan) - 1550 * IF. 1551 * 1552 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1553 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1554 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1555 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1556 */ 1557 static void 1558 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1559 { 1560 u_int mhz; 1561 u_int R; 1562 u_int32_t gpio; 1563 u_int16_t gain; 1564 1565 #ifdef ATW_SYNDEBUG 1566 atw_si4126_print(sc); 1567 #endif /* ATW_SYNDEBUG */ 1568 1569 if (chan == 14) 1570 mhz = 2484; 1571 else 1572 mhz = 2412 + 5 * (chan - 1); 1573 1574 /* Tune IF to 748 MHz to suit the IF LO input of the 1575 * RF2494B, which is 2 x IF. No need to set an IF divider 1576 * because an IF in 526 MHz - 952 MHz is allowed. 1577 * 1578 * XIN is 44.000 MHz, so divide it by two to get allowable 1579 * range of 2-25 MHz. SiLabs tells me that this is not 1580 * strictly necessary. 1581 */ 1582 1583 if (atw_xindiv2) 1584 R = 44; 1585 else 1586 R = 88; 1587 1588 /* Power-up RF, IF synthesizers. */ 1589 atw_si4126_write(sc, SI4126_POWER, 1590 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1591 1592 /* set LPWR, too? */ 1593 atw_si4126_write(sc, SI4126_MAIN, 1594 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1595 1596 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1597 * set KP2 to 1. 1598 * 1599 * REFDIF This is different from the reference driver, which 1600 * always sets SI4126_GAIN to 0. 1601 */ 1602 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1603 1604 atw_si4126_write(sc, SI4126_GAIN, gain); 1605 1606 /* XIN = 44 MHz. 1607 * 1608 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1609 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1610 * 1611 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1612 * so that 1496/88 * 44 MHz = 748 MHz. 1613 */ 1614 atw_si4126_write(sc, SI4126_IFN, 1496); 1615 1616 atw_si4126_write(sc, SI4126_IFR, R); 1617 1618 #ifndef ATW_REFSLAVE 1619 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1620 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1621 * which has no RF1! 1622 */ 1623 atw_si4126_write(sc, SI4126_RF1R, R); 1624 1625 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1626 #endif 1627 1628 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1629 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1630 * Now let's multiply it to mhz. So mhz - IF = N. 1631 */ 1632 atw_si4126_write(sc, SI4126_RF2R, R); 1633 1634 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1635 1636 /* wait 100us from power-up for RF, IF to settle */ 1637 DELAY(100); 1638 1639 gpio = ATW_READ(sc, ATW_GPIO); 1640 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1641 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1642 1643 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1644 /* Set a Prism RF front-end to a special mode for channel 14? 1645 * 1646 * Apparently the SMC2635W needs this, although I don't think 1647 * it has a Prism RF. 1648 */ 1649 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1650 } 1651 ATW_WRITE(sc, ATW_GPIO, gpio); 1652 1653 #ifdef ATW_SYNDEBUG 1654 atw_si4126_print(sc); 1655 #endif /* ATW_SYNDEBUG */ 1656 } 1657 1658 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1659 * diversity. 1660 * 1661 * !!! 1662 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1663 * !!! 1664 */ 1665 static int 1666 atw_rf3000_init(struct atw_softc *sc) 1667 { 1668 int rc = 0; 1669 1670 atw_bbp_io_enable(sc, 1); 1671 1672 /* CCA is acquisition sensitive */ 1673 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1674 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1675 1676 if (rc != 0) 1677 goto out; 1678 1679 /* enable diversity */ 1680 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1681 1682 if (rc != 0) 1683 goto out; 1684 1685 /* sensible setting from a binary-only driver */ 1686 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1687 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1688 1689 if (rc != 0) 1690 goto out; 1691 1692 /* magic from a binary-only driver */ 1693 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1694 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1695 1696 if (rc != 0) 1697 goto out; 1698 1699 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1700 1701 if (rc != 0) 1702 goto out; 1703 1704 /* XXX Reference driver remarks that Abocom sets this to 50. 1705 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1706 * in the "reserved" area of register RF3000_OPTIONS1. 1707 */ 1708 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1709 1710 if (rc != 0) 1711 goto out; 1712 1713 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1714 1715 if (rc != 0) 1716 goto out; 1717 1718 out: 1719 atw_bbp_io_enable(sc, 0); 1720 return rc; 1721 } 1722 1723 #ifdef ATW_BBPDEBUG 1724 static void 1725 atw_rf3000_print(struct atw_softc *sc) 1726 { 1727 struct ifnet *ifp = &sc->sc_if; 1728 u_int addr, val; 1729 1730 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1731 return; 1732 1733 for (addr = 0x01; addr <= 0x15; addr++) { 1734 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1735 if (atw_rf3000_read(sc, addr, &val) != 0) { 1736 printf("<unknown> (quitting print-out)\n"); 1737 break; 1738 } 1739 printf("%08x\n", val); 1740 } 1741 } 1742 #endif /* ATW_BBPDEBUG */ 1743 1744 /* Set the power settings on the BBP for channel `chan'. */ 1745 static int 1746 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1747 { 1748 int rc = 0; 1749 u_int32_t reg; 1750 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1751 1752 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1753 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1754 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1755 1756 /* odd channels: LSB, even channels: MSB */ 1757 if (chan % 2 == 1) { 1758 txpower &= 0xFF; 1759 lpf_cutoff &= 0xFF; 1760 lna_gs_thresh &= 0xFF; 1761 } else { 1762 txpower >>= 8; 1763 lpf_cutoff >>= 8; 1764 lna_gs_thresh >>= 8; 1765 } 1766 1767 #ifdef ATW_BBPDEBUG 1768 atw_rf3000_print(sc); 1769 #endif /* ATW_BBPDEBUG */ 1770 1771 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1772 "lna_gs_thresh %02x\n", 1773 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1774 1775 atw_bbp_io_enable(sc, 1); 1776 1777 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1778 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1779 goto out; 1780 1781 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1782 goto out; 1783 1784 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1785 goto out; 1786 1787 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1788 1789 if (rc != 0) 1790 goto out; 1791 1792 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1793 1794 if (rc != 0) 1795 goto out; 1796 1797 #ifdef ATW_BBPDEBUG 1798 atw_rf3000_print(sc); 1799 #endif /* ATW_BBPDEBUG */ 1800 1801 out: 1802 atw_bbp_io_enable(sc, 0); 1803 1804 /* set beacon, rts, atim transmit power */ 1805 reg = ATW_READ(sc, ATW_PLCPHD); 1806 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1807 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1808 ATW_PLCPHD_SERVICE_MASK); 1809 ATW_WRITE(sc, ATW_PLCPHD, reg); 1810 DELAY(atw_plcphd_delay); 1811 1812 return rc; 1813 } 1814 1815 /* Write a register on the RF3000 baseband processor using the 1816 * registers provided by the ADM8211 for this purpose. 1817 * 1818 * Return 0 on success. 1819 */ 1820 static int 1821 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1822 { 1823 u_int32_t reg; 1824 int i; 1825 1826 reg = sc->sc_bbpctl_wr | 1827 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1828 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1829 1830 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1831 ATW_WRITE(sc, ATW_BBPCTL, reg); 1832 DELAY(2 * atw_pseudo_milli); 1833 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1834 break; 1835 } 1836 1837 if (i < 0) { 1838 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1839 return ETIMEDOUT; 1840 } 1841 return 0; 1842 } 1843 1844 /* Read a register on the RF3000 baseband processor using the registers 1845 * the ADM8211 provides for this purpose. 1846 * 1847 * The 7-bit register address is addr. Record the 8-bit data in the register 1848 * in *val. 1849 * 1850 * Return 0 on success. 1851 * 1852 * XXX This does not seem to work. The ADM8211 must require more or 1853 * different magic to read the chip than to write it. Possibly some 1854 * of the magic I have derived from a binary-only driver concerns 1855 * the "chip address" (see the RF3000 manual). 1856 */ 1857 #ifdef ATW_BBPDEBUG 1858 static int 1859 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1860 { 1861 u_int32_t reg; 1862 int i; 1863 1864 for (i = 1000; --i >= 0; ) { 1865 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1866 break; 1867 DELAY(100); 1868 } 1869 1870 if (i < 0) { 1871 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1872 device_xname(sc->sc_dev)); 1873 return ETIMEDOUT; 1874 } 1875 1876 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1877 1878 ATW_WRITE(sc, ATW_BBPCTL, reg); 1879 1880 for (i = 1000; --i >= 0; ) { 1881 DELAY(100); 1882 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1883 break; 1884 } 1885 1886 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1887 1888 if (i < 0) { 1889 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1890 device_xname(sc->sc_dev), reg); 1891 return ETIMEDOUT; 1892 } 1893 if (val != NULL) 1894 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1895 return 0; 1896 } 1897 #endif /* ATW_BBPDEBUG */ 1898 1899 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1900 * provided by the ADM8211 for that purpose. 1901 * 1902 * val is 18 bits of data, and val is the 4-bit address of the register. 1903 * 1904 * Return 0 on success. 1905 */ 1906 static void 1907 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1908 { 1909 uint32_t bits, mask, reg; 1910 const int nbits = 22; 1911 1912 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1913 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1914 1915 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1916 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1917 1918 reg = ATW_SYNRF_SELSYN; 1919 /* reference driver: reset Si4126 serial bus to initial 1920 * conditions? 1921 */ 1922 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1923 ATW_WRITE(sc, ATW_SYNRF, reg); 1924 1925 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1926 if ((bits & mask) != 0) 1927 reg |= ATW_SYNRF_SYNDATA; 1928 else 1929 reg &= ~ATW_SYNRF_SYNDATA; 1930 ATW_WRITE(sc, ATW_SYNRF, reg); 1931 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1932 ATW_WRITE(sc, ATW_SYNRF, reg); 1933 } 1934 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1935 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1936 } 1937 1938 /* Read 18-bit data from the 4-bit address addr in Si4126 1939 * RF synthesizer and write the data to *val. Return 0 on success. 1940 * 1941 * XXX This does not seem to work. The ADM8211 must require more or 1942 * different magic to read the chip than to write it. 1943 */ 1944 #ifdef ATW_SYNDEBUG 1945 static int 1946 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1947 { 1948 u_int32_t reg; 1949 int i; 1950 1951 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1952 1953 for (i = 1000; --i >= 0; ) { 1954 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1955 break; 1956 DELAY(100); 1957 } 1958 1959 if (i < 0) { 1960 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1961 device_xname(sc->sc_dev)); 1962 return ETIMEDOUT; 1963 } 1964 1965 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1966 1967 ATW_WRITE(sc, ATW_SYNCTL, reg); 1968 1969 for (i = 1000; --i >= 0; ) { 1970 DELAY(100); 1971 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1972 break; 1973 } 1974 1975 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1976 1977 if (i < 0) { 1978 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1979 device_xname(sc->sc_dev), reg); 1980 return ETIMEDOUT; 1981 } 1982 if (val != NULL) 1983 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1984 ATW_SYNCTL_DATA_MASK); 1985 return 0; 1986 } 1987 #endif /* ATW_SYNDEBUG */ 1988 1989 /* XXX is the endianness correct? test. */ 1990 #define atw_calchash(addr) \ 1991 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1992 1993 /* 1994 * atw_filter_setup: 1995 * 1996 * Set the ADM8211's receive filter. 1997 */ 1998 static void 1999 atw_filter_setup(struct atw_softc *sc) 2000 { 2001 struct ieee80211com *ic = &sc->sc_ic; 2002 struct ethercom *ec = &sc->sc_ec; 2003 struct ifnet *ifp = &sc->sc_if; 2004 int hash; 2005 u_int32_t hashes[2]; 2006 struct ether_multi *enm; 2007 struct ether_multistep step; 2008 2009 /* According to comments in tlp_al981_filter_setup 2010 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2011 * multicast filter to be set while it is running. Hopefully 2012 * the ADM8211 is not the same! 2013 */ 2014 if ((ifp->if_flags & IFF_RUNNING) != 0) 2015 atw_idle(sc, ATW_NAR_SR); 2016 2017 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 2018 ifp->if_flags &= ~IFF_ALLMULTI; 2019 2020 /* XXX in scan mode, do not filter packets. Maybe this is 2021 * unnecessary. 2022 */ 2023 if (ic->ic_state == IEEE80211_S_SCAN || 2024 (ifp->if_flags & IFF_PROMISC) != 0) { 2025 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2026 goto allmulti; 2027 } 2028 2029 hashes[0] = hashes[1] = 0x0; 2030 2031 /* 2032 * Program the 64-bit multicast hash filter. 2033 */ 2034 ETHER_FIRST_MULTI(step, ec, enm); 2035 while (enm != NULL) { 2036 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2037 ETHER_ADDR_LEN) != 0) 2038 goto allmulti; 2039 2040 hash = atw_calchash(enm->enm_addrlo); 2041 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2042 ETHER_NEXT_MULTI(step, enm); 2043 sc->sc_opmode |= ATW_NAR_MM; 2044 } 2045 ifp->if_flags &= ~IFF_ALLMULTI; 2046 goto setit; 2047 2048 allmulti: 2049 sc->sc_opmode |= ATW_NAR_MM; 2050 ifp->if_flags |= IFF_ALLMULTI; 2051 hashes[0] = hashes[1] = 0xffffffff; 2052 2053 setit: 2054 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2055 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2056 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2057 DELAY(atw_nar_delay); 2058 ATW_WRITE(sc, ATW_RDR, 0x1); 2059 2060 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2061 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2062 } 2063 2064 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2065 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2066 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2067 * no beacon with the preferred BSSID and SSID in the number of 2068 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2069 */ 2070 static void 2071 atw_write_bssid(struct atw_softc *sc) 2072 { 2073 struct ieee80211com *ic = &sc->sc_ic; 2074 u_int8_t *bssid; 2075 2076 bssid = ic->ic_bss->ni_bssid; 2077 2078 ATW_WRITE(sc, ATW_BSSID0, 2079 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2080 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2081 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2082 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2083 2084 ATW_WRITE(sc, ATW_ABDA1, 2085 (ATW_READ(sc, ATW_ABDA1) & 2086 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2087 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2088 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2089 2090 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2091 ether_sprintf(sc->sc_bssid))); 2092 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2093 2094 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2095 } 2096 2097 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2098 * 16-bit word. 2099 */ 2100 static void 2101 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2102 { 2103 u_int i; 2104 u_int8_t *ptr; 2105 2106 memcpy(&sc->sc_sram[ofs], buf, buflen); 2107 2108 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2109 2110 KASSERT(buflen + ofs <= sc->sc_sramlen); 2111 2112 ptr = &sc->sc_sram[ofs]; 2113 2114 for (i = 0; i < buflen; i += 2) { 2115 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2116 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2117 DELAY(atw_writewep_delay); 2118 2119 ATW_WRITE(sc, ATW_WESK, 2120 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2121 DELAY(atw_writewep_delay); 2122 } 2123 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2124 2125 if (sc->sc_if.if_flags & IFF_DEBUG) { 2126 int n_octets = 0; 2127 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2128 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2129 for (i = 0; i < buflen; i++) { 2130 printf(" %02x", ptr[i]); 2131 if (++n_octets % 24 == 0) 2132 printf("\n"); 2133 } 2134 if (n_octets % 24 != 0) 2135 printf("\n"); 2136 } 2137 } 2138 2139 static int 2140 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2141 { 2142 struct atw_softc *sc = ic->ic_ifp->if_softc; 2143 u_int keyix = k->wk_keyix; 2144 2145 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2146 2147 if (keyix >= IEEE80211_WEP_NKID) 2148 return 0; 2149 if (k->wk_keylen != 0) 2150 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2151 2152 return 1; 2153 } 2154 2155 static int 2156 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2157 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2158 { 2159 struct atw_softc *sc = ic->ic_ifp->if_softc; 2160 2161 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2162 2163 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2164 return 0; 2165 2166 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2167 2168 return 1; 2169 } 2170 2171 static void 2172 atw_key_update_begin(struct ieee80211com *ic) 2173 { 2174 #ifdef ATW_DEBUG 2175 struct ifnet *ifp = ic->ic_ifp; 2176 struct atw_softc *sc = ifp->if_softc; 2177 #endif 2178 2179 DPRINTF(sc, ("%s:\n", __func__)); 2180 } 2181 2182 static void 2183 atw_key_update_end(struct ieee80211com *ic) 2184 { 2185 struct ifnet *ifp = ic->ic_ifp; 2186 struct atw_softc *sc = ifp->if_softc; 2187 2188 DPRINTF(sc, ("%s:\n", __func__)); 2189 2190 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2191 return; 2192 if (ATW_IS_ENABLED(sc) == 0) 2193 return; 2194 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2195 atw_write_wep(sc); 2196 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2197 DELAY(atw_nar_delay); 2198 ATW_WRITE(sc, ATW_RDR, 0x1); 2199 } 2200 2201 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2202 static void 2203 atw_write_wep(struct atw_softc *sc) 2204 { 2205 #if 0 2206 struct ieee80211com *ic = &sc->sc_ic; 2207 u_int32_t reg; 2208 int i; 2209 #endif 2210 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2211 u_int8_t buf[IEEE80211_WEP_NKID] 2212 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2213 2214 sc->sc_wepctl = 0; 2215 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2216 2217 memset(&buf[0][0], 0, sizeof(buf)); 2218 2219 #if 0 2220 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2221 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2222 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2223 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2224 buf[i][1] = ATW_WEP_ENABLED; 2225 } else { 2226 buf[i][1] = 0; 2227 continue; 2228 } 2229 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2230 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2231 ic->ic_nw_keys[i].wk_keylen - 1); 2232 } 2233 2234 reg = ATW_READ(sc, ATW_MACTEST); 2235 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2236 reg &= ~ATW_MACTEST_KEYID_MASK; 2237 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2238 ATW_WRITE(sc, ATW_MACTEST, reg); 2239 2240 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2241 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2242 2243 switch (sc->sc_rev) { 2244 case ATW_REVISION_AB: 2245 case ATW_REVISION_AF: 2246 /* Bypass WEP on Rx. */ 2247 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2248 break; 2249 default: 2250 break; 2251 } 2252 #endif 2253 2254 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2255 sizeof(buf)); 2256 2257 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2258 } 2259 2260 static void 2261 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2262 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2263 { 2264 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2265 2266 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2267 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2268 return; 2269 2270 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2271 2272 switch (subtype) { 2273 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2274 case IEEE80211_FC0_SUBTYPE_BEACON: 2275 if (ic->ic_opmode == IEEE80211_M_IBSS && 2276 ic->ic_state == IEEE80211_S_RUN) { 2277 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2278 (void)ieee80211_ibss_merge(ni); 2279 } 2280 break; 2281 default: 2282 break; 2283 } 2284 return; 2285 } 2286 2287 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2288 * In ad hoc mode, the SSID is written to the beacons sent by the 2289 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2290 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2291 * indications. 2292 */ 2293 static void 2294 atw_write_ssid(struct atw_softc *sc) 2295 { 2296 struct ieee80211com *ic = &sc->sc_ic; 2297 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2298 * it only expects the element length, not its ID. 2299 */ 2300 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2301 2302 memset(buf, 0, sizeof(buf)); 2303 buf[0] = ic->ic_bss->ni_esslen; 2304 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2305 2306 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2307 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2308 } 2309 2310 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2311 * In ad hoc mode, the supported rates are written to beacons sent by the 2312 * ADM8211. 2313 */ 2314 static void 2315 atw_write_sup_rates(struct atw_softc *sc) 2316 { 2317 struct ieee80211com *ic = &sc->sc_ic; 2318 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2319 * supported rates 2320 */ 2321 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2322 2323 memset(buf, 0, sizeof(buf)); 2324 2325 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2326 2327 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2328 ic->ic_bss->ni_rates.rs_nrates); 2329 2330 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2331 } 2332 2333 /* Start/stop sending beacons. */ 2334 void 2335 atw_start_beacon(struct atw_softc *sc, int start) 2336 { 2337 struct ieee80211com *ic = &sc->sc_ic; 2338 uint16_t chan; 2339 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2340 size_t len; 2341 2342 if (ATW_IS_ENABLED(sc) == 0) 2343 return; 2344 2345 /* start beacons */ 2346 len = sizeof(struct ieee80211_frame) + 2347 8 /* timestamp */ + 2 /* beacon interval */ + 2348 2 /* capability info */ + 2349 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2350 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2351 3 /* DS parameters */ + 2352 IEEE80211_CRC_LEN; 2353 2354 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2355 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2356 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2357 2358 ATW_WRITE(sc, ATW_BCNT, bcnt); 2359 ATW_WRITE(sc, ATW_CAP1, cap1); 2360 2361 if (!start) 2362 return; 2363 2364 /* TBD use ni_capinfo */ 2365 2366 capinfo = 0; 2367 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2368 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2369 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2370 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2371 2372 switch (ic->ic_opmode) { 2373 case IEEE80211_M_IBSS: 2374 len += 4; /* IBSS parameters */ 2375 capinfo |= IEEE80211_CAPINFO_IBSS; 2376 break; 2377 case IEEE80211_M_HOSTAP: 2378 /* XXX 6-byte minimum TIM */ 2379 len += atw_beacon_len_adjust; 2380 capinfo |= IEEE80211_CAPINFO_ESS; 2381 break; 2382 default: 2383 return; 2384 } 2385 2386 /* set listen interval 2387 * XXX do software units agree w/ hardware? 2388 */ 2389 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2390 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2391 2392 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2393 2394 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2395 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2396 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2397 2398 ATW_WRITE(sc, ATW_BCNT, bcnt); 2399 ATW_WRITE(sc, ATW_BPLI, bpli); 2400 ATW_WRITE(sc, ATW_CAP0, cap0); 2401 ATW_WRITE(sc, ATW_CAP1, cap1); 2402 2403 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2404 device_xname(sc->sc_dev), bcnt)); 2405 2406 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2407 device_xname(sc->sc_dev), cap1)); 2408 } 2409 2410 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2411 static inline uint32_t 2412 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2413 { 2414 /* Following the reference driver's lead, I compute 2415 * 2416 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2417 * 2418 * without using 64-bit arithmetic, using the following 2419 * relationship: 2420 * 2421 * (0x100000000 * H + L) % m 2422 * = ((0x100000000 % m) * H + L) % m 2423 * = (((0xffffffff + 1) % m) * H + L) % m 2424 * = ((0xffffffff % m + 1 % m) * H + L) % m 2425 * = ((0xffffffff % m + 1) * H + L) % m 2426 */ 2427 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2428 } 2429 2430 static uint64_t 2431 atw_get_tsft(struct atw_softc *sc) 2432 { 2433 int i; 2434 uint32_t tsfth, tsftl; 2435 for (i = 0; i < 2; i++) { 2436 tsfth = ATW_READ(sc, ATW_TSFTH); 2437 tsftl = ATW_READ(sc, ATW_TSFTL); 2438 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2439 break; 2440 } 2441 return ((uint64_t)tsfth << 32) | tsftl; 2442 } 2443 2444 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2445 * the ieee80211com. 2446 * 2447 * Predict the next target beacon transmission time (TBTT) and 2448 * write it to the ADM8211. 2449 */ 2450 static void 2451 atw_predict_beacon(struct atw_softc *sc) 2452 { 2453 #define TBTTOFS 20 /* TU */ 2454 2455 struct ieee80211com *ic = &sc->sc_ic; 2456 uint64_t tsft; 2457 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2458 union { 2459 uint64_t word; 2460 uint8_t tstamp[8]; 2461 } u; 2462 2463 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2464 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2465 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2466 tsft = atw_get_tsft(sc); 2467 u.word = htole64(tsft); 2468 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2469 sizeof(ic->ic_bss->ni_tstamp)); 2470 } else 2471 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2472 2473 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2474 2475 tsftl = tsft & 0xFFFFFFFF; 2476 tsfth = tsft >> 32; 2477 2478 /* We sent/received the last beacon `past' microseconds 2479 * after the interval divided the TSF timer. 2480 */ 2481 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2482 2483 /* Skip ten beacons so that the TBTT cannot pass before 2484 * we've programmed it. Ten is an arbitrary number. 2485 */ 2486 tbtt = past_even + ival * 10; 2487 2488 ATW_WRITE(sc, ATW_TOFS1, 2489 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2490 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2491 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2492 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2493 #undef TBTTOFS 2494 } 2495 2496 static void 2497 atw_next_scan(void *arg) 2498 { 2499 struct atw_softc *sc = arg; 2500 struct ieee80211com *ic = &sc->sc_ic; 2501 int s; 2502 2503 /* don't call atw_start w/o network interrupts blocked */ 2504 s = splnet(); 2505 if (ic->ic_state == IEEE80211_S_SCAN) 2506 ieee80211_next_scan(ic); 2507 splx(s); 2508 } 2509 2510 /* Synchronize the hardware state with the software state. */ 2511 static int 2512 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2513 { 2514 struct ifnet *ifp = ic->ic_ifp; 2515 struct atw_softc *sc = ifp->if_softc; 2516 enum ieee80211_state ostate; 2517 int error = 0; 2518 2519 ostate = ic->ic_state; 2520 callout_stop(&sc->sc_scan_ch); 2521 2522 switch (nstate) { 2523 case IEEE80211_S_AUTH: 2524 case IEEE80211_S_ASSOC: 2525 atw_write_bssid(sc); 2526 error = atw_tune(sc); 2527 break; 2528 case IEEE80211_S_INIT: 2529 callout_stop(&sc->sc_scan_ch); 2530 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2531 atw_start_beacon(sc, 0); 2532 break; 2533 case IEEE80211_S_SCAN: 2534 error = atw_tune(sc); 2535 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2536 atw_next_scan, sc); 2537 break; 2538 case IEEE80211_S_RUN: 2539 error = atw_tune(sc); 2540 atw_write_bssid(sc); 2541 atw_write_ssid(sc); 2542 atw_write_sup_rates(sc); 2543 2544 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2545 ic->ic_opmode == IEEE80211_M_MONITOR) 2546 break; 2547 2548 /* set listen interval 2549 * XXX do software units agree w/ hardware? 2550 */ 2551 ATW_WRITE(sc, ATW_BPLI, 2552 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2553 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2554 ATW_BPLI_LI_MASK)); 2555 2556 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2557 ATW_READ(sc, ATW_BPLI))); 2558 2559 atw_predict_beacon(sc); 2560 2561 switch (ic->ic_opmode) { 2562 case IEEE80211_M_AHDEMO: 2563 case IEEE80211_M_HOSTAP: 2564 case IEEE80211_M_IBSS: 2565 atw_start_beacon(sc, 1); 2566 break; 2567 case IEEE80211_M_MONITOR: 2568 case IEEE80211_M_STA: 2569 break; 2570 } 2571 2572 break; 2573 } 2574 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2575 } 2576 2577 /* 2578 * atw_add_rxbuf: 2579 * 2580 * Add a receive buffer to the indicated descriptor. 2581 */ 2582 int 2583 atw_add_rxbuf(struct atw_softc *sc, int idx) 2584 { 2585 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2586 struct mbuf *m; 2587 int error; 2588 2589 MGETHDR(m, M_DONTWAIT, MT_DATA); 2590 if (m == NULL) 2591 return (ENOBUFS); 2592 2593 MCLGET(m, M_DONTWAIT); 2594 if ((m->m_flags & M_EXT) == 0) { 2595 m_freem(m); 2596 return (ENOBUFS); 2597 } 2598 2599 if (rxs->rxs_mbuf != NULL) 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 2602 rxs->rxs_mbuf = m; 2603 2604 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2606 BUS_DMA_READ|BUS_DMA_NOWAIT); 2607 if (error) { 2608 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2609 idx, error); 2610 panic("atw_add_rxbuf"); /* XXX */ 2611 } 2612 2613 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2614 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2615 2616 atw_init_rxdesc(sc, idx); 2617 2618 return (0); 2619 } 2620 2621 /* 2622 * Release any queued transmit buffers. 2623 */ 2624 void 2625 atw_txdrain(struct atw_softc *sc) 2626 { 2627 struct atw_txsoft *txs; 2628 2629 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2630 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2631 if (txs->txs_mbuf != NULL) { 2632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2633 m_freem(txs->txs_mbuf); 2634 txs->txs_mbuf = NULL; 2635 } 2636 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2637 sc->sc_txfree += txs->txs_ndescs; 2638 } 2639 2640 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2641 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2642 sc->sc_txfree != ATW_NTXDESC)); 2643 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2644 sc->sc_tx_timer = 0; 2645 } 2646 2647 /* 2648 * atw_stop: [ ifnet interface function ] 2649 * 2650 * Stop transmission on the interface. 2651 */ 2652 void 2653 atw_stop(struct ifnet *ifp, int disable) 2654 { 2655 struct atw_softc *sc = ifp->if_softc; 2656 struct ieee80211com *ic = &sc->sc_ic; 2657 2658 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2659 2660 /* Disable interrupts. */ 2661 ATW_WRITE(sc, ATW_IER, 0); 2662 2663 /* Stop the transmit and receive processes. */ 2664 sc->sc_opmode = 0; 2665 ATW_WRITE(sc, ATW_NAR, 0); 2666 DELAY(atw_nar_delay); 2667 ATW_WRITE(sc, ATW_TDBD, 0); 2668 ATW_WRITE(sc, ATW_TDBP, 0); 2669 ATW_WRITE(sc, ATW_RDB, 0); 2670 2671 atw_txdrain(sc); 2672 2673 /* 2674 * Mark the interface down and cancel the watchdog timer. 2675 */ 2676 ifp->if_flags &= ~IFF_RUNNING; 2677 ifp->if_timer = 0; 2678 2679 if (disable) { 2680 atw_rxdrain(sc); 2681 atw_disable(sc); 2682 } else 2683 atw_reset(sc); 2684 } 2685 2686 /* 2687 * atw_rxdrain: 2688 * 2689 * Drain the receive queue. 2690 */ 2691 void 2692 atw_rxdrain(struct atw_softc *sc) 2693 { 2694 struct atw_rxsoft *rxs; 2695 int i; 2696 2697 for (i = 0; i < ATW_NRXDESC; i++) { 2698 rxs = &sc->sc_rxsoft[i]; 2699 if (rxs->rxs_mbuf == NULL) 2700 continue; 2701 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2702 m_freem(rxs->rxs_mbuf); 2703 rxs->rxs_mbuf = NULL; 2704 } 2705 } 2706 2707 /* 2708 * atw_detach: 2709 * 2710 * Detach an ADM8211 interface. 2711 */ 2712 int 2713 atw_detach(struct atw_softc *sc) 2714 { 2715 struct ifnet *ifp = &sc->sc_if; 2716 struct atw_rxsoft *rxs; 2717 struct atw_txsoft *txs; 2718 int i; 2719 2720 /* 2721 * Succeed now if there isn't any work to do. 2722 */ 2723 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2724 return (0); 2725 2726 pmf_device_deregister(sc->sc_dev); 2727 2728 callout_stop(&sc->sc_scan_ch); 2729 2730 ieee80211_ifdetach(&sc->sc_ic); 2731 if_detach(ifp); 2732 2733 for (i = 0; i < ATW_NRXDESC; i++) { 2734 rxs = &sc->sc_rxsoft[i]; 2735 if (rxs->rxs_mbuf != NULL) { 2736 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2737 m_freem(rxs->rxs_mbuf); 2738 rxs->rxs_mbuf = NULL; 2739 } 2740 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2741 } 2742 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2743 txs = &sc->sc_txsoft[i]; 2744 if (txs->txs_mbuf != NULL) { 2745 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2746 m_freem(txs->txs_mbuf); 2747 txs->txs_mbuf = NULL; 2748 } 2749 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2750 } 2751 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2752 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2753 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2754 sizeof(struct atw_control_data)); 2755 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2756 2757 if (sc->sc_srom) 2758 free(sc->sc_srom, M_DEVBUF); 2759 2760 atw_evcnt_detach(sc); 2761 2762 return (0); 2763 } 2764 2765 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2766 bool 2767 atw_shutdown(device_t self, int flags) 2768 { 2769 struct atw_softc *sc = device_private(self); 2770 2771 atw_stop(&sc->sc_if, 1); 2772 return true; 2773 } 2774 2775 #if 0 2776 static void 2777 atw_workaround1(struct atw_softc *sc) 2778 { 2779 uint32_t test1; 2780 2781 test1 = ATW_READ(sc, ATW_TEST1); 2782 2783 sc->sc_misc_ev.ev_count++; 2784 2785 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2786 sc->sc_rxpkt1in_ev.ev_count++; 2787 return; 2788 } 2789 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2790 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2791 sc->sc_rxamatch_ev.ev_count++; 2792 return; 2793 } 2794 sc->sc_workaround1_ev.ev_count++; 2795 (void)atw_init(&sc->sc_if); 2796 } 2797 #endif 2798 2799 int 2800 atw_intr(void *arg) 2801 { 2802 struct atw_softc *sc = arg; 2803 struct ifnet *ifp = &sc->sc_if; 2804 u_int32_t status, rxstatus, txstatus, linkstatus; 2805 int handled = 0, txthresh; 2806 2807 #ifdef DEBUG 2808 if (ATW_IS_ENABLED(sc) == 0) 2809 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2810 #endif 2811 2812 /* 2813 * If the interface isn't running, the interrupt couldn't 2814 * possibly have come from us. 2815 */ 2816 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2817 !device_is_active(sc->sc_dev)) 2818 return (0); 2819 2820 for (;;) { 2821 status = ATW_READ(sc, ATW_STSR); 2822 2823 if (status) 2824 ATW_WRITE(sc, ATW_STSR, status); 2825 2826 #ifdef ATW_DEBUG 2827 #define PRINTINTR(flag) do { \ 2828 if ((status & flag) != 0) { \ 2829 printf("%s" #flag, delim); \ 2830 delim = ","; \ 2831 } \ 2832 } while (0) 2833 2834 if (atw_debug > 1 && status) { 2835 const char *delim = "<"; 2836 2837 printf("%s: reg[STSR] = %x", 2838 device_xname(sc->sc_dev), status); 2839 2840 PRINTINTR(ATW_INTR_FBE); 2841 PRINTINTR(ATW_INTR_LINKOFF); 2842 PRINTINTR(ATW_INTR_LINKON); 2843 PRINTINTR(ATW_INTR_RCI); 2844 PRINTINTR(ATW_INTR_RDU); 2845 PRINTINTR(ATW_INTR_REIS); 2846 PRINTINTR(ATW_INTR_RPS); 2847 PRINTINTR(ATW_INTR_TCI); 2848 PRINTINTR(ATW_INTR_TDU); 2849 PRINTINTR(ATW_INTR_TLT); 2850 PRINTINTR(ATW_INTR_TPS); 2851 PRINTINTR(ATW_INTR_TRT); 2852 PRINTINTR(ATW_INTR_TUF); 2853 PRINTINTR(ATW_INTR_BCNTC); 2854 PRINTINTR(ATW_INTR_ATIME); 2855 PRINTINTR(ATW_INTR_TBTT); 2856 PRINTINTR(ATW_INTR_TSCZ); 2857 PRINTINTR(ATW_INTR_TSFTF); 2858 printf(">\n"); 2859 } 2860 #undef PRINTINTR 2861 #endif /* ATW_DEBUG */ 2862 2863 if ((status & sc->sc_inten) == 0) 2864 break; 2865 2866 handled = 1; 2867 2868 rxstatus = status & sc->sc_rxint_mask; 2869 txstatus = status & sc->sc_txint_mask; 2870 linkstatus = status & sc->sc_linkint_mask; 2871 2872 if (linkstatus) { 2873 atw_linkintr(sc, linkstatus); 2874 } 2875 2876 if (rxstatus) { 2877 /* Grab any new packets. */ 2878 atw_rxintr(sc); 2879 2880 if (rxstatus & ATW_INTR_RDU) { 2881 printf("%s: receive ring overrun\n", 2882 device_xname(sc->sc_dev)); 2883 /* Get the receive process going again. */ 2884 ATW_WRITE(sc, ATW_RDR, 0x1); 2885 } 2886 } 2887 2888 if (txstatus) { 2889 /* Sweep up transmit descriptors. */ 2890 atw_txintr(sc, txstatus); 2891 2892 if (txstatus & ATW_INTR_TLT) { 2893 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2894 device_xname(sc->sc_dev))); 2895 (void)atw_init(&sc->sc_if); 2896 } 2897 2898 if (txstatus & ATW_INTR_TRT) { 2899 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2900 device_xname(sc->sc_dev))); 2901 } 2902 2903 /* If Tx under-run, increase our transmit threshold 2904 * if another is available. 2905 */ 2906 txthresh = sc->sc_txthresh + 1; 2907 if ((txstatus & ATW_INTR_TUF) && 2908 sc->sc_txth[txthresh].txth_name != NULL) { 2909 /* Idle the transmit process. */ 2910 atw_idle(sc, ATW_NAR_ST); 2911 2912 sc->sc_txthresh = txthresh; 2913 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2914 sc->sc_opmode |= 2915 sc->sc_txth[txthresh].txth_opmode; 2916 printf("%s: transmit underrun; new " 2917 "threshold: %s\n", device_xname(sc->sc_dev), 2918 sc->sc_txth[txthresh].txth_name); 2919 2920 /* Set the new threshold and restart 2921 * the transmit process. 2922 */ 2923 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2924 DELAY(atw_nar_delay); 2925 ATW_WRITE(sc, ATW_TDR, 0x1); 2926 /* XXX Log every Nth underrun from 2927 * XXX now on? 2928 */ 2929 } 2930 } 2931 2932 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2933 if (status & ATW_INTR_TPS) 2934 printf("%s: transmit process stopped\n", 2935 device_xname(sc->sc_dev)); 2936 if (status & ATW_INTR_RPS) 2937 printf("%s: receive process stopped\n", 2938 device_xname(sc->sc_dev)); 2939 (void)atw_init(ifp); 2940 break; 2941 } 2942 2943 if (status & ATW_INTR_FBE) { 2944 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2945 (void)atw_init(ifp); 2946 break; 2947 } 2948 2949 /* 2950 * Not handled: 2951 * 2952 * Transmit buffer unavailable -- normal 2953 * condition, nothing to do, really. 2954 * 2955 * Early receive interrupt -- not available on 2956 * all chips, we just use RI. We also only 2957 * use single-segment receive DMA, so this 2958 * is mostly useless. 2959 * 2960 * TBD others 2961 */ 2962 } 2963 2964 /* Try to get more packets going. */ 2965 atw_start(ifp); 2966 2967 return (handled); 2968 } 2969 2970 /* 2971 * atw_idle: 2972 * 2973 * Cause the transmit and/or receive processes to go idle. 2974 * 2975 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2976 * process in STSR if I clear SR or ST after the process has already 2977 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2978 * do not seem to be too reliable. Perhaps I have the sense of the 2979 * Rx bits switched with the Tx bits? 2980 */ 2981 void 2982 atw_idle(struct atw_softc *sc, u_int32_t bits) 2983 { 2984 u_int32_t ackmask = 0, opmode, stsr, test0; 2985 int i, s; 2986 2987 s = splnet(); 2988 2989 opmode = sc->sc_opmode & ~bits; 2990 2991 if (bits & ATW_NAR_SR) 2992 ackmask |= ATW_INTR_RPS; 2993 2994 if (bits & ATW_NAR_ST) { 2995 ackmask |= ATW_INTR_TPS; 2996 /* set ATW_NAR_HF to flush TX FIFO. */ 2997 opmode |= ATW_NAR_HF; 2998 } 2999 3000 ATW_WRITE(sc, ATW_NAR, opmode); 3001 DELAY(atw_nar_delay); 3002 3003 for (i = 0; i < 1000; i++) { 3004 stsr = ATW_READ(sc, ATW_STSR); 3005 if ((stsr & ackmask) == ackmask) 3006 break; 3007 DELAY(10); 3008 } 3009 3010 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3011 3012 if ((stsr & ackmask) == ackmask) 3013 goto out; 3014 3015 test0 = ATW_READ(sc, ATW_TEST0); 3016 3017 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3018 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3019 printf("%s: transmit process not idle [%s]\n", 3020 device_xname(sc->sc_dev), 3021 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3022 printf("%s: bits %08x test0 %08x stsr %08x\n", 3023 device_xname(sc->sc_dev), bits, test0, stsr); 3024 } 3025 3026 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3027 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3028 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3029 device_xname(sc->sc_dev), 3030 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3031 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3032 device_xname(sc->sc_dev), bits, test0, stsr)); 3033 } 3034 out: 3035 if ((bits & ATW_NAR_ST) != 0) 3036 atw_txdrain(sc); 3037 splx(s); 3038 return; 3039 } 3040 3041 /* 3042 * atw_linkintr: 3043 * 3044 * Helper; handle link-status interrupts. 3045 */ 3046 void 3047 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3048 { 3049 struct ieee80211com *ic = &sc->sc_ic; 3050 3051 if (ic->ic_state != IEEE80211_S_RUN) 3052 return; 3053 3054 if (linkstatus & ATW_INTR_LINKON) { 3055 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3056 sc->sc_rescan_timer = 0; 3057 } else if (linkstatus & ATW_INTR_LINKOFF) { 3058 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3059 if (ic->ic_opmode != IEEE80211_M_STA) 3060 return; 3061 sc->sc_rescan_timer = 3; 3062 sc->sc_if.if_timer = 1; 3063 } 3064 } 3065 3066 static inline int 3067 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3068 { 3069 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3070 return 0; 3071 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3072 return 0; 3073 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3074 } 3075 3076 /* 3077 * atw_rxintr: 3078 * 3079 * Helper; handle receive interrupts. 3080 */ 3081 void 3082 atw_rxintr(struct atw_softc *sc) 3083 { 3084 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3085 struct ieee80211com *ic = &sc->sc_ic; 3086 struct ieee80211_node *ni; 3087 struct ieee80211_frame_min *wh; 3088 struct ifnet *ifp = &sc->sc_if; 3089 struct atw_rxsoft *rxs; 3090 struct mbuf *m; 3091 u_int32_t rxstat; 3092 int i, len, rate, rate0; 3093 u_int32_t rssi, ctlrssi; 3094 3095 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3096 rxs = &sc->sc_rxsoft[i]; 3097 3098 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3099 3100 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3101 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3102 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3103 3104 if (rxstat & ATW_RXSTAT_OWN) { 3105 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3106 break; 3107 } 3108 3109 sc->sc_rxptr = ATW_NEXTRX(i); 3110 3111 DPRINTF3(sc, 3112 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3113 device_xname(sc->sc_dev), 3114 rxstat, ctlrssi, 3115 le32toh(sc->sc_rxdescs[i].ar_buf1), 3116 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3117 3118 /* 3119 * Make sure the packet fits in one buffer. This should 3120 * always be the case. 3121 */ 3122 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3123 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3124 printf("%s: incoming packet spilled, resetting\n", 3125 device_xname(sc->sc_dev)); 3126 (void)atw_init(ifp); 3127 return; 3128 } 3129 3130 /* 3131 * If an error occurred, update stats, clear the status 3132 * word, and leave the packet buffer in place. It will 3133 * simply be reused the next time the ring comes around. 3134 */ 3135 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3136 #define PRINTERR(bit, str) \ 3137 if (rxstat & (bit)) \ 3138 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3139 str) 3140 ifp->if_ierrors++; 3141 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3142 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3143 #if 0 3144 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3145 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3146 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3147 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3148 #endif 3149 #undef PRINTERR 3150 atw_init_rxdesc(sc, i); 3151 continue; 3152 } 3153 3154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3156 3157 /* 3158 * No errors; receive the packet. Note the ADM8211 3159 * includes the CRC in promiscuous mode. 3160 */ 3161 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3162 3163 /* 3164 * Allocate a new mbuf cluster. If that fails, we are 3165 * out of memory, and must drop the packet and recycle 3166 * the buffer that's already attached to this descriptor. 3167 */ 3168 m = rxs->rxs_mbuf; 3169 if (atw_add_rxbuf(sc, i) != 0) { 3170 ifp->if_ierrors++; 3171 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3172 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3173 atw_init_rxdesc(sc, i); 3174 continue; 3175 } 3176 3177 ifp->if_ipackets++; 3178 m->m_pkthdr.rcvif = ifp; 3179 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3180 3181 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3182 3183 /* The RSSI comes straight from a register in the 3184 * baseband processor. I know that for the RF3000, 3185 * the RSSI register also contains the antenna-selection 3186 * bits. Mask those off. 3187 * 3188 * TBD Treat other basebands. 3189 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3190 */ 3191 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3192 rssi = ctlrssi & RF3000_RSSI_MASK; 3193 else 3194 rssi = ctlrssi; 3195 3196 #if NBPFILTER > 0 3197 /* Pass this up to any BPF listeners. */ 3198 if (sc->sc_radiobpf != NULL) { 3199 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3200 3201 tap->ar_rate = rate; 3202 3203 /* TBD verify units are dB */ 3204 tap->ar_antsignal = (int)rssi; 3205 if (sc->sc_opmode & ATW_NAR_PR) 3206 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3207 else 3208 tap->ar_flags = 0; 3209 3210 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3211 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3212 3213 bpf_mtap2(sc->sc_radiobpf, tap, 3214 sizeof(sc->sc_rxtapu), m); 3215 } 3216 #endif /* NBPFILTER > 0 */ 3217 3218 sc->sc_recv_ev.ev_count++; 3219 3220 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3221 if (rxstat & ATW_RXSTAT_CRC16E) 3222 sc->sc_crc16e_ev.ev_count++; 3223 if (rxstat & ATW_RXSTAT_CRC32E) 3224 sc->sc_crc32e_ev.ev_count++; 3225 if (rxstat & ATW_RXSTAT_ICVE) 3226 sc->sc_icve_ev.ev_count++; 3227 if (rxstat & ATW_RXSTAT_SFDE) 3228 sc->sc_sfde_ev.ev_count++; 3229 if (rxstat & ATW_RXSTAT_SIGE) 3230 sc->sc_sige_ev.ev_count++; 3231 ifp->if_ierrors++; 3232 m_freem(m); 3233 continue; 3234 } 3235 3236 if (sc->sc_opmode & ATW_NAR_PR) 3237 m_adj(m, -IEEE80211_CRC_LEN); 3238 3239 wh = mtod(m, struct ieee80211_frame_min *); 3240 ni = ieee80211_find_rxnode(ic, wh); 3241 #if 0 3242 if (atw_hw_decrypted(sc, wh)) { 3243 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3244 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3245 } 3246 #endif 3247 ieee80211_input(ic, m, ni, (int)rssi, 0); 3248 ieee80211_free_node(ni); 3249 } 3250 } 3251 3252 /* 3253 * atw_txintr: 3254 * 3255 * Helper; handle transmit interrupts. 3256 */ 3257 void 3258 atw_txintr(struct atw_softc *sc, uint32_t status) 3259 { 3260 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3261 struct ifnet *ifp = &sc->sc_if; 3262 struct atw_txsoft *txs; 3263 u_int32_t txstat; 3264 3265 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3266 device_xname(sc->sc_dev), sc->sc_flags)); 3267 3268 /* 3269 * Go through our Tx list and free mbufs for those 3270 * frames that have been transmitted. 3271 */ 3272 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3273 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3274 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3275 3276 #ifdef ATW_DEBUG 3277 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3278 int i; 3279 printf(" txsoft %p transmit chain:\n", txs); 3280 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3281 txs->txs_ndescs - 1, 3282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3283 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3284 printf(" descriptor %d:\n", i); 3285 printf(" at_status: 0x%08x\n", 3286 le32toh(sc->sc_txdescs[i].at_stat)); 3287 printf(" at_flags: 0x%08x\n", 3288 le32toh(sc->sc_txdescs[i].at_flags)); 3289 printf(" at_buf1: 0x%08x\n", 3290 le32toh(sc->sc_txdescs[i].at_buf1)); 3291 printf(" at_buf2: 0x%08x\n", 3292 le32toh(sc->sc_txdescs[i].at_buf2)); 3293 if (i == txs->txs_lastdesc) 3294 break; 3295 } 3296 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3297 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3298 } 3299 #endif 3300 3301 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3302 if (txstat & ATW_TXSTAT_OWN) { 3303 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3304 BUS_DMASYNC_PREREAD); 3305 break; 3306 } 3307 3308 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3309 3310 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3311 0, txs->txs_dmamap->dm_mapsize, 3312 BUS_DMASYNC_POSTWRITE); 3313 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3314 m_freem(txs->txs_mbuf); 3315 txs->txs_mbuf = NULL; 3316 3317 sc->sc_txfree += txs->txs_ndescs; 3318 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3319 3320 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3321 sc->sc_tx_timer = 0; 3322 ifp->if_flags &= ~IFF_OACTIVE; 3323 3324 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3325 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3326 snprintb(txstat_buf, sizeof(txstat_buf), 3327 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3328 printf("%s: txstat %s %" __PRIuBITS "\n", 3329 device_xname(sc->sc_dev), txstat_buf, 3330 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3331 } 3332 3333 sc->sc_xmit_ev.ev_count++; 3334 3335 /* 3336 * Check for errors and collisions. 3337 */ 3338 if (txstat & ATW_TXSTAT_TUF) 3339 sc->sc_tuf_ev.ev_count++; 3340 if (txstat & ATW_TXSTAT_TLT) 3341 sc->sc_tlt_ev.ev_count++; 3342 if (txstat & ATW_TXSTAT_TRT) 3343 sc->sc_trt_ev.ev_count++; 3344 if (txstat & ATW_TXSTAT_TRO) 3345 sc->sc_tro_ev.ev_count++; 3346 if (txstat & ATW_TXSTAT_SOFBR) 3347 sc->sc_sofbr_ev.ev_count++; 3348 3349 if ((txstat & ATW_TXSTAT_ES) == 0) 3350 ifp->if_collisions += 3351 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3352 else 3353 ifp->if_oerrors++; 3354 3355 ifp->if_opackets++; 3356 } 3357 3358 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3359 } 3360 3361 /* 3362 * atw_watchdog: [ifnet interface function] 3363 * 3364 * Watchdog timer handler. 3365 */ 3366 void 3367 atw_watchdog(struct ifnet *ifp) 3368 { 3369 struct atw_softc *sc = ifp->if_softc; 3370 struct ieee80211com *ic = &sc->sc_ic; 3371 3372 ifp->if_timer = 0; 3373 if (ATW_IS_ENABLED(sc) == 0) 3374 return; 3375 3376 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3377 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3378 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3379 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3380 printf("%s: transmit timeout\n", ifp->if_xname); 3381 ifp->if_oerrors++; 3382 (void)atw_init(ifp); 3383 atw_start(ifp); 3384 } 3385 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3386 ifp->if_timer = 1; 3387 ieee80211_watchdog(ic); 3388 } 3389 3390 static void 3391 atw_evcnt_detach(struct atw_softc *sc) 3392 { 3393 evcnt_detach(&sc->sc_sige_ev); 3394 evcnt_detach(&sc->sc_sfde_ev); 3395 evcnt_detach(&sc->sc_icve_ev); 3396 evcnt_detach(&sc->sc_crc32e_ev); 3397 evcnt_detach(&sc->sc_crc16e_ev); 3398 evcnt_detach(&sc->sc_recv_ev); 3399 3400 evcnt_detach(&sc->sc_tuf_ev); 3401 evcnt_detach(&sc->sc_tro_ev); 3402 evcnt_detach(&sc->sc_trt_ev); 3403 evcnt_detach(&sc->sc_tlt_ev); 3404 evcnt_detach(&sc->sc_sofbr_ev); 3405 evcnt_detach(&sc->sc_xmit_ev); 3406 3407 evcnt_detach(&sc->sc_rxpkt1in_ev); 3408 evcnt_detach(&sc->sc_rxamatch_ev); 3409 evcnt_detach(&sc->sc_workaround1_ev); 3410 evcnt_detach(&sc->sc_misc_ev); 3411 } 3412 3413 static void 3414 atw_evcnt_attach(struct atw_softc *sc) 3415 { 3416 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3417 NULL, sc->sc_if.if_xname, "recv"); 3418 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3419 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3420 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3421 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3422 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3423 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3424 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3425 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3426 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3427 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3428 3429 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3430 NULL, sc->sc_if.if_xname, "xmit"); 3431 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3432 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3433 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3434 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3435 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3436 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3437 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3438 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3439 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3440 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3441 3442 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3443 NULL, sc->sc_if.if_xname, "misc"); 3444 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3445 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3446 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3447 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3448 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3449 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3450 } 3451 3452 #ifdef ATW_DEBUG 3453 static void 3454 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3455 { 3456 struct atw_softc *sc = ifp->if_softc; 3457 struct mbuf *m; 3458 int i, noctets = 0; 3459 3460 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3461 m0->m_pkthdr.len); 3462 3463 for (m = m0; m; m = m->m_next) { 3464 if (m->m_len == 0) 3465 continue; 3466 for (i = 0; i < m->m_len; i++) { 3467 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3468 if (++noctets % 24 == 0) 3469 printf("\n"); 3470 } 3471 } 3472 printf("%s%s: %d bytes emitted\n", 3473 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3474 } 3475 #endif /* ATW_DEBUG */ 3476 3477 /* 3478 * atw_start: [ifnet interface function] 3479 * 3480 * Start packet transmission on the interface. 3481 */ 3482 void 3483 atw_start(struct ifnet *ifp) 3484 { 3485 struct atw_softc *sc = ifp->if_softc; 3486 struct ieee80211_key *k; 3487 struct ieee80211com *ic = &sc->sc_ic; 3488 struct ieee80211_node *ni; 3489 struct ieee80211_frame_min *whm; 3490 struct ieee80211_frame *wh; 3491 struct atw_frame *hh; 3492 uint16_t hdrctl; 3493 struct mbuf *m0, *m; 3494 struct atw_txsoft *txs, *last_txs; 3495 struct atw_txdesc *txd; 3496 int npkt, rate; 3497 bus_dmamap_t dmamap; 3498 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3499 3500 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3501 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3502 3503 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3504 return; 3505 3506 /* 3507 * Remember the previous number of free descriptors and 3508 * the first descriptor we'll use. 3509 */ 3510 ofree = sc->sc_txfree; 3511 firsttx = lasttx = sc->sc_txnext; 3512 3513 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3514 device_xname(sc->sc_dev), ofree, firsttx)); 3515 3516 /* 3517 * Loop through the send queue, setting up transmit descriptors 3518 * until we drain the queue, or use up all available transmit 3519 * descriptors. 3520 */ 3521 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3522 sc->sc_txfree != 0) { 3523 3524 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3525 3526 /* 3527 * Grab a packet off the management queue, if it 3528 * is not empty. Otherwise, from the data queue. 3529 */ 3530 IF_DEQUEUE(&ic->ic_mgtq, m0); 3531 if (m0 != NULL) { 3532 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3533 m0->m_pkthdr.rcvif = NULL; 3534 } else if (ic->ic_state != IEEE80211_S_RUN) 3535 break; /* send no data until associated */ 3536 else { 3537 IFQ_DEQUEUE(&ifp->if_snd, m0); 3538 if (m0 == NULL) 3539 break; 3540 #if NBPFILTER > 0 3541 if (ifp->if_bpf != NULL) 3542 bpf_mtap(ifp->if_bpf, m0); 3543 #endif /* NBPFILTER > 0 */ 3544 ni = ieee80211_find_txnode(ic, 3545 mtod(m0, struct ether_header *)->ether_dhost); 3546 if (ni == NULL) { 3547 ifp->if_oerrors++; 3548 break; 3549 } 3550 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3551 ieee80211_free_node(ni); 3552 ifp->if_oerrors++; 3553 break; 3554 } 3555 } 3556 3557 rate = MAX(ieee80211_get_rate(ni), 2); 3558 3559 whm = mtod(m0, struct ieee80211_frame_min *); 3560 3561 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3562 k = NULL; 3563 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3564 m_freem(m0); 3565 ieee80211_free_node(ni); 3566 ifp->if_oerrors++; 3567 break; 3568 } 3569 #if 0 3570 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3571 m0->m_pkthdr.len > ic->ic_fragthreshold) 3572 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3573 #endif 3574 3575 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3576 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3577 3578 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3579 ic->ic_flags, ic->ic_fragthreshold, rate, 3580 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3581 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3582 m_freem(m0); 3583 break; 3584 } 3585 3586 /* XXX Misleading if fragmentation is enabled. Better 3587 * to fragment in software? 3588 */ 3589 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3590 3591 #if NBPFILTER > 0 3592 /* 3593 * Pass the packet to any BPF listeners. 3594 */ 3595 if (ic->ic_rawbpf != NULL) 3596 bpf_mtap((void *)ic->ic_rawbpf, m0); 3597 3598 if (sc->sc_radiobpf != NULL) { 3599 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3600 3601 tap->at_rate = rate; 3602 3603 bpf_mtap2(sc->sc_radiobpf, tap, 3604 sizeof(sc->sc_txtapu), m0); 3605 } 3606 #endif /* NBPFILTER > 0 */ 3607 3608 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3609 3610 if (ni != NULL) 3611 ieee80211_free_node(ni); 3612 3613 if (m0 == NULL) { 3614 ifp->if_oerrors++; 3615 break; 3616 } 3617 3618 /* just to make sure. */ 3619 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3620 3621 if (m0 == NULL) { 3622 ifp->if_oerrors++; 3623 break; 3624 } 3625 3626 hh = mtod(m0, struct atw_frame *); 3627 wh = &hh->atw_ihdr; 3628 3629 /* Copy everything we need from the 802.11 header: 3630 * Frame Control; address 1, address 3, or addresses 3631 * 3 and 4. NIC fills in BSSID, SA. 3632 */ 3633 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3634 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3635 panic("%s: illegal WDS frame", 3636 device_xname(sc->sc_dev)); 3637 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3638 } else 3639 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3640 3641 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3642 3643 /* initialize remaining Tx parameters */ 3644 memset(&hh->u, 0, sizeof(hh->u)); 3645 3646 hh->atw_rate = rate * 5; 3647 /* XXX this could be incorrect if M_FCS. _encap should 3648 * probably strip FCS just in case it sticks around in 3649 * bridged packets. 3650 */ 3651 hh->atw_service = 0x00; /* XXX guess */ 3652 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3653 sizeof(struct atw_frame)); 3654 3655 /* never fragment multicast frames */ 3656 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3657 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3658 else { 3659 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3660 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3661 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3662 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3663 } 3664 3665 hh->atw_rtylmt = 3; 3666 #if 0 3667 if (do_encrypt) { 3668 hdrctl |= htole16(ATW_HDRCTL_WEP); 3669 hh->atw_keyid = ic->ic_def_txkey; 3670 } 3671 #endif 3672 3673 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3674 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3675 if (txs->txs_d0.d_residue) 3676 hh->atw_head_plcplen |= htole16(0x8000); 3677 if (txs->txs_dn.d_residue) 3678 hh->atw_tail_plcplen |= htole16(0x8000); 3679 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3680 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3681 3682 hh->atw_hdrctl = hdrctl; 3683 hh->atw_fragnum = npkt << 4; 3684 #ifdef ATW_DEBUG 3685 3686 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3687 printf("%s: dst = %s, rate = 0x%02x, " 3688 "service = 0x%02x, paylen = 0x%04x\n", 3689 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3690 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3691 3692 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3693 "dur1 = 0x%04x, dur2 = 0x%04x, " 3694 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3695 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3696 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3697 hh->atw_tail_dur, hh->atw_head_dur); 3698 3699 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3700 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3701 device_xname(sc->sc_dev), hh->atw_hdrctl, 3702 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3703 3704 printf("%s: keyid = %d\n", 3705 device_xname(sc->sc_dev), hh->atw_keyid); 3706 3707 atw_dump_pkt(ifp, m0); 3708 } 3709 #endif /* ATW_DEBUG */ 3710 3711 dmamap = txs->txs_dmamap; 3712 3713 /* 3714 * Load the DMA map. Copy and try (once) again if the packet 3715 * didn't fit in the alloted number of segments. 3716 */ 3717 for (first = 1; 3718 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3719 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3720 first = 0) { 3721 MGETHDR(m, M_DONTWAIT, MT_DATA); 3722 if (m == NULL) { 3723 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3724 break; 3725 } 3726 if (m0->m_pkthdr.len > MHLEN) { 3727 MCLGET(m, M_DONTWAIT); 3728 if ((m->m_flags & M_EXT) == 0) { 3729 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3730 "cluster\n"); 3731 m_freem(m); 3732 break; 3733 } 3734 } 3735 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3736 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3737 m_freem(m0); 3738 m0 = m; 3739 m = NULL; 3740 } 3741 if (error != 0) { 3742 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3743 "error = %d\n", error); 3744 m_freem(m0); 3745 break; 3746 } 3747 3748 /* 3749 * Ensure we have enough descriptors free to describe 3750 * the packet. 3751 */ 3752 if (dmamap->dm_nsegs > sc->sc_txfree) { 3753 /* 3754 * Not enough free descriptors to transmit 3755 * this packet. Unload the DMA map and 3756 * drop the packet. Notify the upper layer 3757 * that there are no more slots left. 3758 * 3759 * XXX We could allocate an mbuf and copy, but 3760 * XXX it is worth it? 3761 */ 3762 bus_dmamap_unload(sc->sc_dmat, dmamap); 3763 m_freem(m0); 3764 break; 3765 } 3766 3767 /* 3768 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3769 */ 3770 3771 /* Sync the DMA map. */ 3772 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3773 BUS_DMASYNC_PREWRITE); 3774 3775 /* XXX arbitrary retry limit; 8 because I have seen it in 3776 * use already and maybe 0 means "no tries" ! 3777 */ 3778 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3779 3780 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3781 device_xname(sc->sc_dev), rate * 5)); 3782 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3783 3784 /* 3785 * Initialize the transmit descriptors. 3786 */ 3787 for (nexttx = sc->sc_txnext, seg = 0; 3788 seg < dmamap->dm_nsegs; 3789 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3790 /* 3791 * If this is the first descriptor we're 3792 * enqueueing, don't set the OWN bit just 3793 * yet. That could cause a race condition. 3794 * We'll do it below. 3795 */ 3796 txd = &sc->sc_txdescs[nexttx]; 3797 txd->at_ctl = ctl | 3798 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3799 3800 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3801 txd->at_flags = 3802 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3803 ATW_TXFLAG_TBS1_MASK)) | 3804 ((nexttx == (ATW_NTXDESC - 1)) 3805 ? htole32(ATW_TXFLAG_TER) : 0); 3806 lasttx = nexttx; 3807 } 3808 3809 /* Set `first segment' and `last segment' appropriately. */ 3810 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3811 htole32(ATW_TXFLAG_FS); 3812 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3813 3814 #ifdef ATW_DEBUG 3815 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3816 printf(" txsoft %p transmit chain:\n", txs); 3817 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3818 printf(" descriptor %d:\n", seg); 3819 printf(" at_ctl: 0x%08x\n", 3820 le32toh(sc->sc_txdescs[seg].at_ctl)); 3821 printf(" at_flags: 0x%08x\n", 3822 le32toh(sc->sc_txdescs[seg].at_flags)); 3823 printf(" at_buf1: 0x%08x\n", 3824 le32toh(sc->sc_txdescs[seg].at_buf1)); 3825 printf(" at_buf2: 0x%08x\n", 3826 le32toh(sc->sc_txdescs[seg].at_buf2)); 3827 if (seg == lasttx) 3828 break; 3829 } 3830 } 3831 #endif 3832 3833 /* Sync the descriptors we're using. */ 3834 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3835 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3836 3837 /* 3838 * Store a pointer to the packet so we can free it later, 3839 * and remember what txdirty will be once the packet is 3840 * done. 3841 */ 3842 txs->txs_mbuf = m0; 3843 txs->txs_firstdesc = sc->sc_txnext; 3844 txs->txs_lastdesc = lasttx; 3845 txs->txs_ndescs = dmamap->dm_nsegs; 3846 3847 /* Advance the tx pointer. */ 3848 sc->sc_txfree -= dmamap->dm_nsegs; 3849 sc->sc_txnext = nexttx; 3850 3851 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3852 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3853 3854 last_txs = txs; 3855 } 3856 3857 if (sc->sc_txfree != ofree) { 3858 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3859 device_xname(sc->sc_dev), lasttx, firsttx)); 3860 /* 3861 * Cause a transmit interrupt to happen on the 3862 * last packet we enqueued. 3863 */ 3864 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3865 ATW_CDTXSYNC(sc, lasttx, 1, 3866 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3867 3868 /* 3869 * The entire packet chain is set up. Give the 3870 * first descriptor to the chip now. 3871 */ 3872 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3873 ATW_CDTXSYNC(sc, firsttx, 1, 3874 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3875 3876 /* Wake up the transmitter. */ 3877 ATW_WRITE(sc, ATW_TDR, 0x1); 3878 3879 if (txs == NULL || sc->sc_txfree == 0) 3880 ifp->if_flags |= IFF_OACTIVE; 3881 3882 /* Set a watchdog timer in case the chip flakes out. */ 3883 sc->sc_tx_timer = 5; 3884 ifp->if_timer = 1; 3885 } 3886 } 3887 3888 /* 3889 * atw_ioctl: [ifnet interface function] 3890 * 3891 * Handle control requests from the operator. 3892 */ 3893 int 3894 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3895 { 3896 struct atw_softc *sc = ifp->if_softc; 3897 struct ieee80211req *ireq; 3898 int s, error = 0; 3899 3900 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3901 if (!device_is_active(sc->sc_dev)) 3902 return ENXIO; 3903 3904 s = splnet(); 3905 3906 switch (cmd) { 3907 case SIOCSIFFLAGS: 3908 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3909 break; 3910 if (ifp->if_flags & IFF_UP) { 3911 if (ATW_IS_ENABLED(sc)) { 3912 /* 3913 * To avoid rescanning another access point, 3914 * do not call atw_init() here. Instead, 3915 * only reflect media settings. 3916 */ 3917 atw_filter_setup(sc); 3918 } else 3919 error = atw_init(ifp); 3920 } else if (ATW_IS_ENABLED(sc)) 3921 atw_stop(ifp, 1); 3922 break; 3923 case SIOCADDMULTI: 3924 case SIOCDELMULTI: 3925 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3926 if (ifp->if_flags & IFF_RUNNING) 3927 atw_filter_setup(sc); /* do not rescan */ 3928 error = 0; 3929 } 3930 break; 3931 case SIOCS80211: 3932 ireq = data; 3933 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3934 if ((error = kauth_authorize_network(curlwp->l_cred, 3935 KAUTH_NETWORK_INTERFACE, 3936 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3937 (void *)cmd, NULL) != 0)) 3938 break; 3939 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3940 ireq->i_val <= IEEE80211_FRAG_MAX)) 3941 error = EINVAL; 3942 else 3943 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3944 break; 3945 } 3946 /*FALLTHROUGH*/ 3947 default: 3948 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3949 if (error == ENETRESET || error == ERESTART) { 3950 if (is_running(ifp)) 3951 error = atw_init(ifp); 3952 else 3953 error = 0; 3954 } 3955 break; 3956 } 3957 3958 /* Try to get more packets going. */ 3959 if (ATW_IS_ENABLED(sc)) 3960 atw_start(ifp); 3961 3962 splx(s); 3963 return (error); 3964 } 3965 3966 static int 3967 atw_media_change(struct ifnet *ifp) 3968 { 3969 int error; 3970 3971 error = ieee80211_media_change(ifp); 3972 if (error == ENETRESET) { 3973 if (is_running(ifp)) 3974 error = atw_init(ifp); 3975 else 3976 error = 0; 3977 } 3978 return error; 3979 } 3980
Indexes created Tue Sep 23 07:09:52 GMT 2025