atw.c revision 1.15
1 /* $NetBSD: atw.c,v 1.15 2004/01/10 07:41:18 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.15 2004/01/10 07:41:18 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/atwvar.h> 82 #include <dev/ic/smc93cx6var.h> 83 84 /* XXX TBD open questions 85 * 86 * 87 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 88 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 89 * handle this for me? 90 * 91 */ 92 /* device attachment 93 * 94 * print TOFS[012] 95 * 96 * device initialization 97 * 98 * clear ATW_FRCTL_MAXPSP to disable max power saving 99 * set ATW_TXBR_ALCUPDATE to enable ALC 100 * set TOFS[012]? (hope not) 101 * disable rx/tx 102 * set ATW_PAR_SWR (software reset) 103 * wait for ATW_PAR_SWR clear 104 * disable interrupts 105 * ack status register 106 * enable interrupts 107 * 108 * rx/tx initialization 109 * 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * allocate and init descriptor rings 112 * write ATW_PAR_DSL (descriptor skip length) 113 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * write ATW_NAR_SQ for one/both transmit descriptor rings 116 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * 118 * rx/tx end 119 * 120 * stop DMA 121 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 122 * flush tx w/ ATW_NAR_HF 123 * 124 * scan 125 * 126 * initialize rx/tx 127 * 128 * IBSS join/create 129 * 130 * set ATW_NAR_EA (is set by ASIC?) 131 * 132 * BSS join: (re)association response 133 * 134 * set ATW_FRCTL_AID 135 * 136 * optimizations ??? 137 * 138 */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_rfio_enable_delay = 20 * 1000; 145 int atw_rfio_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 5; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 150 #ifdef ATW_DEBUG 151 int atw_xhdrctl = 0; 152 int atw_xrtylmt = ~0; 153 int atw_xservice = IEEE80211_PLCP_SERVICE; 154 int atw_xpaylen = 0; 155 156 int atw_debug = 0; 157 158 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 159 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 160 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 161 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 162 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 163 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 164 static void atw_print_regs(struct atw_softc *, const char *); 165 static void atw_rf3000_print(struct atw_softc *); 166 static void atw_si4126_print(struct atw_softc *); 167 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 168 #else 169 #define ATW_DPRINTF(x) 170 #define ATW_DPRINTF2(x) 171 #define ATW_DPRINTF3(x) 172 #define DPRINTF(sc, x) /* nothing */ 173 #define DPRINTF2(sc, x) /* nothing */ 174 #define DPRINTF3(sc, x) /* nothing */ 175 #endif 176 177 #ifdef ATW_STATS 178 void atw_print_stats __P((struct atw_softc *)); 179 #endif 180 181 void atw_start __P((struct ifnet *)); 182 void atw_watchdog __P((struct ifnet *)); 183 int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 184 int atw_init __P((struct ifnet *)); 185 void atw_stop __P((struct ifnet *, int)); 186 187 void atw_reset __P((struct atw_softc *)); 188 int atw_read_srom __P((struct atw_softc *)); 189 190 void atw_shutdown __P((void *)); 191 192 void atw_rxdrain __P((struct atw_softc *)); 193 int atw_add_rxbuf __P((struct atw_softc *, int)); 194 void atw_idle __P((struct atw_softc *, u_int32_t)); 195 196 int atw_enable __P((struct atw_softc *)); 197 void atw_disable __P((struct atw_softc *)); 198 void atw_power __P((int, void *)); 199 200 void atw_rxintr __P((struct atw_softc *)); 201 void atw_txintr __P((struct atw_softc *)); 202 void atw_linkintr __P((struct atw_softc *, u_int32_t)); 203 204 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 205 static void atw_tsf(struct atw_softc *); 206 static void atw_start_beacon(struct atw_softc *, int); 207 static void atw_write_wep(struct atw_softc *); 208 static void atw_write_bssid(struct atw_softc *); 209 static void atw_write_bcn_thresh(struct atw_softc *); 210 static void atw_write_ssid(struct atw_softc *); 211 static void atw_write_sup_rates(struct atw_softc *); 212 static void atw_clear_sram(struct atw_softc *); 213 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 214 static int atw_media_change(struct ifnet *); 215 static void atw_media_status(struct ifnet *, struct ifmediareq *); 216 static void atw_filter_setup(struct atw_softc *); 217 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 218 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 219 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 224 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 225 226 static int atw_tune(struct atw_softc *); 227 228 static void atw_rfio_enable(struct atw_softc *, int); 229 230 /* RFMD RF3000 Baseband Processor */ 231 static int atw_rf3000_init(struct atw_softc *); 232 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 233 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 234 #ifdef ATW_DEBUG 235 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 236 #endif /* ATW_DEBUG */ 237 238 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 239 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 240 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 241 #ifdef ATW_DEBUG 242 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 243 #endif /* ATW_DEBUG */ 244 245 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 246 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 247 248 const char *atw_tx_state[] = { 249 "STOPPED", 250 "RUNNING - FETCH", 251 "RUNNING - WAIT", 252 "RUNNING - READING", 253 "-- RESERVED1 --", 254 "-- RESERVED2 --", 255 "SUSPENDED", 256 "RUNNING - CLOSE" 257 }; 258 259 const char *atw_rx_state[] = { 260 "STOPPED", 261 "RUNNING - FETCH", 262 "RUNNING - CHECK", 263 "RUNNING - WAIT", 264 "SUSPENDED", 265 "RUNNING - CLOSE", 266 "RUNNING - FLUSH", 267 "RUNNING - QUEUE" 268 }; 269 270 int 271 atw_activate(struct device *self, enum devact act) 272 { 273 struct atw_softc *sc = (struct atw_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 282 case DVACT_DEACTIVATE: 283 if_deactivate(&sc->sc_ic.ic_if); 284 break; 285 } 286 splx(s); 287 return rv; 288 } 289 290 /* 291 * atw_enable: 292 * 293 * Enable the ADM8211 chip. 294 */ 295 int 296 atw_enable(sc) 297 struct atw_softc *sc; 298 { 299 300 if (ATW_IS_ENABLED(sc) == 0) { 301 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 302 printf("%s: device enable failed\n", 303 sc->sc_dev.dv_xname); 304 return (EIO); 305 } 306 sc->sc_flags |= ATWF_ENABLED; 307 } 308 return (0); 309 } 310 311 /* 312 * atw_disable: 313 * 314 * Disable the ADM8211 chip. 315 */ 316 void 317 atw_disable(sc) 318 struct atw_softc *sc; 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF(("\n\t")); 400 } 401 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 499 }; 500 struct ieee80211com *ic = &sc->sc_ic; 501 struct ifnet *ifp = &ic->ic_if; 502 int country_code, error, i, nrate; 503 u_int32_t reg; 504 static const char *type_strings[] = {"Intersil (not supported)", 505 "RFMD", "Marvel (not supported)"}; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 } 577 for (i = 0; i < ATW_NRXDESC; i++) { 578 sc->sc_rxsoft[i].rxs_mbuf = NULL; 579 } 580 581 /* Reset the chip to a known state. */ 582 atw_reset(sc); 583 584 if (atw_read_srom(sc) == -1) 585 return; 586 587 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_RFTYPE_MASK); 589 590 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 591 ATW_SR_BBPTYPE_MASK); 592 593 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 594 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 598 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 599 return; 600 } 601 602 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 603 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 604 605 /* XXX There exists a Linux driver which seems to use RFType = 0 for 606 * MARVEL. My bug, or theirs? 607 */ 608 609 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 610 611 switch (sc->sc_rftype) { 612 case ATW_RFTYPE_INTERSIL: 613 reg |= ATW_SYNCTL_CS1; 614 break; 615 case ATW_RFTYPE_RFMD: 616 reg |= ATW_SYNCTL_CS0; 617 break; 618 case ATW_RFTYPE_MARVEL: 619 break; 620 } 621 622 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 623 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 624 625 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 626 627 switch (sc->sc_bbptype) { 628 case ATW_RFTYPE_INTERSIL: 629 reg |= ATW_BBPCTL_TWI; 630 break; 631 case ATW_RFTYPE_RFMD: 632 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 633 ATW_BBPCTL_CCA_ACTLO; 634 break; 635 case ATW_RFTYPE_MARVEL: 636 break; 637 } 638 639 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 640 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 641 642 /* 643 * From this point forward, the attachment cannot fail. A failure 644 * before this point releases all resources that may have been 645 * allocated. 646 */ 647 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 648 649 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 650 htole16(sc->sc_srom[ATW_SR_MAC00]), 651 htole16(sc->sc_srom[ATW_SR_MAC01]), 652 htole16(sc->sc_srom[ATW_SR_MAC10]))); 653 654 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 655 ATW_SR_CTRY_MASK); 656 657 #define ADD_CHANNEL(_ic, _chan) do { \ 658 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 659 _ic->ic_channels[_chan].ic_freq = \ 660 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 661 } while (0) 662 663 /* Find available channels */ 664 switch (country_code) { 665 case COUNTRY_MMK2: /* 1-14 */ 666 ADD_CHANNEL(ic, 14); 667 /*FALLTHROUGH*/ 668 case COUNTRY_ETSI: /* 1-13 */ 669 for (i = 1; i <= 13; i++) 670 ADD_CHANNEL(ic, i); 671 break; 672 case COUNTRY_FCC: /* 1-11 */ 673 case COUNTRY_IC: /* 1-11 */ 674 for (i = 1; i <= 11; i++) 675 ADD_CHANNEL(ic, i); 676 break; 677 case COUNTRY_MMK: /* 14 */ 678 ADD_CHANNEL(ic, 14); 679 break; 680 case COUNTRY_FRANCE: /* 10-13 */ 681 for (i = 10; i <= 13; i++) 682 ADD_CHANNEL(ic, i); 683 break; 684 default: /* assume channels 10-11 */ 685 case COUNTRY_SPAIN: /* 10-11 */ 686 for (i = 10; i <= 11; i++) 687 ADD_CHANNEL(ic, i); 688 break; 689 } 690 691 /* Read the MAC address. */ 692 reg = ATW_READ(sc, ATW_PAR0); 693 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 694 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 695 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 696 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 697 reg = ATW_READ(sc, ATW_PAR1); 698 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 699 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 700 701 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 702 printf(" could not get mac address, attach failed\n"); 703 return; 704 } 705 706 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 707 708 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 709 ifp->if_softc = sc; 710 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 711 IFF_NOTRAILERS; 712 ifp->if_ioctl = atw_ioctl; 713 ifp->if_start = atw_start; 714 ifp->if_watchdog = atw_watchdog; 715 ifp->if_init = atw_init; 716 ifp->if_stop = atw_stop; 717 IFQ_SET_READY(&ifp->if_snd); 718 719 ic->ic_phytype = IEEE80211_T_DS; 720 ic->ic_opmode = IEEE80211_M_STA; 721 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 722 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 723 724 nrate = 0; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 730 731 /* 732 * Call MI attach routines. 733 */ 734 735 if_attach(ifp); 736 ieee80211_ifattach(ifp); 737 738 sc->sc_newstate = ic->ic_newstate; 739 ic->ic_newstate = atw_newstate; 740 741 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 742 ic->ic_recv_mgmt = atw_recv_mgmt; 743 744 sc->sc_node_free = ic->ic_node_free; 745 ic->ic_node_free = atw_node_free; 746 747 sc->sc_node_alloc = ic->ic_node_alloc; 748 ic->ic_node_alloc = atw_node_alloc; 749 750 /* possibly we should fill in our own sc_send_prresp, since 751 * the ADM8211 is probably sending probe responses in ad hoc 752 * mode. 753 */ 754 755 /* complete initialization */ 756 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 757 callout_init(&sc->sc_scan_ch); 758 759 #if NBPFILTER > 0 760 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 761 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 762 #endif 763 764 /* 765 * Make sure the interface is shutdown during reboot. 766 */ 767 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 768 if (sc->sc_sdhook == NULL) 769 printf("%s: WARNING: unable to establish shutdown hook\n", 770 sc->sc_dev.dv_xname); 771 772 /* 773 * Add a suspend hook to make sure we come back up after a 774 * resume. 775 */ 776 sc->sc_powerhook = powerhook_establish(atw_power, sc); 777 if (sc->sc_powerhook == NULL) 778 printf("%s: WARNING: unable to establish power hook\n", 779 sc->sc_dev.dv_xname); 780 781 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 782 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 783 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 784 785 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 786 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 787 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 788 789 return; 790 791 /* 792 * Free any resources we've allocated during the failed attach 793 * attempt. Do this in reverse order and fall through. 794 */ 795 fail_5: 796 for (i = 0; i < ATW_NRXDESC; i++) { 797 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 798 continue; 799 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 800 } 801 fail_4: 802 for (i = 0; i < ATW_TXQUEUELEN; i++) { 803 if (sc->sc_txsoft[i].txs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 806 } 807 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 808 fail_3: 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 810 fail_2: 811 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 812 sizeof(struct atw_control_data)); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 815 fail_0: 816 return; 817 } 818 819 static struct ieee80211_node * 820 atw_node_alloc(struct ieee80211com *ic) 821 { 822 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 823 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 824 825 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 826 return ni; 827 } 828 829 static void 830 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 831 { 832 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 833 834 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 835 ether_sprintf(ni->ni_bssid))); 836 (*sc->sc_node_free)(ic, ni); 837 } 838 839 /* 840 * atw_reset: 841 * 842 * Perform a soft reset on the ADM8211. 843 */ 844 void 845 atw_reset(sc) 846 struct atw_softc *sc; 847 { 848 int i; 849 850 if (ATW_IS_ENABLED(sc) == 0) 851 return; 852 853 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 854 855 for (i = 0; i < 10000; i++) { 856 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 857 break; 858 DELAY(1); 859 } 860 861 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 862 863 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 864 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 865 866 /* Turn off maximum power saving. */ 867 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 868 869 /* Recall EEPROM. */ 870 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 871 872 DELAY(10 * 1000); 873 874 /* A reset seems to affect the SRAM contents, so put them into 875 * a known state. 876 */ 877 atw_clear_sram(sc); 878 879 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 880 881 sc->sc_lost_bcn_thresh = 0; 882 } 883 884 static void 885 atw_clear_sram(sc) 886 struct atw_softc *sc; 887 { 888 #if 0 889 for (addr = 0; addr < 448; addr++) { 890 ATW_WRITE(sc, ATW_WEPCTL, 891 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 892 DELAY(1000); 893 ATW_WRITE(sc, ATW_WESK, 0); 894 DELAY(1000); /* paranoia */ 895 } 896 return; 897 #endif 898 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 899 /* XXX not for revision 0x20. */ 900 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 901 } 902 903 /* TBD atw_init 904 * 905 * set MAC based on ic->ic_bss->myaddr 906 * write WEP keys 907 * set TX rate 908 */ 909 910 /* 911 * atw_init: [ ifnet interface function ] 912 * 913 * Initialize the interface. Must be called at splnet(). 914 */ 915 int 916 atw_init(ifp) 917 struct ifnet *ifp; 918 { 919 struct atw_softc *sc = ifp->if_softc; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct atw_txsoft *txs; 922 struct atw_rxsoft *rxs; 923 u_int32_t reg; 924 int i, error = 0; 925 926 if ((error = atw_enable(sc)) != 0) 927 goto out; 928 929 /* 930 * Cancel any pending I/O. This also resets. 931 */ 932 atw_stop(ifp, 0); 933 934 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 935 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 936 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 937 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 938 939 /* Turn off APM??? (A binary-only driver does this.) 940 * 941 * Set Rx store-and-forward mode. 942 */ 943 reg = ATW_READ(sc, ATW_CMDR); 944 reg &= ~ATW_CMDR_APM; 945 reg &= ~ATW_CMDR_DRT_MASK; 946 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 947 948 ATW_WRITE(sc, ATW_CMDR, reg); 949 950 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 951 * 952 * XXX a binary-only driver sets a different service field than 953 * 0. why? 954 */ 955 reg = ATW_READ(sc, ATW_PLCPHD); 956 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 957 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 958 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 959 ATW_WRITE(sc, ATW_PLCPHD, reg); 960 961 /* XXX this magic can probably be figured out from the RFMD docs */ 962 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 963 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 964 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 965 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 966 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 967 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 968 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 969 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 970 ATW_WRITE(sc, ATW_TOFS2, reg); 971 972 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 973 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 974 975 /* XXX this resets an Intersil RF front-end? */ 976 /* TBD condition on Intersil RFType? */ 977 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 978 DELAY(10 * 1000); 979 ATW_WRITE(sc, ATW_SYNRF, 0); 980 DELAY(5 * 1000); 981 982 /* 16 TU max duration for contention-free period */ 983 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 984 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 985 986 /* XXX I guess that the Cardbus clock is 22MHz? 987 * I am assuming that the role of ATW_TOFS0_USCNT is 988 * to divide the bus clock to get a 1MHz clock---the datasheet is not 989 * very clear on this point. It says in the datasheet that it is 990 * possible for the ADM8211 to accomodate bus speeds between 22MHz 991 * and 33MHz; maybe this is the way? I see a binary-only driver write 992 * these values. These values are also the power-on default. 993 */ 994 ATW_WRITE(sc, ATW_TOFS0, 995 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 996 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 997 998 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 999 * driver. Go figure. 1000 */ 1001 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1002 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1003 ATW_IFST_SIFS_MASK) | 1004 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1005 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1006 1007 ATW_WRITE(sc, ATW_IFST, reg); 1008 1009 /* XXX More magic. Might relate to ACK timing. */ 1010 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1011 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1012 1013 /* Set up the MMI read/write addresses for the BBP. 1014 * 1015 * TBD find out the Marvel settings. 1016 */ 1017 switch (sc->sc_bbptype) { 1018 case ATW_BBPTYPE_INTERSIL: 1019 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1020 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1021 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1022 break; 1023 case ATW_BBPTYPE_MARVEL: 1024 break; 1025 case ATW_BBPTYPE_RFMD: 1026 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1027 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1028 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1029 default: 1030 break; 1031 } 1032 1033 sc->sc_wepctl = 0; 1034 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1035 1036 if ((error = atw_rf3000_init(sc)) != 0) 1037 goto out; 1038 1039 /* 1040 * Initialize the PCI Access Register. 1041 */ 1042 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1043 1044 /* 1045 * If we're allowed to do so, use Memory Read Line 1046 * and Memory Read Multiple. 1047 * 1048 * XXX Should we use Memory Write and Invalidate? 1049 */ 1050 if (sc->sc_flags & ATWF_MRL) 1051 sc->sc_busmode |= ATW_PAR_MRLE; 1052 if (sc->sc_flags & ATWF_MRM) 1053 sc->sc_busmode |= ATW_PAR_MRME; 1054 if (sc->sc_flags & ATWF_MWI) 1055 sc->sc_busmode |= ATW_PAR_MWIE; 1056 if (sc->sc_maxburst == 0) 1057 sc->sc_maxburst = 8; /* ADM8211 default */ 1058 1059 switch (sc->sc_cacheline) { 1060 default: 1061 /* Use burst length. */ 1062 break; 1063 case 8: 1064 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1065 break; 1066 case 16: 1067 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1068 break; 1069 case 32: 1070 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1071 break; 1072 } 1073 switch (sc->sc_maxburst) { 1074 case 1: 1075 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1076 break; 1077 case 2: 1078 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1079 break; 1080 case 4: 1081 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1082 break; 1083 case 8: 1084 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1085 break; 1086 case 16: 1087 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1088 break; 1089 case 32: 1090 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1091 break; 1092 default: 1093 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1094 break; 1095 } 1096 1097 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1098 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1099 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1100 1101 /* 1102 * Initialize the OPMODE register. We don't write it until 1103 * we're ready to begin the transmit and receive processes. 1104 */ 1105 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1106 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1107 1108 /* 1109 * Initialize the transmit descriptor ring. 1110 */ 1111 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1112 for (i = 0; i < ATW_NTXDESC; i++) { 1113 /* no transmit chaining */ 1114 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1115 sc->sc_txdescs[i].at_buf2 = 1116 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1117 } 1118 /* use ring mode */ 1119 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1120 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 sc->sc_txfree = ATW_NTXDESC; 1123 sc->sc_txnext = 0; 1124 1125 /* 1126 * Initialize the transmit job descriptors. 1127 */ 1128 SIMPLEQ_INIT(&sc->sc_txfreeq); 1129 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1130 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1131 txs = &sc->sc_txsoft[i]; 1132 txs->txs_mbuf = NULL; 1133 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1134 } 1135 1136 /* 1137 * Initialize the receive descriptor and receive job 1138 * descriptor rings. 1139 */ 1140 for (i = 0; i < ATW_NRXDESC; i++) { 1141 rxs = &sc->sc_rxsoft[i]; 1142 if (rxs->rxs_mbuf == NULL) { 1143 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1144 printf("%s: unable to allocate or map rx " 1145 "buffer %d, error = %d\n", 1146 sc->sc_dev.dv_xname, i, error); 1147 /* 1148 * XXX Should attempt to run with fewer receive 1149 * XXX buffers instead of just failing. 1150 */ 1151 atw_rxdrain(sc); 1152 goto out; 1153 } 1154 } else 1155 ATW_INIT_RXDESC(sc, i); 1156 } 1157 sc->sc_rxptr = 0; 1158 1159 /* disable all wake-up events */ 1160 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1161 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1162 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1163 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1164 1165 /* ack all wake-up events */ 1166 ATW_SET(sc, ATW_WCSR, 0); 1167 1168 /* 1169 * Initialize the interrupt mask and enable interrupts. 1170 */ 1171 /* normal interrupts */ 1172 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1173 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1174 1175 /* abnormal interrupts */ 1176 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1177 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1178 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1179 1180 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1181 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1182 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1183 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1184 ATW_INTR_TRT; 1185 1186 sc->sc_linkint_mask &= sc->sc_inten; 1187 sc->sc_rxint_mask &= sc->sc_inten; 1188 sc->sc_txint_mask &= sc->sc_inten; 1189 1190 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1191 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1192 if (sc->sc_intr_ack != NULL) 1193 (*sc->sc_intr_ack)(sc); 1194 1195 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1196 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1197 1198 /* 1199 * Give the transmit and receive rings to the ADM8211. 1200 */ 1201 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1202 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1203 1204 /* common 802.11 configuration */ 1205 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1206 switch (ic->ic_opmode) { 1207 case IEEE80211_M_HOSTAP: /* XXX */ 1208 case IEEE80211_M_STA: 1209 sc->sc_opmode &= ~ATW_NAR_EA; 1210 break; 1211 case IEEE80211_M_AHDEMO: /* XXX */ 1212 case IEEE80211_M_IBSS: 1213 /* EA bit seems important for ad hoc reception. */ 1214 sc->sc_opmode |= ATW_NAR_EA; 1215 ic->ic_flags |= IEEE80211_F_IBSSON; 1216 break; 1217 case IEEE80211_M_MONITOR: /* XXX */ 1218 break; 1219 } 1220 1221 atw_start_beacon(sc, 0); 1222 1223 switch (ic->ic_opmode) { 1224 case IEEE80211_M_AHDEMO: 1225 case IEEE80211_M_HOSTAP: 1226 ic->ic_bss->ni_intval = ic->ic_lintval; 1227 ic->ic_bss->ni_rssi = 0; 1228 ic->ic_bss->ni_rstamp = 0; 1229 break; 1230 default: /* XXX */ 1231 break; 1232 } 1233 1234 atw_write_ssid(sc); 1235 atw_write_sup_rates(sc); 1236 if (ic->ic_caps & IEEE80211_C_WEP) 1237 atw_write_wep(sc); 1238 1239 /* 1240 * Set the receive filter. This will start the transmit and 1241 * receive processes. 1242 */ 1243 atw_filter_setup(sc); 1244 1245 /* 1246 * Start the receive process. 1247 */ 1248 ATW_WRITE(sc, ATW_RDR, 0x1); 1249 1250 /* 1251 * Note that the interface is now running. 1252 */ 1253 ifp->if_flags |= IFF_RUNNING; 1254 ifp->if_flags &= ~IFF_OACTIVE; 1255 ic->ic_state = IEEE80211_S_INIT; 1256 1257 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1258 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1259 else 1260 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1261 out: 1262 if (error) { 1263 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1264 ifp->if_timer = 0; 1265 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1266 } 1267 #ifdef ATW_DEBUG 1268 atw_print_regs(sc, "end of init"); 1269 #endif /* ATW_DEBUG */ 1270 1271 return (error); 1272 } 1273 1274 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1275 * 0: MAC control of RF3000/Si4126. 1276 * 1277 * Applies power, or selects RF front-end? Sets reset condition. 1278 * 1279 * TBD support non-RFMD BBP, non-SiLabs synth. 1280 */ 1281 static void 1282 atw_rfio_enable(struct atw_softc *sc, int enable) 1283 { 1284 if (enable) { 1285 ATW_WRITE(sc, ATW_SYNRF, 1286 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1287 DELAY(atw_rfio_enable_delay); 1288 } else { 1289 ATW_WRITE(sc, ATW_SYNRF, 0); 1290 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1291 } 1292 } 1293 1294 static int 1295 atw_tune(sc) 1296 struct atw_softc *sc; 1297 { 1298 int rc; 1299 u_int32_t reg; 1300 int chan; 1301 struct ieee80211com *ic = &sc->sc_ic; 1302 1303 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1304 if (chan == IEEE80211_CHAN_ANY) 1305 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1306 1307 if (chan == sc->sc_cur_chan) 1308 return 0; 1309 1310 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1311 sc->sc_cur_chan, chan)); 1312 1313 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1314 1315 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1316 (rc = atw_rf3000_tune(sc, chan)) != 0) 1317 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1318 chan); 1319 1320 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1321 ATW_WRITE(sc, ATW_CAP0, 1322 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1323 1324 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1325 1326 if (rc == 0) 1327 sc->sc_cur_chan = chan; 1328 1329 return rc; 1330 } 1331 1332 #ifdef ATW_DEBUG 1333 static void 1334 atw_si4126_print(sc) 1335 struct atw_softc *sc; 1336 { 1337 struct ifnet *ifp = &sc->sc_ic.ic_if; 1338 u_int addr, val; 1339 1340 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1341 return; 1342 1343 for (addr = 0; addr <= 8; addr++) { 1344 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1345 if (atw_si4126_read(sc, addr, &val) == 0) { 1346 printf("<unknown> (quitting print-out)\n"); 1347 break; 1348 } 1349 printf("%05x\n", val); 1350 } 1351 } 1352 #endif /* ATW_DEBUG */ 1353 1354 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1355 * 1356 * The RF/IF synthesizer produces two reference frequencies for 1357 * the RF2948B transceiver. The first frequency the RF2948B requires 1358 * is two times the so-called "intermediate frequency" (IF). Since 1359 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1360 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1361 * frequency required by the transceiver is the radio frequency 1362 * (RF). This is a superheterodyne transceiver; for f(chan) the 1363 * center frequency of the channel we are tuning, RF = f(chan) - 1364 * IF. 1365 * 1366 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1367 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1368 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1369 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1370 */ 1371 static int 1372 atw_si4126_tune(sc, chan) 1373 struct atw_softc *sc; 1374 u_int8_t chan; 1375 { 1376 int rc = 0; 1377 u_int mhz; 1378 u_int R; 1379 u_int32_t reg; 1380 u_int16_t gain; 1381 1382 #ifdef ATW_DEBUG 1383 atw_si4126_print(sc); 1384 #endif /* ATW_DEBUG */ 1385 1386 if (chan == 14) 1387 mhz = 2484; 1388 else 1389 mhz = 2412 + 5 * (chan - 1); 1390 1391 /* Tune IF to 748MHz to suit the IF LO input of the 1392 * RF2494B, which is 2 x IF. No need to set an IF divider 1393 * because an IF in 526MHz - 952MHz is allowed. 1394 * 1395 * XIN is 44.000MHz, so divide it by two to get allowable 1396 * range of 2-25MHz. SiLabs tells me that this is not 1397 * strictly necessary. 1398 */ 1399 1400 R = 44; 1401 1402 atw_rfio_enable(sc, 1); 1403 1404 /* Power-up RF, IF synthesizers. */ 1405 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1406 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1407 goto out; 1408 1409 /* If RF2 N > 2047, then set KP2 to 1. */ 1410 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1411 1412 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1413 goto out; 1414 1415 /* set LPWR, too? */ 1416 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1417 SI4126_MAIN_XINDIV2)) != 0) 1418 goto out; 1419 1420 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1421 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1422 */ 1423 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1424 goto out; 1425 1426 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1427 goto out; 1428 1429 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1430 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1431 * which has no RF1! 1432 */ 1433 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1434 goto out; 1435 1436 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1437 goto out; 1438 1439 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1440 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1441 * Now let's multiply it to mhz. So mhz - IF = N. 1442 */ 1443 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1444 goto out; 1445 1446 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1447 goto out; 1448 1449 /* wait 100us from power-up for RF, IF to settle */ 1450 DELAY(100); 1451 1452 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1453 /* XXX there is a binary driver which sends 1454 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1455 * that this enables the Si4126 by raising its PWDN#, but I 1456 * think that it actually sets the Prism RF front-end 1457 * to a special mode for channel 14. 1458 */ 1459 reg = ATW_READ(sc, ATW_GPIO); 1460 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1461 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1462 ATW_WRITE(sc, ATW_GPIO, reg); 1463 } 1464 1465 #ifdef ATW_DEBUG 1466 atw_si4126_print(sc); 1467 #endif /* ATW_DEBUG */ 1468 1469 out: 1470 atw_rfio_enable(sc, 0); 1471 1472 return rc; 1473 } 1474 1475 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1476 * diversity. 1477 * 1478 * Call this w/ Tx/Rx suspended. 1479 */ 1480 static int 1481 atw_rf3000_init(sc) 1482 struct atw_softc *sc; 1483 { 1484 int rc = 0; 1485 1486 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1487 1488 atw_rfio_enable(sc, 1); 1489 1490 /* enable diversity */ 1491 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1492 1493 if (rc != 0) 1494 goto out; 1495 1496 /* sensible setting from a binary-only driver */ 1497 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1498 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1499 1500 if (rc != 0) 1501 goto out; 1502 1503 /* magic from a binary-only driver */ 1504 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1505 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1506 1507 if (rc != 0) 1508 goto out; 1509 1510 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1511 1512 if (rc != 0) 1513 goto out; 1514 1515 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1516 1517 if (rc != 0) 1518 goto out; 1519 1520 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1521 1522 if (rc != 0) 1523 goto out; 1524 1525 /* CCA is acquisition sensitive */ 1526 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1527 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1528 1529 if (rc != 0) 1530 goto out; 1531 1532 out: 1533 atw_rfio_enable(sc, 0); 1534 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1535 return rc; 1536 } 1537 1538 #ifdef ATW_DEBUG 1539 static void 1540 atw_rf3000_print(sc) 1541 struct atw_softc *sc; 1542 { 1543 struct ifnet *ifp = &sc->sc_ic.ic_if; 1544 u_int addr, val; 1545 1546 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1547 return; 1548 1549 for (addr = 0x01; addr <= 0x15; addr++) { 1550 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1551 if (atw_rf3000_read(sc, addr, &val) != 0) { 1552 printf("<unknown> (quitting print-out)\n"); 1553 break; 1554 } 1555 printf("%08x\n", val); 1556 } 1557 } 1558 #endif /* ATW_DEBUG */ 1559 1560 /* Set the power settings on the BBP for channel `chan'. */ 1561 static int 1562 atw_rf3000_tune(sc, chan) 1563 struct atw_softc *sc; 1564 u_int8_t chan; 1565 { 1566 int rc = 0; 1567 u_int32_t reg; 1568 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1569 1570 atw_rfio_enable(sc, 1); 1571 1572 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1573 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1574 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1575 1576 /* odd channels: LSB, even channels: MSB */ 1577 if (chan % 2 == 1) { 1578 txpower &= 0xFF; 1579 lpf_cutoff &= 0xFF; 1580 lna_gs_thresh &= 0xFF; 1581 } else { 1582 txpower >>= 8; 1583 lpf_cutoff >>= 8; 1584 lna_gs_thresh >>= 8; 1585 } 1586 1587 #ifdef ATW_DEBUG 1588 atw_rf3000_print(sc); 1589 #endif /* ATW_DEBUG */ 1590 1591 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1592 "lna_gs_thresh %02x\n", 1593 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1594 1595 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1596 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1597 goto out; 1598 1599 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1600 goto out; 1601 1602 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1603 goto out; 1604 1605 /* from a binary-only driver. */ 1606 reg = ATW_READ(sc, ATW_PLCPHD); 1607 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1608 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1609 ATW_WRITE(sc, ATW_PLCPHD, reg); 1610 1611 #ifdef ATW_DEBUG 1612 atw_rf3000_print(sc); 1613 #endif /* ATW_DEBUG */ 1614 1615 out: 1616 atw_rfio_enable(sc, 0); 1617 1618 return rc; 1619 } 1620 1621 /* Write a register on the RF3000 baseband processor using the 1622 * registers provided by the ADM8211 for this purpose. 1623 * 1624 * Return 0 on success. 1625 */ 1626 static int 1627 atw_rf3000_write(sc, addr, val) 1628 struct atw_softc *sc; 1629 u_int addr, val; 1630 { 1631 u_int32_t reg; 1632 int i; 1633 1634 for (i = 1000; --i >= 0; ) { 1635 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1636 break; 1637 DELAY(100); 1638 } 1639 1640 if (i < 0) { 1641 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1642 return ETIMEDOUT; 1643 } 1644 1645 reg = sc->sc_bbpctl_wr | 1646 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1647 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1648 1649 ATW_WRITE(sc, ATW_BBPCTL, reg); 1650 1651 for (i = 1000; --i >= 0; ) { 1652 DELAY(100); 1653 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1654 break; 1655 } 1656 1657 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1658 1659 if (i < 0) { 1660 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1661 return ETIMEDOUT; 1662 } 1663 return 0; 1664 } 1665 1666 /* Read a register on the RF3000 baseband processor using the registers 1667 * the ADM8211 provides for this purpose. 1668 * 1669 * The 7-bit register address is addr. Record the 8-bit data in the register 1670 * in *val. 1671 * 1672 * Return 0 on success. 1673 * 1674 * XXX This does not seem to work. The ADM8211 must require more or 1675 * different magic to read the chip than to write it. Possibly some 1676 * of the magic I have derived from a binary-only driver concerns 1677 * the "chip address" (see the RF3000 manual). 1678 */ 1679 #ifdef ATW_DEBUG 1680 static int 1681 atw_rf3000_read(sc, addr, val) 1682 struct atw_softc *sc; 1683 u_int addr, *val; 1684 { 1685 u_int32_t reg; 1686 int i; 1687 1688 for (i = 1000; --i >= 0; ) { 1689 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1690 break; 1691 DELAY(100); 1692 } 1693 1694 if (i < 0) { 1695 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1696 sc->sc_dev.dv_xname); 1697 return ETIMEDOUT; 1698 } 1699 1700 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1701 1702 ATW_WRITE(sc, ATW_BBPCTL, reg); 1703 1704 for (i = 1000; --i >= 0; ) { 1705 DELAY(100); 1706 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1707 break; 1708 } 1709 1710 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1711 1712 if (i < 0) { 1713 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1714 sc->sc_dev.dv_xname, reg); 1715 return ETIMEDOUT; 1716 } 1717 if (val != NULL) 1718 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1719 return 0; 1720 } 1721 #endif /* ATW_DEBUG */ 1722 1723 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1724 * provided by the ADM8211 for that purpose. 1725 * 1726 * val is 18 bits of data, and val is the 4-bit address of the register. 1727 * 1728 * Return 0 on success. 1729 */ 1730 static int 1731 atw_si4126_write(sc, addr, val) 1732 struct atw_softc *sc; 1733 u_int addr, val; 1734 { 1735 u_int32_t reg; 1736 int i; 1737 1738 for (i = 1000; --i >= 0; ) { 1739 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1740 break; 1741 DELAY(100); 1742 } 1743 1744 if (i < 0) { 1745 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1746 sc->sc_dev.dv_xname); 1747 return ETIMEDOUT; 1748 } 1749 1750 reg = sc->sc_synctl_wr | 1751 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1752 1753 ATW_WRITE(sc, ATW_SYNCTL, reg); 1754 1755 for (i = 1000; --i >= 0; ) { 1756 DELAY(100); 1757 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1758 break; 1759 } 1760 1761 /* restore to acceptable starting condition */ 1762 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1763 1764 if (i < 0) { 1765 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1766 sc->sc_dev.dv_xname, reg); 1767 return ETIMEDOUT; 1768 } 1769 return 0; 1770 } 1771 1772 /* Read 18-bit data from the 4-bit address addr in Si4126 1773 * RF synthesizer and write the data to *val. Return 0 on success. 1774 * 1775 * XXX This does not seem to work. The ADM8211 must require more or 1776 * different magic to read the chip than to write it. 1777 */ 1778 #ifdef ATW_DEBUG 1779 static int 1780 atw_si4126_read(sc, addr, val) 1781 struct atw_softc *sc; 1782 u_int addr; 1783 u_int *val; 1784 { 1785 u_int32_t reg; 1786 int i; 1787 1788 for (i = 1000; --i >= 0; ) { 1789 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1790 break; 1791 DELAY(100); 1792 } 1793 1794 if (i < 0) { 1795 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1796 sc->sc_dev.dv_xname); 1797 return ETIMEDOUT; 1798 } 1799 1800 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1801 1802 ATW_WRITE(sc, ATW_SYNCTL, reg); 1803 1804 for (i = 1000; --i >= 0; ) { 1805 DELAY(100); 1806 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1807 break; 1808 } 1809 1810 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1811 1812 if (i < 0) { 1813 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1814 sc->sc_dev.dv_xname, reg); 1815 return ETIMEDOUT; 1816 } 1817 if (val != NULL) 1818 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1819 ATW_SYNCTL_DATA_MASK); 1820 return 0; 1821 } 1822 #endif /* ATW_DEBUG */ 1823 1824 /* XXX is the endianness correct? test. */ 1825 #define atw_calchash(addr) \ 1826 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1827 1828 /* 1829 * atw_filter_setup: 1830 * 1831 * Set the ADM8211's receive filter. 1832 */ 1833 static void 1834 atw_filter_setup(sc) 1835 struct atw_softc *sc; 1836 { 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 struct ethercom *ec = &ic->ic_ec; 1839 struct ifnet *ifp = &sc->sc_ic.ic_if; 1840 int hash; 1841 u_int32_t hashes[2] = { 0, 0 }; 1842 struct ether_multi *enm; 1843 struct ether_multistep step; 1844 1845 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1846 sc->sc_dev.dv_xname, sc->sc_flags)); 1847 1848 /* 1849 * If we're running, idle the receive engine. If we're NOT running, 1850 * we're being called from atw_init(), and our writing ATW_NAR will 1851 * start the transmit and receive processes in motion. 1852 */ 1853 if (ifp->if_flags & IFF_RUNNING) 1854 atw_idle(sc, ATW_NAR_SR); 1855 1856 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1857 1858 ifp->if_flags &= ~IFF_ALLMULTI; 1859 1860 if (ifp->if_flags & IFF_PROMISC) { 1861 sc->sc_opmode |= ATW_NAR_PR; 1862 allmulti: 1863 ifp->if_flags |= IFF_ALLMULTI; 1864 goto setit; 1865 } 1866 1867 /* 1868 * Program the 64-bit multicast hash filter. 1869 */ 1870 ETHER_FIRST_MULTI(step, ec, enm); 1871 while (enm != NULL) { 1872 /* XXX */ 1873 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1874 ETHER_ADDR_LEN) != 0) 1875 goto allmulti; 1876 1877 hash = atw_calchash(enm->enm_addrlo); 1878 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1879 ETHER_NEXT_MULTI(step, enm); 1880 } 1881 1882 if (ifp->if_flags & IFF_BROADCAST) { 1883 hash = atw_calchash(etherbroadcastaddr); 1884 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1885 } 1886 1887 /* all bits set => hash is useless */ 1888 if (~(hashes[0] & hashes[1]) == 0) 1889 goto allmulti; 1890 1891 setit: 1892 if (ifp->if_flags & IFF_ALLMULTI) 1893 sc->sc_opmode |= ATW_NAR_MM; 1894 1895 /* XXX in scan mode, do not filter packets. maybe this is 1896 * unnecessary. 1897 */ 1898 if (ic->ic_state == IEEE80211_S_SCAN) 1899 sc->sc_opmode |= ATW_NAR_PR; 1900 1901 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1902 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1903 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1904 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1905 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1906 1907 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1908 } 1909 1910 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1911 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1912 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1913 * no beacon with the preferred BSSID and SSID in the number of 1914 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1915 */ 1916 static void 1917 atw_write_bssid(sc) 1918 struct atw_softc *sc; 1919 { 1920 struct ieee80211com *ic = &sc->sc_ic; 1921 u_int8_t *bssid; 1922 1923 bssid = ic->ic_bss->ni_bssid; 1924 1925 ATW_WRITE(sc, ATW_ABDA1, 1926 (ATW_READ(sc, ATW_ABDA1) & 1927 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1928 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1929 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1930 1931 ATW_WRITE(sc, ATW_BSSID0, 1932 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1933 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1934 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1935 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1936 1937 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1938 ether_sprintf(sc->sc_bssid))); 1939 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1940 1941 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1942 } 1943 1944 /* Tell the ADM8211 how many beacon intervals must pass without 1945 * receiving a beacon with the preferred BSSID & SSID set by 1946 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1947 * raised. 1948 */ 1949 static void 1950 atw_write_bcn_thresh(sc) 1951 struct atw_softc *sc; 1952 { 1953 struct ieee80211com *ic = &sc->sc_ic; 1954 int lost_bcn_thresh; 1955 1956 /* Lose link after one second or 7 beacons, whichever comes 1957 * first, but do not lose link before 2 beacons are lost. 1958 * 1959 * In host AP mode, set the lost-beacon threshold to 0. 1960 */ 1961 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1962 lost_bcn_thresh = 0; 1963 else 1964 lost_bcn_thresh = MAX(2, 1965 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss->ni_intval), 7)); 1966 1967 /* XXX resets wake-up status bits */ 1968 ATW_WRITE(sc, ATW_WCSR, 1969 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1970 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1971 1972 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1973 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1974 1975 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1976 1977 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1978 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1979 } 1980 1981 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1982 * 16-bit word. 1983 */ 1984 static void 1985 atw_write_sram(sc, ofs, buf, buflen) 1986 struct atw_softc *sc; 1987 u_int ofs; 1988 u_int8_t *buf; 1989 u_int buflen; 1990 { 1991 u_int i; 1992 u_int8_t *ptr; 1993 1994 memcpy(&sc->sc_sram[ofs], buf, buflen); 1995 1996 if (ofs % 2 != 0) { 1997 ofs--; 1998 buflen++; 1999 } 2000 2001 if (buflen % 2 != 0) 2002 buflen++; 2003 2004 assert(buflen + ofs <= ATW_SRAM_SIZE); 2005 2006 ptr = &sc->sc_sram[ofs]; 2007 2008 for (i = 0; i < buflen; i += 2) { 2009 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2010 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2011 DELAY(atw_writewep_delay); 2012 2013 ATW_WRITE(sc, ATW_WESK, 2014 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2015 DELAY(atw_writewep_delay); 2016 } 2017 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2018 2019 if (sc->sc_if.if_flags & IFF_DEBUG) { 2020 int n_octets = 0; 2021 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2022 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2023 for (i = 0; i < buflen; i++) { 2024 printf(" %02x", ptr[i]); 2025 if (++n_octets % 24 == 0) 2026 printf("\n"); 2027 } 2028 if (n_octets % 24 != 0) 2029 printf("\n"); 2030 } 2031 } 2032 2033 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2034 static void 2035 atw_write_wep(sc) 2036 struct atw_softc *sc; 2037 { 2038 struct ieee80211com *ic = &sc->sc_ic; 2039 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2040 u_int8_t buf[IEEE80211_WEP_NKID] 2041 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2042 u_int32_t reg; 2043 int i; 2044 2045 sc->sc_wepctl = 0; 2046 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2047 2048 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2049 return; 2050 2051 memset(&buf[0][0], 0, sizeof(buf)); 2052 2053 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2054 if (ic->ic_nw_keys[i].wk_len > 5) { 2055 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2056 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2057 buf[i][1] = ATW_WEP_ENABLED; 2058 } else { 2059 buf[i][1] = 0; 2060 continue; 2061 } 2062 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2063 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2064 ic->ic_nw_keys[i].wk_len - 1); 2065 } 2066 2067 reg = ATW_READ(sc, ATW_MACTEST); 2068 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2069 reg &= ~ATW_MACTEST_KEYID_MASK; 2070 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2071 ATW_WRITE(sc, ATW_MACTEST, reg); 2072 2073 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2074 * throughout.) 2075 */ 2076 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2077 if (sc->sc_if.if_flags & IFF_LINK2) 2078 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2079 2080 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2081 sizeof(buf)); 2082 } 2083 2084 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2085 2086 static void 2087 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2088 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2089 { 2090 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2091 2092 switch (subtype) { 2093 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2094 /* do nothing: hardware answers probe request */ 2095 break; 2096 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2097 case IEEE80211_FC0_SUBTYPE_BEACON: 2098 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2099 break; 2100 default: 2101 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2102 break; 2103 } 2104 return; 2105 } 2106 2107 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2108 * of IBSSs with like SSID/channel but different BSSID. It joins the 2109 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2110 * convention. Possibly the ADMtek chip does this for us; I will have 2111 * to test to find out. 2112 * 2113 * XXX we should add the duration field of the received beacon to 2114 * the TSF time it contains before comparing it with the ADM8211's 2115 * TSF. 2116 */ 2117 static void 2118 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2119 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2120 { 2121 struct atw_softc *sc; 2122 struct ieee80211_frame *wh; 2123 u_int64_t tsft, bcn_tsft; 2124 u_int32_t tsftl, tsfth; 2125 int do_print = 0; 2126 2127 sc = (struct atw_softc*)ic->ic_if.if_softc; 2128 2129 if (ic->ic_if.if_flags & IFF_DEBUG) 2130 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2131 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2132 2133 wh = mtod(m0, struct ieee80211_frame *); 2134 2135 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2136 2137 if (ic->ic_state != IEEE80211_S_RUN) { 2138 if (do_print) 2139 printf("%s: atw_recv_beacon: not running\n", 2140 sc->sc_dev.dv_xname); 2141 return; 2142 } 2143 2144 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2145 ic->ic_bss->ni_chan)) == NULL) { 2146 if (do_print) 2147 printf("%s: atw_recv_beacon: no node %s\n", 2148 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2149 return; 2150 } 2151 2152 if (ieee80211_match_bss(ic, ni) != 0) { 2153 if (do_print) 2154 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2155 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2156 return; 2157 } 2158 2159 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2160 return; 2161 2162 if (do_print) 2163 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2164 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2165 2166 if (ic->ic_opmode != IEEE80211_M_IBSS) 2167 return; 2168 2169 /* If we read TSFTL right before rollover, we read a TSF timer 2170 * that is too high rather than too low. This prevents a spurious 2171 * synchronization down the line, however, our IBSS could suffer 2172 * from a creeping TSF.... 2173 */ 2174 tsftl = ATW_READ(sc, ATW_TSFTL); 2175 tsfth = ATW_READ(sc, ATW_TSFTH); 2176 2177 tsft = (u_int64_t)tsfth << 32 | tsftl; 2178 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2179 2180 if (do_print) 2181 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2182 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2183 2184 /* we are faster, let the other guy catch up */ 2185 if (bcn_tsft < tsft) 2186 return; 2187 2188 if (do_print) 2189 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2190 ether_sprintf(wh->i_addr2)); 2191 2192 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2193 2194 #if 0 2195 atw_tsf(sc); 2196 #endif 2197 2198 /* negotiate rates with new IBSS */ 2199 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2200 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2201 if (ni->ni_rates.rs_nrates == 0) { 2202 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2203 ether_sprintf(ni->ni_bssid)); 2204 return; 2205 } 2206 2207 if (do_print) { 2208 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2209 ether_sprintf(ic->ic_bss->ni_bssid)); 2210 printf("%s ", ether_sprintf(ni->ni_bssid)); 2211 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2212 } 2213 2214 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2215 2216 atw_write_bssid(sc); 2217 atw_write_bcn_thresh(sc); 2218 atw_start_beacon(sc, 1); 2219 } 2220 2221 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2222 * In ad hoc mode, the SSID is written to the beacons sent by the 2223 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2224 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2225 * indications. 2226 */ 2227 static void 2228 atw_write_ssid(sc) 2229 struct atw_softc *sc; 2230 { 2231 struct ieee80211com *ic = &sc->sc_ic; 2232 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2233 u_int8_t buf[1 /* length */ + IEEE80211_NWID_LEN + 2234 1 /* for a round number */]; 2235 2236 memset(buf, 0, sizeof(buf)); 2237 buf[0] = ic->ic_bss->ni_esslen; 2238 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2239 2240 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2241 } 2242 2243 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2244 * In ad hoc mode, the supported rates are written to beacons sent by the 2245 * ADM8211. 2246 */ 2247 static void 2248 atw_write_sup_rates(sc) 2249 struct atw_softc *sc; 2250 { 2251 struct ieee80211com *ic = &sc->sc_ic; 2252 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2253 * supported rates 2254 */ 2255 u_int8_t buf[1 /* length */ + IEEE80211_RATE_SIZE + 2256 1 /* for a round number */]; 2257 2258 memset(buf, 0, sizeof(buf)); 2259 2260 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2261 2262 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2263 ic->ic_bss->ni_rates.rs_nrates); 2264 2265 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2266 } 2267 2268 /* Start/stop sending beacons. */ 2269 void 2270 atw_start_beacon(struct atw_softc *sc, int start) 2271 { 2272 struct ieee80211com *ic = &sc->sc_ic; 2273 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2274 2275 if (ATW_IS_ENABLED(sc) == 0) 2276 return; 2277 2278 len = capinfo = 0; 2279 2280 /* start beacons */ 2281 len = sizeof(struct ieee80211_frame) + 2282 8 /* timestamp */ + 2 /* beacon interval */ + 2283 2 /* capability info */ + 2284 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2285 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2286 3 /* DS parameters */ + 2287 IEEE80211_CRC_LEN; 2288 2289 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2290 2291 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2292 2293 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2294 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2295 2296 if (!start) 2297 return; 2298 2299 /* TBD use ni_capinfo */ 2300 2301 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2302 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2303 if (ic->ic_flags & IEEE80211_F_WEPON) 2304 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2305 2306 switch (ic->ic_opmode) { 2307 case IEEE80211_M_IBSS: 2308 len += 4; /* IBSS parameters */ 2309 capinfo |= IEEE80211_CAPINFO_IBSS; 2310 break; 2311 case IEEE80211_M_HOSTAP: 2312 /* XXX 6-byte minimum TIM */ 2313 len += atw_beacon_len_adjust; 2314 capinfo |= IEEE80211_CAPINFO_ESS; 2315 break; 2316 default: 2317 return; 2318 } 2319 2320 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2321 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2322 2323 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2324 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2325 2326 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2327 sc->sc_dev.dv_xname, reg_bcnt)); 2328 2329 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2330 sc->sc_dev.dv_xname, reg_cap1)); 2331 } 2332 2333 /* First beacon was sent at time 0 microseconds, current time is 2334 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2335 * microseconds. Return the expected time in microseconds for the 2336 * beacon after next. 2337 */ 2338 static __inline u_int64_t 2339 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2340 { 2341 return tsft + (tbtt - tsft % tbtt); 2342 } 2343 2344 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2345 * the ieee80211com. 2346 * 2347 * Predict the next target beacon transmission time (TBTT) and 2348 * write it to the ADM8211. 2349 */ 2350 static void 2351 atw_tsf(struct atw_softc *sc) 2352 { 2353 #define TBTTOFS 20 /* TU */ 2354 2355 struct ieee80211com *ic = &sc->sc_ic; 2356 u_int64_t tsft, tbtt; 2357 2358 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2359 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2360 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2361 tsft = ATW_READ(sc, ATW_TSFTH); 2362 tsft <<= 32; 2363 tsft |= ATW_READ(sc, ATW_TSFTL); 2364 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2365 } else 2366 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2367 2368 tbtt = atw_predict_beacon(tsft, 2369 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2370 2371 /* skip one more beacon so that the TBTT cannot pass before 2372 * we've programmed it, and also so that we can subtract a 2373 * few TU so that we wake a little before TBTT. 2374 */ 2375 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2376 2377 /* wake up a little early */ 2378 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2379 2380 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2381 sc->sc_dev.dv_xname, tsft, tbtt)); 2382 2383 ATW_WRITE(sc, ATW_TOFS1, 2384 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2385 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2386 LSHIFT( 2387 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2388 ATW_TOFS1_TBTTPRE_MASK)); 2389 #undef TBTTOFS 2390 } 2391 2392 static void 2393 atw_next_scan(void *arg) 2394 { 2395 struct atw_softc *sc = arg; 2396 struct ieee80211com *ic = &sc->sc_ic; 2397 struct ifnet *ifp = &ic->ic_if; 2398 int s; 2399 2400 /* don't call atw_start w/o network interrupts blocked */ 2401 s = splnet(); 2402 if (ic->ic_state == IEEE80211_S_SCAN) 2403 ieee80211_next_scan(ifp); 2404 splx(s); 2405 } 2406 2407 /* Synchronize the hardware state with the software state. */ 2408 static int 2409 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2410 { 2411 struct ifnet *ifp = &ic->ic_if; 2412 struct atw_softc *sc = ifp->if_softc; 2413 enum ieee80211_state ostate; 2414 int error; 2415 2416 ostate = ic->ic_state; 2417 2418 if (nstate == IEEE80211_S_INIT) { 2419 callout_stop(&sc->sc_scan_ch); 2420 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2421 atw_start_beacon(sc, 0); 2422 return (*sc->sc_newstate)(ic, nstate, arg); 2423 } 2424 2425 if ((error = atw_tune(sc)) != 0) 2426 return error; 2427 2428 switch (nstate) { 2429 case IEEE80211_S_ASSOC: 2430 break; 2431 case IEEE80211_S_INIT: 2432 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2433 break; 2434 case IEEE80211_S_SCAN: 2435 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2436 atw_write_bssid(sc); 2437 2438 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2439 atw_next_scan, sc); 2440 2441 break; 2442 case IEEE80211_S_RUN: 2443 if (ic->ic_opmode == IEEE80211_M_STA) 2444 break; 2445 /*FALLTHROUGH*/ 2446 case IEEE80211_S_AUTH: 2447 atw_write_bssid(sc); 2448 atw_write_bcn_thresh(sc); 2449 atw_write_ssid(sc); 2450 atw_write_sup_rates(sc); 2451 2452 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2453 ic->ic_opmode == IEEE80211_M_MONITOR) 2454 break; 2455 2456 /* set listen interval 2457 * XXX do software units agree w/ hardware? 2458 */ 2459 ATW_WRITE(sc, ATW_BPLI, 2460 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2461 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2462 ATW_BPLI_LI_MASK)); 2463 2464 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2465 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2466 2467 atw_tsf(sc); 2468 break; 2469 } 2470 2471 if (nstate != IEEE80211_S_SCAN) 2472 callout_stop(&sc->sc_scan_ch); 2473 2474 if (nstate == IEEE80211_S_RUN && 2475 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2476 ic->ic_opmode == IEEE80211_M_IBSS)) 2477 atw_start_beacon(sc, 1); 2478 else 2479 atw_start_beacon(sc, 0); 2480 2481 return (*sc->sc_newstate)(ic, nstate, arg); 2482 } 2483 2484 /* 2485 * atw_add_rxbuf: 2486 * 2487 * Add a receive buffer to the indicated descriptor. 2488 */ 2489 int 2490 atw_add_rxbuf(sc, idx) 2491 struct atw_softc *sc; 2492 int idx; 2493 { 2494 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2495 struct mbuf *m; 2496 int error; 2497 2498 MGETHDR(m, M_DONTWAIT, MT_DATA); 2499 if (m == NULL) 2500 return (ENOBUFS); 2501 2502 MCLGET(m, M_DONTWAIT); 2503 if ((m->m_flags & M_EXT) == 0) { 2504 m_freem(m); 2505 return (ENOBUFS); 2506 } 2507 2508 if (rxs->rxs_mbuf != NULL) 2509 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2510 2511 rxs->rxs_mbuf = m; 2512 2513 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2514 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2515 BUS_DMA_READ|BUS_DMA_NOWAIT); 2516 if (error) { 2517 printf("%s: can't load rx DMA map %d, error = %d\n", 2518 sc->sc_dev.dv_xname, idx, error); 2519 panic("atw_add_rxbuf"); /* XXX */ 2520 } 2521 2522 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2523 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2524 2525 ATW_INIT_RXDESC(sc, idx); 2526 2527 return (0); 2528 } 2529 2530 /* 2531 * atw_stop: [ ifnet interface function ] 2532 * 2533 * Stop transmission on the interface. 2534 */ 2535 void 2536 atw_stop(ifp, disable) 2537 struct ifnet *ifp; 2538 int disable; 2539 { 2540 struct atw_softc *sc = ifp->if_softc; 2541 struct ieee80211com *ic = &sc->sc_ic; 2542 struct atw_txsoft *txs; 2543 2544 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2545 2546 /* Disable interrupts. */ 2547 ATW_WRITE(sc, ATW_IER, 0); 2548 2549 /* Stop the transmit and receive processes. */ 2550 sc->sc_opmode = 0; 2551 ATW_WRITE(sc, ATW_NAR, 0); 2552 ATW_WRITE(sc, ATW_TDBD, 0); 2553 ATW_WRITE(sc, ATW_TDBP, 0); 2554 ATW_WRITE(sc, ATW_RDB, 0); 2555 2556 /* 2557 * Release any queued transmit buffers. 2558 */ 2559 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2560 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2561 if (txs->txs_mbuf != NULL) { 2562 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2563 m_freem(txs->txs_mbuf); 2564 txs->txs_mbuf = NULL; 2565 } 2566 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2567 } 2568 2569 if (disable) { 2570 atw_rxdrain(sc); 2571 atw_disable(sc); 2572 } 2573 2574 /* 2575 * Mark the interface down and cancel the watchdog timer. 2576 */ 2577 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2578 ifp->if_timer = 0; 2579 2580 /* XXX */ 2581 atw_reset(sc); 2582 } 2583 2584 /* 2585 * atw_rxdrain: 2586 * 2587 * Drain the receive queue. 2588 */ 2589 void 2590 atw_rxdrain(sc) 2591 struct atw_softc *sc; 2592 { 2593 struct atw_rxsoft *rxs; 2594 int i; 2595 2596 for (i = 0; i < ATW_NRXDESC; i++) { 2597 rxs = &sc->sc_rxsoft[i]; 2598 if (rxs->rxs_mbuf == NULL) 2599 continue; 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 m_freem(rxs->rxs_mbuf); 2602 rxs->rxs_mbuf = NULL; 2603 } 2604 } 2605 2606 /* 2607 * atw_detach: 2608 * 2609 * Detach an ADM8211 interface. 2610 */ 2611 int 2612 atw_detach(sc) 2613 struct atw_softc *sc; 2614 { 2615 struct ifnet *ifp = &sc->sc_ic.ic_if; 2616 struct atw_rxsoft *rxs; 2617 struct atw_txsoft *txs; 2618 int i; 2619 2620 /* 2621 * Succeed now if there isn't any work to do. 2622 */ 2623 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2624 return (0); 2625 2626 ieee80211_ifdetach(ifp); 2627 if_detach(ifp); 2628 2629 for (i = 0; i < ATW_NRXDESC; i++) { 2630 rxs = &sc->sc_rxsoft[i]; 2631 if (rxs->rxs_mbuf != NULL) { 2632 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2633 m_freem(rxs->rxs_mbuf); 2634 rxs->rxs_mbuf = NULL; 2635 } 2636 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2637 } 2638 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2639 txs = &sc->sc_txsoft[i]; 2640 if (txs->txs_mbuf != NULL) { 2641 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2642 m_freem(txs->txs_mbuf); 2643 txs->txs_mbuf = NULL; 2644 } 2645 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2646 } 2647 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2648 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2649 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2650 sizeof(struct atw_control_data)); 2651 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2652 2653 shutdownhook_disestablish(sc->sc_sdhook); 2654 powerhook_disestablish(sc->sc_powerhook); 2655 2656 if (sc->sc_srom) 2657 free(sc->sc_srom, M_DEVBUF); 2658 2659 return (0); 2660 } 2661 2662 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2663 void 2664 atw_shutdown(arg) 2665 void *arg; 2666 { 2667 struct atw_softc *sc = arg; 2668 2669 atw_stop(&sc->sc_ic.ic_if, 1); 2670 } 2671 2672 int 2673 atw_intr(arg) 2674 void *arg; 2675 { 2676 struct atw_softc *sc = arg; 2677 struct ifnet *ifp = &sc->sc_ic.ic_if; 2678 u_int32_t status, rxstatus, txstatus, linkstatus; 2679 int handled = 0, txthresh; 2680 2681 #ifdef DEBUG 2682 if (ATW_IS_ENABLED(sc) == 0) 2683 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2684 #endif 2685 2686 /* 2687 * If the interface isn't running, the interrupt couldn't 2688 * possibly have come from us. 2689 */ 2690 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2691 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2692 return (0); 2693 2694 for (;;) { 2695 status = ATW_READ(sc, ATW_STSR); 2696 2697 if (status) 2698 ATW_WRITE(sc, ATW_STSR, status); 2699 2700 if (sc->sc_intr_ack != NULL) 2701 (*sc->sc_intr_ack)(sc); 2702 2703 #ifdef ATW_DEBUG 2704 #define PRINTINTR(flag) do { \ 2705 if ((status & flag) != 0) { \ 2706 printf("%s" #flag, delim); \ 2707 delim = ","; \ 2708 } \ 2709 } while (0) 2710 2711 if (atw_debug > 1 && status) { 2712 const char *delim = "<"; 2713 2714 printf("%s: reg[STSR] = %x", 2715 sc->sc_dev.dv_xname, status); 2716 2717 PRINTINTR(ATW_INTR_FBE); 2718 PRINTINTR(ATW_INTR_LINKOFF); 2719 PRINTINTR(ATW_INTR_LINKON); 2720 PRINTINTR(ATW_INTR_RCI); 2721 PRINTINTR(ATW_INTR_RDU); 2722 PRINTINTR(ATW_INTR_REIS); 2723 PRINTINTR(ATW_INTR_RPS); 2724 PRINTINTR(ATW_INTR_TCI); 2725 PRINTINTR(ATW_INTR_TDU); 2726 PRINTINTR(ATW_INTR_TLT); 2727 PRINTINTR(ATW_INTR_TPS); 2728 PRINTINTR(ATW_INTR_TRT); 2729 PRINTINTR(ATW_INTR_TUF); 2730 PRINTINTR(ATW_INTR_BCNTC); 2731 PRINTINTR(ATW_INTR_ATIME); 2732 PRINTINTR(ATW_INTR_TBTT); 2733 PRINTINTR(ATW_INTR_TSCZ); 2734 PRINTINTR(ATW_INTR_TSFTF); 2735 printf(">\n"); 2736 } 2737 #undef PRINTINTR 2738 #endif /* ATW_DEBUG */ 2739 2740 if ((status & sc->sc_inten) == 0) 2741 break; 2742 2743 handled = 1; 2744 2745 rxstatus = status & sc->sc_rxint_mask; 2746 txstatus = status & sc->sc_txint_mask; 2747 linkstatus = status & sc->sc_linkint_mask; 2748 2749 if (linkstatus) { 2750 atw_linkintr(sc, linkstatus); 2751 } 2752 2753 if (rxstatus) { 2754 /* Grab any new packets. */ 2755 atw_rxintr(sc); 2756 2757 if (rxstatus & ATW_INTR_RDU) { 2758 printf("%s: receive ring overrun\n", 2759 sc->sc_dev.dv_xname); 2760 /* Get the receive process going again. */ 2761 ATW_WRITE(sc, ATW_RDR, 0x1); 2762 break; 2763 } 2764 } 2765 2766 if (txstatus) { 2767 /* Sweep up transmit descriptors. */ 2768 atw_txintr(sc); 2769 2770 if (txstatus & ATW_INTR_TLT) 2771 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2772 sc->sc_dev.dv_xname)); 2773 2774 if (txstatus & ATW_INTR_TRT) 2775 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2776 sc->sc_dev.dv_xname)); 2777 2778 /* If Tx under-run, increase our transmit threshold 2779 * if another is available. 2780 */ 2781 txthresh = sc->sc_txthresh + 1; 2782 if ((txstatus & ATW_INTR_TUF) && 2783 sc->sc_txth[txthresh].txth_name != NULL) { 2784 /* Idle the transmit process. */ 2785 atw_idle(sc, ATW_NAR_ST); 2786 2787 sc->sc_txthresh = txthresh; 2788 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2789 sc->sc_opmode |= 2790 sc->sc_txth[txthresh].txth_opmode; 2791 printf("%s: transmit underrun; new " 2792 "threshold: %s\n", sc->sc_dev.dv_xname, 2793 sc->sc_txth[txthresh].txth_name); 2794 2795 /* Set the new threshold and restart 2796 * the transmit process. 2797 */ 2798 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2799 /* XXX Log every Nth underrun from 2800 * XXX now on? 2801 */ 2802 } 2803 } 2804 2805 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2806 if (status & ATW_INTR_TPS) 2807 printf("%s: transmit process stopped\n", 2808 sc->sc_dev.dv_xname); 2809 if (status & ATW_INTR_RPS) 2810 printf("%s: receive process stopped\n", 2811 sc->sc_dev.dv_xname); 2812 (void)atw_init(ifp); 2813 break; 2814 } 2815 2816 if (status & ATW_INTR_FBE) { 2817 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2818 (void)atw_init(ifp); 2819 break; 2820 } 2821 2822 /* 2823 * Not handled: 2824 * 2825 * Transmit buffer unavailable -- normal 2826 * condition, nothing to do, really. 2827 * 2828 * Early receive interrupt -- not available on 2829 * all chips, we just use RI. We also only 2830 * use single-segment receive DMA, so this 2831 * is mostly useless. 2832 * 2833 * TBD others 2834 */ 2835 } 2836 2837 /* Try to get more packets going. */ 2838 atw_start(ifp); 2839 2840 return (handled); 2841 } 2842 2843 /* 2844 * atw_idle: 2845 * 2846 * Cause the transmit and/or receive processes to go idle. 2847 * 2848 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2849 * process in STSR if I clear SR or ST after the process has already 2850 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2851 * do not seem to be too reliable. Perhaps I have the sense of the 2852 * Rx bits switched with the Tx bits? 2853 */ 2854 void 2855 atw_idle(sc, bits) 2856 struct atw_softc *sc; 2857 u_int32_t bits; 2858 { 2859 u_int32_t ackmask = 0, opmode, stsr, test0; 2860 int i, s; 2861 2862 /* without this, somehow we run concurrently w/ interrupt handler */ 2863 s = splnet(); 2864 2865 opmode = sc->sc_opmode & ~bits; 2866 2867 if (bits & ATW_NAR_SR) 2868 ackmask |= ATW_INTR_RPS; 2869 2870 if (bits & ATW_NAR_ST) { 2871 ackmask |= ATW_INTR_TPS; 2872 /* set ATW_NAR_HF to flush TX FIFO. */ 2873 opmode |= ATW_NAR_HF; 2874 } 2875 2876 ATW_WRITE(sc, ATW_NAR, opmode); 2877 2878 for (i = 0; i < 1000; i++) { 2879 stsr = ATW_READ(sc, ATW_STSR); 2880 if ((stsr & ackmask) == ackmask) 2881 break; 2882 DELAY(10); 2883 } 2884 2885 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2886 2887 if ((stsr & ackmask) == ackmask) 2888 goto out; 2889 2890 test0 = ATW_READ(sc, ATW_TEST0); 2891 2892 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2893 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2894 printf("%s: transmit process not idle [%s]\n", 2895 sc->sc_dev.dv_xname, 2896 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2897 printf("%s: bits %08x test0 %08x stsr %08x\n", 2898 sc->sc_dev.dv_xname, bits, test0, stsr); 2899 } 2900 2901 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2902 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2903 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2904 sc->sc_dev.dv_xname, 2905 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2906 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2907 sc->sc_dev.dv_xname, bits, test0, stsr)); 2908 } 2909 out: 2910 splx(s); 2911 return; 2912 } 2913 2914 /* 2915 * atw_linkintr: 2916 * 2917 * Helper; handle link-status interrupts. 2918 */ 2919 void 2920 atw_linkintr(sc, linkstatus) 2921 struct atw_softc *sc; 2922 u_int32_t linkstatus; 2923 { 2924 struct ieee80211com *ic = &sc->sc_ic; 2925 2926 if (ic->ic_state != IEEE80211_S_RUN) 2927 return; 2928 2929 if (linkstatus & ATW_INTR_LINKON) { 2930 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2931 sc->sc_rescan_timer = 0; 2932 } else if (linkstatus & ATW_INTR_LINKOFF) { 2933 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2934 switch (ic->ic_opmode) { 2935 case IEEE80211_M_IBSS: 2936 if (ic->ic_flags & IEEE80211_F_SIBSS) 2937 return; 2938 /*FALLTHROUGH*/ 2939 case IEEE80211_M_STA: 2940 sc->sc_rescan_timer = 3; 2941 ic->ic_if.if_timer = 1; 2942 break; 2943 default: 2944 break; 2945 } 2946 } 2947 } 2948 2949 /* 2950 * atw_rxintr: 2951 * 2952 * Helper; handle receive interrupts. 2953 */ 2954 void 2955 atw_rxintr(sc) 2956 struct atw_softc *sc; 2957 { 2958 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2959 struct ieee80211com *ic = &sc->sc_ic; 2960 struct ieee80211_node *ni; 2961 struct ieee80211_frame *wh; 2962 struct ifnet *ifp = &ic->ic_if; 2963 struct atw_rxsoft *rxs; 2964 struct mbuf *m; 2965 u_int32_t rxstat; 2966 int i, len, rate, rate0, rssi; 2967 2968 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2969 rxs = &sc->sc_rxsoft[i]; 2970 2971 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2972 2973 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2974 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2975 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2976 2977 if (rxstat & ATW_RXSTAT_OWN) 2978 break; /* We have processed all receive buffers. */ 2979 2980 DPRINTF3(sc, 2981 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2982 sc->sc_dev.dv_xname, 2983 sc->sc_rxdescs[i].ar_stat, 2984 sc->sc_rxdescs[i].ar_rssi, 2985 sc->sc_rxdescs[i].ar_buf1, 2986 sc->sc_rxdescs[i].ar_buf2)); 2987 2988 /* 2989 * Make sure the packet fit in one buffer. This should 2990 * always be the case. 2991 */ 2992 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2993 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2994 printf("%s: incoming packet spilled, resetting\n", 2995 sc->sc_dev.dv_xname); 2996 (void)atw_init(ifp); 2997 return; 2998 } 2999 3000 /* 3001 * If an error occurred, update stats, clear the status 3002 * word, and leave the packet buffer in place. It will 3003 * simply be reused the next time the ring comes around. 3004 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3005 * error. 3006 */ 3007 3008 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3009 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3010 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3011 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3012 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3013 ATW_RXSTAT_ICVE)) != 0)) { 3014 #define PRINTERR(bit, str) \ 3015 if (rxstat & (bit)) \ 3016 printf("%s: receive error: %s\n", \ 3017 sc->sc_dev.dv_xname, str) 3018 ifp->if_ierrors++; 3019 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3020 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3021 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3022 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3023 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3024 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3025 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3026 #undef PRINTERR 3027 ATW_INIT_RXDESC(sc, i); 3028 continue; 3029 } 3030 3031 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3032 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3033 3034 /* 3035 * No errors; receive the packet. Note the ADM8211 3036 * includes the CRC in promiscuous mode. 3037 */ 3038 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3039 3040 /* 3041 * Allocate a new mbuf cluster. If that fails, we are 3042 * out of memory, and must drop the packet and recycle 3043 * the buffer that's already attached to this descriptor. 3044 */ 3045 m = rxs->rxs_mbuf; 3046 if (atw_add_rxbuf(sc, i) != 0) { 3047 ifp->if_ierrors++; 3048 ATW_INIT_RXDESC(sc, i); 3049 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3050 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3051 continue; 3052 } 3053 3054 ifp->if_ipackets++; 3055 if (sc->sc_opmode & ATW_NAR_PR) 3056 m->m_flags |= M_HASFCS; 3057 m->m_pkthdr.rcvif = ifp; 3058 m->m_pkthdr.len = m->m_len = len; 3059 3060 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3061 rate = 0; 3062 else 3063 rate = rate_tbl[rate0]; 3064 3065 #if NBPFILTER > 0 3066 /* Pass this up to any BPF listeners. */ 3067 if (sc->sc_radiobpf != NULL) { 3068 struct mbuf mb; 3069 3070 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3071 3072 tap->ar_rate = rate; 3073 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3074 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3075 3076 /* TBD verify units are dB */ 3077 tap->ar_antsignal = rssi; 3078 /* TBD tap->ar_flags */ 3079 3080 M_COPY_PKTHDR(&mb, m); 3081 mb.m_data = (caddr_t)tap; 3082 mb.m_len = tap->ar_ihdr.it_len; 3083 mb.m_next = m; 3084 mb.m_pkthdr.len += mb.m_len; 3085 bpf_mtap(sc->sc_radiobpf, &mb); 3086 } 3087 #endif /* NPBFILTER > 0 */ 3088 3089 wh = mtod(m, struct ieee80211_frame *); 3090 ni = ieee80211_find_rxnode(ic, wh); 3091 ieee80211_input(ifp, m, ni, rssi, 0); 3092 /* 3093 * The frame may have caused the node to be marked for 3094 * reclamation (e.g. in response to a DEAUTH message) 3095 * so use free_node here instead of unref_node. 3096 */ 3097 if (ni == ic->ic_bss) 3098 ieee80211_unref_node(&ni); 3099 else 3100 ieee80211_free_node(ic, ni); 3101 } 3102 3103 /* Update the receive pointer. */ 3104 sc->sc_rxptr = i; 3105 } 3106 3107 /* 3108 * atw_txintr: 3109 * 3110 * Helper; handle transmit interrupts. 3111 */ 3112 void 3113 atw_txintr(sc) 3114 struct atw_softc *sc; 3115 { 3116 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3117 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3118 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3119 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3120 3121 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3122 struct ifnet *ifp = &sc->sc_ic.ic_if; 3123 struct atw_txsoft *txs; 3124 u_int32_t txstat; 3125 3126 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3127 sc->sc_dev.dv_xname, sc->sc_flags)); 3128 3129 ifp->if_flags &= ~IFF_OACTIVE; 3130 3131 /* 3132 * Go through our Tx list and free mbufs for those 3133 * frames that have been transmitted. 3134 */ 3135 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3136 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3137 txs->txs_ndescs, 3138 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3139 3140 #ifdef ATW_DEBUG 3141 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3142 int i; 3143 printf(" txsoft %p transmit chain:\n", txs); 3144 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3145 printf(" descriptor %d:\n", i); 3146 printf(" at_status: 0x%08x\n", 3147 le32toh(sc->sc_txdescs[i].at_stat)); 3148 printf(" at_flags: 0x%08x\n", 3149 le32toh(sc->sc_txdescs[i].at_flags)); 3150 printf(" at_buf1: 0x%08x\n", 3151 le32toh(sc->sc_txdescs[i].at_buf1)); 3152 printf(" at_buf2: 0x%08x\n", 3153 le32toh(sc->sc_txdescs[i].at_buf2)); 3154 if (i == txs->txs_lastdesc) 3155 break; 3156 } 3157 } 3158 #endif 3159 3160 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3161 if (txstat & ATW_TXSTAT_OWN) 3162 break; 3163 3164 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3165 3166 sc->sc_txfree += txs->txs_ndescs; 3167 3168 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3169 0, txs->txs_dmamap->dm_mapsize, 3170 BUS_DMASYNC_POSTWRITE); 3171 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3172 m_freem(txs->txs_mbuf); 3173 txs->txs_mbuf = NULL; 3174 3175 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3176 3177 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3178 (txstat & TXSTAT_ERRMASK) != 0) { 3179 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3180 txstat_buf, sizeof(txstat_buf)); 3181 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3182 txstat_buf, 3183 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3184 } 3185 3186 /* 3187 * Check for errors and collisions. 3188 */ 3189 if (txstat & ATW_TXSTAT_TUF) 3190 sc->sc_stats.ts_tx_tuf++; 3191 if (txstat & ATW_TXSTAT_TLT) 3192 sc->sc_stats.ts_tx_tlt++; 3193 if (txstat & ATW_TXSTAT_TRT) 3194 sc->sc_stats.ts_tx_trt++; 3195 if (txstat & ATW_TXSTAT_TRO) 3196 sc->sc_stats.ts_tx_tro++; 3197 if (txstat & ATW_TXSTAT_SOFBR) { 3198 sc->sc_stats.ts_tx_sofbr++; 3199 } 3200 3201 if ((txstat & ATW_TXSTAT_ES) == 0) 3202 ifp->if_collisions += 3203 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3204 else 3205 ifp->if_oerrors++; 3206 3207 ifp->if_opackets++; 3208 } 3209 3210 /* 3211 * If there are no more pending transmissions, cancel the watchdog 3212 * timer. 3213 */ 3214 if (txs == NULL) 3215 sc->sc_tx_timer = 0; 3216 #undef TXSTAT_ERRMASK 3217 #undef TXSTAT_FMT 3218 } 3219 3220 /* 3221 * atw_watchdog: [ifnet interface function] 3222 * 3223 * Watchdog timer handler. 3224 */ 3225 void 3226 atw_watchdog(ifp) 3227 struct ifnet *ifp; 3228 { 3229 struct atw_softc *sc = ifp->if_softc; 3230 struct ieee80211com *ic = &sc->sc_ic; 3231 3232 ifp->if_timer = 0; 3233 if (ATW_IS_ENABLED(sc) == 0) 3234 return; 3235 3236 if (sc->sc_rescan_timer) { 3237 if (--sc->sc_rescan_timer == 0) 3238 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3239 } 3240 if (sc->sc_tx_timer) { 3241 if (--sc->sc_tx_timer == 0 && 3242 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3243 printf("%s: transmit timeout\n", ifp->if_xname); 3244 ifp->if_oerrors++; 3245 (void)atw_init(ifp); 3246 atw_start(ifp); 3247 } 3248 } 3249 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3250 ifp->if_timer = 1; 3251 ieee80211_watchdog(ifp); 3252 } 3253 3254 /* Compute the 802.11 Duration field and the PLCP Length fields for 3255 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3256 * Write the fields to the ADM8211 Tx header, frm. 3257 * 3258 * TBD use the fragmentation threshold to find the right duration for 3259 * the first & last fragments. 3260 * 3261 * TBD make certain of the duration fields applied by the ADM8211 to each 3262 * fragment. I think that the ADM8211 knows how to subtract the CTS 3263 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3264 * I also think that the ADM8211 does *some* arithmetic for us, because 3265 * otherwise I think we would have to set a first duration for CTS/first 3266 * fragment, a second duration for fragments between the first and the 3267 * last, and a third duration for the last fragment. 3268 * 3269 * TBD make certain that duration fields reflect addition of FCS/WEP 3270 * and correct duration arithmetic as necessary. 3271 */ 3272 static void 3273 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3274 int len) 3275 { 3276 int remainder; 3277 3278 /* deal also with encrypted fragments */ 3279 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3280 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3281 sc->sc_dev.dv_xname)); 3282 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3283 IEEE80211_WEP_CRCLEN; 3284 } 3285 3286 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3287 * duration (XXX added by MAC?). 3288 */ 3289 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3290 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3291 3292 if (rate <= 4) 3293 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3294 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3295 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3296 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3297 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3298 else 3299 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3300 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3301 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3302 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3303 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3304 3305 /* lengthen duration if long preamble */ 3306 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3307 frm->atw_head_dur += 3308 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3309 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3310 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3311 IEEE80211_DUR_DS_FAST_PLCPHDR); 3312 3313 if (remainder != 0) 3314 frm->atw_head_dur++; 3315 3316 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3317 (rate == 2 || rate == 4)) { 3318 /* derived from Linux: how could this be right? */ 3319 frm->atw_head_plcplen = frm->atw_head_dur; 3320 } else { 3321 frm->atw_head_plcplen = (16 * len) / rate; 3322 remainder = (80 * len) % (rate * 5); 3323 3324 if (remainder != 0) { 3325 frm->atw_head_plcplen++; 3326 3327 /* XXX magic */ 3328 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3329 rate == 22 && remainder <= 30) 3330 frm->atw_head_plcplen |= 0x8000; 3331 } 3332 } 3333 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3334 htole16(frm->atw_head_plcplen); 3335 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3336 } 3337 3338 #ifdef ATW_DEBUG 3339 static void 3340 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3341 { 3342 struct atw_softc *sc = ifp->if_softc; 3343 struct mbuf *m; 3344 int i, noctets = 0; 3345 3346 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3347 m0->m_pkthdr.len); 3348 3349 for (m = m0; m; m = m->m_next) { 3350 if (m->m_len == 0) 3351 continue; 3352 for (i = 0; i < m->m_len; i++) { 3353 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3354 if (++noctets % 24 == 0) 3355 printf("\n"); 3356 } 3357 } 3358 printf("%s%s: %d bytes emitted\n", 3359 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3360 } 3361 #endif /* ATW_DEBUG */ 3362 3363 /* 3364 * atw_start: [ifnet interface function] 3365 * 3366 * Start packet transmission on the interface. 3367 */ 3368 void 3369 atw_start(ifp) 3370 struct ifnet *ifp; 3371 { 3372 struct atw_softc *sc = ifp->if_softc; 3373 struct ieee80211com *ic = &sc->sc_ic; 3374 struct ieee80211_node *ni; 3375 struct ieee80211_frame *wh; 3376 struct atw_frame *hh; 3377 struct mbuf *m0, *m; 3378 struct atw_txsoft *txs, *last_txs; 3379 struct atw_txdesc *txd; 3380 int do_encrypt, rate; 3381 bus_dmamap_t dmamap; 3382 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3383 3384 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3385 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3386 3387 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3388 return; 3389 3390 #if 0 /* TBD ??? */ 3391 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3392 return; 3393 #endif 3394 3395 /* 3396 * Remember the previous number of free descriptors and 3397 * the first descriptor we'll use. 3398 */ 3399 ofree = sc->sc_txfree; 3400 firsttx = sc->sc_txnext; 3401 3402 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3403 sc->sc_dev.dv_xname, ofree, firsttx)); 3404 3405 /* 3406 * Loop through the send queue, setting up transmit descriptors 3407 * until we drain the queue, or use up all available transmit 3408 * descriptors. 3409 */ 3410 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3411 sc->sc_txfree != 0) { 3412 3413 do_encrypt = 0; 3414 /* 3415 * Grab a packet off the management queue, if it 3416 * is not empty. Otherwise, from the data queue. 3417 */ 3418 IF_DEQUEUE(&ic->ic_mgtq, m0); 3419 if (m0 != NULL) { 3420 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3421 m0->m_pkthdr.rcvif = NULL; 3422 } else { 3423 IFQ_DEQUEUE(&ifp->if_snd, m0); 3424 if (m0 == NULL) 3425 break; 3426 #if NBPFILTER > 0 3427 if (ifp->if_bpf != NULL) 3428 bpf_mtap(ifp->if_bpf, m0); 3429 #endif /* NBPFILTER > 0 */ 3430 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3431 ifp->if_oerrors++; 3432 break; 3433 } 3434 } 3435 3436 rate = MAX(ieee80211_get_rate(ic), 2); 3437 3438 #if NBPFILTER > 0 3439 /* 3440 * Pass the packet to any BPF listeners. 3441 */ 3442 if (ic->ic_rawbpf != NULL) 3443 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3444 3445 if (sc->sc_radiobpf != NULL) { 3446 struct mbuf mb; 3447 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3448 3449 tap->at_rate = rate; 3450 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3451 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3452 3453 /* TBD tap->at_flags */ 3454 3455 M_COPY_PKTHDR(&mb, m0); 3456 mb.m_data = (caddr_t)tap; 3457 mb.m_len = tap->at_ihdr.it_len; 3458 mb.m_next = m0; 3459 mb.m_pkthdr.len += mb.m_len; 3460 bpf_mtap(sc->sc_radiobpf, &mb); 3461 } 3462 #endif /* NBPFILTER > 0 */ 3463 3464 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3465 3466 if (ni != NULL && ni != ic->ic_bss) 3467 ieee80211_free_node(ic, ni); 3468 3469 if (m0 == NULL) { 3470 ifp->if_oerrors++; 3471 break; 3472 } 3473 3474 /* just to make sure. */ 3475 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3476 3477 if (m0 == NULL) { 3478 ifp->if_oerrors++; 3479 break; 3480 } 3481 3482 hh = mtod(m0, struct atw_frame *); 3483 wh = &hh->atw_ihdr; 3484 3485 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3486 3487 /* Copy everything we need from the 802.11 header: 3488 * Frame Control; address 1, address 3, or addresses 3489 * 3 and 4. NIC fills in BSSID, SA. 3490 */ 3491 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3492 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3493 panic("%s: illegal WDS frame", 3494 sc->sc_dev.dv_xname); 3495 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3496 } else 3497 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3498 3499 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3500 3501 /* initialize remaining Tx parameters */ 3502 memset(&hh->u, 0, sizeof(hh->u)); 3503 3504 hh->atw_rate = rate * 5; 3505 /* XXX this could be incorrect if M_FCS. _encap should 3506 * probably strip FCS just in case it sticks around in 3507 * bridged packets. 3508 */ 3509 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3510 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3511 sizeof(struct atw_frame)); 3512 3513 #if 0 3514 /* this virtually guaranteed that WEP-encrypted frames 3515 * are fragmented. oops. 3516 */ 3517 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3518 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3519 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3520 #else 3521 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3522 #endif 3523 3524 hh->atw_rtylmt = 3; 3525 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3526 if (do_encrypt) { 3527 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3528 hh->atw_keyid = ic->ic_wep_txkey; 3529 } 3530 3531 /* TBD 4-addr frames */ 3532 atw_frame_setdurs(sc, hh, rate, 3533 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3534 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3535 3536 /* never fragment multicast frames */ 3537 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3538 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3539 } else if (sc->sc_flags & ATWF_RTSCTS) { 3540 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3541 } 3542 3543 #ifdef ATW_DEBUG 3544 /* experimental stuff */ 3545 if (atw_xrtylmt != ~0) 3546 hh->atw_rtylmt = atw_xrtylmt; 3547 if (atw_xhdrctl != 0) 3548 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3549 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3550 hh->atw_service = atw_xservice; 3551 if (atw_xpaylen != 0) 3552 hh->atw_paylen = htole16(atw_xpaylen); 3553 hh->atw_fragnum = 0; 3554 3555 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3556 printf("%s: dst = %s, rate = 0x%02x, " 3557 "service = 0x%02x, paylen = 0x%04x\n", 3558 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3559 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3560 3561 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3562 "dur1 = 0x%04x, dur2 = 0x%04x, " 3563 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3564 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3565 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3566 hh->atw_tail_dur, hh->atw_head_dur); 3567 3568 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3569 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3570 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3571 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3572 3573 printf("%s: keyid = %d\n", 3574 sc->sc_dev.dv_xname, hh->atw_keyid); 3575 3576 atw_dump_pkt(ifp, m0); 3577 } 3578 #endif /* ATW_DEBUG */ 3579 3580 dmamap = txs->txs_dmamap; 3581 3582 /* 3583 * Load the DMA map. Copy and try (once) again if the packet 3584 * didn't fit in the alloted number of segments. 3585 */ 3586 for (first = 1; 3587 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3588 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3589 first = 0) { 3590 MGETHDR(m, M_DONTWAIT, MT_DATA); 3591 if (m == NULL) { 3592 printf("%s: unable to allocate Tx mbuf\n", 3593 sc->sc_dev.dv_xname); 3594 break; 3595 } 3596 if (m0->m_pkthdr.len > MHLEN) { 3597 MCLGET(m, M_DONTWAIT); 3598 if ((m->m_flags & M_EXT) == 0) { 3599 printf("%s: unable to allocate Tx " 3600 "cluster\n", sc->sc_dev.dv_xname); 3601 m_freem(m); 3602 break; 3603 } 3604 } 3605 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3606 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3607 m_freem(m0); 3608 m0 = m; 3609 m = NULL; 3610 } 3611 if (error != 0) { 3612 printf("%s: unable to load Tx buffer, " 3613 "error = %d\n", sc->sc_dev.dv_xname, error); 3614 m_freem(m0); 3615 break; 3616 } 3617 3618 /* 3619 * Ensure we have enough descriptors free to describe 3620 * the packet. 3621 */ 3622 if (dmamap->dm_nsegs > sc->sc_txfree) { 3623 /* 3624 * Not enough free descriptors to transmit 3625 * this packet. Unload the DMA map and 3626 * drop the packet. Notify the upper layer 3627 * that there are no more slots left. 3628 * 3629 * XXX We could allocate an mbuf and copy, but 3630 * XXX it is worth it? 3631 */ 3632 ifp->if_flags |= IFF_OACTIVE; 3633 bus_dmamap_unload(sc->sc_dmat, dmamap); 3634 m_freem(m0); 3635 break; 3636 } 3637 3638 /* 3639 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3640 */ 3641 3642 /* Sync the DMA map. */ 3643 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3644 BUS_DMASYNC_PREWRITE); 3645 3646 /* XXX arbitrary retry limit; 8 because I have seen it in 3647 * use already and maybe 0 means "no tries" ! 3648 */ 3649 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3650 3651 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3652 sc->sc_dev.dv_xname, rate * 5)); 3653 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3654 3655 /* 3656 * Initialize the transmit descriptors. 3657 */ 3658 for (nexttx = sc->sc_txnext, seg = 0; 3659 seg < dmamap->dm_nsegs; 3660 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3661 /* 3662 * If this is the first descriptor we're 3663 * enqueueing, don't set the OWN bit just 3664 * yet. That could cause a race condition. 3665 * We'll do it below. 3666 */ 3667 txd = &sc->sc_txdescs[nexttx]; 3668 txd->at_ctl = ctl | 3669 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3670 3671 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3672 txd->at_flags = 3673 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3674 ATW_TXFLAG_TBS1_MASK)) | 3675 ((nexttx == (ATW_NTXDESC - 1)) 3676 ? htole32(ATW_TXFLAG_TER) : 0); 3677 lasttx = nexttx; 3678 } 3679 3680 KASSERT(lasttx != -1, ("bad lastx")); 3681 /* Set `first segment' and `last segment' appropriately. */ 3682 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3683 htole32(ATW_TXFLAG_FS); 3684 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3685 3686 #ifdef ATW_DEBUG 3687 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3688 printf(" txsoft %p transmit chain:\n", txs); 3689 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3690 printf(" descriptor %d:\n", seg); 3691 printf(" at_ctl: 0x%08x\n", 3692 le32toh(sc->sc_txdescs[seg].at_ctl)); 3693 printf(" at_flags: 0x%08x\n", 3694 le32toh(sc->sc_txdescs[seg].at_flags)); 3695 printf(" at_buf1: 0x%08x\n", 3696 le32toh(sc->sc_txdescs[seg].at_buf1)); 3697 printf(" at_buf2: 0x%08x\n", 3698 le32toh(sc->sc_txdescs[seg].at_buf2)); 3699 if (seg == lasttx) 3700 break; 3701 } 3702 } 3703 #endif 3704 3705 /* Sync the descriptors we're using. */ 3706 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3707 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3708 3709 /* 3710 * Store a pointer to the packet so we can free it later, 3711 * and remember what txdirty will be once the packet is 3712 * done. 3713 */ 3714 txs->txs_mbuf = m0; 3715 txs->txs_firstdesc = sc->sc_txnext; 3716 txs->txs_lastdesc = lasttx; 3717 txs->txs_ndescs = dmamap->dm_nsegs; 3718 3719 /* Advance the tx pointer. */ 3720 sc->sc_txfree -= dmamap->dm_nsegs; 3721 sc->sc_txnext = nexttx; 3722 3723 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3724 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3725 3726 last_txs = txs; 3727 } 3728 3729 if (txs == NULL || sc->sc_txfree == 0) { 3730 /* No more slots left; notify upper layer. */ 3731 ifp->if_flags |= IFF_OACTIVE; 3732 } 3733 3734 if (sc->sc_txfree != ofree) { 3735 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3736 sc->sc_dev.dv_xname, lasttx, firsttx)); 3737 /* 3738 * Cause a transmit interrupt to happen on the 3739 * last packet we enqueued. 3740 */ 3741 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3742 ATW_CDTXSYNC(sc, lasttx, 1, 3743 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3744 3745 /* 3746 * The entire packet chain is set up. Give the 3747 * first descriptor to the chip now. 3748 */ 3749 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3750 ATW_CDTXSYNC(sc, firsttx, 1, 3751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3752 3753 /* Wake up the transmitter. */ 3754 /* XXX USE AUTOPOLLING? */ 3755 ATW_WRITE(sc, ATW_TDR, 0x1); 3756 3757 /* Set a watchdog timer in case the chip flakes out. */ 3758 sc->sc_tx_timer = 5; 3759 ifp->if_timer = 1; 3760 } 3761 } 3762 3763 /* 3764 * atw_power: 3765 * 3766 * Power management (suspend/resume) hook. 3767 */ 3768 void 3769 atw_power(why, arg) 3770 int why; 3771 void *arg; 3772 { 3773 struct atw_softc *sc = arg; 3774 struct ifnet *ifp = &sc->sc_ic.ic_if; 3775 int s; 3776 3777 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3778 3779 s = splnet(); 3780 switch (why) { 3781 case PWR_STANDBY: 3782 /* XXX do nothing. */ 3783 break; 3784 case PWR_SUSPEND: 3785 atw_stop(ifp, 0); 3786 if (sc->sc_power != NULL) 3787 (*sc->sc_power)(sc, why); 3788 break; 3789 case PWR_RESUME: 3790 if (ifp->if_flags & IFF_UP) { 3791 if (sc->sc_power != NULL) 3792 (*sc->sc_power)(sc, why); 3793 atw_init(ifp); 3794 } 3795 break; 3796 case PWR_SOFTSUSPEND: 3797 case PWR_SOFTSTANDBY: 3798 case PWR_SOFTRESUME: 3799 break; 3800 } 3801 splx(s); 3802 } 3803 3804 /* 3805 * atw_ioctl: [ifnet interface function] 3806 * 3807 * Handle control requests from the operator. 3808 */ 3809 int 3810 atw_ioctl(ifp, cmd, data) 3811 struct ifnet *ifp; 3812 u_long cmd; 3813 caddr_t data; 3814 { 3815 struct atw_softc *sc = ifp->if_softc; 3816 struct ifreq *ifr = (struct ifreq *)data; 3817 int s, error = 0; 3818 3819 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3820 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3821 return ENXIO; 3822 3823 s = splnet(); 3824 3825 switch (cmd) { 3826 case SIOCSIFFLAGS: 3827 if (ifp->if_flags & IFF_UP) { 3828 if (ATW_IS_ENABLED(sc)) { 3829 /* 3830 * To avoid rescanning another access point, 3831 * do not call atw_init() here. Instead, 3832 * only reflect media settings. 3833 */ 3834 atw_filter_setup(sc); 3835 } else 3836 error = atw_init(ifp); 3837 } else if (ATW_IS_ENABLED(sc)) 3838 atw_stop(ifp, 1); 3839 break; 3840 case SIOCADDMULTI: 3841 case SIOCDELMULTI: 3842 error = (cmd == SIOCADDMULTI) ? 3843 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3844 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3845 if (error == ENETRESET) { 3846 if (ATW_IS_ENABLED(sc)) 3847 atw_filter_setup(sc); /* do not rescan */ 3848 error = 0; 3849 } 3850 break; 3851 default: 3852 error = ieee80211_ioctl(ifp, cmd, data); 3853 if (error == ENETRESET) { 3854 if (ATW_IS_ENABLED(sc)) 3855 error = atw_init(ifp); 3856 else 3857 error = 0; 3858 } 3859 break; 3860 } 3861 3862 /* Try to get more packets going. */ 3863 if (ATW_IS_ENABLED(sc)) 3864 atw_start(ifp); 3865 3866 splx(s); 3867 return (error); 3868 } 3869 3870 static int 3871 atw_media_change(struct ifnet *ifp) 3872 { 3873 int error; 3874 3875 error = ieee80211_media_change(ifp); 3876 if (error == ENETRESET) { 3877 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3878 (IFF_RUNNING|IFF_UP)) 3879 atw_init(ifp); /* XXX lose error */ 3880 error = 0; 3881 } 3882 return error; 3883 } 3884 3885 static void 3886 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3887 { 3888 struct atw_softc *sc = ifp->if_softc; 3889 3890 if (ATW_IS_ENABLED(sc) == 0) { 3891 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3892 imr->ifm_status = 0; 3893 return; 3894 } 3895 ieee80211_media_status(ifp, imr); 3896 } 3897
Indexes created Fri Sep 26 08:10:20 GMT 2025