atw.c revision 1.162
1 /* $NetBSD: atw.c,v 1.162 2017/10/23 09:25:31 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.162 2017/10/23 09:25:31 msaitoh Exp $"); 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/kauth.h> 51 #include <sys/time.h> 52 #include <sys/proc.h> 53 #include <sys/atomic.h> 54 #include <lib/libkern/libkern.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <net/bpf.h> 68 69 #include <sys/bus.h> 70 #include <sys/intr.h> 71 72 #include <dev/ic/atwreg.h> 73 #include <dev/ic/rf3000reg.h> 74 #include <dev/ic/si4136reg.h> 75 #include <dev/ic/atwvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* XXX TBD open questions 79 * 80 * 81 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 82 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 83 * handle this for me? 84 * 85 */ 86 /* device attachment 87 * 88 * print TOFS[012] 89 * 90 * device initialization 91 * 92 * clear ATW_FRCTL_MAXPSP to disable max power saving 93 * set ATW_TXBR_ALCUPDATE to enable ALC 94 * set TOFS[012]? (hope not) 95 * disable rx/tx 96 * set ATW_PAR_SWR (software reset) 97 * wait for ATW_PAR_SWR clear 98 * disable interrupts 99 * ack status register 100 * enable interrupts 101 * 102 * rx/tx initialization 103 * 104 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 105 * allocate and init descriptor rings 106 * write ATW_PAR_DSL (descriptor skip length) 107 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 108 * write ATW_NAR_SQ for one/both transmit descriptor rings 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * 112 * rx/tx end 113 * 114 * stop DMA 115 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * flush tx w/ ATW_NAR_HF 117 * 118 * scan 119 * 120 * initialize rx/tx 121 * 122 * BSS join: (re)association response 123 * 124 * set ATW_FRCTL_AID 125 * 126 * optimizations ??? 127 * 128 */ 129 130 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 131 132 int atw_pseudo_milli = 1; 133 int atw_magic_delay1 = 100 * 1000; 134 int atw_magic_delay2 = 100 * 1000; 135 /* more magic multi-millisecond delays (units: microseconds) */ 136 int atw_nar_delay = 20 * 1000; 137 int atw_magic_delay4 = 10 * 1000; 138 int atw_rf_delay1 = 10 * 1000; 139 int atw_rf_delay2 = 5 * 1000; 140 int atw_plcphd_delay = 2 * 1000; 141 int atw_bbp_io_enable_delay = 20 * 1000; 142 int atw_bbp_io_disable_delay = 2 * 1000; 143 int atw_writewep_delay = 1000; 144 int atw_beacon_len_adjust = 4; 145 int atw_dwelltime = 200; 146 int atw_xindiv2 = 0; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 159 static void atw_print_regs(struct atw_softc *, const char *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static void atw_rf3000_print(struct atw_softc *); 164 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static void atw_si4126_print(struct atw_softc *); 169 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 170 # endif /* ATW_SYNDEBUG */ 171 #define __atwdebugused /* empty */ 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #define __atwdebugused __unused 180 #endif 181 182 /* ifnet methods */ 183 int atw_init(struct ifnet *); 184 int atw_ioctl(struct ifnet *, u_long, void *); 185 void atw_start(struct ifnet *); 186 void atw_stop(struct ifnet *, int); 187 void atw_watchdog(struct ifnet *); 188 189 /* Device attachment */ 190 void atw_attach(struct atw_softc *); 191 int atw_detach(struct atw_softc *); 192 static void atw_evcnt_attach(struct atw_softc *); 193 static void atw_evcnt_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 int atw_add_rxbuf(struct atw_softc *, int); 197 void atw_idle(struct atw_softc *, u_int32_t); 198 void atw_rxdrain(struct atw_softc *); 199 void atw_txdrain(struct atw_softc *); 200 201 /* Device (de)activation and power state */ 202 void atw_reset(struct atw_softc *); 203 204 /* Interrupt handlers */ 205 void atw_softintr(void *); 206 void atw_linkintr(struct atw_softc *, u_int32_t); 207 void atw_rxintr(struct atw_softc *); 208 void atw_txintr(struct atw_softc *, uint32_t); 209 210 /* 802.11 state machine */ 211 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 212 static void atw_next_scan(void *); 213 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 214 struct ieee80211_node *, int, int, u_int32_t); 215 static int atw_tune(struct atw_softc *); 216 217 /* Device initialization */ 218 static void atw_bbp_io_init(struct atw_softc *); 219 static void atw_cfp_init(struct atw_softc *); 220 static void atw_cmdr_init(struct atw_softc *); 221 static void atw_ifs_init(struct atw_softc *); 222 static void atw_nar_init(struct atw_softc *); 223 static void atw_response_times_init(struct atw_softc *); 224 static void atw_rf_reset(struct atw_softc *); 225 static void atw_test1_init(struct atw_softc *); 226 static void atw_tofs0_init(struct atw_softc *); 227 static void atw_tofs2_init(struct atw_softc *); 228 static void atw_txlmt_init(struct atw_softc *); 229 static void atw_wcsr_init(struct atw_softc *); 230 231 /* Key management */ 232 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 233 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 234 const u_int8_t[IEEE80211_ADDR_LEN]); 235 static void atw_key_update_begin(struct ieee80211com *); 236 static void atw_key_update_end(struct ieee80211com *); 237 238 /* RAM/ROM utilities */ 239 static void atw_clear_sram(struct atw_softc *); 240 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 241 static int atw_read_srom(struct atw_softc *); 242 243 /* BSS setup */ 244 static void atw_predict_beacon(struct atw_softc *); 245 static void atw_start_beacon(struct atw_softc *, int); 246 static void atw_write_bssid(struct atw_softc *); 247 static void atw_write_ssid(struct atw_softc *); 248 static void atw_write_sup_rates(struct atw_softc *); 249 static void atw_write_wep(struct atw_softc *); 250 251 /* Media */ 252 static int atw_media_change(struct ifnet *); 253 254 static void atw_filter_setup(struct atw_softc *); 255 256 /* 802.11 utilities */ 257 static uint64_t atw_get_tsft(struct atw_softc *); 258 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 259 uint32_t); 260 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 261 static void atw_node_free(struct ieee80211_node *); 262 263 /* 264 * Tuner/transceiver/modem 265 */ 266 static void atw_bbp_io_enable(struct atw_softc *, int); 267 268 /* RFMD RF3000 Baseband Processor */ 269 static int atw_rf3000_init(struct atw_softc *); 270 static int atw_rf3000_tune(struct atw_softc *, u_int); 271 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 272 273 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 274 static void atw_si4126_tune(struct atw_softc *, u_int); 275 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 276 277 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 278 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 279 280 const char *atw_tx_state[] = { 281 "STOPPED", 282 "RUNNING - read descriptor", 283 "RUNNING - transmitting", 284 "RUNNING - filling fifo", /* XXX */ 285 "SUSPENDED", 286 "RUNNING -- write descriptor", 287 "RUNNING -- write last descriptor", 288 "RUNNING - fifo full" 289 }; 290 291 const char *atw_rx_state[] = { 292 "STOPPED", 293 "RUNNING - read descriptor", 294 "RUNNING - check this packet, pre-fetch next", 295 "RUNNING - wait for reception", 296 "SUSPENDED", 297 "RUNNING - write descriptor", 298 "RUNNING - flush fifo", 299 "RUNNING - fifo drain" 300 }; 301 302 static inline int 303 is_running(struct ifnet *ifp) 304 { 305 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 306 } 307 308 int 309 atw_activate(device_t self, enum devact act) 310 { 311 struct atw_softc *sc = device_private(self); 312 313 switch (act) { 314 case DVACT_DEACTIVATE: 315 if_deactivate(&sc->sc_if); 316 return 0; 317 default: 318 return EOPNOTSUPP; 319 } 320 } 321 322 bool 323 atw_suspend(device_t self, const pmf_qual_t *qual) 324 { 325 struct atw_softc *sc = device_private(self); 326 327 atw_rxdrain(sc); 328 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 329 330 return true; 331 } 332 333 /* Returns -1 on failure. */ 334 static int 335 atw_read_srom(struct atw_softc *sc) 336 { 337 struct seeprom_descriptor sd; 338 uint32_t test0, fail_bits; 339 340 (void)memset(&sd, 0, sizeof(sd)); 341 342 test0 = ATW_READ(sc, ATW_TEST0); 343 344 switch (sc->sc_rev) { 345 case ATW_REVISION_BA: 346 case ATW_REVISION_CA: 347 fail_bits = ATW_TEST0_EPNE; 348 break; 349 default: 350 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 351 break; 352 } 353 if ((test0 & fail_bits) != 0) { 354 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 355 return -1; 356 } 357 358 switch (test0 & ATW_TEST0_EPTYP_MASK) { 359 case ATW_TEST0_EPTYP_93c66: 360 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 361 sc->sc_sromsz = 512; 362 sd.sd_chip = C56_66; 363 break; 364 case ATW_TEST0_EPTYP_93c46: 365 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 366 sc->sc_sromsz = 128; 367 sd.sd_chip = C46; 368 break; 369 default: 370 printf("%s: unknown SROM type %" __PRIuBITS "\n", 371 device_xname(sc->sc_dev), 372 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 373 return -1; 374 } 375 376 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 377 378 if (sc->sc_srom == NULL) { 379 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 380 return -1; 381 } 382 383 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 384 385 /* ADM8211 has a single 32-bit register for controlling the 386 * 93cx6 SROM. Bit SRS enables the serial port. There is no 387 * "ready" bit. The ADM8211 input/output sense is the reverse 388 * of read_seeprom's. 389 */ 390 sd.sd_tag = sc->sc_st; 391 sd.sd_bsh = sc->sc_sh; 392 sd.sd_regsize = 4; 393 sd.sd_control_offset = ATW_SPR; 394 sd.sd_status_offset = ATW_SPR; 395 sd.sd_dataout_offset = ATW_SPR; 396 sd.sd_CK = ATW_SPR_SCLK; 397 sd.sd_CS = ATW_SPR_SCS; 398 sd.sd_DI = ATW_SPR_SDO; 399 sd.sd_DO = ATW_SPR_SDI; 400 sd.sd_MS = ATW_SPR_SRS; 401 sd.sd_RDY = 0; 402 403 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 404 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 405 free(sc->sc_srom, M_DEVBUF); 406 return -1; 407 } 408 #ifdef ATW_DEBUG 409 { 410 int i; 411 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 412 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 413 if (((i % 8) == 0) && (i != 0)) { 414 ATW_DPRINTF(("\n\t")); 415 } 416 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 417 } 418 ATW_DPRINTF(("\n")); 419 } 420 #endif /* ATW_DEBUG */ 421 return 0; 422 } 423 424 #ifdef ATW_DEBUG 425 static void 426 atw_print_regs(struct atw_softc *sc, const char *where) 427 { 428 #define PRINTREG(sc, reg) \ 429 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 430 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 431 432 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 433 434 PRINTREG(sc, ATW_PAR); 435 PRINTREG(sc, ATW_FRCTL); 436 PRINTREG(sc, ATW_TDR); 437 PRINTREG(sc, ATW_WTDP); 438 PRINTREG(sc, ATW_RDR); 439 PRINTREG(sc, ATW_WRDP); 440 PRINTREG(sc, ATW_RDB); 441 PRINTREG(sc, ATW_CSR3A); 442 PRINTREG(sc, ATW_TDBD); 443 PRINTREG(sc, ATW_TDBP); 444 PRINTREG(sc, ATW_STSR); 445 PRINTREG(sc, ATW_CSR5A); 446 PRINTREG(sc, ATW_NAR); 447 PRINTREG(sc, ATW_CSR6A); 448 PRINTREG(sc, ATW_IER); 449 PRINTREG(sc, ATW_CSR7A); 450 PRINTREG(sc, ATW_LPC); 451 PRINTREG(sc, ATW_TEST1); 452 PRINTREG(sc, ATW_SPR); 453 PRINTREG(sc, ATW_TEST0); 454 PRINTREG(sc, ATW_WCSR); 455 PRINTREG(sc, ATW_WPDR); 456 PRINTREG(sc, ATW_GPTMR); 457 PRINTREG(sc, ATW_GPIO); 458 PRINTREG(sc, ATW_BBPCTL); 459 PRINTREG(sc, ATW_SYNCTL); 460 PRINTREG(sc, ATW_PLCPHD); 461 PRINTREG(sc, ATW_MMIWADDR); 462 PRINTREG(sc, ATW_MMIRADDR1); 463 PRINTREG(sc, ATW_MMIRADDR2); 464 PRINTREG(sc, ATW_TXBR); 465 PRINTREG(sc, ATW_CSR15A); 466 PRINTREG(sc, ATW_ALCSTAT); 467 PRINTREG(sc, ATW_TOFS2); 468 PRINTREG(sc, ATW_CMDR); 469 PRINTREG(sc, ATW_PCIC); 470 PRINTREG(sc, ATW_PMCSR); 471 PRINTREG(sc, ATW_PAR0); 472 PRINTREG(sc, ATW_PAR1); 473 PRINTREG(sc, ATW_MAR0); 474 PRINTREG(sc, ATW_MAR1); 475 PRINTREG(sc, ATW_ATIMDA0); 476 PRINTREG(sc, ATW_ABDA1); 477 PRINTREG(sc, ATW_BSSID0); 478 PRINTREG(sc, ATW_TXLMT); 479 PRINTREG(sc, ATW_MIBCNT); 480 PRINTREG(sc, ATW_BCNT); 481 PRINTREG(sc, ATW_TSFTH); 482 PRINTREG(sc, ATW_TSC); 483 PRINTREG(sc, ATW_SYNRF); 484 PRINTREG(sc, ATW_BPLI); 485 PRINTREG(sc, ATW_CAP0); 486 PRINTREG(sc, ATW_CAP1); 487 PRINTREG(sc, ATW_RMD); 488 PRINTREG(sc, ATW_CFPP); 489 PRINTREG(sc, ATW_TOFS0); 490 PRINTREG(sc, ATW_TOFS1); 491 PRINTREG(sc, ATW_IFST); 492 PRINTREG(sc, ATW_RSPT); 493 PRINTREG(sc, ATW_TSFTL); 494 PRINTREG(sc, ATW_WEPCTL); 495 PRINTREG(sc, ATW_WESK); 496 PRINTREG(sc, ATW_WEPCNT); 497 PRINTREG(sc, ATW_MACTEST); 498 PRINTREG(sc, ATW_FER); 499 PRINTREG(sc, ATW_FEMR); 500 PRINTREG(sc, ATW_FPSR); 501 PRINTREG(sc, ATW_FFER); 502 #undef PRINTREG 503 } 504 #endif /* ATW_DEBUG */ 505 506 /* 507 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 508 */ 509 void 510 atw_attach(struct atw_softc *sc) 511 { 512 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 513 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 514 }; 515 struct ieee80211com *ic = &sc->sc_ic; 516 struct ifnet *ifp = &sc->sc_if; 517 int country_code, error, i, nrate, srom_major; 518 u_int32_t reg; 519 static const char *type_strings[] = {"Intersil (not supported)", 520 "RFMD", "Marvel (not supported)"}; 521 522 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 523 524 sc->sc_soft_ih = softint_establish(SOFTINT_NET, atw_softintr, sc); 525 if (sc->sc_soft_ih == NULL) { 526 aprint_error_dev(sc->sc_dev, "unable to establish softint\n"); 527 goto fail_0; 528 } 529 530 sc->sc_txth = atw_txthresh_tab_lo; 531 532 SIMPLEQ_INIT(&sc->sc_txfreeq); 533 SIMPLEQ_INIT(&sc->sc_txdirtyq); 534 535 #ifdef ATW_DEBUG 536 atw_print_regs(sc, "atw_attach"); 537 #endif /* ATW_DEBUG */ 538 539 /* 540 * Allocate the control data structures, and create and load the 541 * DMA map for it. 542 */ 543 if ((error = bus_dmamem_alloc(sc->sc_dmat, 544 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 545 1, &sc->sc_cdnseg, 0)) != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "unable to allocate control data, error = %d\n", 548 error); 549 goto fail_0; 550 } 551 552 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 553 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 554 BUS_DMA_COHERENT)) != 0) { 555 aprint_error_dev(sc->sc_dev, 556 "unable to map control data, error = %d\n", 557 error); 558 goto fail_1; 559 } 560 561 if ((error = bus_dmamap_create(sc->sc_dmat, 562 sizeof(struct atw_control_data), 1, 563 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 564 aprint_error_dev(sc->sc_dev, 565 "unable to create control data DMA map, error = %d\n", 566 error); 567 goto fail_2; 568 } 569 570 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 571 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 572 0)) != 0) { 573 aprint_error_dev(sc->sc_dev, 574 "unable to load control data DMA map, error = %d\n", error); 575 goto fail_3; 576 } 577 578 /* 579 * Create the transmit buffer DMA maps. 580 */ 581 sc->sc_ntxsegs = ATW_NTXSEGS; 582 for (i = 0; i < ATW_TXQUEUELEN; i++) { 583 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 584 sc->sc_ntxsegs, MCLBYTES, 0, 0, 585 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 586 aprint_error_dev(sc->sc_dev, 587 "unable to create tx DMA map %d, error = %d\n", i, 588 error); 589 goto fail_4; 590 } 591 } 592 593 /* 594 * Create the receive buffer DMA maps. 595 */ 596 for (i = 0; i < ATW_NRXDESC; i++) { 597 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 598 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "unable to create rx DMA map %d, error = %d\n", i, 601 error); 602 goto fail_5; 603 } 604 } 605 for (i = 0; i < ATW_NRXDESC; i++) { 606 sc->sc_rxsoft[i].rxs_mbuf = NULL; 607 } 608 609 switch (sc->sc_rev) { 610 case ATW_REVISION_AB: 611 case ATW_REVISION_AF: 612 sc->sc_sramlen = ATW_SRAM_A_SIZE; 613 break; 614 case ATW_REVISION_BA: 615 case ATW_REVISION_CA: 616 sc->sc_sramlen = ATW_SRAM_B_SIZE; 617 break; 618 } 619 620 /* Reset the chip to a known state. */ 621 atw_reset(sc); 622 623 if (atw_read_srom(sc) == -1) 624 goto fail_5; 625 626 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 627 ATW_SR_RFTYPE_MASK); 628 629 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 630 ATW_SR_BBPTYPE_MASK); 631 632 if (sc->sc_rftype >= __arraycount(type_strings)) { 633 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 634 goto fail_5; 635 } 636 if (sc->sc_bbptype >= __arraycount(type_strings)) { 637 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 638 goto fail_5; 639 } 640 641 aprint_normal_dev(sc->sc_dev, "%s RF, %s BBP", 642 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 643 644 /* XXX There exists a Linux driver which seems to use RFType = 0 for 645 * MARVEL. My bug, or theirs? 646 */ 647 648 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 649 650 switch (sc->sc_rftype) { 651 case ATW_RFTYPE_INTERSIL: 652 reg |= ATW_SYNCTL_CS1; 653 break; 654 case ATW_RFTYPE_RFMD: 655 reg |= ATW_SYNCTL_CS0; 656 break; 657 case ATW_RFTYPE_MARVEL: 658 break; 659 } 660 661 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 662 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 663 664 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 665 666 switch (sc->sc_bbptype) { 667 case ATW_BBPTYPE_INTERSIL: 668 reg |= ATW_BBPCTL_TWI; 669 break; 670 case ATW_BBPTYPE_RFMD: 671 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 672 ATW_BBPCTL_CCA_ACTLO; 673 break; 674 case ATW_BBPTYPE_MARVEL: 675 break; 676 case ATW_C_BBPTYPE_RFMD: 677 aprint_error_dev(sc->sc_dev, 678 "ADM8211C MAC/RFMD BBP not supported yet.\n"); 679 break; 680 } 681 682 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 683 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 684 685 /* 686 * From this point forward, the attachment cannot fail. A failure 687 * before this point releases all resources that may have been 688 * allocated. 689 */ 690 sc->sc_flags |= ATWF_ATTACHED; 691 692 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 693 htole16(sc->sc_srom[ATW_SR_MAC00]), 694 htole16(sc->sc_srom[ATW_SR_MAC01]), 695 htole16(sc->sc_srom[ATW_SR_MAC10]))); 696 697 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 698 ATW_SR_MAJOR_MASK); 699 700 if (srom_major < 2) 701 sc->sc_rf3000_options1 = 0; 702 else if (sc->sc_rev == ATW_REVISION_BA) { 703 sc->sc_rf3000_options1 = 704 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 705 ATW_SR_CR28_MASK); 706 } else 707 sc->sc_rf3000_options1 = 0; 708 709 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 710 ATW_SR_CR29_MASK); 711 712 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 713 ATW_SR_CTRY_MASK); 714 715 #define ADD_CHANNEL(_ic, _chan) do { \ 716 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 717 _ic->ic_channels[_chan].ic_freq = \ 718 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 719 } while (0) 720 721 /* Find available channels */ 722 switch (country_code) { 723 case COUNTRY_MMK2: /* 1-14 */ 724 ADD_CHANNEL(ic, 14); 725 /*FALLTHROUGH*/ 726 case COUNTRY_ETSI: /* 1-13 */ 727 for (i = 1; i <= 13; i++) 728 ADD_CHANNEL(ic, i); 729 break; 730 case COUNTRY_FCC: /* 1-11 */ 731 case COUNTRY_IC: /* 1-11 */ 732 for (i = 1; i <= 11; i++) 733 ADD_CHANNEL(ic, i); 734 break; 735 case COUNTRY_MMK: /* 14 */ 736 ADD_CHANNEL(ic, 14); 737 break; 738 case COUNTRY_FRANCE: /* 10-13 */ 739 for (i = 10; i <= 13; i++) 740 ADD_CHANNEL(ic, i); 741 break; 742 default: /* assume channels 10-11 */ 743 case COUNTRY_SPAIN: /* 10-11 */ 744 for (i = 10; i <= 11; i++) 745 ADD_CHANNEL(ic, i); 746 break; 747 } 748 749 /* Read the MAC address. */ 750 reg = ATW_READ(sc, ATW_PAR0); 751 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 752 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 753 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 754 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 755 reg = ATW_READ(sc, ATW_PAR1); 756 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 757 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 758 759 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 760 aprint_error_dev(sc->sc_dev, 761 "could not get mac address, attach failed\n"); 762 goto fail_5; 763 } 764 765 aprint_normal(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 766 767 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 768 ifp->if_softc = sc; 769 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 770 IFF_NOTRAILERS; 771 ifp->if_ioctl = atw_ioctl; 772 ifp->if_start = atw_start; 773 ifp->if_watchdog = atw_watchdog; 774 ifp->if_init = atw_init; 775 ifp->if_stop = atw_stop; 776 IFQ_SET_READY(&ifp->if_snd); 777 778 ic->ic_ifp = ifp; 779 ic->ic_phytype = IEEE80211_T_DS; 780 ic->ic_opmode = IEEE80211_M_STA; 781 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 782 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 783 784 nrate = 0; 785 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 786 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 787 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 788 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 789 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 790 791 /* 792 * Call MI attach routines. 793 */ 794 795 error = if_initialize(ifp); 796 if (error != 0) { 797 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 798 error); 799 goto fail_5; 800 } 801 ieee80211_ifattach(ic); 802 /* Use common softint-based if_input */ 803 ifp->if_percpuq = if_percpuq_create(ifp); 804 if_register(ifp); 805 806 atw_evcnt_attach(sc); 807 808 sc->sc_newstate = ic->ic_newstate; 809 ic->ic_newstate = atw_newstate; 810 811 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 812 ic->ic_recv_mgmt = atw_recv_mgmt; 813 814 sc->sc_node_free = ic->ic_node_free; 815 ic->ic_node_free = atw_node_free; 816 817 sc->sc_node_alloc = ic->ic_node_alloc; 818 ic->ic_node_alloc = atw_node_alloc; 819 820 ic->ic_crypto.cs_key_delete = atw_key_delete; 821 ic->ic_crypto.cs_key_set = atw_key_set; 822 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 823 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 824 825 /* possibly we should fill in our own sc_send_prresp, since 826 * the ADM8211 is probably sending probe responses in ad hoc 827 * mode. 828 */ 829 830 /* complete initialization */ 831 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 832 callout_init(&sc->sc_scan_ch, 0); 833 834 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 835 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 836 837 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 838 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 839 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 840 841 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 842 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 843 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 844 845 ieee80211_announce(ic); 846 return; 847 848 /* 849 * Free any resources we've allocated during the failed attach 850 * attempt. Do this in reverse order and fall through. 851 */ 852 fail_5: 853 for (i = 0; i < ATW_NRXDESC; i++) { 854 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 855 continue; 856 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 857 } 858 fail_4: 859 for (i = 0; i < ATW_TXQUEUELEN; i++) { 860 if (sc->sc_txsoft[i].txs_dmamap == NULL) 861 continue; 862 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 863 } 864 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 865 fail_3: 866 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 867 fail_2: 868 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 869 sizeof(struct atw_control_data)); 870 fail_1: 871 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 872 fail_0: 873 if (sc->sc_soft_ih != NULL) { 874 softint_disestablish(sc->sc_soft_ih); 875 sc->sc_soft_ih = NULL; 876 } 877 } 878 879 static struct ieee80211_node * 880 atw_node_alloc(struct ieee80211_node_table *nt) 881 { 882 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 883 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 884 885 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 886 return ni; 887 } 888 889 static void 890 atw_node_free(struct ieee80211_node *ni) 891 { 892 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 893 894 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 895 ether_sprintf(ni->ni_bssid))); 896 (*sc->sc_node_free)(ni); 897 } 898 899 900 static void 901 atw_test1_reset(struct atw_softc *sc) 902 { 903 switch (sc->sc_rev) { 904 case ATW_REVISION_BA: 905 if (1 /* XXX condition on transceiver type */) { 906 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 907 } 908 break; 909 case ATW_REVISION_CA: 910 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 911 break; 912 default: 913 break; 914 } 915 } 916 917 /* 918 * atw_reset: 919 * 920 * Perform a soft reset on the ADM8211. 921 */ 922 void 923 atw_reset(struct atw_softc *sc) 924 { 925 int i; 926 uint32_t lpc __atwdebugused; 927 928 ATW_WRITE(sc, ATW_NAR, 0x0); 929 DELAY(atw_nar_delay); 930 931 /* Reference driver has a cryptic remark indicating that this might 932 * power-on the chip. I know that it turns off power-saving.... 933 */ 934 ATW_WRITE(sc, ATW_FRCTL, 0x0); 935 936 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 937 938 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 939 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 940 break; 941 DELAY(atw_pseudo_milli); 942 } 943 944 /* ... and then pause 100ms longer for good measure. */ 945 DELAY(atw_magic_delay1); 946 947 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 948 949 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 950 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 951 952 /* 953 * Initialize the PCI Access Register. 954 */ 955 sc->sc_busmode = ATW_PAR_PBL_8DW; 956 957 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 958 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 959 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 960 961 atw_test1_reset(sc); 962 963 /* Turn off maximum power saving, etc. */ 964 ATW_WRITE(sc, ATW_FRCTL, 0x0); 965 966 DELAY(atw_magic_delay2); 967 968 /* Recall EEPROM. */ 969 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 970 971 DELAY(atw_magic_delay4); 972 973 lpc = ATW_READ(sc, ATW_LPC); 974 975 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 976 977 /* A reset seems to affect the SRAM contents, so put them into 978 * a known state. 979 */ 980 atw_clear_sram(sc); 981 982 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 983 } 984 985 static void 986 atw_clear_sram(struct atw_softc *sc) 987 { 988 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 989 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 990 /* XXX not for revision 0x20. */ 991 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 992 } 993 994 /* TBD atw_init 995 * 996 * set MAC based on ic->ic_bss->myaddr 997 * write WEP keys 998 * set TX rate 999 */ 1000 1001 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1002 * without receiving a beacon with the preferred BSSID & SSID. 1003 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1004 */ 1005 static void 1006 atw_wcsr_init(struct atw_softc *sc) 1007 { 1008 uint32_t wcsr; 1009 1010 wcsr = ATW_READ(sc, ATW_WCSR); 1011 wcsr &= ~ATW_WCSR_BLN_MASK; 1012 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1013 /* We always want to wake up on link loss or TSFT out of range */ 1014 wcsr |= ATW_WCSR_LSOE|ATW_WCSR_TSFTWE; 1015 ATW_WRITE(sc, ATW_WCSR, wcsr); 1016 1017 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1018 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1019 } 1020 1021 /* Turn off power management. Set Rx store-and-forward mode. */ 1022 static void 1023 atw_cmdr_init(struct atw_softc *sc) 1024 { 1025 uint32_t cmdr; 1026 cmdr = ATW_READ(sc, ATW_CMDR); 1027 cmdr &= ~ATW_CMDR_APM; 1028 cmdr |= ATW_CMDR_RTE; 1029 cmdr &= ~ATW_CMDR_DRT_MASK; 1030 cmdr |= ATW_CMDR_DRT_SF; 1031 1032 ATW_WRITE(sc, ATW_CMDR, cmdr); 1033 } 1034 1035 static void 1036 atw_tofs2_init(struct atw_softc *sc) 1037 { 1038 uint32_t tofs2; 1039 /* XXX this magic can probably be figured out from the RFMD docs */ 1040 #ifndef ATW_REFSLAVE 1041 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1042 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1043 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1044 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1045 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1046 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1047 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1048 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1049 #else 1050 /* XXX new magic from reference driver source */ 1051 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1052 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1053 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1054 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1055 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1056 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1057 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1058 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1059 #endif 1060 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1061 } 1062 1063 static void 1064 atw_nar_init(struct atw_softc *sc) 1065 { 1066 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1067 } 1068 1069 static void 1070 atw_txlmt_init(struct atw_softc *sc) 1071 { 1072 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1073 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1074 } 1075 1076 static void 1077 atw_test1_init(struct atw_softc *sc) 1078 { 1079 uint32_t test1; 1080 1081 test1 = ATW_READ(sc, ATW_TEST1); 1082 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1083 /* XXX magic 0x1 */ 1084 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1085 ATW_WRITE(sc, ATW_TEST1, test1); 1086 } 1087 1088 static void 1089 atw_rf_reset(struct atw_softc *sc) 1090 { 1091 /* XXX this resets an Intersil RF front-end? */ 1092 /* TBD condition on Intersil RFType? */ 1093 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1094 DELAY(atw_rf_delay1); 1095 ATW_WRITE(sc, ATW_SYNRF, 0); 1096 DELAY(atw_rf_delay2); 1097 } 1098 1099 /* Set 16 TU max duration for the contention-free period (CFP). */ 1100 static void 1101 atw_cfp_init(struct atw_softc *sc) 1102 { 1103 uint32_t cfpp; 1104 1105 cfpp = ATW_READ(sc, ATW_CFPP); 1106 cfpp &= ~ATW_CFPP_CFPMD; 1107 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1108 ATW_WRITE(sc, ATW_CFPP, cfpp); 1109 } 1110 1111 static void 1112 atw_tofs0_init(struct atw_softc *sc) 1113 { 1114 /* XXX I guess that the Cardbus clock is 22 MHz? 1115 * I am assuming that the role of ATW_TOFS0_USCNT is 1116 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1117 * very clear on this point. It says in the datasheet that it is 1118 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1119 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1120 * these values. These values are also the power-on default. 1121 */ 1122 ATW_WRITE(sc, ATW_TOFS0, 1123 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1124 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1125 } 1126 1127 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1128 static void 1129 atw_ifs_init(struct atw_softc *sc) 1130 { 1131 uint32_t ifst; 1132 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1133 * Go figure. 1134 */ 1135 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1136 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1137 ATW_IFST_SIFS_MASK) | 1138 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1139 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1140 1141 ATW_WRITE(sc, ATW_IFST, ifst); 1142 } 1143 1144 static void 1145 atw_response_times_init(struct atw_softc *sc) 1146 { 1147 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1148 * indicate that the MAC expects at least SIFS + MIRT microseconds 1149 * to pass after it transmits a frame that requires a response; 1150 * it waits at most SIFS + MART microseconds for the response. 1151 * Surely this is not the ACK timeout? 1152 */ 1153 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1154 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1155 } 1156 1157 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1158 * engines read and write baseband registers after Rx and before 1159 * Tx, respectively. 1160 */ 1161 static void 1162 atw_bbp_io_init(struct atw_softc *sc) 1163 { 1164 uint32_t mmiraddr2; 1165 1166 /* XXX The reference driver does this, but is it *really* 1167 * necessary? 1168 */ 1169 switch (sc->sc_rev) { 1170 case ATW_REVISION_AB: 1171 case ATW_REVISION_AF: 1172 mmiraddr2 = 0x0; 1173 break; 1174 default: 1175 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1176 mmiraddr2 &= 1177 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1178 break; 1179 } 1180 1181 switch (sc->sc_bbptype) { 1182 case ATW_BBPTYPE_INTERSIL: 1183 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1184 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1185 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1186 break; 1187 case ATW_BBPTYPE_MARVEL: 1188 /* TBD find out the Marvel settings. */ 1189 break; 1190 case ATW_BBPTYPE_RFMD: 1191 default: 1192 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1193 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1194 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1195 break; 1196 } 1197 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1198 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1199 } 1200 1201 /* 1202 * atw_init: [ ifnet interface function ] 1203 * 1204 * Initialize the interface. Must be called at splnet(). 1205 */ 1206 int 1207 atw_init(struct ifnet *ifp) 1208 { 1209 struct atw_softc *sc = ifp->if_softc; 1210 struct ieee80211com *ic = &sc->sc_ic; 1211 struct atw_txsoft *txs; 1212 struct atw_rxsoft *rxs; 1213 int i, error = 0; 1214 1215 if (device_is_active(sc->sc_dev)) { 1216 /* 1217 * Cancel any pending I/O. 1218 */ 1219 atw_stop(ifp, 0); 1220 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1221 !device_is_active(sc->sc_dev)) 1222 return 0; 1223 1224 /* 1225 * Reset the chip to a known state. 1226 */ 1227 atw_reset(sc); 1228 1229 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1230 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1231 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1232 1233 atw_wcsr_init(sc); 1234 1235 atw_cmdr_init(sc); 1236 1237 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1238 * 1239 * XXX Set transmit power for ATIM, RTS, Beacon. 1240 */ 1241 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1242 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1243 1244 atw_tofs2_init(sc); 1245 1246 atw_nar_init(sc); 1247 1248 atw_txlmt_init(sc); 1249 1250 atw_test1_init(sc); 1251 1252 atw_rf_reset(sc); 1253 1254 atw_cfp_init(sc); 1255 1256 atw_tofs0_init(sc); 1257 1258 atw_ifs_init(sc); 1259 1260 /* XXX Fall asleep after one second of inactivity. 1261 * XXX A frame may only dribble in for 65536us. 1262 */ 1263 ATW_WRITE(sc, ATW_RMD, 1264 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1265 1266 atw_response_times_init(sc); 1267 1268 atw_bbp_io_init(sc); 1269 1270 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1271 1272 if ((error = atw_rf3000_init(sc)) != 0) 1273 goto out; 1274 1275 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1276 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1277 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1278 1279 /* 1280 * Initialize the transmit descriptor ring. 1281 */ 1282 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1283 for (i = 0; i < ATW_NTXDESC; i++) { 1284 sc->sc_txdescs[i].at_ctl = 0; 1285 /* no transmit chaining */ 1286 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1287 sc->sc_txdescs[i].at_buf2 = 1288 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1289 } 1290 /* use ring mode */ 1291 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1292 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1293 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1294 sc->sc_txfree = ATW_NTXDESC; 1295 sc->sc_txnext = 0; 1296 1297 /* 1298 * Initialize the transmit job descriptors. 1299 */ 1300 SIMPLEQ_INIT(&sc->sc_txfreeq); 1301 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1302 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1303 txs = &sc->sc_txsoft[i]; 1304 txs->txs_mbuf = NULL; 1305 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1306 } 1307 1308 /* 1309 * Initialize the receive descriptor and receive job 1310 * descriptor rings. 1311 */ 1312 for (i = 0; i < ATW_NRXDESC; i++) { 1313 rxs = &sc->sc_rxsoft[i]; 1314 if (rxs->rxs_mbuf == NULL) { 1315 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1316 aprint_error_dev(sc->sc_dev, 1317 "unable to allocate or map rx buffer %d, " 1318 "error = %d\n", i, error); 1319 /* 1320 * XXX Should attempt to run with fewer receive 1321 * XXX buffers instead of just failing. 1322 */ 1323 atw_rxdrain(sc); 1324 goto out; 1325 } 1326 } else 1327 atw_init_rxdesc(sc, i); 1328 } 1329 sc->sc_rxptr = 0; 1330 1331 /* 1332 * Initialize the interrupt mask and enable interrupts. 1333 */ 1334 /* normal interrupts */ 1335 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1336 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1337 1338 /* abnormal interrupts */ 1339 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1340 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1341 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1342 1343 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1344 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1345 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1346 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1347 ATW_INTR_TRT; 1348 1349 sc->sc_linkint_mask &= sc->sc_inten; 1350 sc->sc_rxint_mask &= sc->sc_inten; 1351 sc->sc_txint_mask &= sc->sc_inten; 1352 1353 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1354 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1355 1356 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1357 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1358 1359 /* 1360 * Give the transmit and receive rings to the ADM8211. 1361 */ 1362 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1363 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1364 1365 sc->sc_txthresh = 0; 1366 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1367 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1368 1369 /* common 802.11 configuration */ 1370 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1371 switch (ic->ic_opmode) { 1372 case IEEE80211_M_STA: 1373 break; 1374 case IEEE80211_M_AHDEMO: /* XXX */ 1375 case IEEE80211_M_IBSS: 1376 ic->ic_flags |= IEEE80211_F_IBSSON; 1377 /*FALLTHROUGH*/ 1378 case IEEE80211_M_HOSTAP: /* XXX */ 1379 break; 1380 case IEEE80211_M_MONITOR: /* XXX */ 1381 break; 1382 } 1383 1384 switch (ic->ic_opmode) { 1385 case IEEE80211_M_AHDEMO: 1386 case IEEE80211_M_HOSTAP: 1387 #ifndef IEEE80211_NO_HOSTAP 1388 ic->ic_bss->ni_intval = ic->ic_lintval; 1389 ic->ic_bss->ni_rssi = 0; 1390 ic->ic_bss->ni_rstamp = 0; 1391 #endif /* !IEEE80211_NO_HOSTAP */ 1392 break; 1393 default: /* XXX */ 1394 break; 1395 } 1396 1397 sc->sc_wepctl = 0; 1398 1399 atw_write_ssid(sc); 1400 atw_write_sup_rates(sc); 1401 atw_write_wep(sc); 1402 1403 ic->ic_state = IEEE80211_S_INIT; 1404 1405 /* 1406 * Set the receive filter. This will start the transmit and 1407 * receive processes. 1408 */ 1409 atw_filter_setup(sc); 1410 1411 /* 1412 * Start the receive process. 1413 */ 1414 ATW_WRITE(sc, ATW_RDR, 0x1); 1415 1416 /* 1417 * Note that the interface is now running. 1418 */ 1419 ifp->if_flags |= IFF_RUNNING; 1420 1421 /* send no beacons, yet. */ 1422 atw_start_beacon(sc, 0); 1423 1424 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1425 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1426 else 1427 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1428 out: 1429 if (error) { 1430 ifp->if_flags &= ~IFF_RUNNING; 1431 sc->sc_tx_timer = 0; 1432 ifp->if_timer = 0; 1433 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1434 } 1435 #ifdef ATW_DEBUG 1436 atw_print_regs(sc, "end of init"); 1437 #endif /* ATW_DEBUG */ 1438 1439 return (error); 1440 } 1441 1442 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1443 * 0: MAC control of RF3000/Si4126. 1444 * 1445 * Applies power, or selects RF front-end? Sets reset condition. 1446 * 1447 * TBD support non-RFMD BBP, non-SiLabs synth. 1448 */ 1449 static void 1450 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1451 { 1452 if (enable) { 1453 ATW_WRITE(sc, ATW_SYNRF, 1454 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1455 DELAY(atw_bbp_io_enable_delay); 1456 } else { 1457 ATW_WRITE(sc, ATW_SYNRF, 0); 1458 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1459 } 1460 } 1461 1462 static int 1463 atw_tune(struct atw_softc *sc) 1464 { 1465 int rc; 1466 u_int chan; 1467 struct ieee80211com *ic = &sc->sc_ic; 1468 1469 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1470 if (chan == IEEE80211_CHAN_ANY) 1471 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1472 1473 if (chan == sc->sc_cur_chan) 1474 return 0; 1475 1476 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1477 sc->sc_cur_chan, chan)); 1478 1479 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1480 1481 atw_si4126_tune(sc, chan); 1482 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1483 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1484 chan); 1485 1486 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1487 DELAY(atw_nar_delay); 1488 ATW_WRITE(sc, ATW_RDR, 0x1); 1489 1490 if (rc == 0) { 1491 sc->sc_cur_chan = chan; 1492 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1493 htole16(ic->ic_curchan->ic_freq); 1494 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1495 htole16(ic->ic_curchan->ic_flags); 1496 } 1497 1498 return rc; 1499 } 1500 1501 #ifdef ATW_SYNDEBUG 1502 static void 1503 atw_si4126_print(struct atw_softc *sc) 1504 { 1505 struct ifnet *ifp = &sc->sc_if; 1506 u_int addr, val; 1507 1508 val = 0; 1509 1510 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1511 return; 1512 1513 for (addr = 0; addr <= 8; addr++) { 1514 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1515 if (atw_si4126_read(sc, addr, &val) == 0) { 1516 printf("<unknown> (quitting print-out)\n"); 1517 break; 1518 } 1519 printf("%05x\n", val); 1520 } 1521 } 1522 #endif /* ATW_SYNDEBUG */ 1523 1524 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1525 * 1526 * The RF/IF synthesizer produces two reference frequencies for 1527 * the RF2948B transceiver. The first frequency the RF2948B requires 1528 * is two times the so-called "intermediate frequency" (IF). Since 1529 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1530 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1531 * frequency required by the transceiver is the radio frequency 1532 * (RF). This is a superheterodyne transceiver; for f(chan) the 1533 * center frequency of the channel we are tuning, RF = f(chan) - 1534 * IF. 1535 * 1536 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1537 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1538 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1539 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1540 */ 1541 static void 1542 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1543 { 1544 u_int mhz; 1545 u_int R; 1546 u_int32_t gpio; 1547 u_int16_t gain; 1548 1549 #ifdef ATW_SYNDEBUG 1550 atw_si4126_print(sc); 1551 #endif /* ATW_SYNDEBUG */ 1552 1553 if (chan == 14) 1554 mhz = 2484; 1555 else 1556 mhz = 2412 + 5 * (chan - 1); 1557 1558 /* Tune IF to 748 MHz to suit the IF LO input of the 1559 * RF2494B, which is 2 x IF. No need to set an IF divider 1560 * because an IF in 526 MHz - 952 MHz is allowed. 1561 * 1562 * XIN is 44.000 MHz, so divide it by two to get allowable 1563 * range of 2-25 MHz. SiLabs tells me that this is not 1564 * strictly necessary. 1565 */ 1566 1567 if (atw_xindiv2) 1568 R = 44; 1569 else 1570 R = 88; 1571 1572 /* Power-up RF, IF synthesizers. */ 1573 atw_si4126_write(sc, SI4126_POWER, 1574 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1575 1576 /* set LPWR, too? */ 1577 atw_si4126_write(sc, SI4126_MAIN, 1578 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1579 1580 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1581 * set KP2 to 1. 1582 * 1583 * REFDIF This is different from the reference driver, which 1584 * always sets SI4126_GAIN to 0. 1585 */ 1586 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1587 1588 atw_si4126_write(sc, SI4126_GAIN, gain); 1589 1590 /* XIN = 44 MHz. 1591 * 1592 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1593 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1594 * 1595 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1596 * so that 1496/88 * 44 MHz = 748 MHz. 1597 */ 1598 atw_si4126_write(sc, SI4126_IFN, 1496); 1599 1600 atw_si4126_write(sc, SI4126_IFR, R); 1601 1602 #ifndef ATW_REFSLAVE 1603 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1604 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1605 * which has no RF1! 1606 */ 1607 atw_si4126_write(sc, SI4126_RF1R, R); 1608 1609 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1610 #endif 1611 1612 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1613 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1614 * Now let's multiply it to mhz. So mhz - IF = N. 1615 */ 1616 atw_si4126_write(sc, SI4126_RF2R, R); 1617 1618 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1619 1620 /* wait 100us from power-up for RF, IF to settle */ 1621 DELAY(100); 1622 1623 gpio = ATW_READ(sc, ATW_GPIO); 1624 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1625 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1626 1627 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1628 /* Set a Prism RF front-end to a special mode for channel 14? 1629 * 1630 * Apparently the SMC2635W needs this, although I don't think 1631 * it has a Prism RF. 1632 */ 1633 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1634 } 1635 ATW_WRITE(sc, ATW_GPIO, gpio); 1636 1637 #ifdef ATW_SYNDEBUG 1638 atw_si4126_print(sc); 1639 #endif /* ATW_SYNDEBUG */ 1640 } 1641 1642 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1643 * diversity. 1644 * 1645 * !!! 1646 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1647 * !!! 1648 */ 1649 static int 1650 atw_rf3000_init(struct atw_softc *sc) 1651 { 1652 int rc = 0; 1653 1654 atw_bbp_io_enable(sc, 1); 1655 1656 /* CCA is acquisition sensitive */ 1657 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1658 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1659 1660 if (rc != 0) 1661 goto out; 1662 1663 /* enable diversity */ 1664 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1665 1666 if (rc != 0) 1667 goto out; 1668 1669 /* sensible setting from a binary-only driver */ 1670 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1671 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1672 1673 if (rc != 0) 1674 goto out; 1675 1676 /* magic from a binary-only driver */ 1677 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1678 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1679 1680 if (rc != 0) 1681 goto out; 1682 1683 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1684 1685 if (rc != 0) 1686 goto out; 1687 1688 /* XXX Reference driver remarks that Abocom sets this to 50. 1689 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1690 * in the "reserved" area of register RF3000_OPTIONS1. 1691 */ 1692 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1698 1699 if (rc != 0) 1700 goto out; 1701 1702 out: 1703 atw_bbp_io_enable(sc, 0); 1704 return rc; 1705 } 1706 1707 #ifdef ATW_BBPDEBUG 1708 static void 1709 atw_rf3000_print(struct atw_softc *sc) 1710 { 1711 struct ifnet *ifp = &sc->sc_if; 1712 u_int addr, val; 1713 1714 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1715 return; 1716 1717 for (addr = 0x01; addr <= 0x15; addr++) { 1718 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1719 if (atw_rf3000_read(sc, addr, &val) != 0) { 1720 printf("<unknown> (quitting print-out)\n"); 1721 break; 1722 } 1723 printf("%08x\n", val); 1724 } 1725 } 1726 #endif /* ATW_BBPDEBUG */ 1727 1728 /* Set the power settings on the BBP for channel `chan'. */ 1729 static int 1730 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1731 { 1732 int rc = 0; 1733 u_int32_t reg; 1734 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1735 1736 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1737 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1738 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1739 1740 /* odd channels: LSB, even channels: MSB */ 1741 if (chan % 2 == 1) { 1742 txpower &= 0xFF; 1743 lpf_cutoff &= 0xFF; 1744 lna_gs_thresh &= 0xFF; 1745 } else { 1746 txpower >>= 8; 1747 lpf_cutoff >>= 8; 1748 lna_gs_thresh >>= 8; 1749 } 1750 1751 #ifdef ATW_BBPDEBUG 1752 atw_rf3000_print(sc); 1753 #endif /* ATW_BBPDEBUG */ 1754 1755 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1756 "lna_gs_thresh %02x\n", 1757 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1758 1759 atw_bbp_io_enable(sc, 1); 1760 1761 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1762 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1763 goto out; 1764 1765 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1766 goto out; 1767 1768 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1769 goto out; 1770 1771 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1772 1773 if (rc != 0) 1774 goto out; 1775 1776 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1777 1778 if (rc != 0) 1779 goto out; 1780 1781 #ifdef ATW_BBPDEBUG 1782 atw_rf3000_print(sc); 1783 #endif /* ATW_BBPDEBUG */ 1784 1785 out: 1786 atw_bbp_io_enable(sc, 0); 1787 1788 /* set beacon, rts, atim transmit power */ 1789 reg = ATW_READ(sc, ATW_PLCPHD); 1790 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1791 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1792 ATW_PLCPHD_SERVICE_MASK); 1793 ATW_WRITE(sc, ATW_PLCPHD, reg); 1794 DELAY(atw_plcphd_delay); 1795 1796 return rc; 1797 } 1798 1799 /* Write a register on the RF3000 baseband processor using the 1800 * registers provided by the ADM8211 for this purpose. 1801 * 1802 * Return 0 on success. 1803 */ 1804 static int 1805 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1806 { 1807 u_int32_t reg; 1808 int i; 1809 1810 reg = sc->sc_bbpctl_wr | 1811 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1812 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1813 1814 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1815 ATW_WRITE(sc, ATW_BBPCTL, reg); 1816 DELAY(2 * atw_pseudo_milli); 1817 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1818 break; 1819 } 1820 1821 if (i < 0) { 1822 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1823 return ETIMEDOUT; 1824 } 1825 return 0; 1826 } 1827 1828 /* Read a register on the RF3000 baseband processor using the registers 1829 * the ADM8211 provides for this purpose. 1830 * 1831 * The 7-bit register address is addr. Record the 8-bit data in the register 1832 * in *val. 1833 * 1834 * Return 0 on success. 1835 * 1836 * XXX This does not seem to work. The ADM8211 must require more or 1837 * different magic to read the chip than to write it. Possibly some 1838 * of the magic I have derived from a binary-only driver concerns 1839 * the "chip address" (see the RF3000 manual). 1840 */ 1841 #ifdef ATW_BBPDEBUG 1842 static int 1843 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1844 { 1845 u_int32_t reg; 1846 int i; 1847 1848 for (i = 1000; --i >= 0; ) { 1849 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1850 break; 1851 DELAY(100); 1852 } 1853 1854 if (i < 0) { 1855 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1856 device_xname(sc->sc_dev)); 1857 return ETIMEDOUT; 1858 } 1859 1860 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1861 1862 ATW_WRITE(sc, ATW_BBPCTL, reg); 1863 1864 for (i = 1000; --i >= 0; ) { 1865 DELAY(100); 1866 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1867 break; 1868 } 1869 1870 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1871 1872 if (i < 0) { 1873 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1874 device_xname(sc->sc_dev), reg); 1875 return ETIMEDOUT; 1876 } 1877 if (val != NULL) 1878 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1879 return 0; 1880 } 1881 #endif /* ATW_BBPDEBUG */ 1882 1883 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1884 * provided by the ADM8211 for that purpose. 1885 * 1886 * val is 18 bits of data, and val is the 4-bit address of the register. 1887 * 1888 * Return 0 on success. 1889 */ 1890 static void 1891 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1892 { 1893 uint32_t bits, mask, reg; 1894 const int nbits = 22; 1895 1896 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1897 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1898 1899 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1900 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1901 1902 reg = ATW_SYNRF_SELSYN; 1903 /* reference driver: reset Si4126 serial bus to initial 1904 * conditions? 1905 */ 1906 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1907 ATW_WRITE(sc, ATW_SYNRF, reg); 1908 1909 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1910 if ((bits & mask) != 0) 1911 reg |= ATW_SYNRF_SYNDATA; 1912 else 1913 reg &= ~ATW_SYNRF_SYNDATA; 1914 ATW_WRITE(sc, ATW_SYNRF, reg); 1915 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1916 ATW_WRITE(sc, ATW_SYNRF, reg); 1917 } 1918 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1919 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1920 } 1921 1922 /* Read 18-bit data from the 4-bit address addr in Si4126 1923 * RF synthesizer and write the data to *val. Return 0 on success. 1924 * 1925 * XXX This does not seem to work. The ADM8211 must require more or 1926 * different magic to read the chip than to write it. 1927 */ 1928 #ifdef ATW_SYNDEBUG 1929 static int 1930 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1931 { 1932 u_int32_t reg; 1933 int i; 1934 1935 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1936 1937 for (i = 1000; --i >= 0; ) { 1938 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1939 break; 1940 DELAY(100); 1941 } 1942 1943 if (i < 0) { 1944 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1945 device_xname(sc->sc_dev)); 1946 return ETIMEDOUT; 1947 } 1948 1949 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1950 1951 ATW_WRITE(sc, ATW_SYNCTL, reg); 1952 1953 for (i = 1000; --i >= 0; ) { 1954 DELAY(100); 1955 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1956 break; 1957 } 1958 1959 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1960 1961 if (i < 0) { 1962 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1963 device_xname(sc->sc_dev), reg); 1964 return ETIMEDOUT; 1965 } 1966 if (val != NULL) 1967 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1968 ATW_SYNCTL_DATA_MASK); 1969 return 0; 1970 } 1971 #endif /* ATW_SYNDEBUG */ 1972 1973 /* XXX is the endianness correct? test. */ 1974 #define atw_calchash(addr) \ 1975 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1976 1977 /* 1978 * atw_filter_setup: 1979 * 1980 * Set the ADM8211's receive filter. 1981 */ 1982 static void 1983 atw_filter_setup(struct atw_softc *sc) 1984 { 1985 struct ieee80211com *ic = &sc->sc_ic; 1986 struct ethercom *ec = &sc->sc_ec; 1987 struct ifnet *ifp = &sc->sc_if; 1988 int hash; 1989 u_int32_t hashes[2]; 1990 struct ether_multi *enm; 1991 struct ether_multistep step; 1992 1993 /* According to comments in tlp_al981_filter_setup 1994 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1995 * multicast filter to be set while it is running. Hopefully 1996 * the ADM8211 is not the same! 1997 */ 1998 if ((ifp->if_flags & IFF_RUNNING) != 0) 1999 atw_idle(sc, ATW_NAR_SR); 2000 2001 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 2002 ifp->if_flags &= ~IFF_ALLMULTI; 2003 2004 /* XXX in scan mode, do not filter packets. Maybe this is 2005 * unnecessary. 2006 */ 2007 if (ic->ic_state == IEEE80211_S_SCAN || 2008 (ifp->if_flags & IFF_PROMISC) != 0) { 2009 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2010 goto allmulti; 2011 } 2012 2013 hashes[0] = hashes[1] = 0x0; 2014 2015 /* 2016 * Program the 64-bit multicast hash filter. 2017 */ 2018 ETHER_FIRST_MULTI(step, ec, enm); 2019 while (enm != NULL) { 2020 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2021 ETHER_ADDR_LEN) != 0) 2022 goto allmulti; 2023 2024 hash = atw_calchash(enm->enm_addrlo); 2025 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2026 ETHER_NEXT_MULTI(step, enm); 2027 sc->sc_opmode |= ATW_NAR_MM; 2028 } 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 goto setit; 2031 2032 allmulti: 2033 sc->sc_opmode |= ATW_NAR_MM; 2034 ifp->if_flags |= IFF_ALLMULTI; 2035 hashes[0] = hashes[1] = 0xffffffff; 2036 2037 setit: 2038 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2039 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2040 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2041 DELAY(atw_nar_delay); 2042 ATW_WRITE(sc, ATW_RDR, 0x1); 2043 2044 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2045 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2046 } 2047 2048 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2049 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2050 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2051 * no beacon with the preferred BSSID and SSID in the number of 2052 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2053 */ 2054 static void 2055 atw_write_bssid(struct atw_softc *sc) 2056 { 2057 struct ieee80211com *ic = &sc->sc_ic; 2058 u_int8_t *bssid; 2059 2060 bssid = ic->ic_bss->ni_bssid; 2061 2062 ATW_WRITE(sc, ATW_BSSID0, 2063 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2064 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2065 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2066 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2067 2068 ATW_WRITE(sc, ATW_ABDA1, 2069 (ATW_READ(sc, ATW_ABDA1) & 2070 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2071 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2072 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2073 2074 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2075 ether_sprintf(sc->sc_bssid))); 2076 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2077 2078 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2079 } 2080 2081 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2082 * 16-bit word. 2083 */ 2084 static void 2085 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2086 { 2087 u_int i; 2088 u_int8_t *ptr; 2089 2090 memcpy(&sc->sc_sram[ofs], buf, buflen); 2091 2092 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2093 2094 KASSERT(buflen + ofs <= sc->sc_sramlen); 2095 2096 ptr = &sc->sc_sram[ofs]; 2097 2098 for (i = 0; i < buflen; i += 2) { 2099 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2100 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2101 DELAY(atw_writewep_delay); 2102 2103 ATW_WRITE(sc, ATW_WESK, 2104 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2105 DELAY(atw_writewep_delay); 2106 } 2107 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2108 2109 if (sc->sc_if.if_flags & IFF_DEBUG) { 2110 int n_octets = 0; 2111 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2112 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2113 for (i = 0; i < buflen; i++) { 2114 printf(" %02x", ptr[i]); 2115 if (++n_octets % 24 == 0) 2116 printf("\n"); 2117 } 2118 if (n_octets % 24 != 0) 2119 printf("\n"); 2120 } 2121 } 2122 2123 static int 2124 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2125 { 2126 struct atw_softc *sc = ic->ic_ifp->if_softc; 2127 u_int keyix = k->wk_keyix; 2128 2129 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2130 2131 if (keyix >= IEEE80211_WEP_NKID) 2132 return 0; 2133 if (k->wk_keylen != 0) 2134 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2135 2136 return 1; 2137 } 2138 2139 static int 2140 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2141 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2142 { 2143 struct atw_softc *sc = ic->ic_ifp->if_softc; 2144 2145 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2146 2147 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2148 return 0; 2149 2150 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2151 2152 return 1; 2153 } 2154 2155 static void 2156 atw_key_update_begin(struct ieee80211com *ic) 2157 { 2158 #ifdef ATW_DEBUG 2159 struct ifnet *ifp = ic->ic_ifp; 2160 struct atw_softc *sc = ifp->if_softc; 2161 #endif 2162 2163 DPRINTF(sc, ("%s:\n", __func__)); 2164 } 2165 2166 static void 2167 atw_key_update_end(struct ieee80211com *ic) 2168 { 2169 struct ifnet *ifp = ic->ic_ifp; 2170 struct atw_softc *sc = ifp->if_softc; 2171 2172 DPRINTF(sc, ("%s:\n", __func__)); 2173 2174 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2175 return; 2176 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2177 return; 2178 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2179 atw_write_wep(sc); 2180 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2181 DELAY(atw_nar_delay); 2182 ATW_WRITE(sc, ATW_RDR, 0x1); 2183 } 2184 2185 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2186 static void 2187 atw_write_wep(struct atw_softc *sc) 2188 { 2189 #if 0 2190 struct ieee80211com *ic = &sc->sc_ic; 2191 u_int32_t reg; 2192 int i; 2193 #endif 2194 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2195 u_int8_t buf[IEEE80211_WEP_NKID] 2196 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2197 2198 sc->sc_wepctl = 0; 2199 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2200 2201 memset(&buf[0][0], 0, sizeof(buf)); 2202 2203 #if 0 2204 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2205 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2206 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2207 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2208 buf[i][1] = ATW_WEP_ENABLED; 2209 } else { 2210 buf[i][1] = 0; 2211 continue; 2212 } 2213 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2214 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2215 ic->ic_nw_keys[i].wk_keylen - 1); 2216 } 2217 2218 reg = ATW_READ(sc, ATW_MACTEST); 2219 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2220 reg &= ~ATW_MACTEST_KEYID_MASK; 2221 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2222 ATW_WRITE(sc, ATW_MACTEST, reg); 2223 2224 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2225 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2226 2227 switch (sc->sc_rev) { 2228 case ATW_REVISION_AB: 2229 case ATW_REVISION_AF: 2230 /* Bypass WEP on Rx. */ 2231 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2232 break; 2233 default: 2234 break; 2235 } 2236 #endif 2237 2238 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2239 sizeof(buf)); 2240 2241 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2242 } 2243 2244 static void 2245 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2246 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2247 { 2248 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2249 2250 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2251 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2252 return; 2253 2254 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2255 2256 switch (subtype) { 2257 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2258 case IEEE80211_FC0_SUBTYPE_BEACON: 2259 if (ic->ic_opmode == IEEE80211_M_IBSS && 2260 ic->ic_state == IEEE80211_S_RUN) { 2261 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2262 (void)ieee80211_ibss_merge(ni); 2263 } 2264 break; 2265 default: 2266 break; 2267 } 2268 return; 2269 } 2270 2271 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2272 * In ad hoc mode, the SSID is written to the beacons sent by the 2273 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2274 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2275 * indications. 2276 */ 2277 static void 2278 atw_write_ssid(struct atw_softc *sc) 2279 { 2280 struct ieee80211com *ic = &sc->sc_ic; 2281 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2282 * it only expects the element length, not its ID. 2283 */ 2284 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2285 2286 memset(buf, 0, sizeof(buf)); 2287 buf[0] = ic->ic_bss->ni_esslen; 2288 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2289 2290 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2291 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2292 } 2293 2294 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2295 * In ad hoc mode, the supported rates are written to beacons sent by the 2296 * ADM8211. 2297 */ 2298 static void 2299 atw_write_sup_rates(struct atw_softc *sc) 2300 { 2301 struct ieee80211com *ic = &sc->sc_ic; 2302 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2303 * supported rates 2304 */ 2305 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2306 2307 memset(buf, 0, sizeof(buf)); 2308 2309 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2310 2311 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2312 ic->ic_bss->ni_rates.rs_nrates); 2313 2314 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2315 } 2316 2317 /* Start/stop sending beacons. */ 2318 void 2319 atw_start_beacon(struct atw_softc *sc, int start) 2320 { 2321 struct ieee80211com *ic = &sc->sc_ic; 2322 uint16_t chan; 2323 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2324 size_t len; 2325 2326 if (!device_is_active(sc->sc_dev)) 2327 return; 2328 2329 /* start beacons */ 2330 len = sizeof(struct ieee80211_frame) + 2331 8 /* timestamp */ + 2 /* beacon interval */ + 2332 2 /* capability info */ + 2333 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2334 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2335 3 /* DS parameters */ + 2336 IEEE80211_CRC_LEN; 2337 2338 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2339 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2340 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2341 2342 ATW_WRITE(sc, ATW_BCNT, bcnt); 2343 ATW_WRITE(sc, ATW_CAP1, cap1); 2344 2345 if (!start) 2346 return; 2347 2348 /* TBD use ni_capinfo */ 2349 2350 capinfo = 0; 2351 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2352 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2353 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2354 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2355 2356 switch (ic->ic_opmode) { 2357 case IEEE80211_M_IBSS: 2358 len += 4; /* IBSS parameters */ 2359 capinfo |= IEEE80211_CAPINFO_IBSS; 2360 break; 2361 case IEEE80211_M_HOSTAP: 2362 /* XXX 6-byte minimum TIM */ 2363 len += atw_beacon_len_adjust; 2364 capinfo |= IEEE80211_CAPINFO_ESS; 2365 break; 2366 default: 2367 return; 2368 } 2369 2370 /* set listen interval 2371 * XXX do software units agree w/ hardware? 2372 */ 2373 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2374 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2375 2376 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2377 2378 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2379 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2380 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2381 2382 ATW_WRITE(sc, ATW_BCNT, bcnt); 2383 ATW_WRITE(sc, ATW_BPLI, bpli); 2384 ATW_WRITE(sc, ATW_CAP0, cap0); 2385 ATW_WRITE(sc, ATW_CAP1, cap1); 2386 2387 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2388 device_xname(sc->sc_dev), bcnt)); 2389 2390 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2391 device_xname(sc->sc_dev), cap1)); 2392 } 2393 2394 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2395 static inline uint32_t 2396 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2397 { 2398 /* Following the reference driver's lead, I compute 2399 * 2400 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2401 * 2402 * without using 64-bit arithmetic, using the following 2403 * relationship: 2404 * 2405 * (0x100000000 * H + L) % m 2406 * = ((0x100000000 % m) * H + L) % m 2407 * = (((0xffffffff + 1) % m) * H + L) % m 2408 * = ((0xffffffff % m + 1 % m) * H + L) % m 2409 * = ((0xffffffff % m + 1) * H + L) % m 2410 */ 2411 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2412 } 2413 2414 static uint64_t 2415 atw_get_tsft(struct atw_softc *sc) 2416 { 2417 int i; 2418 uint32_t tsfth, tsftl; 2419 for (i = 0; i < 2; i++) { 2420 tsfth = ATW_READ(sc, ATW_TSFTH); 2421 tsftl = ATW_READ(sc, ATW_TSFTL); 2422 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2423 break; 2424 } 2425 return ((uint64_t)tsfth << 32) | tsftl; 2426 } 2427 2428 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2429 * the ieee80211com. 2430 * 2431 * Predict the next target beacon transmission time (TBTT) and 2432 * write it to the ADM8211. 2433 */ 2434 static void 2435 atw_predict_beacon(struct atw_softc *sc) 2436 { 2437 #define TBTTOFS 20 /* TU */ 2438 2439 struct ieee80211com *ic = &sc->sc_ic; 2440 uint64_t tsft; 2441 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2442 union { 2443 uint64_t word; 2444 uint8_t tstamp[8]; 2445 } u; 2446 2447 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2448 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2449 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2450 tsft = atw_get_tsft(sc); 2451 u.word = htole64(tsft); 2452 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2453 sizeof(ic->ic_bss->ni_tstamp)); 2454 } else 2455 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2456 2457 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2458 2459 tsftl = tsft & 0xFFFFFFFF; 2460 tsfth = tsft >> 32; 2461 2462 /* We sent/received the last beacon `past' microseconds 2463 * after the interval divided the TSF timer. 2464 */ 2465 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2466 2467 /* Skip ten beacons so that the TBTT cannot pass before 2468 * we've programmed it. Ten is an arbitrary number. 2469 */ 2470 tbtt = past_even + ival * 10; 2471 2472 ATW_WRITE(sc, ATW_TOFS1, 2473 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2474 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2475 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2476 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2477 #undef TBTTOFS 2478 } 2479 2480 static void 2481 atw_next_scan(void *arg) 2482 { 2483 struct atw_softc *sc = arg; 2484 struct ieee80211com *ic = &sc->sc_ic; 2485 int s; 2486 2487 /* don't call atw_start w/o network interrupts blocked */ 2488 s = splnet(); 2489 if (ic->ic_state == IEEE80211_S_SCAN) 2490 ieee80211_next_scan(ic); 2491 splx(s); 2492 } 2493 2494 /* Synchronize the hardware state with the software state. */ 2495 static int 2496 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2497 { 2498 struct ifnet *ifp = ic->ic_ifp; 2499 struct atw_softc *sc = ifp->if_softc; 2500 int error = 0; 2501 2502 callout_stop(&sc->sc_scan_ch); 2503 2504 switch (nstate) { 2505 case IEEE80211_S_AUTH: 2506 case IEEE80211_S_ASSOC: 2507 atw_write_bssid(sc); 2508 error = atw_tune(sc); 2509 break; 2510 case IEEE80211_S_INIT: 2511 callout_stop(&sc->sc_scan_ch); 2512 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2513 atw_start_beacon(sc, 0); 2514 break; 2515 case IEEE80211_S_SCAN: 2516 error = atw_tune(sc); 2517 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2518 atw_next_scan, sc); 2519 break; 2520 case IEEE80211_S_RUN: 2521 error = atw_tune(sc); 2522 atw_write_bssid(sc); 2523 atw_write_ssid(sc); 2524 atw_write_sup_rates(sc); 2525 2526 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2527 ic->ic_opmode == IEEE80211_M_MONITOR) 2528 break; 2529 2530 /* set listen interval 2531 * XXX do software units agree w/ hardware? 2532 */ 2533 ATW_WRITE(sc, ATW_BPLI, 2534 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2535 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2536 ATW_BPLI_LI_MASK)); 2537 2538 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2539 ATW_READ(sc, ATW_BPLI))); 2540 2541 atw_predict_beacon(sc); 2542 2543 switch (ic->ic_opmode) { 2544 case IEEE80211_M_AHDEMO: 2545 case IEEE80211_M_HOSTAP: 2546 case IEEE80211_M_IBSS: 2547 atw_start_beacon(sc, 1); 2548 break; 2549 case IEEE80211_M_MONITOR: 2550 case IEEE80211_M_STA: 2551 break; 2552 } 2553 2554 break; 2555 } 2556 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2557 } 2558 2559 /* 2560 * atw_add_rxbuf: 2561 * 2562 * Add a receive buffer to the indicated descriptor. 2563 */ 2564 int 2565 atw_add_rxbuf(struct atw_softc *sc, int idx) 2566 { 2567 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2568 struct mbuf *m; 2569 int error; 2570 2571 MGETHDR(m, M_DONTWAIT, MT_DATA); 2572 if (m == NULL) 2573 return (ENOBUFS); 2574 2575 MCLGET(m, M_DONTWAIT); 2576 if ((m->m_flags & M_EXT) == 0) { 2577 m_freem(m); 2578 return (ENOBUFS); 2579 } 2580 2581 if (rxs->rxs_mbuf != NULL) 2582 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2583 2584 rxs->rxs_mbuf = m; 2585 2586 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2587 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2588 BUS_DMA_READ|BUS_DMA_NOWAIT); 2589 if (error) { 2590 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2591 idx, error); 2592 panic("atw_add_rxbuf"); /* XXX */ 2593 } 2594 2595 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2596 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2597 2598 atw_init_rxdesc(sc, idx); 2599 2600 return (0); 2601 } 2602 2603 /* 2604 * Release any queued transmit buffers. 2605 */ 2606 void 2607 atw_txdrain(struct atw_softc *sc) 2608 { 2609 struct atw_txsoft *txs; 2610 2611 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2612 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2613 if (txs->txs_mbuf != NULL) { 2614 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2615 m_freem(txs->txs_mbuf); 2616 txs->txs_mbuf = NULL; 2617 } 2618 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2619 sc->sc_txfree += txs->txs_ndescs; 2620 } 2621 2622 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2623 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2624 sc->sc_txfree != ATW_NTXDESC)); 2625 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2626 sc->sc_tx_timer = 0; 2627 } 2628 2629 /* 2630 * atw_stop: [ ifnet interface function ] 2631 * 2632 * Stop transmission on the interface. 2633 */ 2634 void 2635 atw_stop(struct ifnet *ifp, int disable) 2636 { 2637 struct atw_softc *sc = ifp->if_softc; 2638 struct ieee80211com *ic = &sc->sc_ic; 2639 2640 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2641 2642 if (device_is_active(sc->sc_dev)) { 2643 /* Disable interrupts. */ 2644 ATW_WRITE(sc, ATW_IER, 0); 2645 2646 /* Stop the transmit and receive processes. */ 2647 ATW_WRITE(sc, ATW_NAR, 0); 2648 DELAY(atw_nar_delay); 2649 ATW_WRITE(sc, ATW_TDBD, 0); 2650 ATW_WRITE(sc, ATW_TDBP, 0); 2651 ATW_WRITE(sc, ATW_RDB, 0); 2652 } 2653 2654 sc->sc_opmode = 0; 2655 2656 atw_txdrain(sc); 2657 2658 /* 2659 * Mark the interface down and cancel the watchdog timer. 2660 */ 2661 ifp->if_flags &= ~IFF_RUNNING; 2662 ifp->if_timer = 0; 2663 2664 if (disable) 2665 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2666 } 2667 2668 /* 2669 * atw_rxdrain: 2670 * 2671 * Drain the receive queue. 2672 */ 2673 void 2674 atw_rxdrain(struct atw_softc *sc) 2675 { 2676 struct atw_rxsoft *rxs; 2677 int i; 2678 2679 for (i = 0; i < ATW_NRXDESC; i++) { 2680 rxs = &sc->sc_rxsoft[i]; 2681 if (rxs->rxs_mbuf == NULL) 2682 continue; 2683 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2684 m_freem(rxs->rxs_mbuf); 2685 rxs->rxs_mbuf = NULL; 2686 } 2687 } 2688 2689 /* 2690 * atw_detach: 2691 * 2692 * Detach an ADM8211 interface. 2693 */ 2694 int 2695 atw_detach(struct atw_softc *sc) 2696 { 2697 struct ifnet *ifp = &sc->sc_if; 2698 struct atw_rxsoft *rxs; 2699 struct atw_txsoft *txs; 2700 int i; 2701 2702 /* 2703 * Succeed now if there isn't any work to do. 2704 */ 2705 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2706 return (0); 2707 2708 pmf_device_deregister(sc->sc_dev); 2709 2710 callout_stop(&sc->sc_scan_ch); 2711 2712 ieee80211_ifdetach(&sc->sc_ic); 2713 if_detach(ifp); 2714 2715 for (i = 0; i < ATW_NRXDESC; i++) { 2716 rxs = &sc->sc_rxsoft[i]; 2717 if (rxs->rxs_mbuf != NULL) { 2718 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2719 m_freem(rxs->rxs_mbuf); 2720 rxs->rxs_mbuf = NULL; 2721 } 2722 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2723 } 2724 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2725 txs = &sc->sc_txsoft[i]; 2726 if (txs->txs_mbuf != NULL) { 2727 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2728 m_freem(txs->txs_mbuf); 2729 txs->txs_mbuf = NULL; 2730 } 2731 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2732 } 2733 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2734 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2735 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2736 sizeof(struct atw_control_data)); 2737 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2738 2739 if (sc->sc_srom) 2740 free(sc->sc_srom, M_DEVBUF); 2741 2742 atw_evcnt_detach(sc); 2743 2744 if (sc->sc_soft_ih != NULL) { 2745 softint_disestablish(sc->sc_soft_ih); 2746 sc->sc_soft_ih = NULL; 2747 } 2748 2749 return (0); 2750 } 2751 2752 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2753 bool 2754 atw_shutdown(device_t self, int flags) 2755 { 2756 struct atw_softc *sc = device_private(self); 2757 2758 atw_stop(&sc->sc_if, 1); 2759 return true; 2760 } 2761 2762 #if 0 2763 static void 2764 atw_workaround1(struct atw_softc *sc) 2765 { 2766 uint32_t test1; 2767 2768 test1 = ATW_READ(sc, ATW_TEST1); 2769 2770 sc->sc_misc_ev.ev_count++; 2771 2772 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2773 sc->sc_rxpkt1in_ev.ev_count++; 2774 return; 2775 } 2776 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2777 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2778 sc->sc_rxamatch_ev.ev_count++; 2779 return; 2780 } 2781 sc->sc_workaround1_ev.ev_count++; 2782 (void)atw_init(&sc->sc_if); 2783 } 2784 #endif 2785 2786 int 2787 atw_intr(void *arg) 2788 { 2789 struct atw_softc *sc = arg; 2790 struct ifnet *ifp = &sc->sc_if; 2791 uint32_t status; 2792 2793 #ifdef DEBUG 2794 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2795 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2796 #endif 2797 2798 /* 2799 * If the interface isn't running, the interrupt couldn't 2800 * possibly have come from us. 2801 */ 2802 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2803 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2804 return (0); 2805 2806 status = ATW_READ(sc, ATW_STSR); 2807 if (status == 0) 2808 return 0; 2809 2810 if ((status & sc->sc_inten) == 0) { 2811 ATW_WRITE(sc, ATW_STSR, status); 2812 return 0; 2813 } 2814 2815 /* Disable interrupts */ 2816 ATW_WRITE(sc, ATW_IER, 0); 2817 2818 softint_schedule(sc->sc_soft_ih); 2819 return 1; 2820 } 2821 2822 void 2823 atw_softintr(void *arg) 2824 { 2825 struct atw_softc *sc = arg; 2826 struct ifnet *ifp = &sc->sc_if; 2827 uint32_t status, rxstatus, txstatus, linkstatus; 2828 int txthresh, s; 2829 2830 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2831 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2832 return; 2833 2834 for (;;) { 2835 status = ATW_READ(sc, ATW_STSR); 2836 2837 if (status) 2838 ATW_WRITE(sc, ATW_STSR, status); 2839 2840 #ifdef ATW_DEBUG 2841 #define PRINTINTR(flag) do { \ 2842 if ((status & flag) != 0) { \ 2843 printf("%s" #flag, delim); \ 2844 delim = ","; \ 2845 } \ 2846 } while (0) 2847 2848 if (atw_debug > 1 && status) { 2849 const char *delim = "<"; 2850 2851 printf("%s: reg[STSR] = %x", 2852 device_xname(sc->sc_dev), status); 2853 2854 PRINTINTR(ATW_INTR_FBE); 2855 PRINTINTR(ATW_INTR_LINKOFF); 2856 PRINTINTR(ATW_INTR_LINKON); 2857 PRINTINTR(ATW_INTR_RCI); 2858 PRINTINTR(ATW_INTR_RDU); 2859 PRINTINTR(ATW_INTR_REIS); 2860 PRINTINTR(ATW_INTR_RPS); 2861 PRINTINTR(ATW_INTR_TCI); 2862 PRINTINTR(ATW_INTR_TDU); 2863 PRINTINTR(ATW_INTR_TLT); 2864 PRINTINTR(ATW_INTR_TPS); 2865 PRINTINTR(ATW_INTR_TRT); 2866 PRINTINTR(ATW_INTR_TUF); 2867 PRINTINTR(ATW_INTR_BCNTC); 2868 PRINTINTR(ATW_INTR_ATIME); 2869 PRINTINTR(ATW_INTR_TBTT); 2870 PRINTINTR(ATW_INTR_TSCZ); 2871 PRINTINTR(ATW_INTR_TSFTF); 2872 printf(">\n"); 2873 } 2874 #undef PRINTINTR 2875 #endif /* ATW_DEBUG */ 2876 2877 if ((status & sc->sc_inten) == 0) 2878 break; 2879 2880 rxstatus = status & sc->sc_rxint_mask; 2881 txstatus = status & sc->sc_txint_mask; 2882 linkstatus = status & sc->sc_linkint_mask; 2883 2884 if (linkstatus) { 2885 atw_linkintr(sc, linkstatus); 2886 } 2887 2888 if (rxstatus) { 2889 /* Grab any new packets. */ 2890 atw_rxintr(sc); 2891 2892 if (rxstatus & ATW_INTR_RDU) { 2893 printf("%s: receive ring overrun\n", 2894 device_xname(sc->sc_dev)); 2895 /* Get the receive process going again. */ 2896 ATW_WRITE(sc, ATW_RDR, 0x1); 2897 } 2898 } 2899 2900 if (txstatus) { 2901 /* Sweep up transmit descriptors. */ 2902 atw_txintr(sc, txstatus); 2903 2904 if (txstatus & ATW_INTR_TLT) { 2905 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2906 device_xname(sc->sc_dev))); 2907 (void)atw_init(&sc->sc_if); 2908 } 2909 2910 if (txstatus & ATW_INTR_TRT) { 2911 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2912 device_xname(sc->sc_dev))); 2913 } 2914 2915 /* If Tx under-run, increase our transmit threshold 2916 * if another is available. 2917 */ 2918 txthresh = sc->sc_txthresh + 1; 2919 if ((txstatus & ATW_INTR_TUF) && 2920 sc->sc_txth[txthresh].txth_name != NULL) { 2921 /* Idle the transmit process. */ 2922 atw_idle(sc, ATW_NAR_ST); 2923 2924 sc->sc_txthresh = txthresh; 2925 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2926 sc->sc_opmode |= 2927 sc->sc_txth[txthresh].txth_opmode; 2928 printf("%s: transmit underrun; new " 2929 "threshold: %s\n", device_xname(sc->sc_dev), 2930 sc->sc_txth[txthresh].txth_name); 2931 2932 /* Set the new threshold and restart 2933 * the transmit process. 2934 */ 2935 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2936 DELAY(atw_nar_delay); 2937 ATW_WRITE(sc, ATW_TDR, 0x1); 2938 /* XXX Log every Nth underrun from 2939 * XXX now on? 2940 */ 2941 } 2942 } 2943 2944 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2945 if (status & ATW_INTR_TPS) 2946 printf("%s: transmit process stopped\n", 2947 device_xname(sc->sc_dev)); 2948 if (status & ATW_INTR_RPS) 2949 printf("%s: receive process stopped\n", 2950 device_xname(sc->sc_dev)); 2951 s = splnet(); 2952 (void)atw_init(ifp); 2953 splx(s); 2954 break; 2955 } 2956 2957 if (status & ATW_INTR_FBE) { 2958 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2959 s = splnet(); 2960 (void)atw_init(ifp); 2961 splx(s); 2962 break; 2963 } 2964 2965 /* 2966 * Not handled: 2967 * 2968 * Transmit buffer unavailable -- normal 2969 * condition, nothing to do, really. 2970 * 2971 * Early receive interrupt -- not available on 2972 * all chips, we just use RI. We also only 2973 * use single-segment receive DMA, so this 2974 * is mostly useless. 2975 * 2976 * TBD others 2977 */ 2978 } 2979 2980 /* Try to get more packets going. */ 2981 s = splnet(); 2982 atw_start(ifp); 2983 splx(s); 2984 2985 /* Enable interrupts */ 2986 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 2987 } 2988 2989 /* 2990 * atw_idle: 2991 * 2992 * Cause the transmit and/or receive processes to go idle. 2993 * 2994 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2995 * process in STSR if I clear SR or ST after the process has already 2996 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2997 * do not seem to be too reliable. Perhaps I have the sense of the 2998 * Rx bits switched with the Tx bits? 2999 */ 3000 void 3001 atw_idle(struct atw_softc *sc, u_int32_t bits) 3002 { 3003 u_int32_t ackmask = 0, opmode, stsr, test0; 3004 int i, s; 3005 3006 s = splnet(); 3007 3008 opmode = sc->sc_opmode & ~bits; 3009 3010 if (bits & ATW_NAR_SR) 3011 ackmask |= ATW_INTR_RPS; 3012 3013 if (bits & ATW_NAR_ST) { 3014 ackmask |= ATW_INTR_TPS; 3015 /* set ATW_NAR_HF to flush TX FIFO. */ 3016 opmode |= ATW_NAR_HF; 3017 } 3018 3019 ATW_WRITE(sc, ATW_NAR, opmode); 3020 DELAY(atw_nar_delay); 3021 3022 for (i = 0; i < 1000; i++) { 3023 stsr = ATW_READ(sc, ATW_STSR); 3024 if ((stsr & ackmask) == ackmask) 3025 break; 3026 DELAY(10); 3027 } 3028 3029 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3030 3031 if ((stsr & ackmask) == ackmask) 3032 goto out; 3033 3034 test0 = ATW_READ(sc, ATW_TEST0); 3035 3036 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3037 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3038 printf("%s: transmit process not idle [%s]\n", 3039 device_xname(sc->sc_dev), 3040 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3041 printf("%s: bits %08x test0 %08x stsr %08x\n", 3042 device_xname(sc->sc_dev), bits, test0, stsr); 3043 } 3044 3045 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3046 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3047 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3048 device_xname(sc->sc_dev), 3049 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3050 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3051 device_xname(sc->sc_dev), bits, test0, stsr)); 3052 } 3053 out: 3054 if ((bits & ATW_NAR_ST) != 0) 3055 atw_txdrain(sc); 3056 splx(s); 3057 return; 3058 } 3059 3060 /* 3061 * atw_linkintr: 3062 * 3063 * Helper; handle link-status interrupts. 3064 */ 3065 void 3066 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3067 { 3068 struct ieee80211com *ic = &sc->sc_ic; 3069 3070 if (ic->ic_state != IEEE80211_S_RUN) 3071 return; 3072 3073 if (linkstatus & ATW_INTR_LINKON) { 3074 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3075 sc->sc_rescan_timer = 0; 3076 } else if (linkstatus & ATW_INTR_LINKOFF) { 3077 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3078 if (ic->ic_opmode != IEEE80211_M_STA) 3079 return; 3080 sc->sc_rescan_timer = 3; 3081 sc->sc_if.if_timer = 1; 3082 } 3083 } 3084 3085 #if 0 3086 static inline int 3087 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3088 { 3089 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3090 return 0; 3091 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3092 return 0; 3093 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3094 } 3095 #endif 3096 3097 /* 3098 * atw_rxintr: 3099 * 3100 * Helper; handle receive interrupts. 3101 */ 3102 void 3103 atw_rxintr(struct atw_softc *sc) 3104 { 3105 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3106 struct ieee80211com *ic = &sc->sc_ic; 3107 struct ieee80211_node *ni; 3108 struct ieee80211_frame_min *wh; 3109 struct ifnet *ifp = &sc->sc_if; 3110 struct atw_rxsoft *rxs; 3111 struct mbuf *m; 3112 u_int32_t rxstat; 3113 int i, s, len, rate, rate0; 3114 u_int32_t rssi, ctlrssi; 3115 3116 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3117 rxs = &sc->sc_rxsoft[i]; 3118 3119 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3120 3121 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3122 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3123 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3124 3125 if (rxstat & ATW_RXSTAT_OWN) { 3126 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3127 break; 3128 } 3129 3130 sc->sc_rxptr = ATW_NEXTRX(i); 3131 3132 DPRINTF3(sc, 3133 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3134 device_xname(sc->sc_dev), 3135 rxstat, ctlrssi, 3136 le32toh(sc->sc_rxdescs[i].ar_buf1), 3137 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3138 3139 /* 3140 * Make sure the packet fits in one buffer. This should 3141 * always be the case. 3142 */ 3143 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3144 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3145 printf("%s: incoming packet spilled, resetting\n", 3146 device_xname(sc->sc_dev)); 3147 (void)atw_init(ifp); 3148 return; 3149 } 3150 3151 /* 3152 * If an error occurred, update stats, clear the status 3153 * word, and leave the packet buffer in place. It will 3154 * simply be reused the next time the ring comes around. 3155 */ 3156 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3157 #define PRINTERR(bit, str) \ 3158 if (rxstat & (bit)) \ 3159 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3160 str) 3161 ifp->if_ierrors++; 3162 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3163 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3164 #if 0 3165 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3166 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3167 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3168 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3169 #endif 3170 #undef PRINTERR 3171 atw_init_rxdesc(sc, i); 3172 continue; 3173 } 3174 3175 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3176 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3177 3178 /* 3179 * No errors; receive the packet. Note the ADM8211 3180 * includes the CRC in promiscuous mode. 3181 */ 3182 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3183 3184 /* 3185 * Allocate a new mbuf cluster. If that fails, we are 3186 * out of memory, and must drop the packet and recycle 3187 * the buffer that's already attached to this descriptor. 3188 */ 3189 m = rxs->rxs_mbuf; 3190 if (atw_add_rxbuf(sc, i) != 0) { 3191 ifp->if_ierrors++; 3192 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3193 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3194 atw_init_rxdesc(sc, i); 3195 continue; 3196 } 3197 3198 ifp->if_ipackets++; 3199 m_set_rcvif(m, ifp); 3200 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3201 3202 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3203 3204 /* The RSSI comes straight from a register in the 3205 * baseband processor. I know that for the RF3000, 3206 * the RSSI register also contains the antenna-selection 3207 * bits. Mask those off. 3208 * 3209 * TBD Treat other basebands. 3210 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3211 */ 3212 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3213 rssi = ctlrssi & RF3000_RSSI_MASK; 3214 else 3215 rssi = ctlrssi; 3216 3217 s = splnet(); 3218 3219 /* Pass this up to any BPF listeners. */ 3220 if (sc->sc_radiobpf != NULL) { 3221 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3222 3223 tap->ar_rate = rate; 3224 3225 /* TBD verify units are dB */ 3226 tap->ar_antsignal = (int)rssi; 3227 if (sc->sc_opmode & ATW_NAR_PR) 3228 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3229 else 3230 tap->ar_flags = 0; 3231 3232 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3233 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3234 3235 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), 3236 m); 3237 } 3238 3239 sc->sc_recv_ev.ev_count++; 3240 3241 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3242 if (rxstat & ATW_RXSTAT_CRC16E) 3243 sc->sc_crc16e_ev.ev_count++; 3244 if (rxstat & ATW_RXSTAT_CRC32E) 3245 sc->sc_crc32e_ev.ev_count++; 3246 if (rxstat & ATW_RXSTAT_ICVE) 3247 sc->sc_icve_ev.ev_count++; 3248 if (rxstat & ATW_RXSTAT_SFDE) 3249 sc->sc_sfde_ev.ev_count++; 3250 if (rxstat & ATW_RXSTAT_SIGE) 3251 sc->sc_sige_ev.ev_count++; 3252 ifp->if_ierrors++; 3253 m_freem(m); 3254 splx(s); 3255 continue; 3256 } 3257 3258 if (sc->sc_opmode & ATW_NAR_PR) 3259 m_adj(m, -IEEE80211_CRC_LEN); 3260 3261 wh = mtod(m, struct ieee80211_frame_min *); 3262 ni = ieee80211_find_rxnode(ic, wh); 3263 #if 0 3264 if (atw_hw_decrypted(sc, wh)) { 3265 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3266 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3267 } 3268 #endif 3269 ieee80211_input(ic, m, ni, (int)rssi, 0); 3270 ieee80211_free_node(ni); 3271 splx(s); 3272 } 3273 } 3274 3275 /* 3276 * atw_txintr: 3277 * 3278 * Helper; handle transmit interrupts. 3279 */ 3280 void 3281 atw_txintr(struct atw_softc *sc, uint32_t status) 3282 { 3283 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3284 struct ifnet *ifp = &sc->sc_if; 3285 struct atw_txsoft *txs; 3286 u_int32_t txstat; 3287 int s; 3288 3289 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3290 device_xname(sc->sc_dev), sc->sc_flags)); 3291 3292 s = splnet(); 3293 3294 /* 3295 * Go through our Tx list and free mbufs for those 3296 * frames that have been transmitted. 3297 */ 3298 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3299 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3300 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3301 3302 #ifdef ATW_DEBUG 3303 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3304 int i; 3305 printf(" txsoft %p transmit chain:\n", txs); 3306 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3307 txs->txs_ndescs - 1, 3308 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3309 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3310 printf(" descriptor %d:\n", i); 3311 printf(" at_status: 0x%08x\n", 3312 le32toh(sc->sc_txdescs[i].at_stat)); 3313 printf(" at_flags: 0x%08x\n", 3314 le32toh(sc->sc_txdescs[i].at_flags)); 3315 printf(" at_buf1: 0x%08x\n", 3316 le32toh(sc->sc_txdescs[i].at_buf1)); 3317 printf(" at_buf2: 0x%08x\n", 3318 le32toh(sc->sc_txdescs[i].at_buf2)); 3319 if (i == txs->txs_lastdesc) 3320 break; 3321 } 3322 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3323 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3324 } 3325 #endif 3326 3327 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3328 if (txstat & ATW_TXSTAT_OWN) { 3329 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3330 BUS_DMASYNC_PREREAD); 3331 break; 3332 } 3333 3334 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3335 3336 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3337 0, txs->txs_dmamap->dm_mapsize, 3338 BUS_DMASYNC_POSTWRITE); 3339 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3340 m_freem(txs->txs_mbuf); 3341 txs->txs_mbuf = NULL; 3342 3343 sc->sc_txfree += txs->txs_ndescs; 3344 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3345 3346 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3347 sc->sc_tx_timer = 0; 3348 ifp->if_flags &= ~IFF_OACTIVE; 3349 3350 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3351 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3352 snprintb(txstat_buf, sizeof(txstat_buf), 3353 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3354 printf("%s: txstat %s %" __PRIuBITS "\n", 3355 device_xname(sc->sc_dev), txstat_buf, 3356 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3357 } 3358 3359 sc->sc_xmit_ev.ev_count++; 3360 3361 /* 3362 * Check for errors and collisions. 3363 */ 3364 if (txstat & ATW_TXSTAT_TUF) 3365 sc->sc_tuf_ev.ev_count++; 3366 if (txstat & ATW_TXSTAT_TLT) 3367 sc->sc_tlt_ev.ev_count++; 3368 if (txstat & ATW_TXSTAT_TRT) 3369 sc->sc_trt_ev.ev_count++; 3370 if (txstat & ATW_TXSTAT_TRO) 3371 sc->sc_tro_ev.ev_count++; 3372 if (txstat & ATW_TXSTAT_SOFBR) 3373 sc->sc_sofbr_ev.ev_count++; 3374 3375 if ((txstat & ATW_TXSTAT_ES) == 0) 3376 ifp->if_collisions += 3377 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3378 else 3379 ifp->if_oerrors++; 3380 3381 ifp->if_opackets++; 3382 } 3383 3384 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3385 3386 splx(s); 3387 } 3388 3389 /* 3390 * atw_watchdog: [ifnet interface function] 3391 * 3392 * Watchdog timer handler. 3393 */ 3394 void 3395 atw_watchdog(struct ifnet *ifp) 3396 { 3397 struct atw_softc *sc = ifp->if_softc; 3398 struct ieee80211com *ic = &sc->sc_ic; 3399 3400 ifp->if_timer = 0; 3401 if (!device_is_active(sc->sc_dev)) 3402 return; 3403 3404 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3405 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3406 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3407 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3408 printf("%s: transmit timeout\n", ifp->if_xname); 3409 ifp->if_oerrors++; 3410 (void)atw_init(ifp); 3411 atw_start(ifp); 3412 } 3413 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3414 ifp->if_timer = 1; 3415 ieee80211_watchdog(ic); 3416 } 3417 3418 static void 3419 atw_evcnt_detach(struct atw_softc *sc) 3420 { 3421 evcnt_detach(&sc->sc_sige_ev); 3422 evcnt_detach(&sc->sc_sfde_ev); 3423 evcnt_detach(&sc->sc_icve_ev); 3424 evcnt_detach(&sc->sc_crc32e_ev); 3425 evcnt_detach(&sc->sc_crc16e_ev); 3426 evcnt_detach(&sc->sc_recv_ev); 3427 3428 evcnt_detach(&sc->sc_tuf_ev); 3429 evcnt_detach(&sc->sc_tro_ev); 3430 evcnt_detach(&sc->sc_trt_ev); 3431 evcnt_detach(&sc->sc_tlt_ev); 3432 evcnt_detach(&sc->sc_sofbr_ev); 3433 evcnt_detach(&sc->sc_xmit_ev); 3434 3435 evcnt_detach(&sc->sc_rxpkt1in_ev); 3436 evcnt_detach(&sc->sc_rxamatch_ev); 3437 evcnt_detach(&sc->sc_workaround1_ev); 3438 evcnt_detach(&sc->sc_misc_ev); 3439 } 3440 3441 static void 3442 atw_evcnt_attach(struct atw_softc *sc) 3443 { 3444 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3445 NULL, sc->sc_if.if_xname, "recv"); 3446 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3447 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3448 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3449 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3450 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3451 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3452 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3453 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3454 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3455 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3456 3457 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3458 NULL, sc->sc_if.if_xname, "xmit"); 3459 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3460 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3461 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3462 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3463 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3464 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3465 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3466 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3467 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3468 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3469 3470 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3471 NULL, sc->sc_if.if_xname, "misc"); 3472 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3473 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3474 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3475 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3476 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3477 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3478 } 3479 3480 #ifdef ATW_DEBUG 3481 static void 3482 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3483 { 3484 struct atw_softc *sc = ifp->if_softc; 3485 struct mbuf *m; 3486 int i, noctets = 0; 3487 3488 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3489 m0->m_pkthdr.len); 3490 3491 for (m = m0; m; m = m->m_next) { 3492 if (m->m_len == 0) 3493 continue; 3494 for (i = 0; i < m->m_len; i++) { 3495 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3496 if (++noctets % 24 == 0) 3497 printf("\n"); 3498 } 3499 } 3500 printf("%s%s: %d bytes emitted\n", 3501 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3502 } 3503 #endif /* ATW_DEBUG */ 3504 3505 /* 3506 * atw_start: [ifnet interface function] 3507 * 3508 * Start packet transmission on the interface. 3509 */ 3510 void 3511 atw_start(struct ifnet *ifp) 3512 { 3513 struct atw_softc *sc = ifp->if_softc; 3514 struct ieee80211_key *k; 3515 struct ieee80211com *ic = &sc->sc_ic; 3516 struct ieee80211_node *ni; 3517 struct ieee80211_frame_min *whm; 3518 struct ieee80211_frame *wh; 3519 struct atw_frame *hh; 3520 uint16_t hdrctl; 3521 struct mbuf *m0, *m; 3522 struct atw_txsoft *txs; 3523 struct atw_txdesc *txd; 3524 int npkt, rate; 3525 bus_dmamap_t dmamap; 3526 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3527 3528 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3529 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3530 3531 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3532 return; 3533 3534 /* 3535 * Remember the previous number of free descriptors and 3536 * the first descriptor we'll use. 3537 */ 3538 ofree = sc->sc_txfree; 3539 firsttx = lasttx = sc->sc_txnext; 3540 3541 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3542 device_xname(sc->sc_dev), ofree, firsttx)); 3543 3544 /* 3545 * Loop through the send queue, setting up transmit descriptors 3546 * until we drain the queue, or use up all available transmit 3547 * descriptors. 3548 */ 3549 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3550 sc->sc_txfree != 0) { 3551 3552 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3553 3554 /* 3555 * Grab a packet off the management queue, if it 3556 * is not empty. Otherwise, from the data queue. 3557 */ 3558 IF_DEQUEUE(&ic->ic_mgtq, m0); 3559 if (m0 != NULL) { 3560 ni = M_GETCTX(m0, struct ieee80211_node *); 3561 M_CLEARCTX(m0); 3562 } else if (ic->ic_state != IEEE80211_S_RUN) 3563 break; /* send no data until associated */ 3564 else { 3565 IFQ_DEQUEUE(&ifp->if_snd, m0); 3566 if (m0 == NULL) 3567 break; 3568 bpf_mtap(ifp, m0); 3569 ni = ieee80211_find_txnode(ic, 3570 mtod(m0, struct ether_header *)->ether_dhost); 3571 if (ni == NULL) { 3572 ifp->if_oerrors++; 3573 break; 3574 } 3575 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3576 ieee80211_free_node(ni); 3577 ifp->if_oerrors++; 3578 break; 3579 } 3580 } 3581 3582 rate = MAX(ieee80211_get_rate(ni), 2); 3583 3584 whm = mtod(m0, struct ieee80211_frame_min *); 3585 3586 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3587 k = NULL; 3588 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3589 m_freem(m0); 3590 ieee80211_free_node(ni); 3591 ifp->if_oerrors++; 3592 break; 3593 } 3594 #if 0 3595 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3596 m0->m_pkthdr.len > ic->ic_fragthreshold) 3597 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3598 #endif 3599 3600 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3601 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3602 3603 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3604 ic->ic_flags, ic->ic_fragthreshold, rate, 3605 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3606 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3607 m_freem(m0); 3608 break; 3609 } 3610 3611 /* XXX Misleading if fragmentation is enabled. Better 3612 * to fragment in software? 3613 */ 3614 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3615 3616 /* 3617 * Pass the packet to any BPF listeners. 3618 */ 3619 bpf_mtap3(ic->ic_rawbpf, m0); 3620 3621 if (sc->sc_radiobpf != NULL) { 3622 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3623 3624 tap->at_rate = rate; 3625 3626 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), 3627 m0); 3628 } 3629 3630 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3631 3632 if (ni != NULL) 3633 ieee80211_free_node(ni); 3634 3635 if (m0 == NULL) { 3636 ifp->if_oerrors++; 3637 break; 3638 } 3639 3640 /* just to make sure. */ 3641 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3642 3643 if (m0 == NULL) { 3644 ifp->if_oerrors++; 3645 break; 3646 } 3647 3648 hh = mtod(m0, struct atw_frame *); 3649 wh = &hh->atw_ihdr; 3650 3651 /* Copy everything we need from the 802.11 header: 3652 * Frame Control; address 1, address 3, or addresses 3653 * 3 and 4. NIC fills in BSSID, SA. 3654 */ 3655 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3656 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3657 panic("%s: illegal WDS frame", 3658 device_xname(sc->sc_dev)); 3659 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3660 } else 3661 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3662 3663 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3664 3665 /* initialize remaining Tx parameters */ 3666 memset(&hh->u, 0, sizeof(hh->u)); 3667 3668 hh->atw_rate = rate * 5; 3669 /* XXX this could be incorrect if M_FCS. _encap should 3670 * probably strip FCS just in case it sticks around in 3671 * bridged packets. 3672 */ 3673 hh->atw_service = 0x00; /* XXX guess */ 3674 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3675 sizeof(struct atw_frame)); 3676 3677 /* never fragment multicast frames */ 3678 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3679 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3680 else { 3681 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3682 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3683 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3684 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3685 } 3686 3687 hh->atw_rtylmt = 3; 3688 #if 0 3689 if (do_encrypt) { 3690 hdrctl |= htole16(ATW_HDRCTL_WEP); 3691 hh->atw_keyid = ic->ic_def_txkey; 3692 } 3693 #endif 3694 3695 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3696 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3697 if (txs->txs_d0.d_residue) 3698 hh->atw_head_plcplen |= htole16(0x8000); 3699 if (txs->txs_dn.d_residue) 3700 hh->atw_tail_plcplen |= htole16(0x8000); 3701 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3702 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3703 3704 hh->atw_hdrctl = hdrctl; 3705 hh->atw_fragnum = npkt << 4; 3706 #ifdef ATW_DEBUG 3707 3708 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3709 printf("%s: dst = %s, rate = 0x%02x, " 3710 "service = 0x%02x, paylen = 0x%04x\n", 3711 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3712 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3713 3714 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3715 "dur1 = 0x%04x, dur2 = 0x%04x, " 3716 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3717 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3718 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3719 hh->atw_tail_dur, hh->atw_head_dur); 3720 3721 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3722 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3723 device_xname(sc->sc_dev), hh->atw_hdrctl, 3724 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3725 3726 printf("%s: keyid = %d\n", 3727 device_xname(sc->sc_dev), hh->atw_keyid); 3728 3729 atw_dump_pkt(ifp, m0); 3730 } 3731 #endif /* ATW_DEBUG */ 3732 3733 dmamap = txs->txs_dmamap; 3734 3735 /* 3736 * Load the DMA map. Copy and try (once) again if the packet 3737 * didn't fit in the alloted number of segments. 3738 */ 3739 for (first = 1; 3740 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3741 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3742 first = 0) { 3743 MGETHDR(m, M_DONTWAIT, MT_DATA); 3744 if (m == NULL) { 3745 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3746 break; 3747 } 3748 if (m0->m_pkthdr.len > MHLEN) { 3749 MCLGET(m, M_DONTWAIT); 3750 if ((m->m_flags & M_EXT) == 0) { 3751 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3752 "cluster\n"); 3753 m_freem(m); 3754 break; 3755 } 3756 } 3757 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3758 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3759 m_freem(m0); 3760 m0 = m; 3761 m = NULL; 3762 } 3763 if (error != 0) { 3764 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3765 "error = %d\n", error); 3766 m_freem(m0); 3767 break; 3768 } 3769 3770 /* 3771 * Ensure we have enough descriptors free to describe 3772 * the packet. 3773 */ 3774 if (dmamap->dm_nsegs > sc->sc_txfree) { 3775 /* 3776 * Not enough free descriptors to transmit 3777 * this packet. Unload the DMA map and 3778 * drop the packet. Notify the upper layer 3779 * that there are no more slots left. 3780 * 3781 * XXX We could allocate an mbuf and copy, but 3782 * XXX it is worth it? 3783 */ 3784 bus_dmamap_unload(sc->sc_dmat, dmamap); 3785 m_freem(m0); 3786 break; 3787 } 3788 3789 /* 3790 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3791 */ 3792 3793 /* Sync the DMA map. */ 3794 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3795 BUS_DMASYNC_PREWRITE); 3796 3797 /* XXX arbitrary retry limit; 8 because I have seen it in 3798 * use already and maybe 0 means "no tries" ! 3799 */ 3800 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3801 3802 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3803 device_xname(sc->sc_dev), rate * 5)); 3804 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3805 3806 /* 3807 * Initialize the transmit descriptors. 3808 */ 3809 for (nexttx = sc->sc_txnext, seg = 0; 3810 seg < dmamap->dm_nsegs; 3811 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3812 /* 3813 * If this is the first descriptor we're 3814 * enqueueing, don't set the OWN bit just 3815 * yet. That could cause a race condition. 3816 * We'll do it below. 3817 */ 3818 txd = &sc->sc_txdescs[nexttx]; 3819 txd->at_ctl = ctl | 3820 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3821 3822 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3823 txd->at_flags = 3824 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3825 ATW_TXFLAG_TBS1_MASK)) | 3826 ((nexttx == (ATW_NTXDESC - 1)) 3827 ? htole32(ATW_TXFLAG_TER) : 0); 3828 lasttx = nexttx; 3829 } 3830 3831 /* Set `first segment' and `last segment' appropriately. */ 3832 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3833 htole32(ATW_TXFLAG_FS); 3834 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3835 3836 #ifdef ATW_DEBUG 3837 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3838 printf(" txsoft %p transmit chain:\n", txs); 3839 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3840 printf(" descriptor %d:\n", seg); 3841 printf(" at_ctl: 0x%08x\n", 3842 le32toh(sc->sc_txdescs[seg].at_ctl)); 3843 printf(" at_flags: 0x%08x\n", 3844 le32toh(sc->sc_txdescs[seg].at_flags)); 3845 printf(" at_buf1: 0x%08x\n", 3846 le32toh(sc->sc_txdescs[seg].at_buf1)); 3847 printf(" at_buf2: 0x%08x\n", 3848 le32toh(sc->sc_txdescs[seg].at_buf2)); 3849 if (seg == lasttx) 3850 break; 3851 } 3852 } 3853 #endif 3854 3855 /* Sync the descriptors we're using. */ 3856 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3857 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3858 3859 /* 3860 * Store a pointer to the packet so we can free it later, 3861 * and remember what txdirty will be once the packet is 3862 * done. 3863 */ 3864 txs->txs_mbuf = m0; 3865 txs->txs_firstdesc = sc->sc_txnext; 3866 txs->txs_lastdesc = lasttx; 3867 txs->txs_ndescs = dmamap->dm_nsegs; 3868 3869 /* Advance the tx pointer. */ 3870 sc->sc_txfree -= dmamap->dm_nsegs; 3871 sc->sc_txnext = nexttx; 3872 3873 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3874 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3875 } 3876 3877 if (sc->sc_txfree != ofree) { 3878 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3879 device_xname(sc->sc_dev), lasttx, firsttx)); 3880 /* 3881 * Cause a transmit interrupt to happen on the 3882 * last packet we enqueued. 3883 */ 3884 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3885 ATW_CDTXSYNC(sc, lasttx, 1, 3886 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3887 3888 /* 3889 * The entire packet chain is set up. Give the 3890 * first descriptor to the chip now. 3891 */ 3892 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3893 ATW_CDTXSYNC(sc, firsttx, 1, 3894 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3895 3896 /* Wake up the transmitter. */ 3897 ATW_WRITE(sc, ATW_TDR, 0x1); 3898 3899 if (txs == NULL || sc->sc_txfree == 0) 3900 ifp->if_flags |= IFF_OACTIVE; 3901 3902 /* Set a watchdog timer in case the chip flakes out. */ 3903 sc->sc_tx_timer = 5; 3904 ifp->if_timer = 1; 3905 } 3906 } 3907 3908 /* 3909 * atw_ioctl: [ifnet interface function] 3910 * 3911 * Handle control requests from the operator. 3912 */ 3913 int 3914 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3915 { 3916 struct atw_softc *sc = ifp->if_softc; 3917 struct ieee80211req *ireq; 3918 int s, error = 0; 3919 3920 s = splnet(); 3921 3922 switch (cmd) { 3923 case SIOCSIFFLAGS: 3924 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3925 break; 3926 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 3927 case IFF_UP|IFF_RUNNING: 3928 /* 3929 * To avoid rescanning another access point, 3930 * do not call atw_init() here. Instead, 3931 * only reflect media settings. 3932 */ 3933 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3934 atw_filter_setup(sc); 3935 break; 3936 case IFF_UP: 3937 error = atw_init(ifp); 3938 break; 3939 case IFF_RUNNING: 3940 atw_stop(ifp, 1); 3941 break; 3942 case 0: 3943 break; 3944 } 3945 break; 3946 case SIOCADDMULTI: 3947 case SIOCDELMULTI: 3948 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3949 if (ifp->if_flags & IFF_RUNNING) 3950 atw_filter_setup(sc); /* do not rescan */ 3951 error = 0; 3952 } 3953 break; 3954 case SIOCS80211: 3955 ireq = data; 3956 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3957 if ((error = kauth_authorize_network(curlwp->l_cred, 3958 KAUTH_NETWORK_INTERFACE, 3959 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3960 (void *)cmd, NULL)) != 0) 3961 break; 3962 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3963 ireq->i_val <= IEEE80211_FRAG_MAX)) 3964 error = EINVAL; 3965 else 3966 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3967 break; 3968 } 3969 /*FALLTHROUGH*/ 3970 default: 3971 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3972 if (error == ENETRESET || error == ERESTART) { 3973 if (is_running(ifp)) 3974 error = atw_init(ifp); 3975 else 3976 error = 0; 3977 } 3978 break; 3979 } 3980 3981 /* Try to get more packets going. */ 3982 if (device_is_active(sc->sc_dev)) 3983 atw_start(ifp); 3984 3985 splx(s); 3986 return (error); 3987 } 3988 3989 static int 3990 atw_media_change(struct ifnet *ifp) 3991 { 3992 int error; 3993 3994 error = ieee80211_media_change(ifp); 3995 if (error == ENETRESET) { 3996 if (is_running(ifp)) 3997 error = atw_init(ifp); 3998 else 3999 error = 0; 4000 } 4001 return error; 4002 } 4003
Indexes created Wed Sep 24 05:09:52 GMT 2025