atw.c revision 1.162.2.1
1 /* $NetBSD: atw.c,v 1.162.2.1 2018/05/02 07:20:06 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.162.2.1 2018/05/02 07:20:06 pgoyette Exp $"); 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/kauth.h> 51 #include <sys/time.h> 52 #include <sys/proc.h> 53 #include <sys/atomic.h> 54 #include <lib/libkern/libkern.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <net/bpf.h> 68 69 #include <sys/bus.h> 70 #include <sys/intr.h> 71 72 #include <dev/ic/atwreg.h> 73 #include <dev/ic/rf3000reg.h> 74 #include <dev/ic/si4136reg.h> 75 #include <dev/ic/atwvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* XXX TBD open questions 79 * 80 * 81 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 82 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 83 * handle this for me? 84 * 85 */ 86 /* device attachment 87 * 88 * print TOFS[012] 89 * 90 * device initialization 91 * 92 * clear ATW_FRCTL_MAXPSP to disable max power saving 93 * set ATW_TXBR_ALCUPDATE to enable ALC 94 * set TOFS[012]? (hope not) 95 * disable rx/tx 96 * set ATW_PAR_SWR (software reset) 97 * wait for ATW_PAR_SWR clear 98 * disable interrupts 99 * ack status register 100 * enable interrupts 101 * 102 * rx/tx initialization 103 * 104 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 105 * allocate and init descriptor rings 106 * write ATW_PAR_DSL (descriptor skip length) 107 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 108 * write ATW_NAR_SQ for one/both transmit descriptor rings 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * 112 * rx/tx end 113 * 114 * stop DMA 115 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * flush tx w/ ATW_NAR_HF 117 * 118 * scan 119 * 120 * initialize rx/tx 121 * 122 * BSS join: (re)association response 123 * 124 * set ATW_FRCTL_AID 125 * 126 * optimizations ??? 127 * 128 */ 129 130 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 131 132 int atw_pseudo_milli = 1; 133 int atw_magic_delay1 = 100 * 1000; 134 int atw_magic_delay2 = 100 * 1000; 135 /* more magic multi-millisecond delays (units: microseconds) */ 136 int atw_nar_delay = 20 * 1000; 137 int atw_magic_delay4 = 10 * 1000; 138 int atw_rf_delay1 = 10 * 1000; 139 int atw_rf_delay2 = 5 * 1000; 140 int atw_plcphd_delay = 2 * 1000; 141 int atw_bbp_io_enable_delay = 20 * 1000; 142 int atw_bbp_io_disable_delay = 2 * 1000; 143 int atw_writewep_delay = 1000; 144 int atw_beacon_len_adjust = 4; 145 int atw_dwelltime = 200; 146 int atw_xindiv2 = 0; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 159 static void atw_print_regs(struct atw_softc *, const char *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static void atw_rf3000_print(struct atw_softc *); 164 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static void atw_si4126_print(struct atw_softc *); 169 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 170 # endif /* ATW_SYNDEBUG */ 171 #define __atwdebugused /* empty */ 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #define __atwdebugused __unused 180 #endif 181 182 /* ifnet methods */ 183 int atw_init(struct ifnet *); 184 int atw_ioctl(struct ifnet *, u_long, void *); 185 void atw_start(struct ifnet *); 186 void atw_stop(struct ifnet *, int); 187 void atw_watchdog(struct ifnet *); 188 189 /* Device attachment */ 190 void atw_attach(struct atw_softc *); 191 int atw_detach(struct atw_softc *); 192 static void atw_evcnt_attach(struct atw_softc *); 193 static void atw_evcnt_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 int atw_add_rxbuf(struct atw_softc *, int); 197 void atw_idle(struct atw_softc *, u_int32_t); 198 void atw_rxdrain(struct atw_softc *); 199 void atw_txdrain(struct atw_softc *); 200 201 /* Device (de)activation and power state */ 202 void atw_reset(struct atw_softc *); 203 204 /* Interrupt handlers */ 205 void atw_softintr(void *); 206 void atw_linkintr(struct atw_softc *, u_int32_t); 207 void atw_rxintr(struct atw_softc *); 208 void atw_txintr(struct atw_softc *, uint32_t); 209 210 /* 802.11 state machine */ 211 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 212 static void atw_next_scan(void *); 213 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 214 struct ieee80211_node *, int, int, u_int32_t); 215 static int atw_tune(struct atw_softc *); 216 217 /* Device initialization */ 218 static void atw_bbp_io_init(struct atw_softc *); 219 static void atw_cfp_init(struct atw_softc *); 220 static void atw_cmdr_init(struct atw_softc *); 221 static void atw_ifs_init(struct atw_softc *); 222 static void atw_nar_init(struct atw_softc *); 223 static void atw_response_times_init(struct atw_softc *); 224 static void atw_rf_reset(struct atw_softc *); 225 static void atw_test1_init(struct atw_softc *); 226 static void atw_tofs0_init(struct atw_softc *); 227 static void atw_tofs2_init(struct atw_softc *); 228 static void atw_txlmt_init(struct atw_softc *); 229 static void atw_wcsr_init(struct atw_softc *); 230 231 /* Key management */ 232 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 233 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 234 const u_int8_t[IEEE80211_ADDR_LEN]); 235 static void atw_key_update_begin(struct ieee80211com *); 236 static void atw_key_update_end(struct ieee80211com *); 237 238 /* RAM/ROM utilities */ 239 static void atw_clear_sram(struct atw_softc *); 240 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 241 static int atw_read_srom(struct atw_softc *); 242 243 /* BSS setup */ 244 static void atw_predict_beacon(struct atw_softc *); 245 static void atw_start_beacon(struct atw_softc *, int); 246 static void atw_write_bssid(struct atw_softc *); 247 static void atw_write_ssid(struct atw_softc *); 248 static void atw_write_sup_rates(struct atw_softc *); 249 static void atw_write_wep(struct atw_softc *); 250 251 /* Media */ 252 static int atw_media_change(struct ifnet *); 253 254 static void atw_filter_setup(struct atw_softc *); 255 256 /* 802.11 utilities */ 257 static uint64_t atw_get_tsft(struct atw_softc *); 258 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 259 uint32_t); 260 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 261 static void atw_node_free(struct ieee80211_node *); 262 263 /* 264 * Tuner/transceiver/modem 265 */ 266 static void atw_bbp_io_enable(struct atw_softc *, int); 267 268 /* RFMD RF3000 Baseband Processor */ 269 static int atw_rf3000_init(struct atw_softc *); 270 static int atw_rf3000_tune(struct atw_softc *, u_int); 271 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 272 273 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 274 static void atw_si4126_tune(struct atw_softc *, u_int); 275 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 276 277 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 278 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 279 280 const char *atw_tx_state[] = { 281 "STOPPED", 282 "RUNNING - read descriptor", 283 "RUNNING - transmitting", 284 "RUNNING - filling fifo", /* XXX */ 285 "SUSPENDED", 286 "RUNNING -- write descriptor", 287 "RUNNING -- write last descriptor", 288 "RUNNING - fifo full" 289 }; 290 291 const char *atw_rx_state[] = { 292 "STOPPED", 293 "RUNNING - read descriptor", 294 "RUNNING - check this packet, pre-fetch next", 295 "RUNNING - wait for reception", 296 "SUSPENDED", 297 "RUNNING - write descriptor", 298 "RUNNING - flush fifo", 299 "RUNNING - fifo drain" 300 }; 301 302 static inline int 303 is_running(struct ifnet *ifp) 304 { 305 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 306 } 307 308 int 309 atw_activate(device_t self, enum devact act) 310 { 311 struct atw_softc *sc = device_private(self); 312 313 switch (act) { 314 case DVACT_DEACTIVATE: 315 if_deactivate(&sc->sc_if); 316 return 0; 317 default: 318 return EOPNOTSUPP; 319 } 320 } 321 322 bool 323 atw_suspend(device_t self, const pmf_qual_t *qual) 324 { 325 struct atw_softc *sc = device_private(self); 326 327 atw_rxdrain(sc); 328 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 329 330 return true; 331 } 332 333 /* Returns -1 on failure. */ 334 static int 335 atw_read_srom(struct atw_softc *sc) 336 { 337 struct seeprom_descriptor sd; 338 uint32_t test0, fail_bits; 339 340 (void)memset(&sd, 0, sizeof(sd)); 341 342 test0 = ATW_READ(sc, ATW_TEST0); 343 344 switch (sc->sc_rev) { 345 case ATW_REVISION_BA: 346 case ATW_REVISION_CA: 347 fail_bits = ATW_TEST0_EPNE; 348 break; 349 default: 350 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 351 break; 352 } 353 if ((test0 & fail_bits) != 0) { 354 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 355 return -1; 356 } 357 358 switch (test0 & ATW_TEST0_EPTYP_MASK) { 359 case ATW_TEST0_EPTYP_93c66: 360 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 361 sc->sc_sromsz = 512; 362 sd.sd_chip = C56_66; 363 break; 364 case ATW_TEST0_EPTYP_93c46: 365 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 366 sc->sc_sromsz = 128; 367 sd.sd_chip = C46; 368 break; 369 default: 370 printf("%s: unknown SROM type %" __PRIuBITS "\n", 371 device_xname(sc->sc_dev), 372 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 373 return -1; 374 } 375 376 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 377 378 if (sc->sc_srom == NULL) { 379 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 380 return -1; 381 } 382 383 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 384 385 /* ADM8211 has a single 32-bit register for controlling the 386 * 93cx6 SROM. Bit SRS enables the serial port. There is no 387 * "ready" bit. The ADM8211 input/output sense is the reverse 388 * of read_seeprom's. 389 */ 390 sd.sd_tag = sc->sc_st; 391 sd.sd_bsh = sc->sc_sh; 392 sd.sd_regsize = 4; 393 sd.sd_control_offset = ATW_SPR; 394 sd.sd_status_offset = ATW_SPR; 395 sd.sd_dataout_offset = ATW_SPR; 396 sd.sd_CK = ATW_SPR_SCLK; 397 sd.sd_CS = ATW_SPR_SCS; 398 sd.sd_DI = ATW_SPR_SDO; 399 sd.sd_DO = ATW_SPR_SDI; 400 sd.sd_MS = ATW_SPR_SRS; 401 sd.sd_RDY = 0; 402 403 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 404 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 405 free(sc->sc_srom, M_DEVBUF); 406 return -1; 407 } 408 #ifdef ATW_DEBUG 409 { 410 int i; 411 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 412 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 413 if (((i % 8) == 0) && (i != 0)) { 414 ATW_DPRINTF(("\n\t")); 415 } 416 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 417 } 418 ATW_DPRINTF(("\n")); 419 } 420 #endif /* ATW_DEBUG */ 421 return 0; 422 } 423 424 #ifdef ATW_DEBUG 425 static void 426 atw_print_regs(struct atw_softc *sc, const char *where) 427 { 428 #define PRINTREG(sc, reg) \ 429 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 430 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 431 432 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 433 434 PRINTREG(sc, ATW_PAR); 435 PRINTREG(sc, ATW_FRCTL); 436 PRINTREG(sc, ATW_TDR); 437 PRINTREG(sc, ATW_WTDP); 438 PRINTREG(sc, ATW_RDR); 439 PRINTREG(sc, ATW_WRDP); 440 PRINTREG(sc, ATW_RDB); 441 PRINTREG(sc, ATW_CSR3A); 442 PRINTREG(sc, ATW_TDBD); 443 PRINTREG(sc, ATW_TDBP); 444 PRINTREG(sc, ATW_STSR); 445 PRINTREG(sc, ATW_CSR5A); 446 PRINTREG(sc, ATW_NAR); 447 PRINTREG(sc, ATW_CSR6A); 448 PRINTREG(sc, ATW_IER); 449 PRINTREG(sc, ATW_CSR7A); 450 PRINTREG(sc, ATW_LPC); 451 PRINTREG(sc, ATW_TEST1); 452 PRINTREG(sc, ATW_SPR); 453 PRINTREG(sc, ATW_TEST0); 454 PRINTREG(sc, ATW_WCSR); 455 PRINTREG(sc, ATW_WPDR); 456 PRINTREG(sc, ATW_GPTMR); 457 PRINTREG(sc, ATW_GPIO); 458 PRINTREG(sc, ATW_BBPCTL); 459 PRINTREG(sc, ATW_SYNCTL); 460 PRINTREG(sc, ATW_PLCPHD); 461 PRINTREG(sc, ATW_MMIWADDR); 462 PRINTREG(sc, ATW_MMIRADDR1); 463 PRINTREG(sc, ATW_MMIRADDR2); 464 PRINTREG(sc, ATW_TXBR); 465 PRINTREG(sc, ATW_CSR15A); 466 PRINTREG(sc, ATW_ALCSTAT); 467 PRINTREG(sc, ATW_TOFS2); 468 PRINTREG(sc, ATW_CMDR); 469 PRINTREG(sc, ATW_PCIC); 470 PRINTREG(sc, ATW_PMCSR); 471 PRINTREG(sc, ATW_PAR0); 472 PRINTREG(sc, ATW_PAR1); 473 PRINTREG(sc, ATW_MAR0); 474 PRINTREG(sc, ATW_MAR1); 475 PRINTREG(sc, ATW_ATIMDA0); 476 PRINTREG(sc, ATW_ABDA1); 477 PRINTREG(sc, ATW_BSSID0); 478 PRINTREG(sc, ATW_TXLMT); 479 PRINTREG(sc, ATW_MIBCNT); 480 PRINTREG(sc, ATW_BCNT); 481 PRINTREG(sc, ATW_TSFTH); 482 PRINTREG(sc, ATW_TSC); 483 PRINTREG(sc, ATW_SYNRF); 484 PRINTREG(sc, ATW_BPLI); 485 PRINTREG(sc, ATW_CAP0); 486 PRINTREG(sc, ATW_CAP1); 487 PRINTREG(sc, ATW_RMD); 488 PRINTREG(sc, ATW_CFPP); 489 PRINTREG(sc, ATW_TOFS0); 490 PRINTREG(sc, ATW_TOFS1); 491 PRINTREG(sc, ATW_IFST); 492 PRINTREG(sc, ATW_RSPT); 493 PRINTREG(sc, ATW_TSFTL); 494 PRINTREG(sc, ATW_WEPCTL); 495 PRINTREG(sc, ATW_WESK); 496 PRINTREG(sc, ATW_WEPCNT); 497 PRINTREG(sc, ATW_MACTEST); 498 PRINTREG(sc, ATW_FER); 499 PRINTREG(sc, ATW_FEMR); 500 PRINTREG(sc, ATW_FPSR); 501 PRINTREG(sc, ATW_FFER); 502 #undef PRINTREG 503 } 504 #endif /* ATW_DEBUG */ 505 506 /* 507 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 508 */ 509 void 510 atw_attach(struct atw_softc *sc) 511 { 512 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 513 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 514 }; 515 struct ieee80211com *ic = &sc->sc_ic; 516 struct ifnet *ifp = &sc->sc_if; 517 int country_code, error, i, srom_major; 518 u_int32_t reg; 519 static const char *type_strings[] = {"Intersil (not supported)", 520 "RFMD", "Marvel (not supported)"}; 521 522 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 523 524 sc->sc_soft_ih = softint_establish(SOFTINT_NET, atw_softintr, sc); 525 if (sc->sc_soft_ih == NULL) { 526 aprint_error_dev(sc->sc_dev, "unable to establish softint\n"); 527 goto fail_0; 528 } 529 530 sc->sc_txth = atw_txthresh_tab_lo; 531 532 SIMPLEQ_INIT(&sc->sc_txfreeq); 533 SIMPLEQ_INIT(&sc->sc_txdirtyq); 534 535 #ifdef ATW_DEBUG 536 atw_print_regs(sc, "atw_attach"); 537 #endif /* ATW_DEBUG */ 538 539 /* 540 * Allocate the control data structures, and create and load the 541 * DMA map for it. 542 */ 543 if ((error = bus_dmamem_alloc(sc->sc_dmat, 544 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 545 1, &sc->sc_cdnseg, 0)) != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "unable to allocate control data, error = %d\n", 548 error); 549 goto fail_0; 550 } 551 552 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 553 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 554 BUS_DMA_COHERENT)) != 0) { 555 aprint_error_dev(sc->sc_dev, 556 "unable to map control data, error = %d\n", 557 error); 558 goto fail_1; 559 } 560 561 if ((error = bus_dmamap_create(sc->sc_dmat, 562 sizeof(struct atw_control_data), 1, 563 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 564 aprint_error_dev(sc->sc_dev, 565 "unable to create control data DMA map, error = %d\n", 566 error); 567 goto fail_2; 568 } 569 570 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 571 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 572 0)) != 0) { 573 aprint_error_dev(sc->sc_dev, 574 "unable to load control data DMA map, error = %d\n", error); 575 goto fail_3; 576 } 577 578 /* 579 * Create the transmit buffer DMA maps. 580 */ 581 sc->sc_ntxsegs = ATW_NTXSEGS; 582 for (i = 0; i < ATW_TXQUEUELEN; i++) { 583 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 584 sc->sc_ntxsegs, MCLBYTES, 0, 0, 585 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 586 aprint_error_dev(sc->sc_dev, 587 "unable to create tx DMA map %d, error = %d\n", i, 588 error); 589 goto fail_4; 590 } 591 } 592 593 /* 594 * Create the receive buffer DMA maps. 595 */ 596 for (i = 0; i < ATW_NRXDESC; i++) { 597 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 598 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "unable to create rx DMA map %d, error = %d\n", i, 601 error); 602 goto fail_5; 603 } 604 } 605 for (i = 0; i < ATW_NRXDESC; i++) { 606 sc->sc_rxsoft[i].rxs_mbuf = NULL; 607 } 608 609 switch (sc->sc_rev) { 610 case ATW_REVISION_AB: 611 case ATW_REVISION_AF: 612 sc->sc_sramlen = ATW_SRAM_A_SIZE; 613 break; 614 case ATW_REVISION_BA: 615 case ATW_REVISION_CA: 616 sc->sc_sramlen = ATW_SRAM_B_SIZE; 617 break; 618 } 619 620 /* Reset the chip to a known state. */ 621 atw_reset(sc); 622 623 if (atw_read_srom(sc) == -1) 624 goto fail_5; 625 626 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 627 ATW_SR_RFTYPE_MASK); 628 629 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 630 ATW_SR_BBPTYPE_MASK); 631 632 if (sc->sc_rftype >= __arraycount(type_strings)) { 633 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 634 goto fail_5; 635 } 636 if (sc->sc_bbptype >= __arraycount(type_strings)) { 637 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 638 goto fail_5; 639 } 640 641 aprint_normal_dev(sc->sc_dev, "%s RF, %s BBP", 642 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 643 644 /* XXX There exists a Linux driver which seems to use RFType = 0 for 645 * MARVEL. My bug, or theirs? 646 */ 647 648 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 649 650 switch (sc->sc_rftype) { 651 case ATW_RFTYPE_INTERSIL: 652 reg |= ATW_SYNCTL_CS1; 653 break; 654 case ATW_RFTYPE_RFMD: 655 reg |= ATW_SYNCTL_CS0; 656 break; 657 case ATW_RFTYPE_MARVEL: 658 break; 659 } 660 661 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 662 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 663 664 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 665 666 switch (sc->sc_bbptype) { 667 case ATW_BBPTYPE_INTERSIL: 668 reg |= ATW_BBPCTL_TWI; 669 break; 670 case ATW_BBPTYPE_RFMD: 671 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 672 ATW_BBPCTL_CCA_ACTLO; 673 break; 674 case ATW_BBPTYPE_MARVEL: 675 break; 676 case ATW_C_BBPTYPE_RFMD: 677 aprint_error_dev(sc->sc_dev, 678 "ADM8211C MAC/RFMD BBP not supported yet.\n"); 679 break; 680 } 681 682 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 683 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 684 685 /* 686 * From this point forward, the attachment cannot fail. A failure 687 * before this point releases all resources that may have been 688 * allocated. 689 */ 690 sc->sc_flags |= ATWF_ATTACHED; 691 692 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 693 htole16(sc->sc_srom[ATW_SR_MAC00]), 694 htole16(sc->sc_srom[ATW_SR_MAC01]), 695 htole16(sc->sc_srom[ATW_SR_MAC10]))); 696 697 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 698 ATW_SR_MAJOR_MASK); 699 700 if (srom_major < 2) 701 sc->sc_rf3000_options1 = 0; 702 else if (sc->sc_rev == ATW_REVISION_BA) { 703 sc->sc_rf3000_options1 = 704 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 705 ATW_SR_CR28_MASK); 706 } else 707 sc->sc_rf3000_options1 = 0; 708 709 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 710 ATW_SR_CR29_MASK); 711 712 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 713 ATW_SR_CTRY_MASK); 714 715 #define ADD_CHANNEL(_ic, _chan) do { \ 716 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 717 _ic->ic_channels[_chan].ic_freq = \ 718 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 719 } while (0) 720 721 /* Find available channels */ 722 switch (country_code) { 723 case COUNTRY_MMK2: /* 1-14 */ 724 ADD_CHANNEL(ic, 14); 725 /*FALLTHROUGH*/ 726 case COUNTRY_ETSI: /* 1-13 */ 727 for (i = 1; i <= 13; i++) 728 ADD_CHANNEL(ic, i); 729 break; 730 case COUNTRY_FCC: /* 1-11 */ 731 case COUNTRY_IC: /* 1-11 */ 732 for (i = 1; i <= 11; i++) 733 ADD_CHANNEL(ic, i); 734 break; 735 case COUNTRY_MMK: /* 14 */ 736 ADD_CHANNEL(ic, 14); 737 break; 738 case COUNTRY_FRANCE: /* 10-13 */ 739 for (i = 10; i <= 13; i++) 740 ADD_CHANNEL(ic, i); 741 break; 742 default: /* assume channels 10-11 */ 743 case COUNTRY_SPAIN: /* 10-11 */ 744 for (i = 10; i <= 11; i++) 745 ADD_CHANNEL(ic, i); 746 break; 747 } 748 749 /* Read the MAC address. */ 750 reg = ATW_READ(sc, ATW_PAR0); 751 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 752 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 753 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 754 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 755 reg = ATW_READ(sc, ATW_PAR1); 756 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 757 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 758 759 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 760 aprint_error_dev(sc->sc_dev, 761 "could not get mac address, attach failed\n"); 762 goto fail_5; 763 } 764 765 aprint_normal(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 766 767 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 768 ifp->if_softc = sc; 769 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 770 IFF_NOTRAILERS; 771 ifp->if_ioctl = atw_ioctl; 772 ifp->if_start = atw_start; 773 ifp->if_watchdog = atw_watchdog; 774 ifp->if_init = atw_init; 775 ifp->if_stop = atw_stop; 776 IFQ_SET_READY(&ifp->if_snd); 777 778 ic->ic_ifp = ifp; 779 ic->ic_phytype = IEEE80211_T_DS; 780 ic->ic_opmode = IEEE80211_M_STA; 781 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 782 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 783 784 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 785 786 /* 787 * Call MI attach routines. 788 */ 789 790 error = if_initialize(ifp); 791 if (error != 0) { 792 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 793 error); 794 goto fail_5; 795 } 796 ieee80211_ifattach(ic); 797 /* Use common softint-based if_input */ 798 ifp->if_percpuq = if_percpuq_create(ifp); 799 if_register(ifp); 800 801 atw_evcnt_attach(sc); 802 803 sc->sc_newstate = ic->ic_newstate; 804 ic->ic_newstate = atw_newstate; 805 806 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 807 ic->ic_recv_mgmt = atw_recv_mgmt; 808 809 sc->sc_node_free = ic->ic_node_free; 810 ic->ic_node_free = atw_node_free; 811 812 sc->sc_node_alloc = ic->ic_node_alloc; 813 ic->ic_node_alloc = atw_node_alloc; 814 815 ic->ic_crypto.cs_key_delete = atw_key_delete; 816 ic->ic_crypto.cs_key_set = atw_key_set; 817 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 818 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 819 820 /* possibly we should fill in our own sc_send_prresp, since 821 * the ADM8211 is probably sending probe responses in ad hoc 822 * mode. 823 */ 824 825 /* complete initialization */ 826 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 827 callout_init(&sc->sc_scan_ch, 0); 828 829 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 830 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 831 832 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 833 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 834 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 835 836 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 837 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 838 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 839 840 ieee80211_announce(ic); 841 return; 842 843 /* 844 * Free any resources we've allocated during the failed attach 845 * attempt. Do this in reverse order and fall through. 846 */ 847 fail_5: 848 for (i = 0; i < ATW_NRXDESC; i++) { 849 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 850 continue; 851 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 852 } 853 fail_4: 854 for (i = 0; i < ATW_TXQUEUELEN; i++) { 855 if (sc->sc_txsoft[i].txs_dmamap == NULL) 856 continue; 857 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 858 } 859 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 860 fail_3: 861 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 862 fail_2: 863 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 864 sizeof(struct atw_control_data)); 865 fail_1: 866 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 867 fail_0: 868 if (sc->sc_soft_ih != NULL) { 869 softint_disestablish(sc->sc_soft_ih); 870 sc->sc_soft_ih = NULL; 871 } 872 } 873 874 static struct ieee80211_node * 875 atw_node_alloc(struct ieee80211_node_table *nt) 876 { 877 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 878 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 879 880 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 881 return ni; 882 } 883 884 static void 885 atw_node_free(struct ieee80211_node *ni) 886 { 887 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 888 889 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 890 ether_sprintf(ni->ni_bssid))); 891 (*sc->sc_node_free)(ni); 892 } 893 894 895 static void 896 atw_test1_reset(struct atw_softc *sc) 897 { 898 switch (sc->sc_rev) { 899 case ATW_REVISION_BA: 900 if (1 /* XXX condition on transceiver type */) { 901 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 902 } 903 break; 904 case ATW_REVISION_CA: 905 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 906 break; 907 default: 908 break; 909 } 910 } 911 912 /* 913 * atw_reset: 914 * 915 * Perform a soft reset on the ADM8211. 916 */ 917 void 918 atw_reset(struct atw_softc *sc) 919 { 920 int i; 921 uint32_t lpc __atwdebugused; 922 923 ATW_WRITE(sc, ATW_NAR, 0x0); 924 DELAY(atw_nar_delay); 925 926 /* Reference driver has a cryptic remark indicating that this might 927 * power-on the chip. I know that it turns off power-saving.... 928 */ 929 ATW_WRITE(sc, ATW_FRCTL, 0x0); 930 931 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 932 933 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 934 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 935 break; 936 DELAY(atw_pseudo_milli); 937 } 938 939 /* ... and then pause 100ms longer for good measure. */ 940 DELAY(atw_magic_delay1); 941 942 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 943 944 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 945 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 946 947 /* 948 * Initialize the PCI Access Register. 949 */ 950 sc->sc_busmode = ATW_PAR_PBL_8DW; 951 952 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 953 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 954 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 955 956 atw_test1_reset(sc); 957 958 /* Turn off maximum power saving, etc. */ 959 ATW_WRITE(sc, ATW_FRCTL, 0x0); 960 961 DELAY(atw_magic_delay2); 962 963 /* Recall EEPROM. */ 964 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 965 966 DELAY(atw_magic_delay4); 967 968 lpc = ATW_READ(sc, ATW_LPC); 969 970 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 971 972 /* A reset seems to affect the SRAM contents, so put them into 973 * a known state. 974 */ 975 atw_clear_sram(sc); 976 977 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 978 } 979 980 static void 981 atw_clear_sram(struct atw_softc *sc) 982 { 983 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 984 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 985 /* XXX not for revision 0x20. */ 986 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 987 } 988 989 /* TBD atw_init 990 * 991 * set MAC based on ic->ic_bss->myaddr 992 * write WEP keys 993 * set TX rate 994 */ 995 996 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 997 * without receiving a beacon with the preferred BSSID & SSID. 998 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 999 */ 1000 static void 1001 atw_wcsr_init(struct atw_softc *sc) 1002 { 1003 uint32_t wcsr; 1004 1005 wcsr = ATW_READ(sc, ATW_WCSR); 1006 wcsr &= ~ATW_WCSR_BLN_MASK; 1007 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1008 /* We always want to wake up on link loss or TSFT out of range */ 1009 wcsr |= ATW_WCSR_LSOE|ATW_WCSR_TSFTWE; 1010 ATW_WRITE(sc, ATW_WCSR, wcsr); 1011 1012 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1013 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1014 } 1015 1016 /* Turn off power management. Set Rx store-and-forward mode. */ 1017 static void 1018 atw_cmdr_init(struct atw_softc *sc) 1019 { 1020 uint32_t cmdr; 1021 cmdr = ATW_READ(sc, ATW_CMDR); 1022 cmdr &= ~ATW_CMDR_APM; 1023 cmdr |= ATW_CMDR_RTE; 1024 cmdr &= ~ATW_CMDR_DRT_MASK; 1025 cmdr |= ATW_CMDR_DRT_SF; 1026 1027 ATW_WRITE(sc, ATW_CMDR, cmdr); 1028 } 1029 1030 static void 1031 atw_tofs2_init(struct atw_softc *sc) 1032 { 1033 uint32_t tofs2; 1034 /* XXX this magic can probably be figured out from the RFMD docs */ 1035 #ifndef ATW_REFSLAVE 1036 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1037 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1038 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1039 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1040 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1041 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1042 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1043 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1044 #else 1045 /* XXX new magic from reference driver source */ 1046 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1047 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1048 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1049 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1050 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1051 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1052 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1053 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1054 #endif 1055 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1056 } 1057 1058 static void 1059 atw_nar_init(struct atw_softc *sc) 1060 { 1061 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1062 } 1063 1064 static void 1065 atw_txlmt_init(struct atw_softc *sc) 1066 { 1067 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1068 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1069 } 1070 1071 static void 1072 atw_test1_init(struct atw_softc *sc) 1073 { 1074 uint32_t test1; 1075 1076 test1 = ATW_READ(sc, ATW_TEST1); 1077 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1078 /* XXX magic 0x1 */ 1079 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1080 ATW_WRITE(sc, ATW_TEST1, test1); 1081 } 1082 1083 static void 1084 atw_rf_reset(struct atw_softc *sc) 1085 { 1086 /* XXX this resets an Intersil RF front-end? */ 1087 /* TBD condition on Intersil RFType? */ 1088 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1089 DELAY(atw_rf_delay1); 1090 ATW_WRITE(sc, ATW_SYNRF, 0); 1091 DELAY(atw_rf_delay2); 1092 } 1093 1094 /* Set 16 TU max duration for the contention-free period (CFP). */ 1095 static void 1096 atw_cfp_init(struct atw_softc *sc) 1097 { 1098 uint32_t cfpp; 1099 1100 cfpp = ATW_READ(sc, ATW_CFPP); 1101 cfpp &= ~ATW_CFPP_CFPMD; 1102 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1103 ATW_WRITE(sc, ATW_CFPP, cfpp); 1104 } 1105 1106 static void 1107 atw_tofs0_init(struct atw_softc *sc) 1108 { 1109 /* XXX I guess that the Cardbus clock is 22 MHz? 1110 * I am assuming that the role of ATW_TOFS0_USCNT is 1111 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1112 * very clear on this point. It says in the datasheet that it is 1113 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1114 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1115 * these values. These values are also the power-on default. 1116 */ 1117 ATW_WRITE(sc, ATW_TOFS0, 1118 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1119 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1120 } 1121 1122 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1123 static void 1124 atw_ifs_init(struct atw_softc *sc) 1125 { 1126 uint32_t ifst; 1127 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1128 * Go figure. 1129 */ 1130 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1131 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1132 ATW_IFST_SIFS_MASK) | 1133 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1134 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1135 1136 ATW_WRITE(sc, ATW_IFST, ifst); 1137 } 1138 1139 static void 1140 atw_response_times_init(struct atw_softc *sc) 1141 { 1142 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1143 * indicate that the MAC expects at least SIFS + MIRT microseconds 1144 * to pass after it transmits a frame that requires a response; 1145 * it waits at most SIFS + MART microseconds for the response. 1146 * Surely this is not the ACK timeout? 1147 */ 1148 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1149 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1150 } 1151 1152 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1153 * engines read and write baseband registers after Rx and before 1154 * Tx, respectively. 1155 */ 1156 static void 1157 atw_bbp_io_init(struct atw_softc *sc) 1158 { 1159 uint32_t mmiraddr2; 1160 1161 /* XXX The reference driver does this, but is it *really* 1162 * necessary? 1163 */ 1164 switch (sc->sc_rev) { 1165 case ATW_REVISION_AB: 1166 case ATW_REVISION_AF: 1167 mmiraddr2 = 0x0; 1168 break; 1169 default: 1170 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1171 mmiraddr2 &= 1172 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1173 break; 1174 } 1175 1176 switch (sc->sc_bbptype) { 1177 case ATW_BBPTYPE_INTERSIL: 1178 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1179 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1180 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1181 break; 1182 case ATW_BBPTYPE_MARVEL: 1183 /* TBD find out the Marvel settings. */ 1184 break; 1185 case ATW_BBPTYPE_RFMD: 1186 default: 1187 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1188 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1189 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1190 break; 1191 } 1192 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1193 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1194 } 1195 1196 /* 1197 * atw_init: [ ifnet interface function ] 1198 * 1199 * Initialize the interface. Must be called at splnet(). 1200 */ 1201 int 1202 atw_init(struct ifnet *ifp) 1203 { 1204 struct atw_softc *sc = ifp->if_softc; 1205 struct ieee80211com *ic = &sc->sc_ic; 1206 struct atw_txsoft *txs; 1207 struct atw_rxsoft *rxs; 1208 int i, error = 0; 1209 1210 if (device_is_active(sc->sc_dev)) { 1211 /* 1212 * Cancel any pending I/O. 1213 */ 1214 atw_stop(ifp, 0); 1215 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1216 !device_is_active(sc->sc_dev)) 1217 return 0; 1218 1219 /* 1220 * Reset the chip to a known state. 1221 */ 1222 atw_reset(sc); 1223 1224 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1225 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1226 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1227 1228 atw_wcsr_init(sc); 1229 1230 atw_cmdr_init(sc); 1231 1232 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1233 * 1234 * XXX Set transmit power for ATIM, RTS, Beacon. 1235 */ 1236 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1237 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1238 1239 atw_tofs2_init(sc); 1240 1241 atw_nar_init(sc); 1242 1243 atw_txlmt_init(sc); 1244 1245 atw_test1_init(sc); 1246 1247 atw_rf_reset(sc); 1248 1249 atw_cfp_init(sc); 1250 1251 atw_tofs0_init(sc); 1252 1253 atw_ifs_init(sc); 1254 1255 /* XXX Fall asleep after one second of inactivity. 1256 * XXX A frame may only dribble in for 65536us. 1257 */ 1258 ATW_WRITE(sc, ATW_RMD, 1259 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1260 1261 atw_response_times_init(sc); 1262 1263 atw_bbp_io_init(sc); 1264 1265 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1266 1267 if ((error = atw_rf3000_init(sc)) != 0) 1268 goto out; 1269 1270 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1271 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1272 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1273 1274 /* 1275 * Initialize the transmit descriptor ring. 1276 */ 1277 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1278 for (i = 0; i < ATW_NTXDESC; i++) { 1279 sc->sc_txdescs[i].at_ctl = 0; 1280 /* no transmit chaining */ 1281 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1282 sc->sc_txdescs[i].at_buf2 = 1283 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1284 } 1285 /* use ring mode */ 1286 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1287 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1288 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1289 sc->sc_txfree = ATW_NTXDESC; 1290 sc->sc_txnext = 0; 1291 1292 /* 1293 * Initialize the transmit job descriptors. 1294 */ 1295 SIMPLEQ_INIT(&sc->sc_txfreeq); 1296 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1297 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1298 txs = &sc->sc_txsoft[i]; 1299 txs->txs_mbuf = NULL; 1300 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1301 } 1302 1303 /* 1304 * Initialize the receive descriptor and receive job 1305 * descriptor rings. 1306 */ 1307 for (i = 0; i < ATW_NRXDESC; i++) { 1308 rxs = &sc->sc_rxsoft[i]; 1309 if (rxs->rxs_mbuf == NULL) { 1310 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1311 aprint_error_dev(sc->sc_dev, 1312 "unable to allocate or map rx buffer %d, " 1313 "error = %d\n", i, error); 1314 /* 1315 * XXX Should attempt to run with fewer receive 1316 * XXX buffers instead of just failing. 1317 */ 1318 atw_rxdrain(sc); 1319 goto out; 1320 } 1321 } else 1322 atw_init_rxdesc(sc, i); 1323 } 1324 sc->sc_rxptr = 0; 1325 1326 /* 1327 * Initialize the interrupt mask and enable interrupts. 1328 */ 1329 /* normal interrupts */ 1330 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1331 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1332 1333 /* abnormal interrupts */ 1334 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1335 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1336 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1337 1338 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1339 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1340 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1341 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1342 ATW_INTR_TRT; 1343 1344 sc->sc_linkint_mask &= sc->sc_inten; 1345 sc->sc_rxint_mask &= sc->sc_inten; 1346 sc->sc_txint_mask &= sc->sc_inten; 1347 1348 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1349 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1350 1351 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1352 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1353 1354 /* 1355 * Give the transmit and receive rings to the ADM8211. 1356 */ 1357 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1358 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1359 1360 sc->sc_txthresh = 0; 1361 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1362 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1363 1364 /* common 802.11 configuration */ 1365 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1366 switch (ic->ic_opmode) { 1367 case IEEE80211_M_STA: 1368 break; 1369 case IEEE80211_M_AHDEMO: /* XXX */ 1370 case IEEE80211_M_IBSS: 1371 ic->ic_flags |= IEEE80211_F_IBSSON; 1372 /*FALLTHROUGH*/ 1373 case IEEE80211_M_HOSTAP: /* XXX */ 1374 break; 1375 case IEEE80211_M_MONITOR: /* XXX */ 1376 break; 1377 } 1378 1379 switch (ic->ic_opmode) { 1380 case IEEE80211_M_AHDEMO: 1381 case IEEE80211_M_HOSTAP: 1382 #ifndef IEEE80211_NO_HOSTAP 1383 ic->ic_bss->ni_intval = ic->ic_lintval; 1384 ic->ic_bss->ni_rssi = 0; 1385 ic->ic_bss->ni_rstamp = 0; 1386 #endif /* !IEEE80211_NO_HOSTAP */ 1387 break; 1388 default: /* XXX */ 1389 break; 1390 } 1391 1392 sc->sc_wepctl = 0; 1393 1394 atw_write_ssid(sc); 1395 atw_write_sup_rates(sc); 1396 atw_write_wep(sc); 1397 1398 ic->ic_state = IEEE80211_S_INIT; 1399 1400 /* 1401 * Set the receive filter. This will start the transmit and 1402 * receive processes. 1403 */ 1404 atw_filter_setup(sc); 1405 1406 /* 1407 * Start the receive process. 1408 */ 1409 ATW_WRITE(sc, ATW_RDR, 0x1); 1410 1411 /* 1412 * Note that the interface is now running. 1413 */ 1414 ifp->if_flags |= IFF_RUNNING; 1415 1416 /* send no beacons, yet. */ 1417 atw_start_beacon(sc, 0); 1418 1419 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1420 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1421 else 1422 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1423 out: 1424 if (error) { 1425 ifp->if_flags &= ~IFF_RUNNING; 1426 sc->sc_tx_timer = 0; 1427 ifp->if_timer = 0; 1428 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1429 } 1430 #ifdef ATW_DEBUG 1431 atw_print_regs(sc, "end of init"); 1432 #endif /* ATW_DEBUG */ 1433 1434 return (error); 1435 } 1436 1437 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1438 * 0: MAC control of RF3000/Si4126. 1439 * 1440 * Applies power, or selects RF front-end? Sets reset condition. 1441 * 1442 * TBD support non-RFMD BBP, non-SiLabs synth. 1443 */ 1444 static void 1445 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1446 { 1447 if (enable) { 1448 ATW_WRITE(sc, ATW_SYNRF, 1449 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1450 DELAY(atw_bbp_io_enable_delay); 1451 } else { 1452 ATW_WRITE(sc, ATW_SYNRF, 0); 1453 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1454 } 1455 } 1456 1457 static int 1458 atw_tune(struct atw_softc *sc) 1459 { 1460 int rc; 1461 u_int chan; 1462 struct ieee80211com *ic = &sc->sc_ic; 1463 1464 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1465 if (chan == IEEE80211_CHAN_ANY) 1466 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1467 1468 if (chan == sc->sc_cur_chan) 1469 return 0; 1470 1471 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1472 sc->sc_cur_chan, chan)); 1473 1474 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1475 1476 atw_si4126_tune(sc, chan); 1477 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1478 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1479 chan); 1480 1481 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1482 DELAY(atw_nar_delay); 1483 ATW_WRITE(sc, ATW_RDR, 0x1); 1484 1485 if (rc == 0) { 1486 sc->sc_cur_chan = chan; 1487 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1488 htole16(ic->ic_curchan->ic_freq); 1489 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1490 htole16(ic->ic_curchan->ic_flags); 1491 } 1492 1493 return rc; 1494 } 1495 1496 #ifdef ATW_SYNDEBUG 1497 static void 1498 atw_si4126_print(struct atw_softc *sc) 1499 { 1500 struct ifnet *ifp = &sc->sc_if; 1501 u_int addr, val; 1502 1503 val = 0; 1504 1505 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1506 return; 1507 1508 for (addr = 0; addr <= 8; addr++) { 1509 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1510 if (atw_si4126_read(sc, addr, &val) == 0) { 1511 printf("<unknown> (quitting print-out)\n"); 1512 break; 1513 } 1514 printf("%05x\n", val); 1515 } 1516 } 1517 #endif /* ATW_SYNDEBUG */ 1518 1519 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1520 * 1521 * The RF/IF synthesizer produces two reference frequencies for 1522 * the RF2948B transceiver. The first frequency the RF2948B requires 1523 * is two times the so-called "intermediate frequency" (IF). Since 1524 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1525 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1526 * frequency required by the transceiver is the radio frequency 1527 * (RF). This is a superheterodyne transceiver; for f(chan) the 1528 * center frequency of the channel we are tuning, RF = f(chan) - 1529 * IF. 1530 * 1531 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1532 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1533 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1534 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1535 */ 1536 static void 1537 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1538 { 1539 u_int mhz; 1540 u_int R; 1541 u_int32_t gpio; 1542 u_int16_t gain; 1543 1544 #ifdef ATW_SYNDEBUG 1545 atw_si4126_print(sc); 1546 #endif /* ATW_SYNDEBUG */ 1547 1548 if (chan == 14) 1549 mhz = 2484; 1550 else 1551 mhz = 2412 + 5 * (chan - 1); 1552 1553 /* Tune IF to 748 MHz to suit the IF LO input of the 1554 * RF2494B, which is 2 x IF. No need to set an IF divider 1555 * because an IF in 526 MHz - 952 MHz is allowed. 1556 * 1557 * XIN is 44.000 MHz, so divide it by two to get allowable 1558 * range of 2-25 MHz. SiLabs tells me that this is not 1559 * strictly necessary. 1560 */ 1561 1562 if (atw_xindiv2) 1563 R = 44; 1564 else 1565 R = 88; 1566 1567 /* Power-up RF, IF synthesizers. */ 1568 atw_si4126_write(sc, SI4126_POWER, 1569 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1570 1571 /* set LPWR, too? */ 1572 atw_si4126_write(sc, SI4126_MAIN, 1573 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1574 1575 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1576 * set KP2 to 1. 1577 * 1578 * REFDIF This is different from the reference driver, which 1579 * always sets SI4126_GAIN to 0. 1580 */ 1581 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1582 1583 atw_si4126_write(sc, SI4126_GAIN, gain); 1584 1585 /* XIN = 44 MHz. 1586 * 1587 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1588 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1589 * 1590 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1591 * so that 1496/88 * 44 MHz = 748 MHz. 1592 */ 1593 atw_si4126_write(sc, SI4126_IFN, 1496); 1594 1595 atw_si4126_write(sc, SI4126_IFR, R); 1596 1597 #ifndef ATW_REFSLAVE 1598 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1599 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1600 * which has no RF1! 1601 */ 1602 atw_si4126_write(sc, SI4126_RF1R, R); 1603 1604 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1605 #endif 1606 1607 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1608 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1609 * Now let's multiply it to mhz. So mhz - IF = N. 1610 */ 1611 atw_si4126_write(sc, SI4126_RF2R, R); 1612 1613 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1614 1615 /* wait 100us from power-up for RF, IF to settle */ 1616 DELAY(100); 1617 1618 gpio = ATW_READ(sc, ATW_GPIO); 1619 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1620 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1621 1622 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1623 /* Set a Prism RF front-end to a special mode for channel 14? 1624 * 1625 * Apparently the SMC2635W needs this, although I don't think 1626 * it has a Prism RF. 1627 */ 1628 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1629 } 1630 ATW_WRITE(sc, ATW_GPIO, gpio); 1631 1632 #ifdef ATW_SYNDEBUG 1633 atw_si4126_print(sc); 1634 #endif /* ATW_SYNDEBUG */ 1635 } 1636 1637 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1638 * diversity. 1639 * 1640 * !!! 1641 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1642 * !!! 1643 */ 1644 static int 1645 atw_rf3000_init(struct atw_softc *sc) 1646 { 1647 int rc = 0; 1648 1649 atw_bbp_io_enable(sc, 1); 1650 1651 /* CCA is acquisition sensitive */ 1652 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1653 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1654 1655 if (rc != 0) 1656 goto out; 1657 1658 /* enable diversity */ 1659 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1660 1661 if (rc != 0) 1662 goto out; 1663 1664 /* sensible setting from a binary-only driver */ 1665 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1666 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1667 1668 if (rc != 0) 1669 goto out; 1670 1671 /* magic from a binary-only driver */ 1672 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1673 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1674 1675 if (rc != 0) 1676 goto out; 1677 1678 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1679 1680 if (rc != 0) 1681 goto out; 1682 1683 /* XXX Reference driver remarks that Abocom sets this to 50. 1684 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1685 * in the "reserved" area of register RF3000_OPTIONS1. 1686 */ 1687 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1688 1689 if (rc != 0) 1690 goto out; 1691 1692 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 out: 1698 atw_bbp_io_enable(sc, 0); 1699 return rc; 1700 } 1701 1702 #ifdef ATW_BBPDEBUG 1703 static void 1704 atw_rf3000_print(struct atw_softc *sc) 1705 { 1706 struct ifnet *ifp = &sc->sc_if; 1707 u_int addr, val; 1708 1709 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1710 return; 1711 1712 for (addr = 0x01; addr <= 0x15; addr++) { 1713 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1714 if (atw_rf3000_read(sc, addr, &val) != 0) { 1715 printf("<unknown> (quitting print-out)\n"); 1716 break; 1717 } 1718 printf("%08x\n", val); 1719 } 1720 } 1721 #endif /* ATW_BBPDEBUG */ 1722 1723 /* Set the power settings on the BBP for channel `chan'. */ 1724 static int 1725 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1726 { 1727 int rc = 0; 1728 u_int32_t reg; 1729 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1730 1731 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1732 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1733 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1734 1735 /* odd channels: LSB, even channels: MSB */ 1736 if (chan % 2 == 1) { 1737 txpower &= 0xFF; 1738 lpf_cutoff &= 0xFF; 1739 lna_gs_thresh &= 0xFF; 1740 } else { 1741 txpower >>= 8; 1742 lpf_cutoff >>= 8; 1743 lna_gs_thresh >>= 8; 1744 } 1745 1746 #ifdef ATW_BBPDEBUG 1747 atw_rf3000_print(sc); 1748 #endif /* ATW_BBPDEBUG */ 1749 1750 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1751 "lna_gs_thresh %02x\n", 1752 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1753 1754 atw_bbp_io_enable(sc, 1); 1755 1756 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1757 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1758 goto out; 1759 1760 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1761 goto out; 1762 1763 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1764 goto out; 1765 1766 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1767 1768 if (rc != 0) 1769 goto out; 1770 1771 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1772 1773 if (rc != 0) 1774 goto out; 1775 1776 #ifdef ATW_BBPDEBUG 1777 atw_rf3000_print(sc); 1778 #endif /* ATW_BBPDEBUG */ 1779 1780 out: 1781 atw_bbp_io_enable(sc, 0); 1782 1783 /* set beacon, rts, atim transmit power */ 1784 reg = ATW_READ(sc, ATW_PLCPHD); 1785 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1786 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1787 ATW_PLCPHD_SERVICE_MASK); 1788 ATW_WRITE(sc, ATW_PLCPHD, reg); 1789 DELAY(atw_plcphd_delay); 1790 1791 return rc; 1792 } 1793 1794 /* Write a register on the RF3000 baseband processor using the 1795 * registers provided by the ADM8211 for this purpose. 1796 * 1797 * Return 0 on success. 1798 */ 1799 static int 1800 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1801 { 1802 u_int32_t reg; 1803 int i; 1804 1805 reg = sc->sc_bbpctl_wr | 1806 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1807 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1808 1809 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1810 ATW_WRITE(sc, ATW_BBPCTL, reg); 1811 DELAY(2 * atw_pseudo_milli); 1812 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1813 break; 1814 } 1815 1816 if (i < 0) { 1817 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1818 return ETIMEDOUT; 1819 } 1820 return 0; 1821 } 1822 1823 /* Read a register on the RF3000 baseband processor using the registers 1824 * the ADM8211 provides for this purpose. 1825 * 1826 * The 7-bit register address is addr. Record the 8-bit data in the register 1827 * in *val. 1828 * 1829 * Return 0 on success. 1830 * 1831 * XXX This does not seem to work. The ADM8211 must require more or 1832 * different magic to read the chip than to write it. Possibly some 1833 * of the magic I have derived from a binary-only driver concerns 1834 * the "chip address" (see the RF3000 manual). 1835 */ 1836 #ifdef ATW_BBPDEBUG 1837 static int 1838 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1839 { 1840 u_int32_t reg; 1841 int i; 1842 1843 for (i = 1000; --i >= 0; ) { 1844 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1845 break; 1846 DELAY(100); 1847 } 1848 1849 if (i < 0) { 1850 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1851 device_xname(sc->sc_dev)); 1852 return ETIMEDOUT; 1853 } 1854 1855 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1856 1857 ATW_WRITE(sc, ATW_BBPCTL, reg); 1858 1859 for (i = 1000; --i >= 0; ) { 1860 DELAY(100); 1861 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1862 break; 1863 } 1864 1865 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1866 1867 if (i < 0) { 1868 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1869 device_xname(sc->sc_dev), reg); 1870 return ETIMEDOUT; 1871 } 1872 if (val != NULL) 1873 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1874 return 0; 1875 } 1876 #endif /* ATW_BBPDEBUG */ 1877 1878 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1879 * provided by the ADM8211 for that purpose. 1880 * 1881 * val is 18 bits of data, and val is the 4-bit address of the register. 1882 * 1883 * Return 0 on success. 1884 */ 1885 static void 1886 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1887 { 1888 uint32_t bits, mask, reg; 1889 const int nbits = 22; 1890 1891 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1892 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1893 1894 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1895 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1896 1897 reg = ATW_SYNRF_SELSYN; 1898 /* reference driver: reset Si4126 serial bus to initial 1899 * conditions? 1900 */ 1901 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1902 ATW_WRITE(sc, ATW_SYNRF, reg); 1903 1904 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1905 if ((bits & mask) != 0) 1906 reg |= ATW_SYNRF_SYNDATA; 1907 else 1908 reg &= ~ATW_SYNRF_SYNDATA; 1909 ATW_WRITE(sc, ATW_SYNRF, reg); 1910 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1911 ATW_WRITE(sc, ATW_SYNRF, reg); 1912 } 1913 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1914 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1915 } 1916 1917 /* Read 18-bit data from the 4-bit address addr in Si4126 1918 * RF synthesizer and write the data to *val. Return 0 on success. 1919 * 1920 * XXX This does not seem to work. The ADM8211 must require more or 1921 * different magic to read the chip than to write it. 1922 */ 1923 #ifdef ATW_SYNDEBUG 1924 static int 1925 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1926 { 1927 u_int32_t reg; 1928 int i; 1929 1930 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1931 1932 for (i = 1000; --i >= 0; ) { 1933 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1934 break; 1935 DELAY(100); 1936 } 1937 1938 if (i < 0) { 1939 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1940 device_xname(sc->sc_dev)); 1941 return ETIMEDOUT; 1942 } 1943 1944 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1945 1946 ATW_WRITE(sc, ATW_SYNCTL, reg); 1947 1948 for (i = 1000; --i >= 0; ) { 1949 DELAY(100); 1950 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1951 break; 1952 } 1953 1954 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1955 1956 if (i < 0) { 1957 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1958 device_xname(sc->sc_dev), reg); 1959 return ETIMEDOUT; 1960 } 1961 if (val != NULL) 1962 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1963 ATW_SYNCTL_DATA_MASK); 1964 return 0; 1965 } 1966 #endif /* ATW_SYNDEBUG */ 1967 1968 /* XXX is the endianness correct? test. */ 1969 #define atw_calchash(addr) \ 1970 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1971 1972 /* 1973 * atw_filter_setup: 1974 * 1975 * Set the ADM8211's receive filter. 1976 */ 1977 static void 1978 atw_filter_setup(struct atw_softc *sc) 1979 { 1980 struct ieee80211com *ic = &sc->sc_ic; 1981 struct ethercom *ec = &sc->sc_ec; 1982 struct ifnet *ifp = &sc->sc_if; 1983 int hash; 1984 u_int32_t hashes[2]; 1985 struct ether_multi *enm; 1986 struct ether_multistep step; 1987 1988 /* According to comments in tlp_al981_filter_setup 1989 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1990 * multicast filter to be set while it is running. Hopefully 1991 * the ADM8211 is not the same! 1992 */ 1993 if ((ifp->if_flags & IFF_RUNNING) != 0) 1994 atw_idle(sc, ATW_NAR_SR); 1995 1996 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 1997 ifp->if_flags &= ~IFF_ALLMULTI; 1998 1999 /* XXX in scan mode, do not filter packets. Maybe this is 2000 * unnecessary. 2001 */ 2002 if (ic->ic_state == IEEE80211_S_SCAN || 2003 (ifp->if_flags & IFF_PROMISC) != 0) { 2004 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2005 goto allmulti; 2006 } 2007 2008 hashes[0] = hashes[1] = 0x0; 2009 2010 /* 2011 * Program the 64-bit multicast hash filter. 2012 */ 2013 ETHER_FIRST_MULTI(step, ec, enm); 2014 while (enm != NULL) { 2015 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2016 ETHER_ADDR_LEN) != 0) 2017 goto allmulti; 2018 2019 hash = atw_calchash(enm->enm_addrlo); 2020 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2021 ETHER_NEXT_MULTI(step, enm); 2022 sc->sc_opmode |= ATW_NAR_MM; 2023 } 2024 ifp->if_flags &= ~IFF_ALLMULTI; 2025 goto setit; 2026 2027 allmulti: 2028 sc->sc_opmode |= ATW_NAR_MM; 2029 ifp->if_flags |= IFF_ALLMULTI; 2030 hashes[0] = hashes[1] = 0xffffffff; 2031 2032 setit: 2033 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2034 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2035 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2036 DELAY(atw_nar_delay); 2037 ATW_WRITE(sc, ATW_RDR, 0x1); 2038 2039 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2040 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2041 } 2042 2043 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2044 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2045 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2046 * no beacon with the preferred BSSID and SSID in the number of 2047 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2048 */ 2049 static void 2050 atw_write_bssid(struct atw_softc *sc) 2051 { 2052 struct ieee80211com *ic = &sc->sc_ic; 2053 u_int8_t *bssid; 2054 2055 bssid = ic->ic_bss->ni_bssid; 2056 2057 ATW_WRITE(sc, ATW_BSSID0, 2058 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2059 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2060 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2061 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2062 2063 ATW_WRITE(sc, ATW_ABDA1, 2064 (ATW_READ(sc, ATW_ABDA1) & 2065 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2066 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2067 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2068 2069 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2070 ether_sprintf(sc->sc_bssid))); 2071 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2072 2073 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2074 } 2075 2076 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2077 * 16-bit word. 2078 */ 2079 static void 2080 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2081 { 2082 u_int i; 2083 u_int8_t *ptr; 2084 2085 memcpy(&sc->sc_sram[ofs], buf, buflen); 2086 2087 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2088 2089 KASSERT(buflen + ofs <= sc->sc_sramlen); 2090 2091 ptr = &sc->sc_sram[ofs]; 2092 2093 for (i = 0; i < buflen; i += 2) { 2094 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2095 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2096 DELAY(atw_writewep_delay); 2097 2098 ATW_WRITE(sc, ATW_WESK, 2099 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2100 DELAY(atw_writewep_delay); 2101 } 2102 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2103 2104 if (sc->sc_if.if_flags & IFF_DEBUG) { 2105 int n_octets = 0; 2106 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2107 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2108 for (i = 0; i < buflen; i++) { 2109 printf(" %02x", ptr[i]); 2110 if (++n_octets % 24 == 0) 2111 printf("\n"); 2112 } 2113 if (n_octets % 24 != 0) 2114 printf("\n"); 2115 } 2116 } 2117 2118 static int 2119 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2120 { 2121 struct atw_softc *sc = ic->ic_ifp->if_softc; 2122 u_int keyix = k->wk_keyix; 2123 2124 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2125 2126 if (keyix >= IEEE80211_WEP_NKID) 2127 return 0; 2128 if (k->wk_keylen != 0) 2129 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2130 2131 return 1; 2132 } 2133 2134 static int 2135 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2136 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2137 { 2138 struct atw_softc *sc = ic->ic_ifp->if_softc; 2139 2140 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2141 2142 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2143 return 0; 2144 2145 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2146 2147 return 1; 2148 } 2149 2150 static void 2151 atw_key_update_begin(struct ieee80211com *ic) 2152 { 2153 #ifdef ATW_DEBUG 2154 struct ifnet *ifp = ic->ic_ifp; 2155 struct atw_softc *sc = ifp->if_softc; 2156 #endif 2157 2158 DPRINTF(sc, ("%s:\n", __func__)); 2159 } 2160 2161 static void 2162 atw_key_update_end(struct ieee80211com *ic) 2163 { 2164 struct ifnet *ifp = ic->ic_ifp; 2165 struct atw_softc *sc = ifp->if_softc; 2166 2167 DPRINTF(sc, ("%s:\n", __func__)); 2168 2169 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2170 return; 2171 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2172 return; 2173 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2174 atw_write_wep(sc); 2175 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2176 DELAY(atw_nar_delay); 2177 ATW_WRITE(sc, ATW_RDR, 0x1); 2178 } 2179 2180 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2181 static void 2182 atw_write_wep(struct atw_softc *sc) 2183 { 2184 #if 0 2185 struct ieee80211com *ic = &sc->sc_ic; 2186 u_int32_t reg; 2187 int i; 2188 #endif 2189 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2190 u_int8_t buf[IEEE80211_WEP_NKID] 2191 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2192 2193 sc->sc_wepctl = 0; 2194 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2195 2196 memset(&buf[0][0], 0, sizeof(buf)); 2197 2198 #if 0 2199 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2200 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2201 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2202 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2203 buf[i][1] = ATW_WEP_ENABLED; 2204 } else { 2205 buf[i][1] = 0; 2206 continue; 2207 } 2208 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2209 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2210 ic->ic_nw_keys[i].wk_keylen - 1); 2211 } 2212 2213 reg = ATW_READ(sc, ATW_MACTEST); 2214 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2215 reg &= ~ATW_MACTEST_KEYID_MASK; 2216 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2217 ATW_WRITE(sc, ATW_MACTEST, reg); 2218 2219 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2220 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2221 2222 switch (sc->sc_rev) { 2223 case ATW_REVISION_AB: 2224 case ATW_REVISION_AF: 2225 /* Bypass WEP on Rx. */ 2226 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2227 break; 2228 default: 2229 break; 2230 } 2231 #endif 2232 2233 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2234 sizeof(buf)); 2235 2236 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2237 } 2238 2239 static void 2240 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2241 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2242 { 2243 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2244 2245 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2246 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2247 return; 2248 2249 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2250 2251 switch (subtype) { 2252 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2253 case IEEE80211_FC0_SUBTYPE_BEACON: 2254 if (ic->ic_opmode == IEEE80211_M_IBSS && 2255 ic->ic_state == IEEE80211_S_RUN) { 2256 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2257 (void)ieee80211_ibss_merge(ni); 2258 } 2259 break; 2260 default: 2261 break; 2262 } 2263 return; 2264 } 2265 2266 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2267 * In ad hoc mode, the SSID is written to the beacons sent by the 2268 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2269 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2270 * indications. 2271 */ 2272 static void 2273 atw_write_ssid(struct atw_softc *sc) 2274 { 2275 struct ieee80211com *ic = &sc->sc_ic; 2276 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2277 * it only expects the element length, not its ID. 2278 */ 2279 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2280 2281 memset(buf, 0, sizeof(buf)); 2282 buf[0] = ic->ic_bss->ni_esslen; 2283 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2284 2285 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2286 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2287 } 2288 2289 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2290 * In ad hoc mode, the supported rates are written to beacons sent by the 2291 * ADM8211. 2292 */ 2293 static void 2294 atw_write_sup_rates(struct atw_softc *sc) 2295 { 2296 struct ieee80211com *ic = &sc->sc_ic; 2297 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2298 * supported rates 2299 */ 2300 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2301 2302 memset(buf, 0, sizeof(buf)); 2303 2304 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2305 2306 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2307 ic->ic_bss->ni_rates.rs_nrates); 2308 2309 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2310 } 2311 2312 /* Start/stop sending beacons. */ 2313 void 2314 atw_start_beacon(struct atw_softc *sc, int start) 2315 { 2316 struct ieee80211com *ic = &sc->sc_ic; 2317 uint16_t chan; 2318 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2319 size_t len; 2320 2321 if (!device_is_active(sc->sc_dev)) 2322 return; 2323 2324 /* start beacons */ 2325 len = sizeof(struct ieee80211_frame) + 2326 8 /* timestamp */ + 2 /* beacon interval */ + 2327 2 /* capability info */ + 2328 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2329 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2330 3 /* DS parameters */ + 2331 IEEE80211_CRC_LEN; 2332 2333 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2334 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2335 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2336 2337 ATW_WRITE(sc, ATW_BCNT, bcnt); 2338 ATW_WRITE(sc, ATW_CAP1, cap1); 2339 2340 if (!start) 2341 return; 2342 2343 /* TBD use ni_capinfo */ 2344 2345 capinfo = 0; 2346 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2347 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2348 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2349 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2350 2351 switch (ic->ic_opmode) { 2352 case IEEE80211_M_IBSS: 2353 len += 4; /* IBSS parameters */ 2354 capinfo |= IEEE80211_CAPINFO_IBSS; 2355 break; 2356 case IEEE80211_M_HOSTAP: 2357 /* XXX 6-byte minimum TIM */ 2358 len += atw_beacon_len_adjust; 2359 capinfo |= IEEE80211_CAPINFO_ESS; 2360 break; 2361 default: 2362 return; 2363 } 2364 2365 /* set listen interval 2366 * XXX do software units agree w/ hardware? 2367 */ 2368 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2369 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2370 2371 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2372 2373 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2374 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2375 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2376 2377 ATW_WRITE(sc, ATW_BCNT, bcnt); 2378 ATW_WRITE(sc, ATW_BPLI, bpli); 2379 ATW_WRITE(sc, ATW_CAP0, cap0); 2380 ATW_WRITE(sc, ATW_CAP1, cap1); 2381 2382 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2383 device_xname(sc->sc_dev), bcnt)); 2384 2385 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2386 device_xname(sc->sc_dev), cap1)); 2387 } 2388 2389 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2390 static inline uint32_t 2391 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2392 { 2393 /* Following the reference driver's lead, I compute 2394 * 2395 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2396 * 2397 * without using 64-bit arithmetic, using the following 2398 * relationship: 2399 * 2400 * (0x100000000 * H + L) % m 2401 * = ((0x100000000 % m) * H + L) % m 2402 * = (((0xffffffff + 1) % m) * H + L) % m 2403 * = ((0xffffffff % m + 1 % m) * H + L) % m 2404 * = ((0xffffffff % m + 1) * H + L) % m 2405 */ 2406 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2407 } 2408 2409 static uint64_t 2410 atw_get_tsft(struct atw_softc *sc) 2411 { 2412 int i; 2413 uint32_t tsfth, tsftl; 2414 for (i = 0; i < 2; i++) { 2415 tsfth = ATW_READ(sc, ATW_TSFTH); 2416 tsftl = ATW_READ(sc, ATW_TSFTL); 2417 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2418 break; 2419 } 2420 return ((uint64_t)tsfth << 32) | tsftl; 2421 } 2422 2423 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2424 * the ieee80211com. 2425 * 2426 * Predict the next target beacon transmission time (TBTT) and 2427 * write it to the ADM8211. 2428 */ 2429 static void 2430 atw_predict_beacon(struct atw_softc *sc) 2431 { 2432 #define TBTTOFS 20 /* TU */ 2433 2434 struct ieee80211com *ic = &sc->sc_ic; 2435 uint64_t tsft; 2436 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2437 union { 2438 uint64_t word; 2439 uint8_t tstamp[8]; 2440 } u; 2441 2442 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2443 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2444 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2445 tsft = atw_get_tsft(sc); 2446 u.word = htole64(tsft); 2447 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2448 sizeof(ic->ic_bss->ni_tstamp)); 2449 } else 2450 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2451 2452 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2453 2454 tsftl = tsft & 0xFFFFFFFF; 2455 tsfth = tsft >> 32; 2456 2457 /* We sent/received the last beacon `past' microseconds 2458 * after the interval divided the TSF timer. 2459 */ 2460 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2461 2462 /* Skip ten beacons so that the TBTT cannot pass before 2463 * we've programmed it. Ten is an arbitrary number. 2464 */ 2465 tbtt = past_even + ival * 10; 2466 2467 ATW_WRITE(sc, ATW_TOFS1, 2468 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2469 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2470 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2471 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2472 #undef TBTTOFS 2473 } 2474 2475 static void 2476 atw_next_scan(void *arg) 2477 { 2478 struct atw_softc *sc = arg; 2479 struct ieee80211com *ic = &sc->sc_ic; 2480 int s; 2481 2482 /* don't call atw_start w/o network interrupts blocked */ 2483 s = splnet(); 2484 if (ic->ic_state == IEEE80211_S_SCAN) 2485 ieee80211_next_scan(ic); 2486 splx(s); 2487 } 2488 2489 /* Synchronize the hardware state with the software state. */ 2490 static int 2491 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2492 { 2493 struct ifnet *ifp = ic->ic_ifp; 2494 struct atw_softc *sc = ifp->if_softc; 2495 int error = 0; 2496 2497 callout_stop(&sc->sc_scan_ch); 2498 2499 switch (nstate) { 2500 case IEEE80211_S_AUTH: 2501 case IEEE80211_S_ASSOC: 2502 atw_write_bssid(sc); 2503 error = atw_tune(sc); 2504 break; 2505 case IEEE80211_S_INIT: 2506 callout_stop(&sc->sc_scan_ch); 2507 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2508 atw_start_beacon(sc, 0); 2509 break; 2510 case IEEE80211_S_SCAN: 2511 error = atw_tune(sc); 2512 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2513 atw_next_scan, sc); 2514 break; 2515 case IEEE80211_S_RUN: 2516 error = atw_tune(sc); 2517 atw_write_bssid(sc); 2518 atw_write_ssid(sc); 2519 atw_write_sup_rates(sc); 2520 2521 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2522 ic->ic_opmode == IEEE80211_M_MONITOR) 2523 break; 2524 2525 /* set listen interval 2526 * XXX do software units agree w/ hardware? 2527 */ 2528 ATW_WRITE(sc, ATW_BPLI, 2529 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2530 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2531 ATW_BPLI_LI_MASK)); 2532 2533 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2534 ATW_READ(sc, ATW_BPLI))); 2535 2536 atw_predict_beacon(sc); 2537 2538 switch (ic->ic_opmode) { 2539 case IEEE80211_M_AHDEMO: 2540 case IEEE80211_M_HOSTAP: 2541 case IEEE80211_M_IBSS: 2542 atw_start_beacon(sc, 1); 2543 break; 2544 case IEEE80211_M_MONITOR: 2545 case IEEE80211_M_STA: 2546 break; 2547 } 2548 2549 break; 2550 } 2551 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2552 } 2553 2554 /* 2555 * atw_add_rxbuf: 2556 * 2557 * Add a receive buffer to the indicated descriptor. 2558 */ 2559 int 2560 atw_add_rxbuf(struct atw_softc *sc, int idx) 2561 { 2562 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2563 struct mbuf *m; 2564 int error; 2565 2566 MGETHDR(m, M_DONTWAIT, MT_DATA); 2567 if (m == NULL) 2568 return (ENOBUFS); 2569 2570 MCLGET(m, M_DONTWAIT); 2571 if ((m->m_flags & M_EXT) == 0) { 2572 m_freem(m); 2573 return (ENOBUFS); 2574 } 2575 2576 if (rxs->rxs_mbuf != NULL) 2577 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2578 2579 rxs->rxs_mbuf = m; 2580 2581 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2582 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2583 BUS_DMA_READ|BUS_DMA_NOWAIT); 2584 if (error) { 2585 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2586 idx, error); 2587 panic("atw_add_rxbuf"); /* XXX */ 2588 } 2589 2590 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2591 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2592 2593 atw_init_rxdesc(sc, idx); 2594 2595 return (0); 2596 } 2597 2598 /* 2599 * Release any queued transmit buffers. 2600 */ 2601 void 2602 atw_txdrain(struct atw_softc *sc) 2603 { 2604 struct atw_txsoft *txs; 2605 2606 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2607 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2608 if (txs->txs_mbuf != NULL) { 2609 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2610 m_freem(txs->txs_mbuf); 2611 txs->txs_mbuf = NULL; 2612 } 2613 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2614 sc->sc_txfree += txs->txs_ndescs; 2615 } 2616 2617 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2618 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2619 sc->sc_txfree != ATW_NTXDESC)); 2620 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2621 sc->sc_tx_timer = 0; 2622 } 2623 2624 /* 2625 * atw_stop: [ ifnet interface function ] 2626 * 2627 * Stop transmission on the interface. 2628 */ 2629 void 2630 atw_stop(struct ifnet *ifp, int disable) 2631 { 2632 struct atw_softc *sc = ifp->if_softc; 2633 struct ieee80211com *ic = &sc->sc_ic; 2634 2635 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2636 2637 if (device_is_active(sc->sc_dev)) { 2638 /* Disable interrupts. */ 2639 ATW_WRITE(sc, ATW_IER, 0); 2640 2641 /* Stop the transmit and receive processes. */ 2642 ATW_WRITE(sc, ATW_NAR, 0); 2643 DELAY(atw_nar_delay); 2644 ATW_WRITE(sc, ATW_TDBD, 0); 2645 ATW_WRITE(sc, ATW_TDBP, 0); 2646 ATW_WRITE(sc, ATW_RDB, 0); 2647 } 2648 2649 sc->sc_opmode = 0; 2650 2651 atw_txdrain(sc); 2652 2653 /* 2654 * Mark the interface down and cancel the watchdog timer. 2655 */ 2656 ifp->if_flags &= ~IFF_RUNNING; 2657 ifp->if_timer = 0; 2658 2659 if (disable) 2660 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2661 } 2662 2663 /* 2664 * atw_rxdrain: 2665 * 2666 * Drain the receive queue. 2667 */ 2668 void 2669 atw_rxdrain(struct atw_softc *sc) 2670 { 2671 struct atw_rxsoft *rxs; 2672 int i; 2673 2674 for (i = 0; i < ATW_NRXDESC; i++) { 2675 rxs = &sc->sc_rxsoft[i]; 2676 if (rxs->rxs_mbuf == NULL) 2677 continue; 2678 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2679 m_freem(rxs->rxs_mbuf); 2680 rxs->rxs_mbuf = NULL; 2681 } 2682 } 2683 2684 /* 2685 * atw_detach: 2686 * 2687 * Detach an ADM8211 interface. 2688 */ 2689 int 2690 atw_detach(struct atw_softc *sc) 2691 { 2692 struct ifnet *ifp = &sc->sc_if; 2693 struct atw_rxsoft *rxs; 2694 struct atw_txsoft *txs; 2695 int i; 2696 2697 /* 2698 * Succeed now if there isn't any work to do. 2699 */ 2700 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2701 return (0); 2702 2703 pmf_device_deregister(sc->sc_dev); 2704 2705 callout_stop(&sc->sc_scan_ch); 2706 2707 ieee80211_ifdetach(&sc->sc_ic); 2708 if_detach(ifp); 2709 2710 for (i = 0; i < ATW_NRXDESC; i++) { 2711 rxs = &sc->sc_rxsoft[i]; 2712 if (rxs->rxs_mbuf != NULL) { 2713 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2714 m_freem(rxs->rxs_mbuf); 2715 rxs->rxs_mbuf = NULL; 2716 } 2717 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2718 } 2719 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2720 txs = &sc->sc_txsoft[i]; 2721 if (txs->txs_mbuf != NULL) { 2722 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2723 m_freem(txs->txs_mbuf); 2724 txs->txs_mbuf = NULL; 2725 } 2726 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2727 } 2728 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2729 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2730 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2731 sizeof(struct atw_control_data)); 2732 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2733 2734 if (sc->sc_srom) 2735 free(sc->sc_srom, M_DEVBUF); 2736 2737 atw_evcnt_detach(sc); 2738 2739 if (sc->sc_soft_ih != NULL) { 2740 softint_disestablish(sc->sc_soft_ih); 2741 sc->sc_soft_ih = NULL; 2742 } 2743 2744 return (0); 2745 } 2746 2747 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2748 bool 2749 atw_shutdown(device_t self, int flags) 2750 { 2751 struct atw_softc *sc = device_private(self); 2752 2753 atw_stop(&sc->sc_if, 1); 2754 return true; 2755 } 2756 2757 #if 0 2758 static void 2759 atw_workaround1(struct atw_softc *sc) 2760 { 2761 uint32_t test1; 2762 2763 test1 = ATW_READ(sc, ATW_TEST1); 2764 2765 sc->sc_misc_ev.ev_count++; 2766 2767 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2768 sc->sc_rxpkt1in_ev.ev_count++; 2769 return; 2770 } 2771 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2772 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2773 sc->sc_rxamatch_ev.ev_count++; 2774 return; 2775 } 2776 sc->sc_workaround1_ev.ev_count++; 2777 (void)atw_init(&sc->sc_if); 2778 } 2779 #endif 2780 2781 int 2782 atw_intr(void *arg) 2783 { 2784 struct atw_softc *sc = arg; 2785 struct ifnet *ifp = &sc->sc_if; 2786 uint32_t status; 2787 2788 #ifdef DEBUG 2789 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2790 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2791 #endif 2792 2793 /* 2794 * If the interface isn't running, the interrupt couldn't 2795 * possibly have come from us. 2796 */ 2797 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2798 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2799 return (0); 2800 2801 status = ATW_READ(sc, ATW_STSR); 2802 if (status == 0) 2803 return 0; 2804 2805 if ((status & sc->sc_inten) == 0) { 2806 ATW_WRITE(sc, ATW_STSR, status); 2807 return 0; 2808 } 2809 2810 /* Disable interrupts */ 2811 ATW_WRITE(sc, ATW_IER, 0); 2812 2813 softint_schedule(sc->sc_soft_ih); 2814 return 1; 2815 } 2816 2817 void 2818 atw_softintr(void *arg) 2819 { 2820 struct atw_softc *sc = arg; 2821 struct ifnet *ifp = &sc->sc_if; 2822 uint32_t status, rxstatus, txstatus, linkstatus; 2823 int txthresh, s; 2824 2825 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2826 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2827 return; 2828 2829 for (;;) { 2830 status = ATW_READ(sc, ATW_STSR); 2831 2832 if (status) 2833 ATW_WRITE(sc, ATW_STSR, status); 2834 2835 #ifdef ATW_DEBUG 2836 #define PRINTINTR(flag) do { \ 2837 if ((status & flag) != 0) { \ 2838 printf("%s" #flag, delim); \ 2839 delim = ","; \ 2840 } \ 2841 } while (0) 2842 2843 if (atw_debug > 1 && status) { 2844 const char *delim = "<"; 2845 2846 printf("%s: reg[STSR] = %x", 2847 device_xname(sc->sc_dev), status); 2848 2849 PRINTINTR(ATW_INTR_FBE); 2850 PRINTINTR(ATW_INTR_LINKOFF); 2851 PRINTINTR(ATW_INTR_LINKON); 2852 PRINTINTR(ATW_INTR_RCI); 2853 PRINTINTR(ATW_INTR_RDU); 2854 PRINTINTR(ATW_INTR_REIS); 2855 PRINTINTR(ATW_INTR_RPS); 2856 PRINTINTR(ATW_INTR_TCI); 2857 PRINTINTR(ATW_INTR_TDU); 2858 PRINTINTR(ATW_INTR_TLT); 2859 PRINTINTR(ATW_INTR_TPS); 2860 PRINTINTR(ATW_INTR_TRT); 2861 PRINTINTR(ATW_INTR_TUF); 2862 PRINTINTR(ATW_INTR_BCNTC); 2863 PRINTINTR(ATW_INTR_ATIME); 2864 PRINTINTR(ATW_INTR_TBTT); 2865 PRINTINTR(ATW_INTR_TSCZ); 2866 PRINTINTR(ATW_INTR_TSFTF); 2867 printf(">\n"); 2868 } 2869 #undef PRINTINTR 2870 #endif /* ATW_DEBUG */ 2871 2872 if ((status & sc->sc_inten) == 0) 2873 break; 2874 2875 rxstatus = status & sc->sc_rxint_mask; 2876 txstatus = status & sc->sc_txint_mask; 2877 linkstatus = status & sc->sc_linkint_mask; 2878 2879 if (linkstatus) { 2880 atw_linkintr(sc, linkstatus); 2881 } 2882 2883 if (rxstatus) { 2884 /* Grab any new packets. */ 2885 atw_rxintr(sc); 2886 2887 if (rxstatus & ATW_INTR_RDU) { 2888 printf("%s: receive ring overrun\n", 2889 device_xname(sc->sc_dev)); 2890 /* Get the receive process going again. */ 2891 ATW_WRITE(sc, ATW_RDR, 0x1); 2892 } 2893 } 2894 2895 if (txstatus) { 2896 /* Sweep up transmit descriptors. */ 2897 atw_txintr(sc, txstatus); 2898 2899 if (txstatus & ATW_INTR_TLT) { 2900 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2901 device_xname(sc->sc_dev))); 2902 (void)atw_init(&sc->sc_if); 2903 } 2904 2905 if (txstatus & ATW_INTR_TRT) { 2906 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2907 device_xname(sc->sc_dev))); 2908 } 2909 2910 /* If Tx under-run, increase our transmit threshold 2911 * if another is available. 2912 */ 2913 txthresh = sc->sc_txthresh + 1; 2914 if ((txstatus & ATW_INTR_TUF) && 2915 sc->sc_txth[txthresh].txth_name != NULL) { 2916 /* Idle the transmit process. */ 2917 atw_idle(sc, ATW_NAR_ST); 2918 2919 sc->sc_txthresh = txthresh; 2920 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2921 sc->sc_opmode |= 2922 sc->sc_txth[txthresh].txth_opmode; 2923 printf("%s: transmit underrun; new " 2924 "threshold: %s\n", device_xname(sc->sc_dev), 2925 sc->sc_txth[txthresh].txth_name); 2926 2927 /* Set the new threshold and restart 2928 * the transmit process. 2929 */ 2930 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2931 DELAY(atw_nar_delay); 2932 ATW_WRITE(sc, ATW_TDR, 0x1); 2933 /* XXX Log every Nth underrun from 2934 * XXX now on? 2935 */ 2936 } 2937 } 2938 2939 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2940 if (status & ATW_INTR_TPS) 2941 printf("%s: transmit process stopped\n", 2942 device_xname(sc->sc_dev)); 2943 if (status & ATW_INTR_RPS) 2944 printf("%s: receive process stopped\n", 2945 device_xname(sc->sc_dev)); 2946 s = splnet(); 2947 (void)atw_init(ifp); 2948 splx(s); 2949 break; 2950 } 2951 2952 if (status & ATW_INTR_FBE) { 2953 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2954 s = splnet(); 2955 (void)atw_init(ifp); 2956 splx(s); 2957 break; 2958 } 2959 2960 /* 2961 * Not handled: 2962 * 2963 * Transmit buffer unavailable -- normal 2964 * condition, nothing to do, really. 2965 * 2966 * Early receive interrupt -- not available on 2967 * all chips, we just use RI. We also only 2968 * use single-segment receive DMA, so this 2969 * is mostly useless. 2970 * 2971 * TBD others 2972 */ 2973 } 2974 2975 /* Try to get more packets going. */ 2976 s = splnet(); 2977 atw_start(ifp); 2978 splx(s); 2979 2980 /* Enable interrupts */ 2981 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 2982 } 2983 2984 /* 2985 * atw_idle: 2986 * 2987 * Cause the transmit and/or receive processes to go idle. 2988 * 2989 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2990 * process in STSR if I clear SR or ST after the process has already 2991 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2992 * do not seem to be too reliable. Perhaps I have the sense of the 2993 * Rx bits switched with the Tx bits? 2994 */ 2995 void 2996 atw_idle(struct atw_softc *sc, u_int32_t bits) 2997 { 2998 u_int32_t ackmask = 0, opmode, stsr, test0; 2999 int i, s; 3000 3001 s = splnet(); 3002 3003 opmode = sc->sc_opmode & ~bits; 3004 3005 if (bits & ATW_NAR_SR) 3006 ackmask |= ATW_INTR_RPS; 3007 3008 if (bits & ATW_NAR_ST) { 3009 ackmask |= ATW_INTR_TPS; 3010 /* set ATW_NAR_HF to flush TX FIFO. */ 3011 opmode |= ATW_NAR_HF; 3012 } 3013 3014 ATW_WRITE(sc, ATW_NAR, opmode); 3015 DELAY(atw_nar_delay); 3016 3017 for (i = 0; i < 1000; i++) { 3018 stsr = ATW_READ(sc, ATW_STSR); 3019 if ((stsr & ackmask) == ackmask) 3020 break; 3021 DELAY(10); 3022 } 3023 3024 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3025 3026 if ((stsr & ackmask) == ackmask) 3027 goto out; 3028 3029 test0 = ATW_READ(sc, ATW_TEST0); 3030 3031 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3032 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3033 printf("%s: transmit process not idle [%s]\n", 3034 device_xname(sc->sc_dev), 3035 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3036 printf("%s: bits %08x test0 %08x stsr %08x\n", 3037 device_xname(sc->sc_dev), bits, test0, stsr); 3038 } 3039 3040 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3041 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3042 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3043 device_xname(sc->sc_dev), 3044 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3045 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3046 device_xname(sc->sc_dev), bits, test0, stsr)); 3047 } 3048 out: 3049 if ((bits & ATW_NAR_ST) != 0) 3050 atw_txdrain(sc); 3051 splx(s); 3052 return; 3053 } 3054 3055 /* 3056 * atw_linkintr: 3057 * 3058 * Helper; handle link-status interrupts. 3059 */ 3060 void 3061 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3062 { 3063 struct ieee80211com *ic = &sc->sc_ic; 3064 3065 if (ic->ic_state != IEEE80211_S_RUN) 3066 return; 3067 3068 if (linkstatus & ATW_INTR_LINKON) { 3069 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3070 sc->sc_rescan_timer = 0; 3071 } else if (linkstatus & ATW_INTR_LINKOFF) { 3072 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3073 if (ic->ic_opmode != IEEE80211_M_STA) 3074 return; 3075 sc->sc_rescan_timer = 3; 3076 sc->sc_if.if_timer = 1; 3077 } 3078 } 3079 3080 #if 0 3081 static inline int 3082 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3083 { 3084 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3085 return 0; 3086 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3087 return 0; 3088 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3089 } 3090 #endif 3091 3092 /* 3093 * atw_rxintr: 3094 * 3095 * Helper; handle receive interrupts. 3096 */ 3097 void 3098 atw_rxintr(struct atw_softc *sc) 3099 { 3100 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3101 struct ieee80211com *ic = &sc->sc_ic; 3102 struct ieee80211_node *ni; 3103 struct ieee80211_frame_min *wh; 3104 struct ifnet *ifp = &sc->sc_if; 3105 struct atw_rxsoft *rxs; 3106 struct mbuf *m; 3107 u_int32_t rxstat; 3108 int i, s, len, rate, rate0; 3109 u_int32_t rssi, ctlrssi; 3110 3111 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3112 rxs = &sc->sc_rxsoft[i]; 3113 3114 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3115 3116 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3117 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3118 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3119 3120 if (rxstat & ATW_RXSTAT_OWN) { 3121 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3122 break; 3123 } 3124 3125 sc->sc_rxptr = ATW_NEXTRX(i); 3126 3127 DPRINTF3(sc, 3128 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3129 device_xname(sc->sc_dev), 3130 rxstat, ctlrssi, 3131 le32toh(sc->sc_rxdescs[i].ar_buf1), 3132 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3133 3134 /* 3135 * Make sure the packet fits in one buffer. This should 3136 * always be the case. 3137 */ 3138 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3139 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3140 printf("%s: incoming packet spilled, resetting\n", 3141 device_xname(sc->sc_dev)); 3142 (void)atw_init(ifp); 3143 return; 3144 } 3145 3146 /* 3147 * If an error occurred, update stats, clear the status 3148 * word, and leave the packet buffer in place. It will 3149 * simply be reused the next time the ring comes around. 3150 */ 3151 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3152 #define PRINTERR(bit, str) \ 3153 if (rxstat & (bit)) \ 3154 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3155 str) 3156 ifp->if_ierrors++; 3157 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3158 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3159 #if 0 3160 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3161 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3162 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3163 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3164 #endif 3165 #undef PRINTERR 3166 atw_init_rxdesc(sc, i); 3167 continue; 3168 } 3169 3170 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3171 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3172 3173 /* 3174 * No errors; receive the packet. Note the ADM8211 3175 * includes the CRC in promiscuous mode. 3176 */ 3177 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3178 3179 /* 3180 * Allocate a new mbuf cluster. If that fails, we are 3181 * out of memory, and must drop the packet and recycle 3182 * the buffer that's already attached to this descriptor. 3183 */ 3184 m = rxs->rxs_mbuf; 3185 if (atw_add_rxbuf(sc, i) != 0) { 3186 ifp->if_ierrors++; 3187 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3188 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3189 atw_init_rxdesc(sc, i); 3190 continue; 3191 } 3192 3193 ifp->if_ipackets++; 3194 m_set_rcvif(m, ifp); 3195 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3196 3197 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3198 3199 /* The RSSI comes straight from a register in the 3200 * baseband processor. I know that for the RF3000, 3201 * the RSSI register also contains the antenna-selection 3202 * bits. Mask those off. 3203 * 3204 * TBD Treat other basebands. 3205 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3206 */ 3207 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3208 rssi = ctlrssi & RF3000_RSSI_MASK; 3209 else 3210 rssi = ctlrssi; 3211 3212 s = splnet(); 3213 3214 /* Pass this up to any BPF listeners. */ 3215 if (sc->sc_radiobpf != NULL) { 3216 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3217 3218 tap->ar_rate = rate; 3219 3220 /* TBD verify units are dB */ 3221 tap->ar_antsignal = (int)rssi; 3222 if (sc->sc_opmode & ATW_NAR_PR) 3223 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3224 else 3225 tap->ar_flags = 0; 3226 3227 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3228 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3229 3230 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), 3231 m); 3232 } 3233 3234 sc->sc_recv_ev.ev_count++; 3235 3236 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3237 if (rxstat & ATW_RXSTAT_CRC16E) 3238 sc->sc_crc16e_ev.ev_count++; 3239 if (rxstat & ATW_RXSTAT_CRC32E) 3240 sc->sc_crc32e_ev.ev_count++; 3241 if (rxstat & ATW_RXSTAT_ICVE) 3242 sc->sc_icve_ev.ev_count++; 3243 if (rxstat & ATW_RXSTAT_SFDE) 3244 sc->sc_sfde_ev.ev_count++; 3245 if (rxstat & ATW_RXSTAT_SIGE) 3246 sc->sc_sige_ev.ev_count++; 3247 ifp->if_ierrors++; 3248 m_freem(m); 3249 splx(s); 3250 continue; 3251 } 3252 3253 if (sc->sc_opmode & ATW_NAR_PR) 3254 m_adj(m, -IEEE80211_CRC_LEN); 3255 3256 wh = mtod(m, struct ieee80211_frame_min *); 3257 ni = ieee80211_find_rxnode(ic, wh); 3258 #if 0 3259 if (atw_hw_decrypted(sc, wh)) { 3260 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3261 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3262 } 3263 #endif 3264 ieee80211_input(ic, m, ni, (int)rssi, 0); 3265 ieee80211_free_node(ni); 3266 splx(s); 3267 } 3268 } 3269 3270 /* 3271 * atw_txintr: 3272 * 3273 * Helper; handle transmit interrupts. 3274 */ 3275 void 3276 atw_txintr(struct atw_softc *sc, uint32_t status) 3277 { 3278 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3279 struct ifnet *ifp = &sc->sc_if; 3280 struct atw_txsoft *txs; 3281 u_int32_t txstat; 3282 int s; 3283 3284 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3285 device_xname(sc->sc_dev), sc->sc_flags)); 3286 3287 s = splnet(); 3288 3289 /* 3290 * Go through our Tx list and free mbufs for those 3291 * frames that have been transmitted. 3292 */ 3293 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3294 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3295 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3296 3297 #ifdef ATW_DEBUG 3298 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3299 int i; 3300 printf(" txsoft %p transmit chain:\n", txs); 3301 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3302 txs->txs_ndescs - 1, 3303 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3304 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3305 printf(" descriptor %d:\n", i); 3306 printf(" at_status: 0x%08x\n", 3307 le32toh(sc->sc_txdescs[i].at_stat)); 3308 printf(" at_flags: 0x%08x\n", 3309 le32toh(sc->sc_txdescs[i].at_flags)); 3310 printf(" at_buf1: 0x%08x\n", 3311 le32toh(sc->sc_txdescs[i].at_buf1)); 3312 printf(" at_buf2: 0x%08x\n", 3313 le32toh(sc->sc_txdescs[i].at_buf2)); 3314 if (i == txs->txs_lastdesc) 3315 break; 3316 } 3317 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3318 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3319 } 3320 #endif 3321 3322 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3323 if (txstat & ATW_TXSTAT_OWN) { 3324 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3325 BUS_DMASYNC_PREREAD); 3326 break; 3327 } 3328 3329 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3330 3331 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3332 0, txs->txs_dmamap->dm_mapsize, 3333 BUS_DMASYNC_POSTWRITE); 3334 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3335 m_freem(txs->txs_mbuf); 3336 txs->txs_mbuf = NULL; 3337 3338 sc->sc_txfree += txs->txs_ndescs; 3339 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3340 3341 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3342 sc->sc_tx_timer = 0; 3343 ifp->if_flags &= ~IFF_OACTIVE; 3344 3345 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3346 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3347 snprintb(txstat_buf, sizeof(txstat_buf), 3348 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3349 printf("%s: txstat %s %" __PRIuBITS "\n", 3350 device_xname(sc->sc_dev), txstat_buf, 3351 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3352 } 3353 3354 sc->sc_xmit_ev.ev_count++; 3355 3356 /* 3357 * Check for errors and collisions. 3358 */ 3359 if (txstat & ATW_TXSTAT_TUF) 3360 sc->sc_tuf_ev.ev_count++; 3361 if (txstat & ATW_TXSTAT_TLT) 3362 sc->sc_tlt_ev.ev_count++; 3363 if (txstat & ATW_TXSTAT_TRT) 3364 sc->sc_trt_ev.ev_count++; 3365 if (txstat & ATW_TXSTAT_TRO) 3366 sc->sc_tro_ev.ev_count++; 3367 if (txstat & ATW_TXSTAT_SOFBR) 3368 sc->sc_sofbr_ev.ev_count++; 3369 3370 if ((txstat & ATW_TXSTAT_ES) == 0) 3371 ifp->if_collisions += 3372 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3373 else 3374 ifp->if_oerrors++; 3375 3376 ifp->if_opackets++; 3377 } 3378 3379 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3380 3381 splx(s); 3382 } 3383 3384 /* 3385 * atw_watchdog: [ifnet interface function] 3386 * 3387 * Watchdog timer handler. 3388 */ 3389 void 3390 atw_watchdog(struct ifnet *ifp) 3391 { 3392 struct atw_softc *sc = ifp->if_softc; 3393 struct ieee80211com *ic = &sc->sc_ic; 3394 3395 ifp->if_timer = 0; 3396 if (!device_is_active(sc->sc_dev)) 3397 return; 3398 3399 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3400 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3401 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3402 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3403 printf("%s: transmit timeout\n", ifp->if_xname); 3404 ifp->if_oerrors++; 3405 (void)atw_init(ifp); 3406 atw_start(ifp); 3407 } 3408 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3409 ifp->if_timer = 1; 3410 ieee80211_watchdog(ic); 3411 } 3412 3413 static void 3414 atw_evcnt_detach(struct atw_softc *sc) 3415 { 3416 evcnt_detach(&sc->sc_sige_ev); 3417 evcnt_detach(&sc->sc_sfde_ev); 3418 evcnt_detach(&sc->sc_icve_ev); 3419 evcnt_detach(&sc->sc_crc32e_ev); 3420 evcnt_detach(&sc->sc_crc16e_ev); 3421 evcnt_detach(&sc->sc_recv_ev); 3422 3423 evcnt_detach(&sc->sc_tuf_ev); 3424 evcnt_detach(&sc->sc_tro_ev); 3425 evcnt_detach(&sc->sc_trt_ev); 3426 evcnt_detach(&sc->sc_tlt_ev); 3427 evcnt_detach(&sc->sc_sofbr_ev); 3428 evcnt_detach(&sc->sc_xmit_ev); 3429 3430 evcnt_detach(&sc->sc_rxpkt1in_ev); 3431 evcnt_detach(&sc->sc_rxamatch_ev); 3432 evcnt_detach(&sc->sc_workaround1_ev); 3433 evcnt_detach(&sc->sc_misc_ev); 3434 } 3435 3436 static void 3437 atw_evcnt_attach(struct atw_softc *sc) 3438 { 3439 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3440 NULL, sc->sc_if.if_xname, "recv"); 3441 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3442 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3443 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3444 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3445 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3446 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3447 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3448 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3449 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3450 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3451 3452 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3453 NULL, sc->sc_if.if_xname, "xmit"); 3454 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3455 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3456 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3457 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3458 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3459 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3460 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3461 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3462 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3463 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3464 3465 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3466 NULL, sc->sc_if.if_xname, "misc"); 3467 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3468 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3469 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3470 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3471 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3472 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3473 } 3474 3475 #ifdef ATW_DEBUG 3476 static void 3477 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3478 { 3479 struct atw_softc *sc = ifp->if_softc; 3480 struct mbuf *m; 3481 int i, noctets = 0; 3482 3483 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3484 m0->m_pkthdr.len); 3485 3486 for (m = m0; m; m = m->m_next) { 3487 if (m->m_len == 0) 3488 continue; 3489 for (i = 0; i < m->m_len; i++) { 3490 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3491 if (++noctets % 24 == 0) 3492 printf("\n"); 3493 } 3494 } 3495 printf("%s%s: %d bytes emitted\n", 3496 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3497 } 3498 #endif /* ATW_DEBUG */ 3499 3500 /* 3501 * atw_start: [ifnet interface function] 3502 * 3503 * Start packet transmission on the interface. 3504 */ 3505 void 3506 atw_start(struct ifnet *ifp) 3507 { 3508 struct atw_softc *sc = ifp->if_softc; 3509 struct ieee80211_key *k; 3510 struct ieee80211com *ic = &sc->sc_ic; 3511 struct ieee80211_node *ni; 3512 struct ieee80211_frame_min *whm; 3513 struct ieee80211_frame *wh; 3514 struct atw_frame *hh; 3515 uint16_t hdrctl; 3516 struct mbuf *m0, *m; 3517 struct atw_txsoft *txs; 3518 struct atw_txdesc *txd; 3519 int npkt, rate; 3520 bus_dmamap_t dmamap; 3521 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3522 3523 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3524 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3525 3526 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3527 return; 3528 3529 /* 3530 * Remember the previous number of free descriptors and 3531 * the first descriptor we'll use. 3532 */ 3533 ofree = sc->sc_txfree; 3534 firsttx = lasttx = sc->sc_txnext; 3535 3536 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3537 device_xname(sc->sc_dev), ofree, firsttx)); 3538 3539 /* 3540 * Loop through the send queue, setting up transmit descriptors 3541 * until we drain the queue, or use up all available transmit 3542 * descriptors. 3543 */ 3544 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3545 sc->sc_txfree != 0) { 3546 3547 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3548 3549 /* 3550 * Grab a packet off the management queue, if it 3551 * is not empty. Otherwise, from the data queue. 3552 */ 3553 IF_DEQUEUE(&ic->ic_mgtq, m0); 3554 if (m0 != NULL) { 3555 ni = M_GETCTX(m0, struct ieee80211_node *); 3556 M_CLEARCTX(m0); 3557 } else if (ic->ic_state != IEEE80211_S_RUN) 3558 break; /* send no data until associated */ 3559 else { 3560 IFQ_DEQUEUE(&ifp->if_snd, m0); 3561 if (m0 == NULL) 3562 break; 3563 bpf_mtap(ifp, m0); 3564 ni = ieee80211_find_txnode(ic, 3565 mtod(m0, struct ether_header *)->ether_dhost); 3566 if (ni == NULL) { 3567 ifp->if_oerrors++; 3568 break; 3569 } 3570 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3571 ieee80211_free_node(ni); 3572 ifp->if_oerrors++; 3573 break; 3574 } 3575 } 3576 3577 rate = MAX(ieee80211_get_rate(ni), 2); 3578 3579 whm = mtod(m0, struct ieee80211_frame_min *); 3580 3581 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3582 k = NULL; 3583 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3584 m_freem(m0); 3585 ieee80211_free_node(ni); 3586 ifp->if_oerrors++; 3587 break; 3588 } 3589 #if 0 3590 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3591 m0->m_pkthdr.len > ic->ic_fragthreshold) 3592 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3593 #endif 3594 3595 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3596 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3597 3598 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3599 ic->ic_flags, ic->ic_fragthreshold, rate, 3600 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3601 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3602 m_freem(m0); 3603 break; 3604 } 3605 3606 /* XXX Misleading if fragmentation is enabled. Better 3607 * to fragment in software? 3608 */ 3609 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3610 3611 /* 3612 * Pass the packet to any BPF listeners. 3613 */ 3614 bpf_mtap3(ic->ic_rawbpf, m0); 3615 3616 if (sc->sc_radiobpf != NULL) { 3617 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3618 3619 tap->at_rate = rate; 3620 3621 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), 3622 m0); 3623 } 3624 3625 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3626 3627 if (ni != NULL) 3628 ieee80211_free_node(ni); 3629 3630 if (m0 == NULL) { 3631 ifp->if_oerrors++; 3632 break; 3633 } 3634 3635 /* just to make sure. */ 3636 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3637 3638 if (m0 == NULL) { 3639 ifp->if_oerrors++; 3640 break; 3641 } 3642 3643 hh = mtod(m0, struct atw_frame *); 3644 wh = &hh->atw_ihdr; 3645 3646 /* Copy everything we need from the 802.11 header: 3647 * Frame Control; address 1, address 3, or addresses 3648 * 3 and 4. NIC fills in BSSID, SA. 3649 */ 3650 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3651 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3652 panic("%s: illegal WDS frame", 3653 device_xname(sc->sc_dev)); 3654 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3655 } else 3656 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3657 3658 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3659 3660 /* initialize remaining Tx parameters */ 3661 memset(&hh->u, 0, sizeof(hh->u)); 3662 3663 hh->atw_rate = rate * 5; 3664 /* XXX this could be incorrect if M_FCS. _encap should 3665 * probably strip FCS just in case it sticks around in 3666 * bridged packets. 3667 */ 3668 hh->atw_service = 0x00; /* XXX guess */ 3669 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3670 sizeof(struct atw_frame)); 3671 3672 /* never fragment multicast frames */ 3673 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3674 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3675 else { 3676 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3677 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3678 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3679 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3680 } 3681 3682 hh->atw_rtylmt = 3; 3683 #if 0 3684 if (do_encrypt) { 3685 hdrctl |= htole16(ATW_HDRCTL_WEP); 3686 hh->atw_keyid = ic->ic_def_txkey; 3687 } 3688 #endif 3689 3690 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3691 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3692 if (txs->txs_d0.d_residue) 3693 hh->atw_head_plcplen |= htole16(0x8000); 3694 if (txs->txs_dn.d_residue) 3695 hh->atw_tail_plcplen |= htole16(0x8000); 3696 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3697 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3698 3699 hh->atw_hdrctl = hdrctl; 3700 hh->atw_fragnum = npkt << 4; 3701 #ifdef ATW_DEBUG 3702 3703 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3704 printf("%s: dst = %s, rate = 0x%02x, " 3705 "service = 0x%02x, paylen = 0x%04x\n", 3706 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3707 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3708 3709 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3710 "dur1 = 0x%04x, dur2 = 0x%04x, " 3711 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3712 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3713 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3714 hh->atw_tail_dur, hh->atw_head_dur); 3715 3716 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3717 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3718 device_xname(sc->sc_dev), hh->atw_hdrctl, 3719 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3720 3721 printf("%s: keyid = %d\n", 3722 device_xname(sc->sc_dev), hh->atw_keyid); 3723 3724 atw_dump_pkt(ifp, m0); 3725 } 3726 #endif /* ATW_DEBUG */ 3727 3728 dmamap = txs->txs_dmamap; 3729 3730 /* 3731 * Load the DMA map. Copy and try (once) again if the packet 3732 * didn't fit in the alloted number of segments. 3733 */ 3734 for (first = 1; 3735 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3736 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3737 first = 0) { 3738 MGETHDR(m, M_DONTWAIT, MT_DATA); 3739 if (m == NULL) { 3740 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3741 break; 3742 } 3743 if (m0->m_pkthdr.len > MHLEN) { 3744 MCLGET(m, M_DONTWAIT); 3745 if ((m->m_flags & M_EXT) == 0) { 3746 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3747 "cluster\n"); 3748 m_freem(m); 3749 break; 3750 } 3751 } 3752 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3753 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3754 m_freem(m0); 3755 m0 = m; 3756 m = NULL; 3757 } 3758 if (error != 0) { 3759 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3760 "error = %d\n", error); 3761 m_freem(m0); 3762 break; 3763 } 3764 3765 /* 3766 * Ensure we have enough descriptors free to describe 3767 * the packet. 3768 */ 3769 if (dmamap->dm_nsegs > sc->sc_txfree) { 3770 /* 3771 * Not enough free descriptors to transmit 3772 * this packet. Unload the DMA map and 3773 * drop the packet. Notify the upper layer 3774 * that there are no more slots left. 3775 * 3776 * XXX We could allocate an mbuf and copy, but 3777 * XXX it is worth it? 3778 */ 3779 bus_dmamap_unload(sc->sc_dmat, dmamap); 3780 m_freem(m0); 3781 break; 3782 } 3783 3784 /* 3785 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3786 */ 3787 3788 /* Sync the DMA map. */ 3789 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3790 BUS_DMASYNC_PREWRITE); 3791 3792 /* XXX arbitrary retry limit; 8 because I have seen it in 3793 * use already and maybe 0 means "no tries" ! 3794 */ 3795 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3796 3797 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3798 device_xname(sc->sc_dev), rate * 5)); 3799 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3800 3801 /* 3802 * Initialize the transmit descriptors. 3803 */ 3804 for (nexttx = sc->sc_txnext, seg = 0; 3805 seg < dmamap->dm_nsegs; 3806 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3807 /* 3808 * If this is the first descriptor we're 3809 * enqueueing, don't set the OWN bit just 3810 * yet. That could cause a race condition. 3811 * We'll do it below. 3812 */ 3813 txd = &sc->sc_txdescs[nexttx]; 3814 txd->at_ctl = ctl | 3815 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3816 3817 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3818 txd->at_flags = 3819 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3820 ATW_TXFLAG_TBS1_MASK)) | 3821 ((nexttx == (ATW_NTXDESC - 1)) 3822 ? htole32(ATW_TXFLAG_TER) : 0); 3823 lasttx = nexttx; 3824 } 3825 3826 /* Set `first segment' and `last segment' appropriately. */ 3827 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3828 htole32(ATW_TXFLAG_FS); 3829 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3830 3831 #ifdef ATW_DEBUG 3832 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3833 printf(" txsoft %p transmit chain:\n", txs); 3834 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3835 printf(" descriptor %d:\n", seg); 3836 printf(" at_ctl: 0x%08x\n", 3837 le32toh(sc->sc_txdescs[seg].at_ctl)); 3838 printf(" at_flags: 0x%08x\n", 3839 le32toh(sc->sc_txdescs[seg].at_flags)); 3840 printf(" at_buf1: 0x%08x\n", 3841 le32toh(sc->sc_txdescs[seg].at_buf1)); 3842 printf(" at_buf2: 0x%08x\n", 3843 le32toh(sc->sc_txdescs[seg].at_buf2)); 3844 if (seg == lasttx) 3845 break; 3846 } 3847 } 3848 #endif 3849 3850 /* Sync the descriptors we're using. */ 3851 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3853 3854 /* 3855 * Store a pointer to the packet so we can free it later, 3856 * and remember what txdirty will be once the packet is 3857 * done. 3858 */ 3859 txs->txs_mbuf = m0; 3860 txs->txs_firstdesc = sc->sc_txnext; 3861 txs->txs_lastdesc = lasttx; 3862 txs->txs_ndescs = dmamap->dm_nsegs; 3863 3864 /* Advance the tx pointer. */ 3865 sc->sc_txfree -= dmamap->dm_nsegs; 3866 sc->sc_txnext = nexttx; 3867 3868 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3869 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3870 } 3871 3872 if (sc->sc_txfree != ofree) { 3873 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3874 device_xname(sc->sc_dev), lasttx, firsttx)); 3875 /* 3876 * Cause a transmit interrupt to happen on the 3877 * last packet we enqueued. 3878 */ 3879 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3880 ATW_CDTXSYNC(sc, lasttx, 1, 3881 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3882 3883 /* 3884 * The entire packet chain is set up. Give the 3885 * first descriptor to the chip now. 3886 */ 3887 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3888 ATW_CDTXSYNC(sc, firsttx, 1, 3889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3890 3891 /* Wake up the transmitter. */ 3892 ATW_WRITE(sc, ATW_TDR, 0x1); 3893 3894 if (txs == NULL || sc->sc_txfree == 0) 3895 ifp->if_flags |= IFF_OACTIVE; 3896 3897 /* Set a watchdog timer in case the chip flakes out. */ 3898 sc->sc_tx_timer = 5; 3899 ifp->if_timer = 1; 3900 } 3901 } 3902 3903 /* 3904 * atw_ioctl: [ifnet interface function] 3905 * 3906 * Handle control requests from the operator. 3907 */ 3908 int 3909 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3910 { 3911 struct atw_softc *sc = ifp->if_softc; 3912 struct ieee80211req *ireq; 3913 int s, error = 0; 3914 3915 s = splnet(); 3916 3917 switch (cmd) { 3918 case SIOCSIFFLAGS: 3919 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3920 break; 3921 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 3922 case IFF_UP|IFF_RUNNING: 3923 /* 3924 * To avoid rescanning another access point, 3925 * do not call atw_init() here. Instead, 3926 * only reflect media settings. 3927 */ 3928 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3929 atw_filter_setup(sc); 3930 break; 3931 case IFF_UP: 3932 error = atw_init(ifp); 3933 break; 3934 case IFF_RUNNING: 3935 atw_stop(ifp, 1); 3936 break; 3937 case 0: 3938 break; 3939 } 3940 break; 3941 case SIOCADDMULTI: 3942 case SIOCDELMULTI: 3943 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3944 if (ifp->if_flags & IFF_RUNNING) 3945 atw_filter_setup(sc); /* do not rescan */ 3946 error = 0; 3947 } 3948 break; 3949 case SIOCS80211: 3950 ireq = data; 3951 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3952 if ((error = kauth_authorize_network(curlwp->l_cred, 3953 KAUTH_NETWORK_INTERFACE, 3954 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3955 (void *)cmd, NULL)) != 0) 3956 break; 3957 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3958 ireq->i_val <= IEEE80211_FRAG_MAX)) 3959 error = EINVAL; 3960 else 3961 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3962 break; 3963 } 3964 /*FALLTHROUGH*/ 3965 default: 3966 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3967 if (error == ENETRESET || error == ERESTART) { 3968 if (is_running(ifp)) 3969 error = atw_init(ifp); 3970 else 3971 error = 0; 3972 } 3973 break; 3974 } 3975 3976 /* Try to get more packets going. */ 3977 if (device_is_active(sc->sc_dev)) 3978 atw_start(ifp); 3979 3980 splx(s); 3981 return (error); 3982 } 3983 3984 static int 3985 atw_media_change(struct ifnet *ifp) 3986 { 3987 int error; 3988 3989 error = ieee80211_media_change(ifp); 3990 if (error == ENETRESET) { 3991 if (is_running(ifp)) 3992 error = atw_init(ifp); 3993 else 3994 error = 0; 3995 } 3996 return error; 3997 } 3998
Indexes created Fri Oct 17 03:10:13 GMT 2025