atw.c revision 1.166
1 /* $NetBSD: atw.c,v 1.166 2019/05/23 10:57:28 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.166 2019/05/23 10:57:28 msaitoh Exp $"); 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/kauth.h> 51 #include <sys/time.h> 52 #include <sys/proc.h> 53 #include <sys/atomic.h> 54 #include <lib/libkern/libkern.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <net/bpf.h> 68 69 #include <sys/bus.h> 70 #include <sys/intr.h> 71 72 #include <dev/ic/atwreg.h> 73 #include <dev/ic/rf3000reg.h> 74 #include <dev/ic/si4136reg.h> 75 #include <dev/ic/atwvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* XXX TBD open questions 79 * 80 * 81 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 82 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 83 * handle this for me? 84 * 85 */ 86 /* device attachment 87 * 88 * print TOFS[012] 89 * 90 * device initialization 91 * 92 * clear ATW_FRCTL_MAXPSP to disable max power saving 93 * set ATW_TXBR_ALCUPDATE to enable ALC 94 * set TOFS[012]? (hope not) 95 * disable rx/tx 96 * set ATW_PAR_SWR (software reset) 97 * wait for ATW_PAR_SWR clear 98 * disable interrupts 99 * ack status register 100 * enable interrupts 101 * 102 * rx/tx initialization 103 * 104 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 105 * allocate and init descriptor rings 106 * write ATW_PAR_DSL (descriptor skip length) 107 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 108 * write ATW_NAR_SQ for one/both transmit descriptor rings 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * 112 * rx/tx end 113 * 114 * stop DMA 115 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * flush tx w/ ATW_NAR_HF 117 * 118 * scan 119 * 120 * initialize rx/tx 121 * 122 * BSS join: (re)association response 123 * 124 * set ATW_FRCTL_AID 125 * 126 * optimizations ??? 127 * 128 */ 129 130 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 131 132 int atw_pseudo_milli = 1; 133 int atw_magic_delay1 = 100 * 1000; 134 int atw_magic_delay2 = 100 * 1000; 135 /* more magic multi-millisecond delays (units: microseconds) */ 136 int atw_nar_delay = 20 * 1000; 137 int atw_magic_delay4 = 10 * 1000; 138 int atw_rf_delay1 = 10 * 1000; 139 int atw_rf_delay2 = 5 * 1000; 140 int atw_plcphd_delay = 2 * 1000; 141 int atw_bbp_io_enable_delay = 20 * 1000; 142 int atw_bbp_io_disable_delay = 2 * 1000; 143 int atw_writewep_delay = 1000; 144 int atw_beacon_len_adjust = 4; 145 int atw_dwelltime = 200; 146 int atw_xindiv2 = 0; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 159 static void atw_print_regs(struct atw_softc *, const char *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static void atw_rf3000_print(struct atw_softc *); 164 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static void atw_si4126_print(struct atw_softc *); 169 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 170 # endif /* ATW_SYNDEBUG */ 171 #define __atwdebugused /* empty */ 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #define __atwdebugused __unused 180 #endif 181 182 /* ifnet methods */ 183 int atw_init(struct ifnet *); 184 int atw_ioctl(struct ifnet *, u_long, void *); 185 void atw_start(struct ifnet *); 186 void atw_stop(struct ifnet *, int); 187 void atw_watchdog(struct ifnet *); 188 189 /* Device attachment */ 190 void atw_attach(struct atw_softc *); 191 int atw_detach(struct atw_softc *); 192 static void atw_evcnt_attach(struct atw_softc *); 193 static void atw_evcnt_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 int atw_add_rxbuf(struct atw_softc *, int); 197 void atw_idle(struct atw_softc *, uint32_t); 198 void atw_rxdrain(struct atw_softc *); 199 void atw_txdrain(struct atw_softc *); 200 201 /* Device (de)activation and power state */ 202 void atw_reset(struct atw_softc *); 203 204 /* Interrupt handlers */ 205 void atw_softintr(void *); 206 void atw_linkintr(struct atw_softc *, uint32_t); 207 void atw_rxintr(struct atw_softc *); 208 void atw_txintr(struct atw_softc *, uint32_t); 209 210 /* 802.11 state machine */ 211 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 212 static void atw_next_scan(void *); 213 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 214 struct ieee80211_node *, int, int, uint32_t); 215 static int atw_tune(struct atw_softc *); 216 217 /* Device initialization */ 218 static void atw_bbp_io_init(struct atw_softc *); 219 static void atw_cfp_init(struct atw_softc *); 220 static void atw_cmdr_init(struct atw_softc *); 221 static void atw_ifs_init(struct atw_softc *); 222 static void atw_nar_init(struct atw_softc *); 223 static void atw_response_times_init(struct atw_softc *); 224 static void atw_rf_reset(struct atw_softc *); 225 static void atw_test1_init(struct atw_softc *); 226 static void atw_tofs0_init(struct atw_softc *); 227 static void atw_tofs2_init(struct atw_softc *); 228 static void atw_txlmt_init(struct atw_softc *); 229 static void atw_wcsr_init(struct atw_softc *); 230 231 /* Key management */ 232 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 233 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 234 const uint8_t[IEEE80211_ADDR_LEN]); 235 static void atw_key_update_begin(struct ieee80211com *); 236 static void atw_key_update_end(struct ieee80211com *); 237 238 /* RAM/ROM utilities */ 239 static void atw_clear_sram(struct atw_softc *); 240 static void atw_write_sram(struct atw_softc *, u_int, uint8_t *, u_int); 241 static int atw_read_srom(struct atw_softc *); 242 243 /* BSS setup */ 244 static void atw_predict_beacon(struct atw_softc *); 245 static void atw_start_beacon(struct atw_softc *, int); 246 static void atw_write_bssid(struct atw_softc *); 247 static void atw_write_ssid(struct atw_softc *); 248 static void atw_write_sup_rates(struct atw_softc *); 249 static void atw_write_wep(struct atw_softc *); 250 251 /* Media */ 252 static int atw_media_change(struct ifnet *); 253 254 static void atw_filter_setup(struct atw_softc *); 255 256 /* 802.11 utilities */ 257 static uint64_t atw_get_tsft(struct atw_softc *); 258 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 259 uint32_t); 260 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 261 static void atw_node_free(struct ieee80211_node *); 262 263 /* 264 * Tuner/transceiver/modem 265 */ 266 static void atw_bbp_io_enable(struct atw_softc *, int); 267 268 /* RFMD RF3000 Baseband Processor */ 269 static int atw_rf3000_init(struct atw_softc *); 270 static int atw_rf3000_tune(struct atw_softc *, u_int); 271 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 272 273 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 274 static void atw_si4126_tune(struct atw_softc *, u_int); 275 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 276 277 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 278 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 279 280 const char *atw_tx_state[] = { 281 "STOPPED", 282 "RUNNING - read descriptor", 283 "RUNNING - transmitting", 284 "RUNNING - filling fifo", /* XXX */ 285 "SUSPENDED", 286 "RUNNING -- write descriptor", 287 "RUNNING -- write last descriptor", 288 "RUNNING - fifo full" 289 }; 290 291 const char *atw_rx_state[] = { 292 "STOPPED", 293 "RUNNING - read descriptor", 294 "RUNNING - check this packet, pre-fetch next", 295 "RUNNING - wait for reception", 296 "SUSPENDED", 297 "RUNNING - write descriptor", 298 "RUNNING - flush fifo", 299 "RUNNING - fifo drain" 300 }; 301 302 static inline int 303 is_running(struct ifnet *ifp) 304 { 305 return (ifp->if_flags & (IFF_RUNNING | IFF_UP)) 306 == (IFF_RUNNING | IFF_UP); 307 } 308 309 int 310 atw_activate(device_t self, enum devact act) 311 { 312 struct atw_softc *sc = device_private(self); 313 314 switch (act) { 315 case DVACT_DEACTIVATE: 316 if_deactivate(&sc->sc_if); 317 return 0; 318 default: 319 return EOPNOTSUPP; 320 } 321 } 322 323 bool 324 atw_suspend(device_t self, const pmf_qual_t *qual) 325 { 326 struct atw_softc *sc = device_private(self); 327 328 atw_rxdrain(sc); 329 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 330 331 return true; 332 } 333 334 /* Returns -1 on failure. */ 335 static int 336 atw_read_srom(struct atw_softc *sc) 337 { 338 struct seeprom_descriptor sd; 339 uint32_t test0, fail_bits; 340 341 (void)memset(&sd, 0, sizeof(sd)); 342 343 test0 = ATW_READ(sc, ATW_TEST0); 344 345 switch (sc->sc_rev) { 346 case ATW_REVISION_BA: 347 case ATW_REVISION_CA: 348 fail_bits = ATW_TEST0_EPNE; 349 break; 350 default: 351 fail_bits = ATW_TEST0_EPNE | ATW_TEST0_EPSNM; 352 break; 353 } 354 if ((test0 & fail_bits) != 0) { 355 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 356 return -1; 357 } 358 359 switch (test0 & ATW_TEST0_EPTYP_MASK) { 360 case ATW_TEST0_EPTYP_93c66: 361 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 362 sc->sc_sromsz = 512; 363 sd.sd_chip = C56_66; 364 break; 365 case ATW_TEST0_EPTYP_93c46: 366 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 367 sc->sc_sromsz = 128; 368 sd.sd_chip = C46; 369 break; 370 default: 371 printf("%s: unknown SROM type %" __PRIuBITS "\n", 372 device_xname(sc->sc_dev), 373 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 374 return -1; 375 } 376 377 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 378 379 if (sc->sc_srom == NULL) { 380 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 381 return -1; 382 } 383 384 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 385 386 /* ADM8211 has a single 32-bit register for controlling the 387 * 93cx6 SROM. Bit SRS enables the serial port. There is no 388 * "ready" bit. The ADM8211 input/output sense is the reverse 389 * of read_seeprom's. 390 */ 391 sd.sd_tag = sc->sc_st; 392 sd.sd_bsh = sc->sc_sh; 393 sd.sd_regsize = 4; 394 sd.sd_control_offset = ATW_SPR; 395 sd.sd_status_offset = ATW_SPR; 396 sd.sd_dataout_offset = ATW_SPR; 397 sd.sd_CK = ATW_SPR_SCLK; 398 sd.sd_CS = ATW_SPR_SCS; 399 sd.sd_DI = ATW_SPR_SDO; 400 sd.sd_DO = ATW_SPR_SDI; 401 sd.sd_MS = ATW_SPR_SRS; 402 sd.sd_RDY = 0; 403 404 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 405 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 406 free(sc->sc_srom, M_DEVBUF); 407 return -1; 408 } 409 #ifdef ATW_DEBUG 410 { 411 int i; 412 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 413 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 414 if (((i % 8) == 0) && (i != 0)) { 415 ATW_DPRINTF(("\n\t")); 416 } 417 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 418 } 419 ATW_DPRINTF(("\n")); 420 } 421 #endif /* ATW_DEBUG */ 422 return 0; 423 } 424 425 #ifdef ATW_DEBUG 426 static void 427 atw_print_regs(struct atw_softc *sc, const char *where) 428 { 429 #define PRINTREG(sc, reg) \ 430 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 431 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 432 433 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 434 435 PRINTREG(sc, ATW_PAR); 436 PRINTREG(sc, ATW_FRCTL); 437 PRINTREG(sc, ATW_TDR); 438 PRINTREG(sc, ATW_WTDP); 439 PRINTREG(sc, ATW_RDR); 440 PRINTREG(sc, ATW_WRDP); 441 PRINTREG(sc, ATW_RDB); 442 PRINTREG(sc, ATW_CSR3A); 443 PRINTREG(sc, ATW_TDBD); 444 PRINTREG(sc, ATW_TDBP); 445 PRINTREG(sc, ATW_STSR); 446 PRINTREG(sc, ATW_CSR5A); 447 PRINTREG(sc, ATW_NAR); 448 PRINTREG(sc, ATW_CSR6A); 449 PRINTREG(sc, ATW_IER); 450 PRINTREG(sc, ATW_CSR7A); 451 PRINTREG(sc, ATW_LPC); 452 PRINTREG(sc, ATW_TEST1); 453 PRINTREG(sc, ATW_SPR); 454 PRINTREG(sc, ATW_TEST0); 455 PRINTREG(sc, ATW_WCSR); 456 PRINTREG(sc, ATW_WPDR); 457 PRINTREG(sc, ATW_GPTMR); 458 PRINTREG(sc, ATW_GPIO); 459 PRINTREG(sc, ATW_BBPCTL); 460 PRINTREG(sc, ATW_SYNCTL); 461 PRINTREG(sc, ATW_PLCPHD); 462 PRINTREG(sc, ATW_MMIWADDR); 463 PRINTREG(sc, ATW_MMIRADDR1); 464 PRINTREG(sc, ATW_MMIRADDR2); 465 PRINTREG(sc, ATW_TXBR); 466 PRINTREG(sc, ATW_CSR15A); 467 PRINTREG(sc, ATW_ALCSTAT); 468 PRINTREG(sc, ATW_TOFS2); 469 PRINTREG(sc, ATW_CMDR); 470 PRINTREG(sc, ATW_PCIC); 471 PRINTREG(sc, ATW_PMCSR); 472 PRINTREG(sc, ATW_PAR0); 473 PRINTREG(sc, ATW_PAR1); 474 PRINTREG(sc, ATW_MAR0); 475 PRINTREG(sc, ATW_MAR1); 476 PRINTREG(sc, ATW_ATIMDA0); 477 PRINTREG(sc, ATW_ABDA1); 478 PRINTREG(sc, ATW_BSSID0); 479 PRINTREG(sc, ATW_TXLMT); 480 PRINTREG(sc, ATW_MIBCNT); 481 PRINTREG(sc, ATW_BCNT); 482 PRINTREG(sc, ATW_TSFTH); 483 PRINTREG(sc, ATW_TSC); 484 PRINTREG(sc, ATW_SYNRF); 485 PRINTREG(sc, ATW_BPLI); 486 PRINTREG(sc, ATW_CAP0); 487 PRINTREG(sc, ATW_CAP1); 488 PRINTREG(sc, ATW_RMD); 489 PRINTREG(sc, ATW_CFPP); 490 PRINTREG(sc, ATW_TOFS0); 491 PRINTREG(sc, ATW_TOFS1); 492 PRINTREG(sc, ATW_IFST); 493 PRINTREG(sc, ATW_RSPT); 494 PRINTREG(sc, ATW_TSFTL); 495 PRINTREG(sc, ATW_WEPCTL); 496 PRINTREG(sc, ATW_WESK); 497 PRINTREG(sc, ATW_WEPCNT); 498 PRINTREG(sc, ATW_MACTEST); 499 PRINTREG(sc, ATW_FER); 500 PRINTREG(sc, ATW_FEMR); 501 PRINTREG(sc, ATW_FPSR); 502 PRINTREG(sc, ATW_FFER); 503 #undef PRINTREG 504 } 505 #endif /* ATW_DEBUG */ 506 507 /* 508 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 509 */ 510 void 511 atw_attach(struct atw_softc *sc) 512 { 513 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 514 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 515 }; 516 struct ieee80211com *ic = &sc->sc_ic; 517 struct ifnet *ifp = &sc->sc_if; 518 int country_code, error, i, srom_major; 519 uint32_t reg; 520 static const char *type_strings[] = {"Intersil (not supported)", 521 "RFMD", "Marvel (not supported)"}; 522 523 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 524 525 sc->sc_soft_ih = softint_establish(SOFTINT_NET, atw_softintr, sc); 526 if (sc->sc_soft_ih == NULL) { 527 aprint_error_dev(sc->sc_dev, "unable to establish softint\n"); 528 goto fail_0; 529 } 530 531 sc->sc_txth = atw_txthresh_tab_lo; 532 533 SIMPLEQ_INIT(&sc->sc_txfreeq); 534 SIMPLEQ_INIT(&sc->sc_txdirtyq); 535 536 #ifdef ATW_DEBUG 537 atw_print_regs(sc, "atw_attach"); 538 #endif /* ATW_DEBUG */ 539 540 /* 541 * Allocate the control data structures, and create and load the 542 * DMA map for it. 543 */ 544 if ((error = bus_dmamem_alloc(sc->sc_dmat, 545 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 546 1, &sc->sc_cdnseg, 0)) != 0) { 547 aprint_error_dev(sc->sc_dev, 548 "unable to allocate control data, error = %d\n", 549 error); 550 goto fail_0; 551 } 552 553 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 554 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 555 BUS_DMA_COHERENT)) != 0) { 556 aprint_error_dev(sc->sc_dev, 557 "unable to map control data, error = %d\n", 558 error); 559 goto fail_1; 560 } 561 562 if ((error = bus_dmamap_create(sc->sc_dmat, 563 sizeof(struct atw_control_data), 1, 564 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 565 aprint_error_dev(sc->sc_dev, 566 "unable to create control data DMA map, error = %d\n", 567 error); 568 goto fail_2; 569 } 570 571 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 572 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 573 0)) != 0) { 574 aprint_error_dev(sc->sc_dev, 575 "unable to load control data DMA map, error = %d\n", error); 576 goto fail_3; 577 } 578 579 /* 580 * Create the transmit buffer DMA maps. 581 */ 582 sc->sc_ntxsegs = ATW_NTXSEGS; 583 for (i = 0; i < ATW_TXQUEUELEN; i++) { 584 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 585 sc->sc_ntxsegs, MCLBYTES, 0, 0, 586 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 587 aprint_error_dev(sc->sc_dev, 588 "unable to create tx DMA map %d, error = %d\n", i, 589 error); 590 goto fail_4; 591 } 592 } 593 594 /* 595 * Create the receive buffer DMA maps. 596 */ 597 for (i = 0; i < ATW_NRXDESC; i++) { 598 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 599 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 600 aprint_error_dev(sc->sc_dev, 601 "unable to create rx DMA map %d, error = %d\n", i, 602 error); 603 goto fail_5; 604 } 605 } 606 for (i = 0; i < ATW_NRXDESC; i++) { 607 sc->sc_rxsoft[i].rxs_mbuf = NULL; 608 } 609 610 switch (sc->sc_rev) { 611 case ATW_REVISION_AB: 612 case ATW_REVISION_AF: 613 sc->sc_sramlen = ATW_SRAM_A_SIZE; 614 break; 615 case ATW_REVISION_BA: 616 case ATW_REVISION_CA: 617 sc->sc_sramlen = ATW_SRAM_B_SIZE; 618 break; 619 } 620 621 /* Reset the chip to a known state. */ 622 atw_reset(sc); 623 624 if (atw_read_srom(sc) == -1) 625 goto fail_5; 626 627 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 628 ATW_SR_RFTYPE_MASK); 629 630 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 631 ATW_SR_BBPTYPE_MASK); 632 633 if (sc->sc_rftype >= __arraycount(type_strings)) { 634 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 635 goto fail_5; 636 } 637 if (sc->sc_bbptype >= __arraycount(type_strings)) { 638 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 639 goto fail_5; 640 } 641 642 aprint_normal_dev(sc->sc_dev, "%s RF, %s BBP", 643 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 644 645 /* XXX There exists a Linux driver which seems to use RFType = 0 for 646 * MARVEL. My bug, or theirs? 647 */ 648 649 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 650 651 switch (sc->sc_rftype) { 652 case ATW_RFTYPE_INTERSIL: 653 reg |= ATW_SYNCTL_CS1; 654 break; 655 case ATW_RFTYPE_RFMD: 656 reg |= ATW_SYNCTL_CS0; 657 break; 658 case ATW_RFTYPE_MARVEL: 659 break; 660 } 661 662 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 663 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 664 665 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 666 667 switch (sc->sc_bbptype) { 668 case ATW_BBPTYPE_INTERSIL: 669 reg |= ATW_BBPCTL_TWI; 670 break; 671 case ATW_BBPTYPE_RFMD: 672 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 673 ATW_BBPCTL_CCA_ACTLO; 674 break; 675 case ATW_BBPTYPE_MARVEL: 676 break; 677 case ATW_C_BBPTYPE_RFMD: 678 aprint_error_dev(sc->sc_dev, 679 "ADM8211C MAC/RFMD BBP not supported yet.\n"); 680 break; 681 } 682 683 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 684 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 685 686 /* 687 * From this point forward, the attachment cannot fail. A failure 688 * before this point releases all resources that may have been 689 * allocated. 690 */ 691 sc->sc_flags |= ATWF_ATTACHED; 692 693 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 694 htole16(sc->sc_srom[ATW_SR_MAC00]), 695 htole16(sc->sc_srom[ATW_SR_MAC01]), 696 htole16(sc->sc_srom[ATW_SR_MAC10]))); 697 698 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 699 ATW_SR_MAJOR_MASK); 700 701 if (srom_major < 2) 702 sc->sc_rf3000_options1 = 0; 703 else if (sc->sc_rev == ATW_REVISION_BA) { 704 sc->sc_rf3000_options1 = 705 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 706 ATW_SR_CR28_MASK); 707 } else 708 sc->sc_rf3000_options1 = 0; 709 710 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 711 ATW_SR_CR29_MASK); 712 713 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 714 ATW_SR_CTRY_MASK); 715 716 #define ADD_CHANNEL(_ic, _chan) do { \ 717 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 718 _ic->ic_channels[_chan].ic_freq = \ 719 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 720 } while (0) 721 722 /* Find available channels */ 723 switch (country_code) { 724 case COUNTRY_MMK2: /* 1-14 */ 725 ADD_CHANNEL(ic, 14); 726 /*FALLTHROUGH*/ 727 case COUNTRY_ETSI: /* 1-13 */ 728 for (i = 1; i <= 13; i++) 729 ADD_CHANNEL(ic, i); 730 break; 731 case COUNTRY_FCC: /* 1-11 */ 732 case COUNTRY_IC: /* 1-11 */ 733 for (i = 1; i <= 11; i++) 734 ADD_CHANNEL(ic, i); 735 break; 736 case COUNTRY_MMK: /* 14 */ 737 ADD_CHANNEL(ic, 14); 738 break; 739 case COUNTRY_FRANCE: /* 10-13 */ 740 for (i = 10; i <= 13; i++) 741 ADD_CHANNEL(ic, i); 742 break; 743 default: /* assume channels 10-11 */ 744 case COUNTRY_SPAIN: /* 10-11 */ 745 for (i = 10; i <= 11; i++) 746 ADD_CHANNEL(ic, i); 747 break; 748 } 749 750 /* Read the MAC address. */ 751 reg = ATW_READ(sc, ATW_PAR0); 752 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 753 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 754 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 755 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 756 reg = ATW_READ(sc, ATW_PAR1); 757 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 758 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 759 760 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 761 aprint_error_dev(sc->sc_dev, 762 "could not get mac address, attach failed\n"); 763 goto fail_5; 764 } 765 766 aprint_normal(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 767 768 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 769 ifp->if_softc = sc; 770 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 771 ifp->if_ioctl = atw_ioctl; 772 ifp->if_start = atw_start; 773 ifp->if_watchdog = atw_watchdog; 774 ifp->if_init = atw_init; 775 ifp->if_stop = atw_stop; 776 IFQ_SET_READY(&ifp->if_snd); 777 778 ic->ic_ifp = ifp; 779 ic->ic_phytype = IEEE80211_T_DS; 780 ic->ic_opmode = IEEE80211_M_STA; 781 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 782 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 783 784 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 785 786 /* 787 * Call MI attach routines. 788 */ 789 790 error = if_initialize(ifp); 791 if (error != 0) { 792 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 793 error); 794 goto fail_5; 795 } 796 ieee80211_ifattach(ic); 797 /* Use common softint-based if_input */ 798 ifp->if_percpuq = if_percpuq_create(ifp); 799 if_register(ifp); 800 801 atw_evcnt_attach(sc); 802 803 sc->sc_newstate = ic->ic_newstate; 804 ic->ic_newstate = atw_newstate; 805 806 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 807 ic->ic_recv_mgmt = atw_recv_mgmt; 808 809 sc->sc_node_free = ic->ic_node_free; 810 ic->ic_node_free = atw_node_free; 811 812 sc->sc_node_alloc = ic->ic_node_alloc; 813 ic->ic_node_alloc = atw_node_alloc; 814 815 ic->ic_crypto.cs_key_delete = atw_key_delete; 816 ic->ic_crypto.cs_key_set = atw_key_set; 817 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 818 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 819 820 /* possibly we should fill in our own sc_send_prresp, since 821 * the ADM8211 is probably sending probe responses in ad hoc 822 * mode. 823 */ 824 825 /* complete initialization */ 826 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 827 callout_init(&sc->sc_scan_ch, 0); 828 829 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 830 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 831 832 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 833 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 834 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 835 836 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 837 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 838 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 839 840 ieee80211_announce(ic); 841 return; 842 843 /* 844 * Free any resources we've allocated during the failed attach 845 * attempt. Do this in reverse order and fall through. 846 */ 847 fail_5: 848 for (i = 0; i < ATW_NRXDESC; i++) { 849 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 850 continue; 851 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 852 } 853 fail_4: 854 for (i = 0; i < ATW_TXQUEUELEN; i++) { 855 if (sc->sc_txsoft[i].txs_dmamap == NULL) 856 continue; 857 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 858 } 859 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 860 fail_3: 861 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 862 fail_2: 863 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 864 sizeof(struct atw_control_data)); 865 fail_1: 866 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 867 fail_0: 868 if (sc->sc_soft_ih != NULL) { 869 softint_disestablish(sc->sc_soft_ih); 870 sc->sc_soft_ih = NULL; 871 } 872 } 873 874 static struct ieee80211_node * 875 atw_node_alloc(struct ieee80211_node_table *nt) 876 { 877 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 878 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 879 880 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 881 return ni; 882 } 883 884 static void 885 atw_node_free(struct ieee80211_node *ni) 886 { 887 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 888 889 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 890 ether_sprintf(ni->ni_bssid))); 891 (*sc->sc_node_free)(ni); 892 } 893 894 895 static void 896 atw_test1_reset(struct atw_softc *sc) 897 { 898 switch (sc->sc_rev) { 899 case ATW_REVISION_BA: 900 if (1 /* XXX condition on transceiver type */) { 901 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 902 } 903 break; 904 case ATW_REVISION_CA: 905 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 906 break; 907 default: 908 break; 909 } 910 } 911 912 /* 913 * atw_reset: 914 * 915 * Perform a soft reset on the ADM8211. 916 */ 917 void 918 atw_reset(struct atw_softc *sc) 919 { 920 int i; 921 uint32_t lpc __atwdebugused; 922 923 ATW_WRITE(sc, ATW_NAR, 0x0); 924 DELAY(atw_nar_delay); 925 926 /* Reference driver has a cryptic remark indicating that this might 927 * power-on the chip. I know that it turns off power-saving.... 928 */ 929 ATW_WRITE(sc, ATW_FRCTL, 0x0); 930 931 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 932 933 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 934 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 935 break; 936 DELAY(atw_pseudo_milli); 937 } 938 939 /* ... and then pause 100ms longer for good measure. */ 940 DELAY(atw_magic_delay1); 941 942 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 943 944 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 945 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 946 947 /* 948 * Initialize the PCI Access Register. 949 */ 950 sc->sc_busmode = ATW_PAR_PBL_8DW; 951 952 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 953 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 954 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 955 956 atw_test1_reset(sc); 957 958 /* Turn off maximum power saving, etc. */ 959 ATW_WRITE(sc, ATW_FRCTL, 0x0); 960 961 DELAY(atw_magic_delay2); 962 963 /* Recall EEPROM. */ 964 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 965 966 DELAY(atw_magic_delay4); 967 968 lpc = ATW_READ(sc, ATW_LPC); 969 970 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 971 972 /* A reset seems to affect the SRAM contents, so put them into 973 * a known state. 974 */ 975 atw_clear_sram(sc); 976 977 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 978 } 979 980 static void 981 atw_clear_sram(struct atw_softc *sc) 982 { 983 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 984 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 985 /* XXX not for revision 0x20. */ 986 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 987 } 988 989 /* TBD atw_init 990 * 991 * set MAC based on ic->ic_bss->myaddr 992 * write WEP keys 993 * set TX rate 994 */ 995 996 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 997 * without receiving a beacon with the preferred BSSID & SSID. 998 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 999 */ 1000 static void 1001 atw_wcsr_init(struct atw_softc *sc) 1002 { 1003 uint32_t wcsr; 1004 1005 wcsr = ATW_READ(sc, ATW_WCSR); 1006 wcsr &= ~ATW_WCSR_BLN_MASK; 1007 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1008 /* We always want to wake up on link loss or TSFT out of range */ 1009 wcsr |= ATW_WCSR_LSOE | ATW_WCSR_TSFTWE; 1010 ATW_WRITE(sc, ATW_WCSR, wcsr); 1011 1012 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1013 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1014 } 1015 1016 /* Turn off power management. Set Rx store-and-forward mode. */ 1017 static void 1018 atw_cmdr_init(struct atw_softc *sc) 1019 { 1020 uint32_t cmdr; 1021 cmdr = ATW_READ(sc, ATW_CMDR); 1022 cmdr &= ~ATW_CMDR_APM; 1023 cmdr |= ATW_CMDR_RTE; 1024 cmdr &= ~ATW_CMDR_DRT_MASK; 1025 cmdr |= ATW_CMDR_DRT_SF; 1026 1027 ATW_WRITE(sc, ATW_CMDR, cmdr); 1028 } 1029 1030 static void 1031 atw_tofs2_init(struct atw_softc *sc) 1032 { 1033 uint32_t tofs2; 1034 /* XXX this magic can probably be figured out from the RFMD docs */ 1035 #ifndef ATW_REFSLAVE 1036 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1037 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1038 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1039 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1040 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1041 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1042 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1043 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1044 #else 1045 /* XXX new magic from reference driver source */ 1046 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1047 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1048 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1049 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1050 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1051 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1052 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1053 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1054 #endif 1055 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1056 } 1057 1058 static void 1059 atw_nar_init(struct atw_softc *sc) 1060 { 1061 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF | ATW_NAR_PB); 1062 } 1063 1064 static void 1065 atw_txlmt_init(struct atw_softc *sc) 1066 { 1067 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1068 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1069 } 1070 1071 static void 1072 atw_test1_init(struct atw_softc *sc) 1073 { 1074 uint32_t test1; 1075 1076 test1 = ATW_READ(sc, ATW_TEST1); 1077 test1 &= ~(ATW_TEST1_DBGREAD_MASK | ATW_TEST1_CONTROL); 1078 /* XXX magic 0x1 */ 1079 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1080 ATW_WRITE(sc, ATW_TEST1, test1); 1081 } 1082 1083 static void 1084 atw_rf_reset(struct atw_softc *sc) 1085 { 1086 /* XXX this resets an Intersil RF front-end? */ 1087 /* TBD condition on Intersil RFType? */ 1088 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1089 DELAY(atw_rf_delay1); 1090 ATW_WRITE(sc, ATW_SYNRF, 0); 1091 DELAY(atw_rf_delay2); 1092 } 1093 1094 /* Set 16 TU max duration for the contention-free period (CFP). */ 1095 static void 1096 atw_cfp_init(struct atw_softc *sc) 1097 { 1098 uint32_t cfpp; 1099 1100 cfpp = ATW_READ(sc, ATW_CFPP); 1101 cfpp &= ~ATW_CFPP_CFPMD; 1102 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1103 ATW_WRITE(sc, ATW_CFPP, cfpp); 1104 } 1105 1106 static void 1107 atw_tofs0_init(struct atw_softc *sc) 1108 { 1109 /* XXX I guess that the Cardbus clock is 22 MHz? 1110 * I am assuming that the role of ATW_TOFS0_USCNT is 1111 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1112 * very clear on this point. It says in the datasheet that it is 1113 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1114 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1115 * these values. These values are also the power-on default. 1116 */ 1117 ATW_WRITE(sc, ATW_TOFS0, 1118 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1119 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1120 } 1121 1122 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1123 static void 1124 atw_ifs_init(struct atw_softc *sc) 1125 { 1126 uint32_t ifst; 1127 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1128 * Go figure. 1129 */ 1130 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1131 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1132 ATW_IFST_SIFS_MASK) | 1133 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1134 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1135 1136 ATW_WRITE(sc, ATW_IFST, ifst); 1137 } 1138 1139 static void 1140 atw_response_times_init(struct atw_softc *sc) 1141 { 1142 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1143 * indicate that the MAC expects at least SIFS + MIRT microseconds 1144 * to pass after it transmits a frame that requires a response; 1145 * it waits at most SIFS + MART microseconds for the response. 1146 * Surely this is not the ACK timeout? 1147 */ 1148 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1149 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1150 } 1151 1152 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1153 * engines read and write baseband registers after Rx and before 1154 * Tx, respectively. 1155 */ 1156 static void 1157 atw_bbp_io_init(struct atw_softc *sc) 1158 { 1159 uint32_t mmiraddr2; 1160 1161 /* XXX The reference driver does this, but is it *really* 1162 * necessary? 1163 */ 1164 switch (sc->sc_rev) { 1165 case ATW_REVISION_AB: 1166 case ATW_REVISION_AF: 1167 mmiraddr2 = 0x0; 1168 break; 1169 default: 1170 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1171 mmiraddr2 &= 1172 ~(ATW_MMIRADDR2_PROREXT | ATW_MMIRADDR2_PRORLEN_MASK); 1173 break; 1174 } 1175 1176 switch (sc->sc_bbptype) { 1177 case ATW_BBPTYPE_INTERSIL: 1178 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1179 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1180 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1181 break; 1182 case ATW_BBPTYPE_MARVEL: 1183 /* TBD find out the Marvel settings. */ 1184 break; 1185 case ATW_BBPTYPE_RFMD: 1186 default: 1187 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1188 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1189 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1190 break; 1191 } 1192 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1193 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1194 } 1195 1196 /* 1197 * atw_init: [ ifnet interface function ] 1198 * 1199 * Initialize the interface. Must be called at splnet(). 1200 */ 1201 int 1202 atw_init(struct ifnet *ifp) 1203 { 1204 struct atw_softc *sc = ifp->if_softc; 1205 struct ieee80211com *ic = &sc->sc_ic; 1206 struct atw_txsoft *txs; 1207 struct atw_rxsoft *rxs; 1208 int i, error = 0; 1209 1210 if (device_is_active(sc->sc_dev)) { 1211 /* 1212 * Cancel any pending I/O. 1213 */ 1214 atw_stop(ifp, 0); 1215 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1216 !device_is_active(sc->sc_dev)) 1217 return 0; 1218 1219 /* 1220 * Reset the chip to a known state. 1221 */ 1222 atw_reset(sc); 1223 1224 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1225 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1226 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1227 1228 atw_wcsr_init(sc); 1229 1230 atw_cmdr_init(sc); 1231 1232 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1233 * 1234 * XXX Set transmit power for ATIM, RTS, Beacon. 1235 */ 1236 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1237 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1238 1239 atw_tofs2_init(sc); 1240 1241 atw_nar_init(sc); 1242 1243 atw_txlmt_init(sc); 1244 1245 atw_test1_init(sc); 1246 1247 atw_rf_reset(sc); 1248 1249 atw_cfp_init(sc); 1250 1251 atw_tofs0_init(sc); 1252 1253 atw_ifs_init(sc); 1254 1255 /* XXX Fall asleep after one second of inactivity. 1256 * XXX A frame may only dribble in for 65536us. 1257 */ 1258 ATW_WRITE(sc, ATW_RMD, 1259 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1260 1261 atw_response_times_init(sc); 1262 1263 atw_bbp_io_init(sc); 1264 1265 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1266 1267 if ((error = atw_rf3000_init(sc)) != 0) 1268 goto out; 1269 1270 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1271 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1272 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1273 1274 /* 1275 * Initialize the transmit descriptor ring. 1276 */ 1277 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1278 for (i = 0; i < ATW_NTXDESC; i++) { 1279 sc->sc_txdescs[i].at_ctl = 0; 1280 /* no transmit chaining */ 1281 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1282 sc->sc_txdescs[i].at_buf2 = 1283 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1284 } 1285 /* use ring mode */ 1286 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1287 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1288 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1289 sc->sc_txfree = ATW_NTXDESC; 1290 sc->sc_txnext = 0; 1291 1292 /* 1293 * Initialize the transmit job descriptors. 1294 */ 1295 SIMPLEQ_INIT(&sc->sc_txfreeq); 1296 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1297 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1298 txs = &sc->sc_txsoft[i]; 1299 txs->txs_mbuf = NULL; 1300 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1301 } 1302 1303 /* 1304 * Initialize the receive descriptor and receive job 1305 * descriptor rings. 1306 */ 1307 for (i = 0; i < ATW_NRXDESC; i++) { 1308 rxs = &sc->sc_rxsoft[i]; 1309 if (rxs->rxs_mbuf == NULL) { 1310 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1311 aprint_error_dev(sc->sc_dev, 1312 "unable to allocate or map rx buffer %d, " 1313 "error = %d\n", i, error); 1314 /* 1315 * XXX Should attempt to run with fewer receive 1316 * XXX buffers instead of just failing. 1317 */ 1318 atw_rxdrain(sc); 1319 goto out; 1320 } 1321 } else 1322 atw_init_rxdesc(sc, i); 1323 } 1324 sc->sc_rxptr = 0; 1325 1326 /* 1327 * Initialize the interrupt mask and enable interrupts. 1328 */ 1329 /* normal interrupts */ 1330 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1331 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1332 1333 /* abnormal interrupts */ 1334 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1335 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1336 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1337 1338 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1339 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1340 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1341 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1342 ATW_INTR_TRT; 1343 1344 sc->sc_linkint_mask &= sc->sc_inten; 1345 sc->sc_rxint_mask &= sc->sc_inten; 1346 sc->sc_txint_mask &= sc->sc_inten; 1347 1348 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1349 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1350 1351 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1352 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1353 1354 /* 1355 * Give the transmit and receive rings to the ADM8211. 1356 */ 1357 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1358 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1359 1360 sc->sc_txthresh = 0; 1361 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1362 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1363 1364 /* common 802.11 configuration */ 1365 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1366 switch (ic->ic_opmode) { 1367 case IEEE80211_M_STA: 1368 break; 1369 case IEEE80211_M_AHDEMO: /* XXX */ 1370 case IEEE80211_M_IBSS: 1371 ic->ic_flags |= IEEE80211_F_IBSSON; 1372 /*FALLTHROUGH*/ 1373 case IEEE80211_M_HOSTAP: /* XXX */ 1374 break; 1375 case IEEE80211_M_MONITOR: /* XXX */ 1376 break; 1377 } 1378 1379 switch (ic->ic_opmode) { 1380 case IEEE80211_M_AHDEMO: 1381 case IEEE80211_M_HOSTAP: 1382 #ifndef IEEE80211_NO_HOSTAP 1383 ic->ic_bss->ni_intval = ic->ic_lintval; 1384 ic->ic_bss->ni_rssi = 0; 1385 ic->ic_bss->ni_rstamp = 0; 1386 #endif /* !IEEE80211_NO_HOSTAP */ 1387 break; 1388 default: /* XXX */ 1389 break; 1390 } 1391 1392 sc->sc_wepctl = 0; 1393 1394 atw_write_ssid(sc); 1395 atw_write_sup_rates(sc); 1396 atw_write_wep(sc); 1397 1398 ic->ic_state = IEEE80211_S_INIT; 1399 1400 /* 1401 * Set the receive filter. This will start the transmit and 1402 * receive processes. 1403 */ 1404 atw_filter_setup(sc); 1405 1406 /* 1407 * Start the receive process. 1408 */ 1409 ATW_WRITE(sc, ATW_RDR, 0x1); 1410 1411 /* 1412 * Note that the interface is now running. 1413 */ 1414 ifp->if_flags |= IFF_RUNNING; 1415 1416 /* send no beacons, yet. */ 1417 atw_start_beacon(sc, 0); 1418 1419 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1420 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1421 else 1422 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1423 out: 1424 if (error) { 1425 ifp->if_flags &= ~IFF_RUNNING; 1426 sc->sc_tx_timer = 0; 1427 ifp->if_timer = 0; 1428 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1429 } 1430 #ifdef ATW_DEBUG 1431 atw_print_regs(sc, "end of init"); 1432 #endif /* ATW_DEBUG */ 1433 1434 return (error); 1435 } 1436 1437 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1438 * 0: MAC control of RF3000/Si4126. 1439 * 1440 * Applies power, or selects RF front-end? Sets reset condition. 1441 * 1442 * TBD support non-RFMD BBP, non-SiLabs synth. 1443 */ 1444 static void 1445 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1446 { 1447 if (enable) { 1448 ATW_WRITE(sc, ATW_SYNRF, 1449 ATW_SYNRF_SELRF | ATW_SYNRF_PE1 | ATW_SYNRF_PHYRST); 1450 DELAY(atw_bbp_io_enable_delay); 1451 } else { 1452 ATW_WRITE(sc, ATW_SYNRF, 0); 1453 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1454 } 1455 } 1456 1457 static int 1458 atw_tune(struct atw_softc *sc) 1459 { 1460 int rc; 1461 u_int chan; 1462 struct ieee80211com *ic = &sc->sc_ic; 1463 1464 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1465 if (chan == IEEE80211_CHAN_ANY) 1466 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1467 1468 if (chan == sc->sc_cur_chan) 1469 return 0; 1470 1471 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1472 sc->sc_cur_chan, chan)); 1473 1474 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 1475 1476 atw_si4126_tune(sc, chan); 1477 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1478 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1479 chan); 1480 1481 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1482 DELAY(atw_nar_delay); 1483 ATW_WRITE(sc, ATW_RDR, 0x1); 1484 1485 if (rc == 0) { 1486 sc->sc_cur_chan = chan; 1487 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1488 htole16(ic->ic_curchan->ic_freq); 1489 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1490 htole16(ic->ic_curchan->ic_flags); 1491 } 1492 1493 return rc; 1494 } 1495 1496 #ifdef ATW_SYNDEBUG 1497 static void 1498 atw_si4126_print(struct atw_softc *sc) 1499 { 1500 struct ifnet *ifp = &sc->sc_if; 1501 u_int addr, val; 1502 1503 val = 0; 1504 1505 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1506 return; 1507 1508 for (addr = 0; addr <= 8; addr++) { 1509 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1510 if (atw_si4126_read(sc, addr, &val) == 0) { 1511 printf("<unknown> (quitting print-out)\n"); 1512 break; 1513 } 1514 printf("%05x\n", val); 1515 } 1516 } 1517 #endif /* ATW_SYNDEBUG */ 1518 1519 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1520 * 1521 * The RF/IF synthesizer produces two reference frequencies for 1522 * the RF2948B transceiver. The first frequency the RF2948B requires 1523 * is two times the so-called "intermediate frequency" (IF). Since 1524 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1525 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1526 * frequency required by the transceiver is the radio frequency 1527 * (RF). This is a superheterodyne transceiver; for f(chan) the 1528 * center frequency of the channel we are tuning, RF = f(chan) - 1529 * IF. 1530 * 1531 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1532 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1533 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1534 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1535 */ 1536 static void 1537 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1538 { 1539 u_int mhz; 1540 u_int R; 1541 uint32_t gpio; 1542 uint16_t gain; 1543 1544 #ifdef ATW_SYNDEBUG 1545 atw_si4126_print(sc); 1546 #endif /* ATW_SYNDEBUG */ 1547 1548 if (chan == 14) 1549 mhz = 2484; 1550 else 1551 mhz = 2412 + 5 * (chan - 1); 1552 1553 /* Tune IF to 748 MHz to suit the IF LO input of the 1554 * RF2494B, which is 2 x IF. No need to set an IF divider 1555 * because an IF in 526 MHz - 952 MHz is allowed. 1556 * 1557 * XIN is 44.000 MHz, so divide it by two to get allowable 1558 * range of 2-25 MHz. SiLabs tells me that this is not 1559 * strictly necessary. 1560 */ 1561 1562 if (atw_xindiv2) 1563 R = 44; 1564 else 1565 R = 88; 1566 1567 /* Power-up RF, IF synthesizers. */ 1568 atw_si4126_write(sc, SI4126_POWER, 1569 SI4126_POWER_PDIB | SI4126_POWER_PDRB); 1570 1571 /* set LPWR, too? */ 1572 atw_si4126_write(sc, SI4126_MAIN, 1573 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1574 1575 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1576 * set KP2 to 1. 1577 * 1578 * REFDIF This is different from the reference driver, which 1579 * always sets SI4126_GAIN to 0. 1580 */ 1581 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1582 1583 atw_si4126_write(sc, SI4126_GAIN, gain); 1584 1585 /* XIN = 44 MHz. 1586 * 1587 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1588 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1589 * 1590 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1591 * so that 1496/88 * 44 MHz = 748 MHz. 1592 */ 1593 atw_si4126_write(sc, SI4126_IFN, 1496); 1594 1595 atw_si4126_write(sc, SI4126_IFR, R); 1596 1597 #ifndef ATW_REFSLAVE 1598 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1599 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1600 * which has no RF1! 1601 */ 1602 atw_si4126_write(sc, SI4126_RF1R, R); 1603 1604 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1605 #endif 1606 1607 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1608 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1609 * Now let's multiply it to mhz. So mhz - IF = N. 1610 */ 1611 atw_si4126_write(sc, SI4126_RF2R, R); 1612 1613 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1614 1615 /* wait 100us from power-up for RF, IF to settle */ 1616 DELAY(100); 1617 1618 gpio = ATW_READ(sc, ATW_GPIO); 1619 gpio &= ~(ATW_GPIO_EN_MASK | ATW_GPIO_O_MASK | ATW_GPIO_I_MASK); 1620 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1621 1622 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1623 /* Set a Prism RF front-end to a special mode for channel 14? 1624 * 1625 * Apparently the SMC2635W needs this, although I don't think 1626 * it has a Prism RF. 1627 */ 1628 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1629 } 1630 ATW_WRITE(sc, ATW_GPIO, gpio); 1631 1632 #ifdef ATW_SYNDEBUG 1633 atw_si4126_print(sc); 1634 #endif /* ATW_SYNDEBUG */ 1635 } 1636 1637 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1638 * diversity. 1639 * 1640 * !!! 1641 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1642 * !!! 1643 */ 1644 static int 1645 atw_rf3000_init(struct atw_softc *sc) 1646 { 1647 int rc = 0; 1648 1649 atw_bbp_io_enable(sc, 1); 1650 1651 /* CCA is acquisition sensitive */ 1652 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1653 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1654 1655 if (rc != 0) 1656 goto out; 1657 1658 /* enable diversity */ 1659 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1660 1661 if (rc != 0) 1662 goto out; 1663 1664 /* sensible setting from a binary-only driver */ 1665 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1666 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1667 1668 if (rc != 0) 1669 goto out; 1670 1671 /* magic from a binary-only driver */ 1672 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1673 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1674 1675 if (rc != 0) 1676 goto out; 1677 1678 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1679 1680 if (rc != 0) 1681 goto out; 1682 1683 /* XXX Reference driver remarks that Abocom sets this to 50. 1684 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1685 * in the "reserved" area of register RF3000_OPTIONS1. 1686 */ 1687 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1688 1689 if (rc != 0) 1690 goto out; 1691 1692 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 out: 1698 atw_bbp_io_enable(sc, 0); 1699 return rc; 1700 } 1701 1702 #ifdef ATW_BBPDEBUG 1703 static void 1704 atw_rf3000_print(struct atw_softc *sc) 1705 { 1706 struct ifnet *ifp = &sc->sc_if; 1707 u_int addr, val; 1708 1709 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1710 return; 1711 1712 for (addr = 0x01; addr <= 0x15; addr++) { 1713 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1714 if (atw_rf3000_read(sc, addr, &val) != 0) { 1715 printf("<unknown> (quitting print-out)\n"); 1716 break; 1717 } 1718 printf("%08x\n", val); 1719 } 1720 } 1721 #endif /* ATW_BBPDEBUG */ 1722 1723 /* Set the power settings on the BBP for channel `chan'. */ 1724 static int 1725 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1726 { 1727 int rc = 0; 1728 uint32_t reg; 1729 uint16_t txpower, lpf_cutoff, lna_gs_thresh; 1730 1731 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1732 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1733 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1734 1735 /* odd channels: LSB, even channels: MSB */ 1736 if (chan % 2 == 1) { 1737 txpower &= 0xFF; 1738 lpf_cutoff &= 0xFF; 1739 lna_gs_thresh &= 0xFF; 1740 } else { 1741 txpower >>= 8; 1742 lpf_cutoff >>= 8; 1743 lna_gs_thresh >>= 8; 1744 } 1745 1746 #ifdef ATW_BBPDEBUG 1747 atw_rf3000_print(sc); 1748 #endif /* ATW_BBPDEBUG */ 1749 1750 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1751 "lna_gs_thresh %02x\n", 1752 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1753 1754 atw_bbp_io_enable(sc, 1); 1755 1756 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1757 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1758 goto out; 1759 1760 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1761 goto out; 1762 1763 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1764 goto out; 1765 1766 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1767 1768 if (rc != 0) 1769 goto out; 1770 1771 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1772 1773 if (rc != 0) 1774 goto out; 1775 1776 #ifdef ATW_BBPDEBUG 1777 atw_rf3000_print(sc); 1778 #endif /* ATW_BBPDEBUG */ 1779 1780 out: 1781 atw_bbp_io_enable(sc, 0); 1782 1783 /* set beacon, rts, atim transmit power */ 1784 reg = ATW_READ(sc, ATW_PLCPHD); 1785 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1786 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1787 ATW_PLCPHD_SERVICE_MASK); 1788 ATW_WRITE(sc, ATW_PLCPHD, reg); 1789 DELAY(atw_plcphd_delay); 1790 1791 return rc; 1792 } 1793 1794 /* Write a register on the RF3000 baseband processor using the 1795 * registers provided by the ADM8211 for this purpose. 1796 * 1797 * Return 0 on success. 1798 */ 1799 static int 1800 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1801 { 1802 uint32_t reg; 1803 int i; 1804 1805 reg = sc->sc_bbpctl_wr | 1806 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1807 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1808 1809 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1810 ATW_WRITE(sc, ATW_BBPCTL, reg); 1811 DELAY(2 * atw_pseudo_milli); 1812 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1813 break; 1814 } 1815 1816 if (i < 0) { 1817 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1818 return ETIMEDOUT; 1819 } 1820 return 0; 1821 } 1822 1823 /* Read a register on the RF3000 baseband processor using the registers 1824 * the ADM8211 provides for this purpose. 1825 * 1826 * The 7-bit register address is addr. Record the 8-bit data in the register 1827 * in *val. 1828 * 1829 * Return 0 on success. 1830 * 1831 * XXX This does not seem to work. The ADM8211 must require more or 1832 * different magic to read the chip than to write it. Possibly some 1833 * of the magic I have derived from a binary-only driver concerns 1834 * the "chip address" (see the RF3000 manual). 1835 */ 1836 #ifdef ATW_BBPDEBUG 1837 static int 1838 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1839 { 1840 uint32_t reg; 1841 int i; 1842 1843 for (i = 1000; --i >= 0; ) { 1844 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD | ATW_BBPCTL_WR) 1845 == 0) 1846 break; 1847 DELAY(100); 1848 } 1849 1850 if (i < 0) { 1851 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1852 device_xname(sc->sc_dev)); 1853 return ETIMEDOUT; 1854 } 1855 1856 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1857 1858 ATW_WRITE(sc, ATW_BBPCTL, reg); 1859 1860 for (i = 1000; --i >= 0; ) { 1861 DELAY(100); 1862 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1863 break; 1864 } 1865 1866 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1867 1868 if (i < 0) { 1869 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1870 device_xname(sc->sc_dev), reg); 1871 return ETIMEDOUT; 1872 } 1873 if (val != NULL) 1874 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1875 return 0; 1876 } 1877 #endif /* ATW_BBPDEBUG */ 1878 1879 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1880 * provided by the ADM8211 for that purpose. 1881 * 1882 * val is 18 bits of data, and val is the 4-bit address of the register. 1883 * 1884 * Return 0 on success. 1885 */ 1886 static void 1887 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1888 { 1889 uint32_t bits, mask, reg; 1890 const int nbits = 22; 1891 1892 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1893 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1894 1895 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1896 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1897 1898 reg = ATW_SYNRF_SELSYN; 1899 /* reference driver: reset Si4126 serial bus to initial 1900 * conditions? 1901 */ 1902 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1903 ATW_WRITE(sc, ATW_SYNRF, reg); 1904 1905 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1906 if ((bits & mask) != 0) 1907 reg |= ATW_SYNRF_SYNDATA; 1908 else 1909 reg &= ~ATW_SYNRF_SYNDATA; 1910 ATW_WRITE(sc, ATW_SYNRF, reg); 1911 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1912 ATW_WRITE(sc, ATW_SYNRF, reg); 1913 } 1914 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1915 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1916 } 1917 1918 /* Read 18-bit data from the 4-bit address addr in Si4126 1919 * RF synthesizer and write the data to *val. Return 0 on success. 1920 * 1921 * XXX This does not seem to work. The ADM8211 must require more or 1922 * different magic to read the chip than to write it. 1923 */ 1924 #ifdef ATW_SYNDEBUG 1925 static int 1926 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1927 { 1928 uint32_t reg; 1929 int i; 1930 1931 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1932 1933 for (i = 1000; --i >= 0; ) { 1934 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD | ATW_SYNCTL_WR) 1935 == 0) 1936 break; 1937 DELAY(100); 1938 } 1939 1940 if (i < 0) { 1941 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1942 device_xname(sc->sc_dev)); 1943 return ETIMEDOUT; 1944 } 1945 1946 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1947 1948 ATW_WRITE(sc, ATW_SYNCTL, reg); 1949 1950 for (i = 1000; --i >= 0; ) { 1951 DELAY(100); 1952 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1953 break; 1954 } 1955 1956 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1957 1958 if (i < 0) { 1959 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1960 device_xname(sc->sc_dev), reg); 1961 return ETIMEDOUT; 1962 } 1963 if (val != NULL) 1964 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1965 ATW_SYNCTL_DATA_MASK); 1966 return 0; 1967 } 1968 #endif /* ATW_SYNDEBUG */ 1969 1970 /* XXX is the endianness correct? test. */ 1971 #define atw_calchash(addr) \ 1972 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1973 1974 /* 1975 * atw_filter_setup: 1976 * 1977 * Set the ADM8211's receive filter. 1978 */ 1979 static void 1980 atw_filter_setup(struct atw_softc *sc) 1981 { 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ethercom *ec = &sc->sc_ec; 1984 struct ifnet *ifp = &sc->sc_if; 1985 int hash; 1986 uint32_t hashes[2]; 1987 struct ether_multi *enm; 1988 struct ether_multistep step; 1989 1990 /* According to comments in tlp_al981_filter_setup 1991 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1992 * multicast filter to be set while it is running. Hopefully 1993 * the ADM8211 is not the same! 1994 */ 1995 if ((ifp->if_flags & IFF_RUNNING) != 0) 1996 atw_idle(sc, ATW_NAR_SR); 1997 1998 sc->sc_opmode &= ~(ATW_NAR_PB | ATW_NAR_PR | ATW_NAR_MM); 1999 ifp->if_flags &= ~IFF_ALLMULTI; 2000 2001 /* XXX in scan mode, do not filter packets. Maybe this is 2002 * unnecessary. 2003 */ 2004 if (ic->ic_state == IEEE80211_S_SCAN || 2005 (ifp->if_flags & IFF_PROMISC) != 0) { 2006 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2007 goto allmulti; 2008 } 2009 2010 hashes[0] = hashes[1] = 0x0; 2011 2012 /* 2013 * Program the 64-bit multicast hash filter. 2014 */ 2015 ETHER_FIRST_MULTI(step, ec, enm); 2016 while (enm != NULL) { 2017 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2018 ETHER_ADDR_LEN) != 0) 2019 goto allmulti; 2020 2021 hash = atw_calchash(enm->enm_addrlo); 2022 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2023 ETHER_NEXT_MULTI(step, enm); 2024 sc->sc_opmode |= ATW_NAR_MM; 2025 } 2026 ifp->if_flags &= ~IFF_ALLMULTI; 2027 goto setit; 2028 2029 allmulti: 2030 sc->sc_opmode |= ATW_NAR_MM; 2031 ifp->if_flags |= IFF_ALLMULTI; 2032 hashes[0] = hashes[1] = 0xffffffff; 2033 2034 setit: 2035 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2036 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2037 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2038 DELAY(atw_nar_delay); 2039 ATW_WRITE(sc, ATW_RDR, 0x1); 2040 2041 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2042 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2043 } 2044 2045 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2046 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2047 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2048 * no beacon with the preferred BSSID and SSID in the number of 2049 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2050 */ 2051 static void 2052 atw_write_bssid(struct atw_softc *sc) 2053 { 2054 struct ieee80211com *ic = &sc->sc_ic; 2055 uint8_t *bssid; 2056 2057 bssid = ic->ic_bss->ni_bssid; 2058 2059 ATW_WRITE(sc, ATW_BSSID0, 2060 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2061 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2062 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2063 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2064 2065 ATW_WRITE(sc, ATW_ABDA1, 2066 (ATW_READ(sc, ATW_ABDA1) & 2067 ~(ATW_ABDA1_BSSIDB4_MASK | ATW_ABDA1_BSSIDB5_MASK)) | 2068 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2069 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2070 2071 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2072 ether_sprintf(sc->sc_bssid))); 2073 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2074 2075 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2076 } 2077 2078 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2079 * 16-bit word. 2080 */ 2081 static void 2082 atw_write_sram(struct atw_softc *sc, u_int ofs, uint8_t *buf, u_int buflen) 2083 { 2084 u_int i; 2085 uint8_t *ptr; 2086 2087 memcpy(&sc->sc_sram[ofs], buf, buflen); 2088 2089 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2090 2091 KASSERT(buflen + ofs <= sc->sc_sramlen); 2092 2093 ptr = &sc->sc_sram[ofs]; 2094 2095 for (i = 0; i < buflen; i += 2) { 2096 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2097 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2098 DELAY(atw_writewep_delay); 2099 2100 ATW_WRITE(sc, ATW_WESK, 2101 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2102 DELAY(atw_writewep_delay); 2103 } 2104 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2105 2106 if (sc->sc_if.if_flags & IFF_DEBUG) { 2107 int n_octets = 0; 2108 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2109 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2110 for (i = 0; i < buflen; i++) { 2111 printf(" %02x", ptr[i]); 2112 if (++n_octets % 24 == 0) 2113 printf("\n"); 2114 } 2115 if (n_octets % 24 != 0) 2116 printf("\n"); 2117 } 2118 } 2119 2120 static int 2121 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2122 { 2123 struct atw_softc *sc = ic->ic_ifp->if_softc; 2124 u_int keyix = k->wk_keyix; 2125 2126 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2127 2128 if (keyix >= IEEE80211_WEP_NKID) 2129 return 0; 2130 if (k->wk_keylen != 0) 2131 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2132 2133 return 1; 2134 } 2135 2136 static int 2137 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2138 const uint8_t mac[IEEE80211_ADDR_LEN]) 2139 { 2140 struct atw_softc *sc = ic->ic_ifp->if_softc; 2141 2142 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2143 2144 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2145 return 0; 2146 2147 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2148 2149 return 1; 2150 } 2151 2152 static void 2153 atw_key_update_begin(struct ieee80211com *ic) 2154 { 2155 #ifdef ATW_DEBUG 2156 struct ifnet *ifp = ic->ic_ifp; 2157 struct atw_softc *sc = ifp->if_softc; 2158 #endif 2159 2160 DPRINTF(sc, ("%s:\n", __func__)); 2161 } 2162 2163 static void 2164 atw_key_update_end(struct ieee80211com *ic) 2165 { 2166 struct ifnet *ifp = ic->ic_ifp; 2167 struct atw_softc *sc = ifp->if_softc; 2168 2169 DPRINTF(sc, ("%s:\n", __func__)); 2170 2171 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2172 return; 2173 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2174 return; 2175 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2176 atw_write_wep(sc); 2177 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2178 DELAY(atw_nar_delay); 2179 ATW_WRITE(sc, ATW_RDR, 0x1); 2180 } 2181 2182 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2183 static void 2184 atw_write_wep(struct atw_softc *sc) 2185 { 2186 #if 0 2187 struct ieee80211com *ic = &sc->sc_ic; 2188 uint32_t reg; 2189 int i; 2190 #endif 2191 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2192 uint8_t buf[IEEE80211_WEP_NKID] 2193 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2194 2195 sc->sc_wepctl = 0; 2196 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2197 2198 memset(&buf[0][0], 0, sizeof(buf)); 2199 2200 #if 0 2201 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2202 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2203 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2204 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2205 buf[i][1] = ATW_WEP_ENABLED; 2206 } else { 2207 buf[i][1] = 0; 2208 continue; 2209 } 2210 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2211 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2212 ic->ic_nw_keys[i].wk_keylen - 1); 2213 } 2214 2215 reg = ATW_READ(sc, ATW_MACTEST); 2216 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2217 reg &= ~ATW_MACTEST_KEYID_MASK; 2218 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2219 ATW_WRITE(sc, ATW_MACTEST, reg); 2220 2221 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2222 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2223 2224 switch (sc->sc_rev) { 2225 case ATW_REVISION_AB: 2226 case ATW_REVISION_AF: 2227 /* Bypass WEP on Rx. */ 2228 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2229 break; 2230 default: 2231 break; 2232 } 2233 #endif 2234 2235 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (uint8_t*)&buf[0][0], 2236 sizeof(buf)); 2237 2238 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2239 } 2240 2241 static void 2242 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2243 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 2244 { 2245 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2246 2247 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2248 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2249 return; 2250 2251 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2252 2253 switch (subtype) { 2254 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2255 case IEEE80211_FC0_SUBTYPE_BEACON: 2256 if (ic->ic_opmode == IEEE80211_M_IBSS && 2257 ic->ic_state == IEEE80211_S_RUN) { 2258 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2259 (void)ieee80211_ibss_merge(ni); 2260 } 2261 break; 2262 default: 2263 break; 2264 } 2265 return; 2266 } 2267 2268 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2269 * In ad hoc mode, the SSID is written to the beacons sent by the 2270 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2271 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2272 * indications. 2273 */ 2274 static void 2275 atw_write_ssid(struct atw_softc *sc) 2276 { 2277 struct ieee80211com *ic = &sc->sc_ic; 2278 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2279 * it only expects the element length, not its ID. 2280 */ 2281 uint8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2282 2283 memset(buf, 0, sizeof(buf)); 2284 buf[0] = ic->ic_bss->ni_esslen; 2285 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2286 2287 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2288 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2289 } 2290 2291 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2292 * In ad hoc mode, the supported rates are written to beacons sent by the 2293 * ADM8211. 2294 */ 2295 static void 2296 atw_write_sup_rates(struct atw_softc *sc) 2297 { 2298 struct ieee80211com *ic = &sc->sc_ic; 2299 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2300 * supported rates 2301 */ 2302 uint8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2303 2304 memset(buf, 0, sizeof(buf)); 2305 2306 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2307 2308 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2309 ic->ic_bss->ni_rates.rs_nrates); 2310 2311 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2312 } 2313 2314 /* Start/stop sending beacons. */ 2315 void 2316 atw_start_beacon(struct atw_softc *sc, int start) 2317 { 2318 struct ieee80211com *ic = &sc->sc_ic; 2319 uint16_t chan; 2320 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2321 size_t len; 2322 2323 if (!device_is_active(sc->sc_dev)) 2324 return; 2325 2326 /* start beacons */ 2327 len = sizeof(struct ieee80211_frame) + 2328 8 /* timestamp */ + 2 /* beacon interval */ + 2329 2 /* capability info */ + 2330 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2331 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2332 3 /* DS parameters */ + 2333 IEEE80211_CRC_LEN; 2334 2335 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2336 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2337 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2338 2339 ATW_WRITE(sc, ATW_BCNT, bcnt); 2340 ATW_WRITE(sc, ATW_CAP1, cap1); 2341 2342 if (!start) 2343 return; 2344 2345 /* TBD use ni_capinfo */ 2346 2347 capinfo = 0; 2348 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2349 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2350 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2351 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2352 2353 switch (ic->ic_opmode) { 2354 case IEEE80211_M_IBSS: 2355 len += 4; /* IBSS parameters */ 2356 capinfo |= IEEE80211_CAPINFO_IBSS; 2357 break; 2358 case IEEE80211_M_HOSTAP: 2359 /* XXX 6-byte minimum TIM */ 2360 len += atw_beacon_len_adjust; 2361 capinfo |= IEEE80211_CAPINFO_ESS; 2362 break; 2363 default: 2364 return; 2365 } 2366 2367 /* set listen interval 2368 * XXX do software units agree w/ hardware? 2369 */ 2370 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2371 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2372 2373 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2374 2375 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2376 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2377 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2378 2379 ATW_WRITE(sc, ATW_BCNT, bcnt); 2380 ATW_WRITE(sc, ATW_BPLI, bpli); 2381 ATW_WRITE(sc, ATW_CAP0, cap0); 2382 ATW_WRITE(sc, ATW_CAP1, cap1); 2383 2384 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2385 device_xname(sc->sc_dev), bcnt)); 2386 2387 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2388 device_xname(sc->sc_dev), cap1)); 2389 } 2390 2391 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2392 static inline uint32_t 2393 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2394 { 2395 /* Following the reference driver's lead, I compute 2396 * 2397 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2398 * 2399 * without using 64-bit arithmetic, using the following 2400 * relationship: 2401 * 2402 * (0x100000000 * H + L) % m 2403 * = ((0x100000000 % m) * H + L) % m 2404 * = (((0xffffffff + 1) % m) * H + L) % m 2405 * = ((0xffffffff % m + 1 % m) * H + L) % m 2406 * = ((0xffffffff % m + 1) * H + L) % m 2407 */ 2408 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2409 } 2410 2411 static uint64_t 2412 atw_get_tsft(struct atw_softc *sc) 2413 { 2414 int i; 2415 uint32_t tsfth, tsftl; 2416 for (i = 0; i < 2; i++) { 2417 tsfth = ATW_READ(sc, ATW_TSFTH); 2418 tsftl = ATW_READ(sc, ATW_TSFTL); 2419 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2420 break; 2421 } 2422 return ((uint64_t)tsfth << 32) | tsftl; 2423 } 2424 2425 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2426 * the ieee80211com. 2427 * 2428 * Predict the next target beacon transmission time (TBTT) and 2429 * write it to the ADM8211. 2430 */ 2431 static void 2432 atw_predict_beacon(struct atw_softc *sc) 2433 { 2434 #define TBTTOFS 20 /* TU */ 2435 2436 struct ieee80211com *ic = &sc->sc_ic; 2437 uint64_t tsft; 2438 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2439 union { 2440 uint64_t word; 2441 uint8_t tstamp[8]; 2442 } u; 2443 2444 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2445 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2446 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2447 tsft = atw_get_tsft(sc); 2448 u.word = htole64(tsft); 2449 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2450 sizeof(ic->ic_bss->ni_tstamp)); 2451 } else 2452 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2453 2454 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2455 2456 tsftl = tsft & 0xFFFFFFFF; 2457 tsfth = tsft >> 32; 2458 2459 /* We sent/received the last beacon `past' microseconds 2460 * after the interval divided the TSF timer. 2461 */ 2462 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2463 2464 /* Skip ten beacons so that the TBTT cannot pass before 2465 * we've programmed it. Ten is an arbitrary number. 2466 */ 2467 tbtt = past_even + ival * 10; 2468 2469 ATW_WRITE(sc, ATW_TOFS1, 2470 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2471 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2472 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2473 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2474 #undef TBTTOFS 2475 } 2476 2477 static void 2478 atw_next_scan(void *arg) 2479 { 2480 struct atw_softc *sc = arg; 2481 struct ieee80211com *ic = &sc->sc_ic; 2482 int s; 2483 2484 /* don't call atw_start w/o network interrupts blocked */ 2485 s = splnet(); 2486 if (ic->ic_state == IEEE80211_S_SCAN) 2487 ieee80211_next_scan(ic); 2488 splx(s); 2489 } 2490 2491 /* Synchronize the hardware state with the software state. */ 2492 static int 2493 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2494 { 2495 struct ifnet *ifp = ic->ic_ifp; 2496 struct atw_softc *sc = ifp->if_softc; 2497 int error = 0; 2498 2499 callout_stop(&sc->sc_scan_ch); 2500 2501 switch (nstate) { 2502 case IEEE80211_S_AUTH: 2503 case IEEE80211_S_ASSOC: 2504 atw_write_bssid(sc); 2505 error = atw_tune(sc); 2506 break; 2507 case IEEE80211_S_INIT: 2508 callout_stop(&sc->sc_scan_ch); 2509 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2510 atw_start_beacon(sc, 0); 2511 break; 2512 case IEEE80211_S_SCAN: 2513 error = atw_tune(sc); 2514 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2515 atw_next_scan, sc); 2516 break; 2517 case IEEE80211_S_RUN: 2518 error = atw_tune(sc); 2519 atw_write_bssid(sc); 2520 atw_write_ssid(sc); 2521 atw_write_sup_rates(sc); 2522 2523 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2524 ic->ic_opmode == IEEE80211_M_MONITOR) 2525 break; 2526 2527 /* set listen interval 2528 * XXX do software units agree w/ hardware? 2529 */ 2530 ATW_WRITE(sc, ATW_BPLI, 2531 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2532 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2533 ATW_BPLI_LI_MASK)); 2534 2535 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2536 ATW_READ(sc, ATW_BPLI))); 2537 2538 atw_predict_beacon(sc); 2539 2540 switch (ic->ic_opmode) { 2541 case IEEE80211_M_AHDEMO: 2542 case IEEE80211_M_HOSTAP: 2543 case IEEE80211_M_IBSS: 2544 atw_start_beacon(sc, 1); 2545 break; 2546 case IEEE80211_M_MONITOR: 2547 case IEEE80211_M_STA: 2548 break; 2549 } 2550 2551 break; 2552 } 2553 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2554 } 2555 2556 /* 2557 * atw_add_rxbuf: 2558 * 2559 * Add a receive buffer to the indicated descriptor. 2560 */ 2561 int 2562 atw_add_rxbuf(struct atw_softc *sc, int idx) 2563 { 2564 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2565 struct mbuf *m; 2566 int error; 2567 2568 MGETHDR(m, M_DONTWAIT, MT_DATA); 2569 if (m == NULL) 2570 return (ENOBUFS); 2571 2572 MCLGET(m, M_DONTWAIT); 2573 if ((m->m_flags & M_EXT) == 0) { 2574 m_freem(m); 2575 return (ENOBUFS); 2576 } 2577 2578 if (rxs->rxs_mbuf != NULL) 2579 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2580 2581 rxs->rxs_mbuf = m; 2582 2583 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2584 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2585 BUS_DMA_READ | BUS_DMA_NOWAIT); 2586 if (error) { 2587 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2588 idx, error); 2589 panic("atw_add_rxbuf"); /* XXX */ 2590 } 2591 2592 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2593 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2594 2595 atw_init_rxdesc(sc, idx); 2596 2597 return (0); 2598 } 2599 2600 /* 2601 * Release any queued transmit buffers. 2602 */ 2603 void 2604 atw_txdrain(struct atw_softc *sc) 2605 { 2606 struct atw_txsoft *txs; 2607 2608 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2609 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2610 if (txs->txs_mbuf != NULL) { 2611 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2612 m_freem(txs->txs_mbuf); 2613 txs->txs_mbuf = NULL; 2614 } 2615 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2616 sc->sc_txfree += txs->txs_ndescs; 2617 } 2618 2619 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2620 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2621 sc->sc_txfree != ATW_NTXDESC)); 2622 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2623 sc->sc_tx_timer = 0; 2624 } 2625 2626 /* 2627 * atw_stop: [ ifnet interface function ] 2628 * 2629 * Stop transmission on the interface. 2630 */ 2631 void 2632 atw_stop(struct ifnet *ifp, int disable) 2633 { 2634 struct atw_softc *sc = ifp->if_softc; 2635 struct ieee80211com *ic = &sc->sc_ic; 2636 2637 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2638 2639 if (device_is_active(sc->sc_dev)) { 2640 /* Disable interrupts. */ 2641 ATW_WRITE(sc, ATW_IER, 0); 2642 2643 /* Stop the transmit and receive processes. */ 2644 ATW_WRITE(sc, ATW_NAR, 0); 2645 DELAY(atw_nar_delay); 2646 ATW_WRITE(sc, ATW_TDBD, 0); 2647 ATW_WRITE(sc, ATW_TDBP, 0); 2648 ATW_WRITE(sc, ATW_RDB, 0); 2649 } 2650 2651 sc->sc_opmode = 0; 2652 2653 atw_txdrain(sc); 2654 2655 /* 2656 * Mark the interface down and cancel the watchdog timer. 2657 */ 2658 ifp->if_flags &= ~IFF_RUNNING; 2659 ifp->if_timer = 0; 2660 2661 if (disable) 2662 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2663 } 2664 2665 /* 2666 * atw_rxdrain: 2667 * 2668 * Drain the receive queue. 2669 */ 2670 void 2671 atw_rxdrain(struct atw_softc *sc) 2672 { 2673 struct atw_rxsoft *rxs; 2674 int i; 2675 2676 for (i = 0; i < ATW_NRXDESC; i++) { 2677 rxs = &sc->sc_rxsoft[i]; 2678 if (rxs->rxs_mbuf == NULL) 2679 continue; 2680 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2681 m_freem(rxs->rxs_mbuf); 2682 rxs->rxs_mbuf = NULL; 2683 } 2684 } 2685 2686 /* 2687 * atw_detach: 2688 * 2689 * Detach an ADM8211 interface. 2690 */ 2691 int 2692 atw_detach(struct atw_softc *sc) 2693 { 2694 struct ifnet *ifp = &sc->sc_if; 2695 struct atw_rxsoft *rxs; 2696 struct atw_txsoft *txs; 2697 int i; 2698 2699 /* 2700 * Succeed now if there isn't any work to do. 2701 */ 2702 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2703 return (0); 2704 2705 pmf_device_deregister(sc->sc_dev); 2706 2707 callout_stop(&sc->sc_scan_ch); 2708 2709 ieee80211_ifdetach(&sc->sc_ic); 2710 if_detach(ifp); 2711 2712 for (i = 0; i < ATW_NRXDESC; i++) { 2713 rxs = &sc->sc_rxsoft[i]; 2714 if (rxs->rxs_mbuf != NULL) { 2715 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2716 m_freem(rxs->rxs_mbuf); 2717 rxs->rxs_mbuf = NULL; 2718 } 2719 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2720 } 2721 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2722 txs = &sc->sc_txsoft[i]; 2723 if (txs->txs_mbuf != NULL) { 2724 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2725 m_freem(txs->txs_mbuf); 2726 txs->txs_mbuf = NULL; 2727 } 2728 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2729 } 2730 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2731 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2732 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2733 sizeof(struct atw_control_data)); 2734 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2735 2736 if (sc->sc_srom) 2737 free(sc->sc_srom, M_DEVBUF); 2738 2739 atw_evcnt_detach(sc); 2740 2741 if (sc->sc_soft_ih != NULL) { 2742 softint_disestablish(sc->sc_soft_ih); 2743 sc->sc_soft_ih = NULL; 2744 } 2745 2746 return (0); 2747 } 2748 2749 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2750 bool 2751 atw_shutdown(device_t self, int flags) 2752 { 2753 struct atw_softc *sc = device_private(self); 2754 2755 atw_stop(&sc->sc_if, 1); 2756 return true; 2757 } 2758 2759 #if 0 2760 static void 2761 atw_workaround1(struct atw_softc *sc) 2762 { 2763 uint32_t test1; 2764 2765 test1 = ATW_READ(sc, ATW_TEST1); 2766 2767 sc->sc_misc_ev.ev_count++; 2768 2769 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2770 sc->sc_rxpkt1in_ev.ev_count++; 2771 return; 2772 } 2773 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2774 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2775 sc->sc_rxamatch_ev.ev_count++; 2776 return; 2777 } 2778 sc->sc_workaround1_ev.ev_count++; 2779 (void)atw_init(&sc->sc_if); 2780 } 2781 #endif 2782 2783 int 2784 atw_intr(void *arg) 2785 { 2786 struct atw_softc *sc = arg; 2787 struct ifnet *ifp = &sc->sc_if; 2788 uint32_t status; 2789 2790 #ifdef DEBUG 2791 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2792 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2793 #endif 2794 2795 /* 2796 * If the interface isn't running, the interrupt couldn't 2797 * possibly have come from us. 2798 */ 2799 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2800 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2801 return (0); 2802 2803 status = ATW_READ(sc, ATW_STSR); 2804 if (status == 0) 2805 return 0; 2806 2807 if ((status & sc->sc_inten) == 0) { 2808 ATW_WRITE(sc, ATW_STSR, status); 2809 return 0; 2810 } 2811 2812 /* Disable interrupts */ 2813 ATW_WRITE(sc, ATW_IER, 0); 2814 2815 softint_schedule(sc->sc_soft_ih); 2816 return 1; 2817 } 2818 2819 void 2820 atw_softintr(void *arg) 2821 { 2822 struct atw_softc *sc = arg; 2823 struct ifnet *ifp = &sc->sc_if; 2824 uint32_t status, rxstatus, txstatus, linkstatus; 2825 int txthresh, s; 2826 2827 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2828 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2829 return; 2830 2831 for (;;) { 2832 status = ATW_READ(sc, ATW_STSR); 2833 2834 if (status) 2835 ATW_WRITE(sc, ATW_STSR, status); 2836 2837 #ifdef ATW_DEBUG 2838 #define PRINTINTR(flag) do { \ 2839 if ((status & flag) != 0) { \ 2840 printf("%s" #flag, delim); \ 2841 delim = ","; \ 2842 } \ 2843 } while (0) 2844 2845 if (atw_debug > 1 && status) { 2846 const char *delim = "<"; 2847 2848 printf("%s: reg[STSR] = %x", 2849 device_xname(sc->sc_dev), status); 2850 2851 PRINTINTR(ATW_INTR_FBE); 2852 PRINTINTR(ATW_INTR_LINKOFF); 2853 PRINTINTR(ATW_INTR_LINKON); 2854 PRINTINTR(ATW_INTR_RCI); 2855 PRINTINTR(ATW_INTR_RDU); 2856 PRINTINTR(ATW_INTR_REIS); 2857 PRINTINTR(ATW_INTR_RPS); 2858 PRINTINTR(ATW_INTR_TCI); 2859 PRINTINTR(ATW_INTR_TDU); 2860 PRINTINTR(ATW_INTR_TLT); 2861 PRINTINTR(ATW_INTR_TPS); 2862 PRINTINTR(ATW_INTR_TRT); 2863 PRINTINTR(ATW_INTR_TUF); 2864 PRINTINTR(ATW_INTR_BCNTC); 2865 PRINTINTR(ATW_INTR_ATIME); 2866 PRINTINTR(ATW_INTR_TBTT); 2867 PRINTINTR(ATW_INTR_TSCZ); 2868 PRINTINTR(ATW_INTR_TSFTF); 2869 printf(">\n"); 2870 } 2871 #undef PRINTINTR 2872 #endif /* ATW_DEBUG */ 2873 2874 if ((status & sc->sc_inten) == 0) 2875 break; 2876 2877 rxstatus = status & sc->sc_rxint_mask; 2878 txstatus = status & sc->sc_txint_mask; 2879 linkstatus = status & sc->sc_linkint_mask; 2880 2881 if (linkstatus) { 2882 atw_linkintr(sc, linkstatus); 2883 } 2884 2885 if (rxstatus) { 2886 /* Grab any new packets. */ 2887 atw_rxintr(sc); 2888 2889 if (rxstatus & ATW_INTR_RDU) { 2890 printf("%s: receive ring overrun\n", 2891 device_xname(sc->sc_dev)); 2892 /* Get the receive process going again. */ 2893 ATW_WRITE(sc, ATW_RDR, 0x1); 2894 } 2895 } 2896 2897 if (txstatus) { 2898 /* Sweep up transmit descriptors. */ 2899 atw_txintr(sc, txstatus); 2900 2901 if (txstatus & ATW_INTR_TLT) { 2902 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2903 device_xname(sc->sc_dev))); 2904 (void)atw_init(&sc->sc_if); 2905 } 2906 2907 if (txstatus & ATW_INTR_TRT) { 2908 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2909 device_xname(sc->sc_dev))); 2910 } 2911 2912 /* If Tx under-run, increase our transmit threshold 2913 * if another is available. 2914 */ 2915 txthresh = sc->sc_txthresh + 1; 2916 if ((txstatus & ATW_INTR_TUF) && 2917 sc->sc_txth[txthresh].txth_name != NULL) { 2918 /* Idle the transmit process. */ 2919 atw_idle(sc, ATW_NAR_ST); 2920 2921 sc->sc_txthresh = txthresh; 2922 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2923 sc->sc_opmode |= 2924 sc->sc_txth[txthresh].txth_opmode; 2925 printf("%s: transmit underrun; new " 2926 "threshold: %s\n", device_xname(sc->sc_dev), 2927 sc->sc_txth[txthresh].txth_name); 2928 2929 /* Set the new threshold and restart 2930 * the transmit process. 2931 */ 2932 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2933 DELAY(atw_nar_delay); 2934 ATW_WRITE(sc, ATW_TDR, 0x1); 2935 /* XXX Log every Nth underrun from 2936 * XXX now on? 2937 */ 2938 } 2939 } 2940 2941 if (status & (ATW_INTR_TPS | ATW_INTR_RPS)) { 2942 if (status & ATW_INTR_TPS) 2943 printf("%s: transmit process stopped\n", 2944 device_xname(sc->sc_dev)); 2945 if (status & ATW_INTR_RPS) 2946 printf("%s: receive process stopped\n", 2947 device_xname(sc->sc_dev)); 2948 s = splnet(); 2949 (void)atw_init(ifp); 2950 splx(s); 2951 break; 2952 } 2953 2954 if (status & ATW_INTR_FBE) { 2955 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2956 s = splnet(); 2957 (void)atw_init(ifp); 2958 splx(s); 2959 break; 2960 } 2961 2962 /* 2963 * Not handled: 2964 * 2965 * Transmit buffer unavailable -- normal 2966 * condition, nothing to do, really. 2967 * 2968 * Early receive interrupt -- not available on 2969 * all chips, we just use RI. We also only 2970 * use single-segment receive DMA, so this 2971 * is mostly useless. 2972 * 2973 * TBD others 2974 */ 2975 } 2976 2977 /* Try to get more packets going. */ 2978 s = splnet(); 2979 atw_start(ifp); 2980 splx(s); 2981 2982 /* Enable interrupts */ 2983 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 2984 } 2985 2986 /* 2987 * atw_idle: 2988 * 2989 * Cause the transmit and/or receive processes to go idle. 2990 * 2991 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2992 * process in STSR if I clear SR or ST after the process has already 2993 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2994 * do not seem to be too reliable. Perhaps I have the sense of the 2995 * Rx bits switched with the Tx bits? 2996 */ 2997 void 2998 atw_idle(struct atw_softc *sc, uint32_t bits) 2999 { 3000 uint32_t ackmask = 0, opmode, stsr, test0; 3001 int i, s; 3002 3003 s = splnet(); 3004 3005 opmode = sc->sc_opmode & ~bits; 3006 3007 if (bits & ATW_NAR_SR) 3008 ackmask |= ATW_INTR_RPS; 3009 3010 if (bits & ATW_NAR_ST) { 3011 ackmask |= ATW_INTR_TPS; 3012 /* set ATW_NAR_HF to flush TX FIFO. */ 3013 opmode |= ATW_NAR_HF; 3014 } 3015 3016 ATW_WRITE(sc, ATW_NAR, opmode); 3017 DELAY(atw_nar_delay); 3018 3019 for (i = 0; i < 1000; i++) { 3020 stsr = ATW_READ(sc, ATW_STSR); 3021 if ((stsr & ackmask) == ackmask) 3022 break; 3023 DELAY(10); 3024 } 3025 3026 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3027 3028 if ((stsr & ackmask) == ackmask) 3029 goto out; 3030 3031 test0 = ATW_READ(sc, ATW_TEST0); 3032 3033 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3034 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3035 printf("%s: transmit process not idle [%s]\n", 3036 device_xname(sc->sc_dev), 3037 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3038 printf("%s: bits %08x test0 %08x stsr %08x\n", 3039 device_xname(sc->sc_dev), bits, test0, stsr); 3040 } 3041 3042 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3043 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3044 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3045 device_xname(sc->sc_dev), 3046 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3047 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3048 device_xname(sc->sc_dev), bits, test0, stsr)); 3049 } 3050 out: 3051 if ((bits & ATW_NAR_ST) != 0) 3052 atw_txdrain(sc); 3053 splx(s); 3054 return; 3055 } 3056 3057 /* 3058 * atw_linkintr: 3059 * 3060 * Helper; handle link-status interrupts. 3061 */ 3062 void 3063 atw_linkintr(struct atw_softc *sc, uint32_t linkstatus) 3064 { 3065 struct ieee80211com *ic = &sc->sc_ic; 3066 3067 if (ic->ic_state != IEEE80211_S_RUN) 3068 return; 3069 3070 if (linkstatus & ATW_INTR_LINKON) { 3071 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3072 sc->sc_rescan_timer = 0; 3073 } else if (linkstatus & ATW_INTR_LINKOFF) { 3074 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3075 if (ic->ic_opmode != IEEE80211_M_STA) 3076 return; 3077 sc->sc_rescan_timer = 3; 3078 sc->sc_if.if_timer = 1; 3079 } 3080 } 3081 3082 #if 0 3083 static inline int 3084 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3085 { 3086 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3087 return 0; 3088 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3089 return 0; 3090 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3091 } 3092 #endif 3093 3094 /* 3095 * atw_rxintr: 3096 * 3097 * Helper; handle receive interrupts. 3098 */ 3099 void 3100 atw_rxintr(struct atw_softc *sc) 3101 { 3102 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3103 struct ieee80211com *ic = &sc->sc_ic; 3104 struct ieee80211_node *ni; 3105 struct ieee80211_frame_min *wh; 3106 struct ifnet *ifp = &sc->sc_if; 3107 struct atw_rxsoft *rxs; 3108 struct mbuf *m; 3109 uint32_t rxstat; 3110 int i, s, len, rate, rate0; 3111 uint32_t rssi, ctlrssi; 3112 3113 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3114 rxs = &sc->sc_rxsoft[i]; 3115 3116 ATW_CDRXSYNC(sc, i, 3117 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3118 3119 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3120 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3121 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3122 3123 if (rxstat & ATW_RXSTAT_OWN) { 3124 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3125 break; 3126 } 3127 3128 sc->sc_rxptr = ATW_NEXTRX(i); 3129 3130 DPRINTF3(sc, 3131 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3132 device_xname(sc->sc_dev), 3133 rxstat, ctlrssi, 3134 le32toh(sc->sc_rxdescs[i].ar_buf1), 3135 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3136 3137 /* 3138 * Make sure the packet fits in one buffer. This should 3139 * always be the case. 3140 */ 3141 if ((rxstat & (ATW_RXSTAT_FS | ATW_RXSTAT_LS)) != 3142 (ATW_RXSTAT_FS | ATW_RXSTAT_LS)) { 3143 printf("%s: incoming packet spilled, resetting\n", 3144 device_xname(sc->sc_dev)); 3145 (void)atw_init(ifp); 3146 return; 3147 } 3148 3149 /* 3150 * If an error occurred, update stats, clear the status 3151 * word, and leave the packet buffer in place. It will 3152 * simply be reused the next time the ring comes around. 3153 */ 3154 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3155 #define PRINTERR(bit, str) \ 3156 if (rxstat & (bit)) \ 3157 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3158 str) 3159 ifp->if_ierrors++; 3160 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3161 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3162 #if 0 3163 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3164 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3165 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3166 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3167 #endif 3168 #undef PRINTERR 3169 atw_init_rxdesc(sc, i); 3170 continue; 3171 } 3172 3173 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3174 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3175 3176 /* 3177 * No errors; receive the packet. Note the ADM8211 3178 * includes the CRC in promiscuous mode. 3179 */ 3180 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3181 3182 /* 3183 * Allocate a new mbuf cluster. If that fails, we are 3184 * out of memory, and must drop the packet and recycle 3185 * the buffer that's already attached to this descriptor. 3186 */ 3187 m = rxs->rxs_mbuf; 3188 if (atw_add_rxbuf(sc, i) != 0) { 3189 ifp->if_ierrors++; 3190 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3191 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3192 atw_init_rxdesc(sc, i); 3193 continue; 3194 } 3195 3196 ifp->if_ipackets++; 3197 m_set_rcvif(m, ifp); 3198 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3199 3200 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3201 3202 /* The RSSI comes straight from a register in the 3203 * baseband processor. I know that for the RF3000, 3204 * the RSSI register also contains the antenna-selection 3205 * bits. Mask those off. 3206 * 3207 * TBD Treat other basebands. 3208 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3209 */ 3210 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3211 rssi = ctlrssi & RF3000_RSSI_MASK; 3212 else 3213 rssi = ctlrssi; 3214 3215 s = splnet(); 3216 3217 /* Pass this up to any BPF listeners. */ 3218 if (sc->sc_radiobpf != NULL) { 3219 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3220 3221 tap->ar_rate = rate; 3222 3223 /* TBD verify units are dB */ 3224 tap->ar_antsignal = (int)rssi; 3225 if (sc->sc_opmode & ATW_NAR_PR) 3226 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3227 else 3228 tap->ar_flags = 0; 3229 3230 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3231 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3232 3233 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), 3234 m, BPF_D_IN); 3235 } 3236 3237 sc->sc_recv_ev.ev_count++; 3238 3239 if ((rxstat & (ATW_RXSTAT_CRC16E | ATW_RXSTAT_CRC32E | 3240 ATW_RXSTAT_ICVE | ATW_RXSTAT_SFDE | ATW_RXSTAT_SIGE)) 3241 != 0) { 3242 if (rxstat & ATW_RXSTAT_CRC16E) 3243 sc->sc_crc16e_ev.ev_count++; 3244 if (rxstat & ATW_RXSTAT_CRC32E) 3245 sc->sc_crc32e_ev.ev_count++; 3246 if (rxstat & ATW_RXSTAT_ICVE) 3247 sc->sc_icve_ev.ev_count++; 3248 if (rxstat & ATW_RXSTAT_SFDE) 3249 sc->sc_sfde_ev.ev_count++; 3250 if (rxstat & ATW_RXSTAT_SIGE) 3251 sc->sc_sige_ev.ev_count++; 3252 ifp->if_ierrors++; 3253 m_freem(m); 3254 splx(s); 3255 continue; 3256 } 3257 3258 if (sc->sc_opmode & ATW_NAR_PR) 3259 m_adj(m, -IEEE80211_CRC_LEN); 3260 3261 wh = mtod(m, struct ieee80211_frame_min *); 3262 ni = ieee80211_find_rxnode(ic, wh); 3263 #if 0 3264 if (atw_hw_decrypted(sc, wh)) { 3265 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3266 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3267 } 3268 #endif 3269 ieee80211_input(ic, m, ni, (int)rssi, 0); 3270 ieee80211_free_node(ni); 3271 splx(s); 3272 } 3273 } 3274 3275 /* 3276 * atw_txintr: 3277 * 3278 * Helper; handle transmit interrupts. 3279 */ 3280 void 3281 atw_txintr(struct atw_softc *sc, uint32_t status) 3282 { 3283 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3284 struct ifnet *ifp = &sc->sc_if; 3285 struct atw_txsoft *txs; 3286 uint32_t txstat; 3287 int s; 3288 3289 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3290 device_xname(sc->sc_dev), sc->sc_flags)); 3291 3292 s = splnet(); 3293 3294 /* 3295 * Go through our Tx list and free mbufs for those 3296 * frames that have been transmitted. 3297 */ 3298 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3299 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3301 3302 #ifdef ATW_DEBUG 3303 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3304 int i; 3305 printf(" txsoft %p transmit chain:\n", txs); 3306 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3307 txs->txs_ndescs - 1, 3308 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3309 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3310 printf(" descriptor %d:\n", i); 3311 printf(" at_status: 0x%08x\n", 3312 le32toh(sc->sc_txdescs[i].at_stat)); 3313 printf(" at_flags: 0x%08x\n", 3314 le32toh(sc->sc_txdescs[i].at_flags)); 3315 printf(" at_buf1: 0x%08x\n", 3316 le32toh(sc->sc_txdescs[i].at_buf1)); 3317 printf(" at_buf2: 0x%08x\n", 3318 le32toh(sc->sc_txdescs[i].at_buf2)); 3319 if (i == txs->txs_lastdesc) 3320 break; 3321 } 3322 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3323 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3324 } 3325 #endif 3326 3327 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3328 if (txstat & ATW_TXSTAT_OWN) { 3329 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3330 BUS_DMASYNC_PREREAD); 3331 break; 3332 } 3333 3334 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3335 3336 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3337 0, txs->txs_dmamap->dm_mapsize, 3338 BUS_DMASYNC_POSTWRITE); 3339 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3340 m_freem(txs->txs_mbuf); 3341 txs->txs_mbuf = NULL; 3342 3343 sc->sc_txfree += txs->txs_ndescs; 3344 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3345 3346 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3347 sc->sc_tx_timer = 0; 3348 ifp->if_flags &= ~IFF_OACTIVE; 3349 3350 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3351 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3352 snprintb(txstat_buf, sizeof(txstat_buf), 3353 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3354 printf("%s: txstat %s %" __PRIuBITS "\n", 3355 device_xname(sc->sc_dev), txstat_buf, 3356 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3357 } 3358 3359 sc->sc_xmit_ev.ev_count++; 3360 3361 /* 3362 * Check for errors and collisions. 3363 */ 3364 if (txstat & ATW_TXSTAT_TUF) 3365 sc->sc_tuf_ev.ev_count++; 3366 if (txstat & ATW_TXSTAT_TLT) 3367 sc->sc_tlt_ev.ev_count++; 3368 if (txstat & ATW_TXSTAT_TRT) 3369 sc->sc_trt_ev.ev_count++; 3370 if (txstat & ATW_TXSTAT_TRO) 3371 sc->sc_tro_ev.ev_count++; 3372 if (txstat & ATW_TXSTAT_SOFBR) 3373 sc->sc_sofbr_ev.ev_count++; 3374 3375 if ((txstat & ATW_TXSTAT_ES) == 0) 3376 ifp->if_collisions += 3377 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3378 else 3379 ifp->if_oerrors++; 3380 3381 ifp->if_opackets++; 3382 } 3383 3384 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3385 3386 splx(s); 3387 } 3388 3389 /* 3390 * atw_watchdog: [ifnet interface function] 3391 * 3392 * Watchdog timer handler. 3393 */ 3394 void 3395 atw_watchdog(struct ifnet *ifp) 3396 { 3397 struct atw_softc *sc = ifp->if_softc; 3398 struct ieee80211com *ic = &sc->sc_ic; 3399 3400 ifp->if_timer = 0; 3401 if (!device_is_active(sc->sc_dev)) 3402 return; 3403 3404 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3405 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3406 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3407 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3408 printf("%s: transmit timeout\n", ifp->if_xname); 3409 ifp->if_oerrors++; 3410 (void)atw_init(ifp); 3411 atw_start(ifp); 3412 } 3413 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3414 ifp->if_timer = 1; 3415 ieee80211_watchdog(ic); 3416 } 3417 3418 static void 3419 atw_evcnt_detach(struct atw_softc *sc) 3420 { 3421 evcnt_detach(&sc->sc_sige_ev); 3422 evcnt_detach(&sc->sc_sfde_ev); 3423 evcnt_detach(&sc->sc_icve_ev); 3424 evcnt_detach(&sc->sc_crc32e_ev); 3425 evcnt_detach(&sc->sc_crc16e_ev); 3426 evcnt_detach(&sc->sc_recv_ev); 3427 3428 evcnt_detach(&sc->sc_tuf_ev); 3429 evcnt_detach(&sc->sc_tro_ev); 3430 evcnt_detach(&sc->sc_trt_ev); 3431 evcnt_detach(&sc->sc_tlt_ev); 3432 evcnt_detach(&sc->sc_sofbr_ev); 3433 evcnt_detach(&sc->sc_xmit_ev); 3434 3435 evcnt_detach(&sc->sc_rxpkt1in_ev); 3436 evcnt_detach(&sc->sc_rxamatch_ev); 3437 evcnt_detach(&sc->sc_workaround1_ev); 3438 evcnt_detach(&sc->sc_misc_ev); 3439 } 3440 3441 static void 3442 atw_evcnt_attach(struct atw_softc *sc) 3443 { 3444 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3445 NULL, sc->sc_if.if_xname, "recv"); 3446 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3447 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3448 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3449 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3450 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3451 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3452 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3453 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3454 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3455 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3456 3457 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3458 NULL, sc->sc_if.if_xname, "xmit"); 3459 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3460 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3461 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3462 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3463 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3464 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3465 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3466 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3467 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3468 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3469 3470 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3471 NULL, sc->sc_if.if_xname, "misc"); 3472 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3473 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3474 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3475 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3476 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3477 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3478 } 3479 3480 #ifdef ATW_DEBUG 3481 static void 3482 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3483 { 3484 struct atw_softc *sc = ifp->if_softc; 3485 struct mbuf *m; 3486 int i, noctets = 0; 3487 3488 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3489 m0->m_pkthdr.len); 3490 3491 for (m = m0; m; m = m->m_next) { 3492 if (m->m_len == 0) 3493 continue; 3494 for (i = 0; i < m->m_len; i++) { 3495 printf(" %02x", ((uint8_t*)m->m_data)[i]); 3496 if (++noctets % 24 == 0) 3497 printf("\n"); 3498 } 3499 } 3500 printf("%s%s: %d bytes emitted\n", 3501 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3502 } 3503 #endif /* ATW_DEBUG */ 3504 3505 /* 3506 * atw_start: [ifnet interface function] 3507 * 3508 * Start packet transmission on the interface. 3509 */ 3510 void 3511 atw_start(struct ifnet *ifp) 3512 { 3513 struct atw_softc *sc = ifp->if_softc; 3514 struct ieee80211_key *k; 3515 struct ieee80211com *ic = &sc->sc_ic; 3516 struct ieee80211_node *ni; 3517 struct ieee80211_frame_min *whm; 3518 struct ieee80211_frame *wh; 3519 struct atw_frame *hh; 3520 uint16_t hdrctl; 3521 struct mbuf *m0, *m; 3522 struct atw_txsoft *txs; 3523 struct atw_txdesc *txd; 3524 int npkt, rate; 3525 bus_dmamap_t dmamap; 3526 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3527 3528 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3529 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3530 3531 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3532 return; 3533 3534 /* 3535 * Remember the previous number of free descriptors and 3536 * the first descriptor we'll use. 3537 */ 3538 ofree = sc->sc_txfree; 3539 firsttx = lasttx = sc->sc_txnext; 3540 3541 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3542 device_xname(sc->sc_dev), ofree, firsttx)); 3543 3544 /* 3545 * Loop through the send queue, setting up transmit descriptors 3546 * until we drain the queue, or use up all available transmit 3547 * descriptors. 3548 */ 3549 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3550 sc->sc_txfree != 0) { 3551 3552 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3553 3554 /* 3555 * Grab a packet off the management queue, if it 3556 * is not empty. Otherwise, from the data queue. 3557 */ 3558 IF_DEQUEUE(&ic->ic_mgtq, m0); 3559 if (m0 != NULL) { 3560 ni = M_GETCTX(m0, struct ieee80211_node *); 3561 M_CLEARCTX(m0); 3562 } else if (ic->ic_state != IEEE80211_S_RUN) 3563 break; /* send no data until associated */ 3564 else { 3565 IFQ_DEQUEUE(&ifp->if_snd, m0); 3566 if (m0 == NULL) 3567 break; 3568 bpf_mtap(ifp, m0, BPF_D_OUT); 3569 ni = ieee80211_find_txnode(ic, 3570 mtod(m0, struct ether_header *)->ether_dhost); 3571 if (ni == NULL) { 3572 ifp->if_oerrors++; 3573 break; 3574 } 3575 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3576 ieee80211_free_node(ni); 3577 ifp->if_oerrors++; 3578 break; 3579 } 3580 } 3581 3582 rate = MAX(ieee80211_get_rate(ni), 2); 3583 3584 whm = mtod(m0, struct ieee80211_frame_min *); 3585 3586 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3587 k = NULL; 3588 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3589 m_freem(m0); 3590 ieee80211_free_node(ni); 3591 ifp->if_oerrors++; 3592 break; 3593 } 3594 #if 0 3595 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3596 m0->m_pkthdr.len > ic->ic_fragthreshold) 3597 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3598 #endif 3599 3600 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3601 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3602 3603 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3604 ic->ic_flags, ic->ic_fragthreshold, rate, 3605 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3606 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3607 m_freem(m0); 3608 break; 3609 } 3610 3611 /* XXX Misleading if fragmentation is enabled. Better 3612 * to fragment in software? 3613 */ 3614 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3615 3616 /* 3617 * Pass the packet to any BPF listeners. 3618 */ 3619 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3620 3621 if (sc->sc_radiobpf != NULL) { 3622 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3623 3624 tap->at_rate = rate; 3625 3626 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), 3627 m0, BPF_D_OUT); 3628 } 3629 3630 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3631 3632 if (ni != NULL) 3633 ieee80211_free_node(ni); 3634 3635 if (m0 == NULL) { 3636 ifp->if_oerrors++; 3637 break; 3638 } 3639 3640 /* just to make sure. */ 3641 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3642 3643 if (m0 == NULL) { 3644 ifp->if_oerrors++; 3645 break; 3646 } 3647 3648 hh = mtod(m0, struct atw_frame *); 3649 wh = &hh->atw_ihdr; 3650 3651 /* Copy everything we need from the 802.11 header: 3652 * Frame Control; address 1, address 3, or addresses 3653 * 3 and 4. NIC fills in BSSID, SA. 3654 */ 3655 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3656 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3657 panic("%s: illegal WDS frame", 3658 device_xname(sc->sc_dev)); 3659 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3660 } else 3661 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3662 3663 *(uint16_t*)hh->atw_fc = *(uint16_t*)wh->i_fc; 3664 3665 /* initialize remaining Tx parameters */ 3666 memset(&hh->u, 0, sizeof(hh->u)); 3667 3668 hh->atw_rate = rate * 5; 3669 /* XXX this could be incorrect if M_FCS. _encap should 3670 * probably strip FCS just in case it sticks around in 3671 * bridged packets. 3672 */ 3673 hh->atw_service = 0x00; /* XXX guess */ 3674 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3675 sizeof(struct atw_frame)); 3676 3677 /* never fragment multicast frames */ 3678 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3679 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3680 else { 3681 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3682 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3683 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3684 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3685 } 3686 3687 hh->atw_rtylmt = 3; 3688 #if 0 3689 if (do_encrypt) { 3690 hdrctl |= htole16(ATW_HDRCTL_WEP); 3691 hh->atw_keyid = ic->ic_def_txkey; 3692 } 3693 #endif 3694 3695 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3696 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3697 if (txs->txs_d0.d_residue) 3698 hh->atw_head_plcplen |= htole16(0x8000); 3699 if (txs->txs_dn.d_residue) 3700 hh->atw_tail_plcplen |= htole16(0x8000); 3701 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3702 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3703 3704 hh->atw_hdrctl = hdrctl; 3705 hh->atw_fragnum = npkt << 4; 3706 #ifdef ATW_DEBUG 3707 3708 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3709 printf("%s: dst = %s, rate = 0x%02x, " 3710 "service = 0x%02x, paylen = 0x%04x\n", 3711 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3712 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3713 3714 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3715 "dur1 = 0x%04x, dur2 = 0x%04x, " 3716 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3717 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3718 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3719 hh->atw_tail_dur, hh->atw_head_dur); 3720 3721 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3722 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3723 device_xname(sc->sc_dev), hh->atw_hdrctl, 3724 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3725 3726 printf("%s: keyid = %d\n", 3727 device_xname(sc->sc_dev), hh->atw_keyid); 3728 3729 atw_dump_pkt(ifp, m0); 3730 } 3731 #endif /* ATW_DEBUG */ 3732 3733 dmamap = txs->txs_dmamap; 3734 3735 /* 3736 * Load the DMA map. Copy and try (once) again if the packet 3737 * didn't fit in the alloted number of segments. 3738 */ 3739 for (first = 1; 3740 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3741 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 && first; 3742 first = 0) { 3743 MGETHDR(m, M_DONTWAIT, MT_DATA); 3744 if (m == NULL) { 3745 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3746 break; 3747 } 3748 if (m0->m_pkthdr.len > MHLEN) { 3749 MCLGET(m, M_DONTWAIT); 3750 if ((m->m_flags & M_EXT) == 0) { 3751 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3752 "cluster\n"); 3753 m_freem(m); 3754 break; 3755 } 3756 } 3757 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3758 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3759 m_freem(m0); 3760 m0 = m; 3761 m = NULL; 3762 } 3763 if (error != 0) { 3764 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3765 "error = %d\n", error); 3766 m_freem(m0); 3767 break; 3768 } 3769 3770 /* 3771 * Ensure we have enough descriptors free to describe 3772 * the packet. 3773 */ 3774 if (dmamap->dm_nsegs > sc->sc_txfree) { 3775 /* 3776 * Not enough free descriptors to transmit 3777 * this packet. Unload the DMA map and 3778 * drop the packet. Notify the upper layer 3779 * that there are no more slots left. 3780 * 3781 * XXX We could allocate an mbuf and copy, but 3782 * XXX it is worth it? 3783 */ 3784 bus_dmamap_unload(sc->sc_dmat, dmamap); 3785 m_freem(m0); 3786 break; 3787 } 3788 3789 /* 3790 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3791 */ 3792 3793 /* Sync the DMA map. */ 3794 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3795 BUS_DMASYNC_PREWRITE); 3796 3797 /* XXX arbitrary retry limit; 8 because I have seen it in 3798 * use already and maybe 0 means "no tries" ! 3799 */ 3800 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3801 3802 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3803 device_xname(sc->sc_dev), rate * 5)); 3804 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3805 3806 /* 3807 * Initialize the transmit descriptors. 3808 */ 3809 for (nexttx = sc->sc_txnext, seg = 0; 3810 seg < dmamap->dm_nsegs; 3811 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3812 /* 3813 * If this is the first descriptor we're 3814 * enqueueing, don't set the OWN bit just 3815 * yet. That could cause a race condition. 3816 * We'll do it below. 3817 */ 3818 txd = &sc->sc_txdescs[nexttx]; 3819 txd->at_ctl = ctl | 3820 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3821 3822 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3823 txd->at_flags = 3824 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3825 ATW_TXFLAG_TBS1_MASK)) | 3826 ((nexttx == (ATW_NTXDESC - 1)) 3827 ? htole32(ATW_TXFLAG_TER) : 0); 3828 lasttx = nexttx; 3829 } 3830 3831 /* Set `first segment' and `last segment' appropriately. */ 3832 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3833 htole32(ATW_TXFLAG_FS); 3834 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3835 3836 #ifdef ATW_DEBUG 3837 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3838 printf(" txsoft %p transmit chain:\n", txs); 3839 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3840 printf(" descriptor %d:\n", seg); 3841 printf(" at_ctl: 0x%08x\n", 3842 le32toh(sc->sc_txdescs[seg].at_ctl)); 3843 printf(" at_flags: 0x%08x\n", 3844 le32toh(sc->sc_txdescs[seg].at_flags)); 3845 printf(" at_buf1: 0x%08x\n", 3846 le32toh(sc->sc_txdescs[seg].at_buf1)); 3847 printf(" at_buf2: 0x%08x\n", 3848 le32toh(sc->sc_txdescs[seg].at_buf2)); 3849 if (seg == lasttx) 3850 break; 3851 } 3852 } 3853 #endif 3854 3855 /* Sync the descriptors we're using. */ 3856 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3858 3859 /* 3860 * Store a pointer to the packet so we can free it later, 3861 * and remember what txdirty will be once the packet is 3862 * done. 3863 */ 3864 txs->txs_mbuf = m0; 3865 txs->txs_firstdesc = sc->sc_txnext; 3866 txs->txs_lastdesc = lasttx; 3867 txs->txs_ndescs = dmamap->dm_nsegs; 3868 3869 /* Advance the tx pointer. */ 3870 sc->sc_txfree -= dmamap->dm_nsegs; 3871 sc->sc_txnext = nexttx; 3872 3873 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3874 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3875 } 3876 3877 if (sc->sc_txfree != ofree) { 3878 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3879 device_xname(sc->sc_dev), lasttx, firsttx)); 3880 /* 3881 * Cause a transmit interrupt to happen on the 3882 * last packet we enqueued. 3883 */ 3884 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3885 ATW_CDTXSYNC(sc, lasttx, 1, 3886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3887 3888 /* 3889 * The entire packet chain is set up. Give the 3890 * first descriptor to the chip now. 3891 */ 3892 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3893 ATW_CDTXSYNC(sc, firsttx, 1, 3894 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3895 3896 /* Wake up the transmitter. */ 3897 ATW_WRITE(sc, ATW_TDR, 0x1); 3898 3899 if (txs == NULL || sc->sc_txfree == 0) 3900 ifp->if_flags |= IFF_OACTIVE; 3901 3902 /* Set a watchdog timer in case the chip flakes out. */ 3903 sc->sc_tx_timer = 5; 3904 ifp->if_timer = 1; 3905 } 3906 } 3907 3908 /* 3909 * atw_ioctl: [ifnet interface function] 3910 * 3911 * Handle control requests from the operator. 3912 */ 3913 int 3914 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3915 { 3916 struct atw_softc *sc = ifp->if_softc; 3917 struct ieee80211req *ireq; 3918 int s, error = 0; 3919 3920 s = splnet(); 3921 3922 switch (cmd) { 3923 case SIOCSIFFLAGS: 3924 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3925 break; 3926 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3927 case IFF_UP | IFF_RUNNING: 3928 /* 3929 * To avoid rescanning another access point, 3930 * do not call atw_init() here. Instead, 3931 * only reflect media settings. 3932 */ 3933 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3934 atw_filter_setup(sc); 3935 break; 3936 case IFF_UP: 3937 error = atw_init(ifp); 3938 break; 3939 case IFF_RUNNING: 3940 atw_stop(ifp, 1); 3941 break; 3942 case 0: 3943 break; 3944 } 3945 break; 3946 case SIOCADDMULTI: 3947 case SIOCDELMULTI: 3948 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3949 if (ifp->if_flags & IFF_RUNNING) 3950 atw_filter_setup(sc); /* do not rescan */ 3951 error = 0; 3952 } 3953 break; 3954 case SIOCS80211: 3955 ireq = data; 3956 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3957 if ((error = kauth_authorize_network(curlwp->l_cred, 3958 KAUTH_NETWORK_INTERFACE, 3959 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3960 (void *)cmd, NULL)) != 0) 3961 break; 3962 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3963 ireq->i_val <= IEEE80211_FRAG_MAX)) 3964 error = EINVAL; 3965 else 3966 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3967 break; 3968 } 3969 /*FALLTHROUGH*/ 3970 default: 3971 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3972 if (error == ENETRESET || error == ERESTART) { 3973 if (is_running(ifp)) 3974 error = atw_init(ifp); 3975 else 3976 error = 0; 3977 } 3978 break; 3979 } 3980 3981 /* Try to get more packets going. */ 3982 if (device_is_active(sc->sc_dev)) 3983 atw_start(ifp); 3984 3985 splx(s); 3986 return (error); 3987 } 3988 3989 static int 3990 atw_media_change(struct ifnet *ifp) 3991 { 3992 int error; 3993 3994 error = ieee80211_media_change(ifp); 3995 if (error == ENETRESET) { 3996 if (is_running(ifp)) 3997 error = atw_init(ifp); 3998 else 3999 error = 0; 4000 } 4001 return error; 4002 } 4003
Indexes created Thu Sep 25 16:09:42 GMT 2025